1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <rdma/ib_mad.h> 34 #include <rdma/ib_smi.h> 35 #include <rdma/ib_sa.h> 36 #include <rdma/ib_cache.h> 37 38 #include <linux/random.h> 39 #include <linux/mlx4/cmd.h> 40 #include <linux/gfp.h> 41 #include <rdma/ib_pma.h> 42 #include <linux/ip.h> 43 #include <net/ipv6.h> 44 45 #include <linux/mlx4/driver.h> 46 #include "mlx4_ib.h" 47 48 enum { 49 MLX4_IB_VENDOR_CLASS1 = 0x9, 50 MLX4_IB_VENDOR_CLASS2 = 0xa 51 }; 52 53 #define MLX4_TUN_SEND_WRID_SHIFT 34 54 #define MLX4_TUN_QPN_SHIFT 32 55 #define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT) 56 #define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT) 57 58 #define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1) 59 #define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3) 60 61 /* Port mgmt change event handling */ 62 63 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr) 64 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask) 65 #define NUM_IDX_IN_PKEY_TBL_BLK 32 66 #define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */ 67 #define GUID_TBL_BLK_NUM_ENTRIES 8 68 #define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES) 69 70 struct mlx4_mad_rcv_buf { 71 struct ib_grh grh; 72 u8 payload[256]; 73 } __packed; 74 75 struct mlx4_mad_snd_buf { 76 u8 payload[256]; 77 } __packed; 78 79 struct mlx4_tunnel_mad { 80 struct ib_grh grh; 81 struct mlx4_ib_tunnel_header hdr; 82 struct ib_mad mad; 83 } __packed; 84 85 struct mlx4_rcv_tunnel_mad { 86 struct mlx4_rcv_tunnel_hdr hdr; 87 struct ib_grh grh; 88 struct ib_mad mad; 89 } __packed; 90 91 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num); 92 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num); 93 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 94 int block, u32 change_bitmap); 95 96 __be64 mlx4_ib_gen_node_guid(void) 97 { 98 #define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40)) 99 return cpu_to_be64(NODE_GUID_HI | prandom_u32()); 100 } 101 102 __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx) 103 { 104 return cpu_to_be64(atomic_inc_return(&ctx->tid)) | 105 cpu_to_be64(0xff00000000000000LL); 106 } 107 108 int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, 109 int port, const struct ib_wc *in_wc, 110 const struct ib_grh *in_grh, 111 const void *in_mad, void *response_mad) 112 { 113 struct mlx4_cmd_mailbox *inmailbox, *outmailbox; 114 void *inbox; 115 int err; 116 u32 in_modifier = port; 117 u8 op_modifier = 0; 118 119 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 120 if (IS_ERR(inmailbox)) 121 return PTR_ERR(inmailbox); 122 inbox = inmailbox->buf; 123 124 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 125 if (IS_ERR(outmailbox)) { 126 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 127 return PTR_ERR(outmailbox); 128 } 129 130 memcpy(inbox, in_mad, 256); 131 132 /* 133 * Key check traps can't be generated unless we have in_wc to 134 * tell us where to send the trap. 135 */ 136 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc) 137 op_modifier |= 0x1; 138 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc) 139 op_modifier |= 0x2; 140 if (mlx4_is_mfunc(dev->dev) && 141 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc)) 142 op_modifier |= 0x8; 143 144 if (in_wc) { 145 struct { 146 __be32 my_qpn; 147 u32 reserved1; 148 __be32 rqpn; 149 u8 sl; 150 u8 g_path; 151 u16 reserved2[2]; 152 __be16 pkey; 153 u32 reserved3[11]; 154 u8 grh[40]; 155 } *ext_info; 156 157 memset(inbox + 256, 0, 256); 158 ext_info = inbox + 256; 159 160 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num); 161 ext_info->rqpn = cpu_to_be32(in_wc->src_qp); 162 ext_info->sl = in_wc->sl << 4; 163 ext_info->g_path = in_wc->dlid_path_bits | 164 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 165 ext_info->pkey = cpu_to_be16(in_wc->pkey_index); 166 167 if (in_grh) 168 memcpy(ext_info->grh, in_grh, 40); 169 170 op_modifier |= 0x4; 171 172 in_modifier |= in_wc->slid << 16; 173 } 174 175 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier, 176 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier, 177 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, 178 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED); 179 180 if (!err) 181 memcpy(response_mad, outmailbox->buf, 256); 182 183 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 184 mlx4_free_cmd_mailbox(dev->dev, outmailbox); 185 186 return err; 187 } 188 189 static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl) 190 { 191 struct ib_ah *new_ah; 192 struct ib_ah_attr ah_attr; 193 unsigned long flags; 194 195 if (!dev->send_agent[port_num - 1][0]) 196 return; 197 198 memset(&ah_attr, 0, sizeof ah_attr); 199 ah_attr.dlid = lid; 200 ah_attr.sl = sl; 201 ah_attr.port_num = port_num; 202 203 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd, 204 &ah_attr); 205 if (IS_ERR(new_ah)) 206 return; 207 208 spin_lock_irqsave(&dev->sm_lock, flags); 209 if (dev->sm_ah[port_num - 1]) 210 ib_destroy_ah(dev->sm_ah[port_num - 1]); 211 dev->sm_ah[port_num - 1] = new_ah; 212 spin_unlock_irqrestore(&dev->sm_lock, flags); 213 } 214 215 /* 216 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can 217 * synthesize LID change, Client-Rereg, GID change, and P_Key change events. 218 */ 219 static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad, 220 u16 prev_lid) 221 { 222 struct ib_port_info *pinfo; 223 u16 lid; 224 __be16 *base; 225 u32 bn, pkey_change_bitmap; 226 int i; 227 228 229 struct mlx4_ib_dev *dev = to_mdev(ibdev); 230 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 231 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 232 mad->mad_hdr.method == IB_MGMT_METHOD_SET) 233 switch (mad->mad_hdr.attr_id) { 234 case IB_SMP_ATTR_PORT_INFO: 235 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 236 return; 237 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data; 238 lid = be16_to_cpu(pinfo->lid); 239 240 update_sm_ah(dev, port_num, 241 be16_to_cpu(pinfo->sm_lid), 242 pinfo->neighbormtu_mastersmsl & 0xf); 243 244 if (pinfo->clientrereg_resv_subnetto & 0x80) 245 handle_client_rereg_event(dev, port_num); 246 247 if (prev_lid != lid) 248 handle_lid_change_event(dev, port_num); 249 break; 250 251 case IB_SMP_ATTR_PKEY_TABLE: 252 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 253 return; 254 if (!mlx4_is_mfunc(dev->dev)) { 255 mlx4_ib_dispatch_event(dev, port_num, 256 IB_EVENT_PKEY_CHANGE); 257 break; 258 } 259 260 /* at this point, we are running in the master. 261 * Slaves do not receive SMPs. 262 */ 263 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF; 264 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]); 265 pkey_change_bitmap = 0; 266 for (i = 0; i < 32; i++) { 267 pr_debug("PKEY[%d] = x%x\n", 268 i + bn*32, be16_to_cpu(base[i])); 269 if (be16_to_cpu(base[i]) != 270 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) { 271 pkey_change_bitmap |= (1 << i); 272 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] = 273 be16_to_cpu(base[i]); 274 } 275 } 276 pr_debug("PKEY Change event: port=%d, " 277 "block=0x%x, change_bitmap=0x%x\n", 278 port_num, bn, pkey_change_bitmap); 279 280 if (pkey_change_bitmap) { 281 mlx4_ib_dispatch_event(dev, port_num, 282 IB_EVENT_PKEY_CHANGE); 283 if (!dev->sriov.is_going_down) 284 __propagate_pkey_ev(dev, port_num, bn, 285 pkey_change_bitmap); 286 } 287 break; 288 289 case IB_SMP_ATTR_GUID_INFO: 290 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 291 return; 292 /* paravirtualized master's guid is guid 0 -- does not change */ 293 if (!mlx4_is_master(dev->dev)) 294 mlx4_ib_dispatch_event(dev, port_num, 295 IB_EVENT_GID_CHANGE); 296 /*if master, notify relevant slaves*/ 297 if (mlx4_is_master(dev->dev) && 298 !dev->sriov.is_going_down) { 299 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod); 300 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num, 301 (u8 *)(&((struct ib_smp *)mad)->data)); 302 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num, 303 (u8 *)(&((struct ib_smp *)mad)->data)); 304 } 305 break; 306 307 case IB_SMP_ATTR_SL_TO_VL_TABLE: 308 /* cache sl to vl mapping changes for use in 309 * filling QP1 LRH VL field when sending packets 310 */ 311 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV && 312 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT) 313 return; 314 if (!mlx4_is_slave(dev->dev)) { 315 union sl2vl_tbl_to_u64 sl2vl64; 316 int jj; 317 318 for (jj = 0; jj < 8; jj++) { 319 sl2vl64.sl8[jj] = ((struct ib_smp *)mad)->data[jj]; 320 pr_debug("port %u, sl2vl[%d] = %02x\n", 321 port_num, jj, sl2vl64.sl8[jj]); 322 } 323 atomic64_set(&dev->sl2vl[port_num - 1], sl2vl64.sl64); 324 } 325 break; 326 327 default: 328 break; 329 } 330 } 331 332 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 333 int block, u32 change_bitmap) 334 { 335 int i, ix, slave, err; 336 int have_event = 0; 337 338 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) { 339 if (slave == mlx4_master_func_num(dev->dev)) 340 continue; 341 if (!mlx4_is_slave_active(dev->dev, slave)) 342 continue; 343 344 have_event = 0; 345 for (i = 0; i < 32; i++) { 346 if (!(change_bitmap & (1 << i))) 347 continue; 348 for (ix = 0; 349 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) { 350 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1] 351 [ix] == i + 32 * block) { 352 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num); 353 pr_debug("propagate_pkey_ev: slave %d," 354 " port %d, ix %d (%d)\n", 355 slave, port_num, ix, err); 356 have_event = 1; 357 break; 358 } 359 } 360 if (have_event) 361 break; 362 } 363 } 364 } 365 366 static void node_desc_override(struct ib_device *dev, 367 struct ib_mad *mad) 368 { 369 unsigned long flags; 370 371 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 372 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 373 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP && 374 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) { 375 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags); 376 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 377 IB_DEVICE_NODE_DESC_MAX); 378 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags); 379 } 380 } 381 382 static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad) 383 { 384 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED; 385 struct ib_mad_send_buf *send_buf; 386 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn]; 387 int ret; 388 unsigned long flags; 389 390 if (agent) { 391 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 392 IB_MGMT_MAD_DATA, GFP_ATOMIC, 393 IB_MGMT_BASE_VERSION); 394 if (IS_ERR(send_buf)) 395 return; 396 /* 397 * We rely here on the fact that MLX QPs don't use the 398 * address handle after the send is posted (this is 399 * wrong following the IB spec strictly, but we know 400 * it's OK for our devices). 401 */ 402 spin_lock_irqsave(&dev->sm_lock, flags); 403 memcpy(send_buf->mad, mad, sizeof *mad); 404 if ((send_buf->ah = dev->sm_ah[port_num - 1])) 405 ret = ib_post_send_mad(send_buf, NULL); 406 else 407 ret = -EINVAL; 408 spin_unlock_irqrestore(&dev->sm_lock, flags); 409 410 if (ret) 411 ib_free_send_mad(send_buf); 412 } 413 } 414 415 static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave, 416 struct ib_sa_mad *sa_mad) 417 { 418 int ret = 0; 419 420 /* dispatch to different sa handlers */ 421 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 422 case IB_SA_ATTR_MC_MEMBER_REC: 423 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad); 424 break; 425 default: 426 break; 427 } 428 return ret; 429 } 430 431 int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid) 432 { 433 struct mlx4_ib_dev *dev = to_mdev(ibdev); 434 int i; 435 436 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 437 if (dev->sriov.demux[port - 1].guid_cache[i] == guid) 438 return i; 439 } 440 return -1; 441 } 442 443 444 static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave, 445 u8 port, u16 pkey, u16 *ix) 446 { 447 int i, ret; 448 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF; 449 u16 slot_pkey; 450 451 if (slave == mlx4_master_func_num(dev->dev)) 452 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix); 453 454 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1; 455 456 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) { 457 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix) 458 continue; 459 460 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i]; 461 462 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey); 463 if (ret) 464 continue; 465 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) { 466 if (slot_pkey & 0x8000) { 467 *ix = (u16) pkey_ix; 468 return 0; 469 } else { 470 /* take first partial pkey index found */ 471 if (partial_ix == 0xFF) 472 partial_ix = pkey_ix; 473 } 474 } 475 } 476 477 if (partial_ix < 0xFF) { 478 *ix = (u16) partial_ix; 479 return 0; 480 } 481 482 return -EINVAL; 483 } 484 485 static int get_gids_from_l3_hdr(struct ib_grh *grh, union ib_gid *sgid, 486 union ib_gid *dgid) 487 { 488 int version = ib_get_rdma_header_version((const union rdma_network_hdr *)grh); 489 enum rdma_network_type net_type; 490 491 if (version == 4) 492 net_type = RDMA_NETWORK_IPV4; 493 else if (version == 6) 494 net_type = RDMA_NETWORK_IPV6; 495 else 496 return -EINVAL; 497 498 return ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type, 499 sgid, dgid); 500 } 501 502 int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, 503 enum ib_qp_type dest_qpt, struct ib_wc *wc, 504 struct ib_grh *grh, struct ib_mad *mad) 505 { 506 struct ib_sge list; 507 struct ib_ud_wr wr; 508 struct ib_send_wr *bad_wr; 509 struct mlx4_ib_demux_pv_ctx *tun_ctx; 510 struct mlx4_ib_demux_pv_qp *tun_qp; 511 struct mlx4_rcv_tunnel_mad *tun_mad; 512 struct ib_ah_attr attr; 513 struct ib_ah *ah; 514 struct ib_qp *src_qp = NULL; 515 unsigned tun_tx_ix = 0; 516 int dqpn; 517 int ret = 0; 518 u16 tun_pkey_ix; 519 u16 cached_pkey; 520 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 521 522 if (dest_qpt > IB_QPT_GSI) 523 return -EINVAL; 524 525 tun_ctx = dev->sriov.demux[port-1].tun[slave]; 526 527 /* check if proxy qp created */ 528 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE) 529 return -EAGAIN; 530 531 if (!dest_qpt) 532 tun_qp = &tun_ctx->qp[0]; 533 else 534 tun_qp = &tun_ctx->qp[1]; 535 536 /* compute P_Key index to put in tunnel header for slave */ 537 if (dest_qpt) { 538 u16 pkey_ix; 539 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey); 540 if (ret) 541 return -EINVAL; 542 543 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix); 544 if (ret) 545 return -EINVAL; 546 tun_pkey_ix = pkey_ix; 547 } else 548 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 549 550 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1; 551 552 /* get tunnel tx data buf for slave */ 553 src_qp = tun_qp->qp; 554 555 /* create ah. Just need an empty one with the port num for the post send. 556 * The driver will set the force loopback bit in post_send */ 557 memset(&attr, 0, sizeof attr); 558 attr.port_num = port; 559 if (is_eth) { 560 union ib_gid sgid; 561 562 if (get_gids_from_l3_hdr(grh, &sgid, &attr.grh.dgid)) 563 return -EINVAL; 564 attr.ah_flags = IB_AH_GRH; 565 } 566 ah = ib_create_ah(tun_ctx->pd, &attr); 567 if (IS_ERR(ah)) 568 return -ENOMEM; 569 570 /* allocate tunnel tx buf after pass failure returns */ 571 spin_lock(&tun_qp->tx_lock); 572 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >= 573 (MLX4_NUM_TUNNEL_BUFS - 1)) 574 ret = -EAGAIN; 575 else 576 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 577 spin_unlock(&tun_qp->tx_lock); 578 if (ret) 579 goto end; 580 581 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr); 582 if (tun_qp->tx_ring[tun_tx_ix].ah) 583 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah); 584 tun_qp->tx_ring[tun_tx_ix].ah = ah; 585 ib_dma_sync_single_for_cpu(&dev->ib_dev, 586 tun_qp->tx_ring[tun_tx_ix].buf.map, 587 sizeof (struct mlx4_rcv_tunnel_mad), 588 DMA_TO_DEVICE); 589 590 /* copy over to tunnel buffer */ 591 if (grh) 592 memcpy(&tun_mad->grh, grh, sizeof *grh); 593 memcpy(&tun_mad->mad, mad, sizeof *mad); 594 595 /* adjust tunnel data */ 596 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix); 597 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF); 598 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0; 599 600 if (is_eth) { 601 u16 vlan = 0; 602 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan, 603 NULL)) { 604 /* VST mode */ 605 if (vlan != wc->vlan_id) 606 /* Packet vlan is not the VST-assigned vlan. 607 * Drop the packet. 608 */ 609 goto out; 610 else 611 /* Remove the vlan tag before forwarding 612 * the packet to the VF. 613 */ 614 vlan = 0xffff; 615 } else { 616 vlan = wc->vlan_id; 617 } 618 619 tun_mad->hdr.sl_vid = cpu_to_be16(vlan); 620 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4); 621 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2); 622 } else { 623 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12); 624 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid); 625 } 626 627 ib_dma_sync_single_for_device(&dev->ib_dev, 628 tun_qp->tx_ring[tun_tx_ix].buf.map, 629 sizeof (struct mlx4_rcv_tunnel_mad), 630 DMA_TO_DEVICE); 631 632 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map; 633 list.length = sizeof (struct mlx4_rcv_tunnel_mad); 634 list.lkey = tun_ctx->pd->local_dma_lkey; 635 636 wr.ah = ah; 637 wr.port_num = port; 638 wr.remote_qkey = IB_QP_SET_QKEY; 639 wr.remote_qpn = dqpn; 640 wr.wr.next = NULL; 641 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt); 642 wr.wr.sg_list = &list; 643 wr.wr.num_sge = 1; 644 wr.wr.opcode = IB_WR_SEND; 645 wr.wr.send_flags = IB_SEND_SIGNALED; 646 647 ret = ib_post_send(src_qp, &wr.wr, &bad_wr); 648 if (!ret) 649 return 0; 650 out: 651 spin_lock(&tun_qp->tx_lock); 652 tun_qp->tx_ix_tail++; 653 spin_unlock(&tun_qp->tx_lock); 654 tun_qp->tx_ring[tun_tx_ix].ah = NULL; 655 end: 656 ib_destroy_ah(ah); 657 return ret; 658 } 659 660 static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, 661 struct ib_wc *wc, struct ib_grh *grh, 662 struct ib_mad *mad) 663 { 664 struct mlx4_ib_dev *dev = to_mdev(ibdev); 665 int err, other_port; 666 int slave = -1; 667 u8 *slave_id; 668 int is_eth = 0; 669 670 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND) 671 is_eth = 0; 672 else 673 is_eth = 1; 674 675 if (is_eth) { 676 union ib_gid dgid; 677 union ib_gid sgid; 678 679 if (get_gids_from_l3_hdr(grh, &sgid, &dgid)) 680 return -EINVAL; 681 if (!(wc->wc_flags & IB_WC_GRH)) { 682 mlx4_ib_warn(ibdev, "RoCE grh not present.\n"); 683 return -EINVAL; 684 } 685 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) { 686 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); 687 return -EINVAL; 688 } 689 err = mlx4_get_slave_from_roce_gid(dev->dev, port, dgid.raw, &slave); 690 if (err && mlx4_is_mf_bonded(dev->dev)) { 691 other_port = (port == 1) ? 2 : 1; 692 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, dgid.raw, &slave); 693 if (!err) { 694 port = other_port; 695 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n", 696 slave, grh->dgid.raw, port, other_port); 697 } 698 } 699 if (err) { 700 mlx4_ib_warn(ibdev, "failed matching grh\n"); 701 return -ENOENT; 702 } 703 if (slave >= dev->dev->caps.sqp_demux) { 704 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 705 slave, dev->dev->caps.sqp_demux); 706 return -ENOENT; 707 } 708 709 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad)) 710 return 0; 711 712 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 713 if (err) 714 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 715 slave, err); 716 return 0; 717 } 718 719 /* Initially assume that this mad is for us */ 720 slave = mlx4_master_func_num(dev->dev); 721 722 /* See if the slave id is encoded in a response mad */ 723 if (mad->mad_hdr.method & 0x80) { 724 slave_id = (u8 *) &mad->mad_hdr.tid; 725 slave = *slave_id; 726 if (slave != 255) /*255 indicates the dom0*/ 727 *slave_id = 0; /* remap tid */ 728 } 729 730 /* If a grh is present, we demux according to it */ 731 if (wc->wc_flags & IB_WC_GRH) { 732 if (grh->dgid.global.interface_id == 733 cpu_to_be64(IB_SA_WELL_KNOWN_GUID) && 734 grh->dgid.global.subnet_prefix == cpu_to_be64( 735 atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix))) { 736 slave = 0; 737 } else { 738 slave = mlx4_ib_find_real_gid(ibdev, port, 739 grh->dgid.global.interface_id); 740 if (slave < 0) { 741 mlx4_ib_warn(ibdev, "failed matching grh\n"); 742 return -ENOENT; 743 } 744 } 745 } 746 /* Class-specific handling */ 747 switch (mad->mad_hdr.mgmt_class) { 748 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 749 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 750 /* 255 indicates the dom0 */ 751 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) { 752 if (!mlx4_vf_smi_enabled(dev->dev, slave, port)) 753 return -EPERM; 754 /* for a VF. drop unsolicited MADs */ 755 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) { 756 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n", 757 slave, mad->mad_hdr.mgmt_class, 758 mad->mad_hdr.method); 759 return -EINVAL; 760 } 761 } 762 break; 763 case IB_MGMT_CLASS_SUBN_ADM: 764 if (mlx4_ib_demux_sa_handler(ibdev, port, slave, 765 (struct ib_sa_mad *) mad)) 766 return 0; 767 break; 768 case IB_MGMT_CLASS_CM: 769 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad)) 770 return 0; 771 break; 772 case IB_MGMT_CLASS_DEVICE_MGMT: 773 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP) 774 return 0; 775 break; 776 default: 777 /* Drop unsupported classes for slaves in tunnel mode */ 778 if (slave != mlx4_master_func_num(dev->dev)) { 779 pr_debug("dropping unsupported ingress mad from class:%d " 780 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave); 781 return 0; 782 } 783 } 784 /*make sure that no slave==255 was not handled yet.*/ 785 if (slave >= dev->dev->caps.sqp_demux) { 786 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 787 slave, dev->dev->caps.sqp_demux); 788 return -ENOENT; 789 } 790 791 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 792 if (err) 793 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 794 slave, err); 795 return 0; 796 } 797 798 static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 799 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 800 const struct ib_mad *in_mad, struct ib_mad *out_mad) 801 { 802 u16 slid, prev_lid = 0; 803 int err; 804 struct ib_port_attr pattr; 805 806 if (in_wc && in_wc->qp->qp_num) { 807 pr_debug("received MAD: slid:%d sqpn:%d " 808 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n", 809 in_wc->slid, in_wc->src_qp, 810 in_wc->dlid_path_bits, 811 in_wc->qp->qp_num, 812 in_wc->wc_flags, 813 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method, 814 be16_to_cpu(in_mad->mad_hdr.attr_id)); 815 if (in_wc->wc_flags & IB_WC_GRH) { 816 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n", 817 be64_to_cpu(in_grh->sgid.global.subnet_prefix), 818 be64_to_cpu(in_grh->sgid.global.interface_id)); 819 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n", 820 be64_to_cpu(in_grh->dgid.global.subnet_prefix), 821 be64_to_cpu(in_grh->dgid.global.interface_id)); 822 } 823 } 824 825 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE); 826 827 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) { 828 forward_trap(to_mdev(ibdev), port_num, in_mad); 829 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 830 } 831 832 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 833 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) { 834 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 835 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET && 836 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS) 837 return IB_MAD_RESULT_SUCCESS; 838 839 /* 840 * Don't process SMInfo queries -- the SMA can't handle them. 841 */ 842 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO) 843 return IB_MAD_RESULT_SUCCESS; 844 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT || 845 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 || 846 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 || 847 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) { 848 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 849 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET) 850 return IB_MAD_RESULT_SUCCESS; 851 } else 852 return IB_MAD_RESULT_SUCCESS; 853 854 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 855 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 856 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET && 857 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO && 858 !ib_query_port(ibdev, port_num, &pattr)) 859 prev_lid = pattr.lid; 860 861 err = mlx4_MAD_IFC(to_mdev(ibdev), 862 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) | 863 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) | 864 MLX4_MAD_IFC_NET_VIEW, 865 port_num, in_wc, in_grh, in_mad, out_mad); 866 if (err) 867 return IB_MAD_RESULT_FAILURE; 868 869 if (!out_mad->mad_hdr.status) { 870 smp_snoop(ibdev, port_num, in_mad, prev_lid); 871 /* slaves get node desc from FW */ 872 if (!mlx4_is_slave(to_mdev(ibdev)->dev)) 873 node_desc_override(ibdev, out_mad); 874 } 875 876 /* set return bit in status of directed route responses */ 877 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) 878 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15); 879 880 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) 881 /* no response for trap repress */ 882 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 883 884 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 885 } 886 887 static void edit_counter(struct mlx4_counter *cnt, void *counters, 888 __be16 attr_id) 889 { 890 switch (attr_id) { 891 case IB_PMA_PORT_COUNTERS: 892 { 893 struct ib_pma_portcounters *pma_cnt = 894 (struct ib_pma_portcounters *)counters; 895 896 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data, 897 (be64_to_cpu(cnt->tx_bytes) >> 2)); 898 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data, 899 (be64_to_cpu(cnt->rx_bytes) >> 2)); 900 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets, 901 be64_to_cpu(cnt->tx_frames)); 902 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets, 903 be64_to_cpu(cnt->rx_frames)); 904 break; 905 } 906 case IB_PMA_PORT_COUNTERS_EXT: 907 { 908 struct ib_pma_portcounters_ext *pma_cnt_ext = 909 (struct ib_pma_portcounters_ext *)counters; 910 911 pma_cnt_ext->port_xmit_data = 912 cpu_to_be64(be64_to_cpu(cnt->tx_bytes) >> 2); 913 pma_cnt_ext->port_rcv_data = 914 cpu_to_be64(be64_to_cpu(cnt->rx_bytes) >> 2); 915 pma_cnt_ext->port_xmit_packets = cnt->tx_frames; 916 pma_cnt_ext->port_rcv_packets = cnt->rx_frames; 917 break; 918 } 919 } 920 } 921 922 static int iboe_process_mad_port_info(void *out_mad) 923 { 924 struct ib_class_port_info cpi = {}; 925 926 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH; 927 memcpy(out_mad, &cpi, sizeof(cpi)); 928 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 929 } 930 931 static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 932 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 933 const struct ib_mad *in_mad, struct ib_mad *out_mad) 934 { 935 struct mlx4_counter counter_stats; 936 struct mlx4_ib_dev *dev = to_mdev(ibdev); 937 struct counter_index *tmp_counter; 938 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0; 939 940 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 941 return -EINVAL; 942 943 if (in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO) 944 return iboe_process_mad_port_info((void *)(out_mad->data + 40)); 945 946 memset(&counter_stats, 0, sizeof(counter_stats)); 947 mutex_lock(&dev->counters_table[port_num - 1].mutex); 948 list_for_each_entry(tmp_counter, 949 &dev->counters_table[port_num - 1].counters_list, 950 list) { 951 err = mlx4_get_counter_stats(dev->dev, 952 tmp_counter->index, 953 &counter_stats, 0); 954 if (err) { 955 err = IB_MAD_RESULT_FAILURE; 956 stats_avail = 0; 957 break; 958 } 959 stats_avail = 1; 960 } 961 mutex_unlock(&dev->counters_table[port_num - 1].mutex); 962 if (stats_avail) { 963 memset(out_mad->data, 0, sizeof out_mad->data); 964 switch (counter_stats.counter_mode & 0xf) { 965 case 0: 966 edit_counter(&counter_stats, 967 (void *)(out_mad->data + 40), 968 in_mad->mad_hdr.attr_id); 969 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 970 break; 971 default: 972 err = IB_MAD_RESULT_FAILURE; 973 } 974 } 975 976 return err; 977 } 978 979 int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 980 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 981 const struct ib_mad_hdr *in, size_t in_mad_size, 982 struct ib_mad_hdr *out, size_t *out_mad_size, 983 u16 *out_mad_pkey_index) 984 { 985 struct mlx4_ib_dev *dev = to_mdev(ibdev); 986 const struct ib_mad *in_mad = (const struct ib_mad *)in; 987 struct ib_mad *out_mad = (struct ib_mad *)out; 988 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num); 989 990 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) || 991 *out_mad_size != sizeof(*out_mad))) 992 return IB_MAD_RESULT_FAILURE; 993 994 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA 995 * queries, should be called only by VFs and for that specific purpose 996 */ 997 if (link == IB_LINK_LAYER_INFINIBAND) { 998 if (mlx4_is_slave(dev->dev) && 999 (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT && 1000 (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS || 1001 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT || 1002 in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO))) 1003 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 1004 in_grh, in_mad, out_mad); 1005 1006 return ib_process_mad(ibdev, mad_flags, port_num, in_wc, 1007 in_grh, in_mad, out_mad); 1008 } 1009 1010 if (link == IB_LINK_LAYER_ETHERNET) 1011 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 1012 in_grh, in_mad, out_mad); 1013 1014 return -EINVAL; 1015 } 1016 1017 static void send_handler(struct ib_mad_agent *agent, 1018 struct ib_mad_send_wc *mad_send_wc) 1019 { 1020 if (mad_send_wc->send_buf->context[0]) 1021 ib_destroy_ah(mad_send_wc->send_buf->context[0]); 1022 ib_free_send_mad(mad_send_wc->send_buf); 1023 } 1024 1025 int mlx4_ib_mad_init(struct mlx4_ib_dev *dev) 1026 { 1027 struct ib_mad_agent *agent; 1028 int p, q; 1029 int ret; 1030 enum rdma_link_layer ll; 1031 1032 for (p = 0; p < dev->num_ports; ++p) { 1033 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1); 1034 for (q = 0; q <= 1; ++q) { 1035 if (ll == IB_LINK_LAYER_INFINIBAND) { 1036 agent = ib_register_mad_agent(&dev->ib_dev, p + 1, 1037 q ? IB_QPT_GSI : IB_QPT_SMI, 1038 NULL, 0, send_handler, 1039 NULL, NULL, 0); 1040 if (IS_ERR(agent)) { 1041 ret = PTR_ERR(agent); 1042 goto err; 1043 } 1044 dev->send_agent[p][q] = agent; 1045 } else 1046 dev->send_agent[p][q] = NULL; 1047 } 1048 } 1049 1050 return 0; 1051 1052 err: 1053 for (p = 0; p < dev->num_ports; ++p) 1054 for (q = 0; q <= 1; ++q) 1055 if (dev->send_agent[p][q]) 1056 ib_unregister_mad_agent(dev->send_agent[p][q]); 1057 1058 return ret; 1059 } 1060 1061 void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev) 1062 { 1063 struct ib_mad_agent *agent; 1064 int p, q; 1065 1066 for (p = 0; p < dev->num_ports; ++p) { 1067 for (q = 0; q <= 1; ++q) { 1068 agent = dev->send_agent[p][q]; 1069 if (agent) { 1070 dev->send_agent[p][q] = NULL; 1071 ib_unregister_mad_agent(agent); 1072 } 1073 } 1074 1075 if (dev->sm_ah[p]) 1076 ib_destroy_ah(dev->sm_ah[p]); 1077 } 1078 } 1079 1080 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num) 1081 { 1082 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE); 1083 1084 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1085 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1086 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK); 1087 } 1088 1089 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num) 1090 { 1091 /* re-configure the alias-guid and mcg's */ 1092 if (mlx4_is_master(dev->dev)) { 1093 mlx4_ib_invalidate_all_guid_record(dev, port_num); 1094 1095 if (!dev->sriov.is_going_down) { 1096 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0); 1097 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 1098 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK); 1099 } 1100 } 1101 1102 /* Update the sl to vl table from inside client rereg 1103 * only if in secure-host mode (snooping is not possible) 1104 * and the sl-to-vl change event is not generated by FW. 1105 */ 1106 if (!mlx4_is_slave(dev->dev) && 1107 dev->dev->flags & MLX4_FLAG_SECURE_HOST && 1108 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) { 1109 if (mlx4_is_master(dev->dev)) 1110 /* already in work queue from mlx4_ib_event queueing 1111 * mlx4_handle_port_mgmt_change_event, which calls 1112 * this procedure. Therefore, call sl2vl_update directly. 1113 */ 1114 mlx4_ib_sl2vl_update(dev, port_num); 1115 else 1116 mlx4_sched_ib_sl2vl_update_work(dev, port_num); 1117 } 1118 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER); 1119 } 1120 1121 static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 1122 struct mlx4_eqe *eqe) 1123 { 1124 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe), 1125 GET_MASK_FROM_EQE(eqe)); 1126 } 1127 1128 static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num, 1129 u32 guid_tbl_blk_num, u32 change_bitmap) 1130 { 1131 struct ib_smp *in_mad = NULL; 1132 struct ib_smp *out_mad = NULL; 1133 u16 i; 1134 1135 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev)) 1136 return; 1137 1138 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL); 1139 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 1140 if (!in_mad || !out_mad) 1141 goto out; 1142 1143 guid_tbl_blk_num *= 4; 1144 1145 for (i = 0; i < 4; i++) { 1146 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff))) 1147 continue; 1148 memset(in_mad, 0, sizeof *in_mad); 1149 memset(out_mad, 0, sizeof *out_mad); 1150 1151 in_mad->base_version = 1; 1152 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1153 in_mad->class_version = 1; 1154 in_mad->method = IB_MGMT_METHOD_GET; 1155 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 1156 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i); 1157 1158 if (mlx4_MAD_IFC(dev, 1159 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW, 1160 port_num, NULL, NULL, in_mad, out_mad)) { 1161 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n"); 1162 goto out; 1163 } 1164 1165 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i, 1166 port_num, 1167 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1168 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i, 1169 port_num, 1170 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1171 } 1172 1173 out: 1174 kfree(in_mad); 1175 kfree(out_mad); 1176 return; 1177 } 1178 1179 void handle_port_mgmt_change_event(struct work_struct *work) 1180 { 1181 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 1182 struct mlx4_ib_dev *dev = ew->ib_dev; 1183 struct mlx4_eqe *eqe = &(ew->ib_eqe); 1184 u8 port = eqe->event.port_mgmt_change.port; 1185 u32 changed_attr; 1186 u32 tbl_block; 1187 u32 change_bitmap; 1188 1189 switch (eqe->subtype) { 1190 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO: 1191 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr); 1192 1193 /* Update the SM ah - This should be done before handling 1194 the other changed attributes so that MADs can be sent to the SM */ 1195 if (changed_attr & MSTR_SM_CHANGE_MASK) { 1196 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid); 1197 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf; 1198 update_sm_ah(dev, port, lid, sl); 1199 } 1200 1201 /* Check if it is a lid change event */ 1202 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK) 1203 handle_lid_change_event(dev, port); 1204 1205 /* Generate GUID changed event */ 1206 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) { 1207 if (mlx4_is_master(dev->dev)) { 1208 union ib_gid gid; 1209 int err = 0; 1210 1211 if (!eqe->event.port_mgmt_change.params.port_info.gid_prefix) 1212 err = __mlx4_ib_query_gid(&dev->ib_dev, port, 0, &gid, 1); 1213 else 1214 gid.global.subnet_prefix = 1215 eqe->event.port_mgmt_change.params.port_info.gid_prefix; 1216 if (err) { 1217 pr_warn("Could not change QP1 subnet prefix for port %d: query_gid error (%d)\n", 1218 port, err); 1219 } else { 1220 pr_debug("Changing QP1 subnet prefix for port %d. old=0x%llx. new=0x%llx\n", 1221 port, 1222 (u64)atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix), 1223 be64_to_cpu(gid.global.subnet_prefix)); 1224 atomic64_set(&dev->sriov.demux[port - 1].subnet_prefix, 1225 be64_to_cpu(gid.global.subnet_prefix)); 1226 } 1227 } 1228 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1229 /*if master, notify all slaves*/ 1230 if (mlx4_is_master(dev->dev)) 1231 mlx4_gen_slaves_port_mgt_ev(dev->dev, port, 1232 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK); 1233 } 1234 1235 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK) 1236 handle_client_rereg_event(dev, port); 1237 break; 1238 1239 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE: 1240 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE); 1241 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1242 propagate_pkey_ev(dev, port, eqe); 1243 break; 1244 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO: 1245 /* paravirtualized master's guid is guid 0 -- does not change */ 1246 if (!mlx4_is_master(dev->dev)) 1247 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1248 /*if master, notify relevant slaves*/ 1249 else if (!dev->sriov.is_going_down) { 1250 tbl_block = GET_BLK_PTR_FROM_EQE(eqe); 1251 change_bitmap = GET_MASK_FROM_EQE(eqe); 1252 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap); 1253 } 1254 break; 1255 1256 case MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP: 1257 /* cache sl to vl mapping changes for use in 1258 * filling QP1 LRH VL field when sending packets 1259 */ 1260 if (!mlx4_is_slave(dev->dev)) { 1261 union sl2vl_tbl_to_u64 sl2vl64; 1262 int jj; 1263 1264 for (jj = 0; jj < 8; jj++) { 1265 sl2vl64.sl8[jj] = 1266 eqe->event.port_mgmt_change.params.sl2vl_tbl_change_info.sl2vl_table[jj]; 1267 pr_debug("port %u, sl2vl[%d] = %02x\n", 1268 port, jj, sl2vl64.sl8[jj]); 1269 } 1270 atomic64_set(&dev->sl2vl[port - 1], sl2vl64.sl64); 1271 } 1272 break; 1273 default: 1274 pr_warn("Unsupported subtype 0x%x for " 1275 "Port Management Change event\n", eqe->subtype); 1276 } 1277 1278 kfree(ew); 1279 } 1280 1281 void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, 1282 enum ib_event_type type) 1283 { 1284 struct ib_event event; 1285 1286 event.device = &dev->ib_dev; 1287 event.element.port_num = port_num; 1288 event.event = type; 1289 1290 ib_dispatch_event(&event); 1291 } 1292 1293 static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg) 1294 { 1295 unsigned long flags; 1296 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context; 1297 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1298 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 1299 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE) 1300 queue_work(ctx->wq, &ctx->work); 1301 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 1302 } 1303 1304 static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx, 1305 struct mlx4_ib_demux_pv_qp *tun_qp, 1306 int index) 1307 { 1308 struct ib_sge sg_list; 1309 struct ib_recv_wr recv_wr, *bad_recv_wr; 1310 int size; 1311 1312 size = (tun_qp->qp->qp_type == IB_QPT_UD) ? 1313 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf); 1314 1315 sg_list.addr = tun_qp->ring[index].map; 1316 sg_list.length = size; 1317 sg_list.lkey = ctx->pd->local_dma_lkey; 1318 1319 recv_wr.next = NULL; 1320 recv_wr.sg_list = &sg_list; 1321 recv_wr.num_sge = 1; 1322 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV | 1323 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt); 1324 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map, 1325 size, DMA_FROM_DEVICE); 1326 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr); 1327 } 1328 1329 static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port, 1330 int slave, struct ib_sa_mad *sa_mad) 1331 { 1332 int ret = 0; 1333 1334 /* dispatch to different sa handlers */ 1335 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 1336 case IB_SA_ATTR_MC_MEMBER_REC: 1337 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad); 1338 break; 1339 default: 1340 break; 1341 } 1342 return ret; 1343 } 1344 1345 static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave) 1346 { 1347 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave; 1348 1349 return (qpn >= proxy_start && qpn <= proxy_start + 1); 1350 } 1351 1352 1353 int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, 1354 enum ib_qp_type dest_qpt, u16 pkey_index, 1355 u32 remote_qpn, u32 qkey, struct ib_ah_attr *attr, 1356 u8 *s_mac, u16 vlan_id, struct ib_mad *mad) 1357 { 1358 struct ib_sge list; 1359 struct ib_ud_wr wr; 1360 struct ib_send_wr *bad_wr; 1361 struct mlx4_ib_demux_pv_ctx *sqp_ctx; 1362 struct mlx4_ib_demux_pv_qp *sqp; 1363 struct mlx4_mad_snd_buf *sqp_mad; 1364 struct ib_ah *ah; 1365 struct ib_qp *send_qp = NULL; 1366 unsigned wire_tx_ix = 0; 1367 int ret = 0; 1368 u16 wire_pkey_ix; 1369 int src_qpnum; 1370 u8 sgid_index; 1371 1372 1373 sqp_ctx = dev->sriov.sqps[port-1]; 1374 1375 /* check if proxy qp created */ 1376 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE) 1377 return -EAGAIN; 1378 1379 if (dest_qpt == IB_QPT_SMI) { 1380 src_qpnum = 0; 1381 sqp = &sqp_ctx->qp[0]; 1382 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 1383 } else { 1384 src_qpnum = 1; 1385 sqp = &sqp_ctx->qp[1]; 1386 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index]; 1387 } 1388 1389 send_qp = sqp->qp; 1390 1391 /* create ah */ 1392 sgid_index = attr->grh.sgid_index; 1393 attr->grh.sgid_index = 0; 1394 ah = ib_create_ah(sqp_ctx->pd, attr); 1395 if (IS_ERR(ah)) 1396 return -ENOMEM; 1397 attr->grh.sgid_index = sgid_index; 1398 to_mah(ah)->av.ib.gid_index = sgid_index; 1399 /* get rid of force-loopback bit */ 1400 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF); 1401 spin_lock(&sqp->tx_lock); 1402 if (sqp->tx_ix_head - sqp->tx_ix_tail >= 1403 (MLX4_NUM_TUNNEL_BUFS - 1)) 1404 ret = -EAGAIN; 1405 else 1406 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 1407 spin_unlock(&sqp->tx_lock); 1408 if (ret) 1409 goto out; 1410 1411 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr); 1412 if (sqp->tx_ring[wire_tx_ix].ah) 1413 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah); 1414 sqp->tx_ring[wire_tx_ix].ah = ah; 1415 ib_dma_sync_single_for_cpu(&dev->ib_dev, 1416 sqp->tx_ring[wire_tx_ix].buf.map, 1417 sizeof (struct mlx4_mad_snd_buf), 1418 DMA_TO_DEVICE); 1419 1420 memcpy(&sqp_mad->payload, mad, sizeof *mad); 1421 1422 ib_dma_sync_single_for_device(&dev->ib_dev, 1423 sqp->tx_ring[wire_tx_ix].buf.map, 1424 sizeof (struct mlx4_mad_snd_buf), 1425 DMA_TO_DEVICE); 1426 1427 list.addr = sqp->tx_ring[wire_tx_ix].buf.map; 1428 list.length = sizeof (struct mlx4_mad_snd_buf); 1429 list.lkey = sqp_ctx->pd->local_dma_lkey; 1430 1431 wr.ah = ah; 1432 wr.port_num = port; 1433 wr.pkey_index = wire_pkey_ix; 1434 wr.remote_qkey = qkey; 1435 wr.remote_qpn = remote_qpn; 1436 wr.wr.next = NULL; 1437 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum); 1438 wr.wr.sg_list = &list; 1439 wr.wr.num_sge = 1; 1440 wr.wr.opcode = IB_WR_SEND; 1441 wr.wr.send_flags = IB_SEND_SIGNALED; 1442 if (s_mac) 1443 memcpy(to_mah(ah)->av.eth.s_mac, s_mac, 6); 1444 if (vlan_id < 0x1000) 1445 vlan_id |= (attr->sl & 7) << 13; 1446 to_mah(ah)->av.eth.vlan = cpu_to_be16(vlan_id); 1447 1448 1449 ret = ib_post_send(send_qp, &wr.wr, &bad_wr); 1450 if (!ret) 1451 return 0; 1452 1453 spin_lock(&sqp->tx_lock); 1454 sqp->tx_ix_tail++; 1455 spin_unlock(&sqp->tx_lock); 1456 sqp->tx_ring[wire_tx_ix].ah = NULL; 1457 out: 1458 ib_destroy_ah(ah); 1459 return ret; 1460 } 1461 1462 static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port) 1463 { 1464 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1465 return slave; 1466 return mlx4_get_base_gid_ix(dev->dev, slave, port); 1467 } 1468 1469 static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port, 1470 struct ib_ah_attr *ah_attr) 1471 { 1472 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1473 ah_attr->grh.sgid_index = slave; 1474 else 1475 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port); 1476 } 1477 1478 static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc) 1479 { 1480 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1481 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)]; 1482 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1); 1483 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr; 1484 struct mlx4_ib_ah ah; 1485 struct ib_ah_attr ah_attr; 1486 u8 *slave_id; 1487 int slave; 1488 int port; 1489 u16 vlan_id; 1490 1491 /* Get slave that sent this packet */ 1492 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn || 1493 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX || 1494 (wc->src_qp & 0x1) != ctx->port - 1 || 1495 wc->src_qp & 0x4) { 1496 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp); 1497 return; 1498 } 1499 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8; 1500 if (slave != ctx->slave) { 1501 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: " 1502 "belongs to another slave\n", wc->src_qp); 1503 return; 1504 } 1505 1506 /* Map transaction ID */ 1507 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map, 1508 sizeof (struct mlx4_tunnel_mad), 1509 DMA_FROM_DEVICE); 1510 switch (tunnel->mad.mad_hdr.method) { 1511 case IB_MGMT_METHOD_SET: 1512 case IB_MGMT_METHOD_GET: 1513 case IB_MGMT_METHOD_REPORT: 1514 case IB_SA_METHOD_GET_TABLE: 1515 case IB_SA_METHOD_DELETE: 1516 case IB_SA_METHOD_GET_MULTI: 1517 case IB_SA_METHOD_GET_TRACE_TBL: 1518 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid; 1519 if (*slave_id) { 1520 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d " 1521 "class:%d slave:%d\n", *slave_id, 1522 tunnel->mad.mad_hdr.mgmt_class, slave); 1523 return; 1524 } else 1525 *slave_id = slave; 1526 default: 1527 /* nothing */; 1528 } 1529 1530 /* Class-specific handling */ 1531 switch (tunnel->mad.mad_hdr.mgmt_class) { 1532 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 1533 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 1534 if (slave != mlx4_master_func_num(dev->dev) && 1535 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port)) 1536 return; 1537 break; 1538 case IB_MGMT_CLASS_SUBN_ADM: 1539 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave, 1540 (struct ib_sa_mad *) &tunnel->mad)) 1541 return; 1542 break; 1543 case IB_MGMT_CLASS_CM: 1544 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave, 1545 (struct ib_mad *) &tunnel->mad)) 1546 return; 1547 break; 1548 case IB_MGMT_CLASS_DEVICE_MGMT: 1549 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET && 1550 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET) 1551 return; 1552 break; 1553 default: 1554 /* Drop unsupported classes for slaves in tunnel mode */ 1555 if (slave != mlx4_master_func_num(dev->dev)) { 1556 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d " 1557 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave); 1558 return; 1559 } 1560 } 1561 1562 /* We are using standard ib_core services to send the mad, so generate a 1563 * stadard address handle by decoding the tunnelled mlx4_ah fields */ 1564 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av)); 1565 ah.ibah.device = ctx->ib_dev; 1566 1567 port = be32_to_cpu(ah.av.ib.port_pd) >> 24; 1568 port = mlx4_slave_convert_port(dev->dev, slave, port); 1569 if (port < 0) 1570 return; 1571 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff)); 1572 1573 mlx4_ib_query_ah(&ah.ibah, &ah_attr); 1574 if (ah_attr.ah_flags & IB_AH_GRH) 1575 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr); 1576 1577 memcpy(ah_attr.dmac, tunnel->hdr.mac, 6); 1578 vlan_id = be16_to_cpu(tunnel->hdr.vlan); 1579 /* if slave have default vlan use it */ 1580 mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave, 1581 &vlan_id, &ah_attr.sl); 1582 1583 mlx4_ib_send_to_wire(dev, slave, ctx->port, 1584 is_proxy_qp0(dev, wc->src_qp, slave) ? 1585 IB_QPT_SMI : IB_QPT_GSI, 1586 be16_to_cpu(tunnel->hdr.pkey_index), 1587 be32_to_cpu(tunnel->hdr.remote_qpn), 1588 be32_to_cpu(tunnel->hdr.qkey), 1589 &ah_attr, wc->smac, vlan_id, &tunnel->mad); 1590 } 1591 1592 static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1593 enum ib_qp_type qp_type, int is_tun) 1594 { 1595 int i; 1596 struct mlx4_ib_demux_pv_qp *tun_qp; 1597 int rx_buf_size, tx_buf_size; 1598 1599 if (qp_type > IB_QPT_GSI) 1600 return -EINVAL; 1601 1602 tun_qp = &ctx->qp[qp_type]; 1603 1604 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS, 1605 GFP_KERNEL); 1606 if (!tun_qp->ring) 1607 return -ENOMEM; 1608 1609 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS, 1610 sizeof (struct mlx4_ib_tun_tx_buf), 1611 GFP_KERNEL); 1612 if (!tun_qp->tx_ring) { 1613 kfree(tun_qp->ring); 1614 tun_qp->ring = NULL; 1615 return -ENOMEM; 1616 } 1617 1618 if (is_tun) { 1619 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1620 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1621 } else { 1622 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1623 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1624 } 1625 1626 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1627 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL); 1628 if (!tun_qp->ring[i].addr) 1629 goto err; 1630 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev, 1631 tun_qp->ring[i].addr, 1632 rx_buf_size, 1633 DMA_FROM_DEVICE); 1634 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) { 1635 kfree(tun_qp->ring[i].addr); 1636 goto err; 1637 } 1638 } 1639 1640 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1641 tun_qp->tx_ring[i].buf.addr = 1642 kmalloc(tx_buf_size, GFP_KERNEL); 1643 if (!tun_qp->tx_ring[i].buf.addr) 1644 goto tx_err; 1645 tun_qp->tx_ring[i].buf.map = 1646 ib_dma_map_single(ctx->ib_dev, 1647 tun_qp->tx_ring[i].buf.addr, 1648 tx_buf_size, 1649 DMA_TO_DEVICE); 1650 if (ib_dma_mapping_error(ctx->ib_dev, 1651 tun_qp->tx_ring[i].buf.map)) { 1652 kfree(tun_qp->tx_ring[i].buf.addr); 1653 goto tx_err; 1654 } 1655 tun_qp->tx_ring[i].ah = NULL; 1656 } 1657 spin_lock_init(&tun_qp->tx_lock); 1658 tun_qp->tx_ix_head = 0; 1659 tun_qp->tx_ix_tail = 0; 1660 tun_qp->proxy_qpt = qp_type; 1661 1662 return 0; 1663 1664 tx_err: 1665 while (i > 0) { 1666 --i; 1667 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1668 tx_buf_size, DMA_TO_DEVICE); 1669 kfree(tun_qp->tx_ring[i].buf.addr); 1670 } 1671 kfree(tun_qp->tx_ring); 1672 tun_qp->tx_ring = NULL; 1673 i = MLX4_NUM_TUNNEL_BUFS; 1674 err: 1675 while (i > 0) { 1676 --i; 1677 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1678 rx_buf_size, DMA_FROM_DEVICE); 1679 kfree(tun_qp->ring[i].addr); 1680 } 1681 kfree(tun_qp->ring); 1682 tun_qp->ring = NULL; 1683 return -ENOMEM; 1684 } 1685 1686 static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1687 enum ib_qp_type qp_type, int is_tun) 1688 { 1689 int i; 1690 struct mlx4_ib_demux_pv_qp *tun_qp; 1691 int rx_buf_size, tx_buf_size; 1692 1693 if (qp_type > IB_QPT_GSI) 1694 return; 1695 1696 tun_qp = &ctx->qp[qp_type]; 1697 if (is_tun) { 1698 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1699 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1700 } else { 1701 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1702 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1703 } 1704 1705 1706 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1707 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1708 rx_buf_size, DMA_FROM_DEVICE); 1709 kfree(tun_qp->ring[i].addr); 1710 } 1711 1712 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1713 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1714 tx_buf_size, DMA_TO_DEVICE); 1715 kfree(tun_qp->tx_ring[i].buf.addr); 1716 if (tun_qp->tx_ring[i].ah) 1717 ib_destroy_ah(tun_qp->tx_ring[i].ah); 1718 } 1719 kfree(tun_qp->tx_ring); 1720 kfree(tun_qp->ring); 1721 } 1722 1723 static void mlx4_ib_tunnel_comp_worker(struct work_struct *work) 1724 { 1725 struct mlx4_ib_demux_pv_ctx *ctx; 1726 struct mlx4_ib_demux_pv_qp *tun_qp; 1727 struct ib_wc wc; 1728 int ret; 1729 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1730 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1731 1732 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1733 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1734 if (wc.status == IB_WC_SUCCESS) { 1735 switch (wc.opcode) { 1736 case IB_WC_RECV: 1737 mlx4_ib_multiplex_mad(ctx, &wc); 1738 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, 1739 wc.wr_id & 1740 (MLX4_NUM_TUNNEL_BUFS - 1)); 1741 if (ret) 1742 pr_err("Failed reposting tunnel " 1743 "buf:%lld\n", wc.wr_id); 1744 break; 1745 case IB_WC_SEND: 1746 pr_debug("received tunnel send completion:" 1747 "wrid=0x%llx, status=0x%x\n", 1748 wc.wr_id, wc.status); 1749 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1750 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1751 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1752 = NULL; 1753 spin_lock(&tun_qp->tx_lock); 1754 tun_qp->tx_ix_tail++; 1755 spin_unlock(&tun_qp->tx_lock); 1756 1757 break; 1758 default: 1759 break; 1760 } 1761 } else { 1762 pr_debug("mlx4_ib: completion error in tunnel: %d." 1763 " status = %d, wrid = 0x%llx\n", 1764 ctx->slave, wc.status, wc.wr_id); 1765 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1766 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1767 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1768 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1769 = NULL; 1770 spin_lock(&tun_qp->tx_lock); 1771 tun_qp->tx_ix_tail++; 1772 spin_unlock(&tun_qp->tx_lock); 1773 } 1774 } 1775 } 1776 } 1777 1778 static void pv_qp_event_handler(struct ib_event *event, void *qp_context) 1779 { 1780 struct mlx4_ib_demux_pv_ctx *sqp = qp_context; 1781 1782 /* It's worse than that! He's dead, Jim! */ 1783 pr_err("Fatal error (%d) on a MAD QP on port %d\n", 1784 event->event, sqp->port); 1785 } 1786 1787 static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx, 1788 enum ib_qp_type qp_type, int create_tun) 1789 { 1790 int i, ret; 1791 struct mlx4_ib_demux_pv_qp *tun_qp; 1792 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr; 1793 struct ib_qp_attr attr; 1794 int qp_attr_mask_INIT; 1795 1796 if (qp_type > IB_QPT_GSI) 1797 return -EINVAL; 1798 1799 tun_qp = &ctx->qp[qp_type]; 1800 1801 memset(&qp_init_attr, 0, sizeof qp_init_attr); 1802 qp_init_attr.init_attr.send_cq = ctx->cq; 1803 qp_init_attr.init_attr.recv_cq = ctx->cq; 1804 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 1805 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS; 1806 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS; 1807 qp_init_attr.init_attr.cap.max_send_sge = 1; 1808 qp_init_attr.init_attr.cap.max_recv_sge = 1; 1809 if (create_tun) { 1810 qp_init_attr.init_attr.qp_type = IB_QPT_UD; 1811 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP; 1812 qp_init_attr.port = ctx->port; 1813 qp_init_attr.slave = ctx->slave; 1814 qp_init_attr.proxy_qp_type = qp_type; 1815 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | 1816 IB_QP_QKEY | IB_QP_PORT; 1817 } else { 1818 qp_init_attr.init_attr.qp_type = qp_type; 1819 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP; 1820 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY; 1821 } 1822 qp_init_attr.init_attr.port_num = ctx->port; 1823 qp_init_attr.init_attr.qp_context = ctx; 1824 qp_init_attr.init_attr.event_handler = pv_qp_event_handler; 1825 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr); 1826 if (IS_ERR(tun_qp->qp)) { 1827 ret = PTR_ERR(tun_qp->qp); 1828 tun_qp->qp = NULL; 1829 pr_err("Couldn't create %s QP (%d)\n", 1830 create_tun ? "tunnel" : "special", ret); 1831 return ret; 1832 } 1833 1834 memset(&attr, 0, sizeof attr); 1835 attr.qp_state = IB_QPS_INIT; 1836 ret = 0; 1837 if (create_tun) 1838 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave, 1839 ctx->port, IB_DEFAULT_PKEY_FULL, 1840 &attr.pkey_index); 1841 if (ret || !create_tun) 1842 attr.pkey_index = 1843 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0]; 1844 attr.qkey = IB_QP1_QKEY; 1845 attr.port_num = ctx->port; 1846 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT); 1847 if (ret) { 1848 pr_err("Couldn't change %s qp state to INIT (%d)\n", 1849 create_tun ? "tunnel" : "special", ret); 1850 goto err_qp; 1851 } 1852 attr.qp_state = IB_QPS_RTR; 1853 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE); 1854 if (ret) { 1855 pr_err("Couldn't change %s qp state to RTR (%d)\n", 1856 create_tun ? "tunnel" : "special", ret); 1857 goto err_qp; 1858 } 1859 attr.qp_state = IB_QPS_RTS; 1860 attr.sq_psn = 0; 1861 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN); 1862 if (ret) { 1863 pr_err("Couldn't change %s qp state to RTS (%d)\n", 1864 create_tun ? "tunnel" : "special", ret); 1865 goto err_qp; 1866 } 1867 1868 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1869 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i); 1870 if (ret) { 1871 pr_err(" mlx4_ib_post_pv_buf error" 1872 " (err = %d, i = %d)\n", ret, i); 1873 goto err_qp; 1874 } 1875 } 1876 return 0; 1877 1878 err_qp: 1879 ib_destroy_qp(tun_qp->qp); 1880 tun_qp->qp = NULL; 1881 return ret; 1882 } 1883 1884 /* 1885 * IB MAD completion callback for real SQPs 1886 */ 1887 static void mlx4_ib_sqp_comp_worker(struct work_struct *work) 1888 { 1889 struct mlx4_ib_demux_pv_ctx *ctx; 1890 struct mlx4_ib_demux_pv_qp *sqp; 1891 struct ib_wc wc; 1892 struct ib_grh *grh; 1893 struct ib_mad *mad; 1894 1895 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1896 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1897 1898 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1899 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1900 if (wc.status == IB_WC_SUCCESS) { 1901 switch (wc.opcode) { 1902 case IB_WC_SEND: 1903 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1904 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1905 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1906 = NULL; 1907 spin_lock(&sqp->tx_lock); 1908 sqp->tx_ix_tail++; 1909 spin_unlock(&sqp->tx_lock); 1910 break; 1911 case IB_WC_RECV: 1912 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *) 1913 (sqp->ring[wc.wr_id & 1914 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload); 1915 grh = &(((struct mlx4_mad_rcv_buf *) 1916 (sqp->ring[wc.wr_id & 1917 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh); 1918 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad); 1919 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id & 1920 (MLX4_NUM_TUNNEL_BUFS - 1))) 1921 pr_err("Failed reposting SQP " 1922 "buf:%lld\n", wc.wr_id); 1923 break; 1924 default: 1925 BUG_ON(1); 1926 break; 1927 } 1928 } else { 1929 pr_debug("mlx4_ib: completion error in tunnel: %d." 1930 " status = %d, wrid = 0x%llx\n", 1931 ctx->slave, wc.status, wc.wr_id); 1932 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1933 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1934 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1935 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1936 = NULL; 1937 spin_lock(&sqp->tx_lock); 1938 sqp->tx_ix_tail++; 1939 spin_unlock(&sqp->tx_lock); 1940 } 1941 } 1942 } 1943 } 1944 1945 static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port, 1946 struct mlx4_ib_demux_pv_ctx **ret_ctx) 1947 { 1948 struct mlx4_ib_demux_pv_ctx *ctx; 1949 1950 *ret_ctx = NULL; 1951 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL); 1952 if (!ctx) 1953 return -ENOMEM; 1954 1955 ctx->ib_dev = &dev->ib_dev; 1956 ctx->port = port; 1957 ctx->slave = slave; 1958 *ret_ctx = ctx; 1959 return 0; 1960 } 1961 1962 static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port) 1963 { 1964 if (dev->sriov.demux[port - 1].tun[slave]) { 1965 kfree(dev->sriov.demux[port - 1].tun[slave]); 1966 dev->sriov.demux[port - 1].tun[slave] = NULL; 1967 } 1968 } 1969 1970 static int create_pv_resources(struct ib_device *ibdev, int slave, int port, 1971 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx) 1972 { 1973 int ret, cq_size; 1974 struct ib_cq_init_attr cq_attr = {}; 1975 1976 if (ctx->state != DEMUX_PV_STATE_DOWN) 1977 return -EEXIST; 1978 1979 ctx->state = DEMUX_PV_STATE_STARTING; 1980 /* have QP0 only if link layer is IB */ 1981 if (rdma_port_get_link_layer(ibdev, ctx->port) == 1982 IB_LINK_LAYER_INFINIBAND) 1983 ctx->has_smi = 1; 1984 1985 if (ctx->has_smi) { 1986 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun); 1987 if (ret) { 1988 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret); 1989 goto err_out; 1990 } 1991 } 1992 1993 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun); 1994 if (ret) { 1995 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret); 1996 goto err_out_qp0; 1997 } 1998 1999 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS; 2000 if (ctx->has_smi) 2001 cq_size *= 2; 2002 2003 cq_attr.cqe = cq_size; 2004 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler, 2005 NULL, ctx, &cq_attr); 2006 if (IS_ERR(ctx->cq)) { 2007 ret = PTR_ERR(ctx->cq); 2008 pr_err("Couldn't create tunnel CQ (%d)\n", ret); 2009 goto err_buf; 2010 } 2011 2012 ctx->pd = ib_alloc_pd(ctx->ib_dev, 0); 2013 if (IS_ERR(ctx->pd)) { 2014 ret = PTR_ERR(ctx->pd); 2015 pr_err("Couldn't create tunnel PD (%d)\n", ret); 2016 goto err_cq; 2017 } 2018 2019 if (ctx->has_smi) { 2020 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun); 2021 if (ret) { 2022 pr_err("Couldn't create %s QP0 (%d)\n", 2023 create_tun ? "tunnel for" : "", ret); 2024 goto err_pd; 2025 } 2026 } 2027 2028 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun); 2029 if (ret) { 2030 pr_err("Couldn't create %s QP1 (%d)\n", 2031 create_tun ? "tunnel for" : "", ret); 2032 goto err_qp0; 2033 } 2034 2035 if (create_tun) 2036 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker); 2037 else 2038 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker); 2039 2040 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq; 2041 2042 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 2043 if (ret) { 2044 pr_err("Couldn't arm tunnel cq (%d)\n", ret); 2045 goto err_wq; 2046 } 2047 ctx->state = DEMUX_PV_STATE_ACTIVE; 2048 return 0; 2049 2050 err_wq: 2051 ctx->wq = NULL; 2052 ib_destroy_qp(ctx->qp[1].qp); 2053 ctx->qp[1].qp = NULL; 2054 2055 2056 err_qp0: 2057 if (ctx->has_smi) 2058 ib_destroy_qp(ctx->qp[0].qp); 2059 ctx->qp[0].qp = NULL; 2060 2061 err_pd: 2062 ib_dealloc_pd(ctx->pd); 2063 ctx->pd = NULL; 2064 2065 err_cq: 2066 ib_destroy_cq(ctx->cq); 2067 ctx->cq = NULL; 2068 2069 err_buf: 2070 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun); 2071 2072 err_out_qp0: 2073 if (ctx->has_smi) 2074 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun); 2075 err_out: 2076 ctx->state = DEMUX_PV_STATE_DOWN; 2077 return ret; 2078 } 2079 2080 static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port, 2081 struct mlx4_ib_demux_pv_ctx *ctx, int flush) 2082 { 2083 if (!ctx) 2084 return; 2085 if (ctx->state > DEMUX_PV_STATE_DOWN) { 2086 ctx->state = DEMUX_PV_STATE_DOWNING; 2087 if (flush) 2088 flush_workqueue(ctx->wq); 2089 if (ctx->has_smi) { 2090 ib_destroy_qp(ctx->qp[0].qp); 2091 ctx->qp[0].qp = NULL; 2092 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1); 2093 } 2094 ib_destroy_qp(ctx->qp[1].qp); 2095 ctx->qp[1].qp = NULL; 2096 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1); 2097 ib_dealloc_pd(ctx->pd); 2098 ctx->pd = NULL; 2099 ib_destroy_cq(ctx->cq); 2100 ctx->cq = NULL; 2101 ctx->state = DEMUX_PV_STATE_DOWN; 2102 } 2103 } 2104 2105 static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave, 2106 int port, int do_init) 2107 { 2108 int ret = 0; 2109 2110 if (!do_init) { 2111 clean_vf_mcast(&dev->sriov.demux[port - 1], slave); 2112 /* for master, destroy real sqp resources */ 2113 if (slave == mlx4_master_func_num(dev->dev)) 2114 destroy_pv_resources(dev, slave, port, 2115 dev->sriov.sqps[port - 1], 1); 2116 /* destroy the tunnel qp resources */ 2117 destroy_pv_resources(dev, slave, port, 2118 dev->sriov.demux[port - 1].tun[slave], 1); 2119 return 0; 2120 } 2121 2122 /* create the tunnel qp resources */ 2123 ret = create_pv_resources(&dev->ib_dev, slave, port, 1, 2124 dev->sriov.demux[port - 1].tun[slave]); 2125 2126 /* for master, create the real sqp resources */ 2127 if (!ret && slave == mlx4_master_func_num(dev->dev)) 2128 ret = create_pv_resources(&dev->ib_dev, slave, port, 0, 2129 dev->sriov.sqps[port - 1]); 2130 return ret; 2131 } 2132 2133 void mlx4_ib_tunnels_update_work(struct work_struct *work) 2134 { 2135 struct mlx4_ib_demux_work *dmxw; 2136 2137 dmxw = container_of(work, struct mlx4_ib_demux_work, work); 2138 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port, 2139 dmxw->do_init); 2140 kfree(dmxw); 2141 return; 2142 } 2143 2144 static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev, 2145 struct mlx4_ib_demux_ctx *ctx, 2146 int port) 2147 { 2148 char name[12]; 2149 int ret = 0; 2150 int i; 2151 2152 ctx->tun = kcalloc(dev->dev->caps.sqp_demux, 2153 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL); 2154 if (!ctx->tun) 2155 return -ENOMEM; 2156 2157 ctx->dev = dev; 2158 ctx->port = port; 2159 ctx->ib_dev = &dev->ib_dev; 2160 2161 for (i = 0; 2162 i < min(dev->dev->caps.sqp_demux, 2163 (u16)(dev->dev->persist->num_vfs + 1)); 2164 i++) { 2165 struct mlx4_active_ports actv_ports = 2166 mlx4_get_active_ports(dev->dev, i); 2167 2168 if (!test_bit(port - 1, actv_ports.ports)) 2169 continue; 2170 2171 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]); 2172 if (ret) { 2173 ret = -ENOMEM; 2174 goto err_mcg; 2175 } 2176 } 2177 2178 ret = mlx4_ib_mcg_port_init(ctx); 2179 if (ret) { 2180 pr_err("Failed initializing mcg para-virt (%d)\n", ret); 2181 goto err_mcg; 2182 } 2183 2184 snprintf(name, sizeof name, "mlx4_ibt%d", port); 2185 ctx->wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM); 2186 if (!ctx->wq) { 2187 pr_err("Failed to create tunnelling WQ for port %d\n", port); 2188 ret = -ENOMEM; 2189 goto err_wq; 2190 } 2191 2192 snprintf(name, sizeof name, "mlx4_ibud%d", port); 2193 ctx->ud_wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM); 2194 if (!ctx->ud_wq) { 2195 pr_err("Failed to create up/down WQ for port %d\n", port); 2196 ret = -ENOMEM; 2197 goto err_udwq; 2198 } 2199 2200 return 0; 2201 2202 err_udwq: 2203 destroy_workqueue(ctx->wq); 2204 ctx->wq = NULL; 2205 2206 err_wq: 2207 mlx4_ib_mcg_port_cleanup(ctx, 1); 2208 err_mcg: 2209 for (i = 0; i < dev->dev->caps.sqp_demux; i++) 2210 free_pv_object(dev, i, port); 2211 kfree(ctx->tun); 2212 ctx->tun = NULL; 2213 return ret; 2214 } 2215 2216 static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx) 2217 { 2218 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) { 2219 sqp_ctx->state = DEMUX_PV_STATE_DOWNING; 2220 flush_workqueue(sqp_ctx->wq); 2221 if (sqp_ctx->has_smi) { 2222 ib_destroy_qp(sqp_ctx->qp[0].qp); 2223 sqp_ctx->qp[0].qp = NULL; 2224 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0); 2225 } 2226 ib_destroy_qp(sqp_ctx->qp[1].qp); 2227 sqp_ctx->qp[1].qp = NULL; 2228 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0); 2229 ib_dealloc_pd(sqp_ctx->pd); 2230 sqp_ctx->pd = NULL; 2231 ib_destroy_cq(sqp_ctx->cq); 2232 sqp_ctx->cq = NULL; 2233 sqp_ctx->state = DEMUX_PV_STATE_DOWN; 2234 } 2235 } 2236 2237 static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx) 2238 { 2239 int i; 2240 if (ctx) { 2241 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 2242 mlx4_ib_mcg_port_cleanup(ctx, 1); 2243 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2244 if (!ctx->tun[i]) 2245 continue; 2246 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN) 2247 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING; 2248 } 2249 flush_workqueue(ctx->wq); 2250 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2251 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0); 2252 free_pv_object(dev, i, ctx->port); 2253 } 2254 kfree(ctx->tun); 2255 destroy_workqueue(ctx->ud_wq); 2256 destroy_workqueue(ctx->wq); 2257 } 2258 } 2259 2260 static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init) 2261 { 2262 int i; 2263 2264 if (!mlx4_is_master(dev->dev)) 2265 return; 2266 /* initialize or tear down tunnel QPs for the master */ 2267 for (i = 0; i < dev->dev->caps.num_ports; i++) 2268 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init); 2269 return; 2270 } 2271 2272 int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev) 2273 { 2274 int i = 0; 2275 int err; 2276 2277 if (!mlx4_is_mfunc(dev->dev)) 2278 return 0; 2279 2280 dev->sriov.is_going_down = 0; 2281 spin_lock_init(&dev->sriov.going_down_lock); 2282 mlx4_ib_cm_paravirt_init(dev); 2283 2284 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n"); 2285 2286 if (mlx4_is_slave(dev->dev)) { 2287 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n"); 2288 return 0; 2289 } 2290 2291 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2292 if (i == mlx4_master_func_num(dev->dev)) 2293 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid); 2294 else 2295 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid()); 2296 } 2297 2298 err = mlx4_ib_init_alias_guid_service(dev); 2299 if (err) { 2300 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n"); 2301 goto paravirt_err; 2302 } 2303 err = mlx4_ib_device_register_sysfs(dev); 2304 if (err) { 2305 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n"); 2306 goto sysfs_err; 2307 } 2308 2309 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n", 2310 dev->dev->caps.sqp_demux); 2311 for (i = 0; i < dev->num_ports; i++) { 2312 union ib_gid gid; 2313 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1); 2314 if (err) 2315 goto demux_err; 2316 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id; 2317 atomic64_set(&dev->sriov.demux[i].subnet_prefix, 2318 be64_to_cpu(gid.global.subnet_prefix)); 2319 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1, 2320 &dev->sriov.sqps[i]); 2321 if (err) 2322 goto demux_err; 2323 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1); 2324 if (err) 2325 goto free_pv; 2326 } 2327 mlx4_ib_master_tunnels(dev, 1); 2328 return 0; 2329 2330 free_pv: 2331 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2332 demux_err: 2333 while (--i >= 0) { 2334 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2335 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2336 } 2337 mlx4_ib_device_unregister_sysfs(dev); 2338 2339 sysfs_err: 2340 mlx4_ib_destroy_alias_guid_service(dev); 2341 2342 paravirt_err: 2343 mlx4_ib_cm_paravirt_clean(dev, -1); 2344 2345 return err; 2346 } 2347 2348 void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev) 2349 { 2350 int i; 2351 unsigned long flags; 2352 2353 if (!mlx4_is_mfunc(dev->dev)) 2354 return; 2355 2356 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 2357 dev->sriov.is_going_down = 1; 2358 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 2359 if (mlx4_is_master(dev->dev)) { 2360 for (i = 0; i < dev->num_ports; i++) { 2361 flush_workqueue(dev->sriov.demux[i].ud_wq); 2362 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]); 2363 kfree(dev->sriov.sqps[i]); 2364 dev->sriov.sqps[i] = NULL; 2365 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2366 } 2367 2368 mlx4_ib_cm_paravirt_clean(dev, -1); 2369 mlx4_ib_destroy_alias_guid_service(dev); 2370 mlx4_ib_device_unregister_sysfs(dev); 2371 } 2372 } 2373