1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/mlx4/qp.h> 36 #include <linux/mlx4/srq.h> 37 #include <linux/slab.h> 38 39 #include "mlx4_ib.h" 40 #include <rdma/mlx4-abi.h> 41 #include <rdma/uverbs_ioctl.h> 42 43 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 44 { 45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 46 ibcq->comp_handler(ibcq, ibcq->cq_context); 47 } 48 49 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 50 { 51 struct ib_event event; 52 struct ib_cq *ibcq; 53 54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 55 pr_warn("Unexpected event type %d " 56 "on CQ %06x\n", type, cq->cqn); 57 return; 58 } 59 60 ibcq = &to_mibcq(cq)->ibcq; 61 if (ibcq->event_handler) { 62 event.device = ibcq->device; 63 event.event = IB_EVENT_CQ_ERR; 64 event.element.cq = ibcq; 65 ibcq->event_handler(&event, ibcq->cq_context); 66 } 67 } 68 69 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 70 { 71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 72 } 73 74 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 75 { 76 return get_cqe_from_buf(&cq->buf, n); 77 } 78 79 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 80 { 81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 83 84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 86 } 87 88 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 89 { 90 return get_sw_cqe(cq, cq->mcq.cons_index); 91 } 92 93 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 94 { 95 struct mlx4_ib_cq *mcq = to_mcq(cq); 96 struct mlx4_ib_dev *dev = to_mdev(cq->device); 97 98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 99 } 100 101 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 102 { 103 int err; 104 105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 106 PAGE_SIZE * 2, &buf->buf); 107 108 if (err) 109 goto out; 110 111 buf->entry_size = dev->dev->caps.cqe_size; 112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 113 &buf->mtt); 114 if (err) 115 goto err_buf; 116 117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); 118 if (err) 119 goto err_mtt; 120 121 return 0; 122 123 err_mtt: 124 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 125 126 err_buf: 127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 128 129 out: 130 return err; 131 } 132 133 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 134 { 135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 136 } 137 138 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_udata *udata, 139 struct mlx4_ib_cq_buf *buf, 140 struct ib_umem **umem, u64 buf_addr, int cqe) 141 { 142 int err; 143 int cqe_size = dev->dev->caps.cqe_size; 144 int shift; 145 int n; 146 147 *umem = ib_umem_get(udata, buf_addr, cqe * cqe_size, 148 IB_ACCESS_LOCAL_WRITE, 1); 149 if (IS_ERR(*umem)) 150 return PTR_ERR(*umem); 151 152 n = ib_umem_page_count(*umem); 153 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n); 154 err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt); 155 156 if (err) 157 goto err_buf; 158 159 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 160 if (err) 161 goto err_mtt; 162 163 return 0; 164 165 err_mtt: 166 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 167 168 err_buf: 169 ib_umem_release(*umem); 170 171 return err; 172 } 173 174 #define CQ_CREATE_FLAGS_SUPPORTED IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION 175 int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 176 struct ib_udata *udata) 177 { 178 struct ib_device *ibdev = ibcq->device; 179 int entries = attr->cqe; 180 int vector = attr->comp_vector; 181 struct mlx4_ib_dev *dev = to_mdev(ibdev); 182 struct mlx4_ib_cq *cq = to_mcq(ibcq); 183 struct mlx4_uar *uar; 184 void *buf_addr; 185 int err; 186 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context( 187 udata, struct mlx4_ib_ucontext, ibucontext); 188 189 if (entries < 1 || entries > dev->dev->caps.max_cqes) 190 return -EINVAL; 191 192 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 193 return -EINVAL; 194 195 entries = roundup_pow_of_two(entries + 1); 196 cq->ibcq.cqe = entries - 1; 197 mutex_init(&cq->resize_mutex); 198 spin_lock_init(&cq->lock); 199 cq->resize_buf = NULL; 200 cq->resize_umem = NULL; 201 cq->create_flags = attr->flags; 202 INIT_LIST_HEAD(&cq->send_qp_list); 203 INIT_LIST_HEAD(&cq->recv_qp_list); 204 205 if (udata) { 206 struct mlx4_ib_create_cq ucmd; 207 208 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 209 err = -EFAULT; 210 goto err_cq; 211 } 212 213 buf_addr = (void *)(unsigned long)ucmd.buf_addr; 214 err = mlx4_ib_get_cq_umem(dev, udata, &cq->buf, &cq->umem, 215 ucmd.buf_addr, entries); 216 if (err) 217 goto err_cq; 218 219 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &cq->db); 220 if (err) 221 goto err_mtt; 222 223 uar = &context->uar; 224 cq->mcq.usage = MLX4_RES_USAGE_USER_VERBS; 225 } else { 226 err = mlx4_db_alloc(dev->dev, &cq->db, 1); 227 if (err) 228 goto err_cq; 229 230 cq->mcq.set_ci_db = cq->db.db; 231 cq->mcq.arm_db = cq->db.db + 1; 232 *cq->mcq.set_ci_db = 0; 233 *cq->mcq.arm_db = 0; 234 235 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 236 if (err) 237 goto err_db; 238 239 buf_addr = &cq->buf.buf; 240 241 uar = &dev->priv_uar; 242 cq->mcq.usage = MLX4_RES_USAGE_DRIVER; 243 } 244 245 if (dev->eq_table) 246 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 247 248 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, cq->db.dma, 249 &cq->mcq, vector, 0, 250 !!(cq->create_flags & 251 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION), 252 buf_addr, !!udata); 253 if (err) 254 goto err_dbmap; 255 256 if (udata) 257 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp; 258 else 259 cq->mcq.comp = mlx4_ib_cq_comp; 260 cq->mcq.event = mlx4_ib_cq_event; 261 262 if (udata) 263 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 264 err = -EFAULT; 265 goto err_cq_free; 266 } 267 268 return 0; 269 270 err_cq_free: 271 mlx4_cq_free(dev->dev, &cq->mcq); 272 273 err_dbmap: 274 if (udata) 275 mlx4_ib_db_unmap_user(context, &cq->db); 276 277 err_mtt: 278 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 279 280 ib_umem_release(cq->umem); 281 if (!udata) 282 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 283 284 err_db: 285 if (!udata) 286 mlx4_db_free(dev->dev, &cq->db); 287 err_cq: 288 return err; 289 } 290 291 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 292 int entries) 293 { 294 int err; 295 296 if (cq->resize_buf) 297 return -EBUSY; 298 299 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 300 if (!cq->resize_buf) 301 return -ENOMEM; 302 303 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 304 if (err) { 305 kfree(cq->resize_buf); 306 cq->resize_buf = NULL; 307 return err; 308 } 309 310 cq->resize_buf->cqe = entries - 1; 311 312 return 0; 313 } 314 315 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 316 int entries, struct ib_udata *udata) 317 { 318 struct mlx4_ib_resize_cq ucmd; 319 int err; 320 321 if (cq->resize_umem) 322 return -EBUSY; 323 324 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 325 return -EFAULT; 326 327 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 328 if (!cq->resize_buf) 329 return -ENOMEM; 330 331 err = mlx4_ib_get_cq_umem(dev, udata, &cq->resize_buf->buf, 332 &cq->resize_umem, ucmd.buf_addr, entries); 333 if (err) { 334 kfree(cq->resize_buf); 335 cq->resize_buf = NULL; 336 return err; 337 } 338 339 cq->resize_buf->cqe = entries - 1; 340 341 return 0; 342 } 343 344 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 345 { 346 u32 i; 347 348 i = cq->mcq.cons_index; 349 while (get_sw_cqe(cq, i)) 350 ++i; 351 352 return i - cq->mcq.cons_index; 353 } 354 355 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 356 { 357 struct mlx4_cqe *cqe, *new_cqe; 358 int i; 359 int cqe_size = cq->buf.entry_size; 360 int cqe_inc = cqe_size == 64 ? 1 : 0; 361 362 i = cq->mcq.cons_index; 363 cqe = get_cqe(cq, i & cq->ibcq.cqe); 364 cqe += cqe_inc; 365 366 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 367 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 368 (i + 1) & cq->resize_buf->cqe); 369 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 370 new_cqe += cqe_inc; 371 372 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 373 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 374 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 375 cqe += cqe_inc; 376 } 377 ++cq->mcq.cons_index; 378 } 379 380 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 381 { 382 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 383 struct mlx4_ib_cq *cq = to_mcq(ibcq); 384 struct mlx4_mtt mtt; 385 int outst_cqe; 386 int err; 387 388 mutex_lock(&cq->resize_mutex); 389 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 390 err = -EINVAL; 391 goto out; 392 } 393 394 entries = roundup_pow_of_two(entries + 1); 395 if (entries == ibcq->cqe + 1) { 396 err = 0; 397 goto out; 398 } 399 400 if (entries > dev->dev->caps.max_cqes + 1) { 401 err = -EINVAL; 402 goto out; 403 } 404 405 if (ibcq->uobject) { 406 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 407 if (err) 408 goto out; 409 } else { 410 /* Can't be smaller than the number of outstanding CQEs */ 411 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 412 if (entries < outst_cqe + 1) { 413 err = -EINVAL; 414 goto out; 415 } 416 417 err = mlx4_alloc_resize_buf(dev, cq, entries); 418 if (err) 419 goto out; 420 } 421 422 mtt = cq->buf.mtt; 423 424 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 425 if (err) 426 goto err_buf; 427 428 mlx4_mtt_cleanup(dev->dev, &mtt); 429 if (ibcq->uobject) { 430 cq->buf = cq->resize_buf->buf; 431 cq->ibcq.cqe = cq->resize_buf->cqe; 432 ib_umem_release(cq->umem); 433 cq->umem = cq->resize_umem; 434 435 kfree(cq->resize_buf); 436 cq->resize_buf = NULL; 437 cq->resize_umem = NULL; 438 } else { 439 struct mlx4_ib_cq_buf tmp_buf; 440 int tmp_cqe = 0; 441 442 spin_lock_irq(&cq->lock); 443 if (cq->resize_buf) { 444 mlx4_ib_cq_resize_copy_cqes(cq); 445 tmp_buf = cq->buf; 446 tmp_cqe = cq->ibcq.cqe; 447 cq->buf = cq->resize_buf->buf; 448 cq->ibcq.cqe = cq->resize_buf->cqe; 449 450 kfree(cq->resize_buf); 451 cq->resize_buf = NULL; 452 } 453 spin_unlock_irq(&cq->lock); 454 455 if (tmp_cqe) 456 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 457 } 458 459 goto out; 460 461 err_buf: 462 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 463 if (!ibcq->uobject) 464 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 465 cq->resize_buf->cqe); 466 467 kfree(cq->resize_buf); 468 cq->resize_buf = NULL; 469 470 ib_umem_release(cq->resize_umem); 471 cq->resize_umem = NULL; 472 out: 473 mutex_unlock(&cq->resize_mutex); 474 475 return err; 476 } 477 478 void mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) 479 { 480 struct mlx4_ib_dev *dev = to_mdev(cq->device); 481 struct mlx4_ib_cq *mcq = to_mcq(cq); 482 483 mlx4_cq_free(dev->dev, &mcq->mcq); 484 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 485 486 if (udata) { 487 mlx4_ib_db_unmap_user( 488 rdma_udata_to_drv_context( 489 udata, 490 struct mlx4_ib_ucontext, 491 ibucontext), 492 &mcq->db); 493 } else { 494 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 495 mlx4_db_free(dev->dev, &mcq->db); 496 } 497 ib_umem_release(mcq->umem); 498 } 499 500 static void dump_cqe(void *cqe) 501 { 502 __be32 *buf = cqe; 503 504 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 505 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 506 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 507 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 508 } 509 510 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 511 struct ib_wc *wc) 512 { 513 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 514 pr_debug("local QP operation err " 515 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 516 "opcode = %02x)\n", 517 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 518 cqe->vendor_err_syndrome, 519 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 520 dump_cqe(cqe); 521 } 522 523 switch (cqe->syndrome) { 524 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 525 wc->status = IB_WC_LOC_LEN_ERR; 526 break; 527 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 528 wc->status = IB_WC_LOC_QP_OP_ERR; 529 break; 530 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 531 wc->status = IB_WC_LOC_PROT_ERR; 532 break; 533 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 534 wc->status = IB_WC_WR_FLUSH_ERR; 535 break; 536 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 537 wc->status = IB_WC_MW_BIND_ERR; 538 break; 539 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 540 wc->status = IB_WC_BAD_RESP_ERR; 541 break; 542 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 543 wc->status = IB_WC_LOC_ACCESS_ERR; 544 break; 545 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 546 wc->status = IB_WC_REM_INV_REQ_ERR; 547 break; 548 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 549 wc->status = IB_WC_REM_ACCESS_ERR; 550 break; 551 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 552 wc->status = IB_WC_REM_OP_ERR; 553 break; 554 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 555 wc->status = IB_WC_RETRY_EXC_ERR; 556 break; 557 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 558 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 559 break; 560 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 561 wc->status = IB_WC_REM_ABORT_ERR; 562 break; 563 default: 564 wc->status = IB_WC_GENERAL_ERR; 565 break; 566 } 567 568 wc->vendor_err = cqe->vendor_err_syndrome; 569 } 570 571 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) 572 { 573 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 574 MLX4_CQE_STATUS_IPV4F | 575 MLX4_CQE_STATUS_IPV4OPT | 576 MLX4_CQE_STATUS_IPV6 | 577 MLX4_CQE_STATUS_IPOK)) == 578 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 579 MLX4_CQE_STATUS_IPOK)) && 580 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | 581 MLX4_CQE_STATUS_TCP)) && 582 checksum == cpu_to_be16(0xffff); 583 } 584 585 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 586 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 587 { 588 struct mlx4_ib_proxy_sqp_hdr *hdr; 589 590 ib_dma_sync_single_for_cpu(qp->ibqp.device, 591 qp->sqp_proxy_rcv[tail].map, 592 sizeof (struct mlx4_ib_proxy_sqp_hdr), 593 DMA_FROM_DEVICE); 594 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 595 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 596 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 597 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 598 wc->dlid_path_bits = 0; 599 600 if (is_eth) { 601 wc->slid = 0; 602 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 603 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 604 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 605 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 606 } else { 607 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 608 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 609 } 610 } 611 612 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 613 struct ib_wc *wc, int *npolled, int is_send) 614 { 615 struct mlx4_ib_wq *wq; 616 unsigned cur; 617 int i; 618 619 wq = is_send ? &qp->sq : &qp->rq; 620 cur = wq->head - wq->tail; 621 622 if (cur == 0) 623 return; 624 625 for (i = 0; i < cur && *npolled < num_entries; i++) { 626 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 627 wc->status = IB_WC_WR_FLUSH_ERR; 628 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 629 wq->tail++; 630 (*npolled)++; 631 wc->qp = &qp->ibqp; 632 wc++; 633 } 634 } 635 636 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 637 struct ib_wc *wc, int *npolled) 638 { 639 struct mlx4_ib_qp *qp; 640 641 *npolled = 0; 642 /* Find uncompleted WQEs belonging to that cq and return 643 * simulated FLUSH_ERR completions 644 */ 645 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 646 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 647 if (*npolled >= num_entries) 648 goto out; 649 } 650 651 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 652 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 653 if (*npolled >= num_entries) 654 goto out; 655 } 656 657 out: 658 return; 659 } 660 661 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 662 struct mlx4_ib_qp **cur_qp, 663 struct ib_wc *wc) 664 { 665 struct mlx4_cqe *cqe; 666 struct mlx4_qp *mqp; 667 struct mlx4_ib_wq *wq; 668 struct mlx4_ib_srq *srq; 669 struct mlx4_srq *msrq = NULL; 670 int is_send; 671 int is_error; 672 int is_eth; 673 u32 g_mlpath_rqpn; 674 u16 wqe_ctr; 675 unsigned tail = 0; 676 677 repoll: 678 cqe = next_cqe_sw(cq); 679 if (!cqe) 680 return -EAGAIN; 681 682 if (cq->buf.entry_size == 64) 683 cqe++; 684 685 ++cq->mcq.cons_index; 686 687 /* 688 * Make sure we read CQ entry contents after we've checked the 689 * ownership bit. 690 */ 691 rmb(); 692 693 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 694 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 695 MLX4_CQE_OPCODE_ERROR; 696 697 /* Resize CQ in progress */ 698 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 699 if (cq->resize_buf) { 700 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 701 702 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 703 cq->buf = cq->resize_buf->buf; 704 cq->ibcq.cqe = cq->resize_buf->cqe; 705 706 kfree(cq->resize_buf); 707 cq->resize_buf = NULL; 708 } 709 710 goto repoll; 711 } 712 713 if (!*cur_qp || 714 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 715 /* 716 * We do not have to take the QP table lock here, 717 * because CQs will be locked while QPs are removed 718 * from the table. 719 */ 720 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 721 be32_to_cpu(cqe->vlan_my_qpn)); 722 *cur_qp = to_mibqp(mqp); 723 } 724 725 wc->qp = &(*cur_qp)->ibqp; 726 727 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 728 u32 srq_num; 729 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 730 srq_num = g_mlpath_rqpn & 0xffffff; 731 /* SRQ is also in the radix tree */ 732 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 733 srq_num); 734 } 735 736 if (is_send) { 737 wq = &(*cur_qp)->sq; 738 if (!(*cur_qp)->sq_signal_bits) { 739 wqe_ctr = be16_to_cpu(cqe->wqe_index); 740 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 741 } 742 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 743 ++wq->tail; 744 } else if ((*cur_qp)->ibqp.srq) { 745 srq = to_msrq((*cur_qp)->ibqp.srq); 746 wqe_ctr = be16_to_cpu(cqe->wqe_index); 747 wc->wr_id = srq->wrid[wqe_ctr]; 748 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 749 } else if (msrq) { 750 srq = to_mibsrq(msrq); 751 wqe_ctr = be16_to_cpu(cqe->wqe_index); 752 wc->wr_id = srq->wrid[wqe_ctr]; 753 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 754 } else { 755 wq = &(*cur_qp)->rq; 756 tail = wq->tail & (wq->wqe_cnt - 1); 757 wc->wr_id = wq->wrid[tail]; 758 ++wq->tail; 759 } 760 761 if (unlikely(is_error)) { 762 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 763 return 0; 764 } 765 766 wc->status = IB_WC_SUCCESS; 767 768 if (is_send) { 769 wc->wc_flags = 0; 770 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 771 case MLX4_OPCODE_RDMA_WRITE_IMM: 772 wc->wc_flags |= IB_WC_WITH_IMM; 773 /* fall through */ 774 case MLX4_OPCODE_RDMA_WRITE: 775 wc->opcode = IB_WC_RDMA_WRITE; 776 break; 777 case MLX4_OPCODE_SEND_IMM: 778 wc->wc_flags |= IB_WC_WITH_IMM; 779 /* fall through */ 780 case MLX4_OPCODE_SEND: 781 case MLX4_OPCODE_SEND_INVAL: 782 wc->opcode = IB_WC_SEND; 783 break; 784 case MLX4_OPCODE_RDMA_READ: 785 wc->opcode = IB_WC_RDMA_READ; 786 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 787 break; 788 case MLX4_OPCODE_ATOMIC_CS: 789 wc->opcode = IB_WC_COMP_SWAP; 790 wc->byte_len = 8; 791 break; 792 case MLX4_OPCODE_ATOMIC_FA: 793 wc->opcode = IB_WC_FETCH_ADD; 794 wc->byte_len = 8; 795 break; 796 case MLX4_OPCODE_MASKED_ATOMIC_CS: 797 wc->opcode = IB_WC_MASKED_COMP_SWAP; 798 wc->byte_len = 8; 799 break; 800 case MLX4_OPCODE_MASKED_ATOMIC_FA: 801 wc->opcode = IB_WC_MASKED_FETCH_ADD; 802 wc->byte_len = 8; 803 break; 804 case MLX4_OPCODE_LSO: 805 wc->opcode = IB_WC_LSO; 806 break; 807 case MLX4_OPCODE_FMR: 808 wc->opcode = IB_WC_REG_MR; 809 break; 810 case MLX4_OPCODE_LOCAL_INVAL: 811 wc->opcode = IB_WC_LOCAL_INV; 812 break; 813 } 814 } else { 815 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 816 817 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 818 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 819 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 820 wc->wc_flags = IB_WC_WITH_IMM; 821 wc->ex.imm_data = cqe->immed_rss_invalid; 822 break; 823 case MLX4_RECV_OPCODE_SEND_INVAL: 824 wc->opcode = IB_WC_RECV; 825 wc->wc_flags = IB_WC_WITH_INVALIDATE; 826 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 827 break; 828 case MLX4_RECV_OPCODE_SEND: 829 wc->opcode = IB_WC_RECV; 830 wc->wc_flags = 0; 831 break; 832 case MLX4_RECV_OPCODE_SEND_IMM: 833 wc->opcode = IB_WC_RECV; 834 wc->wc_flags = IB_WC_WITH_IMM; 835 wc->ex.imm_data = cqe->immed_rss_invalid; 836 break; 837 } 838 839 is_eth = (rdma_port_get_link_layer(wc->qp->device, 840 (*cur_qp)->port) == 841 IB_LINK_LAYER_ETHERNET); 842 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 843 if ((*cur_qp)->mlx4_ib_qp_type & 844 (MLX4_IB_QPT_PROXY_SMI_OWNER | 845 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 846 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 847 is_eth); 848 return 0; 849 } 850 } 851 852 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 853 wc->src_qp = g_mlpath_rqpn & 0xffffff; 854 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 855 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 856 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 857 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 858 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 859 if (is_eth) { 860 wc->slid = 0; 861 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 862 if (be32_to_cpu(cqe->vlan_my_qpn) & 863 MLX4_CQE_CVLAN_PRESENT_MASK) { 864 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 865 MLX4_CQE_VID_MASK; 866 } else { 867 wc->vlan_id = 0xffff; 868 } 869 memcpy(wc->smac, cqe->smac, ETH_ALEN); 870 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 871 } else { 872 wc->slid = be16_to_cpu(cqe->rlid); 873 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 874 wc->vlan_id = 0xffff; 875 } 876 } 877 878 return 0; 879 } 880 881 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 882 { 883 struct mlx4_ib_cq *cq = to_mcq(ibcq); 884 struct mlx4_ib_qp *cur_qp = NULL; 885 unsigned long flags; 886 int npolled; 887 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 888 889 spin_lock_irqsave(&cq->lock, flags); 890 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 891 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 892 goto out; 893 } 894 895 for (npolled = 0; npolled < num_entries; ++npolled) { 896 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 897 break; 898 } 899 900 mlx4_cq_set_ci(&cq->mcq); 901 902 out: 903 spin_unlock_irqrestore(&cq->lock, flags); 904 905 return npolled; 906 } 907 908 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 909 { 910 mlx4_cq_arm(&to_mcq(ibcq)->mcq, 911 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 912 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 913 to_mdev(ibcq->device)->uar_map, 914 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); 915 916 return 0; 917 } 918 919 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 920 { 921 u32 prod_index; 922 int nfreed = 0; 923 struct mlx4_cqe *cqe, *dest; 924 u8 owner_bit; 925 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 926 927 /* 928 * First we need to find the current producer index, so we 929 * know where to start cleaning from. It doesn't matter if HW 930 * adds new entries after this loop -- the QP we're worried 931 * about is already in RESET, so the new entries won't come 932 * from our QP and therefore don't need to be checked. 933 */ 934 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 935 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 936 break; 937 938 /* 939 * Now sweep backwards through the CQ, removing CQ entries 940 * that match our QP by copying older entries on top of them. 941 */ 942 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 943 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 944 cqe += cqe_inc; 945 946 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 947 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 948 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 949 ++nfreed; 950 } else if (nfreed) { 951 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 952 dest += cqe_inc; 953 954 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 955 memcpy(dest, cqe, sizeof *cqe); 956 dest->owner_sr_opcode = owner_bit | 957 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 958 } 959 } 960 961 if (nfreed) { 962 cq->mcq.cons_index += nfreed; 963 /* 964 * Make sure update of buffer contents is done before 965 * updating consumer index. 966 */ 967 wmb(); 968 mlx4_cq_set_ci(&cq->mcq); 969 } 970 } 971 972 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 973 { 974 spin_lock_irq(&cq->lock); 975 __mlx4_ib_cq_clean(cq, qpn, srq); 976 spin_unlock_irq(&cq->lock); 977 } 978