1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/mlx4/cq.h> 35 #include <linux/mlx4/qp.h> 36 #include <linux/mlx4/srq.h> 37 #include <linux/slab.h> 38 39 #include "mlx4_ib.h" 40 #include <rdma/mlx4-abi.h> 41 42 static void mlx4_ib_cq_comp(struct mlx4_cq *cq) 43 { 44 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; 45 ibcq->comp_handler(ibcq, ibcq->cq_context); 46 } 47 48 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) 49 { 50 struct ib_event event; 51 struct ib_cq *ibcq; 52 53 if (type != MLX4_EVENT_TYPE_CQ_ERROR) { 54 pr_warn("Unexpected event type %d " 55 "on CQ %06x\n", type, cq->cqn); 56 return; 57 } 58 59 ibcq = &to_mibcq(cq)->ibcq; 60 if (ibcq->event_handler) { 61 event.device = ibcq->device; 62 event.event = IB_EVENT_CQ_ERR; 63 event.element.cq = ibcq; 64 ibcq->event_handler(&event, ibcq->cq_context); 65 } 66 } 67 68 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) 69 { 70 return mlx4_buf_offset(&buf->buf, n * buf->entry_size); 71 } 72 73 static void *get_cqe(struct mlx4_ib_cq *cq, int n) 74 { 75 return get_cqe_from_buf(&cq->buf, n); 76 } 77 78 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) 79 { 80 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); 81 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe); 82 83 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ 84 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; 85 } 86 87 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) 88 { 89 return get_sw_cqe(cq, cq->mcq.cons_index); 90 } 91 92 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 93 { 94 struct mlx4_ib_cq *mcq = to_mcq(cq); 95 struct mlx4_ib_dev *dev = to_mdev(cq->device); 96 97 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); 98 } 99 100 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) 101 { 102 int err; 103 104 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, 105 PAGE_SIZE * 2, &buf->buf); 106 107 if (err) 108 goto out; 109 110 buf->entry_size = dev->dev->caps.cqe_size; 111 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, 112 &buf->mtt); 113 if (err) 114 goto err_buf; 115 116 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); 117 if (err) 118 goto err_mtt; 119 120 return 0; 121 122 err_mtt: 123 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 124 125 err_buf: 126 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf); 127 128 out: 129 return err; 130 } 131 132 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) 133 { 134 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf); 135 } 136 137 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context, 138 struct mlx4_ib_cq_buf *buf, struct ib_umem **umem, 139 u64 buf_addr, int cqe) 140 { 141 int err; 142 int cqe_size = dev->dev->caps.cqe_size; 143 144 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size, 145 IB_ACCESS_LOCAL_WRITE, 1); 146 if (IS_ERR(*umem)) 147 return PTR_ERR(*umem); 148 149 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), 150 (*umem)->page_shift, &buf->mtt); 151 if (err) 152 goto err_buf; 153 154 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); 155 if (err) 156 goto err_mtt; 157 158 return 0; 159 160 err_mtt: 161 mlx4_mtt_cleanup(dev->dev, &buf->mtt); 162 163 err_buf: 164 ib_umem_release(*umem); 165 166 return err; 167 } 168 169 #define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION 170 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, 171 const struct ib_cq_init_attr *attr, 172 struct ib_ucontext *context, 173 struct ib_udata *udata) 174 { 175 int entries = attr->cqe; 176 int vector = attr->comp_vector; 177 struct mlx4_ib_dev *dev = to_mdev(ibdev); 178 struct mlx4_ib_cq *cq; 179 struct mlx4_uar *uar; 180 int err; 181 182 if (entries < 1 || entries > dev->dev->caps.max_cqes) 183 return ERR_PTR(-EINVAL); 184 185 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED) 186 return ERR_PTR(-EINVAL); 187 188 cq = kmalloc(sizeof *cq, GFP_KERNEL); 189 if (!cq) 190 return ERR_PTR(-ENOMEM); 191 192 entries = roundup_pow_of_two(entries + 1); 193 cq->ibcq.cqe = entries - 1; 194 mutex_init(&cq->resize_mutex); 195 spin_lock_init(&cq->lock); 196 cq->resize_buf = NULL; 197 cq->resize_umem = NULL; 198 cq->create_flags = attr->flags; 199 INIT_LIST_HEAD(&cq->send_qp_list); 200 INIT_LIST_HEAD(&cq->recv_qp_list); 201 202 if (context) { 203 struct mlx4_ib_create_cq ucmd; 204 205 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 206 err = -EFAULT; 207 goto err_cq; 208 } 209 210 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem, 211 ucmd.buf_addr, entries); 212 if (err) 213 goto err_cq; 214 215 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr, 216 &cq->db); 217 if (err) 218 goto err_mtt; 219 220 uar = &to_mucontext(context)->uar; 221 } else { 222 err = mlx4_db_alloc(dev->dev, &cq->db, 1); 223 if (err) 224 goto err_cq; 225 226 cq->mcq.set_ci_db = cq->db.db; 227 cq->mcq.arm_db = cq->db.db + 1; 228 *cq->mcq.set_ci_db = 0; 229 *cq->mcq.arm_db = 0; 230 231 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); 232 if (err) 233 goto err_db; 234 235 uar = &dev->priv_uar; 236 } 237 238 if (dev->eq_table) 239 vector = dev->eq_table[vector % ibdev->num_comp_vectors]; 240 241 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, 242 cq->db.dma, &cq->mcq, vector, 0, 243 !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION)); 244 if (err) 245 goto err_dbmap; 246 247 if (context) 248 cq->mcq.tasklet_ctx.comp = mlx4_ib_cq_comp; 249 else 250 cq->mcq.comp = mlx4_ib_cq_comp; 251 cq->mcq.event = mlx4_ib_cq_event; 252 253 if (context) 254 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { 255 err = -EFAULT; 256 goto err_cq_free; 257 } 258 259 return &cq->ibcq; 260 261 err_cq_free: 262 mlx4_cq_free(dev->dev, &cq->mcq); 263 264 err_dbmap: 265 if (context) 266 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db); 267 268 err_mtt: 269 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); 270 271 if (context) 272 ib_umem_release(cq->umem); 273 else 274 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 275 276 err_db: 277 if (!context) 278 mlx4_db_free(dev->dev, &cq->db); 279 280 err_cq: 281 kfree(cq); 282 283 return ERR_PTR(err); 284 } 285 286 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 287 int entries) 288 { 289 int err; 290 291 if (cq->resize_buf) 292 return -EBUSY; 293 294 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 295 if (!cq->resize_buf) 296 return -ENOMEM; 297 298 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); 299 if (err) { 300 kfree(cq->resize_buf); 301 cq->resize_buf = NULL; 302 return err; 303 } 304 305 cq->resize_buf->cqe = entries - 1; 306 307 return 0; 308 } 309 310 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, 311 int entries, struct ib_udata *udata) 312 { 313 struct mlx4_ib_resize_cq ucmd; 314 int err; 315 316 if (cq->resize_umem) 317 return -EBUSY; 318 319 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) 320 return -EFAULT; 321 322 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL); 323 if (!cq->resize_buf) 324 return -ENOMEM; 325 326 err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf, 327 &cq->resize_umem, ucmd.buf_addr, entries); 328 if (err) { 329 kfree(cq->resize_buf); 330 cq->resize_buf = NULL; 331 return err; 332 } 333 334 cq->resize_buf->cqe = entries - 1; 335 336 return 0; 337 } 338 339 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) 340 { 341 u32 i; 342 343 i = cq->mcq.cons_index; 344 while (get_sw_cqe(cq, i)) 345 ++i; 346 347 return i - cq->mcq.cons_index; 348 } 349 350 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) 351 { 352 struct mlx4_cqe *cqe, *new_cqe; 353 int i; 354 int cqe_size = cq->buf.entry_size; 355 int cqe_inc = cqe_size == 64 ? 1 : 0; 356 357 i = cq->mcq.cons_index; 358 cqe = get_cqe(cq, i & cq->ibcq.cqe); 359 cqe += cqe_inc; 360 361 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { 362 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, 363 (i + 1) & cq->resize_buf->cqe); 364 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size); 365 new_cqe += cqe_inc; 366 367 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | 368 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); 369 cqe = get_cqe(cq, ++i & cq->ibcq.cqe); 370 cqe += cqe_inc; 371 } 372 ++cq->mcq.cons_index; 373 } 374 375 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) 376 { 377 struct mlx4_ib_dev *dev = to_mdev(ibcq->device); 378 struct mlx4_ib_cq *cq = to_mcq(ibcq); 379 struct mlx4_mtt mtt; 380 int outst_cqe; 381 int err; 382 383 mutex_lock(&cq->resize_mutex); 384 if (entries < 1 || entries > dev->dev->caps.max_cqes) { 385 err = -EINVAL; 386 goto out; 387 } 388 389 entries = roundup_pow_of_two(entries + 1); 390 if (entries == ibcq->cqe + 1) { 391 err = 0; 392 goto out; 393 } 394 395 if (entries > dev->dev->caps.max_cqes + 1) { 396 err = -EINVAL; 397 goto out; 398 } 399 400 if (ibcq->uobject) { 401 err = mlx4_alloc_resize_umem(dev, cq, entries, udata); 402 if (err) 403 goto out; 404 } else { 405 /* Can't be smaller than the number of outstanding CQEs */ 406 outst_cqe = mlx4_ib_get_outstanding_cqes(cq); 407 if (entries < outst_cqe + 1) { 408 err = -EINVAL; 409 goto out; 410 } 411 412 err = mlx4_alloc_resize_buf(dev, cq, entries); 413 if (err) 414 goto out; 415 } 416 417 mtt = cq->buf.mtt; 418 419 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); 420 if (err) 421 goto err_buf; 422 423 mlx4_mtt_cleanup(dev->dev, &mtt); 424 if (ibcq->uobject) { 425 cq->buf = cq->resize_buf->buf; 426 cq->ibcq.cqe = cq->resize_buf->cqe; 427 ib_umem_release(cq->umem); 428 cq->umem = cq->resize_umem; 429 430 kfree(cq->resize_buf); 431 cq->resize_buf = NULL; 432 cq->resize_umem = NULL; 433 } else { 434 struct mlx4_ib_cq_buf tmp_buf; 435 int tmp_cqe = 0; 436 437 spin_lock_irq(&cq->lock); 438 if (cq->resize_buf) { 439 mlx4_ib_cq_resize_copy_cqes(cq); 440 tmp_buf = cq->buf; 441 tmp_cqe = cq->ibcq.cqe; 442 cq->buf = cq->resize_buf->buf; 443 cq->ibcq.cqe = cq->resize_buf->cqe; 444 445 kfree(cq->resize_buf); 446 cq->resize_buf = NULL; 447 } 448 spin_unlock_irq(&cq->lock); 449 450 if (tmp_cqe) 451 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 452 } 453 454 goto out; 455 456 err_buf: 457 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); 458 if (!ibcq->uobject) 459 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, 460 cq->resize_buf->cqe); 461 462 kfree(cq->resize_buf); 463 cq->resize_buf = NULL; 464 465 if (cq->resize_umem) { 466 ib_umem_release(cq->resize_umem); 467 cq->resize_umem = NULL; 468 } 469 470 out: 471 mutex_unlock(&cq->resize_mutex); 472 473 return err; 474 } 475 476 int mlx4_ib_destroy_cq(struct ib_cq *cq) 477 { 478 struct mlx4_ib_dev *dev = to_mdev(cq->device); 479 struct mlx4_ib_cq *mcq = to_mcq(cq); 480 481 mlx4_cq_free(dev->dev, &mcq->mcq); 482 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); 483 484 if (cq->uobject) { 485 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db); 486 ib_umem_release(mcq->umem); 487 } else { 488 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); 489 mlx4_db_free(dev->dev, &mcq->db); 490 } 491 492 kfree(mcq); 493 494 return 0; 495 } 496 497 static void dump_cqe(void *cqe) 498 { 499 __be32 *buf = cqe; 500 501 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", 502 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), 503 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), 504 be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); 505 } 506 507 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, 508 struct ib_wc *wc) 509 { 510 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { 511 pr_debug("local QP operation err " 512 "(QPN %06x, WQE index %x, vendor syndrome %02x, " 513 "opcode = %02x)\n", 514 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), 515 cqe->vendor_err_syndrome, 516 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 517 dump_cqe(cqe); 518 } 519 520 switch (cqe->syndrome) { 521 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: 522 wc->status = IB_WC_LOC_LEN_ERR; 523 break; 524 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: 525 wc->status = IB_WC_LOC_QP_OP_ERR; 526 break; 527 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: 528 wc->status = IB_WC_LOC_PROT_ERR; 529 break; 530 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: 531 wc->status = IB_WC_WR_FLUSH_ERR; 532 break; 533 case MLX4_CQE_SYNDROME_MW_BIND_ERR: 534 wc->status = IB_WC_MW_BIND_ERR; 535 break; 536 case MLX4_CQE_SYNDROME_BAD_RESP_ERR: 537 wc->status = IB_WC_BAD_RESP_ERR; 538 break; 539 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: 540 wc->status = IB_WC_LOC_ACCESS_ERR; 541 break; 542 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: 543 wc->status = IB_WC_REM_INV_REQ_ERR; 544 break; 545 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: 546 wc->status = IB_WC_REM_ACCESS_ERR; 547 break; 548 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: 549 wc->status = IB_WC_REM_OP_ERR; 550 break; 551 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: 552 wc->status = IB_WC_RETRY_EXC_ERR; 553 break; 554 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: 555 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 556 break; 557 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: 558 wc->status = IB_WC_REM_ABORT_ERR; 559 break; 560 default: 561 wc->status = IB_WC_GENERAL_ERR; 562 break; 563 } 564 565 wc->vendor_err = cqe->vendor_err_syndrome; 566 } 567 568 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) 569 { 570 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 571 MLX4_CQE_STATUS_IPV4F | 572 MLX4_CQE_STATUS_IPV4OPT | 573 MLX4_CQE_STATUS_IPV6 | 574 MLX4_CQE_STATUS_IPOK)) == 575 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 576 MLX4_CQE_STATUS_IPOK)) && 577 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | 578 MLX4_CQE_STATUS_TCP)) && 579 checksum == cpu_to_be16(0xffff); 580 } 581 582 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, 583 unsigned tail, struct mlx4_cqe *cqe, int is_eth) 584 { 585 struct mlx4_ib_proxy_sqp_hdr *hdr; 586 587 ib_dma_sync_single_for_cpu(qp->ibqp.device, 588 qp->sqp_proxy_rcv[tail].map, 589 sizeof (struct mlx4_ib_proxy_sqp_hdr), 590 DMA_FROM_DEVICE); 591 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); 592 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); 593 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; 594 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; 595 wc->dlid_path_bits = 0; 596 597 if (is_eth) { 598 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid); 599 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4); 600 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2); 601 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 602 } else { 603 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); 604 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); 605 } 606 } 607 608 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries, 609 struct ib_wc *wc, int *npolled, int is_send) 610 { 611 struct mlx4_ib_wq *wq; 612 unsigned cur; 613 int i; 614 615 wq = is_send ? &qp->sq : &qp->rq; 616 cur = wq->head - wq->tail; 617 618 if (cur == 0) 619 return; 620 621 for (i = 0; i < cur && *npolled < num_entries; i++) { 622 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 623 wc->status = IB_WC_WR_FLUSH_ERR; 624 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR; 625 wq->tail++; 626 (*npolled)++; 627 wc->qp = &qp->ibqp; 628 wc++; 629 } 630 } 631 632 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries, 633 struct ib_wc *wc, int *npolled) 634 { 635 struct mlx4_ib_qp *qp; 636 637 *npolled = 0; 638 /* Find uncompleted WQEs belonging to that cq and retrun 639 * simulated FLUSH_ERR completions 640 */ 641 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) { 642 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1); 643 if (*npolled >= num_entries) 644 goto out; 645 } 646 647 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) { 648 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0); 649 if (*npolled >= num_entries) 650 goto out; 651 } 652 653 out: 654 return; 655 } 656 657 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 658 struct mlx4_ib_qp **cur_qp, 659 struct ib_wc *wc) 660 { 661 struct mlx4_cqe *cqe; 662 struct mlx4_qp *mqp; 663 struct mlx4_ib_wq *wq; 664 struct mlx4_ib_srq *srq; 665 struct mlx4_srq *msrq = NULL; 666 int is_send; 667 int is_error; 668 int is_eth; 669 u32 g_mlpath_rqpn; 670 u16 wqe_ctr; 671 unsigned tail = 0; 672 673 repoll: 674 cqe = next_cqe_sw(cq); 675 if (!cqe) 676 return -EAGAIN; 677 678 if (cq->buf.entry_size == 64) 679 cqe++; 680 681 ++cq->mcq.cons_index; 682 683 /* 684 * Make sure we read CQ entry contents after we've checked the 685 * ownership bit. 686 */ 687 rmb(); 688 689 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; 690 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == 691 MLX4_CQE_OPCODE_ERROR; 692 693 /* Resize CQ in progress */ 694 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { 695 if (cq->resize_buf) { 696 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); 697 698 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 699 cq->buf = cq->resize_buf->buf; 700 cq->ibcq.cqe = cq->resize_buf->cqe; 701 702 kfree(cq->resize_buf); 703 cq->resize_buf = NULL; 704 } 705 706 goto repoll; 707 } 708 709 if (!*cur_qp || 710 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 711 /* 712 * We do not have to take the QP table lock here, 713 * because CQs will be locked while QPs are removed 714 * from the table. 715 */ 716 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 717 be32_to_cpu(cqe->vlan_my_qpn)); 718 *cur_qp = to_mibqp(mqp); 719 } 720 721 wc->qp = &(*cur_qp)->ibqp; 722 723 if (wc->qp->qp_type == IB_QPT_XRC_TGT) { 724 u32 srq_num; 725 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 726 srq_num = g_mlpath_rqpn & 0xffffff; 727 /* SRQ is also in the radix tree */ 728 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev, 729 srq_num); 730 } 731 732 if (is_send) { 733 wq = &(*cur_qp)->sq; 734 if (!(*cur_qp)->sq_signal_bits) { 735 wqe_ctr = be16_to_cpu(cqe->wqe_index); 736 wq->tail += (u16) (wqe_ctr - (u16) wq->tail); 737 } 738 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 739 ++wq->tail; 740 } else if ((*cur_qp)->ibqp.srq) { 741 srq = to_msrq((*cur_qp)->ibqp.srq); 742 wqe_ctr = be16_to_cpu(cqe->wqe_index); 743 wc->wr_id = srq->wrid[wqe_ctr]; 744 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 745 } else if (msrq) { 746 srq = to_mibsrq(msrq); 747 wqe_ctr = be16_to_cpu(cqe->wqe_index); 748 wc->wr_id = srq->wrid[wqe_ctr]; 749 mlx4_ib_free_srq_wqe(srq, wqe_ctr); 750 } else { 751 wq = &(*cur_qp)->rq; 752 tail = wq->tail & (wq->wqe_cnt - 1); 753 wc->wr_id = wq->wrid[tail]; 754 ++wq->tail; 755 } 756 757 if (unlikely(is_error)) { 758 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); 759 return 0; 760 } 761 762 wc->status = IB_WC_SUCCESS; 763 764 if (is_send) { 765 wc->wc_flags = 0; 766 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 767 case MLX4_OPCODE_RDMA_WRITE_IMM: 768 wc->wc_flags |= IB_WC_WITH_IMM; 769 case MLX4_OPCODE_RDMA_WRITE: 770 wc->opcode = IB_WC_RDMA_WRITE; 771 break; 772 case MLX4_OPCODE_SEND_IMM: 773 wc->wc_flags |= IB_WC_WITH_IMM; 774 case MLX4_OPCODE_SEND: 775 case MLX4_OPCODE_SEND_INVAL: 776 wc->opcode = IB_WC_SEND; 777 break; 778 case MLX4_OPCODE_RDMA_READ: 779 wc->opcode = IB_WC_RDMA_READ; 780 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 781 break; 782 case MLX4_OPCODE_ATOMIC_CS: 783 wc->opcode = IB_WC_COMP_SWAP; 784 wc->byte_len = 8; 785 break; 786 case MLX4_OPCODE_ATOMIC_FA: 787 wc->opcode = IB_WC_FETCH_ADD; 788 wc->byte_len = 8; 789 break; 790 case MLX4_OPCODE_MASKED_ATOMIC_CS: 791 wc->opcode = IB_WC_MASKED_COMP_SWAP; 792 wc->byte_len = 8; 793 break; 794 case MLX4_OPCODE_MASKED_ATOMIC_FA: 795 wc->opcode = IB_WC_MASKED_FETCH_ADD; 796 wc->byte_len = 8; 797 break; 798 case MLX4_OPCODE_LSO: 799 wc->opcode = IB_WC_LSO; 800 break; 801 case MLX4_OPCODE_FMR: 802 wc->opcode = IB_WC_REG_MR; 803 break; 804 case MLX4_OPCODE_LOCAL_INVAL: 805 wc->opcode = IB_WC_LOCAL_INV; 806 break; 807 } 808 } else { 809 wc->byte_len = be32_to_cpu(cqe->byte_cnt); 810 811 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { 812 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: 813 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 814 wc->wc_flags = IB_WC_WITH_IMM; 815 wc->ex.imm_data = cqe->immed_rss_invalid; 816 break; 817 case MLX4_RECV_OPCODE_SEND_INVAL: 818 wc->opcode = IB_WC_RECV; 819 wc->wc_flags = IB_WC_WITH_INVALIDATE; 820 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); 821 break; 822 case MLX4_RECV_OPCODE_SEND: 823 wc->opcode = IB_WC_RECV; 824 wc->wc_flags = 0; 825 break; 826 case MLX4_RECV_OPCODE_SEND_IMM: 827 wc->opcode = IB_WC_RECV; 828 wc->wc_flags = IB_WC_WITH_IMM; 829 wc->ex.imm_data = cqe->immed_rss_invalid; 830 break; 831 } 832 833 is_eth = (rdma_port_get_link_layer(wc->qp->device, 834 (*cur_qp)->port) == 835 IB_LINK_LAYER_ETHERNET); 836 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { 837 if ((*cur_qp)->mlx4_ib_qp_type & 838 (MLX4_IB_QPT_PROXY_SMI_OWNER | 839 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 840 use_tunnel_data(*cur_qp, cq, wc, tail, cqe, 841 is_eth); 842 return 0; 843 } 844 } 845 846 wc->slid = be16_to_cpu(cqe->rlid); 847 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 848 wc->src_qp = g_mlpath_rqpn & 0xffffff; 849 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 850 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 851 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 852 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, 853 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; 854 if (is_eth) { 855 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; 856 if (be32_to_cpu(cqe->vlan_my_qpn) & 857 MLX4_CQE_CVLAN_PRESENT_MASK) { 858 wc->vlan_id = be16_to_cpu(cqe->sl_vid) & 859 MLX4_CQE_VID_MASK; 860 } else { 861 wc->vlan_id = 0xffff; 862 } 863 memcpy(wc->smac, cqe->smac, ETH_ALEN); 864 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 865 } else { 866 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; 867 wc->vlan_id = 0xffff; 868 } 869 } 870 871 return 0; 872 } 873 874 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) 875 { 876 struct mlx4_ib_cq *cq = to_mcq(ibcq); 877 struct mlx4_ib_qp *cur_qp = NULL; 878 unsigned long flags; 879 int npolled; 880 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device); 881 882 spin_lock_irqsave(&cq->lock, flags); 883 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 884 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled); 885 goto out; 886 } 887 888 for (npolled = 0; npolled < num_entries; ++npolled) { 889 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled)) 890 break; 891 } 892 893 mlx4_cq_set_ci(&cq->mcq); 894 895 out: 896 spin_unlock_irqrestore(&cq->lock, flags); 897 898 return npolled; 899 } 900 901 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 902 { 903 mlx4_cq_arm(&to_mcq(ibcq)->mcq, 904 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 905 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, 906 to_mdev(ibcq->device)->uar_map, 907 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); 908 909 return 0; 910 } 911 912 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 913 { 914 u32 prod_index; 915 int nfreed = 0; 916 struct mlx4_cqe *cqe, *dest; 917 u8 owner_bit; 918 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0; 919 920 /* 921 * First we need to find the current producer index, so we 922 * know where to start cleaning from. It doesn't matter if HW 923 * adds new entries after this loop -- the QP we're worried 924 * about is already in RESET, so the new entries won't come 925 * from our QP and therefore don't need to be checked. 926 */ 927 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) 928 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) 929 break; 930 931 /* 932 * Now sweep backwards through the CQ, removing CQ entries 933 * that match our QP by copying older entries on top of them. 934 */ 935 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 936 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 937 cqe += cqe_inc; 938 939 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 940 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 941 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 942 ++nfreed; 943 } else if (nfreed) { 944 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); 945 dest += cqe_inc; 946 947 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; 948 memcpy(dest, cqe, sizeof *cqe); 949 dest->owner_sr_opcode = owner_bit | 950 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); 951 } 952 } 953 954 if (nfreed) { 955 cq->mcq.cons_index += nfreed; 956 /* 957 * Make sure update of buffer contents is done before 958 * updating consumer index. 959 */ 960 wmb(); 961 mlx4_cq_set_ci(&cq->mcq); 962 } 963 } 964 965 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) 966 { 967 spin_lock_irq(&cq->lock); 968 __mlx4_ib_cq_clean(cq, qpn, srq); 969 spin_unlock_irq(&cq->lock); 970 } 971