1*44d9e529SMustafa Ismail /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ 2*44d9e529SMustafa Ismail /* Copyright (c) 2017 - 2021 Intel Corporation */ 3*44d9e529SMustafa Ismail #ifndef ICRDMA_HW_H 4*44d9e529SMustafa Ismail #define ICRDMA_HW_H 5*44d9e529SMustafa Ismail 6*44d9e529SMustafa Ismail #include "irdma.h" 7*44d9e529SMustafa Ismail 8*44d9e529SMustafa Ismail #define VFPE_CQPTAIL1 0x0000a000 9*44d9e529SMustafa Ismail #define VFPE_CQPDB1 0x0000bc00 10*44d9e529SMustafa Ismail #define VFPE_CCQPSTATUS1 0x0000b800 11*44d9e529SMustafa Ismail #define VFPE_CCQPHIGH1 0x00009800 12*44d9e529SMustafa Ismail #define VFPE_CCQPLOW1 0x0000ac00 13*44d9e529SMustafa Ismail #define VFPE_CQARM1 0x0000b400 14*44d9e529SMustafa Ismail #define VFPE_CQARM1 0x0000b400 15*44d9e529SMustafa Ismail #define VFPE_CQACK1 0x0000b000 16*44d9e529SMustafa Ismail #define VFPE_AEQALLOC1 0x0000a400 17*44d9e529SMustafa Ismail #define VFPE_CQPERRCODES1 0x00009c00 18*44d9e529SMustafa Ismail #define VFPE_WQEALLOC1 0x0000c000 19*44d9e529SMustafa Ismail #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ 20*44d9e529SMustafa Ismail 21*44d9e529SMustafa Ismail #define PFPE_CQPTAIL 0x00500880 22*44d9e529SMustafa Ismail #define PFPE_CQPDB 0x00500800 23*44d9e529SMustafa Ismail #define PFPE_CCQPSTATUS 0x0050a000 24*44d9e529SMustafa Ismail #define PFPE_CCQPHIGH 0x0050a100 25*44d9e529SMustafa Ismail #define PFPE_CCQPLOW 0x0050a080 26*44d9e529SMustafa Ismail #define PFPE_CQARM 0x00502c00 27*44d9e529SMustafa Ismail #define PFPE_CQACK 0x00502c80 28*44d9e529SMustafa Ismail #define PFPE_AEQALLOC 0x00502d00 29*44d9e529SMustafa Ismail #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ 30*44d9e529SMustafa Ismail #define GLPCI_LBARCTRL 0x0009de74 31*44d9e529SMustafa Ismail #define GLPE_CPUSTATUS0 0x0050ba5c 32*44d9e529SMustafa Ismail #define GLPE_CPUSTATUS1 0x0050ba60 33*44d9e529SMustafa Ismail #define GLPE_CPUSTATUS2 0x0050ba64 34*44d9e529SMustafa Ismail #define PFINT_AEQCTL 0x0016cb00 35*44d9e529SMustafa Ismail #define PFPE_CQPERRCODES 0x0050a200 36*44d9e529SMustafa Ismail #define PFPE_WQEALLOC 0x00504400 37*44d9e529SMustafa Ismail #define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */ 38*44d9e529SMustafa Ismail #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ 39*44d9e529SMustafa Ismail #define PFHMC_PDINV 0x00520300 40*44d9e529SMustafa Ismail #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ 41*44d9e529SMustafa Ismail #define GLPE_CRITERR 0x00534000 42*44d9e529SMustafa Ismail #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 43*44d9e529SMustafa Ismail 44*44d9e529SMustafa Ismail #define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024) 45*44d9e529SMustafa Ismail 46*44d9e529SMustafa Ismail #define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024) 47*44d9e529SMustafa Ismail 48*44d9e529SMustafa Ismail /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */ 49*44d9e529SMustafa Ismail #define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0 50*44d9e529SMustafa Ismail #define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0) 51*44d9e529SMustafa Ismail #define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31 52*44d9e529SMustafa Ismail #define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31) 53*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_STAG_PDID_S 46 54*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46) 55*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_CQ_CEQID_S 22 56*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22) 57*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_CQ_CQID_S 0 58*44d9e529SMustafa Ismail #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0) 59*44d9e529SMustafa Ismail #define ICRDMA_COMMIT_FPM_CQCNT_S 0 60*44d9e529SMustafa Ismail #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0) 61*44d9e529SMustafa Ismail 62*44d9e529SMustafa Ismail enum icrdma_device_caps_const { 63*44d9e529SMustafa Ismail ICRDMA_MAX_STATS_COUNT = 128, 64*44d9e529SMustafa Ismail 65*44d9e529SMustafa Ismail ICRDMA_MAX_IRD_SIZE = 127, 66*44d9e529SMustafa Ismail ICRDMA_MAX_ORD_SIZE = 255, 67*44d9e529SMustafa Ismail 68*44d9e529SMustafa Ismail }; 69*44d9e529SMustafa Ismail 70*44d9e529SMustafa Ismail void icrdma_init_hw(struct irdma_sc_dev *dev); 71*44d9e529SMustafa Ismail #endif /* ICRDMA_HW_H*/ 72