144d9e529SMustafa Ismail // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
244d9e529SMustafa Ismail /* Copyright (c) 2017 - 2021 Intel Corporation */
344d9e529SMustafa Ismail #include "osdep.h"
444d9e529SMustafa Ismail #include "type.h"
544d9e529SMustafa Ismail #include "icrdma_hw.h"
644d9e529SMustafa Ismail
744d9e529SMustafa Ismail static u32 icrdma_regs[IRDMA_MAX_REGS] = {
844d9e529SMustafa Ismail PFPE_CQPTAIL,
944d9e529SMustafa Ismail PFPE_CQPDB,
1044d9e529SMustafa Ismail PFPE_CCQPSTATUS,
1144d9e529SMustafa Ismail PFPE_CCQPHIGH,
1244d9e529SMustafa Ismail PFPE_CCQPLOW,
1344d9e529SMustafa Ismail PFPE_CQARM,
1444d9e529SMustafa Ismail PFPE_CQACK,
1544d9e529SMustafa Ismail PFPE_AEQALLOC,
1644d9e529SMustafa Ismail PFPE_CQPERRCODES,
1744d9e529SMustafa Ismail PFPE_WQEALLOC,
1844d9e529SMustafa Ismail GLINT_DYN_CTL(0),
1944d9e529SMustafa Ismail ICRDMA_DB_ADDR_OFFSET,
2044d9e529SMustafa Ismail
2144d9e529SMustafa Ismail GLPCI_LBARCTRL,
2244d9e529SMustafa Ismail GLPE_CPUSTATUS0,
2344d9e529SMustafa Ismail GLPE_CPUSTATUS1,
2444d9e529SMustafa Ismail GLPE_CPUSTATUS2,
2544d9e529SMustafa Ismail PFINT_AEQCTL,
2644d9e529SMustafa Ismail GLINT_CEQCTL(0),
2744d9e529SMustafa Ismail VSIQF_PE_CTL1(0),
2844d9e529SMustafa Ismail PFHMC_PDINV,
2944d9e529SMustafa Ismail GLHMC_VFPDINV(0),
3044d9e529SMustafa Ismail GLPE_CRITERR,
3144d9e529SMustafa Ismail GLINT_RATE(0),
3244d9e529SMustafa Ismail };
3344d9e529SMustafa Ismail
3444d9e529SMustafa Ismail static u64 icrdma_masks[IRDMA_MAX_MASKS] = {
3544d9e529SMustafa Ismail ICRDMA_CCQPSTATUS_CCQP_DONE,
3644d9e529SMustafa Ismail ICRDMA_CCQPSTATUS_CCQP_ERR,
3744d9e529SMustafa Ismail ICRDMA_CQPSQ_STAG_PDID,
3844d9e529SMustafa Ismail ICRDMA_CQPSQ_CQ_CEQID,
3944d9e529SMustafa Ismail ICRDMA_CQPSQ_CQ_CQID,
4044d9e529SMustafa Ismail ICRDMA_COMMIT_FPM_CQCNT,
4144d9e529SMustafa Ismail };
4244d9e529SMustafa Ismail
4344d9e529SMustafa Ismail static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
4444d9e529SMustafa Ismail ICRDMA_CCQPSTATUS_CCQP_DONE_S,
4544d9e529SMustafa Ismail ICRDMA_CCQPSTATUS_CCQP_ERR_S,
4644d9e529SMustafa Ismail ICRDMA_CQPSQ_STAG_PDID_S,
4744d9e529SMustafa Ismail ICRDMA_CQPSQ_CQ_CEQID_S,
4844d9e529SMustafa Ismail ICRDMA_CQPSQ_CQ_CQID_S,
4944d9e529SMustafa Ismail ICRDMA_COMMIT_FPM_CQCNT_S,
5044d9e529SMustafa Ismail };
5144d9e529SMustafa Ismail
5244d9e529SMustafa Ismail /**
5344d9e529SMustafa Ismail * icrdma_ena_irq - Enable interrupt
5444d9e529SMustafa Ismail * @dev: pointer to the device structure
5544d9e529SMustafa Ismail * @idx: vector index
5644d9e529SMustafa Ismail */
icrdma_ena_irq(struct irdma_sc_dev * dev,u32 idx)5744d9e529SMustafa Ismail static void icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx)
5844d9e529SMustafa Ismail {
5944d9e529SMustafa Ismail u32 val;
6044d9e529SMustafa Ismail u32 interval = 0;
6144d9e529SMustafa Ismail
6244d9e529SMustafa Ismail if (dev->ceq_itr && dev->aeq->msix_idx != idx)
6344d9e529SMustafa Ismail interval = dev->ceq_itr >> 1; /* 2 usec units */
6444d9e529SMustafa Ismail val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0) |
6544d9e529SMustafa Ismail FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTERVAL, interval) |
6644d9e529SMustafa Ismail FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 1) |
6744d9e529SMustafa Ismail FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 1);
6844d9e529SMustafa Ismail
6944d9e529SMustafa Ismail if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
7044d9e529SMustafa Ismail writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
7144d9e529SMustafa Ismail else
7244d9e529SMustafa Ismail writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
7344d9e529SMustafa Ismail }
7444d9e529SMustafa Ismail
7544d9e529SMustafa Ismail /**
7644d9e529SMustafa Ismail * icrdma_disable_irq - Disable interrupt
7744d9e529SMustafa Ismail * @dev: pointer to the device structure
7844d9e529SMustafa Ismail * @idx: vector index
7944d9e529SMustafa Ismail */
icrdma_disable_irq(struct irdma_sc_dev * dev,u32 idx)8044d9e529SMustafa Ismail static void icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx)
8144d9e529SMustafa Ismail {
8244d9e529SMustafa Ismail if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1)
8344d9e529SMustafa Ismail writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
8444d9e529SMustafa Ismail else
8544d9e529SMustafa Ismail writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
8644d9e529SMustafa Ismail }
8744d9e529SMustafa Ismail
8844d9e529SMustafa Ismail /**
8944d9e529SMustafa Ismail * icrdma_cfg_ceq- Configure CEQ interrupt
9044d9e529SMustafa Ismail * @dev: pointer to the device structure
9144d9e529SMustafa Ismail * @ceq_id: Completion Event Queue ID
9244d9e529SMustafa Ismail * @idx: vector index
9344d9e529SMustafa Ismail * @enable: True to enable, False disables
9444d9e529SMustafa Ismail */
icrdma_cfg_ceq(struct irdma_sc_dev * dev,u32 ceq_id,u32 idx,bool enable)9544d9e529SMustafa Ismail static void icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
9644d9e529SMustafa Ismail bool enable)
9744d9e529SMustafa Ismail {
9844d9e529SMustafa Ismail u32 reg_val;
9944d9e529SMustafa Ismail
10044d9e529SMustafa Ismail reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
10144d9e529SMustafa Ismail FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) |
10244d9e529SMustafa Ismail FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 3);
10344d9e529SMustafa Ismail
10444d9e529SMustafa Ismail writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
10544d9e529SMustafa Ismail }
10644d9e529SMustafa Ismail
10744d9e529SMustafa Ismail static const struct irdma_irq_ops icrdma_irq_ops = {
10844d9e529SMustafa Ismail .irdma_cfg_aeq = irdma_cfg_aeq,
10944d9e529SMustafa Ismail .irdma_cfg_ceq = icrdma_cfg_ceq,
11044d9e529SMustafa Ismail .irdma_dis_irq = icrdma_disable_irq,
11144d9e529SMustafa Ismail .irdma_en_irq = icrdma_ena_irq,
11244d9e529SMustafa Ismail };
11344d9e529SMustafa Ismail
1145a711e58SKrzysztof Czurylo static const struct irdma_hw_stat_map icrdma_hw_stat_map[] = {
1155a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RXVLANERR] = { 0, 32, IRDMA_MAX_STATS_24 },
1165a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = { 8, 0, IRDMA_MAX_STATS_48 },
1175a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = { 16, 0, IRDMA_MAX_STATS_48 },
1185a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = { 24, 32, IRDMA_MAX_STATS_32 },
1195a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = { 24, 0, IRDMA_MAX_STATS_32 },
1205a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = { 32, 0, IRDMA_MAX_STATS_48 },
1215a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = { 40, 0, IRDMA_MAX_STATS_48 },
1225a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = { 48, 0, IRDMA_MAX_STATS_48 },
1235a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = { 56, 0, IRDMA_MAX_STATS_48 },
1245a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = { 64, 0, IRDMA_MAX_STATS_48 },
1255a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = { 72, 32, IRDMA_MAX_STATS_32 },
1265a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = { 72, 0, IRDMA_MAX_STATS_32 },
1275a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = { 80, 0, IRDMA_MAX_STATS_48 },
1285a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = { 88, 0, IRDMA_MAX_STATS_48 },
1295a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = { 96, 0, IRDMA_MAX_STATS_48 },
1305a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = { 104, 0, IRDMA_MAX_STATS_48 },
1315a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = { 112, 0, IRDMA_MAX_STATS_48 },
1325a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = { 120, 0, IRDMA_MAX_STATS_48 },
1335a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = { 128, 0, IRDMA_MAX_STATS_48 },
1345a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = { 136, 0, IRDMA_MAX_STATS_48 },
1355a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = { 144, 0, IRDMA_MAX_STATS_48 },
1365a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = { 152, 0, IRDMA_MAX_STATS_48 },
1375a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = { 160, 0, IRDMA_MAX_STATS_48 },
1385a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = { 168, 0, IRDMA_MAX_STATS_48 },
1395a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = { 176, 0, IRDMA_MAX_STATS_48 },
1405a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = { 184, 32, IRDMA_MAX_STATS_24 },
1415a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = { 184, 0, IRDMA_MAX_STATS_24 },
1425a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = { 192, 32, IRDMA_MAX_STATS_48 },
1435a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = { 200, 32, IRDMA_MAX_STATS_24 },
1445a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = { 200, 0, IRDMA_MAX_STATS_24 },
1455a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TCPTXSEG] = { 208, 0, IRDMA_MAX_STATS_48 },
1465a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = { 216, 32, IRDMA_MAX_STATS_32 },
1475a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = { 224, 0, IRDMA_MAX_STATS_48 },
1485a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = { 232, 0, IRDMA_MAX_STATS_48 },
1495a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMARXWRS] = { 240, 0, IRDMA_MAX_STATS_48 },
1505a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMARXRDS] = { 248, 0, IRDMA_MAX_STATS_48 },
1515a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = { 256, 0, IRDMA_MAX_STATS_48 },
1525a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMATXWRS] = { 264, 0, IRDMA_MAX_STATS_48 },
1535a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMATXRDS] = { 272, 0, IRDMA_MAX_STATS_48 },
1545a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = { 280, 0, IRDMA_MAX_STATS_48 },
1555a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMAVBND] = { 288, 0, IRDMA_MAX_STATS_48 },
1565a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RDMAVINV] = { 296, 0, IRDMA_MAX_STATS_48 },
1575a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = { 304, 0, IRDMA_MAX_STATS_56 },
1585a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = { 312, 32, IRDMA_MAX_STATS_24 },
1595a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = { 312, 0, IRDMA_MAX_STATS_32 },
1605a711e58SKrzysztof Czurylo [IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = { 320, 0, IRDMA_MAX_STATS_32 },
1615a711e58SKrzysztof Czurylo };
1625a711e58SKrzysztof Czurylo
icrdma_init_hw(struct irdma_sc_dev * dev)16344d9e529SMustafa Ismail void icrdma_init_hw(struct irdma_sc_dev *dev)
16444d9e529SMustafa Ismail {
16544d9e529SMustafa Ismail int i;
16644d9e529SMustafa Ismail u8 __iomem *hw_addr;
16744d9e529SMustafa Ismail
16844d9e529SMustafa Ismail for (i = 0; i < IRDMA_MAX_REGS; ++i) {
16944d9e529SMustafa Ismail hw_addr = dev->hw->hw_addr;
17044d9e529SMustafa Ismail
17144d9e529SMustafa Ismail if (i == IRDMA_DB_ADDR_OFFSET)
17244d9e529SMustafa Ismail hw_addr = NULL;
17344d9e529SMustafa Ismail
17444d9e529SMustafa Ismail dev->hw_regs[i] = (u32 __iomem *)(hw_addr + icrdma_regs[i]);
17544d9e529SMustafa Ismail }
17644d9e529SMustafa Ismail dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID;
17744d9e529SMustafa Ismail dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID;
17844d9e529SMustafa Ismail
17944d9e529SMustafa Ismail for (i = 0; i < IRDMA_MAX_SHIFTS; ++i)
18044d9e529SMustafa Ismail dev->hw_shifts[i] = icrdma_shifts[i];
18144d9e529SMustafa Ismail
18244d9e529SMustafa Ismail for (i = 0; i < IRDMA_MAX_MASKS; ++i)
18344d9e529SMustafa Ismail dev->hw_masks[i] = icrdma_masks[i];
18444d9e529SMustafa Ismail
18544d9e529SMustafa Ismail dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
18644d9e529SMustafa Ismail dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
18744d9e529SMustafa Ismail dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
18844d9e529SMustafa Ismail dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
18944d9e529SMustafa Ismail dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
19044d9e529SMustafa Ismail dev->irq_ops = &icrdma_irq_ops;
1915e8afb87SMustafa Ismail dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;
1925a711e58SKrzysztof Czurylo dev->hw_stats_map = icrdma_hw_stat_map;
19344d9e529SMustafa Ismail dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE;
19444d9e529SMustafa Ismail dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
19544d9e529SMustafa Ismail dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
1965a711e58SKrzysztof Czurylo dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_2;
19744d9e529SMustafa Ismail
198*72d422c2SSindhu Devale dev->hw_attrs.uk_attrs.min_hw_wq_size = ICRDMA_MIN_WQ_SIZE;
19944d9e529SMustafa Ismail dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
20044d9e529SMustafa Ismail dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |
20144d9e529SMustafa Ismail IRDMA_FEATURE_CQ_RESIZE;
20244d9e529SMustafa Ismail }
203