1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "osdep.h" 4 #include "type.h" 5 #include "i40iw_hw.h" 6 #include "status.h" 7 #include "protos.h" 8 9 static u32 i40iw_regs[IRDMA_MAX_REGS] = { 10 I40E_PFPE_CQPTAIL, 11 I40E_PFPE_CQPDB, 12 I40E_PFPE_CCQPSTATUS, 13 I40E_PFPE_CCQPHIGH, 14 I40E_PFPE_CCQPLOW, 15 I40E_PFPE_CQARM, 16 I40E_PFPE_CQACK, 17 I40E_PFPE_AEQALLOC, 18 I40E_PFPE_CQPERRCODES, 19 I40E_PFPE_WQEALLOC, 20 I40E_PFINT_DYN_CTLN(0), 21 I40IW_DB_ADDR_OFFSET, 22 23 I40E_GLPCI_LBARCTRL, 24 I40E_GLPE_CPUSTATUS0, 25 I40E_GLPE_CPUSTATUS1, 26 I40E_GLPE_CPUSTATUS2, 27 I40E_PFINT_AEQCTL, 28 I40E_PFINT_CEQCTL(0), 29 I40E_VSIQF_CTL(0), 30 I40E_PFHMC_PDINV, 31 I40E_GLHMC_VFPDINV(0), 32 I40E_GLPE_CRITERR, 33 0xffffffff /* PFINT_RATEN not used in FPK */ 34 }; 35 36 static u32 i40iw_stat_offsets_32[IRDMA_HW_STAT_INDEX_MAX_32] = { 37 I40E_GLPES_PFIP4RXDISCARD(0), 38 I40E_GLPES_PFIP4RXTRUNC(0), 39 I40E_GLPES_PFIP4TXNOROUTE(0), 40 I40E_GLPES_PFIP6RXDISCARD(0), 41 I40E_GLPES_PFIP6RXTRUNC(0), 42 I40E_GLPES_PFIP6TXNOROUTE(0), 43 I40E_GLPES_PFTCPRTXSEG(0), 44 I40E_GLPES_PFTCPRXOPTERR(0), 45 I40E_GLPES_PFTCPRXPROTOERR(0), 46 I40E_GLPES_PFRXVLANERR(0) 47 }; 48 49 static u32 i40iw_stat_offsets_64[IRDMA_HW_STAT_INDEX_MAX_64] = { 50 I40E_GLPES_PFIP4RXOCTSLO(0), 51 I40E_GLPES_PFIP4RXPKTSLO(0), 52 I40E_GLPES_PFIP4RXFRAGSLO(0), 53 I40E_GLPES_PFIP4RXMCPKTSLO(0), 54 I40E_GLPES_PFIP4TXOCTSLO(0), 55 I40E_GLPES_PFIP4TXPKTSLO(0), 56 I40E_GLPES_PFIP4TXFRAGSLO(0), 57 I40E_GLPES_PFIP4TXMCPKTSLO(0), 58 I40E_GLPES_PFIP6RXOCTSLO(0), 59 I40E_GLPES_PFIP6RXPKTSLO(0), 60 I40E_GLPES_PFIP6RXFRAGSLO(0), 61 I40E_GLPES_PFIP6RXMCPKTSLO(0), 62 I40E_GLPES_PFIP6TXOCTSLO(0), 63 I40E_GLPES_PFIP6TXPKTSLO(0), 64 I40E_GLPES_PFIP6TXFRAGSLO(0), 65 I40E_GLPES_PFIP6TXMCPKTSLO(0), 66 I40E_GLPES_PFTCPRXSEGSLO(0), 67 I40E_GLPES_PFTCPTXSEGLO(0), 68 I40E_GLPES_PFRDMARXRDSLO(0), 69 I40E_GLPES_PFRDMARXSNDSLO(0), 70 I40E_GLPES_PFRDMARXWRSLO(0), 71 I40E_GLPES_PFRDMATXRDSLO(0), 72 I40E_GLPES_PFRDMATXSNDSLO(0), 73 I40E_GLPES_PFRDMATXWRSLO(0), 74 I40E_GLPES_PFRDMAVBNDLO(0), 75 I40E_GLPES_PFRDMAVINVLO(0), 76 I40E_GLPES_PFIP4RXMCOCTSLO(0), 77 I40E_GLPES_PFIP4TXMCOCTSLO(0), 78 I40E_GLPES_PFIP6RXMCOCTSLO(0), 79 I40E_GLPES_PFIP6TXMCOCTSLO(0), 80 I40E_GLPES_PFUDPRXPKTSLO(0), 81 I40E_GLPES_PFUDPTXPKTSLO(0) 82 }; 83 84 static u64 i40iw_masks[IRDMA_MAX_MASKS] = { 85 I40E_PFPE_CCQPSTATUS_CCQP_DONE, 86 I40E_PFPE_CCQPSTATUS_CCQP_ERR, 87 I40E_CQPSQ_STAG_PDID, 88 I40E_CQPSQ_CQ_CEQID, 89 I40E_CQPSQ_CQ_CQID, 90 I40E_COMMIT_FPM_CQCNT, 91 }; 92 93 static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = { 94 I40E_PFPE_CCQPSTATUS_CCQP_DONE_S, 95 I40E_PFPE_CCQPSTATUS_CCQP_ERR_S, 96 I40E_CQPSQ_STAG_PDID_S, 97 I40E_CQPSQ_CQ_CEQID_S, 98 I40E_CQPSQ_CQ_CQID_S, 99 I40E_COMMIT_FPM_CQCNT_S, 100 }; 101 102 /** 103 * i40iw_config_ceq- Configure CEQ interrupt 104 * @dev: pointer to the device structure 105 * @ceq_id: Completion Event Queue ID 106 * @idx: vector index 107 * @enable: Enable CEQ interrupt when true 108 */ 109 static void i40iw_config_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx, 110 bool enable) 111 { 112 u32 reg_val; 113 114 reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) | 115 FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_TYPE, QUEUE_TYPE_CEQ); 116 wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val); 117 118 reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, 0x3) | 119 FIELD_PREP(I40E_PFINT_DYN_CTLN_INTENA, 0x1); 120 wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val); 121 122 reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) | 123 FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) | 124 FIELD_PREP(I40E_PFINT_CEQCTL_NEXTQ_INDX, NULL_QUEUE_INDEX) | 125 FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, 0x3); 126 127 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val); 128 } 129 130 /** 131 * i40iw_ena_irq - Enable interrupt 132 * @dev: pointer to the device structure 133 * @idx: vector index 134 */ 135 static void i40iw_ena_irq(struct irdma_sc_dev *dev, u32 idx) 136 { 137 u32 val; 138 139 val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 0x1) | 140 FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 0x1) | 141 FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, 0x3); 142 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), val); 143 } 144 145 /** 146 * i40iw_disable_irq - Disable interrupt 147 * @dev: pointer to the device structure 148 * @idx: vector index 149 */ 150 static void i40iw_disable_irq(struct irdma_sc_dev *dev, u32 idx) 151 { 152 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), 0); 153 } 154 155 static const struct irdma_irq_ops i40iw_irq_ops = { 156 .irdma_cfg_aeq = irdma_cfg_aeq, 157 .irdma_cfg_ceq = i40iw_config_ceq, 158 .irdma_dis_irq = i40iw_disable_irq, 159 .irdma_en_irq = i40iw_ena_irq, 160 }; 161 162 void i40iw_init_hw(struct irdma_sc_dev *dev) 163 { 164 int i; 165 u8 __iomem *hw_addr; 166 167 for (i = 0; i < IRDMA_MAX_REGS; ++i) { 168 hw_addr = dev->hw->hw_addr; 169 170 if (i == IRDMA_DB_ADDR_OFFSET) 171 hw_addr = NULL; 172 173 dev->hw_regs[i] = (u32 __iomem *)(i40iw_regs[i] + hw_addr); 174 } 175 176 for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_32; ++i) 177 dev->hw_stats_regs_32[i] = i40iw_stat_offsets_32[i]; 178 179 for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_64; ++i) 180 dev->hw_stats_regs_64[i] = i40iw_stat_offsets_64[i]; 181 182 dev->hw_attrs.first_hw_vf_fpm_id = I40IW_FIRST_VF_FPM_ID; 183 dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID; 184 185 for (i = 0; i < IRDMA_MAX_SHIFTS; ++i) 186 dev->hw_shifts[i] = i40iw_shifts[i]; 187 188 for (i = 0; i < IRDMA_MAX_MASKS; ++i) 189 dev->hw_masks[i] = i40iw_masks[i]; 190 191 dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC]; 192 dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM]; 193 dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC]; 194 dev->cqp_db = dev->hw_regs[IRDMA_CQPDB]; 195 dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; 196 dev->ceq_itr_mask_db = NULL; 197 dev->aeq_itr_mask_db = NULL; 198 dev->irq_ops = &i40iw_irq_ops; 199 200 /* Setup the hardware limits, hmc may limit further */ 201 dev->hw_attrs.uk_attrs.max_hw_wq_frags = I40IW_MAX_WQ_FRAGMENT_COUNT; 202 dev->hw_attrs.uk_attrs.max_hw_read_sges = I40IW_MAX_SGE_RD; 203 dev->hw_attrs.max_hw_device_pages = I40IW_MAX_PUSH_PAGE_COUNT; 204 dev->hw_attrs.uk_attrs.max_hw_inline = I40IW_MAX_INLINE_DATA_SIZE; 205 dev->hw_attrs.max_hw_ird = I40IW_MAX_IRD_SIZE; 206 dev->hw_attrs.max_hw_ord = I40IW_MAX_ORD_SIZE; 207 dev->hw_attrs.max_hw_wqes = I40IW_MAX_WQ_ENTRIES; 208 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = I40IW_QP_SW_MAX_RQ_QUANTA; 209 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = I40IW_QP_SW_MAX_WQ_QUANTA; 210 dev->hw_attrs.uk_attrs.max_hw_sq_chunk = I40IW_MAX_QUANTA_PER_WR; 211 dev->hw_attrs.max_hw_pds = I40IW_MAX_PDS; 212 dev->hw_attrs.max_stat_inst = I40IW_MAX_STATS_COUNT; 213 dev->hw_attrs.max_hw_outbound_msg_size = I40IW_MAX_OUTBOUND_MSG_SIZE; 214 dev->hw_attrs.max_hw_inbound_msg_size = I40IW_MAX_INBOUND_MSG_SIZE; 215 dev->hw_attrs.max_qp_wr = I40IW_MAX_QP_WRS; 216 } 217