1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "main.h" 4 5 static struct irdma_rsrc_limits rsrc_limits_table[] = { 6 [0] = { 7 .qplimit = SZ_128, 8 }, 9 [1] = { 10 .qplimit = SZ_1K, 11 }, 12 [2] = { 13 .qplimit = SZ_2K, 14 }, 15 [3] = { 16 .qplimit = SZ_4K, 17 }, 18 [4] = { 19 .qplimit = SZ_16K, 20 }, 21 [5] = { 22 .qplimit = SZ_64K, 23 }, 24 [6] = { 25 .qplimit = SZ_128K, 26 }, 27 [7] = { 28 .qplimit = SZ_256K, 29 }, 30 }; 31 32 /* types of hmc objects */ 33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 34 IRDMA_HMC_IW_QP, 35 IRDMA_HMC_IW_CQ, 36 IRDMA_HMC_IW_HTE, 37 IRDMA_HMC_IW_ARP, 38 IRDMA_HMC_IW_APBVT_ENTRY, 39 IRDMA_HMC_IW_MR, 40 IRDMA_HMC_IW_XF, 41 IRDMA_HMC_IW_XFFL, 42 IRDMA_HMC_IW_Q1, 43 IRDMA_HMC_IW_Q1FL, 44 IRDMA_HMC_IW_TIMER, 45 IRDMA_HMC_IW_FSIMC, 46 IRDMA_HMC_IW_FSIAV, 47 IRDMA_HMC_IW_RRF, 48 IRDMA_HMC_IW_RRFFL, 49 IRDMA_HMC_IW_HDR, 50 IRDMA_HMC_IW_MD, 51 IRDMA_HMC_IW_OOISC, 52 IRDMA_HMC_IW_OOISCFFL, 53 }; 54 55 /** 56 * irdma_iwarp_ce_handler - handle iwarp completions 57 * @iwcq: iwarp cq receiving event 58 */ 59 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 60 { 61 struct irdma_cq *cq = iwcq->back_cq; 62 63 if (!cq->user_mode) 64 atomic_set(&cq->armed, 0); 65 if (cq->ibcq.comp_handler) 66 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 67 } 68 69 /** 70 * irdma_puda_ce_handler - handle puda completion events 71 * @rf: RDMA PCI function 72 * @cq: puda completion q for event 73 */ 74 static void irdma_puda_ce_handler(struct irdma_pci_f *rf, 75 struct irdma_sc_cq *cq) 76 { 77 struct irdma_sc_dev *dev = &rf->sc_dev; 78 u32 compl_error; 79 int status; 80 81 do { 82 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 83 if (status == -ENOENT) 84 break; 85 if (status) { 86 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); 87 break; 88 } 89 if (compl_error) { 90 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n", 91 compl_error); 92 break; 93 } 94 } while (1); 95 96 irdma_sc_ccq_arm(cq); 97 } 98 99 /** 100 * irdma_process_ceq - handle ceq for completions 101 * @rf: RDMA PCI function 102 * @ceq: ceq having cq for completion 103 */ 104 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 105 { 106 struct irdma_sc_dev *dev = &rf->sc_dev; 107 struct irdma_sc_ceq *sc_ceq; 108 struct irdma_sc_cq *cq; 109 unsigned long flags; 110 111 sc_ceq = &ceq->sc_ceq; 112 do { 113 spin_lock_irqsave(&ceq->ce_lock, flags); 114 cq = irdma_sc_process_ceq(dev, sc_ceq); 115 if (!cq) { 116 spin_unlock_irqrestore(&ceq->ce_lock, flags); 117 break; 118 } 119 120 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 121 irdma_iwarp_ce_handler(cq); 122 123 spin_unlock_irqrestore(&ceq->ce_lock, flags); 124 125 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 126 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 127 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 128 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 129 irdma_puda_ce_handler(rf, cq); 130 } while (1); 131 } 132 133 static void irdma_set_flush_fields(struct irdma_sc_qp *qp, 134 struct irdma_aeqe_info *info) 135 { 136 qp->sq_flush_code = info->sq; 137 qp->rq_flush_code = info->rq; 138 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 139 140 switch (info->ae_id) { 141 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 142 case IRDMA_AE_AMP_INVALID_STAG: 143 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 144 case IRDMA_AE_AMP_UNALLOCATED_STAG: 145 case IRDMA_AE_AMP_BAD_PD: 146 case IRDMA_AE_AMP_BAD_QP: 147 case IRDMA_AE_AMP_BAD_STAG_KEY: 148 case IRDMA_AE_AMP_BAD_STAG_INDEX: 149 case IRDMA_AE_AMP_TO_WRAP: 150 case IRDMA_AE_PRIV_OPERATION_DENIED: 151 qp->flush_code = FLUSH_PROT_ERR; 152 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 153 break; 154 case IRDMA_AE_UDA_XMIT_BAD_PD: 155 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 156 qp->flush_code = FLUSH_LOC_QP_OP_ERR; 157 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 158 break; 159 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 160 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 161 case IRDMA_AE_UDA_L4LEN_INVALID: 162 case IRDMA_AE_DDP_UBE_INVALID_MO: 163 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 164 qp->flush_code = FLUSH_LOC_LEN_ERR; 165 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 166 break; 167 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 168 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 169 qp->flush_code = FLUSH_REM_ACCESS_ERR; 170 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 171 break; 172 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 173 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 174 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 175 case IRDMA_AE_IB_REMOTE_OP_ERROR: 176 qp->flush_code = FLUSH_REM_OP_ERR; 177 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 178 break; 179 case IRDMA_AE_LCE_QP_CATASTROPHIC: 180 qp->flush_code = FLUSH_FATAL_ERR; 181 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 182 break; 183 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 184 qp->flush_code = FLUSH_GENERAL_ERR; 185 break; 186 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 187 qp->flush_code = FLUSH_RETRY_EXC_ERR; 188 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 189 break; 190 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 191 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 192 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 193 qp->flush_code = FLUSH_MW_BIND_ERR; 194 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 195 break; 196 case IRDMA_AE_IB_INVALID_REQUEST: 197 qp->flush_code = FLUSH_REM_INV_REQ_ERR; 198 qp->event_type = IRDMA_QP_EVENT_REQ_ERR; 199 break; 200 default: 201 qp->flush_code = FLUSH_GENERAL_ERR; 202 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 203 break; 204 } 205 } 206 207 /** 208 * irdma_process_aeq - handle aeq events 209 * @rf: RDMA PCI function 210 */ 211 static void irdma_process_aeq(struct irdma_pci_f *rf) 212 { 213 struct irdma_sc_dev *dev = &rf->sc_dev; 214 struct irdma_aeq *aeq = &rf->aeq; 215 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 216 struct irdma_aeqe_info aeinfo; 217 struct irdma_aeqe_info *info = &aeinfo; 218 int ret; 219 struct irdma_qp *iwqp = NULL; 220 struct irdma_sc_cq *cq = NULL; 221 struct irdma_cq *iwcq = NULL; 222 struct irdma_sc_qp *qp = NULL; 223 struct irdma_qp_host_ctx_info *ctx_info = NULL; 224 struct irdma_device *iwdev = rf->iwdev; 225 unsigned long flags; 226 227 u32 aeqcnt = 0; 228 229 if (!sc_aeq->size) 230 return; 231 232 do { 233 memset(info, 0, sizeof(*info)); 234 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 235 if (ret) 236 break; 237 238 aeqcnt++; 239 ibdev_dbg(&iwdev->ibdev, 240 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 241 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 242 info->iwarp_state, info->ae_src); 243 244 if (info->qp) { 245 spin_lock_irqsave(&rf->qptable_lock, flags); 246 iwqp = rf->qp_table[info->qp_cq_id]; 247 if (!iwqp) { 248 spin_unlock_irqrestore(&rf->qptable_lock, 249 flags); 250 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 251 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 252 wake_up(&iwdev->suspend_wq); 253 continue; 254 } 255 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", 256 info->qp_cq_id); 257 continue; 258 } 259 irdma_qp_add_ref(&iwqp->ibqp); 260 spin_unlock_irqrestore(&rf->qptable_lock, flags); 261 qp = &iwqp->sc_qp; 262 spin_lock_irqsave(&iwqp->lock, flags); 263 iwqp->hw_tcp_state = info->tcp_state; 264 iwqp->hw_iwarp_state = info->iwarp_state; 265 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 266 iwqp->last_aeq = info->ae_id; 267 spin_unlock_irqrestore(&iwqp->lock, flags); 268 ctx_info = &iwqp->ctx_info; 269 } else { 270 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 271 continue; 272 } 273 274 switch (info->ae_id) { 275 struct irdma_cm_node *cm_node; 276 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 277 cm_node = iwqp->cm_node; 278 if (cm_node->accept_pend) { 279 atomic_dec(&cm_node->listener->pend_accepts_cnt); 280 cm_node->accept_pend = 0; 281 } 282 iwqp->rts_ae_rcvd = 1; 283 wake_up_interruptible(&iwqp->waitq); 284 break; 285 case IRDMA_AE_LLP_FIN_RECEIVED: 286 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 287 if (qp->term_flags) 288 break; 289 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 290 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 291 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT && 292 iwqp->ibqp_state == IB_QPS_RTS) { 293 irdma_next_iw_state(iwqp, 294 IRDMA_QP_STATE_CLOSING, 295 0, 0, 0); 296 irdma_cm_disconn(iwqp); 297 } 298 irdma_schedule_cm_timer(iwqp->cm_node, 299 (struct irdma_puda_buf *)iwqp, 300 IRDMA_TIMER_TYPE_CLOSE, 301 1, 0); 302 } 303 break; 304 case IRDMA_AE_LLP_CLOSE_COMPLETE: 305 if (qp->term_flags) 306 irdma_terminate_done(qp, 0); 307 else 308 irdma_cm_disconn(iwqp); 309 break; 310 case IRDMA_AE_BAD_CLOSE: 311 case IRDMA_AE_RESET_SENT: 312 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 313 0); 314 irdma_cm_disconn(iwqp); 315 break; 316 case IRDMA_AE_LLP_CONNECTION_RESET: 317 if (atomic_read(&iwqp->close_timer_started)) 318 break; 319 irdma_cm_disconn(iwqp); 320 break; 321 case IRDMA_AE_QP_SUSPEND_COMPLETE: 322 if (iwqp->iwdev->vsi.tc_change_pending) { 323 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 324 wake_up(&iwqp->iwdev->suspend_wq); 325 } 326 break; 327 case IRDMA_AE_TERMINATE_SENT: 328 irdma_terminate_send_fin(qp); 329 break; 330 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 331 irdma_terminate_received(qp, info); 332 break; 333 case IRDMA_AE_CQ_OPERATION_ERROR: 334 ibdev_err(&iwdev->ibdev, 335 "Processing an iWARP related AE for CQ misc = 0x%04X\n", 336 info->ae_id); 337 cq = (struct irdma_sc_cq *)(unsigned long) 338 info->compl_ctx; 339 340 iwcq = cq->back_cq; 341 342 if (iwcq->ibcq.event_handler) { 343 struct ib_event ibevent; 344 345 ibevent.device = iwcq->ibcq.device; 346 ibevent.event = IB_EVENT_CQ_ERR; 347 ibevent.element.cq = &iwcq->ibcq; 348 iwcq->ibcq.event_handler(&ibevent, 349 iwcq->ibcq.cq_context); 350 } 351 break; 352 case IRDMA_AE_RESET_NOT_SENT: 353 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 354 case IRDMA_AE_RESOURCE_EXHAUSTION: 355 break; 356 case IRDMA_AE_PRIV_OPERATION_DENIED: 357 case IRDMA_AE_STAG_ZERO_INVALID: 358 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 359 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 360 case IRDMA_AE_DDP_UBE_INVALID_MO: 361 case IRDMA_AE_DDP_UBE_INVALID_QN: 362 case IRDMA_AE_DDP_NO_L_BIT: 363 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 364 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 365 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 366 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 367 case IRDMA_AE_INVALID_ARP_ENTRY: 368 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 369 case IRDMA_AE_STALE_ARP_ENTRY: 370 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 371 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 372 case IRDMA_AE_LLP_SYN_RECEIVED: 373 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 374 case IRDMA_AE_LCE_QP_CATASTROPHIC: 375 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 376 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 377 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 378 default: 379 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n", 380 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 381 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 382 ctx_info->roce_info->err_rq_idx_valid = info->rq; 383 if (info->rq) { 384 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 385 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 386 ctx_info); 387 } 388 irdma_set_flush_fields(qp, info); 389 irdma_cm_disconn(iwqp); 390 break; 391 } 392 ctx_info->iwarp_info->err_rq_idx_valid = info->rq; 393 if (info->rq) { 394 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 395 ctx_info->tcp_info_valid = false; 396 ctx_info->iwarp_info_valid = true; 397 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 398 ctx_info); 399 } 400 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 401 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 402 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 403 irdma_cm_disconn(iwqp); 404 } else { 405 irdma_terminate_connection(qp, info); 406 } 407 break; 408 } 409 if (info->qp) 410 irdma_qp_rem_ref(&iwqp->ibqp); 411 } while (1); 412 413 if (aeqcnt) 414 irdma_sc_repost_aeq_entries(dev, aeqcnt); 415 } 416 417 /** 418 * irdma_ena_intr - set up device interrupts 419 * @dev: hardware control device structure 420 * @msix_id: id of the interrupt to be enabled 421 */ 422 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 423 { 424 dev->irq_ops->irdma_en_irq(dev, msix_id); 425 } 426 427 /** 428 * irdma_dpc - tasklet for aeq and ceq 0 429 * @t: tasklet_struct ptr 430 */ 431 static void irdma_dpc(struct tasklet_struct *t) 432 { 433 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 434 435 if (rf->msix_shared) 436 irdma_process_ceq(rf, rf->ceqlist); 437 irdma_process_aeq(rf); 438 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 439 } 440 441 /** 442 * irdma_ceq_dpc - dpc handler for CEQ 443 * @t: tasklet_struct ptr 444 */ 445 static void irdma_ceq_dpc(struct tasklet_struct *t) 446 { 447 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 448 struct irdma_pci_f *rf = iwceq->rf; 449 450 irdma_process_ceq(rf, iwceq); 451 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 452 } 453 454 /** 455 * irdma_save_msix_info - copy msix vector information to iwarp device 456 * @rf: RDMA PCI function 457 * 458 * Allocate iwdev msix table and copy the msix info to the table 459 * Return 0 if successful, otherwise return error 460 */ 461 static int irdma_save_msix_info(struct irdma_pci_f *rf) 462 { 463 struct irdma_qvlist_info *iw_qvlist; 464 struct irdma_qv_info *iw_qvinfo; 465 struct msix_entry *pmsix; 466 u32 ceq_idx; 467 u32 i; 468 size_t size; 469 470 if (!rf->msix_count) 471 return -EINVAL; 472 473 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 474 size += struct_size(iw_qvlist, qv_info, rf->msix_count); 475 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 476 if (!rf->iw_msixtbl) 477 return -ENOMEM; 478 479 rf->iw_qvlist = (struct irdma_qvlist_info *) 480 (&rf->iw_msixtbl[rf->msix_count]); 481 iw_qvlist = rf->iw_qvlist; 482 iw_qvinfo = iw_qvlist->qv_info; 483 iw_qvlist->num_vectors = rf->msix_count; 484 if (rf->msix_count <= num_online_cpus()) 485 rf->msix_shared = true; 486 else if (rf->msix_count > num_online_cpus() + 1) 487 rf->msix_count = num_online_cpus() + 1; 488 489 pmsix = rf->msix_entries; 490 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 491 rf->iw_msixtbl[i].idx = pmsix->entry; 492 rf->iw_msixtbl[i].irq = pmsix->vector; 493 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 494 if (!i) { 495 iw_qvinfo->aeq_idx = 0; 496 if (rf->msix_shared) 497 iw_qvinfo->ceq_idx = ceq_idx++; 498 else 499 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 500 } else { 501 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 502 iw_qvinfo->ceq_idx = ceq_idx++; 503 } 504 iw_qvinfo->itr_idx = 3; 505 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 506 pmsix++; 507 } 508 509 return 0; 510 } 511 512 /** 513 * irdma_irq_handler - interrupt handler for aeq and ceq0 514 * @irq: Interrupt request number 515 * @data: RDMA PCI function 516 */ 517 static irqreturn_t irdma_irq_handler(int irq, void *data) 518 { 519 struct irdma_pci_f *rf = data; 520 521 tasklet_schedule(&rf->dpc_tasklet); 522 523 return IRQ_HANDLED; 524 } 525 526 /** 527 * irdma_ceq_handler - interrupt handler for ceq 528 * @irq: interrupt request number 529 * @data: ceq pointer 530 */ 531 static irqreturn_t irdma_ceq_handler(int irq, void *data) 532 { 533 struct irdma_ceq *iwceq = data; 534 535 if (iwceq->irq != irq) 536 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n", 537 iwceq->irq, irq); 538 tasklet_schedule(&iwceq->dpc_tasklet); 539 540 return IRQ_HANDLED; 541 } 542 543 /** 544 * irdma_destroy_irq - destroy device interrupts 545 * @rf: RDMA PCI function 546 * @msix_vec: msix vector to disable irq 547 * @dev_id: parameter to pass to free_irq (used during irq setup) 548 * 549 * The function is called when destroying aeq/ceq 550 */ 551 static void irdma_destroy_irq(struct irdma_pci_f *rf, 552 struct irdma_msix_vector *msix_vec, void *dev_id) 553 { 554 struct irdma_sc_dev *dev = &rf->sc_dev; 555 556 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 557 irq_update_affinity_hint(msix_vec->irq, NULL); 558 free_irq(msix_vec->irq, dev_id); 559 } 560 561 /** 562 * irdma_destroy_cqp - destroy control qp 563 * @rf: RDMA PCI function 564 * @free_hwcqp: 1 if hw cqp should be freed 565 * 566 * Issue destroy cqp request and 567 * free the resources associated with the cqp 568 */ 569 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 570 { 571 struct irdma_sc_dev *dev = &rf->sc_dev; 572 struct irdma_cqp *cqp = &rf->cqp; 573 int status = 0; 574 575 if (rf->cqp_cmpl_wq) 576 destroy_workqueue(rf->cqp_cmpl_wq); 577 if (free_hwcqp) 578 status = irdma_sc_cqp_destroy(dev->cqp); 579 if (status) 580 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); 581 582 irdma_cleanup_pending_cqp_op(rf); 583 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, 584 cqp->sq.pa); 585 cqp->sq.va = NULL; 586 kfree(cqp->scratch_array); 587 cqp->scratch_array = NULL; 588 kfree(cqp->cqp_requests); 589 cqp->cqp_requests = NULL; 590 } 591 592 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 593 { 594 struct irdma_aeq *aeq = &rf->aeq; 595 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 596 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 597 598 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 599 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 600 vfree(aeq->mem.va); 601 } 602 603 /** 604 * irdma_destroy_aeq - destroy aeq 605 * @rf: RDMA PCI function 606 * 607 * Issue a destroy aeq request and 608 * free the resources associated with the aeq 609 * The function is called during driver unload 610 */ 611 static void irdma_destroy_aeq(struct irdma_pci_f *rf) 612 { 613 struct irdma_sc_dev *dev = &rf->sc_dev; 614 struct irdma_aeq *aeq = &rf->aeq; 615 int status = -EBUSY; 616 617 if (!rf->msix_shared) { 618 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 619 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 620 } 621 if (rf->reset) 622 goto exit; 623 624 aeq->sc_aeq.size = 0; 625 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 626 if (status) 627 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); 628 629 exit: 630 if (aeq->virtual_map) { 631 irdma_destroy_virt_aeq(rf); 632 } else { 633 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 634 aeq->mem.pa); 635 aeq->mem.va = NULL; 636 } 637 } 638 639 /** 640 * irdma_destroy_ceq - destroy ceq 641 * @rf: RDMA PCI function 642 * @iwceq: ceq to be destroyed 643 * 644 * Issue a destroy ceq request and 645 * free the resources associated with the ceq 646 */ 647 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 648 { 649 struct irdma_sc_dev *dev = &rf->sc_dev; 650 int status; 651 652 if (rf->reset) 653 goto exit; 654 655 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 656 if (status) { 657 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); 658 goto exit; 659 } 660 661 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 662 if (status) 663 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", 664 status); 665 exit: 666 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, 667 iwceq->mem.pa); 668 iwceq->mem.va = NULL; 669 } 670 671 /** 672 * irdma_del_ceq_0 - destroy ceq 0 673 * @rf: RDMA PCI function 674 * 675 * Disable the ceq 0 interrupt and destroy the ceq 0 676 */ 677 static void irdma_del_ceq_0(struct irdma_pci_f *rf) 678 { 679 struct irdma_ceq *iwceq = rf->ceqlist; 680 struct irdma_msix_vector *msix_vec; 681 682 if (rf->msix_shared) { 683 msix_vec = &rf->iw_msixtbl[0]; 684 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 685 msix_vec->ceq_id, 686 msix_vec->idx, false); 687 irdma_destroy_irq(rf, msix_vec, rf); 688 } else { 689 msix_vec = &rf->iw_msixtbl[1]; 690 irdma_destroy_irq(rf, msix_vec, iwceq); 691 } 692 693 irdma_destroy_ceq(rf, iwceq); 694 rf->sc_dev.ceq_valid = false; 695 rf->ceqs_count = 0; 696 } 697 698 /** 699 * irdma_del_ceqs - destroy all ceq's except CEQ 0 700 * @rf: RDMA PCI function 701 * 702 * Go through all of the device ceq's, except 0, and for each 703 * ceq disable the ceq interrupt and destroy the ceq 704 */ 705 static void irdma_del_ceqs(struct irdma_pci_f *rf) 706 { 707 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 708 struct irdma_msix_vector *msix_vec; 709 u32 i = 0; 710 711 if (rf->msix_shared) 712 msix_vec = &rf->iw_msixtbl[1]; 713 else 714 msix_vec = &rf->iw_msixtbl[2]; 715 716 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 717 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 718 msix_vec->idx, false); 719 irdma_destroy_irq(rf, msix_vec, iwceq); 720 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 721 IRDMA_OP_CEQ_DESTROY); 722 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, 723 iwceq->mem.va, iwceq->mem.pa); 724 iwceq->mem.va = NULL; 725 } 726 rf->ceqs_count = 1; 727 } 728 729 /** 730 * irdma_destroy_ccq - destroy control cq 731 * @rf: RDMA PCI function 732 * 733 * Issue destroy ccq request and 734 * free the resources associated with the ccq 735 */ 736 static void irdma_destroy_ccq(struct irdma_pci_f *rf) 737 { 738 struct irdma_sc_dev *dev = &rf->sc_dev; 739 struct irdma_ccq *ccq = &rf->ccq; 740 int status = 0; 741 742 if (!rf->reset) 743 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 744 if (status) 745 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); 746 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, 747 ccq->mem_cq.pa); 748 ccq->mem_cq.va = NULL; 749 } 750 751 /** 752 * irdma_close_hmc_objects_type - delete hmc objects of a given type 753 * @dev: iwarp device 754 * @obj_type: the hmc object type to be deleted 755 * @hmc_info: host memory info struct 756 * @privileged: permission to close HMC objects 757 * @reset: true if called before reset 758 */ 759 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 760 enum irdma_hmc_rsrc_type obj_type, 761 struct irdma_hmc_info *hmc_info, 762 bool privileged, bool reset) 763 { 764 struct irdma_hmc_del_obj_info info = {}; 765 766 info.hmc_info = hmc_info; 767 info.rsrc_type = obj_type; 768 info.count = hmc_info->hmc_obj[obj_type].cnt; 769 info.privileged = privileged; 770 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 771 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", 772 obj_type); 773 } 774 775 /** 776 * irdma_del_hmc_objects - remove all device hmc objects 777 * @dev: iwarp device 778 * @hmc_info: hmc_info to free 779 * @privileged: permission to delete HMC objects 780 * @reset: true if called before reset 781 * @vers: hardware version 782 */ 783 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev, 784 struct irdma_hmc_info *hmc_info, bool privileged, 785 bool reset, enum irdma_vers vers) 786 { 787 unsigned int i; 788 789 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 790 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 791 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 792 hmc_info, privileged, reset); 793 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 794 break; 795 } 796 } 797 798 /** 799 * irdma_create_hmc_obj_type - create hmc object of a given type 800 * @dev: hardware control device structure 801 * @info: information for the hmc object to create 802 */ 803 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 804 struct irdma_hmc_create_obj_info *info) 805 { 806 return irdma_sc_create_hmc_obj(dev, info); 807 } 808 809 /** 810 * irdma_create_hmc_objs - create all hmc objects for the device 811 * @rf: RDMA PCI function 812 * @privileged: permission to create HMC objects 813 * @vers: HW version 814 * 815 * Create the device hmc objects and allocate hmc pages 816 * Return 0 if successful, otherwise clean up and return error 817 */ 818 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 819 enum irdma_vers vers) 820 { 821 struct irdma_sc_dev *dev = &rf->sc_dev; 822 struct irdma_hmc_create_obj_info info = {}; 823 int i, status = 0; 824 825 info.hmc_info = dev->hmc_info; 826 info.privileged = privileged; 827 info.entry_type = rf->sd_type; 828 829 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 830 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 831 info.rsrc_type = iw_hmc_obj_types[i]; 832 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 833 info.add_sd_cnt = 0; 834 status = irdma_create_hmc_obj_type(dev, &info); 835 if (status) { 836 ibdev_dbg(to_ibdev(dev), 837 "ERR: create obj type %d status = %d\n", 838 iw_hmc_obj_types[i], status); 839 break; 840 } 841 } 842 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 843 break; 844 } 845 846 if (!status) 847 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 848 true, true); 849 850 while (i) { 851 i--; 852 /* destroy the hmc objects of a given type */ 853 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 854 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 855 dev->hmc_info, privileged, 856 false); 857 } 858 859 return status; 860 } 861 862 /** 863 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 864 * @rf: RDMA PCI function 865 * @memptr: points to the memory addresses 866 * @size: size of memory needed 867 * @mask: mask for the aligned memory 868 * 869 * Get aligned memory of the requested size and 870 * update the memptr to point to the new aligned memory 871 * Return 0 if successful, otherwise return no memory error 872 */ 873 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf, 874 struct irdma_dma_mem *memptr, u32 size, 875 u32 mask) 876 { 877 unsigned long va, newva; 878 unsigned long extra; 879 880 va = (unsigned long)rf->obj_next.va; 881 newva = va; 882 if (mask) 883 newva = ALIGN(va, (unsigned long)mask + 1ULL); 884 extra = newva - va; 885 memptr->va = (u8 *)va + extra; 886 memptr->pa = rf->obj_next.pa + extra; 887 memptr->size = size; 888 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 889 return -ENOMEM; 890 891 rf->obj_next.va = (u8 *)memptr->va + size; 892 rf->obj_next.pa = memptr->pa + size; 893 894 return 0; 895 } 896 897 /** 898 * irdma_create_cqp - create control qp 899 * @rf: RDMA PCI function 900 * 901 * Return 0, if the cqp and all the resources associated with it 902 * are successfully created, otherwise return error 903 */ 904 static int irdma_create_cqp(struct irdma_pci_f *rf) 905 { 906 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 907 struct irdma_dma_mem mem; 908 struct irdma_sc_dev *dev = &rf->sc_dev; 909 struct irdma_cqp_init_info cqp_init_info = {}; 910 struct irdma_cqp *cqp = &rf->cqp; 911 u16 maj_err, min_err; 912 int i, status; 913 914 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 915 if (!cqp->cqp_requests) 916 return -ENOMEM; 917 918 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 919 if (!cqp->scratch_array) { 920 kfree(cqp->cqp_requests); 921 return -ENOMEM; 922 } 923 924 dev->cqp = &cqp->sc_cqp; 925 dev->cqp->dev = dev; 926 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, 927 IRDMA_CQP_ALIGNMENT); 928 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, 929 &cqp->sq.pa, GFP_KERNEL); 930 if (!cqp->sq.va) { 931 kfree(cqp->scratch_array); 932 kfree(cqp->cqp_requests); 933 return -ENOMEM; 934 } 935 936 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 937 IRDMA_HOST_CTX_ALIGNMENT_M); 938 if (status) 939 goto exit; 940 941 dev->cqp->host_ctx_pa = mem.pa; 942 dev->cqp->host_ctx = mem.va; 943 /* populate the cqp init info */ 944 cqp_init_info.dev = dev; 945 cqp_init_info.sq_size = sqsize; 946 cqp_init_info.sq = cqp->sq.va; 947 cqp_init_info.sq_pa = cqp->sq.pa; 948 cqp_init_info.host_ctx_pa = mem.pa; 949 cqp_init_info.host_ctx = mem.va; 950 cqp_init_info.hmc_profile = rf->rsrc_profile; 951 cqp_init_info.scratch_array = cqp->scratch_array; 952 cqp_init_info.protocol_used = rf->protocol_used; 953 954 switch (rf->rdma_ver) { 955 case IRDMA_GEN_1: 956 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 957 break; 958 case IRDMA_GEN_2: 959 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 960 break; 961 } 962 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 963 if (status) { 964 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); 965 goto exit; 966 } 967 968 spin_lock_init(&cqp->req_lock); 969 spin_lock_init(&cqp->compl_lock); 970 971 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 972 if (status) { 973 ibdev_dbg(to_ibdev(dev), 974 "ERR: cqp create failed - status %d maj_err %d min_err %d\n", 975 status, maj_err, min_err); 976 goto exit; 977 } 978 979 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 980 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 981 982 /* init the waitqueue of the cqp_requests and add them to the list */ 983 for (i = 0; i < sqsize; i++) { 984 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 985 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 986 } 987 init_waitqueue_head(&cqp->remove_wq); 988 return 0; 989 990 exit: 991 irdma_destroy_cqp(rf, false); 992 993 return status; 994 } 995 996 /** 997 * irdma_create_ccq - create control cq 998 * @rf: RDMA PCI function 999 * 1000 * Return 0, if the ccq and the resources associated with it 1001 * are successfully created, otherwise return error 1002 */ 1003 static int irdma_create_ccq(struct irdma_pci_f *rf) 1004 { 1005 struct irdma_sc_dev *dev = &rf->sc_dev; 1006 struct irdma_ccq_init_info info = {}; 1007 struct irdma_ccq *ccq = &rf->ccq; 1008 int status; 1009 1010 dev->ccq = &ccq->sc_cq; 1011 dev->ccq->dev = dev; 1012 info.dev = dev; 1013 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1014 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, 1015 IRDMA_CQ0_ALIGNMENT); 1016 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, 1017 &ccq->mem_cq.pa, GFP_KERNEL); 1018 if (!ccq->mem_cq.va) 1019 return -ENOMEM; 1020 1021 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1022 ccq->shadow_area.size, 1023 IRDMA_SHADOWAREA_M); 1024 if (status) 1025 goto exit; 1026 1027 ccq->sc_cq.back_cq = ccq; 1028 /* populate the ccq init info */ 1029 info.cq_base = ccq->mem_cq.va; 1030 info.cq_pa = ccq->mem_cq.pa; 1031 info.num_elem = IW_CCQ_SIZE; 1032 info.shadow_area = ccq->shadow_area.va; 1033 info.shadow_area_pa = ccq->shadow_area.pa; 1034 info.ceqe_mask = false; 1035 info.ceq_id_valid = true; 1036 info.shadow_read_threshold = 16; 1037 info.vsi = &rf->default_vsi; 1038 status = irdma_sc_ccq_init(dev->ccq, &info); 1039 if (!status) 1040 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1041 exit: 1042 if (status) { 1043 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, 1044 ccq->mem_cq.va, ccq->mem_cq.pa); 1045 ccq->mem_cq.va = NULL; 1046 } 1047 1048 return status; 1049 } 1050 1051 /** 1052 * irdma_alloc_set_mac - set up a mac address table entry 1053 * @iwdev: irdma device 1054 * 1055 * Allocate a mac ip entry and add it to the hw table Return 0 1056 * if successful, otherwise return error 1057 */ 1058 static int irdma_alloc_set_mac(struct irdma_device *iwdev) 1059 { 1060 int status; 1061 1062 status = irdma_alloc_local_mac_entry(iwdev->rf, 1063 &iwdev->mac_ip_table_idx); 1064 if (!status) { 1065 status = irdma_add_local_mac_entry(iwdev->rf, 1066 (const u8 *)iwdev->netdev->dev_addr, 1067 (u8)iwdev->mac_ip_table_idx); 1068 if (status) 1069 irdma_del_local_mac_entry(iwdev->rf, 1070 (u8)iwdev->mac_ip_table_idx); 1071 } 1072 return status; 1073 } 1074 1075 /** 1076 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1077 * ceq 1078 * @rf: RDMA PCI function 1079 * @iwceq: ceq associated with the vector 1080 * @ceq_id: the id number of the iwceq 1081 * @msix_vec: interrupt vector information 1082 * 1083 * Allocate interrupt resources and enable irq handling 1084 * Return 0 if successful, otherwise return error 1085 */ 1086 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1087 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1088 { 1089 int status; 1090 1091 if (rf->msix_shared && !ceq_id) { 1092 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1093 status = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1094 "AEQCEQ", rf); 1095 } else { 1096 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1097 1098 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0, 1099 "CEQ", iwceq); 1100 } 1101 cpumask_clear(&msix_vec->mask); 1102 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); 1103 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask); 1104 if (status) { 1105 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); 1106 return status; 1107 } 1108 1109 msix_vec->ceq_id = ceq_id; 1110 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1111 1112 return 0; 1113 } 1114 1115 /** 1116 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1117 * @rf: RDMA PCI function 1118 * 1119 * Allocate interrupt resources and enable irq handling 1120 * Return 0 if successful, otherwise return error 1121 */ 1122 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1123 { 1124 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1125 u32 ret = 0; 1126 1127 if (!rf->msix_shared) { 1128 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1129 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1130 "irdma", rf); 1131 } 1132 if (ret) { 1133 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); 1134 return -EINVAL; 1135 } 1136 1137 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1138 1139 return 0; 1140 } 1141 1142 /** 1143 * irdma_create_ceq - create completion event queue 1144 * @rf: RDMA PCI function 1145 * @iwceq: pointer to the ceq resources to be created 1146 * @ceq_id: the id number of the iwceq 1147 * @vsi: SC vsi struct 1148 * 1149 * Return 0, if the ceq and the resources associated with it 1150 * are successfully created, otherwise return error 1151 */ 1152 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1153 u32 ceq_id, struct irdma_sc_vsi *vsi) 1154 { 1155 int status; 1156 struct irdma_ceq_init_info info = {}; 1157 struct irdma_sc_dev *dev = &rf->sc_dev; 1158 u64 scratch; 1159 u32 ceq_size; 1160 1161 info.ceq_id = ceq_id; 1162 iwceq->rf = rf; 1163 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1164 dev->hw_attrs.max_hw_ceq_size); 1165 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, 1166 IRDMA_CEQ_ALIGNMENT); 1167 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, 1168 &iwceq->mem.pa, GFP_KERNEL); 1169 if (!iwceq->mem.va) 1170 return -ENOMEM; 1171 1172 info.ceq_id = ceq_id; 1173 info.ceqe_base = iwceq->mem.va; 1174 info.ceqe_pa = iwceq->mem.pa; 1175 info.elem_cnt = ceq_size; 1176 iwceq->sc_ceq.ceq_id = ceq_id; 1177 info.dev = dev; 1178 info.vsi = vsi; 1179 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1180 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1181 if (!status) { 1182 if (dev->ceq_valid) 1183 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1184 IRDMA_OP_CEQ_CREATE); 1185 else 1186 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1187 } 1188 1189 if (status) { 1190 dma_free_coherent(dev->hw->device, iwceq->mem.size, 1191 iwceq->mem.va, iwceq->mem.pa); 1192 iwceq->mem.va = NULL; 1193 } 1194 1195 return status; 1196 } 1197 1198 /** 1199 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1200 * @rf: RDMA PCI function 1201 * 1202 * Allocate a list for all device completion event queues 1203 * Create the ceq 0 and configure it's msix interrupt vector 1204 * Return 0, if successfully set up, otherwise return error 1205 */ 1206 static int irdma_setup_ceq_0(struct irdma_pci_f *rf) 1207 { 1208 struct irdma_ceq *iwceq; 1209 struct irdma_msix_vector *msix_vec; 1210 u32 i; 1211 int status = 0; 1212 u32 num_ceqs; 1213 1214 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1215 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1216 if (!rf->ceqlist) { 1217 status = -ENOMEM; 1218 goto exit; 1219 } 1220 1221 iwceq = &rf->ceqlist[0]; 1222 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1223 if (status) { 1224 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", 1225 status); 1226 goto exit; 1227 } 1228 1229 spin_lock_init(&iwceq->ce_lock); 1230 i = rf->msix_shared ? 0 : 1; 1231 msix_vec = &rf->iw_msixtbl[i]; 1232 iwceq->irq = msix_vec->irq; 1233 iwceq->msix_idx = msix_vec->idx; 1234 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1235 if (status) { 1236 irdma_destroy_ceq(rf, iwceq); 1237 goto exit; 1238 } 1239 1240 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1241 rf->ceqs_count++; 1242 1243 exit: 1244 if (status && !rf->ceqs_count) { 1245 kfree(rf->ceqlist); 1246 rf->ceqlist = NULL; 1247 return status; 1248 } 1249 rf->sc_dev.ceq_valid = true; 1250 1251 return 0; 1252 } 1253 1254 /** 1255 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1256 * @rf: RDMA PCI function 1257 * @vsi: VSI structure for this CEQ 1258 * 1259 * Allocate a list for all device completion event queues 1260 * Create the ceq's and configure their msix interrupt vectors 1261 * Return 0, if ceqs are successfully set up, otherwise return error 1262 */ 1263 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1264 { 1265 u32 i; 1266 u32 ceq_id; 1267 struct irdma_ceq *iwceq; 1268 struct irdma_msix_vector *msix_vec; 1269 int status; 1270 u32 num_ceqs; 1271 1272 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1273 i = (rf->msix_shared) ? 1 : 2; 1274 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1275 iwceq = &rf->ceqlist[ceq_id]; 1276 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1277 if (status) { 1278 ibdev_dbg(&rf->iwdev->ibdev, 1279 "ERR: create ceq status = %d\n", status); 1280 goto del_ceqs; 1281 } 1282 spin_lock_init(&iwceq->ce_lock); 1283 msix_vec = &rf->iw_msixtbl[i]; 1284 iwceq->irq = msix_vec->irq; 1285 iwceq->msix_idx = msix_vec->idx; 1286 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1287 if (status) { 1288 irdma_destroy_ceq(rf, iwceq); 1289 goto del_ceqs; 1290 } 1291 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1292 rf->ceqs_count++; 1293 } 1294 1295 return 0; 1296 1297 del_ceqs: 1298 irdma_del_ceqs(rf); 1299 1300 return status; 1301 } 1302 1303 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1304 { 1305 struct irdma_aeq *aeq = &rf->aeq; 1306 dma_addr_t *pg_arr; 1307 u32 pg_cnt; 1308 int status; 1309 1310 if (rf->rdma_ver < IRDMA_GEN_2) 1311 return -EOPNOTSUPP; 1312 1313 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1314 aeq->mem.va = vzalloc(aeq->mem.size); 1315 1316 if (!aeq->mem.va) 1317 return -ENOMEM; 1318 1319 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1320 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1321 if (status) { 1322 vfree(aeq->mem.va); 1323 return status; 1324 } 1325 1326 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 1327 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1328 if (status) { 1329 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1330 vfree(aeq->mem.va); 1331 return status; 1332 } 1333 1334 return 0; 1335 } 1336 1337 /** 1338 * irdma_create_aeq - create async event queue 1339 * @rf: RDMA PCI function 1340 * 1341 * Return 0, if the aeq and the resources associated with it 1342 * are successfully created, otherwise return error 1343 */ 1344 static int irdma_create_aeq(struct irdma_pci_f *rf) 1345 { 1346 struct irdma_aeq_init_info info = {}; 1347 struct irdma_sc_dev *dev = &rf->sc_dev; 1348 struct irdma_aeq *aeq = &rf->aeq; 1349 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1350 u32 aeq_size; 1351 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1352 int status; 1353 1354 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1355 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1356 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1357 1358 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, 1359 IRDMA_AEQ_ALIGNMENT); 1360 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, 1361 &aeq->mem.pa, 1362 GFP_KERNEL | __GFP_NOWARN); 1363 if (aeq->mem.va) 1364 goto skip_virt_aeq; 1365 1366 /* physically mapped aeq failed. setup virtual aeq */ 1367 status = irdma_create_virt_aeq(rf, aeq_size); 1368 if (status) 1369 return status; 1370 1371 info.virtual_map = true; 1372 aeq->virtual_map = info.virtual_map; 1373 info.pbl_chunk_size = 1; 1374 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1375 1376 skip_virt_aeq: 1377 info.aeqe_base = aeq->mem.va; 1378 info.aeq_elem_pa = aeq->mem.pa; 1379 info.elem_cnt = aeq_size; 1380 info.dev = dev; 1381 info.msix_idx = rf->iw_msixtbl->idx; 1382 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1383 if (status) 1384 goto err; 1385 1386 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1387 if (status) 1388 goto err; 1389 1390 return 0; 1391 1392 err: 1393 if (aeq->virtual_map) { 1394 irdma_destroy_virt_aeq(rf); 1395 } else { 1396 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 1397 aeq->mem.pa); 1398 aeq->mem.va = NULL; 1399 } 1400 1401 return status; 1402 } 1403 1404 /** 1405 * irdma_setup_aeq - set up the device aeq 1406 * @rf: RDMA PCI function 1407 * 1408 * Create the aeq and configure its msix interrupt vector 1409 * Return 0 if successful, otherwise return error 1410 */ 1411 static int irdma_setup_aeq(struct irdma_pci_f *rf) 1412 { 1413 struct irdma_sc_dev *dev = &rf->sc_dev; 1414 int status; 1415 1416 status = irdma_create_aeq(rf); 1417 if (status) 1418 return status; 1419 1420 status = irdma_cfg_aeq_vector(rf); 1421 if (status) { 1422 irdma_destroy_aeq(rf); 1423 return status; 1424 } 1425 1426 if (!rf->msix_shared) 1427 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1428 1429 return 0; 1430 } 1431 1432 /** 1433 * irdma_initialize_ilq - create iwarp local queue for cm 1434 * @iwdev: irdma device 1435 * 1436 * Return 0 if successful, otherwise return error 1437 */ 1438 static int irdma_initialize_ilq(struct irdma_device *iwdev) 1439 { 1440 struct irdma_puda_rsrc_info info = {}; 1441 int status; 1442 1443 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1444 info.cq_id = 1; 1445 info.qp_id = 1; 1446 info.count = 1; 1447 info.pd_id = 1; 1448 info.abi_ver = IRDMA_ABI_VER; 1449 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1450 info.rq_size = info.sq_size; 1451 info.buf_size = 1024; 1452 info.tx_buf_cnt = 2 * info.sq_size; 1453 info.receive = irdma_receive_ilq; 1454 info.xmit_complete = irdma_free_sqbuf; 1455 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1456 if (status) 1457 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); 1458 1459 return status; 1460 } 1461 1462 /** 1463 * irdma_initialize_ieq - create iwarp exception queue 1464 * @iwdev: irdma device 1465 * 1466 * Return 0 if successful, otherwise return error 1467 */ 1468 static int irdma_initialize_ieq(struct irdma_device *iwdev) 1469 { 1470 struct irdma_puda_rsrc_info info = {}; 1471 int status; 1472 1473 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1474 info.cq_id = 2; 1475 info.qp_id = iwdev->vsi.exception_lan_q; 1476 info.count = 1; 1477 info.pd_id = 2; 1478 info.abi_ver = IRDMA_ABI_VER; 1479 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1480 info.rq_size = info.sq_size; 1481 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1482 info.tx_buf_cnt = 4096; 1483 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1484 if (status) 1485 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); 1486 1487 return status; 1488 } 1489 1490 /** 1491 * irdma_reinitialize_ieq - destroy and re-create ieq 1492 * @vsi: VSI structure 1493 */ 1494 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1495 { 1496 struct irdma_device *iwdev = vsi->back_vsi; 1497 struct irdma_pci_f *rf = iwdev->rf; 1498 1499 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1500 if (irdma_initialize_ieq(iwdev)) { 1501 iwdev->rf->reset = true; 1502 rf->gen_ops.request_reset(rf); 1503 } 1504 } 1505 1506 /** 1507 * irdma_hmc_setup - create hmc objects for the device 1508 * @rf: RDMA PCI function 1509 * 1510 * Set up the device private memory space for the number and size of 1511 * the hmc objects and create the objects 1512 * Return 0 if successful, otherwise return error 1513 */ 1514 static int irdma_hmc_setup(struct irdma_pci_f *rf) 1515 { 1516 int status; 1517 u32 qpcnt; 1518 1519 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1520 1521 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1522 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt); 1523 if (status) 1524 return status; 1525 1526 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1527 1528 return status; 1529 } 1530 1531 /** 1532 * irdma_del_init_mem - deallocate memory resources 1533 * @rf: RDMA PCI function 1534 */ 1535 static void irdma_del_init_mem(struct irdma_pci_f *rf) 1536 { 1537 struct irdma_sc_dev *dev = &rf->sc_dev; 1538 1539 kfree(dev->hmc_info->sd_table.sd_entry); 1540 dev->hmc_info->sd_table.sd_entry = NULL; 1541 kfree(rf->mem_rsrc); 1542 rf->mem_rsrc = NULL; 1543 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1544 rf->obj_mem.pa); 1545 rf->obj_mem.va = NULL; 1546 if (rf->rdma_ver != IRDMA_GEN_1) { 1547 bitmap_free(rf->allocated_ws_nodes); 1548 rf->allocated_ws_nodes = NULL; 1549 } 1550 kfree(rf->ceqlist); 1551 rf->ceqlist = NULL; 1552 kfree(rf->iw_msixtbl); 1553 rf->iw_msixtbl = NULL; 1554 kfree(rf->hmc_info_mem); 1555 rf->hmc_info_mem = NULL; 1556 } 1557 1558 /** 1559 * irdma_initialize_dev - initialize device 1560 * @rf: RDMA PCI function 1561 * 1562 * Allocate memory for the hmc objects and initialize iwdev 1563 * Return 0 if successful, otherwise clean up the resources 1564 * and return error 1565 */ 1566 static int irdma_initialize_dev(struct irdma_pci_f *rf) 1567 { 1568 int status; 1569 struct irdma_sc_dev *dev = &rf->sc_dev; 1570 struct irdma_device_init_info info = {}; 1571 struct irdma_dma_mem mem; 1572 u32 size; 1573 1574 size = sizeof(struct irdma_hmc_pble_rsrc) + 1575 sizeof(struct irdma_hmc_info) + 1576 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1577 1578 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1579 if (!rf->hmc_info_mem) 1580 return -ENOMEM; 1581 1582 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1583 dev->hmc_info = &rf->hw.hmc; 1584 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1585 (rf->pble_rsrc + 1); 1586 1587 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1588 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1589 if (status) 1590 goto error; 1591 1592 info.fpm_query_buf_pa = mem.pa; 1593 info.fpm_query_buf = mem.va; 1594 1595 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1596 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1597 if (status) 1598 goto error; 1599 1600 info.fpm_commit_buf_pa = mem.pa; 1601 info.fpm_commit_buf = mem.va; 1602 1603 info.bar0 = rf->hw.hw_addr; 1604 info.hmc_fn_id = rf->pf_id; 1605 info.hw = &rf->hw; 1606 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info); 1607 if (status) 1608 goto error; 1609 1610 return status; 1611 error: 1612 kfree(rf->hmc_info_mem); 1613 rf->hmc_info_mem = NULL; 1614 1615 return status; 1616 } 1617 1618 /** 1619 * irdma_rt_deinit_hw - clean up the irdma device resources 1620 * @iwdev: irdma device 1621 * 1622 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1623 * device queues and free the pble and the hmc objects 1624 */ 1625 void irdma_rt_deinit_hw(struct irdma_device *iwdev) 1626 { 1627 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); 1628 1629 switch (iwdev->init_state) { 1630 case IP_ADDR_REGISTERED: 1631 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1632 irdma_del_local_mac_entry(iwdev->rf, 1633 (u8)iwdev->mac_ip_table_idx); 1634 fallthrough; 1635 case AEQ_CREATED: 1636 case PBLE_CHUNK_MEM: 1637 case CEQS_CREATED: 1638 case IEQ_CREATED: 1639 if (!iwdev->roce_mode) 1640 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1641 iwdev->rf->reset); 1642 fallthrough; 1643 case ILQ_CREATED: 1644 if (!iwdev->roce_mode) 1645 irdma_puda_dele_rsrc(&iwdev->vsi, 1646 IRDMA_PUDA_RSRC_TYPE_ILQ, 1647 iwdev->rf->reset); 1648 break; 1649 default: 1650 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1651 break; 1652 } 1653 1654 irdma_cleanup_cm_core(&iwdev->cm_core); 1655 if (iwdev->vsi.pestat) { 1656 irdma_vsi_stats_free(&iwdev->vsi); 1657 kfree(iwdev->vsi.pestat); 1658 } 1659 if (iwdev->cleanup_wq) 1660 destroy_workqueue(iwdev->cleanup_wq); 1661 } 1662 1663 static int irdma_setup_init_state(struct irdma_pci_f *rf) 1664 { 1665 int status; 1666 1667 status = irdma_save_msix_info(rf); 1668 if (status) 1669 return status; 1670 1671 rf->hw.device = &rf->pcidev->dev; 1672 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); 1673 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, 1674 &rf->obj_mem.pa, GFP_KERNEL); 1675 if (!rf->obj_mem.va) { 1676 status = -ENOMEM; 1677 goto clean_msixtbl; 1678 } 1679 1680 rf->obj_next = rf->obj_mem; 1681 status = irdma_initialize_dev(rf); 1682 if (status) 1683 goto clean_obj_mem; 1684 1685 return 0; 1686 1687 clean_obj_mem: 1688 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1689 rf->obj_mem.pa); 1690 rf->obj_mem.va = NULL; 1691 clean_msixtbl: 1692 kfree(rf->iw_msixtbl); 1693 rf->iw_msixtbl = NULL; 1694 return status; 1695 } 1696 1697 /** 1698 * irdma_get_used_rsrc - determine resources used internally 1699 * @iwdev: irdma device 1700 * 1701 * Called at the end of open to get all internal allocations 1702 */ 1703 static void irdma_get_used_rsrc(struct irdma_device *iwdev) 1704 { 1705 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1706 iwdev->rf->max_pd); 1707 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1708 iwdev->rf->max_qp); 1709 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1710 iwdev->rf->max_cq); 1711 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1712 iwdev->rf->max_mr); 1713 } 1714 1715 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1716 { 1717 enum init_completion_state state = rf->init_state; 1718 1719 rf->init_state = INVALID_STATE; 1720 if (rf->rsrc_created) { 1721 irdma_destroy_aeq(rf); 1722 irdma_destroy_pble_prm(rf->pble_rsrc); 1723 irdma_del_ceqs(rf); 1724 rf->rsrc_created = false; 1725 } 1726 switch (state) { 1727 case CEQ0_CREATED: 1728 irdma_del_ceq_0(rf); 1729 fallthrough; 1730 case CCQ_CREATED: 1731 irdma_destroy_ccq(rf); 1732 fallthrough; 1733 case HW_RSRC_INITIALIZED: 1734 case HMC_OBJS_CREATED: 1735 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1736 rf->reset, rf->rdma_ver); 1737 fallthrough; 1738 case CQP_CREATED: 1739 irdma_destroy_cqp(rf, true); 1740 fallthrough; 1741 case INITIAL_STATE: 1742 irdma_del_init_mem(rf); 1743 break; 1744 case INVALID_STATE: 1745 default: 1746 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1747 break; 1748 } 1749 } 1750 1751 /** 1752 * irdma_rt_init_hw - Initializes runtime portion of HW 1753 * @iwdev: irdma device 1754 * @l2params: qos, tc, mtu info from netdev driver 1755 * 1756 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1757 * device resource objects. 1758 */ 1759 int irdma_rt_init_hw(struct irdma_device *iwdev, 1760 struct irdma_l2params *l2params) 1761 { 1762 struct irdma_pci_f *rf = iwdev->rf; 1763 struct irdma_sc_dev *dev = &rf->sc_dev; 1764 struct irdma_vsi_init_info vsi_info = {}; 1765 struct irdma_vsi_stats_info stats_info = {}; 1766 int status; 1767 1768 vsi_info.dev = dev; 1769 vsi_info.back_vsi = iwdev; 1770 vsi_info.params = l2params; 1771 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1772 vsi_info.register_qset = rf->gen_ops.register_qset; 1773 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1774 vsi_info.exception_lan_q = 2; 1775 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1776 1777 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1778 if (status) 1779 return status; 1780 1781 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1782 if (!stats_info.pestat) { 1783 irdma_cleanup_cm_core(&iwdev->cm_core); 1784 return -ENOMEM; 1785 } 1786 stats_info.fcn_id = dev->hmc_fn_id; 1787 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1788 if (status) { 1789 irdma_cleanup_cm_core(&iwdev->cm_core); 1790 kfree(stats_info.pestat); 1791 return status; 1792 } 1793 1794 do { 1795 if (!iwdev->roce_mode) { 1796 status = irdma_initialize_ilq(iwdev); 1797 if (status) 1798 break; 1799 iwdev->init_state = ILQ_CREATED; 1800 status = irdma_initialize_ieq(iwdev); 1801 if (status) 1802 break; 1803 iwdev->init_state = IEQ_CREATED; 1804 } 1805 if (!rf->rsrc_created) { 1806 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1807 if (status) 1808 break; 1809 1810 iwdev->init_state = CEQS_CREATED; 1811 1812 status = irdma_hmc_init_pble(&rf->sc_dev, 1813 rf->pble_rsrc); 1814 if (status) { 1815 irdma_del_ceqs(rf); 1816 break; 1817 } 1818 1819 iwdev->init_state = PBLE_CHUNK_MEM; 1820 1821 status = irdma_setup_aeq(rf); 1822 if (status) { 1823 irdma_destroy_pble_prm(rf->pble_rsrc); 1824 irdma_del_ceqs(rf); 1825 break; 1826 } 1827 iwdev->init_state = AEQ_CREATED; 1828 rf->rsrc_created = true; 1829 } 1830 1831 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1832 irdma_alloc_set_mac(iwdev); 1833 irdma_add_ip(iwdev); 1834 iwdev->init_state = IP_ADDR_REGISTERED; 1835 1836 /* handles asynch cleanup tasks - disconnect CM , free qp, 1837 * free cq bufs 1838 */ 1839 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1840 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1841 if (!iwdev->cleanup_wq) 1842 return -ENOMEM; 1843 irdma_get_used_rsrc(iwdev); 1844 init_waitqueue_head(&iwdev->suspend_wq); 1845 1846 return 0; 1847 } while (0); 1848 1849 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1850 status, iwdev->init_state); 1851 irdma_rt_deinit_hw(iwdev); 1852 1853 return status; 1854 } 1855 1856 /** 1857 * irdma_ctrl_init_hw - Initializes control portion of HW 1858 * @rf: RDMA PCI function 1859 * 1860 * Create admin queues, HMC obejcts and RF resource objects 1861 */ 1862 int irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1863 { 1864 struct irdma_sc_dev *dev = &rf->sc_dev; 1865 int status; 1866 do { 1867 status = irdma_setup_init_state(rf); 1868 if (status) 1869 break; 1870 rf->init_state = INITIAL_STATE; 1871 1872 status = irdma_create_cqp(rf); 1873 if (status) 1874 break; 1875 rf->init_state = CQP_CREATED; 1876 1877 status = irdma_hmc_setup(rf); 1878 if (status) 1879 break; 1880 rf->init_state = HMC_OBJS_CREATED; 1881 1882 status = irdma_initialize_hw_rsrc(rf); 1883 if (status) 1884 break; 1885 rf->init_state = HW_RSRC_INITIALIZED; 1886 1887 status = irdma_create_ccq(rf); 1888 if (status) 1889 break; 1890 rf->init_state = CCQ_CREATED; 1891 1892 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 1893 if (rf->rdma_ver != IRDMA_GEN_1) { 1894 status = irdma_get_rdma_features(dev); 1895 if (status) 1896 break; 1897 } 1898 1899 status = irdma_setup_ceq_0(rf); 1900 if (status) 1901 break; 1902 rf->init_state = CEQ0_CREATED; 1903 /* Handles processing of CQP completions */ 1904 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 1905 WQ_HIGHPRI | WQ_UNBOUND); 1906 if (!rf->cqp_cmpl_wq) { 1907 status = -ENOMEM; 1908 break; 1909 } 1910 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 1911 irdma_sc_ccq_arm(dev->ccq); 1912 return 0; 1913 } while (0); 1914 1915 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n", 1916 rf->init_state, status); 1917 irdma_ctrl_deinit_hw(rf); 1918 return status; 1919 } 1920 1921 /** 1922 * irdma_set_hw_rsrc - set hw memory resources. 1923 * @rf: RDMA PCI function 1924 */ 1925 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) 1926 { 1927 rf->allocated_qps = (void *)(rf->mem_rsrc + 1928 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 1929 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 1930 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 1931 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 1932 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 1933 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 1934 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 1935 rf->qp_table = (struct irdma_qp **) 1936 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 1937 1938 spin_lock_init(&rf->rsrc_lock); 1939 spin_lock_init(&rf->arp_lock); 1940 spin_lock_init(&rf->qptable_lock); 1941 spin_lock_init(&rf->qh_list_lock); 1942 } 1943 1944 /** 1945 * irdma_calc_mem_rsrc_size - calculate memory resources size. 1946 * @rf: RDMA PCI function 1947 */ 1948 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 1949 { 1950 u32 rsrc_size; 1951 1952 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 1953 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 1954 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 1955 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 1956 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 1957 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 1958 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 1959 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 1960 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 1961 1962 return rsrc_size; 1963 } 1964 1965 /** 1966 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 1967 * @rf: RDMA PCI function 1968 */ 1969 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 1970 { 1971 u32 rsrc_size; 1972 u32 mrdrvbits; 1973 u32 ret; 1974 1975 if (rf->rdma_ver != IRDMA_GEN_1) { 1976 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES, 1977 GFP_KERNEL); 1978 if (!rf->allocated_ws_nodes) 1979 return -ENOMEM; 1980 1981 set_bit(0, rf->allocated_ws_nodes); 1982 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 1983 } 1984 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 1985 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 1986 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 1987 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1988 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 1989 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 1990 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 1991 rf->max_mcg = rf->max_qp; 1992 1993 rsrc_size = irdma_calc_mem_rsrc_size(rf); 1994 rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL); 1995 if (!rf->mem_rsrc) { 1996 ret = -ENOMEM; 1997 goto mem_rsrc_kzalloc_fail; 1998 } 1999 2000 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2001 2002 irdma_set_hw_rsrc(rf); 2003 2004 set_bit(0, rf->allocated_mrs); 2005 set_bit(0, rf->allocated_qps); 2006 set_bit(0, rf->allocated_cqs); 2007 set_bit(0, rf->allocated_pds); 2008 set_bit(0, rf->allocated_arps); 2009 set_bit(0, rf->allocated_ahs); 2010 set_bit(0, rf->allocated_mcgs); 2011 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2012 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2013 set_bit(1, rf->allocated_cqs); 2014 set_bit(1, rf->allocated_pds); 2015 set_bit(2, rf->allocated_cqs); 2016 set_bit(2, rf->allocated_pds); 2017 2018 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2019 /* stag index mask has a minimum of 14 bits */ 2020 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2021 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2022 2023 return 0; 2024 2025 mem_rsrc_kzalloc_fail: 2026 bitmap_free(rf->allocated_ws_nodes); 2027 rf->allocated_ws_nodes = NULL; 2028 2029 return ret; 2030 } 2031 2032 /** 2033 * irdma_cqp_ce_handler - handle cqp completions 2034 * @rf: RDMA PCI function 2035 * @cq: cq for cqp completions 2036 */ 2037 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2038 { 2039 struct irdma_cqp_request *cqp_request; 2040 struct irdma_sc_dev *dev = &rf->sc_dev; 2041 u32 cqe_count = 0; 2042 struct irdma_ccq_cqe_info info; 2043 unsigned long flags; 2044 int ret; 2045 2046 do { 2047 memset(&info, 0, sizeof(info)); 2048 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2049 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2050 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2051 if (ret) 2052 break; 2053 2054 cqp_request = (struct irdma_cqp_request *) 2055 (unsigned long)info.scratch; 2056 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2057 info.maj_err_code, 2058 info.min_err_code)) 2059 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2060 info.op_code, info.maj_err_code, info.min_err_code); 2061 if (cqp_request) { 2062 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2063 cqp_request->compl_info.min_err_code = info.min_err_code; 2064 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2065 cqp_request->compl_info.error = info.error; 2066 2067 if (cqp_request->waiting) { 2068 cqp_request->request_done = true; 2069 wake_up(&cqp_request->waitq); 2070 irdma_put_cqp_request(&rf->cqp, cqp_request); 2071 } else { 2072 if (cqp_request->callback_fcn) 2073 cqp_request->callback_fcn(cqp_request); 2074 irdma_put_cqp_request(&rf->cqp, cqp_request); 2075 } 2076 } 2077 2078 cqe_count++; 2079 } while (1); 2080 2081 if (cqe_count) { 2082 irdma_process_bh(dev); 2083 irdma_sc_ccq_arm(cq); 2084 } 2085 } 2086 2087 /** 2088 * cqp_compl_worker - Handle cqp completions 2089 * @work: Pointer to work structure 2090 */ 2091 void cqp_compl_worker(struct work_struct *work) 2092 { 2093 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2094 cqp_cmpl_work); 2095 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2096 2097 irdma_cqp_ce_handler(rf, cq); 2098 } 2099 2100 /** 2101 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2102 * @cm_core: cm's core 2103 * @port: port to identify apbvt entry 2104 */ 2105 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2106 u16 port) 2107 { 2108 struct irdma_apbvt_entry *entry; 2109 2110 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2111 if (entry->port == port) { 2112 entry->use_cnt++; 2113 return entry; 2114 } 2115 } 2116 2117 return NULL; 2118 } 2119 2120 /** 2121 * irdma_next_iw_state - modify qp state 2122 * @iwqp: iwarp qp to modify 2123 * @state: next state for qp 2124 * @del_hash: del hash 2125 * @term: term message 2126 * @termlen: length of term message 2127 */ 2128 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2129 u8 termlen) 2130 { 2131 struct irdma_modify_qp_info info = {}; 2132 2133 info.next_iwarp_state = state; 2134 info.remove_hash_idx = del_hash; 2135 info.cq_num_valid = true; 2136 info.arp_cache_idx_valid = true; 2137 info.dont_send_term = true; 2138 info.dont_send_fin = true; 2139 info.termlen = termlen; 2140 2141 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2142 info.dont_send_term = false; 2143 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2144 info.dont_send_fin = false; 2145 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2146 info.reset_tcp_conn = true; 2147 iwqp->hw_iwarp_state = state; 2148 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2149 iwqp->iwarp_state = info.next_iwarp_state; 2150 } 2151 2152 /** 2153 * irdma_del_local_mac_entry - remove a mac entry from the hw 2154 * table 2155 * @rf: RDMA PCI function 2156 * @idx: the index of the mac ip address to delete 2157 */ 2158 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2159 { 2160 struct irdma_cqp *iwcqp = &rf->cqp; 2161 struct irdma_cqp_request *cqp_request; 2162 struct cqp_cmds_info *cqp_info; 2163 2164 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2165 if (!cqp_request) 2166 return; 2167 2168 cqp_info = &cqp_request->info; 2169 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2170 cqp_info->post_sq = 1; 2171 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2172 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2173 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2174 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2175 2176 irdma_handle_cqp_op(rf, cqp_request); 2177 irdma_put_cqp_request(iwcqp, cqp_request); 2178 } 2179 2180 /** 2181 * irdma_add_local_mac_entry - add a mac ip address entry to the 2182 * hw table 2183 * @rf: RDMA PCI function 2184 * @mac_addr: pointer to mac address 2185 * @idx: the index of the mac ip address to add 2186 */ 2187 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2188 { 2189 struct irdma_local_mac_entry_info *info; 2190 struct irdma_cqp *iwcqp = &rf->cqp; 2191 struct irdma_cqp_request *cqp_request; 2192 struct cqp_cmds_info *cqp_info; 2193 int status; 2194 2195 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2196 if (!cqp_request) 2197 return -ENOMEM; 2198 2199 cqp_info = &cqp_request->info; 2200 cqp_info->post_sq = 1; 2201 info = &cqp_info->in.u.add_local_mac_entry.info; 2202 ether_addr_copy(info->mac_addr, mac_addr); 2203 info->entry_idx = idx; 2204 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2205 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2206 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2207 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2208 2209 status = irdma_handle_cqp_op(rf, cqp_request); 2210 irdma_put_cqp_request(iwcqp, cqp_request); 2211 2212 return status; 2213 } 2214 2215 /** 2216 * irdma_alloc_local_mac_entry - allocate a mac entry 2217 * @rf: RDMA PCI function 2218 * @mac_tbl_idx: the index of the new mac address 2219 * 2220 * Allocate a mac address entry and update the mac_tbl_idx 2221 * to hold the index of the newly created mac address 2222 * Return 0 if successful, otherwise return error 2223 */ 2224 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2225 { 2226 struct irdma_cqp *iwcqp = &rf->cqp; 2227 struct irdma_cqp_request *cqp_request; 2228 struct cqp_cmds_info *cqp_info; 2229 int status = 0; 2230 2231 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2232 if (!cqp_request) 2233 return -ENOMEM; 2234 2235 cqp_info = &cqp_request->info; 2236 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2237 cqp_info->post_sq = 1; 2238 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2239 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2240 status = irdma_handle_cqp_op(rf, cqp_request); 2241 if (!status) 2242 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2243 2244 irdma_put_cqp_request(iwcqp, cqp_request); 2245 2246 return status; 2247 } 2248 2249 /** 2250 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2251 * @iwdev: irdma device 2252 * @accel_local_port: port for apbvt 2253 * @add_port: add ordelete port 2254 */ 2255 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2256 u16 accel_local_port, bool add_port) 2257 { 2258 struct irdma_apbvt_info *info; 2259 struct irdma_cqp_request *cqp_request; 2260 struct cqp_cmds_info *cqp_info; 2261 int status; 2262 2263 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2264 if (!cqp_request) 2265 return -ENOMEM; 2266 2267 cqp_info = &cqp_request->info; 2268 info = &cqp_info->in.u.manage_apbvt_entry.info; 2269 memset(info, 0, sizeof(*info)); 2270 info->add = add_port; 2271 info->port = accel_local_port; 2272 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2273 cqp_info->post_sq = 1; 2274 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2275 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2276 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", 2277 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2278 2279 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2280 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2281 2282 return status; 2283 } 2284 2285 /** 2286 * irdma_add_apbvt - add tcp port to HW apbvt table 2287 * @iwdev: irdma device 2288 * @port: port for apbvt 2289 */ 2290 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2291 { 2292 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2293 struct irdma_apbvt_entry *entry; 2294 unsigned long flags; 2295 2296 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2297 entry = irdma_lookup_apbvt_entry(cm_core, port); 2298 if (entry) { 2299 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2300 return entry; 2301 } 2302 2303 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2304 if (!entry) { 2305 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2306 return NULL; 2307 } 2308 2309 entry->port = port; 2310 entry->use_cnt = 1; 2311 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2312 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2313 2314 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2315 kfree(entry); 2316 return NULL; 2317 } 2318 2319 return entry; 2320 } 2321 2322 /** 2323 * irdma_del_apbvt - delete tcp port from HW apbvt table 2324 * @iwdev: irdma device 2325 * @entry: apbvt entry object 2326 */ 2327 void irdma_del_apbvt(struct irdma_device *iwdev, 2328 struct irdma_apbvt_entry *entry) 2329 { 2330 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2331 unsigned long flags; 2332 2333 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2334 if (--entry->use_cnt) { 2335 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2336 return; 2337 } 2338 2339 hash_del(&entry->hlist); 2340 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to 2341 * protect against race where add APBVT CQP can race ahead of the delete 2342 * APBVT for same port. 2343 */ 2344 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2345 kfree(entry); 2346 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2347 } 2348 2349 /** 2350 * irdma_manage_arp_cache - manage hw arp cache 2351 * @rf: RDMA PCI function 2352 * @mac_addr: mac address ptr 2353 * @ip_addr: ip addr for arp cache 2354 * @ipv4: flag inicating IPv4 2355 * @action: add, delete or modify 2356 */ 2357 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 2358 const unsigned char *mac_addr, 2359 u32 *ip_addr, bool ipv4, u32 action) 2360 { 2361 struct irdma_add_arp_cache_entry_info *info; 2362 struct irdma_cqp_request *cqp_request; 2363 struct cqp_cmds_info *cqp_info; 2364 int arp_index; 2365 2366 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action); 2367 if (arp_index == -1) 2368 return; 2369 2370 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2371 if (!cqp_request) 2372 return; 2373 2374 cqp_info = &cqp_request->info; 2375 if (action == IRDMA_ARP_ADD) { 2376 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2377 info = &cqp_info->in.u.add_arp_cache_entry.info; 2378 memset(info, 0, sizeof(*info)); 2379 info->arp_index = (u16)arp_index; 2380 info->permanent = true; 2381 ether_addr_copy(info->mac_addr, mac_addr); 2382 cqp_info->in.u.add_arp_cache_entry.scratch = 2383 (uintptr_t)cqp_request; 2384 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2385 } else { 2386 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2387 cqp_info->in.u.del_arp_cache_entry.scratch = 2388 (uintptr_t)cqp_request; 2389 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2390 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2391 } 2392 2393 cqp_info->post_sq = 1; 2394 irdma_handle_cqp_op(rf, cqp_request); 2395 irdma_put_cqp_request(&rf->cqp, cqp_request); 2396 } 2397 2398 /** 2399 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2400 * @cqp_request: qhash cqp completion 2401 */ 2402 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2403 { 2404 struct irdma_cm_node *cm_node = cqp_request->param; 2405 2406 irdma_send_syn(cm_node, 1); 2407 irdma_rem_ref_cm_node(cm_node); 2408 } 2409 2410 /** 2411 * irdma_manage_qhash - add or modify qhash 2412 * @iwdev: irdma device 2413 * @cminfo: cm info for qhash 2414 * @etype: type (syn or quad) 2415 * @mtype: type of qhash 2416 * @cmnode: cmnode associated with connection 2417 * @wait: wait for completion 2418 */ 2419 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2420 enum irdma_quad_entry_type etype, 2421 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2422 bool wait) 2423 { 2424 struct irdma_qhash_table_info *info; 2425 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2426 struct irdma_cqp_request *cqp_request; 2427 struct cqp_cmds_info *cqp_info; 2428 struct irdma_cm_node *cm_node = cmnode; 2429 int status; 2430 2431 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2432 if (!cqp_request) 2433 return -ENOMEM; 2434 2435 cqp_info = &cqp_request->info; 2436 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2437 memset(info, 0, sizeof(*info)); 2438 info->vsi = &iwdev->vsi; 2439 info->manage = mtype; 2440 info->entry_type = etype; 2441 if (cminfo->vlan_id < VLAN_N_VID) { 2442 info->vlan_valid = true; 2443 info->vlan_id = cminfo->vlan_id; 2444 } else { 2445 info->vlan_valid = false; 2446 } 2447 info->ipv4_valid = cminfo->ipv4; 2448 info->user_pri = cminfo->user_pri; 2449 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 2450 info->qp_num = cminfo->qh_qpid; 2451 info->dest_port = cminfo->loc_port; 2452 info->dest_ip[0] = cminfo->loc_addr[0]; 2453 info->dest_ip[1] = cminfo->loc_addr[1]; 2454 info->dest_ip[2] = cminfo->loc_addr[2]; 2455 info->dest_ip[3] = cminfo->loc_addr[3]; 2456 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2457 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2458 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2459 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2460 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2461 info->src_port = cminfo->rem_port; 2462 info->src_ip[0] = cminfo->rem_addr[0]; 2463 info->src_ip[1] = cminfo->rem_addr[1]; 2464 info->src_ip[2] = cminfo->rem_addr[2]; 2465 info->src_ip[3] = cminfo->rem_addr[3]; 2466 } 2467 if (cmnode) { 2468 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2469 cqp_request->param = cmnode; 2470 if (!wait) 2471 refcount_inc(&cm_node->refcnt); 2472 } 2473 if (info->ipv4_valid) 2474 ibdev_dbg(&iwdev->ibdev, 2475 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2476 (!mtype) ? "DELETE" : "ADD", 2477 __builtin_return_address(0), info->dest_port, 2478 info->src_port, info->dest_ip, info->src_ip, 2479 info->mac_addr, cminfo->vlan_id, 2480 cmnode ? cmnode : NULL); 2481 else 2482 ibdev_dbg(&iwdev->ibdev, 2483 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2484 (!mtype) ? "DELETE" : "ADD", 2485 __builtin_return_address(0), info->dest_port, 2486 info->src_port, info->dest_ip, info->src_ip, 2487 info->mac_addr, cminfo->vlan_id, 2488 cmnode ? cmnode : NULL); 2489 2490 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2491 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2492 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2493 cqp_info->post_sq = 1; 2494 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2495 if (status && cm_node && !wait) 2496 irdma_rem_ref_cm_node(cm_node); 2497 2498 irdma_put_cqp_request(iwcqp, cqp_request); 2499 2500 return status; 2501 } 2502 2503 /** 2504 * irdma_hw_flush_wqes_callback - Check return code after flush 2505 * @cqp_request: qhash cqp completion 2506 */ 2507 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request) 2508 { 2509 struct irdma_qp_flush_info *hw_info; 2510 struct irdma_sc_qp *qp; 2511 struct irdma_qp *iwqp; 2512 struct cqp_cmds_info *cqp_info; 2513 2514 cqp_info = &cqp_request->info; 2515 hw_info = &cqp_info->in.u.qp_flush_wqes.info; 2516 qp = cqp_info->in.u.qp_flush_wqes.qp; 2517 iwqp = qp->qp_uk.back_qp; 2518 2519 if (cqp_request->compl_info.maj_err_code) 2520 return; 2521 2522 if (hw_info->rq && 2523 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2524 cqp_request->compl_info.min_err_code == 0)) { 2525 /* RQ WQE flush was requested but did not happen */ 2526 qp->qp_uk.rq_flush_complete = true; 2527 } 2528 if (hw_info->sq && 2529 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2530 cqp_request->compl_info.min_err_code == 0)) { 2531 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2532 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work", 2533 qp->qp_uk.qp_id); 2534 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2535 } 2536 qp->qp_uk.sq_flush_complete = true; 2537 } 2538 } 2539 2540 /** 2541 * irdma_hw_flush_wqes - flush qp's wqe 2542 * @rf: RDMA PCI function 2543 * @qp: hardware control qp 2544 * @info: info for flush 2545 * @wait: flag wait for completion 2546 */ 2547 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2548 struct irdma_qp_flush_info *info, bool wait) 2549 { 2550 int status; 2551 struct irdma_qp_flush_info *hw_info; 2552 struct irdma_cqp_request *cqp_request; 2553 struct cqp_cmds_info *cqp_info; 2554 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2555 2556 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2557 if (!cqp_request) 2558 return -ENOMEM; 2559 2560 cqp_info = &cqp_request->info; 2561 if (!wait) 2562 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback; 2563 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2564 memcpy(hw_info, info, sizeof(*hw_info)); 2565 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2566 cqp_info->post_sq = 1; 2567 cqp_info->in.u.qp_flush_wqes.qp = qp; 2568 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2569 status = irdma_handle_cqp_op(rf, cqp_request); 2570 if (status) { 2571 qp->qp_uk.sq_flush_complete = true; 2572 qp->qp_uk.rq_flush_complete = true; 2573 irdma_put_cqp_request(&rf->cqp, cqp_request); 2574 return status; 2575 } 2576 2577 if (!wait || cqp_request->compl_info.maj_err_code) 2578 goto put_cqp; 2579 2580 if (info->rq) { 2581 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2582 cqp_request->compl_info.min_err_code == 0) { 2583 /* RQ WQE flush was requested but did not happen */ 2584 qp->qp_uk.rq_flush_complete = true; 2585 } 2586 } 2587 if (info->sq) { 2588 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2589 cqp_request->compl_info.min_err_code == 0) { 2590 /* 2591 * Handling case where WQE is posted to empty SQ when 2592 * flush has not completed 2593 */ 2594 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2595 struct irdma_cqp_request *new_req; 2596 2597 if (!qp->qp_uk.sq_flush_complete) 2598 goto put_cqp; 2599 qp->qp_uk.sq_flush_complete = false; 2600 qp->flush_sq = false; 2601 2602 info->rq = false; 2603 info->sq = true; 2604 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 2605 if (!new_req) { 2606 status = -ENOMEM; 2607 goto put_cqp; 2608 } 2609 cqp_info = &new_req->info; 2610 hw_info = &new_req->info.in.u.qp_flush_wqes.info; 2611 memcpy(hw_info, info, sizeof(*hw_info)); 2612 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2613 cqp_info->post_sq = 1; 2614 cqp_info->in.u.qp_flush_wqes.qp = qp; 2615 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req; 2616 2617 status = irdma_handle_cqp_op(rf, new_req); 2618 if (new_req->compl_info.maj_err_code || 2619 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2620 status) { 2621 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d", 2622 iwqp->ibqp.qp_num); 2623 qp->qp_uk.sq_flush_complete = false; 2624 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2625 } 2626 irdma_put_cqp_request(&rf->cqp, new_req); 2627 } else { 2628 /* SQ WQE flush was requested but did not happen */ 2629 qp->qp_uk.sq_flush_complete = true; 2630 } 2631 } else { 2632 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) 2633 qp->qp_uk.sq_flush_complete = true; 2634 } 2635 } 2636 2637 ibdev_dbg(&rf->iwdev->ibdev, 2638 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2639 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2640 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2641 cqp_request->compl_info.maj_err_code, 2642 cqp_request->compl_info.min_err_code); 2643 put_cqp: 2644 irdma_put_cqp_request(&rf->cqp, cqp_request); 2645 2646 return status; 2647 } 2648 2649 /** 2650 * irdma_gen_ae - generate AE 2651 * @rf: RDMA PCI function 2652 * @qp: qp associated with AE 2653 * @info: info for ae 2654 * @wait: wait for completion 2655 */ 2656 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2657 struct irdma_gen_ae_info *info, bool wait) 2658 { 2659 struct irdma_gen_ae_info *ae_info; 2660 struct irdma_cqp_request *cqp_request; 2661 struct cqp_cmds_info *cqp_info; 2662 2663 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2664 if (!cqp_request) 2665 return; 2666 2667 cqp_info = &cqp_request->info; 2668 ae_info = &cqp_request->info.in.u.gen_ae.info; 2669 memcpy(ae_info, info, sizeof(*ae_info)); 2670 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2671 cqp_info->post_sq = 1; 2672 cqp_info->in.u.gen_ae.qp = qp; 2673 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2674 2675 irdma_handle_cqp_op(rf, cqp_request); 2676 irdma_put_cqp_request(&rf->cqp, cqp_request); 2677 } 2678 2679 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2680 { 2681 struct irdma_qp_flush_info info = {}; 2682 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2683 u8 flush_code = iwqp->sc_qp.flush_code; 2684 2685 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2686 return; 2687 2688 /* Set flush info fields*/ 2689 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2690 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2691 2692 /* Generate userflush errors in CQE */ 2693 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2694 info.sq_minor_code = FLUSH_GENERAL_ERR; 2695 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2696 info.rq_minor_code = FLUSH_GENERAL_ERR; 2697 info.userflushcode = true; 2698 2699 if (flush_mask & IRDMA_REFLUSH) { 2700 if (info.sq) 2701 iwqp->sc_qp.flush_sq = false; 2702 if (info.rq) 2703 iwqp->sc_qp.flush_rq = false; 2704 } else { 2705 if (flush_code) { 2706 if (info.sq && iwqp->sc_qp.sq_flush_code) 2707 info.sq_minor_code = flush_code; 2708 if (info.rq && iwqp->sc_qp.rq_flush_code) 2709 info.rq_minor_code = flush_code; 2710 } 2711 if (!iwqp->user_mode) 2712 queue_delayed_work(iwqp->iwdev->cleanup_wq, 2713 &iwqp->dwork_flush, 2714 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS)); 2715 } 2716 2717 /* Issue flush */ 2718 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2719 flush_mask & IRDMA_FLUSH_WAIT); 2720 iwqp->flush_issued = true; 2721 } 2722