1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "main.h" 4 5 static struct irdma_rsrc_limits rsrc_limits_table[] = { 6 [0] = { 7 .qplimit = SZ_128, 8 }, 9 [1] = { 10 .qplimit = SZ_1K, 11 }, 12 [2] = { 13 .qplimit = SZ_2K, 14 }, 15 [3] = { 16 .qplimit = SZ_4K, 17 }, 18 [4] = { 19 .qplimit = SZ_16K, 20 }, 21 [5] = { 22 .qplimit = SZ_64K, 23 }, 24 [6] = { 25 .qplimit = SZ_128K, 26 }, 27 [7] = { 28 .qplimit = SZ_256K, 29 }, 30 }; 31 32 /* types of hmc objects */ 33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 34 IRDMA_HMC_IW_QP, 35 IRDMA_HMC_IW_CQ, 36 IRDMA_HMC_IW_HTE, 37 IRDMA_HMC_IW_ARP, 38 IRDMA_HMC_IW_APBVT_ENTRY, 39 IRDMA_HMC_IW_MR, 40 IRDMA_HMC_IW_XF, 41 IRDMA_HMC_IW_XFFL, 42 IRDMA_HMC_IW_Q1, 43 IRDMA_HMC_IW_Q1FL, 44 IRDMA_HMC_IW_PBLE, 45 IRDMA_HMC_IW_TIMER, 46 IRDMA_HMC_IW_FSIMC, 47 IRDMA_HMC_IW_FSIAV, 48 IRDMA_HMC_IW_RRF, 49 IRDMA_HMC_IW_RRFFL, 50 IRDMA_HMC_IW_HDR, 51 IRDMA_HMC_IW_MD, 52 IRDMA_HMC_IW_OOISC, 53 IRDMA_HMC_IW_OOISCFFL, 54 }; 55 56 /** 57 * irdma_iwarp_ce_handler - handle iwarp completions 58 * @iwcq: iwarp cq receiving event 59 */ 60 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 61 { 62 struct irdma_cq *cq = iwcq->back_cq; 63 64 if (!cq->user_mode) 65 atomic_set(&cq->armed, 0); 66 if (cq->ibcq.comp_handler) 67 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 68 } 69 70 /** 71 * irdma_puda_ce_handler - handle puda completion events 72 * @rf: RDMA PCI function 73 * @cq: puda completion q for event 74 */ 75 static void irdma_puda_ce_handler(struct irdma_pci_f *rf, 76 struct irdma_sc_cq *cq) 77 { 78 struct irdma_sc_dev *dev = &rf->sc_dev; 79 u32 compl_error; 80 int status; 81 82 do { 83 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 84 if (status == -ENOENT) 85 break; 86 if (status) { 87 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); 88 break; 89 } 90 if (compl_error) { 91 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n", 92 compl_error); 93 break; 94 } 95 } while (1); 96 97 irdma_sc_ccq_arm(cq); 98 } 99 100 /** 101 * irdma_process_ceq - handle ceq for completions 102 * @rf: RDMA PCI function 103 * @ceq: ceq having cq for completion 104 */ 105 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 106 { 107 struct irdma_sc_dev *dev = &rf->sc_dev; 108 struct irdma_sc_ceq *sc_ceq; 109 struct irdma_sc_cq *cq; 110 unsigned long flags; 111 112 sc_ceq = &ceq->sc_ceq; 113 do { 114 spin_lock_irqsave(&ceq->ce_lock, flags); 115 cq = irdma_sc_process_ceq(dev, sc_ceq); 116 if (!cq) { 117 spin_unlock_irqrestore(&ceq->ce_lock, flags); 118 break; 119 } 120 121 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 122 irdma_iwarp_ce_handler(cq); 123 124 spin_unlock_irqrestore(&ceq->ce_lock, flags); 125 126 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 127 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 128 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 129 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 130 irdma_puda_ce_handler(rf, cq); 131 } while (1); 132 } 133 134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp, 135 struct irdma_aeqe_info *info) 136 { 137 qp->sq_flush_code = info->sq; 138 qp->rq_flush_code = info->rq; 139 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 140 141 switch (info->ae_id) { 142 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 143 case IRDMA_AE_AMP_INVALID_STAG: 144 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 145 case IRDMA_AE_AMP_UNALLOCATED_STAG: 146 case IRDMA_AE_AMP_BAD_PD: 147 case IRDMA_AE_AMP_BAD_QP: 148 case IRDMA_AE_AMP_BAD_STAG_KEY: 149 case IRDMA_AE_AMP_BAD_STAG_INDEX: 150 case IRDMA_AE_AMP_TO_WRAP: 151 case IRDMA_AE_PRIV_OPERATION_DENIED: 152 qp->flush_code = FLUSH_PROT_ERR; 153 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 154 break; 155 case IRDMA_AE_UDA_XMIT_BAD_PD: 156 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 157 qp->flush_code = FLUSH_LOC_QP_OP_ERR; 158 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 159 break; 160 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 161 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 162 case IRDMA_AE_UDA_L4LEN_INVALID: 163 case IRDMA_AE_DDP_UBE_INVALID_MO: 164 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 165 qp->flush_code = FLUSH_LOC_LEN_ERR; 166 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 167 break; 168 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 169 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 170 qp->flush_code = FLUSH_REM_ACCESS_ERR; 171 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 172 break; 173 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 174 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 175 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 176 case IRDMA_AE_IB_REMOTE_OP_ERROR: 177 qp->flush_code = FLUSH_REM_OP_ERR; 178 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 179 break; 180 case IRDMA_AE_LCE_QP_CATASTROPHIC: 181 qp->flush_code = FLUSH_FATAL_ERR; 182 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 183 break; 184 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 185 qp->flush_code = FLUSH_GENERAL_ERR; 186 break; 187 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 188 qp->flush_code = FLUSH_RETRY_EXC_ERR; 189 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 190 break; 191 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 192 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 193 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 194 qp->flush_code = FLUSH_MW_BIND_ERR; 195 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 196 break; 197 case IRDMA_AE_IB_INVALID_REQUEST: 198 qp->flush_code = FLUSH_REM_INV_REQ_ERR; 199 qp->event_type = IRDMA_QP_EVENT_REQ_ERR; 200 break; 201 default: 202 qp->flush_code = FLUSH_GENERAL_ERR; 203 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 204 break; 205 } 206 } 207 208 /** 209 * irdma_process_aeq - handle aeq events 210 * @rf: RDMA PCI function 211 */ 212 static void irdma_process_aeq(struct irdma_pci_f *rf) 213 { 214 struct irdma_sc_dev *dev = &rf->sc_dev; 215 struct irdma_aeq *aeq = &rf->aeq; 216 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 217 struct irdma_aeqe_info aeinfo; 218 struct irdma_aeqe_info *info = &aeinfo; 219 int ret; 220 struct irdma_qp *iwqp = NULL; 221 struct irdma_sc_cq *cq = NULL; 222 struct irdma_cq *iwcq = NULL; 223 struct irdma_sc_qp *qp = NULL; 224 struct irdma_qp_host_ctx_info *ctx_info = NULL; 225 struct irdma_device *iwdev = rf->iwdev; 226 unsigned long flags; 227 228 u32 aeqcnt = 0; 229 230 if (!sc_aeq->size) 231 return; 232 233 do { 234 memset(info, 0, sizeof(*info)); 235 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 236 if (ret) 237 break; 238 239 aeqcnt++; 240 ibdev_dbg(&iwdev->ibdev, 241 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 242 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 243 info->iwarp_state, info->ae_src); 244 245 if (info->qp) { 246 spin_lock_irqsave(&rf->qptable_lock, flags); 247 iwqp = rf->qp_table[info->qp_cq_id]; 248 if (!iwqp) { 249 spin_unlock_irqrestore(&rf->qptable_lock, 250 flags); 251 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 252 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 253 wake_up(&iwdev->suspend_wq); 254 continue; 255 } 256 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", 257 info->qp_cq_id); 258 continue; 259 } 260 irdma_qp_add_ref(&iwqp->ibqp); 261 spin_unlock_irqrestore(&rf->qptable_lock, flags); 262 qp = &iwqp->sc_qp; 263 spin_lock_irqsave(&iwqp->lock, flags); 264 iwqp->hw_tcp_state = info->tcp_state; 265 iwqp->hw_iwarp_state = info->iwarp_state; 266 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 267 iwqp->last_aeq = info->ae_id; 268 spin_unlock_irqrestore(&iwqp->lock, flags); 269 ctx_info = &iwqp->ctx_info; 270 } else { 271 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 272 continue; 273 } 274 275 switch (info->ae_id) { 276 struct irdma_cm_node *cm_node; 277 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 278 cm_node = iwqp->cm_node; 279 if (cm_node->accept_pend) { 280 atomic_dec(&cm_node->listener->pend_accepts_cnt); 281 cm_node->accept_pend = 0; 282 } 283 iwqp->rts_ae_rcvd = 1; 284 wake_up_interruptible(&iwqp->waitq); 285 break; 286 case IRDMA_AE_LLP_FIN_RECEIVED: 287 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 288 if (qp->term_flags) 289 break; 290 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 291 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 292 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT && 293 iwqp->ibqp_state == IB_QPS_RTS) { 294 irdma_next_iw_state(iwqp, 295 IRDMA_QP_STATE_CLOSING, 296 0, 0, 0); 297 irdma_cm_disconn(iwqp); 298 } 299 irdma_schedule_cm_timer(iwqp->cm_node, 300 (struct irdma_puda_buf *)iwqp, 301 IRDMA_TIMER_TYPE_CLOSE, 302 1, 0); 303 } 304 break; 305 case IRDMA_AE_LLP_CLOSE_COMPLETE: 306 if (qp->term_flags) 307 irdma_terminate_done(qp, 0); 308 else 309 irdma_cm_disconn(iwqp); 310 break; 311 case IRDMA_AE_BAD_CLOSE: 312 case IRDMA_AE_RESET_SENT: 313 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 314 0); 315 irdma_cm_disconn(iwqp); 316 break; 317 case IRDMA_AE_LLP_CONNECTION_RESET: 318 if (atomic_read(&iwqp->close_timer_started)) 319 break; 320 irdma_cm_disconn(iwqp); 321 break; 322 case IRDMA_AE_QP_SUSPEND_COMPLETE: 323 if (iwqp->iwdev->vsi.tc_change_pending) { 324 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 325 wake_up(&iwqp->iwdev->suspend_wq); 326 } 327 break; 328 case IRDMA_AE_TERMINATE_SENT: 329 irdma_terminate_send_fin(qp); 330 break; 331 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 332 irdma_terminate_received(qp, info); 333 break; 334 case IRDMA_AE_CQ_OPERATION_ERROR: 335 ibdev_err(&iwdev->ibdev, 336 "Processing an iWARP related AE for CQ misc = 0x%04X\n", 337 info->ae_id); 338 cq = (struct irdma_sc_cq *)(unsigned long) 339 info->compl_ctx; 340 341 iwcq = cq->back_cq; 342 343 if (iwcq->ibcq.event_handler) { 344 struct ib_event ibevent; 345 346 ibevent.device = iwcq->ibcq.device; 347 ibevent.event = IB_EVENT_CQ_ERR; 348 ibevent.element.cq = &iwcq->ibcq; 349 iwcq->ibcq.event_handler(&ibevent, 350 iwcq->ibcq.cq_context); 351 } 352 break; 353 case IRDMA_AE_RESET_NOT_SENT: 354 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 355 case IRDMA_AE_RESOURCE_EXHAUSTION: 356 break; 357 case IRDMA_AE_PRIV_OPERATION_DENIED: 358 case IRDMA_AE_STAG_ZERO_INVALID: 359 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 360 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 361 case IRDMA_AE_DDP_UBE_INVALID_MO: 362 case IRDMA_AE_DDP_UBE_INVALID_QN: 363 case IRDMA_AE_DDP_NO_L_BIT: 364 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 365 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 366 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 367 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 368 case IRDMA_AE_INVALID_ARP_ENTRY: 369 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 370 case IRDMA_AE_STALE_ARP_ENTRY: 371 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 372 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 373 case IRDMA_AE_LLP_SYN_RECEIVED: 374 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 375 case IRDMA_AE_LCE_QP_CATASTROPHIC: 376 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 377 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 378 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 379 default: 380 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n", 381 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 382 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 383 ctx_info->roce_info->err_rq_idx_valid = info->rq; 384 if (info->rq) { 385 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 386 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 387 ctx_info); 388 } 389 irdma_set_flush_fields(qp, info); 390 irdma_cm_disconn(iwqp); 391 break; 392 } 393 ctx_info->iwarp_info->err_rq_idx_valid = info->rq; 394 if (info->rq) { 395 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 396 ctx_info->tcp_info_valid = false; 397 ctx_info->iwarp_info_valid = true; 398 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 399 ctx_info); 400 } 401 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 402 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 403 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 404 irdma_cm_disconn(iwqp); 405 } else { 406 irdma_terminate_connection(qp, info); 407 } 408 break; 409 } 410 if (info->qp) 411 irdma_qp_rem_ref(&iwqp->ibqp); 412 } while (1); 413 414 if (aeqcnt) 415 irdma_sc_repost_aeq_entries(dev, aeqcnt); 416 } 417 418 /** 419 * irdma_ena_intr - set up device interrupts 420 * @dev: hardware control device structure 421 * @msix_id: id of the interrupt to be enabled 422 */ 423 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 424 { 425 dev->irq_ops->irdma_en_irq(dev, msix_id); 426 } 427 428 /** 429 * irdma_dpc - tasklet for aeq and ceq 0 430 * @t: tasklet_struct ptr 431 */ 432 static void irdma_dpc(struct tasklet_struct *t) 433 { 434 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 435 436 if (rf->msix_shared) 437 irdma_process_ceq(rf, rf->ceqlist); 438 irdma_process_aeq(rf); 439 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 440 } 441 442 /** 443 * irdma_ceq_dpc - dpc handler for CEQ 444 * @t: tasklet_struct ptr 445 */ 446 static void irdma_ceq_dpc(struct tasklet_struct *t) 447 { 448 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 449 struct irdma_pci_f *rf = iwceq->rf; 450 451 irdma_process_ceq(rf, iwceq); 452 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 453 } 454 455 /** 456 * irdma_save_msix_info - copy msix vector information to iwarp device 457 * @rf: RDMA PCI function 458 * 459 * Allocate iwdev msix table and copy the msix info to the table 460 * Return 0 if successful, otherwise return error 461 */ 462 static int irdma_save_msix_info(struct irdma_pci_f *rf) 463 { 464 struct irdma_qvlist_info *iw_qvlist; 465 struct irdma_qv_info *iw_qvinfo; 466 struct msix_entry *pmsix; 467 u32 ceq_idx; 468 u32 i; 469 size_t size; 470 471 if (!rf->msix_count) 472 return -EINVAL; 473 474 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 475 size += struct_size(iw_qvlist, qv_info, rf->msix_count); 476 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 477 if (!rf->iw_msixtbl) 478 return -ENOMEM; 479 480 rf->iw_qvlist = (struct irdma_qvlist_info *) 481 (&rf->iw_msixtbl[rf->msix_count]); 482 iw_qvlist = rf->iw_qvlist; 483 iw_qvinfo = iw_qvlist->qv_info; 484 iw_qvlist->num_vectors = rf->msix_count; 485 if (rf->msix_count <= num_online_cpus()) 486 rf->msix_shared = true; 487 else if (rf->msix_count > num_online_cpus() + 1) 488 rf->msix_count = num_online_cpus() + 1; 489 490 pmsix = rf->msix_entries; 491 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 492 rf->iw_msixtbl[i].idx = pmsix->entry; 493 rf->iw_msixtbl[i].irq = pmsix->vector; 494 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 495 if (!i) { 496 iw_qvinfo->aeq_idx = 0; 497 if (rf->msix_shared) 498 iw_qvinfo->ceq_idx = ceq_idx++; 499 else 500 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 501 } else { 502 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 503 iw_qvinfo->ceq_idx = ceq_idx++; 504 } 505 iw_qvinfo->itr_idx = 3; 506 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 507 pmsix++; 508 } 509 510 return 0; 511 } 512 513 /** 514 * irdma_irq_handler - interrupt handler for aeq and ceq0 515 * @irq: Interrupt request number 516 * @data: RDMA PCI function 517 */ 518 static irqreturn_t irdma_irq_handler(int irq, void *data) 519 { 520 struct irdma_pci_f *rf = data; 521 522 tasklet_schedule(&rf->dpc_tasklet); 523 524 return IRQ_HANDLED; 525 } 526 527 /** 528 * irdma_ceq_handler - interrupt handler for ceq 529 * @irq: interrupt request number 530 * @data: ceq pointer 531 */ 532 static irqreturn_t irdma_ceq_handler(int irq, void *data) 533 { 534 struct irdma_ceq *iwceq = data; 535 536 if (iwceq->irq != irq) 537 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n", 538 iwceq->irq, irq); 539 tasklet_schedule(&iwceq->dpc_tasklet); 540 541 return IRQ_HANDLED; 542 } 543 544 /** 545 * irdma_destroy_irq - destroy device interrupts 546 * @rf: RDMA PCI function 547 * @msix_vec: msix vector to disable irq 548 * @dev_id: parameter to pass to free_irq (used during irq setup) 549 * 550 * The function is called when destroying aeq/ceq 551 */ 552 static void irdma_destroy_irq(struct irdma_pci_f *rf, 553 struct irdma_msix_vector *msix_vec, void *dev_id) 554 { 555 struct irdma_sc_dev *dev = &rf->sc_dev; 556 557 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 558 irq_update_affinity_hint(msix_vec->irq, NULL); 559 free_irq(msix_vec->irq, dev_id); 560 } 561 562 /** 563 * irdma_destroy_cqp - destroy control qp 564 * @rf: RDMA PCI function 565 * @free_hwcqp: 1 if hw cqp should be freed 566 * 567 * Issue destroy cqp request and 568 * free the resources associated with the cqp 569 */ 570 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 571 { 572 struct irdma_sc_dev *dev = &rf->sc_dev; 573 struct irdma_cqp *cqp = &rf->cqp; 574 int status = 0; 575 576 if (rf->cqp_cmpl_wq) 577 destroy_workqueue(rf->cqp_cmpl_wq); 578 if (free_hwcqp) 579 status = irdma_sc_cqp_destroy(dev->cqp); 580 if (status) 581 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); 582 583 irdma_cleanup_pending_cqp_op(rf); 584 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, 585 cqp->sq.pa); 586 cqp->sq.va = NULL; 587 kfree(cqp->scratch_array); 588 cqp->scratch_array = NULL; 589 kfree(cqp->cqp_requests); 590 cqp->cqp_requests = NULL; 591 } 592 593 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 594 { 595 struct irdma_aeq *aeq = &rf->aeq; 596 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 597 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 598 599 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 600 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 601 vfree(aeq->mem.va); 602 } 603 604 /** 605 * irdma_destroy_aeq - destroy aeq 606 * @rf: RDMA PCI function 607 * 608 * Issue a destroy aeq request and 609 * free the resources associated with the aeq 610 * The function is called during driver unload 611 */ 612 static void irdma_destroy_aeq(struct irdma_pci_f *rf) 613 { 614 struct irdma_sc_dev *dev = &rf->sc_dev; 615 struct irdma_aeq *aeq = &rf->aeq; 616 int status = -EBUSY; 617 618 if (!rf->msix_shared) { 619 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 620 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 621 } 622 if (rf->reset) 623 goto exit; 624 625 aeq->sc_aeq.size = 0; 626 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 627 if (status) 628 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); 629 630 exit: 631 if (aeq->virtual_map) { 632 irdma_destroy_virt_aeq(rf); 633 } else { 634 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 635 aeq->mem.pa); 636 aeq->mem.va = NULL; 637 } 638 } 639 640 /** 641 * irdma_destroy_ceq - destroy ceq 642 * @rf: RDMA PCI function 643 * @iwceq: ceq to be destroyed 644 * 645 * Issue a destroy ceq request and 646 * free the resources associated with the ceq 647 */ 648 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 649 { 650 struct irdma_sc_dev *dev = &rf->sc_dev; 651 int status; 652 653 if (rf->reset) 654 goto exit; 655 656 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 657 if (status) { 658 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); 659 goto exit; 660 } 661 662 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 663 if (status) 664 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", 665 status); 666 exit: 667 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, 668 iwceq->mem.pa); 669 iwceq->mem.va = NULL; 670 } 671 672 /** 673 * irdma_del_ceq_0 - destroy ceq 0 674 * @rf: RDMA PCI function 675 * 676 * Disable the ceq 0 interrupt and destroy the ceq 0 677 */ 678 static void irdma_del_ceq_0(struct irdma_pci_f *rf) 679 { 680 struct irdma_ceq *iwceq = rf->ceqlist; 681 struct irdma_msix_vector *msix_vec; 682 683 if (rf->msix_shared) { 684 msix_vec = &rf->iw_msixtbl[0]; 685 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 686 msix_vec->ceq_id, 687 msix_vec->idx, false); 688 irdma_destroy_irq(rf, msix_vec, rf); 689 } else { 690 msix_vec = &rf->iw_msixtbl[1]; 691 irdma_destroy_irq(rf, msix_vec, iwceq); 692 } 693 694 irdma_destroy_ceq(rf, iwceq); 695 rf->sc_dev.ceq_valid = false; 696 rf->ceqs_count = 0; 697 } 698 699 /** 700 * irdma_del_ceqs - destroy all ceq's except CEQ 0 701 * @rf: RDMA PCI function 702 * 703 * Go through all of the device ceq's, except 0, and for each 704 * ceq disable the ceq interrupt and destroy the ceq 705 */ 706 static void irdma_del_ceqs(struct irdma_pci_f *rf) 707 { 708 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 709 struct irdma_msix_vector *msix_vec; 710 u32 i = 0; 711 712 if (rf->msix_shared) 713 msix_vec = &rf->iw_msixtbl[1]; 714 else 715 msix_vec = &rf->iw_msixtbl[2]; 716 717 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 718 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 719 msix_vec->idx, false); 720 irdma_destroy_irq(rf, msix_vec, iwceq); 721 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 722 IRDMA_OP_CEQ_DESTROY); 723 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, 724 iwceq->mem.va, iwceq->mem.pa); 725 iwceq->mem.va = NULL; 726 } 727 rf->ceqs_count = 1; 728 } 729 730 /** 731 * irdma_destroy_ccq - destroy control cq 732 * @rf: RDMA PCI function 733 * 734 * Issue destroy ccq request and 735 * free the resources associated with the ccq 736 */ 737 static void irdma_destroy_ccq(struct irdma_pci_f *rf) 738 { 739 struct irdma_sc_dev *dev = &rf->sc_dev; 740 struct irdma_ccq *ccq = &rf->ccq; 741 int status = 0; 742 743 if (!rf->reset) 744 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 745 if (status) 746 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); 747 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, 748 ccq->mem_cq.pa); 749 ccq->mem_cq.va = NULL; 750 } 751 752 /** 753 * irdma_close_hmc_objects_type - delete hmc objects of a given type 754 * @dev: iwarp device 755 * @obj_type: the hmc object type to be deleted 756 * @hmc_info: host memory info struct 757 * @privileged: permission to close HMC objects 758 * @reset: true if called before reset 759 */ 760 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 761 enum irdma_hmc_rsrc_type obj_type, 762 struct irdma_hmc_info *hmc_info, 763 bool privileged, bool reset) 764 { 765 struct irdma_hmc_del_obj_info info = {}; 766 767 info.hmc_info = hmc_info; 768 info.rsrc_type = obj_type; 769 info.count = hmc_info->hmc_obj[obj_type].cnt; 770 info.privileged = privileged; 771 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 772 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", 773 obj_type); 774 } 775 776 /** 777 * irdma_del_hmc_objects - remove all device hmc objects 778 * @dev: iwarp device 779 * @hmc_info: hmc_info to free 780 * @privileged: permission to delete HMC objects 781 * @reset: true if called before reset 782 * @vers: hardware version 783 */ 784 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev, 785 struct irdma_hmc_info *hmc_info, bool privileged, 786 bool reset, enum irdma_vers vers) 787 { 788 unsigned int i; 789 790 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 791 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 792 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 793 hmc_info, privileged, reset); 794 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 795 break; 796 } 797 } 798 799 /** 800 * irdma_create_hmc_obj_type - create hmc object of a given type 801 * @dev: hardware control device structure 802 * @info: information for the hmc object to create 803 */ 804 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 805 struct irdma_hmc_create_obj_info *info) 806 { 807 return irdma_sc_create_hmc_obj(dev, info); 808 } 809 810 /** 811 * irdma_create_hmc_objs - create all hmc objects for the device 812 * @rf: RDMA PCI function 813 * @privileged: permission to create HMC objects 814 * @vers: HW version 815 * 816 * Create the device hmc objects and allocate hmc pages 817 * Return 0 if successful, otherwise clean up and return error 818 */ 819 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 820 enum irdma_vers vers) 821 { 822 struct irdma_sc_dev *dev = &rf->sc_dev; 823 struct irdma_hmc_create_obj_info info = {}; 824 int i, status = 0; 825 826 info.hmc_info = dev->hmc_info; 827 info.privileged = privileged; 828 info.entry_type = rf->sd_type; 829 830 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 831 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) 832 continue; 833 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 834 info.rsrc_type = iw_hmc_obj_types[i]; 835 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 836 info.add_sd_cnt = 0; 837 status = irdma_create_hmc_obj_type(dev, &info); 838 if (status) { 839 ibdev_dbg(to_ibdev(dev), 840 "ERR: create obj type %d status = %d\n", 841 iw_hmc_obj_types[i], status); 842 break; 843 } 844 } 845 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 846 break; 847 } 848 849 if (!status) 850 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 851 true, true); 852 853 while (i) { 854 i--; 855 /* destroy the hmc objects of a given type */ 856 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 857 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 858 dev->hmc_info, privileged, 859 false); 860 } 861 862 return status; 863 } 864 865 /** 866 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 867 * @rf: RDMA PCI function 868 * @memptr: points to the memory addresses 869 * @size: size of memory needed 870 * @mask: mask for the aligned memory 871 * 872 * Get aligned memory of the requested size and 873 * update the memptr to point to the new aligned memory 874 * Return 0 if successful, otherwise return no memory error 875 */ 876 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf, 877 struct irdma_dma_mem *memptr, u32 size, 878 u32 mask) 879 { 880 unsigned long va, newva; 881 unsigned long extra; 882 883 va = (unsigned long)rf->obj_next.va; 884 newva = va; 885 if (mask) 886 newva = ALIGN(va, (unsigned long)mask + 1ULL); 887 extra = newva - va; 888 memptr->va = (u8 *)va + extra; 889 memptr->pa = rf->obj_next.pa + extra; 890 memptr->size = size; 891 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 892 return -ENOMEM; 893 894 rf->obj_next.va = (u8 *)memptr->va + size; 895 rf->obj_next.pa = memptr->pa + size; 896 897 return 0; 898 } 899 900 /** 901 * irdma_create_cqp - create control qp 902 * @rf: RDMA PCI function 903 * 904 * Return 0, if the cqp and all the resources associated with it 905 * are successfully created, otherwise return error 906 */ 907 static int irdma_create_cqp(struct irdma_pci_f *rf) 908 { 909 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 910 struct irdma_dma_mem mem; 911 struct irdma_sc_dev *dev = &rf->sc_dev; 912 struct irdma_cqp_init_info cqp_init_info = {}; 913 struct irdma_cqp *cqp = &rf->cqp; 914 u16 maj_err, min_err; 915 int i, status; 916 917 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 918 if (!cqp->cqp_requests) 919 return -ENOMEM; 920 921 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 922 if (!cqp->scratch_array) { 923 kfree(cqp->cqp_requests); 924 return -ENOMEM; 925 } 926 927 dev->cqp = &cqp->sc_cqp; 928 dev->cqp->dev = dev; 929 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, 930 IRDMA_CQP_ALIGNMENT); 931 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, 932 &cqp->sq.pa, GFP_KERNEL); 933 if (!cqp->sq.va) { 934 kfree(cqp->scratch_array); 935 kfree(cqp->cqp_requests); 936 return -ENOMEM; 937 } 938 939 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 940 IRDMA_HOST_CTX_ALIGNMENT_M); 941 if (status) 942 goto exit; 943 944 dev->cqp->host_ctx_pa = mem.pa; 945 dev->cqp->host_ctx = mem.va; 946 /* populate the cqp init info */ 947 cqp_init_info.dev = dev; 948 cqp_init_info.sq_size = sqsize; 949 cqp_init_info.sq = cqp->sq.va; 950 cqp_init_info.sq_pa = cqp->sq.pa; 951 cqp_init_info.host_ctx_pa = mem.pa; 952 cqp_init_info.host_ctx = mem.va; 953 cqp_init_info.hmc_profile = rf->rsrc_profile; 954 cqp_init_info.scratch_array = cqp->scratch_array; 955 cqp_init_info.protocol_used = rf->protocol_used; 956 957 switch (rf->rdma_ver) { 958 case IRDMA_GEN_1: 959 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 960 break; 961 case IRDMA_GEN_2: 962 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 963 break; 964 } 965 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 966 if (status) { 967 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); 968 goto exit; 969 } 970 971 spin_lock_init(&cqp->req_lock); 972 spin_lock_init(&cqp->compl_lock); 973 974 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 975 if (status) { 976 ibdev_dbg(to_ibdev(dev), 977 "ERR: cqp create failed - status %d maj_err %d min_err %d\n", 978 status, maj_err, min_err); 979 goto exit; 980 } 981 982 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 983 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 984 985 /* init the waitqueue of the cqp_requests and add them to the list */ 986 for (i = 0; i < sqsize; i++) { 987 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 988 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 989 } 990 init_waitqueue_head(&cqp->remove_wq); 991 return 0; 992 993 exit: 994 irdma_destroy_cqp(rf, false); 995 996 return status; 997 } 998 999 /** 1000 * irdma_create_ccq - create control cq 1001 * @rf: RDMA PCI function 1002 * 1003 * Return 0, if the ccq and the resources associated with it 1004 * are successfully created, otherwise return error 1005 */ 1006 static int irdma_create_ccq(struct irdma_pci_f *rf) 1007 { 1008 struct irdma_sc_dev *dev = &rf->sc_dev; 1009 struct irdma_ccq_init_info info = {}; 1010 struct irdma_ccq *ccq = &rf->ccq; 1011 int status; 1012 1013 dev->ccq = &ccq->sc_cq; 1014 dev->ccq->dev = dev; 1015 info.dev = dev; 1016 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1017 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, 1018 IRDMA_CQ0_ALIGNMENT); 1019 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, 1020 &ccq->mem_cq.pa, GFP_KERNEL); 1021 if (!ccq->mem_cq.va) 1022 return -ENOMEM; 1023 1024 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1025 ccq->shadow_area.size, 1026 IRDMA_SHADOWAREA_M); 1027 if (status) 1028 goto exit; 1029 1030 ccq->sc_cq.back_cq = ccq; 1031 /* populate the ccq init info */ 1032 info.cq_base = ccq->mem_cq.va; 1033 info.cq_pa = ccq->mem_cq.pa; 1034 info.num_elem = IW_CCQ_SIZE; 1035 info.shadow_area = ccq->shadow_area.va; 1036 info.shadow_area_pa = ccq->shadow_area.pa; 1037 info.ceqe_mask = false; 1038 info.ceq_id_valid = true; 1039 info.shadow_read_threshold = 16; 1040 info.vsi = &rf->default_vsi; 1041 status = irdma_sc_ccq_init(dev->ccq, &info); 1042 if (!status) 1043 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1044 exit: 1045 if (status) { 1046 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, 1047 ccq->mem_cq.va, ccq->mem_cq.pa); 1048 ccq->mem_cq.va = NULL; 1049 } 1050 1051 return status; 1052 } 1053 1054 /** 1055 * irdma_alloc_set_mac - set up a mac address table entry 1056 * @iwdev: irdma device 1057 * 1058 * Allocate a mac ip entry and add it to the hw table Return 0 1059 * if successful, otherwise return error 1060 */ 1061 static int irdma_alloc_set_mac(struct irdma_device *iwdev) 1062 { 1063 int status; 1064 1065 status = irdma_alloc_local_mac_entry(iwdev->rf, 1066 &iwdev->mac_ip_table_idx); 1067 if (!status) { 1068 status = irdma_add_local_mac_entry(iwdev->rf, 1069 (const u8 *)iwdev->netdev->dev_addr, 1070 (u8)iwdev->mac_ip_table_idx); 1071 if (status) 1072 irdma_del_local_mac_entry(iwdev->rf, 1073 (u8)iwdev->mac_ip_table_idx); 1074 } 1075 return status; 1076 } 1077 1078 /** 1079 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1080 * ceq 1081 * @rf: RDMA PCI function 1082 * @iwceq: ceq associated with the vector 1083 * @ceq_id: the id number of the iwceq 1084 * @msix_vec: interrupt vector information 1085 * 1086 * Allocate interrupt resources and enable irq handling 1087 * Return 0 if successful, otherwise return error 1088 */ 1089 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1090 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1091 { 1092 int status; 1093 1094 if (rf->msix_shared && !ceq_id) { 1095 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1096 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev)); 1097 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1098 status = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1099 msix_vec->name, rf); 1100 } else { 1101 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1102 "irdma-%s-CEQ-%d", 1103 dev_name(&rf->pcidev->dev), ceq_id); 1104 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1105 1106 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0, 1107 msix_vec->name, iwceq); 1108 } 1109 cpumask_clear(&msix_vec->mask); 1110 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); 1111 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask); 1112 if (status) { 1113 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); 1114 return status; 1115 } 1116 1117 msix_vec->ceq_id = ceq_id; 1118 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1119 1120 return 0; 1121 } 1122 1123 /** 1124 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1125 * @rf: RDMA PCI function 1126 * 1127 * Allocate interrupt resources and enable irq handling 1128 * Return 0 if successful, otherwise return error 1129 */ 1130 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1131 { 1132 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1133 u32 ret = 0; 1134 1135 if (!rf->msix_shared) { 1136 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1137 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev)); 1138 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1139 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1140 msix_vec->name, rf); 1141 } 1142 if (ret) { 1143 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); 1144 return -EINVAL; 1145 } 1146 1147 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1148 1149 return 0; 1150 } 1151 1152 /** 1153 * irdma_create_ceq - create completion event queue 1154 * @rf: RDMA PCI function 1155 * @iwceq: pointer to the ceq resources to be created 1156 * @ceq_id: the id number of the iwceq 1157 * @vsi: SC vsi struct 1158 * 1159 * Return 0, if the ceq and the resources associated with it 1160 * are successfully created, otherwise return error 1161 */ 1162 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1163 u32 ceq_id, struct irdma_sc_vsi *vsi) 1164 { 1165 int status; 1166 struct irdma_ceq_init_info info = {}; 1167 struct irdma_sc_dev *dev = &rf->sc_dev; 1168 u64 scratch; 1169 u32 ceq_size; 1170 1171 info.ceq_id = ceq_id; 1172 iwceq->rf = rf; 1173 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1174 dev->hw_attrs.max_hw_ceq_size); 1175 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, 1176 IRDMA_CEQ_ALIGNMENT); 1177 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, 1178 &iwceq->mem.pa, GFP_KERNEL); 1179 if (!iwceq->mem.va) 1180 return -ENOMEM; 1181 1182 info.ceq_id = ceq_id; 1183 info.ceqe_base = iwceq->mem.va; 1184 info.ceqe_pa = iwceq->mem.pa; 1185 info.elem_cnt = ceq_size; 1186 iwceq->sc_ceq.ceq_id = ceq_id; 1187 info.dev = dev; 1188 info.vsi = vsi; 1189 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1190 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1191 if (!status) { 1192 if (dev->ceq_valid) 1193 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1194 IRDMA_OP_CEQ_CREATE); 1195 else 1196 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1197 } 1198 1199 if (status) { 1200 dma_free_coherent(dev->hw->device, iwceq->mem.size, 1201 iwceq->mem.va, iwceq->mem.pa); 1202 iwceq->mem.va = NULL; 1203 } 1204 1205 return status; 1206 } 1207 1208 /** 1209 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1210 * @rf: RDMA PCI function 1211 * 1212 * Allocate a list for all device completion event queues 1213 * Create the ceq 0 and configure it's msix interrupt vector 1214 * Return 0, if successfully set up, otherwise return error 1215 */ 1216 static int irdma_setup_ceq_0(struct irdma_pci_f *rf) 1217 { 1218 struct irdma_ceq *iwceq; 1219 struct irdma_msix_vector *msix_vec; 1220 u32 i; 1221 int status = 0; 1222 u32 num_ceqs; 1223 1224 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1225 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1226 if (!rf->ceqlist) { 1227 status = -ENOMEM; 1228 goto exit; 1229 } 1230 1231 iwceq = &rf->ceqlist[0]; 1232 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1233 if (status) { 1234 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", 1235 status); 1236 goto exit; 1237 } 1238 1239 spin_lock_init(&iwceq->ce_lock); 1240 i = rf->msix_shared ? 0 : 1; 1241 msix_vec = &rf->iw_msixtbl[i]; 1242 iwceq->irq = msix_vec->irq; 1243 iwceq->msix_idx = msix_vec->idx; 1244 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1245 if (status) { 1246 irdma_destroy_ceq(rf, iwceq); 1247 goto exit; 1248 } 1249 1250 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1251 rf->ceqs_count++; 1252 1253 exit: 1254 if (status && !rf->ceqs_count) { 1255 kfree(rf->ceqlist); 1256 rf->ceqlist = NULL; 1257 return status; 1258 } 1259 rf->sc_dev.ceq_valid = true; 1260 1261 return 0; 1262 } 1263 1264 /** 1265 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1266 * @rf: RDMA PCI function 1267 * @vsi: VSI structure for this CEQ 1268 * 1269 * Allocate a list for all device completion event queues 1270 * Create the ceq's and configure their msix interrupt vectors 1271 * Return 0, if ceqs are successfully set up, otherwise return error 1272 */ 1273 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1274 { 1275 u32 i; 1276 u32 ceq_id; 1277 struct irdma_ceq *iwceq; 1278 struct irdma_msix_vector *msix_vec; 1279 int status; 1280 u32 num_ceqs; 1281 1282 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1283 i = (rf->msix_shared) ? 1 : 2; 1284 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1285 iwceq = &rf->ceqlist[ceq_id]; 1286 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1287 if (status) { 1288 ibdev_dbg(&rf->iwdev->ibdev, 1289 "ERR: create ceq status = %d\n", status); 1290 goto del_ceqs; 1291 } 1292 spin_lock_init(&iwceq->ce_lock); 1293 msix_vec = &rf->iw_msixtbl[i]; 1294 iwceq->irq = msix_vec->irq; 1295 iwceq->msix_idx = msix_vec->idx; 1296 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1297 if (status) { 1298 irdma_destroy_ceq(rf, iwceq); 1299 goto del_ceqs; 1300 } 1301 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1302 rf->ceqs_count++; 1303 } 1304 1305 return 0; 1306 1307 del_ceqs: 1308 irdma_del_ceqs(rf); 1309 1310 return status; 1311 } 1312 1313 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1314 { 1315 struct irdma_aeq *aeq = &rf->aeq; 1316 dma_addr_t *pg_arr; 1317 u32 pg_cnt; 1318 int status; 1319 1320 if (rf->rdma_ver < IRDMA_GEN_2) 1321 return -EOPNOTSUPP; 1322 1323 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1324 aeq->mem.va = vzalloc(aeq->mem.size); 1325 1326 if (!aeq->mem.va) 1327 return -ENOMEM; 1328 1329 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1330 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1331 if (status) { 1332 vfree(aeq->mem.va); 1333 return status; 1334 } 1335 1336 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 1337 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1338 if (status) { 1339 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1340 vfree(aeq->mem.va); 1341 return status; 1342 } 1343 1344 return 0; 1345 } 1346 1347 /** 1348 * irdma_create_aeq - create async event queue 1349 * @rf: RDMA PCI function 1350 * 1351 * Return 0, if the aeq and the resources associated with it 1352 * are successfully created, otherwise return error 1353 */ 1354 static int irdma_create_aeq(struct irdma_pci_f *rf) 1355 { 1356 struct irdma_aeq_init_info info = {}; 1357 struct irdma_sc_dev *dev = &rf->sc_dev; 1358 struct irdma_aeq *aeq = &rf->aeq; 1359 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1360 u32 aeq_size; 1361 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1362 int status; 1363 1364 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1365 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1366 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1367 1368 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, 1369 IRDMA_AEQ_ALIGNMENT); 1370 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, 1371 &aeq->mem.pa, 1372 GFP_KERNEL | __GFP_NOWARN); 1373 if (aeq->mem.va) 1374 goto skip_virt_aeq; 1375 1376 /* physically mapped aeq failed. setup virtual aeq */ 1377 status = irdma_create_virt_aeq(rf, aeq_size); 1378 if (status) 1379 return status; 1380 1381 info.virtual_map = true; 1382 aeq->virtual_map = info.virtual_map; 1383 info.pbl_chunk_size = 1; 1384 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1385 1386 skip_virt_aeq: 1387 info.aeqe_base = aeq->mem.va; 1388 info.aeq_elem_pa = aeq->mem.pa; 1389 info.elem_cnt = aeq_size; 1390 info.dev = dev; 1391 info.msix_idx = rf->iw_msixtbl->idx; 1392 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1393 if (status) 1394 goto err; 1395 1396 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1397 if (status) 1398 goto err; 1399 1400 return 0; 1401 1402 err: 1403 if (aeq->virtual_map) { 1404 irdma_destroy_virt_aeq(rf); 1405 } else { 1406 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 1407 aeq->mem.pa); 1408 aeq->mem.va = NULL; 1409 } 1410 1411 return status; 1412 } 1413 1414 /** 1415 * irdma_setup_aeq - set up the device aeq 1416 * @rf: RDMA PCI function 1417 * 1418 * Create the aeq and configure its msix interrupt vector 1419 * Return 0 if successful, otherwise return error 1420 */ 1421 static int irdma_setup_aeq(struct irdma_pci_f *rf) 1422 { 1423 struct irdma_sc_dev *dev = &rf->sc_dev; 1424 int status; 1425 1426 status = irdma_create_aeq(rf); 1427 if (status) 1428 return status; 1429 1430 status = irdma_cfg_aeq_vector(rf); 1431 if (status) { 1432 irdma_destroy_aeq(rf); 1433 return status; 1434 } 1435 1436 if (!rf->msix_shared) 1437 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1438 1439 return 0; 1440 } 1441 1442 /** 1443 * irdma_initialize_ilq - create iwarp local queue for cm 1444 * @iwdev: irdma device 1445 * 1446 * Return 0 if successful, otherwise return error 1447 */ 1448 static int irdma_initialize_ilq(struct irdma_device *iwdev) 1449 { 1450 struct irdma_puda_rsrc_info info = {}; 1451 int status; 1452 1453 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1454 info.cq_id = 1; 1455 info.qp_id = 1; 1456 info.count = 1; 1457 info.pd_id = 1; 1458 info.abi_ver = IRDMA_ABI_VER; 1459 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1460 info.rq_size = info.sq_size; 1461 info.buf_size = 1024; 1462 info.tx_buf_cnt = 2 * info.sq_size; 1463 info.receive = irdma_receive_ilq; 1464 info.xmit_complete = irdma_free_sqbuf; 1465 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1466 if (status) 1467 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); 1468 1469 return status; 1470 } 1471 1472 /** 1473 * irdma_initialize_ieq - create iwarp exception queue 1474 * @iwdev: irdma device 1475 * 1476 * Return 0 if successful, otherwise return error 1477 */ 1478 static int irdma_initialize_ieq(struct irdma_device *iwdev) 1479 { 1480 struct irdma_puda_rsrc_info info = {}; 1481 int status; 1482 1483 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1484 info.cq_id = 2; 1485 info.qp_id = iwdev->vsi.exception_lan_q; 1486 info.count = 1; 1487 info.pd_id = 2; 1488 info.abi_ver = IRDMA_ABI_VER; 1489 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1490 info.rq_size = info.sq_size; 1491 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1492 info.tx_buf_cnt = 4096; 1493 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1494 if (status) 1495 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); 1496 1497 return status; 1498 } 1499 1500 /** 1501 * irdma_reinitialize_ieq - destroy and re-create ieq 1502 * @vsi: VSI structure 1503 */ 1504 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1505 { 1506 struct irdma_device *iwdev = vsi->back_vsi; 1507 struct irdma_pci_f *rf = iwdev->rf; 1508 1509 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1510 if (irdma_initialize_ieq(iwdev)) { 1511 iwdev->rf->reset = true; 1512 rf->gen_ops.request_reset(rf); 1513 } 1514 } 1515 1516 /** 1517 * irdma_hmc_setup - create hmc objects for the device 1518 * @rf: RDMA PCI function 1519 * 1520 * Set up the device private memory space for the number and size of 1521 * the hmc objects and create the objects 1522 * Return 0 if successful, otherwise return error 1523 */ 1524 static int irdma_hmc_setup(struct irdma_pci_f *rf) 1525 { 1526 int status; 1527 u32 qpcnt; 1528 1529 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1530 1531 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1532 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt); 1533 if (status) 1534 return status; 1535 1536 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1537 1538 return status; 1539 } 1540 1541 /** 1542 * irdma_del_init_mem - deallocate memory resources 1543 * @rf: RDMA PCI function 1544 */ 1545 static void irdma_del_init_mem(struct irdma_pci_f *rf) 1546 { 1547 struct irdma_sc_dev *dev = &rf->sc_dev; 1548 1549 kfree(dev->hmc_info->sd_table.sd_entry); 1550 dev->hmc_info->sd_table.sd_entry = NULL; 1551 kfree(rf->mem_rsrc); 1552 rf->mem_rsrc = NULL; 1553 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1554 rf->obj_mem.pa); 1555 rf->obj_mem.va = NULL; 1556 if (rf->rdma_ver != IRDMA_GEN_1) { 1557 bitmap_free(rf->allocated_ws_nodes); 1558 rf->allocated_ws_nodes = NULL; 1559 } 1560 kfree(rf->ceqlist); 1561 rf->ceqlist = NULL; 1562 kfree(rf->iw_msixtbl); 1563 rf->iw_msixtbl = NULL; 1564 kfree(rf->hmc_info_mem); 1565 rf->hmc_info_mem = NULL; 1566 } 1567 1568 /** 1569 * irdma_initialize_dev - initialize device 1570 * @rf: RDMA PCI function 1571 * 1572 * Allocate memory for the hmc objects and initialize iwdev 1573 * Return 0 if successful, otherwise clean up the resources 1574 * and return error 1575 */ 1576 static int irdma_initialize_dev(struct irdma_pci_f *rf) 1577 { 1578 int status; 1579 struct irdma_sc_dev *dev = &rf->sc_dev; 1580 struct irdma_device_init_info info = {}; 1581 struct irdma_dma_mem mem; 1582 u32 size; 1583 1584 size = sizeof(struct irdma_hmc_pble_rsrc) + 1585 sizeof(struct irdma_hmc_info) + 1586 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1587 1588 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1589 if (!rf->hmc_info_mem) 1590 return -ENOMEM; 1591 1592 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1593 dev->hmc_info = &rf->hw.hmc; 1594 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1595 (rf->pble_rsrc + 1); 1596 1597 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1598 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1599 if (status) 1600 goto error; 1601 1602 info.fpm_query_buf_pa = mem.pa; 1603 info.fpm_query_buf = mem.va; 1604 1605 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1606 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1607 if (status) 1608 goto error; 1609 1610 info.fpm_commit_buf_pa = mem.pa; 1611 info.fpm_commit_buf = mem.va; 1612 1613 info.bar0 = rf->hw.hw_addr; 1614 info.hmc_fn_id = rf->pf_id; 1615 info.hw = &rf->hw; 1616 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info); 1617 if (status) 1618 goto error; 1619 1620 return status; 1621 error: 1622 kfree(rf->hmc_info_mem); 1623 rf->hmc_info_mem = NULL; 1624 1625 return status; 1626 } 1627 1628 /** 1629 * irdma_rt_deinit_hw - clean up the irdma device resources 1630 * @iwdev: irdma device 1631 * 1632 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1633 * device queues and free the pble and the hmc objects 1634 */ 1635 void irdma_rt_deinit_hw(struct irdma_device *iwdev) 1636 { 1637 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); 1638 1639 switch (iwdev->init_state) { 1640 case IP_ADDR_REGISTERED: 1641 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1642 irdma_del_local_mac_entry(iwdev->rf, 1643 (u8)iwdev->mac_ip_table_idx); 1644 fallthrough; 1645 case AEQ_CREATED: 1646 case PBLE_CHUNK_MEM: 1647 case CEQS_CREATED: 1648 case IEQ_CREATED: 1649 if (!iwdev->roce_mode) 1650 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1651 iwdev->rf->reset); 1652 fallthrough; 1653 case ILQ_CREATED: 1654 if (!iwdev->roce_mode) 1655 irdma_puda_dele_rsrc(&iwdev->vsi, 1656 IRDMA_PUDA_RSRC_TYPE_ILQ, 1657 iwdev->rf->reset); 1658 break; 1659 default: 1660 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1661 break; 1662 } 1663 1664 irdma_cleanup_cm_core(&iwdev->cm_core); 1665 if (iwdev->vsi.pestat) { 1666 irdma_vsi_stats_free(&iwdev->vsi); 1667 kfree(iwdev->vsi.pestat); 1668 } 1669 if (iwdev->cleanup_wq) 1670 destroy_workqueue(iwdev->cleanup_wq); 1671 } 1672 1673 static int irdma_setup_init_state(struct irdma_pci_f *rf) 1674 { 1675 int status; 1676 1677 status = irdma_save_msix_info(rf); 1678 if (status) 1679 return status; 1680 1681 rf->hw.device = &rf->pcidev->dev; 1682 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); 1683 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, 1684 &rf->obj_mem.pa, GFP_KERNEL); 1685 if (!rf->obj_mem.va) { 1686 status = -ENOMEM; 1687 goto clean_msixtbl; 1688 } 1689 1690 rf->obj_next = rf->obj_mem; 1691 status = irdma_initialize_dev(rf); 1692 if (status) 1693 goto clean_obj_mem; 1694 1695 return 0; 1696 1697 clean_obj_mem: 1698 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1699 rf->obj_mem.pa); 1700 rf->obj_mem.va = NULL; 1701 clean_msixtbl: 1702 kfree(rf->iw_msixtbl); 1703 rf->iw_msixtbl = NULL; 1704 return status; 1705 } 1706 1707 /** 1708 * irdma_get_used_rsrc - determine resources used internally 1709 * @iwdev: irdma device 1710 * 1711 * Called at the end of open to get all internal allocations 1712 */ 1713 static void irdma_get_used_rsrc(struct irdma_device *iwdev) 1714 { 1715 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1716 iwdev->rf->max_pd); 1717 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1718 iwdev->rf->max_qp); 1719 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1720 iwdev->rf->max_cq); 1721 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1722 iwdev->rf->max_mr); 1723 } 1724 1725 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1726 { 1727 enum init_completion_state state = rf->init_state; 1728 1729 rf->init_state = INVALID_STATE; 1730 if (rf->rsrc_created) { 1731 irdma_destroy_aeq(rf); 1732 irdma_destroy_pble_prm(rf->pble_rsrc); 1733 irdma_del_ceqs(rf); 1734 rf->rsrc_created = false; 1735 } 1736 switch (state) { 1737 case CEQ0_CREATED: 1738 irdma_del_ceq_0(rf); 1739 fallthrough; 1740 case CCQ_CREATED: 1741 irdma_destroy_ccq(rf); 1742 fallthrough; 1743 case HW_RSRC_INITIALIZED: 1744 case HMC_OBJS_CREATED: 1745 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1746 rf->reset, rf->rdma_ver); 1747 fallthrough; 1748 case CQP_CREATED: 1749 irdma_destroy_cqp(rf, true); 1750 fallthrough; 1751 case INITIAL_STATE: 1752 irdma_del_init_mem(rf); 1753 break; 1754 case INVALID_STATE: 1755 default: 1756 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1757 break; 1758 } 1759 } 1760 1761 /** 1762 * irdma_rt_init_hw - Initializes runtime portion of HW 1763 * @iwdev: irdma device 1764 * @l2params: qos, tc, mtu info from netdev driver 1765 * 1766 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1767 * device resource objects. 1768 */ 1769 int irdma_rt_init_hw(struct irdma_device *iwdev, 1770 struct irdma_l2params *l2params) 1771 { 1772 struct irdma_pci_f *rf = iwdev->rf; 1773 struct irdma_sc_dev *dev = &rf->sc_dev; 1774 struct irdma_vsi_init_info vsi_info = {}; 1775 struct irdma_vsi_stats_info stats_info = {}; 1776 int status; 1777 1778 vsi_info.dev = dev; 1779 vsi_info.back_vsi = iwdev; 1780 vsi_info.params = l2params; 1781 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1782 vsi_info.register_qset = rf->gen_ops.register_qset; 1783 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1784 vsi_info.exception_lan_q = 2; 1785 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1786 1787 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1788 if (status) 1789 return status; 1790 1791 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1792 if (!stats_info.pestat) { 1793 irdma_cleanup_cm_core(&iwdev->cm_core); 1794 return -ENOMEM; 1795 } 1796 stats_info.fcn_id = dev->hmc_fn_id; 1797 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1798 if (status) { 1799 irdma_cleanup_cm_core(&iwdev->cm_core); 1800 kfree(stats_info.pestat); 1801 return status; 1802 } 1803 1804 do { 1805 if (!iwdev->roce_mode) { 1806 status = irdma_initialize_ilq(iwdev); 1807 if (status) 1808 break; 1809 iwdev->init_state = ILQ_CREATED; 1810 status = irdma_initialize_ieq(iwdev); 1811 if (status) 1812 break; 1813 iwdev->init_state = IEQ_CREATED; 1814 } 1815 if (!rf->rsrc_created) { 1816 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1817 if (status) 1818 break; 1819 1820 iwdev->init_state = CEQS_CREATED; 1821 1822 status = irdma_hmc_init_pble(&rf->sc_dev, 1823 rf->pble_rsrc); 1824 if (status) { 1825 irdma_del_ceqs(rf); 1826 break; 1827 } 1828 1829 iwdev->init_state = PBLE_CHUNK_MEM; 1830 1831 status = irdma_setup_aeq(rf); 1832 if (status) { 1833 irdma_destroy_pble_prm(rf->pble_rsrc); 1834 irdma_del_ceqs(rf); 1835 break; 1836 } 1837 iwdev->init_state = AEQ_CREATED; 1838 rf->rsrc_created = true; 1839 } 1840 1841 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1842 irdma_alloc_set_mac(iwdev); 1843 irdma_add_ip(iwdev); 1844 iwdev->init_state = IP_ADDR_REGISTERED; 1845 1846 /* handles asynch cleanup tasks - disconnect CM , free qp, 1847 * free cq bufs 1848 */ 1849 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1850 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1851 if (!iwdev->cleanup_wq) 1852 return -ENOMEM; 1853 irdma_get_used_rsrc(iwdev); 1854 init_waitqueue_head(&iwdev->suspend_wq); 1855 1856 return 0; 1857 } while (0); 1858 1859 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1860 status, iwdev->init_state); 1861 irdma_rt_deinit_hw(iwdev); 1862 1863 return status; 1864 } 1865 1866 /** 1867 * irdma_ctrl_init_hw - Initializes control portion of HW 1868 * @rf: RDMA PCI function 1869 * 1870 * Create admin queues, HMC obejcts and RF resource objects 1871 */ 1872 int irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1873 { 1874 struct irdma_sc_dev *dev = &rf->sc_dev; 1875 int status; 1876 do { 1877 status = irdma_setup_init_state(rf); 1878 if (status) 1879 break; 1880 rf->init_state = INITIAL_STATE; 1881 1882 status = irdma_create_cqp(rf); 1883 if (status) 1884 break; 1885 rf->init_state = CQP_CREATED; 1886 1887 status = irdma_hmc_setup(rf); 1888 if (status) 1889 break; 1890 rf->init_state = HMC_OBJS_CREATED; 1891 1892 status = irdma_initialize_hw_rsrc(rf); 1893 if (status) 1894 break; 1895 rf->init_state = HW_RSRC_INITIALIZED; 1896 1897 status = irdma_create_ccq(rf); 1898 if (status) 1899 break; 1900 rf->init_state = CCQ_CREATED; 1901 1902 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 1903 if (rf->rdma_ver != IRDMA_GEN_1) { 1904 status = irdma_get_rdma_features(dev); 1905 if (status) 1906 break; 1907 } 1908 1909 status = irdma_setup_ceq_0(rf); 1910 if (status) 1911 break; 1912 rf->init_state = CEQ0_CREATED; 1913 /* Handles processing of CQP completions */ 1914 rf->cqp_cmpl_wq = 1915 alloc_ordered_workqueue("cqp_cmpl_wq", WQ_HIGHPRI); 1916 if (!rf->cqp_cmpl_wq) { 1917 status = -ENOMEM; 1918 break; 1919 } 1920 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 1921 irdma_sc_ccq_arm(dev->ccq); 1922 return 0; 1923 } while (0); 1924 1925 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n", 1926 rf->init_state, status); 1927 irdma_ctrl_deinit_hw(rf); 1928 return status; 1929 } 1930 1931 /** 1932 * irdma_set_hw_rsrc - set hw memory resources. 1933 * @rf: RDMA PCI function 1934 */ 1935 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) 1936 { 1937 rf->allocated_qps = (void *)(rf->mem_rsrc + 1938 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 1939 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 1940 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 1941 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 1942 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 1943 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 1944 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 1945 rf->qp_table = (struct irdma_qp **) 1946 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 1947 1948 spin_lock_init(&rf->rsrc_lock); 1949 spin_lock_init(&rf->arp_lock); 1950 spin_lock_init(&rf->qptable_lock); 1951 spin_lock_init(&rf->qh_list_lock); 1952 } 1953 1954 /** 1955 * irdma_calc_mem_rsrc_size - calculate memory resources size. 1956 * @rf: RDMA PCI function 1957 */ 1958 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 1959 { 1960 u32 rsrc_size; 1961 1962 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 1963 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 1964 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 1965 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 1966 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 1967 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 1968 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 1969 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 1970 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 1971 1972 return rsrc_size; 1973 } 1974 1975 /** 1976 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 1977 * @rf: RDMA PCI function 1978 */ 1979 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 1980 { 1981 u32 rsrc_size; 1982 u32 mrdrvbits; 1983 u32 ret; 1984 1985 if (rf->rdma_ver != IRDMA_GEN_1) { 1986 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES, 1987 GFP_KERNEL); 1988 if (!rf->allocated_ws_nodes) 1989 return -ENOMEM; 1990 1991 set_bit(0, rf->allocated_ws_nodes); 1992 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 1993 } 1994 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 1995 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 1996 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 1997 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1998 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 1999 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 2000 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 2001 rf->max_mcg = rf->max_qp; 2002 2003 rsrc_size = irdma_calc_mem_rsrc_size(rf); 2004 rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL); 2005 if (!rf->mem_rsrc) { 2006 ret = -ENOMEM; 2007 goto mem_rsrc_kzalloc_fail; 2008 } 2009 2010 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2011 2012 irdma_set_hw_rsrc(rf); 2013 2014 set_bit(0, rf->allocated_mrs); 2015 set_bit(0, rf->allocated_qps); 2016 set_bit(0, rf->allocated_cqs); 2017 set_bit(0, rf->allocated_pds); 2018 set_bit(0, rf->allocated_arps); 2019 set_bit(0, rf->allocated_ahs); 2020 set_bit(0, rf->allocated_mcgs); 2021 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2022 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2023 set_bit(1, rf->allocated_cqs); 2024 set_bit(1, rf->allocated_pds); 2025 set_bit(2, rf->allocated_cqs); 2026 set_bit(2, rf->allocated_pds); 2027 2028 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2029 /* stag index mask has a minimum of 14 bits */ 2030 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2031 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2032 2033 return 0; 2034 2035 mem_rsrc_kzalloc_fail: 2036 bitmap_free(rf->allocated_ws_nodes); 2037 rf->allocated_ws_nodes = NULL; 2038 2039 return ret; 2040 } 2041 2042 /** 2043 * irdma_cqp_ce_handler - handle cqp completions 2044 * @rf: RDMA PCI function 2045 * @cq: cq for cqp completions 2046 */ 2047 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2048 { 2049 struct irdma_cqp_request *cqp_request; 2050 struct irdma_sc_dev *dev = &rf->sc_dev; 2051 u32 cqe_count = 0; 2052 struct irdma_ccq_cqe_info info; 2053 unsigned long flags; 2054 int ret; 2055 2056 do { 2057 memset(&info, 0, sizeof(info)); 2058 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2059 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2060 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2061 if (ret) 2062 break; 2063 2064 cqp_request = (struct irdma_cqp_request *) 2065 (unsigned long)info.scratch; 2066 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2067 info.maj_err_code, 2068 info.min_err_code)) 2069 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2070 info.op_code, info.maj_err_code, info.min_err_code); 2071 if (cqp_request) { 2072 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2073 cqp_request->compl_info.min_err_code = info.min_err_code; 2074 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2075 cqp_request->compl_info.error = info.error; 2076 2077 if (cqp_request->waiting) { 2078 cqp_request->request_done = true; 2079 wake_up(&cqp_request->waitq); 2080 irdma_put_cqp_request(&rf->cqp, cqp_request); 2081 } else { 2082 if (cqp_request->callback_fcn) 2083 cqp_request->callback_fcn(cqp_request); 2084 irdma_put_cqp_request(&rf->cqp, cqp_request); 2085 } 2086 } 2087 2088 cqe_count++; 2089 } while (1); 2090 2091 if (cqe_count) { 2092 irdma_process_bh(dev); 2093 irdma_sc_ccq_arm(cq); 2094 } 2095 } 2096 2097 /** 2098 * cqp_compl_worker - Handle cqp completions 2099 * @work: Pointer to work structure 2100 */ 2101 void cqp_compl_worker(struct work_struct *work) 2102 { 2103 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2104 cqp_cmpl_work); 2105 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2106 2107 irdma_cqp_ce_handler(rf, cq); 2108 } 2109 2110 /** 2111 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2112 * @cm_core: cm's core 2113 * @port: port to identify apbvt entry 2114 */ 2115 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2116 u16 port) 2117 { 2118 struct irdma_apbvt_entry *entry; 2119 2120 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2121 if (entry->port == port) { 2122 entry->use_cnt++; 2123 return entry; 2124 } 2125 } 2126 2127 return NULL; 2128 } 2129 2130 /** 2131 * irdma_next_iw_state - modify qp state 2132 * @iwqp: iwarp qp to modify 2133 * @state: next state for qp 2134 * @del_hash: del hash 2135 * @term: term message 2136 * @termlen: length of term message 2137 */ 2138 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2139 u8 termlen) 2140 { 2141 struct irdma_modify_qp_info info = {}; 2142 2143 info.next_iwarp_state = state; 2144 info.remove_hash_idx = del_hash; 2145 info.cq_num_valid = true; 2146 info.arp_cache_idx_valid = true; 2147 info.dont_send_term = true; 2148 info.dont_send_fin = true; 2149 info.termlen = termlen; 2150 2151 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2152 info.dont_send_term = false; 2153 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2154 info.dont_send_fin = false; 2155 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2156 info.reset_tcp_conn = true; 2157 iwqp->hw_iwarp_state = state; 2158 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2159 iwqp->iwarp_state = info.next_iwarp_state; 2160 } 2161 2162 /** 2163 * irdma_del_local_mac_entry - remove a mac entry from the hw 2164 * table 2165 * @rf: RDMA PCI function 2166 * @idx: the index of the mac ip address to delete 2167 */ 2168 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2169 { 2170 struct irdma_cqp *iwcqp = &rf->cqp; 2171 struct irdma_cqp_request *cqp_request; 2172 struct cqp_cmds_info *cqp_info; 2173 2174 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2175 if (!cqp_request) 2176 return; 2177 2178 cqp_info = &cqp_request->info; 2179 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2180 cqp_info->post_sq = 1; 2181 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2182 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2183 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2184 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2185 2186 irdma_handle_cqp_op(rf, cqp_request); 2187 irdma_put_cqp_request(iwcqp, cqp_request); 2188 } 2189 2190 /** 2191 * irdma_add_local_mac_entry - add a mac ip address entry to the 2192 * hw table 2193 * @rf: RDMA PCI function 2194 * @mac_addr: pointer to mac address 2195 * @idx: the index of the mac ip address to add 2196 */ 2197 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2198 { 2199 struct irdma_local_mac_entry_info *info; 2200 struct irdma_cqp *iwcqp = &rf->cqp; 2201 struct irdma_cqp_request *cqp_request; 2202 struct cqp_cmds_info *cqp_info; 2203 int status; 2204 2205 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2206 if (!cqp_request) 2207 return -ENOMEM; 2208 2209 cqp_info = &cqp_request->info; 2210 cqp_info->post_sq = 1; 2211 info = &cqp_info->in.u.add_local_mac_entry.info; 2212 ether_addr_copy(info->mac_addr, mac_addr); 2213 info->entry_idx = idx; 2214 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2215 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2216 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2217 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2218 2219 status = irdma_handle_cqp_op(rf, cqp_request); 2220 irdma_put_cqp_request(iwcqp, cqp_request); 2221 2222 return status; 2223 } 2224 2225 /** 2226 * irdma_alloc_local_mac_entry - allocate a mac entry 2227 * @rf: RDMA PCI function 2228 * @mac_tbl_idx: the index of the new mac address 2229 * 2230 * Allocate a mac address entry and update the mac_tbl_idx 2231 * to hold the index of the newly created mac address 2232 * Return 0 if successful, otherwise return error 2233 */ 2234 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2235 { 2236 struct irdma_cqp *iwcqp = &rf->cqp; 2237 struct irdma_cqp_request *cqp_request; 2238 struct cqp_cmds_info *cqp_info; 2239 int status = 0; 2240 2241 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2242 if (!cqp_request) 2243 return -ENOMEM; 2244 2245 cqp_info = &cqp_request->info; 2246 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2247 cqp_info->post_sq = 1; 2248 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2249 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2250 status = irdma_handle_cqp_op(rf, cqp_request); 2251 if (!status) 2252 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2253 2254 irdma_put_cqp_request(iwcqp, cqp_request); 2255 2256 return status; 2257 } 2258 2259 /** 2260 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2261 * @iwdev: irdma device 2262 * @accel_local_port: port for apbvt 2263 * @add_port: add ordelete port 2264 */ 2265 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2266 u16 accel_local_port, bool add_port) 2267 { 2268 struct irdma_apbvt_info *info; 2269 struct irdma_cqp_request *cqp_request; 2270 struct cqp_cmds_info *cqp_info; 2271 int status; 2272 2273 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2274 if (!cqp_request) 2275 return -ENOMEM; 2276 2277 cqp_info = &cqp_request->info; 2278 info = &cqp_info->in.u.manage_apbvt_entry.info; 2279 memset(info, 0, sizeof(*info)); 2280 info->add = add_port; 2281 info->port = accel_local_port; 2282 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2283 cqp_info->post_sq = 1; 2284 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2285 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2286 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", 2287 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2288 2289 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2290 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2291 2292 return status; 2293 } 2294 2295 /** 2296 * irdma_add_apbvt - add tcp port to HW apbvt table 2297 * @iwdev: irdma device 2298 * @port: port for apbvt 2299 */ 2300 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2301 { 2302 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2303 struct irdma_apbvt_entry *entry; 2304 unsigned long flags; 2305 2306 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2307 entry = irdma_lookup_apbvt_entry(cm_core, port); 2308 if (entry) { 2309 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2310 return entry; 2311 } 2312 2313 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2314 if (!entry) { 2315 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2316 return NULL; 2317 } 2318 2319 entry->port = port; 2320 entry->use_cnt = 1; 2321 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2322 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2323 2324 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2325 kfree(entry); 2326 return NULL; 2327 } 2328 2329 return entry; 2330 } 2331 2332 /** 2333 * irdma_del_apbvt - delete tcp port from HW apbvt table 2334 * @iwdev: irdma device 2335 * @entry: apbvt entry object 2336 */ 2337 void irdma_del_apbvt(struct irdma_device *iwdev, 2338 struct irdma_apbvt_entry *entry) 2339 { 2340 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2341 unsigned long flags; 2342 2343 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2344 if (--entry->use_cnt) { 2345 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2346 return; 2347 } 2348 2349 hash_del(&entry->hlist); 2350 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to 2351 * protect against race where add APBVT CQP can race ahead of the delete 2352 * APBVT for same port. 2353 */ 2354 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2355 kfree(entry); 2356 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2357 } 2358 2359 /** 2360 * irdma_manage_arp_cache - manage hw arp cache 2361 * @rf: RDMA PCI function 2362 * @mac_addr: mac address ptr 2363 * @ip_addr: ip addr for arp cache 2364 * @ipv4: flag inicating IPv4 2365 * @action: add, delete or modify 2366 */ 2367 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 2368 const unsigned char *mac_addr, 2369 u32 *ip_addr, bool ipv4, u32 action) 2370 { 2371 struct irdma_add_arp_cache_entry_info *info; 2372 struct irdma_cqp_request *cqp_request; 2373 struct cqp_cmds_info *cqp_info; 2374 int arp_index; 2375 2376 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action); 2377 if (arp_index == -1) 2378 return; 2379 2380 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2381 if (!cqp_request) 2382 return; 2383 2384 cqp_info = &cqp_request->info; 2385 if (action == IRDMA_ARP_ADD) { 2386 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2387 info = &cqp_info->in.u.add_arp_cache_entry.info; 2388 memset(info, 0, sizeof(*info)); 2389 info->arp_index = (u16)arp_index; 2390 info->permanent = true; 2391 ether_addr_copy(info->mac_addr, mac_addr); 2392 cqp_info->in.u.add_arp_cache_entry.scratch = 2393 (uintptr_t)cqp_request; 2394 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2395 } else { 2396 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2397 cqp_info->in.u.del_arp_cache_entry.scratch = 2398 (uintptr_t)cqp_request; 2399 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2400 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2401 } 2402 2403 cqp_info->post_sq = 1; 2404 irdma_handle_cqp_op(rf, cqp_request); 2405 irdma_put_cqp_request(&rf->cqp, cqp_request); 2406 } 2407 2408 /** 2409 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2410 * @cqp_request: qhash cqp completion 2411 */ 2412 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2413 { 2414 struct irdma_cm_node *cm_node = cqp_request->param; 2415 2416 irdma_send_syn(cm_node, 1); 2417 irdma_rem_ref_cm_node(cm_node); 2418 } 2419 2420 /** 2421 * irdma_manage_qhash - add or modify qhash 2422 * @iwdev: irdma device 2423 * @cminfo: cm info for qhash 2424 * @etype: type (syn or quad) 2425 * @mtype: type of qhash 2426 * @cmnode: cmnode associated with connection 2427 * @wait: wait for completion 2428 */ 2429 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2430 enum irdma_quad_entry_type etype, 2431 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2432 bool wait) 2433 { 2434 struct irdma_qhash_table_info *info; 2435 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2436 struct irdma_cqp_request *cqp_request; 2437 struct cqp_cmds_info *cqp_info; 2438 struct irdma_cm_node *cm_node = cmnode; 2439 int status; 2440 2441 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2442 if (!cqp_request) 2443 return -ENOMEM; 2444 2445 cqp_info = &cqp_request->info; 2446 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2447 memset(info, 0, sizeof(*info)); 2448 info->vsi = &iwdev->vsi; 2449 info->manage = mtype; 2450 info->entry_type = etype; 2451 if (cminfo->vlan_id < VLAN_N_VID) { 2452 info->vlan_valid = true; 2453 info->vlan_id = cminfo->vlan_id; 2454 } else { 2455 info->vlan_valid = false; 2456 } 2457 info->ipv4_valid = cminfo->ipv4; 2458 info->user_pri = cminfo->user_pri; 2459 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 2460 info->qp_num = cminfo->qh_qpid; 2461 info->dest_port = cminfo->loc_port; 2462 info->dest_ip[0] = cminfo->loc_addr[0]; 2463 info->dest_ip[1] = cminfo->loc_addr[1]; 2464 info->dest_ip[2] = cminfo->loc_addr[2]; 2465 info->dest_ip[3] = cminfo->loc_addr[3]; 2466 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2467 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2468 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2469 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2470 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2471 info->src_port = cminfo->rem_port; 2472 info->src_ip[0] = cminfo->rem_addr[0]; 2473 info->src_ip[1] = cminfo->rem_addr[1]; 2474 info->src_ip[2] = cminfo->rem_addr[2]; 2475 info->src_ip[3] = cminfo->rem_addr[3]; 2476 } 2477 if (cmnode) { 2478 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2479 cqp_request->param = cmnode; 2480 if (!wait) 2481 refcount_inc(&cm_node->refcnt); 2482 } 2483 if (info->ipv4_valid) 2484 ibdev_dbg(&iwdev->ibdev, 2485 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2486 (!mtype) ? "DELETE" : "ADD", 2487 __builtin_return_address(0), info->dest_port, 2488 info->src_port, info->dest_ip, info->src_ip, 2489 info->mac_addr, cminfo->vlan_id, 2490 cmnode ? cmnode : NULL); 2491 else 2492 ibdev_dbg(&iwdev->ibdev, 2493 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2494 (!mtype) ? "DELETE" : "ADD", 2495 __builtin_return_address(0), info->dest_port, 2496 info->src_port, info->dest_ip, info->src_ip, 2497 info->mac_addr, cminfo->vlan_id, 2498 cmnode ? cmnode : NULL); 2499 2500 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2501 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2502 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2503 cqp_info->post_sq = 1; 2504 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2505 if (status && cm_node && !wait) 2506 irdma_rem_ref_cm_node(cm_node); 2507 2508 irdma_put_cqp_request(iwcqp, cqp_request); 2509 2510 return status; 2511 } 2512 2513 /** 2514 * irdma_hw_flush_wqes_callback - Check return code after flush 2515 * @cqp_request: qhash cqp completion 2516 */ 2517 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request) 2518 { 2519 struct irdma_qp_flush_info *hw_info; 2520 struct irdma_sc_qp *qp; 2521 struct irdma_qp *iwqp; 2522 struct cqp_cmds_info *cqp_info; 2523 2524 cqp_info = &cqp_request->info; 2525 hw_info = &cqp_info->in.u.qp_flush_wqes.info; 2526 qp = cqp_info->in.u.qp_flush_wqes.qp; 2527 iwqp = qp->qp_uk.back_qp; 2528 2529 if (cqp_request->compl_info.maj_err_code) 2530 return; 2531 2532 if (hw_info->rq && 2533 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2534 cqp_request->compl_info.min_err_code == 0)) { 2535 /* RQ WQE flush was requested but did not happen */ 2536 qp->qp_uk.rq_flush_complete = true; 2537 } 2538 if (hw_info->sq && 2539 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2540 cqp_request->compl_info.min_err_code == 0)) { 2541 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2542 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work", 2543 qp->qp_uk.qp_id); 2544 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2545 } 2546 qp->qp_uk.sq_flush_complete = true; 2547 } 2548 } 2549 2550 /** 2551 * irdma_hw_flush_wqes - flush qp's wqe 2552 * @rf: RDMA PCI function 2553 * @qp: hardware control qp 2554 * @info: info for flush 2555 * @wait: flag wait for completion 2556 */ 2557 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2558 struct irdma_qp_flush_info *info, bool wait) 2559 { 2560 int status; 2561 struct irdma_qp_flush_info *hw_info; 2562 struct irdma_cqp_request *cqp_request; 2563 struct cqp_cmds_info *cqp_info; 2564 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2565 2566 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2567 if (!cqp_request) 2568 return -ENOMEM; 2569 2570 cqp_info = &cqp_request->info; 2571 if (!wait) 2572 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback; 2573 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2574 memcpy(hw_info, info, sizeof(*hw_info)); 2575 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2576 cqp_info->post_sq = 1; 2577 cqp_info->in.u.qp_flush_wqes.qp = qp; 2578 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2579 status = irdma_handle_cqp_op(rf, cqp_request); 2580 if (status) { 2581 qp->qp_uk.sq_flush_complete = true; 2582 qp->qp_uk.rq_flush_complete = true; 2583 irdma_put_cqp_request(&rf->cqp, cqp_request); 2584 return status; 2585 } 2586 2587 if (!wait || cqp_request->compl_info.maj_err_code) 2588 goto put_cqp; 2589 2590 if (info->rq) { 2591 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2592 cqp_request->compl_info.min_err_code == 0) { 2593 /* RQ WQE flush was requested but did not happen */ 2594 qp->qp_uk.rq_flush_complete = true; 2595 } 2596 } 2597 if (info->sq) { 2598 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2599 cqp_request->compl_info.min_err_code == 0) { 2600 /* 2601 * Handling case where WQE is posted to empty SQ when 2602 * flush has not completed 2603 */ 2604 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2605 struct irdma_cqp_request *new_req; 2606 2607 if (!qp->qp_uk.sq_flush_complete) 2608 goto put_cqp; 2609 qp->qp_uk.sq_flush_complete = false; 2610 qp->flush_sq = false; 2611 2612 info->rq = false; 2613 info->sq = true; 2614 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 2615 if (!new_req) { 2616 status = -ENOMEM; 2617 goto put_cqp; 2618 } 2619 cqp_info = &new_req->info; 2620 hw_info = &new_req->info.in.u.qp_flush_wqes.info; 2621 memcpy(hw_info, info, sizeof(*hw_info)); 2622 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2623 cqp_info->post_sq = 1; 2624 cqp_info->in.u.qp_flush_wqes.qp = qp; 2625 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req; 2626 2627 status = irdma_handle_cqp_op(rf, new_req); 2628 if (new_req->compl_info.maj_err_code || 2629 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2630 status) { 2631 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d", 2632 iwqp->ibqp.qp_num); 2633 qp->qp_uk.sq_flush_complete = false; 2634 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2635 } 2636 irdma_put_cqp_request(&rf->cqp, new_req); 2637 } else { 2638 /* SQ WQE flush was requested but did not happen */ 2639 qp->qp_uk.sq_flush_complete = true; 2640 } 2641 } else { 2642 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) 2643 qp->qp_uk.sq_flush_complete = true; 2644 } 2645 } 2646 2647 ibdev_dbg(&rf->iwdev->ibdev, 2648 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2649 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2650 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2651 cqp_request->compl_info.maj_err_code, 2652 cqp_request->compl_info.min_err_code); 2653 put_cqp: 2654 irdma_put_cqp_request(&rf->cqp, cqp_request); 2655 2656 return status; 2657 } 2658 2659 /** 2660 * irdma_gen_ae - generate AE 2661 * @rf: RDMA PCI function 2662 * @qp: qp associated with AE 2663 * @info: info for ae 2664 * @wait: wait for completion 2665 */ 2666 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2667 struct irdma_gen_ae_info *info, bool wait) 2668 { 2669 struct irdma_gen_ae_info *ae_info; 2670 struct irdma_cqp_request *cqp_request; 2671 struct cqp_cmds_info *cqp_info; 2672 2673 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2674 if (!cqp_request) 2675 return; 2676 2677 cqp_info = &cqp_request->info; 2678 ae_info = &cqp_request->info.in.u.gen_ae.info; 2679 memcpy(ae_info, info, sizeof(*ae_info)); 2680 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2681 cqp_info->post_sq = 1; 2682 cqp_info->in.u.gen_ae.qp = qp; 2683 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2684 2685 irdma_handle_cqp_op(rf, cqp_request); 2686 irdma_put_cqp_request(&rf->cqp, cqp_request); 2687 } 2688 2689 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2690 { 2691 struct irdma_qp_flush_info info = {}; 2692 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2693 u8 flush_code = iwqp->sc_qp.flush_code; 2694 2695 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2696 return; 2697 2698 /* Set flush info fields*/ 2699 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2700 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2701 2702 /* Generate userflush errors in CQE */ 2703 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2704 info.sq_minor_code = FLUSH_GENERAL_ERR; 2705 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2706 info.rq_minor_code = FLUSH_GENERAL_ERR; 2707 info.userflushcode = true; 2708 2709 if (flush_mask & IRDMA_REFLUSH) { 2710 if (info.sq) 2711 iwqp->sc_qp.flush_sq = false; 2712 if (info.rq) 2713 iwqp->sc_qp.flush_rq = false; 2714 } else { 2715 if (flush_code) { 2716 if (info.sq && iwqp->sc_qp.sq_flush_code) 2717 info.sq_minor_code = flush_code; 2718 if (info.rq && iwqp->sc_qp.rq_flush_code) 2719 info.rq_minor_code = flush_code; 2720 } 2721 if (!iwqp->user_mode) 2722 queue_delayed_work(iwqp->iwdev->cleanup_wq, 2723 &iwqp->dwork_flush, 2724 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS)); 2725 } 2726 2727 /* Issue flush */ 2728 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2729 flush_mask & IRDMA_FLUSH_WAIT); 2730 iwqp->flush_issued = true; 2731 } 2732