1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "main.h" 4 5 static struct irdma_rsrc_limits rsrc_limits_table[] = { 6 [0] = { 7 .qplimit = SZ_128, 8 }, 9 [1] = { 10 .qplimit = SZ_1K, 11 }, 12 [2] = { 13 .qplimit = SZ_2K, 14 }, 15 [3] = { 16 .qplimit = SZ_4K, 17 }, 18 [4] = { 19 .qplimit = SZ_16K, 20 }, 21 [5] = { 22 .qplimit = SZ_64K, 23 }, 24 [6] = { 25 .qplimit = SZ_128K, 26 }, 27 [7] = { 28 .qplimit = SZ_256K, 29 }, 30 }; 31 32 /* types of hmc objects */ 33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 34 IRDMA_HMC_IW_QP, 35 IRDMA_HMC_IW_CQ, 36 IRDMA_HMC_IW_HTE, 37 IRDMA_HMC_IW_ARP, 38 IRDMA_HMC_IW_APBVT_ENTRY, 39 IRDMA_HMC_IW_MR, 40 IRDMA_HMC_IW_XF, 41 IRDMA_HMC_IW_XFFL, 42 IRDMA_HMC_IW_Q1, 43 IRDMA_HMC_IW_Q1FL, 44 IRDMA_HMC_IW_TIMER, 45 IRDMA_HMC_IW_FSIMC, 46 IRDMA_HMC_IW_FSIAV, 47 IRDMA_HMC_IW_RRF, 48 IRDMA_HMC_IW_RRFFL, 49 IRDMA_HMC_IW_HDR, 50 IRDMA_HMC_IW_MD, 51 IRDMA_HMC_IW_OOISC, 52 IRDMA_HMC_IW_OOISCFFL, 53 }; 54 55 /** 56 * irdma_iwarp_ce_handler - handle iwarp completions 57 * @iwcq: iwarp cq receiving event 58 */ 59 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 60 { 61 struct irdma_cq *cq = iwcq->back_cq; 62 63 if (!cq->user_mode) 64 atomic_set(&cq->armed, 0); 65 if (cq->ibcq.comp_handler) 66 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 67 } 68 69 /** 70 * irdma_puda_ce_handler - handle puda completion events 71 * @rf: RDMA PCI function 72 * @cq: puda completion q for event 73 */ 74 static void irdma_puda_ce_handler(struct irdma_pci_f *rf, 75 struct irdma_sc_cq *cq) 76 { 77 struct irdma_sc_dev *dev = &rf->sc_dev; 78 u32 compl_error; 79 int status; 80 81 do { 82 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 83 if (status == -ENOENT) 84 break; 85 if (status) { 86 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); 87 break; 88 } 89 if (compl_error) { 90 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n", 91 compl_error); 92 break; 93 } 94 } while (1); 95 96 irdma_sc_ccq_arm(cq); 97 } 98 99 /** 100 * irdma_process_ceq - handle ceq for completions 101 * @rf: RDMA PCI function 102 * @ceq: ceq having cq for completion 103 */ 104 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 105 { 106 struct irdma_sc_dev *dev = &rf->sc_dev; 107 struct irdma_sc_ceq *sc_ceq; 108 struct irdma_sc_cq *cq; 109 unsigned long flags; 110 111 sc_ceq = &ceq->sc_ceq; 112 do { 113 spin_lock_irqsave(&ceq->ce_lock, flags); 114 cq = irdma_sc_process_ceq(dev, sc_ceq); 115 if (!cq) { 116 spin_unlock_irqrestore(&ceq->ce_lock, flags); 117 break; 118 } 119 120 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 121 irdma_iwarp_ce_handler(cq); 122 123 spin_unlock_irqrestore(&ceq->ce_lock, flags); 124 125 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 126 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 127 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 128 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 129 irdma_puda_ce_handler(rf, cq); 130 } while (1); 131 } 132 133 static void irdma_set_flush_fields(struct irdma_sc_qp *qp, 134 struct irdma_aeqe_info *info) 135 { 136 qp->sq_flush_code = info->sq; 137 qp->rq_flush_code = info->rq; 138 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 139 140 switch (info->ae_id) { 141 case IRDMA_AE_AMP_UNALLOCATED_STAG: 142 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 143 case IRDMA_AE_AMP_INVALID_STAG: 144 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 145 fallthrough; 146 case IRDMA_AE_AMP_BAD_PD: 147 case IRDMA_AE_UDA_XMIT_BAD_PD: 148 qp->flush_code = FLUSH_PROT_ERR; 149 break; 150 case IRDMA_AE_AMP_BAD_QP: 151 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 152 qp->flush_code = FLUSH_LOC_QP_OP_ERR; 153 break; 154 case IRDMA_AE_AMP_BAD_STAG_KEY: 155 case IRDMA_AE_AMP_BAD_STAG_INDEX: 156 case IRDMA_AE_AMP_TO_WRAP: 157 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 158 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 159 case IRDMA_AE_PRIV_OPERATION_DENIED: 160 case IRDMA_AE_IB_INVALID_REQUEST: 161 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 162 qp->flush_code = FLUSH_REM_ACCESS_ERR; 163 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 164 break; 165 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 166 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 167 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 168 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 169 case IRDMA_AE_UDA_L4LEN_INVALID: 170 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 171 qp->flush_code = FLUSH_LOC_LEN_ERR; 172 break; 173 case IRDMA_AE_LCE_QP_CATASTROPHIC: 174 qp->flush_code = FLUSH_FATAL_ERR; 175 break; 176 case IRDMA_AE_DDP_UBE_INVALID_MO: 177 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 178 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 179 qp->flush_code = FLUSH_GENERAL_ERR; 180 break; 181 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 182 qp->flush_code = FLUSH_RETRY_EXC_ERR; 183 break; 184 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 185 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 186 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 187 qp->flush_code = FLUSH_MW_BIND_ERR; 188 break; 189 case IRDMA_AE_IB_REMOTE_OP_ERROR: 190 qp->flush_code = FLUSH_REM_OP_ERR; 191 break; 192 default: 193 qp->flush_code = FLUSH_FATAL_ERR; 194 break; 195 } 196 } 197 198 /** 199 * irdma_process_aeq - handle aeq events 200 * @rf: RDMA PCI function 201 */ 202 static void irdma_process_aeq(struct irdma_pci_f *rf) 203 { 204 struct irdma_sc_dev *dev = &rf->sc_dev; 205 struct irdma_aeq *aeq = &rf->aeq; 206 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 207 struct irdma_aeqe_info aeinfo; 208 struct irdma_aeqe_info *info = &aeinfo; 209 int ret; 210 struct irdma_qp *iwqp = NULL; 211 struct irdma_sc_cq *cq = NULL; 212 struct irdma_cq *iwcq = NULL; 213 struct irdma_sc_qp *qp = NULL; 214 struct irdma_qp_host_ctx_info *ctx_info = NULL; 215 struct irdma_device *iwdev = rf->iwdev; 216 unsigned long flags; 217 218 u32 aeqcnt = 0; 219 220 if (!sc_aeq->size) 221 return; 222 223 do { 224 memset(info, 0, sizeof(*info)); 225 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 226 if (ret) 227 break; 228 229 aeqcnt++; 230 ibdev_dbg(&iwdev->ibdev, 231 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 232 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 233 info->iwarp_state, info->ae_src); 234 235 if (info->qp) { 236 spin_lock_irqsave(&rf->qptable_lock, flags); 237 iwqp = rf->qp_table[info->qp_cq_id]; 238 if (!iwqp) { 239 spin_unlock_irqrestore(&rf->qptable_lock, 240 flags); 241 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 242 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 243 wake_up(&iwdev->suspend_wq); 244 continue; 245 } 246 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", 247 info->qp_cq_id); 248 continue; 249 } 250 irdma_qp_add_ref(&iwqp->ibqp); 251 spin_unlock_irqrestore(&rf->qptable_lock, flags); 252 qp = &iwqp->sc_qp; 253 spin_lock_irqsave(&iwqp->lock, flags); 254 iwqp->hw_tcp_state = info->tcp_state; 255 iwqp->hw_iwarp_state = info->iwarp_state; 256 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 257 iwqp->last_aeq = info->ae_id; 258 spin_unlock_irqrestore(&iwqp->lock, flags); 259 ctx_info = &iwqp->ctx_info; 260 } else { 261 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 262 continue; 263 } 264 265 switch (info->ae_id) { 266 struct irdma_cm_node *cm_node; 267 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 268 cm_node = iwqp->cm_node; 269 if (cm_node->accept_pend) { 270 atomic_dec(&cm_node->listener->pend_accepts_cnt); 271 cm_node->accept_pend = 0; 272 } 273 iwqp->rts_ae_rcvd = 1; 274 wake_up_interruptible(&iwqp->waitq); 275 break; 276 case IRDMA_AE_LLP_FIN_RECEIVED: 277 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 278 if (qp->term_flags) 279 break; 280 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 281 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 282 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT && 283 iwqp->ibqp_state == IB_QPS_RTS) { 284 irdma_next_iw_state(iwqp, 285 IRDMA_QP_STATE_CLOSING, 286 0, 0, 0); 287 irdma_cm_disconn(iwqp); 288 } 289 irdma_schedule_cm_timer(iwqp->cm_node, 290 (struct irdma_puda_buf *)iwqp, 291 IRDMA_TIMER_TYPE_CLOSE, 292 1, 0); 293 } 294 break; 295 case IRDMA_AE_LLP_CLOSE_COMPLETE: 296 if (qp->term_flags) 297 irdma_terminate_done(qp, 0); 298 else 299 irdma_cm_disconn(iwqp); 300 break; 301 case IRDMA_AE_BAD_CLOSE: 302 case IRDMA_AE_RESET_SENT: 303 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 304 0); 305 irdma_cm_disconn(iwqp); 306 break; 307 case IRDMA_AE_LLP_CONNECTION_RESET: 308 if (atomic_read(&iwqp->close_timer_started)) 309 break; 310 irdma_cm_disconn(iwqp); 311 break; 312 case IRDMA_AE_QP_SUSPEND_COMPLETE: 313 if (iwqp->iwdev->vsi.tc_change_pending) { 314 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs); 315 wake_up(&iwqp->iwdev->suspend_wq); 316 } 317 break; 318 case IRDMA_AE_TERMINATE_SENT: 319 irdma_terminate_send_fin(qp); 320 break; 321 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 322 irdma_terminate_received(qp, info); 323 break; 324 case IRDMA_AE_CQ_OPERATION_ERROR: 325 ibdev_err(&iwdev->ibdev, 326 "Processing an iWARP related AE for CQ misc = 0x%04X\n", 327 info->ae_id); 328 cq = (struct irdma_sc_cq *)(unsigned long) 329 info->compl_ctx; 330 331 iwcq = cq->back_cq; 332 333 if (iwcq->ibcq.event_handler) { 334 struct ib_event ibevent; 335 336 ibevent.device = iwcq->ibcq.device; 337 ibevent.event = IB_EVENT_CQ_ERR; 338 ibevent.element.cq = &iwcq->ibcq; 339 iwcq->ibcq.event_handler(&ibevent, 340 iwcq->ibcq.cq_context); 341 } 342 break; 343 case IRDMA_AE_RESET_NOT_SENT: 344 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 345 case IRDMA_AE_RESOURCE_EXHAUSTION: 346 break; 347 case IRDMA_AE_PRIV_OPERATION_DENIED: 348 case IRDMA_AE_STAG_ZERO_INVALID: 349 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 350 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 351 case IRDMA_AE_DDP_UBE_INVALID_MO: 352 case IRDMA_AE_DDP_UBE_INVALID_QN: 353 case IRDMA_AE_DDP_NO_L_BIT: 354 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 355 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 356 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 357 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 358 case IRDMA_AE_INVALID_ARP_ENTRY: 359 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 360 case IRDMA_AE_STALE_ARP_ENTRY: 361 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 362 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 363 case IRDMA_AE_LLP_SYN_RECEIVED: 364 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 365 case IRDMA_AE_LCE_QP_CATASTROPHIC: 366 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 367 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 368 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 369 default: 370 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n", 371 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 372 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 373 ctx_info->roce_info->err_rq_idx_valid = info->rq; 374 if (info->rq) { 375 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 376 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 377 ctx_info); 378 } 379 irdma_set_flush_fields(qp, info); 380 irdma_cm_disconn(iwqp); 381 break; 382 } 383 ctx_info->iwarp_info->err_rq_idx_valid = info->rq; 384 if (info->rq) { 385 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 386 ctx_info->tcp_info_valid = false; 387 ctx_info->iwarp_info_valid = true; 388 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 389 ctx_info); 390 } 391 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 392 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 393 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 394 irdma_cm_disconn(iwqp); 395 } else { 396 irdma_terminate_connection(qp, info); 397 } 398 break; 399 } 400 if (info->qp) 401 irdma_qp_rem_ref(&iwqp->ibqp); 402 } while (1); 403 404 if (aeqcnt) 405 irdma_sc_repost_aeq_entries(dev, aeqcnt); 406 } 407 408 /** 409 * irdma_ena_intr - set up device interrupts 410 * @dev: hardware control device structure 411 * @msix_id: id of the interrupt to be enabled 412 */ 413 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 414 { 415 dev->irq_ops->irdma_en_irq(dev, msix_id); 416 } 417 418 /** 419 * irdma_dpc - tasklet for aeq and ceq 0 420 * @t: tasklet_struct ptr 421 */ 422 static void irdma_dpc(struct tasklet_struct *t) 423 { 424 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 425 426 if (rf->msix_shared) 427 irdma_process_ceq(rf, rf->ceqlist); 428 irdma_process_aeq(rf); 429 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 430 } 431 432 /** 433 * irdma_ceq_dpc - dpc handler for CEQ 434 * @t: tasklet_struct ptr 435 */ 436 static void irdma_ceq_dpc(struct tasklet_struct *t) 437 { 438 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 439 struct irdma_pci_f *rf = iwceq->rf; 440 441 irdma_process_ceq(rf, iwceq); 442 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 443 } 444 445 /** 446 * irdma_save_msix_info - copy msix vector information to iwarp device 447 * @rf: RDMA PCI function 448 * 449 * Allocate iwdev msix table and copy the msix info to the table 450 * Return 0 if successful, otherwise return error 451 */ 452 static int irdma_save_msix_info(struct irdma_pci_f *rf) 453 { 454 struct irdma_qvlist_info *iw_qvlist; 455 struct irdma_qv_info *iw_qvinfo; 456 struct msix_entry *pmsix; 457 u32 ceq_idx; 458 u32 i; 459 size_t size; 460 461 if (!rf->msix_count) 462 return -EINVAL; 463 464 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 465 size += struct_size(iw_qvlist, qv_info, rf->msix_count); 466 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 467 if (!rf->iw_msixtbl) 468 return -ENOMEM; 469 470 rf->iw_qvlist = (struct irdma_qvlist_info *) 471 (&rf->iw_msixtbl[rf->msix_count]); 472 iw_qvlist = rf->iw_qvlist; 473 iw_qvinfo = iw_qvlist->qv_info; 474 iw_qvlist->num_vectors = rf->msix_count; 475 if (rf->msix_count <= num_online_cpus()) 476 rf->msix_shared = true; 477 478 pmsix = rf->msix_entries; 479 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 480 rf->iw_msixtbl[i].idx = pmsix->entry; 481 rf->iw_msixtbl[i].irq = pmsix->vector; 482 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 483 if (!i) { 484 iw_qvinfo->aeq_idx = 0; 485 if (rf->msix_shared) 486 iw_qvinfo->ceq_idx = ceq_idx++; 487 else 488 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 489 } else { 490 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 491 iw_qvinfo->ceq_idx = ceq_idx++; 492 } 493 iw_qvinfo->itr_idx = 3; 494 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 495 pmsix++; 496 } 497 498 return 0; 499 } 500 501 /** 502 * irdma_irq_handler - interrupt handler for aeq and ceq0 503 * @irq: Interrupt request number 504 * @data: RDMA PCI function 505 */ 506 static irqreturn_t irdma_irq_handler(int irq, void *data) 507 { 508 struct irdma_pci_f *rf = data; 509 510 tasklet_schedule(&rf->dpc_tasklet); 511 512 return IRQ_HANDLED; 513 } 514 515 /** 516 * irdma_ceq_handler - interrupt handler for ceq 517 * @irq: interrupt request number 518 * @data: ceq pointer 519 */ 520 static irqreturn_t irdma_ceq_handler(int irq, void *data) 521 { 522 struct irdma_ceq *iwceq = data; 523 524 if (iwceq->irq != irq) 525 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n", 526 iwceq->irq, irq); 527 tasklet_schedule(&iwceq->dpc_tasklet); 528 529 return IRQ_HANDLED; 530 } 531 532 /** 533 * irdma_destroy_irq - destroy device interrupts 534 * @rf: RDMA PCI function 535 * @msix_vec: msix vector to disable irq 536 * @dev_id: parameter to pass to free_irq (used during irq setup) 537 * 538 * The function is called when destroying aeq/ceq 539 */ 540 static void irdma_destroy_irq(struct irdma_pci_f *rf, 541 struct irdma_msix_vector *msix_vec, void *dev_id) 542 { 543 struct irdma_sc_dev *dev = &rf->sc_dev; 544 545 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 546 irq_update_affinity_hint(msix_vec->irq, NULL); 547 free_irq(msix_vec->irq, dev_id); 548 } 549 550 /** 551 * irdma_destroy_cqp - destroy control qp 552 * @rf: RDMA PCI function 553 * @free_hwcqp: 1 if hw cqp should be freed 554 * 555 * Issue destroy cqp request and 556 * free the resources associated with the cqp 557 */ 558 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) 559 { 560 struct irdma_sc_dev *dev = &rf->sc_dev; 561 struct irdma_cqp *cqp = &rf->cqp; 562 int status = 0; 563 564 if (rf->cqp_cmpl_wq) 565 destroy_workqueue(rf->cqp_cmpl_wq); 566 if (free_hwcqp) 567 status = irdma_sc_cqp_destroy(dev->cqp); 568 if (status) 569 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); 570 571 irdma_cleanup_pending_cqp_op(rf); 572 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, 573 cqp->sq.pa); 574 cqp->sq.va = NULL; 575 kfree(cqp->scratch_array); 576 cqp->scratch_array = NULL; 577 kfree(cqp->cqp_requests); 578 cqp->cqp_requests = NULL; 579 } 580 581 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 582 { 583 struct irdma_aeq *aeq = &rf->aeq; 584 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 585 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 586 587 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 588 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 589 vfree(aeq->mem.va); 590 } 591 592 /** 593 * irdma_destroy_aeq - destroy aeq 594 * @rf: RDMA PCI function 595 * 596 * Issue a destroy aeq request and 597 * free the resources associated with the aeq 598 * The function is called during driver unload 599 */ 600 static void irdma_destroy_aeq(struct irdma_pci_f *rf) 601 { 602 struct irdma_sc_dev *dev = &rf->sc_dev; 603 struct irdma_aeq *aeq = &rf->aeq; 604 int status = -EBUSY; 605 606 if (!rf->msix_shared) { 607 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 608 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 609 } 610 if (rf->reset) 611 goto exit; 612 613 aeq->sc_aeq.size = 0; 614 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 615 if (status) 616 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); 617 618 exit: 619 if (aeq->virtual_map) { 620 irdma_destroy_virt_aeq(rf); 621 } else { 622 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 623 aeq->mem.pa); 624 aeq->mem.va = NULL; 625 } 626 } 627 628 /** 629 * irdma_destroy_ceq - destroy ceq 630 * @rf: RDMA PCI function 631 * @iwceq: ceq to be destroyed 632 * 633 * Issue a destroy ceq request and 634 * free the resources associated with the ceq 635 */ 636 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 637 { 638 struct irdma_sc_dev *dev = &rf->sc_dev; 639 int status; 640 641 if (rf->reset) 642 goto exit; 643 644 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 645 if (status) { 646 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); 647 goto exit; 648 } 649 650 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 651 if (status) 652 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", 653 status); 654 exit: 655 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, 656 iwceq->mem.pa); 657 iwceq->mem.va = NULL; 658 } 659 660 /** 661 * irdma_del_ceq_0 - destroy ceq 0 662 * @rf: RDMA PCI function 663 * 664 * Disable the ceq 0 interrupt and destroy the ceq 0 665 */ 666 static void irdma_del_ceq_0(struct irdma_pci_f *rf) 667 { 668 struct irdma_ceq *iwceq = rf->ceqlist; 669 struct irdma_msix_vector *msix_vec; 670 671 if (rf->msix_shared) { 672 msix_vec = &rf->iw_msixtbl[0]; 673 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 674 msix_vec->ceq_id, 675 msix_vec->idx, false); 676 irdma_destroy_irq(rf, msix_vec, rf); 677 } else { 678 msix_vec = &rf->iw_msixtbl[1]; 679 irdma_destroy_irq(rf, msix_vec, iwceq); 680 } 681 682 irdma_destroy_ceq(rf, iwceq); 683 rf->sc_dev.ceq_valid = false; 684 rf->ceqs_count = 0; 685 } 686 687 /** 688 * irdma_del_ceqs - destroy all ceq's except CEQ 0 689 * @rf: RDMA PCI function 690 * 691 * Go through all of the device ceq's, except 0, and for each 692 * ceq disable the ceq interrupt and destroy the ceq 693 */ 694 static void irdma_del_ceqs(struct irdma_pci_f *rf) 695 { 696 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 697 struct irdma_msix_vector *msix_vec; 698 u32 i = 0; 699 700 if (rf->msix_shared) 701 msix_vec = &rf->iw_msixtbl[1]; 702 else 703 msix_vec = &rf->iw_msixtbl[2]; 704 705 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 706 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 707 msix_vec->idx, false); 708 irdma_destroy_irq(rf, msix_vec, iwceq); 709 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 710 IRDMA_OP_CEQ_DESTROY); 711 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, 712 iwceq->mem.va, iwceq->mem.pa); 713 iwceq->mem.va = NULL; 714 } 715 rf->ceqs_count = 1; 716 } 717 718 /** 719 * irdma_destroy_ccq - destroy control cq 720 * @rf: RDMA PCI function 721 * 722 * Issue destroy ccq request and 723 * free the resources associated with the ccq 724 */ 725 static void irdma_destroy_ccq(struct irdma_pci_f *rf) 726 { 727 struct irdma_sc_dev *dev = &rf->sc_dev; 728 struct irdma_ccq *ccq = &rf->ccq; 729 int status = 0; 730 731 if (!rf->reset) 732 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 733 if (status) 734 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); 735 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, 736 ccq->mem_cq.pa); 737 ccq->mem_cq.va = NULL; 738 } 739 740 /** 741 * irdma_close_hmc_objects_type - delete hmc objects of a given type 742 * @dev: iwarp device 743 * @obj_type: the hmc object type to be deleted 744 * @hmc_info: host memory info struct 745 * @privileged: permission to close HMC objects 746 * @reset: true if called before reset 747 */ 748 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 749 enum irdma_hmc_rsrc_type obj_type, 750 struct irdma_hmc_info *hmc_info, 751 bool privileged, bool reset) 752 { 753 struct irdma_hmc_del_obj_info info = {}; 754 755 info.hmc_info = hmc_info; 756 info.rsrc_type = obj_type; 757 info.count = hmc_info->hmc_obj[obj_type].cnt; 758 info.privileged = privileged; 759 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 760 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", 761 obj_type); 762 } 763 764 /** 765 * irdma_del_hmc_objects - remove all device hmc objects 766 * @dev: iwarp device 767 * @hmc_info: hmc_info to free 768 * @privileged: permission to delete HMC objects 769 * @reset: true if called before reset 770 * @vers: hardware version 771 */ 772 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev, 773 struct irdma_hmc_info *hmc_info, bool privileged, 774 bool reset, enum irdma_vers vers) 775 { 776 unsigned int i; 777 778 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 779 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 780 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 781 hmc_info, privileged, reset); 782 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 783 break; 784 } 785 } 786 787 /** 788 * irdma_create_hmc_obj_type - create hmc object of a given type 789 * @dev: hardware control device structure 790 * @info: information for the hmc object to create 791 */ 792 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 793 struct irdma_hmc_create_obj_info *info) 794 { 795 return irdma_sc_create_hmc_obj(dev, info); 796 } 797 798 /** 799 * irdma_create_hmc_objs - create all hmc objects for the device 800 * @rf: RDMA PCI function 801 * @privileged: permission to create HMC objects 802 * @vers: HW version 803 * 804 * Create the device hmc objects and allocate hmc pages 805 * Return 0 if successful, otherwise clean up and return error 806 */ 807 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 808 enum irdma_vers vers) 809 { 810 struct irdma_sc_dev *dev = &rf->sc_dev; 811 struct irdma_hmc_create_obj_info info = {}; 812 int i, status = 0; 813 814 info.hmc_info = dev->hmc_info; 815 info.privileged = privileged; 816 info.entry_type = rf->sd_type; 817 818 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 819 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 820 info.rsrc_type = iw_hmc_obj_types[i]; 821 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 822 info.add_sd_cnt = 0; 823 status = irdma_create_hmc_obj_type(dev, &info); 824 if (status) { 825 ibdev_dbg(to_ibdev(dev), 826 "ERR: create obj type %d status = %d\n", 827 iw_hmc_obj_types[i], status); 828 break; 829 } 830 } 831 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 832 break; 833 } 834 835 if (!status) 836 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 837 true, true); 838 839 while (i) { 840 i--; 841 /* destroy the hmc objects of a given type */ 842 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 843 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 844 dev->hmc_info, privileged, 845 false); 846 } 847 848 return status; 849 } 850 851 /** 852 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 853 * @rf: RDMA PCI function 854 * @memptr: points to the memory addresses 855 * @size: size of memory needed 856 * @mask: mask for the aligned memory 857 * 858 * Get aligned memory of the requested size and 859 * update the memptr to point to the new aligned memory 860 * Return 0 if successful, otherwise return no memory error 861 */ 862 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf, 863 struct irdma_dma_mem *memptr, u32 size, 864 u32 mask) 865 { 866 unsigned long va, newva; 867 unsigned long extra; 868 869 va = (unsigned long)rf->obj_next.va; 870 newva = va; 871 if (mask) 872 newva = ALIGN(va, (unsigned long)mask + 1ULL); 873 extra = newva - va; 874 memptr->va = (u8 *)va + extra; 875 memptr->pa = rf->obj_next.pa + extra; 876 memptr->size = size; 877 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 878 return -ENOMEM; 879 880 rf->obj_next.va = (u8 *)memptr->va + size; 881 rf->obj_next.pa = memptr->pa + size; 882 883 return 0; 884 } 885 886 /** 887 * irdma_create_cqp - create control qp 888 * @rf: RDMA PCI function 889 * 890 * Return 0, if the cqp and all the resources associated with it 891 * are successfully created, otherwise return error 892 */ 893 static int irdma_create_cqp(struct irdma_pci_f *rf) 894 { 895 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 896 struct irdma_dma_mem mem; 897 struct irdma_sc_dev *dev = &rf->sc_dev; 898 struct irdma_cqp_init_info cqp_init_info = {}; 899 struct irdma_cqp *cqp = &rf->cqp; 900 u16 maj_err, min_err; 901 int i, status; 902 903 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 904 if (!cqp->cqp_requests) 905 return -ENOMEM; 906 907 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 908 if (!cqp->scratch_array) { 909 kfree(cqp->cqp_requests); 910 return -ENOMEM; 911 } 912 913 dev->cqp = &cqp->sc_cqp; 914 dev->cqp->dev = dev; 915 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, 916 IRDMA_CQP_ALIGNMENT); 917 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, 918 &cqp->sq.pa, GFP_KERNEL); 919 if (!cqp->sq.va) { 920 kfree(cqp->scratch_array); 921 kfree(cqp->cqp_requests); 922 return -ENOMEM; 923 } 924 925 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 926 IRDMA_HOST_CTX_ALIGNMENT_M); 927 if (status) 928 goto exit; 929 930 dev->cqp->host_ctx_pa = mem.pa; 931 dev->cqp->host_ctx = mem.va; 932 /* populate the cqp init info */ 933 cqp_init_info.dev = dev; 934 cqp_init_info.sq_size = sqsize; 935 cqp_init_info.sq = cqp->sq.va; 936 cqp_init_info.sq_pa = cqp->sq.pa; 937 cqp_init_info.host_ctx_pa = mem.pa; 938 cqp_init_info.host_ctx = mem.va; 939 cqp_init_info.hmc_profile = rf->rsrc_profile; 940 cqp_init_info.scratch_array = cqp->scratch_array; 941 cqp_init_info.protocol_used = rf->protocol_used; 942 943 switch (rf->rdma_ver) { 944 case IRDMA_GEN_1: 945 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 946 break; 947 case IRDMA_GEN_2: 948 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 949 break; 950 } 951 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 952 if (status) { 953 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); 954 goto exit; 955 } 956 957 spin_lock_init(&cqp->req_lock); 958 spin_lock_init(&cqp->compl_lock); 959 960 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 961 if (status) { 962 ibdev_dbg(to_ibdev(dev), 963 "ERR: cqp create failed - status %d maj_err %d min_err %d\n", 964 status, maj_err, min_err); 965 goto exit; 966 } 967 968 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 969 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 970 971 /* init the waitqueue of the cqp_requests and add them to the list */ 972 for (i = 0; i < sqsize; i++) { 973 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 974 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 975 } 976 init_waitqueue_head(&cqp->remove_wq); 977 return 0; 978 979 exit: 980 irdma_destroy_cqp(rf, false); 981 982 return status; 983 } 984 985 /** 986 * irdma_create_ccq - create control cq 987 * @rf: RDMA PCI function 988 * 989 * Return 0, if the ccq and the resources associated with it 990 * are successfully created, otherwise return error 991 */ 992 static int irdma_create_ccq(struct irdma_pci_f *rf) 993 { 994 struct irdma_sc_dev *dev = &rf->sc_dev; 995 struct irdma_ccq_init_info info = {}; 996 struct irdma_ccq *ccq = &rf->ccq; 997 int status; 998 999 dev->ccq = &ccq->sc_cq; 1000 dev->ccq->dev = dev; 1001 info.dev = dev; 1002 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1003 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, 1004 IRDMA_CQ0_ALIGNMENT); 1005 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, 1006 &ccq->mem_cq.pa, GFP_KERNEL); 1007 if (!ccq->mem_cq.va) 1008 return -ENOMEM; 1009 1010 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1011 ccq->shadow_area.size, 1012 IRDMA_SHADOWAREA_M); 1013 if (status) 1014 goto exit; 1015 1016 ccq->sc_cq.back_cq = ccq; 1017 /* populate the ccq init info */ 1018 info.cq_base = ccq->mem_cq.va; 1019 info.cq_pa = ccq->mem_cq.pa; 1020 info.num_elem = IW_CCQ_SIZE; 1021 info.shadow_area = ccq->shadow_area.va; 1022 info.shadow_area_pa = ccq->shadow_area.pa; 1023 info.ceqe_mask = false; 1024 info.ceq_id_valid = true; 1025 info.shadow_read_threshold = 16; 1026 info.vsi = &rf->default_vsi; 1027 status = irdma_sc_ccq_init(dev->ccq, &info); 1028 if (!status) 1029 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1030 exit: 1031 if (status) { 1032 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, 1033 ccq->mem_cq.va, ccq->mem_cq.pa); 1034 ccq->mem_cq.va = NULL; 1035 } 1036 1037 return status; 1038 } 1039 1040 /** 1041 * irdma_alloc_set_mac - set up a mac address table entry 1042 * @iwdev: irdma device 1043 * 1044 * Allocate a mac ip entry and add it to the hw table Return 0 1045 * if successful, otherwise return error 1046 */ 1047 static int irdma_alloc_set_mac(struct irdma_device *iwdev) 1048 { 1049 int status; 1050 1051 status = irdma_alloc_local_mac_entry(iwdev->rf, 1052 &iwdev->mac_ip_table_idx); 1053 if (!status) { 1054 status = irdma_add_local_mac_entry(iwdev->rf, 1055 (const u8 *)iwdev->netdev->dev_addr, 1056 (u8)iwdev->mac_ip_table_idx); 1057 if (status) 1058 irdma_del_local_mac_entry(iwdev->rf, 1059 (u8)iwdev->mac_ip_table_idx); 1060 } 1061 return status; 1062 } 1063 1064 /** 1065 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1066 * ceq 1067 * @rf: RDMA PCI function 1068 * @iwceq: ceq associated with the vector 1069 * @ceq_id: the id number of the iwceq 1070 * @msix_vec: interrupt vector information 1071 * 1072 * Allocate interrupt resources and enable irq handling 1073 * Return 0 if successful, otherwise return error 1074 */ 1075 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1076 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1077 { 1078 int status; 1079 1080 if (rf->msix_shared && !ceq_id) { 1081 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1082 status = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1083 "AEQCEQ", rf); 1084 } else { 1085 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1086 1087 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0, 1088 "CEQ", iwceq); 1089 } 1090 cpumask_clear(&msix_vec->mask); 1091 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); 1092 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask); 1093 if (status) { 1094 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); 1095 return status; 1096 } 1097 1098 msix_vec->ceq_id = ceq_id; 1099 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1100 1101 return 0; 1102 } 1103 1104 /** 1105 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1106 * @rf: RDMA PCI function 1107 * 1108 * Allocate interrupt resources and enable irq handling 1109 * Return 0 if successful, otherwise return error 1110 */ 1111 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1112 { 1113 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1114 u32 ret = 0; 1115 1116 if (!rf->msix_shared) { 1117 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1118 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1119 "irdma", rf); 1120 } 1121 if (ret) { 1122 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); 1123 return -EINVAL; 1124 } 1125 1126 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1127 1128 return 0; 1129 } 1130 1131 /** 1132 * irdma_create_ceq - create completion event queue 1133 * @rf: RDMA PCI function 1134 * @iwceq: pointer to the ceq resources to be created 1135 * @ceq_id: the id number of the iwceq 1136 * @vsi: SC vsi struct 1137 * 1138 * Return 0, if the ceq and the resources associated with it 1139 * are successfully created, otherwise return error 1140 */ 1141 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1142 u32 ceq_id, struct irdma_sc_vsi *vsi) 1143 { 1144 int status; 1145 struct irdma_ceq_init_info info = {}; 1146 struct irdma_sc_dev *dev = &rf->sc_dev; 1147 u64 scratch; 1148 u32 ceq_size; 1149 1150 info.ceq_id = ceq_id; 1151 iwceq->rf = rf; 1152 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1153 dev->hw_attrs.max_hw_ceq_size); 1154 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, 1155 IRDMA_CEQ_ALIGNMENT); 1156 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, 1157 &iwceq->mem.pa, GFP_KERNEL); 1158 if (!iwceq->mem.va) 1159 return -ENOMEM; 1160 1161 info.ceq_id = ceq_id; 1162 info.ceqe_base = iwceq->mem.va; 1163 info.ceqe_pa = iwceq->mem.pa; 1164 info.elem_cnt = ceq_size; 1165 iwceq->sc_ceq.ceq_id = ceq_id; 1166 info.dev = dev; 1167 info.vsi = vsi; 1168 scratch = (uintptr_t)&rf->cqp.sc_cqp; 1169 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1170 if (!status) { 1171 if (dev->ceq_valid) 1172 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1173 IRDMA_OP_CEQ_CREATE); 1174 else 1175 status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch); 1176 } 1177 1178 if (status) { 1179 dma_free_coherent(dev->hw->device, iwceq->mem.size, 1180 iwceq->mem.va, iwceq->mem.pa); 1181 iwceq->mem.va = NULL; 1182 } 1183 1184 return status; 1185 } 1186 1187 /** 1188 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1189 * @rf: RDMA PCI function 1190 * 1191 * Allocate a list for all device completion event queues 1192 * Create the ceq 0 and configure it's msix interrupt vector 1193 * Return 0, if successfully set up, otherwise return error 1194 */ 1195 static int irdma_setup_ceq_0(struct irdma_pci_f *rf) 1196 { 1197 struct irdma_ceq *iwceq; 1198 struct irdma_msix_vector *msix_vec; 1199 u32 i; 1200 int status = 0; 1201 u32 num_ceqs; 1202 1203 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1204 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1205 if (!rf->ceqlist) { 1206 status = -ENOMEM; 1207 goto exit; 1208 } 1209 1210 iwceq = &rf->ceqlist[0]; 1211 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1212 if (status) { 1213 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", 1214 status); 1215 goto exit; 1216 } 1217 1218 spin_lock_init(&iwceq->ce_lock); 1219 i = rf->msix_shared ? 0 : 1; 1220 msix_vec = &rf->iw_msixtbl[i]; 1221 iwceq->irq = msix_vec->irq; 1222 iwceq->msix_idx = msix_vec->idx; 1223 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1224 if (status) { 1225 irdma_destroy_ceq(rf, iwceq); 1226 goto exit; 1227 } 1228 1229 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1230 rf->ceqs_count++; 1231 1232 exit: 1233 if (status && !rf->ceqs_count) { 1234 kfree(rf->ceqlist); 1235 rf->ceqlist = NULL; 1236 return status; 1237 } 1238 rf->sc_dev.ceq_valid = true; 1239 1240 return 0; 1241 } 1242 1243 /** 1244 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1245 * @rf: RDMA PCI function 1246 * @vsi: VSI structure for this CEQ 1247 * 1248 * Allocate a list for all device completion event queues 1249 * Create the ceq's and configure their msix interrupt vectors 1250 * Return 0, if ceqs are successfully set up, otherwise return error 1251 */ 1252 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1253 { 1254 u32 i; 1255 u32 ceq_id; 1256 struct irdma_ceq *iwceq; 1257 struct irdma_msix_vector *msix_vec; 1258 int status; 1259 u32 num_ceqs; 1260 1261 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1262 i = (rf->msix_shared) ? 1 : 2; 1263 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1264 iwceq = &rf->ceqlist[ceq_id]; 1265 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1266 if (status) { 1267 ibdev_dbg(&rf->iwdev->ibdev, 1268 "ERR: create ceq status = %d\n", status); 1269 goto del_ceqs; 1270 } 1271 spin_lock_init(&iwceq->ce_lock); 1272 msix_vec = &rf->iw_msixtbl[i]; 1273 iwceq->irq = msix_vec->irq; 1274 iwceq->msix_idx = msix_vec->idx; 1275 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1276 if (status) { 1277 irdma_destroy_ceq(rf, iwceq); 1278 goto del_ceqs; 1279 } 1280 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1281 rf->ceqs_count++; 1282 } 1283 1284 return 0; 1285 1286 del_ceqs: 1287 irdma_del_ceqs(rf); 1288 1289 return status; 1290 } 1291 1292 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1293 { 1294 struct irdma_aeq *aeq = &rf->aeq; 1295 dma_addr_t *pg_arr; 1296 u32 pg_cnt; 1297 int status; 1298 1299 if (rf->rdma_ver < IRDMA_GEN_2) 1300 return -EOPNOTSUPP; 1301 1302 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1303 aeq->mem.va = vzalloc(aeq->mem.size); 1304 1305 if (!aeq->mem.va) 1306 return -ENOMEM; 1307 1308 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1309 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1310 if (status) { 1311 vfree(aeq->mem.va); 1312 return status; 1313 } 1314 1315 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 1316 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1317 if (status) { 1318 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1319 vfree(aeq->mem.va); 1320 return status; 1321 } 1322 1323 return 0; 1324 } 1325 1326 /** 1327 * irdma_create_aeq - create async event queue 1328 * @rf: RDMA PCI function 1329 * 1330 * Return 0, if the aeq and the resources associated with it 1331 * are successfully created, otherwise return error 1332 */ 1333 static int irdma_create_aeq(struct irdma_pci_f *rf) 1334 { 1335 struct irdma_aeq_init_info info = {}; 1336 struct irdma_sc_dev *dev = &rf->sc_dev; 1337 struct irdma_aeq *aeq = &rf->aeq; 1338 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1339 u32 aeq_size; 1340 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1341 int status; 1342 1343 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1344 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1345 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1346 1347 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, 1348 IRDMA_AEQ_ALIGNMENT); 1349 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, 1350 &aeq->mem.pa, 1351 GFP_KERNEL | __GFP_NOWARN); 1352 if (aeq->mem.va) 1353 goto skip_virt_aeq; 1354 1355 /* physically mapped aeq failed. setup virtual aeq */ 1356 status = irdma_create_virt_aeq(rf, aeq_size); 1357 if (status) 1358 return status; 1359 1360 info.virtual_map = true; 1361 aeq->virtual_map = info.virtual_map; 1362 info.pbl_chunk_size = 1; 1363 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1364 1365 skip_virt_aeq: 1366 info.aeqe_base = aeq->mem.va; 1367 info.aeq_elem_pa = aeq->mem.pa; 1368 info.elem_cnt = aeq_size; 1369 info.dev = dev; 1370 info.msix_idx = rf->iw_msixtbl->idx; 1371 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1372 if (status) 1373 goto err; 1374 1375 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1376 if (status) 1377 goto err; 1378 1379 return 0; 1380 1381 err: 1382 if (aeq->virtual_map) { 1383 irdma_destroy_virt_aeq(rf); 1384 } else { 1385 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 1386 aeq->mem.pa); 1387 aeq->mem.va = NULL; 1388 } 1389 1390 return status; 1391 } 1392 1393 /** 1394 * irdma_setup_aeq - set up the device aeq 1395 * @rf: RDMA PCI function 1396 * 1397 * Create the aeq and configure its msix interrupt vector 1398 * Return 0 if successful, otherwise return error 1399 */ 1400 static int irdma_setup_aeq(struct irdma_pci_f *rf) 1401 { 1402 struct irdma_sc_dev *dev = &rf->sc_dev; 1403 int status; 1404 1405 status = irdma_create_aeq(rf); 1406 if (status) 1407 return status; 1408 1409 status = irdma_cfg_aeq_vector(rf); 1410 if (status) { 1411 irdma_destroy_aeq(rf); 1412 return status; 1413 } 1414 1415 if (!rf->msix_shared) 1416 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1417 1418 return 0; 1419 } 1420 1421 /** 1422 * irdma_initialize_ilq - create iwarp local queue for cm 1423 * @iwdev: irdma device 1424 * 1425 * Return 0 if successful, otherwise return error 1426 */ 1427 static int irdma_initialize_ilq(struct irdma_device *iwdev) 1428 { 1429 struct irdma_puda_rsrc_info info = {}; 1430 int status; 1431 1432 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1433 info.cq_id = 1; 1434 info.qp_id = 1; 1435 info.count = 1; 1436 info.pd_id = 1; 1437 info.abi_ver = IRDMA_ABI_VER; 1438 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1439 info.rq_size = info.sq_size; 1440 info.buf_size = 1024; 1441 info.tx_buf_cnt = 2 * info.sq_size; 1442 info.receive = irdma_receive_ilq; 1443 info.xmit_complete = irdma_free_sqbuf; 1444 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1445 if (status) 1446 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); 1447 1448 return status; 1449 } 1450 1451 /** 1452 * irdma_initialize_ieq - create iwarp exception queue 1453 * @iwdev: irdma device 1454 * 1455 * Return 0 if successful, otherwise return error 1456 */ 1457 static int irdma_initialize_ieq(struct irdma_device *iwdev) 1458 { 1459 struct irdma_puda_rsrc_info info = {}; 1460 int status; 1461 1462 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1463 info.cq_id = 2; 1464 info.qp_id = iwdev->vsi.exception_lan_q; 1465 info.count = 1; 1466 info.pd_id = 2; 1467 info.abi_ver = IRDMA_ABI_VER; 1468 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1469 info.rq_size = info.sq_size; 1470 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1471 info.tx_buf_cnt = 4096; 1472 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1473 if (status) 1474 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); 1475 1476 return status; 1477 } 1478 1479 /** 1480 * irdma_reinitialize_ieq - destroy and re-create ieq 1481 * @vsi: VSI structure 1482 */ 1483 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1484 { 1485 struct irdma_device *iwdev = vsi->back_vsi; 1486 struct irdma_pci_f *rf = iwdev->rf; 1487 1488 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1489 if (irdma_initialize_ieq(iwdev)) { 1490 iwdev->rf->reset = true; 1491 rf->gen_ops.request_reset(rf); 1492 } 1493 } 1494 1495 /** 1496 * irdma_hmc_setup - create hmc objects for the device 1497 * @rf: RDMA PCI function 1498 * 1499 * Set up the device private memory space for the number and size of 1500 * the hmc objects and create the objects 1501 * Return 0 if successful, otherwise return error 1502 */ 1503 static int irdma_hmc_setup(struct irdma_pci_f *rf) 1504 { 1505 int status; 1506 u32 qpcnt; 1507 1508 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1509 1510 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1511 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt); 1512 if (status) 1513 return status; 1514 1515 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1516 1517 return status; 1518 } 1519 1520 /** 1521 * irdma_del_init_mem - deallocate memory resources 1522 * @rf: RDMA PCI function 1523 */ 1524 static void irdma_del_init_mem(struct irdma_pci_f *rf) 1525 { 1526 struct irdma_sc_dev *dev = &rf->sc_dev; 1527 1528 kfree(dev->hmc_info->sd_table.sd_entry); 1529 dev->hmc_info->sd_table.sd_entry = NULL; 1530 kfree(rf->mem_rsrc); 1531 rf->mem_rsrc = NULL; 1532 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1533 rf->obj_mem.pa); 1534 rf->obj_mem.va = NULL; 1535 if (rf->rdma_ver != IRDMA_GEN_1) { 1536 bitmap_free(rf->allocated_ws_nodes); 1537 rf->allocated_ws_nodes = NULL; 1538 } 1539 kfree(rf->ceqlist); 1540 rf->ceqlist = NULL; 1541 kfree(rf->iw_msixtbl); 1542 rf->iw_msixtbl = NULL; 1543 kfree(rf->hmc_info_mem); 1544 rf->hmc_info_mem = NULL; 1545 } 1546 1547 /** 1548 * irdma_initialize_dev - initialize device 1549 * @rf: RDMA PCI function 1550 * 1551 * Allocate memory for the hmc objects and initialize iwdev 1552 * Return 0 if successful, otherwise clean up the resources 1553 * and return error 1554 */ 1555 static int irdma_initialize_dev(struct irdma_pci_f *rf) 1556 { 1557 int status; 1558 struct irdma_sc_dev *dev = &rf->sc_dev; 1559 struct irdma_device_init_info info = {}; 1560 struct irdma_dma_mem mem; 1561 u32 size; 1562 1563 size = sizeof(struct irdma_hmc_pble_rsrc) + 1564 sizeof(struct irdma_hmc_info) + 1565 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1566 1567 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1568 if (!rf->hmc_info_mem) 1569 return -ENOMEM; 1570 1571 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1572 dev->hmc_info = &rf->hw.hmc; 1573 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1574 (rf->pble_rsrc + 1); 1575 1576 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1577 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1578 if (status) 1579 goto error; 1580 1581 info.fpm_query_buf_pa = mem.pa; 1582 info.fpm_query_buf = mem.va; 1583 1584 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1585 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1586 if (status) 1587 goto error; 1588 1589 info.fpm_commit_buf_pa = mem.pa; 1590 info.fpm_commit_buf = mem.va; 1591 1592 info.bar0 = rf->hw.hw_addr; 1593 info.hmc_fn_id = rf->pf_id; 1594 info.hw = &rf->hw; 1595 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info); 1596 if (status) 1597 goto error; 1598 1599 return status; 1600 error: 1601 kfree(rf->hmc_info_mem); 1602 rf->hmc_info_mem = NULL; 1603 1604 return status; 1605 } 1606 1607 /** 1608 * irdma_rt_deinit_hw - clean up the irdma device resources 1609 * @iwdev: irdma device 1610 * 1611 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1612 * device queues and free the pble and the hmc objects 1613 */ 1614 void irdma_rt_deinit_hw(struct irdma_device *iwdev) 1615 { 1616 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); 1617 1618 switch (iwdev->init_state) { 1619 case IP_ADDR_REGISTERED: 1620 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1621 irdma_del_local_mac_entry(iwdev->rf, 1622 (u8)iwdev->mac_ip_table_idx); 1623 fallthrough; 1624 case AEQ_CREATED: 1625 case PBLE_CHUNK_MEM: 1626 case CEQS_CREATED: 1627 case IEQ_CREATED: 1628 if (!iwdev->roce_mode) 1629 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1630 iwdev->rf->reset); 1631 fallthrough; 1632 case ILQ_CREATED: 1633 if (!iwdev->roce_mode) 1634 irdma_puda_dele_rsrc(&iwdev->vsi, 1635 IRDMA_PUDA_RSRC_TYPE_ILQ, 1636 iwdev->rf->reset); 1637 break; 1638 default: 1639 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1640 break; 1641 } 1642 1643 irdma_cleanup_cm_core(&iwdev->cm_core); 1644 if (iwdev->vsi.pestat) { 1645 irdma_vsi_stats_free(&iwdev->vsi); 1646 kfree(iwdev->vsi.pestat); 1647 } 1648 if (iwdev->cleanup_wq) 1649 destroy_workqueue(iwdev->cleanup_wq); 1650 } 1651 1652 static int irdma_setup_init_state(struct irdma_pci_f *rf) 1653 { 1654 int status; 1655 1656 status = irdma_save_msix_info(rf); 1657 if (status) 1658 return status; 1659 1660 rf->hw.device = &rf->pcidev->dev; 1661 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); 1662 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, 1663 &rf->obj_mem.pa, GFP_KERNEL); 1664 if (!rf->obj_mem.va) { 1665 status = -ENOMEM; 1666 goto clean_msixtbl; 1667 } 1668 1669 rf->obj_next = rf->obj_mem; 1670 status = irdma_initialize_dev(rf); 1671 if (status) 1672 goto clean_obj_mem; 1673 1674 return 0; 1675 1676 clean_obj_mem: 1677 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1678 rf->obj_mem.pa); 1679 rf->obj_mem.va = NULL; 1680 clean_msixtbl: 1681 kfree(rf->iw_msixtbl); 1682 rf->iw_msixtbl = NULL; 1683 return status; 1684 } 1685 1686 /** 1687 * irdma_get_used_rsrc - determine resources used internally 1688 * @iwdev: irdma device 1689 * 1690 * Called at the end of open to get all internal allocations 1691 */ 1692 static void irdma_get_used_rsrc(struct irdma_device *iwdev) 1693 { 1694 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1695 iwdev->rf->max_pd); 1696 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1697 iwdev->rf->max_qp); 1698 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1699 iwdev->rf->max_cq); 1700 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1701 iwdev->rf->max_mr); 1702 } 1703 1704 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1705 { 1706 enum init_completion_state state = rf->init_state; 1707 1708 rf->init_state = INVALID_STATE; 1709 if (rf->rsrc_created) { 1710 irdma_destroy_aeq(rf); 1711 irdma_destroy_pble_prm(rf->pble_rsrc); 1712 irdma_del_ceqs(rf); 1713 rf->rsrc_created = false; 1714 } 1715 switch (state) { 1716 case CEQ0_CREATED: 1717 irdma_del_ceq_0(rf); 1718 fallthrough; 1719 case CCQ_CREATED: 1720 irdma_destroy_ccq(rf); 1721 fallthrough; 1722 case HW_RSRC_INITIALIZED: 1723 case HMC_OBJS_CREATED: 1724 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1725 rf->reset, rf->rdma_ver); 1726 fallthrough; 1727 case CQP_CREATED: 1728 irdma_destroy_cqp(rf, true); 1729 fallthrough; 1730 case INITIAL_STATE: 1731 irdma_del_init_mem(rf); 1732 break; 1733 case INVALID_STATE: 1734 default: 1735 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1736 break; 1737 } 1738 } 1739 1740 /** 1741 * irdma_rt_init_hw - Initializes runtime portion of HW 1742 * @iwdev: irdma device 1743 * @l2params: qos, tc, mtu info from netdev driver 1744 * 1745 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1746 * device resource objects. 1747 */ 1748 int irdma_rt_init_hw(struct irdma_device *iwdev, 1749 struct irdma_l2params *l2params) 1750 { 1751 struct irdma_pci_f *rf = iwdev->rf; 1752 struct irdma_sc_dev *dev = &rf->sc_dev; 1753 struct irdma_vsi_init_info vsi_info = {}; 1754 struct irdma_vsi_stats_info stats_info = {}; 1755 int status; 1756 1757 vsi_info.dev = dev; 1758 vsi_info.back_vsi = iwdev; 1759 vsi_info.params = l2params; 1760 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1761 vsi_info.register_qset = rf->gen_ops.register_qset; 1762 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1763 vsi_info.exception_lan_q = 2; 1764 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1765 1766 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1767 if (status) 1768 return status; 1769 1770 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1771 if (!stats_info.pestat) { 1772 irdma_cleanup_cm_core(&iwdev->cm_core); 1773 return -ENOMEM; 1774 } 1775 stats_info.fcn_id = dev->hmc_fn_id; 1776 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1777 if (status) { 1778 irdma_cleanup_cm_core(&iwdev->cm_core); 1779 kfree(stats_info.pestat); 1780 return status; 1781 } 1782 1783 do { 1784 if (!iwdev->roce_mode) { 1785 status = irdma_initialize_ilq(iwdev); 1786 if (status) 1787 break; 1788 iwdev->init_state = ILQ_CREATED; 1789 status = irdma_initialize_ieq(iwdev); 1790 if (status) 1791 break; 1792 iwdev->init_state = IEQ_CREATED; 1793 } 1794 if (!rf->rsrc_created) { 1795 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1796 if (status) 1797 break; 1798 1799 iwdev->init_state = CEQS_CREATED; 1800 1801 status = irdma_hmc_init_pble(&rf->sc_dev, 1802 rf->pble_rsrc); 1803 if (status) { 1804 irdma_del_ceqs(rf); 1805 break; 1806 } 1807 1808 iwdev->init_state = PBLE_CHUNK_MEM; 1809 1810 status = irdma_setup_aeq(rf); 1811 if (status) { 1812 irdma_destroy_pble_prm(rf->pble_rsrc); 1813 irdma_del_ceqs(rf); 1814 break; 1815 } 1816 iwdev->init_state = AEQ_CREATED; 1817 rf->rsrc_created = true; 1818 } 1819 1820 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1821 irdma_alloc_set_mac(iwdev); 1822 irdma_add_ip(iwdev); 1823 iwdev->init_state = IP_ADDR_REGISTERED; 1824 1825 /* handles asynch cleanup tasks - disconnect CM , free qp, 1826 * free cq bufs 1827 */ 1828 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1829 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1830 if (!iwdev->cleanup_wq) 1831 return -ENOMEM; 1832 irdma_get_used_rsrc(iwdev); 1833 init_waitqueue_head(&iwdev->suspend_wq); 1834 1835 return 0; 1836 } while (0); 1837 1838 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1839 status, iwdev->init_state); 1840 irdma_rt_deinit_hw(iwdev); 1841 1842 return status; 1843 } 1844 1845 /** 1846 * irdma_ctrl_init_hw - Initializes control portion of HW 1847 * @rf: RDMA PCI function 1848 * 1849 * Create admin queues, HMC obejcts and RF resource objects 1850 */ 1851 int irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1852 { 1853 struct irdma_sc_dev *dev = &rf->sc_dev; 1854 int status; 1855 do { 1856 status = irdma_setup_init_state(rf); 1857 if (status) 1858 break; 1859 rf->init_state = INITIAL_STATE; 1860 1861 status = irdma_create_cqp(rf); 1862 if (status) 1863 break; 1864 rf->init_state = CQP_CREATED; 1865 1866 status = irdma_hmc_setup(rf); 1867 if (status) 1868 break; 1869 rf->init_state = HMC_OBJS_CREATED; 1870 1871 status = irdma_initialize_hw_rsrc(rf); 1872 if (status) 1873 break; 1874 rf->init_state = HW_RSRC_INITIALIZED; 1875 1876 status = irdma_create_ccq(rf); 1877 if (status) 1878 break; 1879 rf->init_state = CCQ_CREATED; 1880 1881 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 1882 if (rf->rdma_ver != IRDMA_GEN_1) { 1883 status = irdma_get_rdma_features(dev); 1884 if (status) 1885 break; 1886 } 1887 1888 status = irdma_setup_ceq_0(rf); 1889 if (status) 1890 break; 1891 rf->init_state = CEQ0_CREATED; 1892 /* Handles processing of CQP completions */ 1893 rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", 1894 WQ_HIGHPRI | WQ_UNBOUND); 1895 if (!rf->cqp_cmpl_wq) { 1896 status = -ENOMEM; 1897 break; 1898 } 1899 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 1900 irdma_sc_ccq_arm(dev->ccq); 1901 return 0; 1902 } while (0); 1903 1904 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n", 1905 rf->init_state, status); 1906 irdma_ctrl_deinit_hw(rf); 1907 return status; 1908 } 1909 1910 /** 1911 * irdma_set_hw_rsrc - set hw memory resources. 1912 * @rf: RDMA PCI function 1913 */ 1914 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) 1915 { 1916 rf->allocated_qps = (void *)(rf->mem_rsrc + 1917 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 1918 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 1919 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 1920 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 1921 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 1922 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 1923 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 1924 rf->qp_table = (struct irdma_qp **) 1925 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 1926 1927 spin_lock_init(&rf->rsrc_lock); 1928 spin_lock_init(&rf->arp_lock); 1929 spin_lock_init(&rf->qptable_lock); 1930 spin_lock_init(&rf->qh_list_lock); 1931 } 1932 1933 /** 1934 * irdma_calc_mem_rsrc_size - calculate memory resources size. 1935 * @rf: RDMA PCI function 1936 */ 1937 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 1938 { 1939 u32 rsrc_size; 1940 1941 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 1942 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 1943 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 1944 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 1945 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 1946 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 1947 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 1948 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 1949 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 1950 1951 return rsrc_size; 1952 } 1953 1954 /** 1955 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 1956 * @rf: RDMA PCI function 1957 */ 1958 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 1959 { 1960 u32 rsrc_size; 1961 u32 mrdrvbits; 1962 u32 ret; 1963 1964 if (rf->rdma_ver != IRDMA_GEN_1) { 1965 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES, 1966 GFP_KERNEL); 1967 if (!rf->allocated_ws_nodes) 1968 return -ENOMEM; 1969 1970 set_bit(0, rf->allocated_ws_nodes); 1971 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 1972 } 1973 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 1974 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 1975 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 1976 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1977 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 1978 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 1979 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 1980 rf->max_mcg = rf->max_qp; 1981 1982 rsrc_size = irdma_calc_mem_rsrc_size(rf); 1983 rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL); 1984 if (!rf->mem_rsrc) { 1985 ret = -ENOMEM; 1986 goto mem_rsrc_kzalloc_fail; 1987 } 1988 1989 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 1990 1991 irdma_set_hw_rsrc(rf); 1992 1993 set_bit(0, rf->allocated_mrs); 1994 set_bit(0, rf->allocated_qps); 1995 set_bit(0, rf->allocated_cqs); 1996 set_bit(0, rf->allocated_pds); 1997 set_bit(0, rf->allocated_arps); 1998 set_bit(0, rf->allocated_ahs); 1999 set_bit(0, rf->allocated_mcgs); 2000 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2001 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2002 set_bit(1, rf->allocated_cqs); 2003 set_bit(1, rf->allocated_pds); 2004 set_bit(2, rf->allocated_cqs); 2005 set_bit(2, rf->allocated_pds); 2006 2007 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2008 /* stag index mask has a minimum of 14 bits */ 2009 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2010 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2011 2012 return 0; 2013 2014 mem_rsrc_kzalloc_fail: 2015 bitmap_free(rf->allocated_ws_nodes); 2016 rf->allocated_ws_nodes = NULL; 2017 2018 return ret; 2019 } 2020 2021 /** 2022 * irdma_cqp_ce_handler - handle cqp completions 2023 * @rf: RDMA PCI function 2024 * @cq: cq for cqp completions 2025 */ 2026 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2027 { 2028 struct irdma_cqp_request *cqp_request; 2029 struct irdma_sc_dev *dev = &rf->sc_dev; 2030 u32 cqe_count = 0; 2031 struct irdma_ccq_cqe_info info; 2032 unsigned long flags; 2033 int ret; 2034 2035 do { 2036 memset(&info, 0, sizeof(info)); 2037 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2038 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2039 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2040 if (ret) 2041 break; 2042 2043 cqp_request = (struct irdma_cqp_request *) 2044 (unsigned long)info.scratch; 2045 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2046 info.maj_err_code, 2047 info.min_err_code)) 2048 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2049 info.op_code, info.maj_err_code, info.min_err_code); 2050 if (cqp_request) { 2051 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2052 cqp_request->compl_info.min_err_code = info.min_err_code; 2053 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2054 cqp_request->compl_info.error = info.error; 2055 2056 if (cqp_request->waiting) { 2057 cqp_request->request_done = true; 2058 wake_up(&cqp_request->waitq); 2059 irdma_put_cqp_request(&rf->cqp, cqp_request); 2060 } else { 2061 if (cqp_request->callback_fcn) 2062 cqp_request->callback_fcn(cqp_request); 2063 irdma_put_cqp_request(&rf->cqp, cqp_request); 2064 } 2065 } 2066 2067 cqe_count++; 2068 } while (1); 2069 2070 if (cqe_count) { 2071 irdma_process_bh(dev); 2072 irdma_sc_ccq_arm(cq); 2073 } 2074 } 2075 2076 /** 2077 * cqp_compl_worker - Handle cqp completions 2078 * @work: Pointer to work structure 2079 */ 2080 void cqp_compl_worker(struct work_struct *work) 2081 { 2082 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2083 cqp_cmpl_work); 2084 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2085 2086 irdma_cqp_ce_handler(rf, cq); 2087 } 2088 2089 /** 2090 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2091 * @cm_core: cm's core 2092 * @port: port to identify apbvt entry 2093 */ 2094 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2095 u16 port) 2096 { 2097 struct irdma_apbvt_entry *entry; 2098 2099 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2100 if (entry->port == port) { 2101 entry->use_cnt++; 2102 return entry; 2103 } 2104 } 2105 2106 return NULL; 2107 } 2108 2109 /** 2110 * irdma_next_iw_state - modify qp state 2111 * @iwqp: iwarp qp to modify 2112 * @state: next state for qp 2113 * @del_hash: del hash 2114 * @term: term message 2115 * @termlen: length of term message 2116 */ 2117 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2118 u8 termlen) 2119 { 2120 struct irdma_modify_qp_info info = {}; 2121 2122 info.next_iwarp_state = state; 2123 info.remove_hash_idx = del_hash; 2124 info.cq_num_valid = true; 2125 info.arp_cache_idx_valid = true; 2126 info.dont_send_term = true; 2127 info.dont_send_fin = true; 2128 info.termlen = termlen; 2129 2130 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2131 info.dont_send_term = false; 2132 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2133 info.dont_send_fin = false; 2134 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2135 info.reset_tcp_conn = true; 2136 iwqp->hw_iwarp_state = state; 2137 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2138 iwqp->iwarp_state = info.next_iwarp_state; 2139 } 2140 2141 /** 2142 * irdma_del_local_mac_entry - remove a mac entry from the hw 2143 * table 2144 * @rf: RDMA PCI function 2145 * @idx: the index of the mac ip address to delete 2146 */ 2147 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2148 { 2149 struct irdma_cqp *iwcqp = &rf->cqp; 2150 struct irdma_cqp_request *cqp_request; 2151 struct cqp_cmds_info *cqp_info; 2152 2153 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2154 if (!cqp_request) 2155 return; 2156 2157 cqp_info = &cqp_request->info; 2158 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2159 cqp_info->post_sq = 1; 2160 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2161 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2162 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2163 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2164 2165 irdma_handle_cqp_op(rf, cqp_request); 2166 irdma_put_cqp_request(iwcqp, cqp_request); 2167 } 2168 2169 /** 2170 * irdma_add_local_mac_entry - add a mac ip address entry to the 2171 * hw table 2172 * @rf: RDMA PCI function 2173 * @mac_addr: pointer to mac address 2174 * @idx: the index of the mac ip address to add 2175 */ 2176 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2177 { 2178 struct irdma_local_mac_entry_info *info; 2179 struct irdma_cqp *iwcqp = &rf->cqp; 2180 struct irdma_cqp_request *cqp_request; 2181 struct cqp_cmds_info *cqp_info; 2182 int status; 2183 2184 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2185 if (!cqp_request) 2186 return -ENOMEM; 2187 2188 cqp_info = &cqp_request->info; 2189 cqp_info->post_sq = 1; 2190 info = &cqp_info->in.u.add_local_mac_entry.info; 2191 ether_addr_copy(info->mac_addr, mac_addr); 2192 info->entry_idx = idx; 2193 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2194 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2195 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2196 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2197 2198 status = irdma_handle_cqp_op(rf, cqp_request); 2199 irdma_put_cqp_request(iwcqp, cqp_request); 2200 2201 return status; 2202 } 2203 2204 /** 2205 * irdma_alloc_local_mac_entry - allocate a mac entry 2206 * @rf: RDMA PCI function 2207 * @mac_tbl_idx: the index of the new mac address 2208 * 2209 * Allocate a mac address entry and update the mac_tbl_idx 2210 * to hold the index of the newly created mac address 2211 * Return 0 if successful, otherwise return error 2212 */ 2213 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2214 { 2215 struct irdma_cqp *iwcqp = &rf->cqp; 2216 struct irdma_cqp_request *cqp_request; 2217 struct cqp_cmds_info *cqp_info; 2218 int status = 0; 2219 2220 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2221 if (!cqp_request) 2222 return -ENOMEM; 2223 2224 cqp_info = &cqp_request->info; 2225 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2226 cqp_info->post_sq = 1; 2227 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2228 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2229 status = irdma_handle_cqp_op(rf, cqp_request); 2230 if (!status) 2231 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2232 2233 irdma_put_cqp_request(iwcqp, cqp_request); 2234 2235 return status; 2236 } 2237 2238 /** 2239 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2240 * @iwdev: irdma device 2241 * @accel_local_port: port for apbvt 2242 * @add_port: add ordelete port 2243 */ 2244 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2245 u16 accel_local_port, bool add_port) 2246 { 2247 struct irdma_apbvt_info *info; 2248 struct irdma_cqp_request *cqp_request; 2249 struct cqp_cmds_info *cqp_info; 2250 int status; 2251 2252 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2253 if (!cqp_request) 2254 return -ENOMEM; 2255 2256 cqp_info = &cqp_request->info; 2257 info = &cqp_info->in.u.manage_apbvt_entry.info; 2258 memset(info, 0, sizeof(*info)); 2259 info->add = add_port; 2260 info->port = accel_local_port; 2261 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2262 cqp_info->post_sq = 1; 2263 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2264 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2265 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", 2266 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2267 2268 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2269 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2270 2271 return status; 2272 } 2273 2274 /** 2275 * irdma_add_apbvt - add tcp port to HW apbvt table 2276 * @iwdev: irdma device 2277 * @port: port for apbvt 2278 */ 2279 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2280 { 2281 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2282 struct irdma_apbvt_entry *entry; 2283 unsigned long flags; 2284 2285 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2286 entry = irdma_lookup_apbvt_entry(cm_core, port); 2287 if (entry) { 2288 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2289 return entry; 2290 } 2291 2292 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2293 if (!entry) { 2294 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2295 return NULL; 2296 } 2297 2298 entry->port = port; 2299 entry->use_cnt = 1; 2300 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2301 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2302 2303 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2304 kfree(entry); 2305 return NULL; 2306 } 2307 2308 return entry; 2309 } 2310 2311 /** 2312 * irdma_del_apbvt - delete tcp port from HW apbvt table 2313 * @iwdev: irdma device 2314 * @entry: apbvt entry object 2315 */ 2316 void irdma_del_apbvt(struct irdma_device *iwdev, 2317 struct irdma_apbvt_entry *entry) 2318 { 2319 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2320 unsigned long flags; 2321 2322 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2323 if (--entry->use_cnt) { 2324 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2325 return; 2326 } 2327 2328 hash_del(&entry->hlist); 2329 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to 2330 * protect against race where add APBVT CQP can race ahead of the delete 2331 * APBVT for same port. 2332 */ 2333 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2334 kfree(entry); 2335 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2336 } 2337 2338 /** 2339 * irdma_manage_arp_cache - manage hw arp cache 2340 * @rf: RDMA PCI function 2341 * @mac_addr: mac address ptr 2342 * @ip_addr: ip addr for arp cache 2343 * @ipv4: flag inicating IPv4 2344 * @action: add, delete or modify 2345 */ 2346 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 2347 const unsigned char *mac_addr, 2348 u32 *ip_addr, bool ipv4, u32 action) 2349 { 2350 struct irdma_add_arp_cache_entry_info *info; 2351 struct irdma_cqp_request *cqp_request; 2352 struct cqp_cmds_info *cqp_info; 2353 int arp_index; 2354 2355 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action); 2356 if (arp_index == -1) 2357 return; 2358 2359 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2360 if (!cqp_request) 2361 return; 2362 2363 cqp_info = &cqp_request->info; 2364 if (action == IRDMA_ARP_ADD) { 2365 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2366 info = &cqp_info->in.u.add_arp_cache_entry.info; 2367 memset(info, 0, sizeof(*info)); 2368 info->arp_index = (u16)arp_index; 2369 info->permanent = true; 2370 ether_addr_copy(info->mac_addr, mac_addr); 2371 cqp_info->in.u.add_arp_cache_entry.scratch = 2372 (uintptr_t)cqp_request; 2373 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2374 } else { 2375 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2376 cqp_info->in.u.del_arp_cache_entry.scratch = 2377 (uintptr_t)cqp_request; 2378 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2379 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2380 } 2381 2382 cqp_info->post_sq = 1; 2383 irdma_handle_cqp_op(rf, cqp_request); 2384 irdma_put_cqp_request(&rf->cqp, cqp_request); 2385 } 2386 2387 /** 2388 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2389 * @cqp_request: qhash cqp completion 2390 */ 2391 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2392 { 2393 struct irdma_cm_node *cm_node = cqp_request->param; 2394 2395 irdma_send_syn(cm_node, 1); 2396 irdma_rem_ref_cm_node(cm_node); 2397 } 2398 2399 /** 2400 * irdma_manage_qhash - add or modify qhash 2401 * @iwdev: irdma device 2402 * @cminfo: cm info for qhash 2403 * @etype: type (syn or quad) 2404 * @mtype: type of qhash 2405 * @cmnode: cmnode associated with connection 2406 * @wait: wait for completion 2407 */ 2408 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2409 enum irdma_quad_entry_type etype, 2410 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2411 bool wait) 2412 { 2413 struct irdma_qhash_table_info *info; 2414 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2415 struct irdma_cqp_request *cqp_request; 2416 struct cqp_cmds_info *cqp_info; 2417 struct irdma_cm_node *cm_node = cmnode; 2418 int status; 2419 2420 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2421 if (!cqp_request) 2422 return -ENOMEM; 2423 2424 cqp_info = &cqp_request->info; 2425 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2426 memset(info, 0, sizeof(*info)); 2427 info->vsi = &iwdev->vsi; 2428 info->manage = mtype; 2429 info->entry_type = etype; 2430 if (cminfo->vlan_id < VLAN_N_VID) { 2431 info->vlan_valid = true; 2432 info->vlan_id = cminfo->vlan_id; 2433 } else { 2434 info->vlan_valid = false; 2435 } 2436 info->ipv4_valid = cminfo->ipv4; 2437 info->user_pri = cminfo->user_pri; 2438 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 2439 info->qp_num = cminfo->qh_qpid; 2440 info->dest_port = cminfo->loc_port; 2441 info->dest_ip[0] = cminfo->loc_addr[0]; 2442 info->dest_ip[1] = cminfo->loc_addr[1]; 2443 info->dest_ip[2] = cminfo->loc_addr[2]; 2444 info->dest_ip[3] = cminfo->loc_addr[3]; 2445 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2446 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2447 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2448 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2449 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2450 info->src_port = cminfo->rem_port; 2451 info->src_ip[0] = cminfo->rem_addr[0]; 2452 info->src_ip[1] = cminfo->rem_addr[1]; 2453 info->src_ip[2] = cminfo->rem_addr[2]; 2454 info->src_ip[3] = cminfo->rem_addr[3]; 2455 } 2456 if (cmnode) { 2457 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2458 cqp_request->param = cmnode; 2459 if (!wait) 2460 refcount_inc(&cm_node->refcnt); 2461 } 2462 if (info->ipv4_valid) 2463 ibdev_dbg(&iwdev->ibdev, 2464 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2465 (!mtype) ? "DELETE" : "ADD", 2466 __builtin_return_address(0), info->dest_port, 2467 info->src_port, info->dest_ip, info->src_ip, 2468 info->mac_addr, cminfo->vlan_id, 2469 cmnode ? cmnode : NULL); 2470 else 2471 ibdev_dbg(&iwdev->ibdev, 2472 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2473 (!mtype) ? "DELETE" : "ADD", 2474 __builtin_return_address(0), info->dest_port, 2475 info->src_port, info->dest_ip, info->src_ip, 2476 info->mac_addr, cminfo->vlan_id, 2477 cmnode ? cmnode : NULL); 2478 2479 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2480 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2481 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2482 cqp_info->post_sq = 1; 2483 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2484 if (status && cm_node && !wait) 2485 irdma_rem_ref_cm_node(cm_node); 2486 2487 irdma_put_cqp_request(iwcqp, cqp_request); 2488 2489 return status; 2490 } 2491 2492 /** 2493 * irdma_hw_flush_wqes_callback - Check return code after flush 2494 * @cqp_request: qhash cqp completion 2495 */ 2496 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request) 2497 { 2498 struct irdma_qp_flush_info *hw_info; 2499 struct irdma_sc_qp *qp; 2500 struct irdma_qp *iwqp; 2501 struct cqp_cmds_info *cqp_info; 2502 2503 cqp_info = &cqp_request->info; 2504 hw_info = &cqp_info->in.u.qp_flush_wqes.info; 2505 qp = cqp_info->in.u.qp_flush_wqes.qp; 2506 iwqp = qp->qp_uk.back_qp; 2507 2508 if (cqp_request->compl_info.maj_err_code) 2509 return; 2510 2511 if (hw_info->rq && 2512 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2513 cqp_request->compl_info.min_err_code == 0)) { 2514 /* RQ WQE flush was requested but did not happen */ 2515 qp->qp_uk.rq_flush_complete = true; 2516 } 2517 if (hw_info->sq && 2518 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2519 cqp_request->compl_info.min_err_code == 0)) { 2520 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2521 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work", 2522 qp->qp_uk.qp_id); 2523 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2524 } 2525 qp->qp_uk.sq_flush_complete = true; 2526 } 2527 } 2528 2529 /** 2530 * irdma_hw_flush_wqes - flush qp's wqe 2531 * @rf: RDMA PCI function 2532 * @qp: hardware control qp 2533 * @info: info for flush 2534 * @wait: flag wait for completion 2535 */ 2536 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2537 struct irdma_qp_flush_info *info, bool wait) 2538 { 2539 int status; 2540 struct irdma_qp_flush_info *hw_info; 2541 struct irdma_cqp_request *cqp_request; 2542 struct cqp_cmds_info *cqp_info; 2543 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2544 2545 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2546 if (!cqp_request) 2547 return -ENOMEM; 2548 2549 cqp_info = &cqp_request->info; 2550 if (!wait) 2551 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback; 2552 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2553 memcpy(hw_info, info, sizeof(*hw_info)); 2554 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2555 cqp_info->post_sq = 1; 2556 cqp_info->in.u.qp_flush_wqes.qp = qp; 2557 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2558 status = irdma_handle_cqp_op(rf, cqp_request); 2559 if (status) { 2560 qp->qp_uk.sq_flush_complete = true; 2561 qp->qp_uk.rq_flush_complete = true; 2562 irdma_put_cqp_request(&rf->cqp, cqp_request); 2563 return status; 2564 } 2565 2566 if (!wait || cqp_request->compl_info.maj_err_code) 2567 goto put_cqp; 2568 2569 if (info->rq) { 2570 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2571 cqp_request->compl_info.min_err_code == 0) { 2572 /* RQ WQE flush was requested but did not happen */ 2573 qp->qp_uk.rq_flush_complete = true; 2574 } 2575 } 2576 if (info->sq) { 2577 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2578 cqp_request->compl_info.min_err_code == 0) { 2579 /* 2580 * Handling case where WQE is posted to empty SQ when 2581 * flush has not completed 2582 */ 2583 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2584 struct irdma_cqp_request *new_req; 2585 2586 if (!qp->qp_uk.sq_flush_complete) 2587 goto put_cqp; 2588 qp->qp_uk.sq_flush_complete = false; 2589 qp->flush_sq = false; 2590 2591 info->rq = false; 2592 info->sq = true; 2593 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 2594 if (!new_req) { 2595 status = -ENOMEM; 2596 goto put_cqp; 2597 } 2598 cqp_info = &new_req->info; 2599 hw_info = &new_req->info.in.u.qp_flush_wqes.info; 2600 memcpy(hw_info, info, sizeof(*hw_info)); 2601 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2602 cqp_info->post_sq = 1; 2603 cqp_info->in.u.qp_flush_wqes.qp = qp; 2604 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req; 2605 2606 status = irdma_handle_cqp_op(rf, new_req); 2607 if (new_req->compl_info.maj_err_code || 2608 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2609 status) { 2610 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d", 2611 iwqp->ibqp.qp_num); 2612 qp->qp_uk.sq_flush_complete = false; 2613 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2614 } 2615 irdma_put_cqp_request(&rf->cqp, new_req); 2616 } else { 2617 /* SQ WQE flush was requested but did not happen */ 2618 qp->qp_uk.sq_flush_complete = true; 2619 } 2620 } else { 2621 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) 2622 qp->qp_uk.sq_flush_complete = true; 2623 } 2624 } 2625 2626 ibdev_dbg(&rf->iwdev->ibdev, 2627 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2628 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2629 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2630 cqp_request->compl_info.maj_err_code, 2631 cqp_request->compl_info.min_err_code); 2632 put_cqp: 2633 irdma_put_cqp_request(&rf->cqp, cqp_request); 2634 2635 return status; 2636 } 2637 2638 /** 2639 * irdma_gen_ae - generate AE 2640 * @rf: RDMA PCI function 2641 * @qp: qp associated with AE 2642 * @info: info for ae 2643 * @wait: wait for completion 2644 */ 2645 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2646 struct irdma_gen_ae_info *info, bool wait) 2647 { 2648 struct irdma_gen_ae_info *ae_info; 2649 struct irdma_cqp_request *cqp_request; 2650 struct cqp_cmds_info *cqp_info; 2651 2652 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2653 if (!cqp_request) 2654 return; 2655 2656 cqp_info = &cqp_request->info; 2657 ae_info = &cqp_request->info.in.u.gen_ae.info; 2658 memcpy(ae_info, info, sizeof(*ae_info)); 2659 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2660 cqp_info->post_sq = 1; 2661 cqp_info->in.u.gen_ae.qp = qp; 2662 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2663 2664 irdma_handle_cqp_op(rf, cqp_request); 2665 irdma_put_cqp_request(&rf->cqp, cqp_request); 2666 } 2667 2668 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2669 { 2670 struct irdma_qp_flush_info info = {}; 2671 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2672 u8 flush_code = iwqp->sc_qp.flush_code; 2673 2674 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2675 return; 2676 2677 /* Set flush info fields*/ 2678 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2679 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2680 2681 /* Generate userflush errors in CQE */ 2682 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2683 info.sq_minor_code = FLUSH_GENERAL_ERR; 2684 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2685 info.rq_minor_code = FLUSH_GENERAL_ERR; 2686 info.userflushcode = true; 2687 2688 if (flush_mask & IRDMA_REFLUSH) { 2689 if (info.sq) 2690 iwqp->sc_qp.flush_sq = false; 2691 if (info.rq) 2692 iwqp->sc_qp.flush_rq = false; 2693 } else { 2694 if (flush_code) { 2695 if (info.sq && iwqp->sc_qp.sq_flush_code) 2696 info.sq_minor_code = flush_code; 2697 if (info.rq && iwqp->sc_qp.rq_flush_code) 2698 info.rq_minor_code = flush_code; 2699 } 2700 if (!iwqp->user_mode) 2701 queue_delayed_work(iwqp->iwdev->cleanup_wq, 2702 &iwqp->dwork_flush, 2703 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS)); 2704 } 2705 2706 /* Issue flush */ 2707 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2708 flush_mask & IRDMA_FLUSH_WAIT); 2709 iwqp->flush_issued = true; 2710 } 2711