1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "osdep.h" 4 #include "status.h" 5 #include "hmc.h" 6 #include "defs.h" 7 #include "type.h" 8 #include "ws.h" 9 #include "protos.h" 10 11 /** 12 * irdma_get_qp_from_list - get next qp from a list 13 * @head: Listhead of qp's 14 * @qp: current qp 15 */ 16 struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, 17 struct irdma_sc_qp *qp) 18 { 19 struct list_head *lastentry; 20 struct list_head *entry = NULL; 21 22 if (list_empty(head)) 23 return NULL; 24 25 if (!qp) { 26 entry = head->next; 27 } else { 28 lastentry = &qp->list; 29 entry = lastentry->next; 30 if (entry == head) 31 return NULL; 32 } 33 34 return container_of(entry, struct irdma_sc_qp, list); 35 } 36 37 /** 38 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI 39 * @vsi: the VSI struct pointer 40 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND 41 */ 42 void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op) 43 { 44 struct irdma_sc_qp *qp = NULL; 45 u8 i; 46 47 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 48 mutex_lock(&vsi->qos[i].qos_mutex); 49 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 50 while (qp) { 51 if (op == IRDMA_OP_RESUME) { 52 if (!qp->dev->ws_add(vsi, i)) { 53 qp->qs_handle = 54 vsi->qos[qp->user_pri].qs_handle; 55 irdma_cqp_qp_suspend_resume(qp, op); 56 } else { 57 irdma_cqp_qp_suspend_resume(qp, op); 58 irdma_modify_qp_to_err(qp); 59 } 60 } else if (op == IRDMA_OP_SUSPEND) { 61 /* issue cqp suspend command */ 62 if (!irdma_cqp_qp_suspend_resume(qp, op)) 63 atomic_inc(&vsi->qp_suspend_reqs); 64 } 65 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 66 } 67 mutex_unlock(&vsi->qos[i].qos_mutex); 68 } 69 } 70 71 /** 72 * irdma_change_l2params - given the new l2 parameters, change all qp 73 * @vsi: RDMA VSI pointer 74 * @l2params: New parameters from l2 75 */ 76 void irdma_change_l2params(struct irdma_sc_vsi *vsi, 77 struct irdma_l2params *l2params) 78 { 79 if (l2params->mtu_changed) { 80 vsi->mtu = l2params->mtu; 81 if (vsi->ieq) 82 irdma_reinitialize_ieq(vsi); 83 } 84 85 if (!l2params->tc_changed) 86 return; 87 88 vsi->tc_change_pending = false; 89 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME); 90 } 91 92 /** 93 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp 94 * @qp: qp to be removed from qos 95 */ 96 void irdma_qp_rem_qos(struct irdma_sc_qp *qp) 97 { 98 struct irdma_sc_vsi *vsi = qp->vsi; 99 100 ibdev_dbg(to_ibdev(qp->dev), 101 "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 102 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 103 qp->on_qoslist); 104 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 105 if (qp->on_qoslist) { 106 qp->on_qoslist = false; 107 list_del(&qp->list); 108 } 109 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 110 } 111 112 /** 113 * irdma_qp_add_qos - called during setctx for qp to be added to qos 114 * @qp: qp to be added to qos 115 */ 116 void irdma_qp_add_qos(struct irdma_sc_qp *qp) 117 { 118 struct irdma_sc_vsi *vsi = qp->vsi; 119 120 ibdev_dbg(to_ibdev(qp->dev), 121 "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 122 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 123 qp->on_qoslist); 124 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 125 if (!qp->on_qoslist) { 126 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); 127 qp->on_qoslist = true; 128 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle; 129 } 130 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 131 } 132 133 /** 134 * irdma_sc_pd_init - initialize sc pd struct 135 * @dev: sc device struct 136 * @pd: sc pd ptr 137 * @pd_id: pd_id for allocated pd 138 * @abi_ver: User/Kernel ABI version 139 */ 140 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, 141 int abi_ver) 142 { 143 pd->pd_id = pd_id; 144 pd->abi_ver = abi_ver; 145 pd->dev = dev; 146 } 147 148 /** 149 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry 150 * @cqp: struct for cqp hw 151 * @info: arp entry information 152 * @scratch: u64 saved to be used during cqp completion 153 * @post_sq: flag for cqp db to ring 154 */ 155 static enum irdma_status_code 156 irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp, 157 struct irdma_add_arp_cache_entry_info *info, 158 u64 scratch, bool post_sq) 159 { 160 __le64 *wqe; 161 u64 hdr; 162 163 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 164 if (!wqe) 165 return IRDMA_ERR_RING_FULL; 166 set_64bit_val(wqe, 8, info->reach_max); 167 set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr)); 168 169 hdr = info->arp_index | 170 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 171 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | 172 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | 173 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 174 dma_wmb(); /* make sure WQE is written before valid bit is set */ 175 176 set_64bit_val(wqe, 24, hdr); 177 178 print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET, 179 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 180 if (post_sq) 181 irdma_sc_cqp_post_sq(cqp); 182 183 return 0; 184 } 185 186 /** 187 * irdma_sc_del_arp_cache_entry - dele arp cache entry 188 * @cqp: struct for cqp hw 189 * @scratch: u64 saved to be used during cqp completion 190 * @arp_index: arp index to delete arp entry 191 * @post_sq: flag for cqp db to ring 192 */ 193 static enum irdma_status_code 194 irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch, 195 u16 arp_index, bool post_sq) 196 { 197 __le64 *wqe; 198 u64 hdr; 199 200 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 201 if (!wqe) 202 return IRDMA_ERR_RING_FULL; 203 204 hdr = arp_index | 205 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 206 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 207 dma_wmb(); /* make sure WQE is written before valid bit is set */ 208 209 set_64bit_val(wqe, 24, hdr); 210 211 print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE", 212 DUMP_PREFIX_OFFSET, 16, 8, wqe, 213 IRDMA_CQP_WQE_SIZE * 8, false); 214 if (post_sq) 215 irdma_sc_cqp_post_sq(cqp); 216 217 return 0; 218 } 219 220 /** 221 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries 222 * @cqp: struct for cqp hw 223 * @info: info for apbvt entry to add or delete 224 * @scratch: u64 saved to be used during cqp completion 225 * @post_sq: flag for cqp db to ring 226 */ 227 static enum irdma_status_code 228 irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp, 229 struct irdma_apbvt_info *info, u64 scratch, 230 bool post_sq) 231 { 232 __le64 *wqe; 233 u64 hdr; 234 235 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 236 if (!wqe) 237 return IRDMA_ERR_RING_FULL; 238 239 set_64bit_val(wqe, 16, info->port); 240 241 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | 242 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | 243 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 244 dma_wmb(); /* make sure WQE is written before valid bit is set */ 245 246 set_64bit_val(wqe, 24, hdr); 247 248 print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16, 249 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 250 if (post_sq) 251 irdma_sc_cqp_post_sq(cqp); 252 253 return 0; 254 } 255 256 /** 257 * irdma_sc_manage_qhash_table_entry - manage quad hash entries 258 * @cqp: struct for cqp hw 259 * @info: info for quad hash to manage 260 * @scratch: u64 saved to be used during cqp completion 261 * @post_sq: flag for cqp db to ring 262 * 263 * This is called before connection establishment is started. 264 * For passive connections, when listener is created, it will 265 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local 266 * ip address and tcp port. When SYN is received (passive 267 * connections) or sent (active connections), this routine is 268 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED 269 * and quad is passed in info. 270 * 271 * When iwarp connection is done and its state moves to RTS, the 272 * quad hash entry in the hardware will point to iwarp's qp 273 * number and requires no calls from the driver. 274 */ 275 static enum irdma_status_code 276 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp, 277 struct irdma_qhash_table_info *info, 278 u64 scratch, bool post_sq) 279 { 280 __le64 *wqe; 281 u64 qw1 = 0; 282 u64 qw2 = 0; 283 u64 temp; 284 struct irdma_sc_vsi *vsi = info->vsi; 285 286 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 287 if (!wqe) 288 return IRDMA_ERR_RING_FULL; 289 290 set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr)); 291 292 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | 293 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port); 294 if (info->ipv4_valid) { 295 set_64bit_val(wqe, 48, 296 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0])); 297 } else { 298 set_64bit_val(wqe, 56, 299 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) | 300 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1])); 301 302 set_64bit_val(wqe, 48, 303 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) | 304 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3])); 305 } 306 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE, 307 vsi->qos[info->user_pri].qs_handle); 308 if (info->vlan_valid) 309 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id); 310 set_64bit_val(wqe, 16, qw2); 311 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) { 312 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port); 313 if (!info->ipv4_valid) { 314 set_64bit_val(wqe, 40, 315 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) | 316 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1])); 317 set_64bit_val(wqe, 32, 318 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) | 319 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3])); 320 } else { 321 set_64bit_val(wqe, 32, 322 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0])); 323 } 324 } 325 326 set_64bit_val(wqe, 8, qw1); 327 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) | 328 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, 329 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) | 330 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) | 331 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) | 332 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) | 333 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type); 334 dma_wmb(); /* make sure WQE is written before valid bit is set */ 335 336 set_64bit_val(wqe, 24, temp); 337 338 print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16, 339 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 340 if (post_sq) 341 irdma_sc_cqp_post_sq(cqp); 342 343 return 0; 344 } 345 346 /** 347 * irdma_sc_qp_init - initialize qp 348 * @qp: sc qp 349 * @info: initialization qp info 350 */ 351 enum irdma_status_code irdma_sc_qp_init(struct irdma_sc_qp *qp, 352 struct irdma_qp_init_info *info) 353 { 354 enum irdma_status_code ret_code; 355 u32 pble_obj_cnt; 356 u16 wqe_size; 357 358 if (info->qp_uk_init_info.max_sq_frag_cnt > 359 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags || 360 info->qp_uk_init_info.max_rq_frag_cnt > 361 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags) 362 return IRDMA_ERR_INVALID_FRAG_COUNT; 363 364 qp->dev = info->pd->dev; 365 qp->vsi = info->vsi; 366 qp->ieq_qp = info->vsi->exception_lan_q; 367 qp->sq_pa = info->sq_pa; 368 qp->rq_pa = info->rq_pa; 369 qp->hw_host_ctx_pa = info->host_ctx_pa; 370 qp->q2_pa = info->q2_pa; 371 qp->shadow_area_pa = info->shadow_area_pa; 372 qp->q2_buf = info->q2; 373 qp->pd = info->pd; 374 qp->hw_host_ctx = info->host_ctx; 375 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 376 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info); 377 if (ret_code) 378 return ret_code; 379 380 qp->virtual_map = info->virtual_map; 381 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 382 383 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) || 384 (info->virtual_map && info->rq_pa >= pble_obj_cnt)) 385 return IRDMA_ERR_INVALID_PBLE_INDEX; 386 387 qp->llp_stream_handle = (void *)(-1); 388 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, 389 IRDMA_QUEUE_TYPE_SQ_RQ); 390 ibdev_dbg(to_ibdev(qp->dev), 391 "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n", 392 qp->hw_sq_size, qp->qp_uk.sq_ring.size); 393 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4) 394 wqe_size = IRDMA_WQE_SIZE_128; 395 else 396 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, 397 &wqe_size); 398 if (ret_code) 399 return ret_code; 400 401 qp->hw_rq_size = irdma_get_encoded_wqe_size(qp->qp_uk.rq_size * 402 (wqe_size / IRDMA_QP_WQE_MIN_SIZE), IRDMA_QUEUE_TYPE_SQ_RQ); 403 ibdev_dbg(to_ibdev(qp->dev), 404 "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", 405 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); 406 qp->sq_tph_val = info->sq_tph_val; 407 qp->rq_tph_val = info->rq_tph_val; 408 qp->sq_tph_en = info->sq_tph_en; 409 qp->rq_tph_en = info->rq_tph_en; 410 qp->rcv_tph_en = info->rcv_tph_en; 411 qp->xmit_tph_en = info->xmit_tph_en; 412 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq; 413 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; 414 415 return 0; 416 } 417 418 /** 419 * irdma_sc_qp_create - create qp 420 * @qp: sc qp 421 * @info: qp create info 422 * @scratch: u64 saved to be used during cqp completion 423 * @post_sq: flag for cqp db to ring 424 */ 425 enum irdma_status_code irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info, 426 u64 scratch, bool post_sq) 427 { 428 struct irdma_sc_cqp *cqp; 429 __le64 *wqe; 430 u64 hdr; 431 432 cqp = qp->dev->cqp; 433 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id || 434 qp->qp_uk.qp_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt - 1)) 435 return IRDMA_ERR_INVALID_QP_ID; 436 437 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 438 if (!wqe) 439 return IRDMA_ERR_RING_FULL; 440 441 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 442 set_64bit_val(wqe, 40, qp->shadow_area_pa); 443 444 hdr = qp->qp_uk.qp_id | 445 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 446 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, (info->ord_valid ? 1 : 0)) | 447 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 448 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 449 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 450 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 451 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 452 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 453 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 454 info->arp_cache_idx_valid) | 455 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 456 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 457 dma_wmb(); /* make sure WQE is written before valid bit is set */ 458 459 set_64bit_val(wqe, 24, hdr); 460 461 print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 462 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 463 if (post_sq) 464 irdma_sc_cqp_post_sq(cqp); 465 466 return 0; 467 } 468 469 /** 470 * irdma_sc_qp_modify - modify qp cqp wqe 471 * @qp: sc qp 472 * @info: modify qp info 473 * @scratch: u64 saved to be used during cqp completion 474 * @post_sq: flag for cqp db to ring 475 */ 476 enum irdma_status_code irdma_sc_qp_modify(struct irdma_sc_qp *qp, 477 struct irdma_modify_qp_info *info, 478 u64 scratch, bool post_sq) 479 { 480 __le64 *wqe; 481 struct irdma_sc_cqp *cqp; 482 u64 hdr; 483 u8 term_actions = 0; 484 u8 term_len = 0; 485 486 cqp = qp->dev->cqp; 487 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 488 if (!wqe) 489 return IRDMA_ERR_RING_FULL; 490 491 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) { 492 if (info->dont_send_fin) 493 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY; 494 if (info->dont_send_term) 495 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY; 496 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN || 497 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY) 498 term_len = info->termlen; 499 } 500 501 set_64bit_val(wqe, 8, 502 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) | 503 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len)); 504 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 505 set_64bit_val(wqe, 40, qp->shadow_area_pa); 506 507 hdr = qp->qp_uk.qp_id | 508 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) | 509 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | 510 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 511 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID, 512 info->cached_var_valid) | 513 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 514 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 515 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 516 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 517 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 518 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) | 519 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, 520 info->remove_hash_idx) | 521 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) | 522 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) | 523 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 524 info->arp_cache_idx_valid) | 525 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 526 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 527 dma_wmb(); /* make sure WQE is written before valid bit is set */ 528 529 set_64bit_val(wqe, 24, hdr); 530 531 print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 532 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 533 if (post_sq) 534 irdma_sc_cqp_post_sq(cqp); 535 536 return 0; 537 } 538 539 /** 540 * irdma_sc_qp_destroy - cqp destroy qp 541 * @qp: sc qp 542 * @scratch: u64 saved to be used during cqp completion 543 * @remove_hash_idx: flag if to remove hash idx 544 * @ignore_mw_bnd: memory window bind flag 545 * @post_sq: flag for cqp db to ring 546 */ 547 enum irdma_status_code irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, 548 bool remove_hash_idx, bool ignore_mw_bnd, 549 bool post_sq) 550 { 551 __le64 *wqe; 552 struct irdma_sc_cqp *cqp; 553 u64 hdr; 554 555 cqp = qp->dev->cqp; 556 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 557 if (!wqe) 558 return IRDMA_ERR_RING_FULL; 559 560 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 561 set_64bit_val(wqe, 40, qp->shadow_area_pa); 562 563 hdr = qp->qp_uk.qp_id | 564 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) | 565 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 566 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) | 567 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) | 568 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 569 dma_wmb(); /* make sure WQE is written before valid bit is set */ 570 571 set_64bit_val(wqe, 24, hdr); 572 573 print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 574 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 575 if (post_sq) 576 irdma_sc_cqp_post_sq(cqp); 577 578 return 0; 579 } 580 581 /** 582 * irdma_sc_get_encoded_ird_size - 583 * @ird_size: IRD size 584 * The ird from the connection is rounded to a supported HW setting and then encoded 585 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 586 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input 587 */ 588 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) 589 { 590 switch (ird_size ? 591 roundup_pow_of_two(2 * ird_size) : 4) { 592 case 256: 593 return IRDMA_IRD_HW_SIZE_256; 594 case 128: 595 return IRDMA_IRD_HW_SIZE_128; 596 case 64: 597 case 32: 598 return IRDMA_IRD_HW_SIZE_64; 599 case 16: 600 case 8: 601 return IRDMA_IRD_HW_SIZE_16; 602 case 4: 603 default: 604 break; 605 } 606 607 return IRDMA_IRD_HW_SIZE_4; 608 } 609 610 /** 611 * irdma_sc_qp_setctx_roce - set qp's context 612 * @qp: sc qp 613 * @qp_ctx: context ptr 614 * @info: ctx info 615 */ 616 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 617 struct irdma_qp_host_ctx_info *info) 618 { 619 struct irdma_roce_offload_info *roce_info; 620 struct irdma_udp_offload_info *udp; 621 u8 push_mode_en; 622 u32 push_idx; 623 624 roce_info = info->roce_info; 625 udp = info->udp_info; 626 qp->user_pri = info->user_pri; 627 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 628 push_mode_en = 0; 629 push_idx = 0; 630 } else { 631 push_mode_en = 1; 632 push_idx = qp->push_idx; 633 } 634 set_64bit_val(qp_ctx, 0, 635 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 636 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 637 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 638 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 639 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 640 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 641 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 642 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) | 643 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 644 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) | 645 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 646 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 647 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 648 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag)); 649 set_64bit_val(qp_ctx, 8, qp->sq_pa); 650 set_64bit_val(qp_ctx, 16, qp->rq_pa); 651 if ((roce_info->dcqcn_en || roce_info->dctcp_en) && 652 !(udp->tos & 0x03)) 653 udp->tos |= ECN_CODE_PT_VAL; 654 set_64bit_val(qp_ctx, 24, 655 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 656 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 657 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 658 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 659 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port)); 660 set_64bit_val(qp_ctx, 32, 661 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 662 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 663 set_64bit_val(qp_ctx, 40, 664 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 665 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 666 set_64bit_val(qp_ctx, 48, 667 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 668 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 669 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 670 set_64bit_val(qp_ctx, 56, 671 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 672 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) | 673 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 674 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label)); 675 set_64bit_val(qp_ctx, 64, 676 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 677 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp)); 678 set_64bit_val(qp_ctx, 80, 679 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 680 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 681 set_64bit_val(qp_ctx, 88, 682 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 683 set_64bit_val(qp_ctx, 96, 684 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 685 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 686 set_64bit_val(qp_ctx, 112, 687 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 688 set_64bit_val(qp_ctx, 128, 689 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | 690 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 691 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 692 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 693 set_64bit_val(qp_ctx, 136, 694 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 695 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 696 set_64bit_val(qp_ctx, 144, 697 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 698 set_64bit_val(qp_ctx, 152, ether_addr_to_u64(roce_info->mac_addr) << 16); 699 set_64bit_val(qp_ctx, 160, 700 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) | 701 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) | 702 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 703 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 704 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 705 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 706 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 707 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 708 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 709 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) | 710 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) | 711 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 712 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 713 set_64bit_val(qp_ctx, 168, 714 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 715 set_64bit_val(qp_ctx, 176, 716 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 717 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 718 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 719 set_64bit_val(qp_ctx, 184, 720 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 721 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 722 set_64bit_val(qp_ctx, 192, 723 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 724 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 725 set_64bit_val(qp_ctx, 200, 726 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 727 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 728 set_64bit_val(qp_ctx, 208, 729 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 730 731 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, 732 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 733 } 734 735 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry 736 * @cqp: struct for cqp hw 737 * @scratch: u64 saved to be used during cqp completion 738 * @post_sq: flag for cqp db to ring 739 */ 740 static enum irdma_status_code 741 irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 742 bool post_sq) 743 { 744 __le64 *wqe; 745 u64 hdr; 746 747 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 748 if (!wqe) 749 return IRDMA_ERR_RING_FULL; 750 751 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 752 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) | 753 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 754 755 dma_wmb(); /* make sure WQE is written before valid bit is set */ 756 757 set_64bit_val(wqe, 24, hdr); 758 759 print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE", 760 DUMP_PREFIX_OFFSET, 16, 8, wqe, 761 IRDMA_CQP_WQE_SIZE * 8, false); 762 763 if (post_sq) 764 irdma_sc_cqp_post_sq(cqp); 765 return 0; 766 } 767 768 /** 769 * irdma_sc_add_local_mac_entry - add mac enry 770 * @cqp: struct for cqp hw 771 * @info:mac addr info 772 * @scratch: u64 saved to be used during cqp completion 773 * @post_sq: flag for cqp db to ring 774 */ 775 static enum irdma_status_code 776 irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp, 777 struct irdma_local_mac_entry_info *info, 778 u64 scratch, bool post_sq) 779 { 780 __le64 *wqe; 781 u64 header; 782 783 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 784 if (!wqe) 785 return IRDMA_ERR_RING_FULL; 786 787 set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr)); 788 789 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) | 790 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 791 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 792 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 793 794 dma_wmb(); /* make sure WQE is written before valid bit is set */ 795 796 set_64bit_val(wqe, 24, header); 797 798 print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16, 799 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 800 801 if (post_sq) 802 irdma_sc_cqp_post_sq(cqp); 803 return 0; 804 } 805 806 /** 807 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac 808 * @cqp: struct for cqp hw 809 * @scratch: u64 saved to be used during cqp completion 810 * @entry_idx: index of mac entry 811 * @ignore_ref_count: to force mac adde delete 812 * @post_sq: flag for cqp db to ring 813 */ 814 static enum irdma_status_code 815 irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 816 u16 entry_idx, u8 ignore_ref_count, bool post_sq) 817 { 818 __le64 *wqe; 819 u64 header; 820 821 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 822 if (!wqe) 823 return IRDMA_ERR_RING_FULL; 824 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) | 825 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 826 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 827 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) | 828 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 829 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count); 830 831 dma_wmb(); /* make sure WQE is written before valid bit is set */ 832 833 set_64bit_val(wqe, 24, header); 834 835 print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE", 836 DUMP_PREFIX_OFFSET, 16, 8, wqe, 837 IRDMA_CQP_WQE_SIZE * 8, false); 838 839 if (post_sq) 840 irdma_sc_cqp_post_sq(cqp); 841 return 0; 842 } 843 844 /** 845 * irdma_sc_qp_setctx - set qp's context 846 * @qp: sc qp 847 * @qp_ctx: context ptr 848 * @info: ctx info 849 */ 850 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, 851 struct irdma_qp_host_ctx_info *info) 852 { 853 struct irdma_iwarp_offload_info *iw; 854 struct irdma_tcp_offload_info *tcp; 855 struct irdma_sc_dev *dev; 856 u8 push_mode_en; 857 u32 push_idx; 858 u64 qw0, qw3, qw7 = 0, qw16 = 0; 859 u64 mac = 0; 860 861 iw = info->iwarp_info; 862 tcp = info->tcp_info; 863 dev = qp->dev; 864 if (iw->rcv_mark_en) { 865 qp->pfpdu.marker_len = 4; 866 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt; 867 } 868 qp->user_pri = info->user_pri; 869 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 870 push_mode_en = 0; 871 push_idx = 0; 872 } else { 873 push_mode_en = 1; 874 push_idx = qp->push_idx; 875 } 876 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 877 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 878 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 879 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 880 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 881 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 882 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en); 883 884 set_64bit_val(qp_ctx, 8, qp->sq_pa); 885 set_64bit_val(qp_ctx, 16, qp->rq_pa); 886 887 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 888 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size); 889 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 890 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, 891 qp->src_mac_addr_idx); 892 set_64bit_val(qp_ctx, 136, 893 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 894 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 895 set_64bit_val(qp_ctx, 168, 896 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 897 set_64bit_val(qp_ctx, 176, 898 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 899 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 900 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) | 901 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp)); 902 if (info->iwarp_info_valid) { 903 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) | 904 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) | 905 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) | 906 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) | 907 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) | 908 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) | 909 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, 910 iw->err_rq_idx_valid); 911 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id); 912 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) | 913 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); 914 set_64bit_val(qp_ctx, 144, 915 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) | 916 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 917 918 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 919 mac = ether_addr_to_u64(iw->mac_addr); 920 921 set_64bit_val(qp_ctx, 152, 922 mac << 16 | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent)); 923 set_64bit_val(qp_ctx, 160, 924 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) | 925 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) | 926 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) | 927 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) | 928 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) | 929 FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) | 930 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) | 931 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) | 932 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 933 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) | 934 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) | 935 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) | 936 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) | 937 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) | 938 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) | 939 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en)); 940 } 941 if (info->tcp_info_valid) { 942 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) | 943 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) | 944 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, 945 tcp->insert_vlan_tag) | 946 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) | 947 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) | 948 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) | 949 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh); 950 951 if ((iw->ecn_en || iw->dctcp_en) && !(tcp->tos & 0x03)) 952 tcp->tos |= ECN_CODE_PT_VAL; 953 954 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) | 955 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) | 956 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) | 957 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) | 958 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port); 959 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 960 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx); 961 962 qp->src_mac_addr_idx = tcp->src_mac_addr_idx; 963 } 964 set_64bit_val(qp_ctx, 32, 965 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) | 966 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3])); 967 set_64bit_val(qp_ctx, 40, 968 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) | 969 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1])); 970 set_64bit_val(qp_ctx, 48, 971 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) | 972 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) | 973 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) | 974 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx)); 975 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) | 976 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) | 977 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT, 978 tcp->ignore_tcp_opt) | 979 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT, 980 tcp->ignore_tcp_uns_opt) | 981 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) | 982 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) | 983 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale); 984 set_64bit_val(qp_ctx, 72, 985 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) | 986 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age)); 987 set_64bit_val(qp_ctx, 80, 988 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) | 989 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd)); 990 set_64bit_val(qp_ctx, 88, 991 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) | 992 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd)); 993 set_64bit_val(qp_ctx, 96, 994 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) | 995 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una)); 996 set_64bit_val(qp_ctx, 104, 997 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) | 998 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var)); 999 set_64bit_val(qp_ctx, 112, 1000 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) | 1001 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd)); 1002 set_64bit_val(qp_ctx, 120, 1003 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) | 1004 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2)); 1005 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) | 1006 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh); 1007 set_64bit_val(qp_ctx, 184, 1008 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) | 1009 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2])); 1010 set_64bit_val(qp_ctx, 192, 1011 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) | 1012 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0])); 1013 set_64bit_val(qp_ctx, 200, 1014 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) | 1015 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low)); 1016 set_64bit_val(qp_ctx, 208, 1017 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 1018 } 1019 1020 set_64bit_val(qp_ctx, 0, qw0); 1021 set_64bit_val(qp_ctx, 24, qw3); 1022 set_64bit_val(qp_ctx, 56, qw7); 1023 set_64bit_val(qp_ctx, 128, qw16); 1024 1025 print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8, 1026 qp_ctx, IRDMA_QP_CTX_SIZE, false); 1027 } 1028 1029 /** 1030 * irdma_sc_alloc_stag - mr stag alloc 1031 * @dev: sc device struct 1032 * @info: stag info 1033 * @scratch: u64 saved to be used during cqp completion 1034 * @post_sq: flag for cqp db to ring 1035 */ 1036 static enum irdma_status_code 1037 irdma_sc_alloc_stag(struct irdma_sc_dev *dev, 1038 struct irdma_allocate_stag_info *info, u64 scratch, 1039 bool post_sq) 1040 { 1041 __le64 *wqe; 1042 struct irdma_sc_cqp *cqp; 1043 u64 hdr; 1044 enum irdma_page_size page_size; 1045 1046 if (info->page_size == 0x40000000) 1047 page_size = IRDMA_PAGE_SIZE_1G; 1048 else if (info->page_size == 0x200000) 1049 page_size = IRDMA_PAGE_SIZE_2M; 1050 else 1051 page_size = IRDMA_PAGE_SIZE_4K; 1052 1053 cqp = dev->cqp; 1054 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1055 if (!wqe) 1056 return IRDMA_ERR_RING_FULL; 1057 1058 set_64bit_val(wqe, 8, 1059 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) | 1060 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len)); 1061 set_64bit_val(wqe, 16, 1062 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1063 set_64bit_val(wqe, 40, 1064 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index)); 1065 1066 if (info->chunk_size) 1067 set_64bit_val(wqe, 48, 1068 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx)); 1069 1070 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1071 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1072 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1073 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1074 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1075 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) | 1076 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1077 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1078 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1079 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1080 1081 set_64bit_val(wqe, 24, hdr); 1082 1083 print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1084 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1085 if (post_sq) 1086 irdma_sc_cqp_post_sq(cqp); 1087 1088 return 0; 1089 } 1090 1091 /** 1092 * irdma_sc_mr_reg_non_shared - non-shared mr registration 1093 * @dev: sc device struct 1094 * @info: mr info 1095 * @scratch: u64 saved to be used during cqp completion 1096 * @post_sq: flag for cqp db to ring 1097 */ 1098 static enum irdma_status_code 1099 irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev, 1100 struct irdma_reg_ns_stag_info *info, u64 scratch, 1101 bool post_sq) 1102 { 1103 __le64 *wqe; 1104 u64 fbo; 1105 struct irdma_sc_cqp *cqp; 1106 u64 hdr; 1107 u32 pble_obj_cnt; 1108 bool remote_access; 1109 u8 addr_type; 1110 enum irdma_page_size page_size; 1111 1112 if (info->page_size == 0x40000000) 1113 page_size = IRDMA_PAGE_SIZE_1G; 1114 else if (info->page_size == 0x200000) 1115 page_size = IRDMA_PAGE_SIZE_2M; 1116 else if (info->page_size == 0x1000) 1117 page_size = IRDMA_PAGE_SIZE_4K; 1118 else 1119 return IRDMA_ERR_PARAM; 1120 1121 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY | 1122 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY)) 1123 remote_access = true; 1124 else 1125 remote_access = false; 1126 1127 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 1128 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt) 1129 return IRDMA_ERR_INVALID_PBLE_INDEX; 1130 1131 cqp = dev->cqp; 1132 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1133 if (!wqe) 1134 return IRDMA_ERR_RING_FULL; 1135 fbo = info->va & (info->page_size - 1); 1136 1137 set_64bit_val(wqe, 0, 1138 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ? 1139 info->va : fbo)); 1140 set_64bit_val(wqe, 8, 1141 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) | 1142 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1143 set_64bit_val(wqe, 16, 1144 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) | 1145 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1146 if (!info->chunk_size) { 1147 set_64bit_val(wqe, 32, info->reg_addr_pa); 1148 set_64bit_val(wqe, 48, 0); 1149 } else { 1150 set_64bit_val(wqe, 32, 0); 1151 set_64bit_val(wqe, 48, 1152 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index)); 1153 } 1154 set_64bit_val(wqe, 40, info->hmc_fcn_index); 1155 set_64bit_val(wqe, 56, 0); 1156 1157 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0; 1158 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) | 1159 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1160 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1161 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1162 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1163 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) | 1164 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) | 1165 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1166 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1167 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1168 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1169 1170 set_64bit_val(wqe, 24, hdr); 1171 1172 print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8, 1173 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1174 if (post_sq) 1175 irdma_sc_cqp_post_sq(cqp); 1176 1177 return 0; 1178 } 1179 1180 /** 1181 * irdma_sc_dealloc_stag - deallocate stag 1182 * @dev: sc device struct 1183 * @info: dealloc stag info 1184 * @scratch: u64 saved to be used during cqp completion 1185 * @post_sq: flag for cqp db to ring 1186 */ 1187 static enum irdma_status_code 1188 irdma_sc_dealloc_stag(struct irdma_sc_dev *dev, 1189 struct irdma_dealloc_stag_info *info, u64 scratch, 1190 bool post_sq) 1191 { 1192 u64 hdr; 1193 __le64 *wqe; 1194 struct irdma_sc_cqp *cqp; 1195 1196 cqp = dev->cqp; 1197 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1198 if (!wqe) 1199 return IRDMA_ERR_RING_FULL; 1200 1201 set_64bit_val(wqe, 8, 1202 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1203 set_64bit_val(wqe, 16, 1204 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1205 1206 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) | 1207 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) | 1208 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1209 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1210 1211 set_64bit_val(wqe, 24, hdr); 1212 1213 print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 1214 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1215 if (post_sq) 1216 irdma_sc_cqp_post_sq(cqp); 1217 1218 return 0; 1219 } 1220 1221 /** 1222 * irdma_sc_mw_alloc - mw allocate 1223 * @dev: sc device struct 1224 * @info: memory window allocation information 1225 * @scratch: u64 saved to be used during cqp completion 1226 * @post_sq: flag for cqp db to ring 1227 */ 1228 static enum irdma_status_code 1229 irdma_sc_mw_alloc(struct irdma_sc_dev *dev, struct irdma_mw_alloc_info *info, 1230 u64 scratch, bool post_sq) 1231 { 1232 u64 hdr; 1233 struct irdma_sc_cqp *cqp; 1234 __le64 *wqe; 1235 1236 cqp = dev->cqp; 1237 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1238 if (!wqe) 1239 return IRDMA_ERR_RING_FULL; 1240 1241 set_64bit_val(wqe, 8, 1242 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1243 set_64bit_val(wqe, 16, 1244 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index)); 1245 1246 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1247 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) | 1248 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY, 1249 info->mw1_bind_dont_vldt_key) | 1250 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1251 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1252 1253 set_64bit_val(wqe, 24, hdr); 1254 1255 print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8, 1256 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1257 if (post_sq) 1258 irdma_sc_cqp_post_sq(cqp); 1259 1260 return 0; 1261 } 1262 1263 /** 1264 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp 1265 * @qp: sc qp struct 1266 * @info: fast mr info 1267 * @post_sq: flag for cqp db to ring 1268 */ 1269 enum irdma_status_code 1270 irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, 1271 struct irdma_fast_reg_stag_info *info, bool post_sq) 1272 { 1273 u64 temp, hdr; 1274 __le64 *wqe; 1275 u32 wqe_idx; 1276 enum irdma_page_size page_size; 1277 struct irdma_post_sq_info sq_info = {}; 1278 1279 if (info->page_size == 0x40000000) 1280 page_size = IRDMA_PAGE_SIZE_1G; 1281 else if (info->page_size == 0x200000) 1282 page_size = IRDMA_PAGE_SIZE_2M; 1283 else 1284 page_size = IRDMA_PAGE_SIZE_4K; 1285 1286 sq_info.wr_id = info->wr_id; 1287 sq_info.signaled = info->signaled; 1288 sq_info.push_wqe = info->push_wqe; 1289 1290 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, 1291 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info); 1292 if (!wqe) 1293 return IRDMA_ERR_QP_TOOMANY_WRS_POSTED; 1294 1295 irdma_clr_wqes(&qp->qp_uk, wqe_idx); 1296 1297 ibdev_dbg(to_ibdev(qp->dev), 1298 "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", 1299 info->wr_id, wqe_idx, 1300 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); 1301 1302 temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1303 (uintptr_t)info->va : info->fbo; 1304 set_64bit_val(wqe, 0, temp); 1305 1306 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI, 1307 info->first_pm_pbl_index >> 16); 1308 set_64bit_val(wqe, 8, 1309 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) | 1310 FIELD_PREP(IRDMAQPSQ_PBLADDR >> IRDMA_HW_PAGE_SHIFT, info->reg_addr_pa)); 1311 set_64bit_val(wqe, 16, 1312 info->total_len | 1313 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index)); 1314 1315 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) | 1316 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) | 1317 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) | 1318 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) | 1319 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) | 1320 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) | 1321 FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) | 1322 FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) | 1323 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 1324 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 1325 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 1326 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1327 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1328 1329 set_64bit_val(wqe, 24, hdr); 1330 1331 print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1332 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1333 if (sq_info.push_wqe) { 1334 irdma_qp_push_wqe(&qp->qp_uk, wqe, IRDMA_QP_WQE_MIN_QUANTA, 1335 wqe_idx, post_sq); 1336 } else { 1337 if (post_sq) 1338 irdma_uk_qp_post_wr(&qp->qp_uk); 1339 } 1340 1341 return 0; 1342 } 1343 1344 /** 1345 * irdma_sc_gen_rts_ae - request AE generated after RTS 1346 * @qp: sc qp struct 1347 */ 1348 static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp) 1349 { 1350 __le64 *wqe; 1351 u64 hdr; 1352 struct irdma_qp_uk *qp_uk; 1353 1354 qp_uk = &qp->qp_uk; 1355 1356 wqe = qp_uk->sq_base[1].elem; 1357 1358 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 1359 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | 1360 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1361 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1362 1363 set_64bit_val(wqe, 24, hdr); 1364 print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET, 1365 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1366 1367 wqe = qp_uk->sq_base[2].elem; 1368 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) | 1369 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1370 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1371 1372 set_64bit_val(wqe, 24, hdr); 1373 print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8, 1374 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1375 } 1376 1377 /** 1378 * irdma_sc_send_lsmm - send last streaming mode message 1379 * @qp: sc qp struct 1380 * @lsmm_buf: buffer with lsmm message 1381 * @size: size of lsmm buffer 1382 * @stag: stag of lsmm buffer 1383 */ 1384 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, 1385 irdma_stag stag) 1386 { 1387 __le64 *wqe; 1388 u64 hdr; 1389 struct irdma_qp_uk *qp_uk; 1390 1391 qp_uk = &qp->qp_uk; 1392 wqe = qp_uk->sq_base->elem; 1393 1394 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); 1395 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1396 set_64bit_val(wqe, 8, 1397 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) | 1398 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag)); 1399 } else { 1400 set_64bit_val(wqe, 8, 1401 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) | 1402 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) | 1403 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1404 } 1405 set_64bit_val(wqe, 16, 0); 1406 1407 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) | 1408 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) | 1409 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) | 1410 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1411 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1412 1413 set_64bit_val(wqe, 24, hdr); 1414 1415 print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8, 1416 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1417 1418 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1419 irdma_sc_gen_rts_ae(qp); 1420 } 1421 1422 /** 1423 * irdma_sc_send_rtt - send last read0 or write0 1424 * @qp: sc qp struct 1425 * @read: Do read0 or write0 1426 */ 1427 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read) 1428 { 1429 __le64 *wqe; 1430 u64 hdr; 1431 struct irdma_qp_uk *qp_uk; 1432 1433 qp_uk = &qp->qp_uk; 1434 wqe = qp_uk->sq_base->elem; 1435 1436 set_64bit_val(wqe, 0, 0); 1437 set_64bit_val(wqe, 16, 0); 1438 if (read) { 1439 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1440 set_64bit_val(wqe, 8, 1441 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd)); 1442 } else { 1443 set_64bit_val(wqe, 8, 1444 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1445 } 1446 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) | 1447 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) | 1448 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1449 1450 } else { 1451 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1452 set_64bit_val(wqe, 8, 0); 1453 } else { 1454 set_64bit_val(wqe, 8, 1455 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1456 } 1457 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) | 1458 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1459 } 1460 1461 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1462 1463 set_64bit_val(wqe, 24, hdr); 1464 1465 print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 1466 IRDMA_QP_WQE_MIN_SIZE, false); 1467 1468 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1469 irdma_sc_gen_rts_ae(qp); 1470 } 1471 1472 /** 1473 * irdma_iwarp_opcode - determine if incoming is rdma layer 1474 * @info: aeq info for the packet 1475 * @pkt: packet for error 1476 */ 1477 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt) 1478 { 1479 __be16 *mpa; 1480 u32 opcode = 0xffffffff; 1481 1482 if (info->q2_data_written) { 1483 mpa = (__be16 *)pkt; 1484 opcode = ntohs(mpa[1]) & 0xf; 1485 } 1486 1487 return opcode; 1488 } 1489 1490 /** 1491 * irdma_locate_mpa - return pointer to mpa in the pkt 1492 * @pkt: packet with data 1493 */ 1494 static u8 *irdma_locate_mpa(u8 *pkt) 1495 { 1496 /* skip over ethernet header */ 1497 pkt += IRDMA_MAC_HLEN; 1498 1499 /* Skip over IP and TCP headers */ 1500 pkt += 4 * (pkt[0] & 0x0f); 1501 pkt += 4 * ((pkt[12] >> 4) & 0x0f); 1502 1503 return pkt; 1504 } 1505 1506 /** 1507 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields 1508 * @qp: sc qp ptr for pkt 1509 * @hdr: term hdr 1510 * @opcode: flush opcode for termhdr 1511 * @layer_etype: error layer + error type 1512 * @err: error cod ein the header 1513 */ 1514 static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp, 1515 struct irdma_terminate_hdr *hdr, 1516 enum irdma_flush_opcode opcode, 1517 u8 layer_etype, u8 err) 1518 { 1519 qp->flush_code = opcode; 1520 hdr->layer_etype = layer_etype; 1521 hdr->error_code = err; 1522 } 1523 1524 /** 1525 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr 1526 * @pkt: ptr to mpa in offending pkt 1527 * @hdr: term hdr 1528 * @copy_len: offending pkt length to be copied to term hdr 1529 * @is_tagged: DDP tagged or untagged 1530 */ 1531 static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr, 1532 int *copy_len, u8 *is_tagged) 1533 { 1534 u16 ddp_seg_len; 1535 1536 ddp_seg_len = ntohs(*(__be16 *)pkt); 1537 if (ddp_seg_len) { 1538 *copy_len = 2; 1539 hdr->hdrct = DDP_LEN_FLAG; 1540 if (pkt[2] & 0x80) { 1541 *is_tagged = 1; 1542 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { 1543 *copy_len += TERM_DDP_LEN_TAGGED; 1544 hdr->hdrct |= DDP_HDR_FLAG; 1545 } 1546 } else { 1547 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { 1548 *copy_len += TERM_DDP_LEN_UNTAGGED; 1549 hdr->hdrct |= DDP_HDR_FLAG; 1550 } 1551 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) && 1552 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) { 1553 *copy_len += TERM_RDMA_LEN; 1554 hdr->hdrct |= RDMA_HDR_FLAG; 1555 } 1556 } 1557 } 1558 } 1559 1560 /** 1561 * irdma_bld_terminate_hdr - build terminate message header 1562 * @qp: qp associated with received terminate AE 1563 * @info: the struct contiaing AE information 1564 */ 1565 static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp, 1566 struct irdma_aeqe_info *info) 1567 { 1568 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1569 int copy_len = 0; 1570 u8 is_tagged = 0; 1571 u32 opcode; 1572 struct irdma_terminate_hdr *termhdr; 1573 1574 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf; 1575 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); 1576 1577 if (info->q2_data_written) { 1578 pkt = irdma_locate_mpa(pkt); 1579 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged); 1580 } 1581 1582 opcode = irdma_iwarp_opcode(info, pkt); 1583 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 1584 qp->sq_flush_code = info->sq; 1585 qp->rq_flush_code = info->rq; 1586 1587 switch (info->ae_id) { 1588 case IRDMA_AE_AMP_UNALLOCATED_STAG: 1589 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1590 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE) 1591 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1592 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1593 DDP_TAGGED_INV_STAG); 1594 else 1595 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1596 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1597 RDMAP_INV_STAG); 1598 break; 1599 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 1600 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1601 if (info->q2_data_written) 1602 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1603 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1604 DDP_TAGGED_BOUNDS); 1605 else 1606 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1607 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1608 RDMAP_INV_BOUNDS); 1609 break; 1610 case IRDMA_AE_AMP_BAD_PD: 1611 switch (opcode) { 1612 case IRDMA_OP_TYPE_RDMA_WRITE: 1613 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1614 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1615 DDP_TAGGED_UNASSOC_STAG); 1616 break; 1617 case IRDMA_OP_TYPE_SEND_INV: 1618 case IRDMA_OP_TYPE_SEND_SOL_INV: 1619 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1620 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1621 RDMAP_CANT_INV_STAG); 1622 break; 1623 default: 1624 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1625 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1626 RDMAP_UNASSOC_STAG); 1627 } 1628 break; 1629 case IRDMA_AE_AMP_INVALID_STAG: 1630 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1631 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1632 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1633 RDMAP_INV_STAG); 1634 break; 1635 case IRDMA_AE_AMP_BAD_QP: 1636 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR, 1637 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1638 DDP_UNTAGGED_INV_QN); 1639 break; 1640 case IRDMA_AE_AMP_BAD_STAG_KEY: 1641 case IRDMA_AE_AMP_BAD_STAG_INDEX: 1642 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1643 switch (opcode) { 1644 case IRDMA_OP_TYPE_SEND_INV: 1645 case IRDMA_OP_TYPE_SEND_SOL_INV: 1646 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 1647 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1648 RDMAP_CANT_INV_STAG); 1649 break; 1650 default: 1651 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1652 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1653 RDMAP_INV_STAG); 1654 } 1655 break; 1656 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 1657 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 1658 case IRDMA_AE_PRIV_OPERATION_DENIED: 1659 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1660 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1661 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1662 RDMAP_ACCESS); 1663 break; 1664 case IRDMA_AE_AMP_TO_WRAP: 1665 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1666 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1667 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1668 RDMAP_TO_WRAP); 1669 break; 1670 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 1671 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1672 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); 1673 break; 1674 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 1675 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 1676 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 1677 DDP_CATASTROPHIC_LOCAL); 1678 break; 1679 case IRDMA_AE_LCE_QP_CATASTROPHIC: 1680 case IRDMA_AE_DDP_NO_L_BIT: 1681 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 1682 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 1683 DDP_CATASTROPHIC_LOCAL); 1684 break; 1685 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN: 1686 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1687 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1688 DDP_UNTAGGED_INV_MSN_RANGE); 1689 break; 1690 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 1691 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1692 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 1693 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1694 DDP_UNTAGGED_INV_TOO_LONG); 1695 break; 1696 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 1697 if (is_tagged) 1698 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1699 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1700 DDP_TAGGED_INV_DDP_VER); 1701 else 1702 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1703 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1704 DDP_UNTAGGED_INV_DDP_VER); 1705 break; 1706 case IRDMA_AE_DDP_UBE_INVALID_MO: 1707 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1708 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1709 DDP_UNTAGGED_INV_MO); 1710 break; 1711 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 1712 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 1713 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1714 DDP_UNTAGGED_INV_MSN_NO_BUF); 1715 break; 1716 case IRDMA_AE_DDP_UBE_INVALID_QN: 1717 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1718 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1719 DDP_UNTAGGED_INV_QN); 1720 break; 1721 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 1722 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1723 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1724 RDMAP_INV_RDMAP_VER); 1725 break; 1726 default: 1727 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 1728 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1729 RDMAP_UNSPECIFIED); 1730 break; 1731 } 1732 1733 if (copy_len) 1734 memcpy(termhdr + 1, pkt, copy_len); 1735 1736 return sizeof(struct irdma_terminate_hdr) + copy_len; 1737 } 1738 1739 /** 1740 * irdma_terminate_send_fin() - Send fin for terminate message 1741 * @qp: qp associated with received terminate AE 1742 */ 1743 void irdma_terminate_send_fin(struct irdma_sc_qp *qp) 1744 { 1745 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 1746 IRDMAQP_TERM_SEND_FIN_ONLY, 0); 1747 } 1748 1749 /** 1750 * irdma_terminate_connection() - Bad AE and send terminate to remote QP 1751 * @qp: qp associated with received terminate AE 1752 * @info: the struct contiaing AE information 1753 */ 1754 void irdma_terminate_connection(struct irdma_sc_qp *qp, 1755 struct irdma_aeqe_info *info) 1756 { 1757 u8 termlen = 0; 1758 1759 if (qp->term_flags & IRDMA_TERM_SENT) 1760 return; 1761 1762 termlen = irdma_bld_terminate_hdr(qp, info); 1763 irdma_terminate_start_timer(qp); 1764 qp->term_flags |= IRDMA_TERM_SENT; 1765 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 1766 IRDMAQP_TERM_SEND_TERM_ONLY, termlen); 1767 } 1768 1769 /** 1770 * irdma_terminate_received - handle terminate received AE 1771 * @qp: qp associated with received terminate AE 1772 * @info: the struct contiaing AE information 1773 */ 1774 void irdma_terminate_received(struct irdma_sc_qp *qp, 1775 struct irdma_aeqe_info *info) 1776 { 1777 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1778 __be32 *mpa; 1779 u8 ddp_ctl; 1780 u8 rdma_ctl; 1781 u16 aeq_id = 0; 1782 struct irdma_terminate_hdr *termhdr; 1783 1784 mpa = (__be32 *)irdma_locate_mpa(pkt); 1785 if (info->q2_data_written) { 1786 /* did not validate the frame - do it now */ 1787 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; 1788 rdma_ctl = ntohl(mpa[0]) & 0xff; 1789 if ((ddp_ctl & 0xc0) != 0x40) 1790 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC; 1791 else if ((ddp_ctl & 0x03) != 1) 1792 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION; 1793 else if (ntohl(mpa[2]) != 2) 1794 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN; 1795 else if (ntohl(mpa[3]) != 1) 1796 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN; 1797 else if (ntohl(mpa[4]) != 0) 1798 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO; 1799 else if ((rdma_ctl & 0xc0) != 0x40) 1800 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; 1801 1802 info->ae_id = aeq_id; 1803 if (info->ae_id) { 1804 /* Bad terminate recvd - send back a terminate */ 1805 irdma_terminate_connection(qp, info); 1806 return; 1807 } 1808 } 1809 1810 qp->term_flags |= IRDMA_TERM_RCVD; 1811 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 1812 termhdr = (struct irdma_terminate_hdr *)&mpa[5]; 1813 if (termhdr->layer_etype == RDMAP_REMOTE_PROT || 1814 termhdr->layer_etype == RDMAP_REMOTE_OP) { 1815 irdma_terminate_done(qp, 0); 1816 } else { 1817 irdma_terminate_start_timer(qp); 1818 irdma_terminate_send_fin(qp); 1819 } 1820 } 1821 1822 static enum irdma_status_code irdma_null_ws_add(struct irdma_sc_vsi *vsi, 1823 u8 user_pri) 1824 { 1825 return 0; 1826 } 1827 1828 static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) 1829 { 1830 /* do nothing */ 1831 } 1832 1833 static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi) 1834 { 1835 /* do nothing */ 1836 } 1837 1838 /** 1839 * irdma_sc_vsi_init - Init the vsi structure 1840 * @vsi: pointer to vsi structure to initialize 1841 * @info: the info used to initialize the vsi struct 1842 */ 1843 void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, 1844 struct irdma_vsi_init_info *info) 1845 { 1846 struct irdma_l2params *l2p; 1847 int i; 1848 1849 vsi->dev = info->dev; 1850 vsi->back_vsi = info->back_vsi; 1851 vsi->register_qset = info->register_qset; 1852 vsi->unregister_qset = info->unregister_qset; 1853 vsi->mtu = info->params->mtu; 1854 vsi->exception_lan_q = info->exception_lan_q; 1855 vsi->vsi_idx = info->pf_data_vsi_num; 1856 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1857 vsi->fcn_id = info->dev->hmc_fn_id; 1858 1859 l2p = info->params; 1860 vsi->qos_rel_bw = l2p->vsi_rel_bw; 1861 vsi->qos_prio_type = l2p->vsi_prio_type; 1862 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 1863 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1864 vsi->qos[i].qs_handle = l2p->qs_handle_list[i]; 1865 vsi->qos[i].traffic_class = info->params->up2tc[i]; 1866 vsi->qos[i].rel_bw = 1867 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw; 1868 vsi->qos[i].prio_type = 1869 l2p->tc_info[vsi->qos[i].traffic_class].prio_type; 1870 vsi->qos[i].valid = false; 1871 mutex_init(&vsi->qos[i].qos_mutex); 1872 INIT_LIST_HEAD(&vsi->qos[i].qplist); 1873 } 1874 if (vsi->register_qset) { 1875 vsi->dev->ws_add = irdma_ws_add; 1876 vsi->dev->ws_remove = irdma_ws_remove; 1877 vsi->dev->ws_reset = irdma_ws_reset; 1878 } else { 1879 vsi->dev->ws_add = irdma_null_ws_add; 1880 vsi->dev->ws_remove = irdma_null_ws_remove; 1881 vsi->dev->ws_reset = irdma_null_ws_reset; 1882 } 1883 } 1884 1885 /** 1886 * irdma_get_fcn_id - Return the function id 1887 * @vsi: pointer to the vsi 1888 */ 1889 static u8 irdma_get_fcn_id(struct irdma_sc_vsi *vsi) 1890 { 1891 struct irdma_stats_inst_info stats_info = {}; 1892 struct irdma_sc_dev *dev = vsi->dev; 1893 u8 fcn_id = IRDMA_INVALID_FCN_ID; 1894 u8 start_idx, max_stats, i; 1895 1896 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 1897 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE, 1898 &stats_info)) 1899 return stats_info.stats_idx; 1900 } 1901 1902 start_idx = 1; 1903 max_stats = 16; 1904 for (i = start_idx; i < max_stats; i++) 1905 if (!dev->fcn_id_array[i]) { 1906 fcn_id = i; 1907 dev->fcn_id_array[i] = true; 1908 break; 1909 } 1910 1911 return fcn_id; 1912 } 1913 1914 /** 1915 * irdma_vsi_stats_init - Initialize the vsi statistics 1916 * @vsi: pointer to the vsi structure 1917 * @info: The info structure used for initialization 1918 */ 1919 enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, 1920 struct irdma_vsi_stats_info *info) 1921 { 1922 u8 fcn_id = info->fcn_id; 1923 struct irdma_dma_mem *stats_buff_mem; 1924 1925 vsi->pestat = info->pestat; 1926 vsi->pestat->hw = vsi->dev->hw; 1927 vsi->pestat->vsi = vsi; 1928 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem; 1929 stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1); 1930 stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device, 1931 stats_buff_mem->size, 1932 &stats_buff_mem->pa, 1933 GFP_KERNEL); 1934 if (!stats_buff_mem->va) 1935 return IRDMA_ERR_NO_MEMORY; 1936 1937 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va; 1938 vsi->pestat->gather_info.last_gather_stats_va = 1939 (void *)((uintptr_t)stats_buff_mem->va + 1940 IRDMA_GATHER_STATS_BUF_SIZE); 1941 1942 irdma_hw_stats_start_timer(vsi); 1943 if (info->alloc_fcn_id) 1944 fcn_id = irdma_get_fcn_id(vsi); 1945 if (fcn_id == IRDMA_INVALID_FCN_ID) 1946 goto stats_error; 1947 1948 vsi->stats_fcn_id_alloc = info->alloc_fcn_id; 1949 vsi->fcn_id = fcn_id; 1950 if (info->alloc_fcn_id) { 1951 vsi->pestat->gather_info.use_stats_inst = true; 1952 vsi->pestat->gather_info.stats_inst_index = fcn_id; 1953 } 1954 1955 return 0; 1956 1957 stats_error: 1958 dma_free_coherent(vsi->pestat->hw->device, stats_buff_mem->size, 1959 stats_buff_mem->va, stats_buff_mem->pa); 1960 stats_buff_mem->va = NULL; 1961 1962 return IRDMA_ERR_CQP_COMPL_ERROR; 1963 } 1964 1965 /** 1966 * irdma_vsi_stats_free - Free the vsi stats 1967 * @vsi: pointer to the vsi structure 1968 */ 1969 void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi) 1970 { 1971 struct irdma_stats_inst_info stats_info = {}; 1972 u8 fcn_id = vsi->fcn_id; 1973 struct irdma_sc_dev *dev = vsi->dev; 1974 1975 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 1976 if (vsi->stats_fcn_id_alloc) { 1977 stats_info.stats_idx = vsi->fcn_id; 1978 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE, 1979 &stats_info); 1980 } 1981 } else { 1982 if (vsi->stats_fcn_id_alloc && 1983 fcn_id < vsi->dev->hw_attrs.max_stat_inst) 1984 vsi->dev->fcn_id_array[fcn_id] = false; 1985 } 1986 1987 if (!vsi->pestat) 1988 return; 1989 irdma_hw_stats_stop_timer(vsi); 1990 dma_free_coherent(vsi->pestat->hw->device, 1991 vsi->pestat->gather_info.stats_buff_mem.size, 1992 vsi->pestat->gather_info.stats_buff_mem.va, 1993 vsi->pestat->gather_info.stats_buff_mem.pa); 1994 vsi->pestat->gather_info.stats_buff_mem.va = NULL; 1995 } 1996 1997 /** 1998 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size 1999 * @wqsize: size of the wq (sq, rq) to encoded_size 2000 * @queue_type: queue type selected for the calculation algorithm 2001 */ 2002 u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) 2003 { 2004 u8 encoded_size = 0; 2005 2006 /* cqp sq's hw coded value starts from 1 for size of 4 2007 * while it starts from 0 for qp' wq's. 2008 */ 2009 if (queue_type == IRDMA_QUEUE_TYPE_CQP) 2010 encoded_size = 1; 2011 wqsize >>= 2; 2012 while (wqsize >>= 1) 2013 encoded_size++; 2014 2015 return encoded_size; 2016 } 2017 2018 /** 2019 * irdma_sc_gather_stats - collect the statistics 2020 * @cqp: struct for cqp hw 2021 * @info: gather stats info structure 2022 * @scratch: u64 saved to be used during cqp completion 2023 */ 2024 static enum irdma_status_code 2025 irdma_sc_gather_stats(struct irdma_sc_cqp *cqp, 2026 struct irdma_stats_gather_info *info, u64 scratch) 2027 { 2028 __le64 *wqe; 2029 u64 temp; 2030 2031 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE) 2032 return IRDMA_ERR_BUF_TOO_SHORT; 2033 2034 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2035 if (!wqe) 2036 return IRDMA_ERR_RING_FULL; 2037 2038 set_64bit_val(wqe, 40, 2039 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index)); 2040 set_64bit_val(wqe, 32, info->stats_buff_mem.pa); 2041 2042 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2043 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) | 2044 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, 2045 info->stats_inst_index) | 2046 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2047 info->use_hmc_fcn_index) | 2048 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS); 2049 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2050 2051 set_64bit_val(wqe, 24, temp); 2052 2053 print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET, 2054 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2055 2056 irdma_sc_cqp_post_sq(cqp); 2057 ibdev_dbg(to_ibdev(cqp->dev), 2058 "STATS: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 2059 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 2060 2061 return 0; 2062 } 2063 2064 /** 2065 * irdma_sc_manage_stats_inst - allocate or free stats instance 2066 * @cqp: struct for cqp hw 2067 * @info: stats info structure 2068 * @alloc: alloc vs. delete flag 2069 * @scratch: u64 saved to be used during cqp completion 2070 */ 2071 static enum irdma_status_code 2072 irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp, 2073 struct irdma_stats_inst_info *info, bool alloc, 2074 u64 scratch) 2075 { 2076 __le64 *wqe; 2077 u64 temp; 2078 2079 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2080 if (!wqe) 2081 return IRDMA_ERR_RING_FULL; 2082 2083 set_64bit_val(wqe, 40, 2084 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id)); 2085 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2086 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) | 2087 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2088 info->use_hmc_fcn_index) | 2089 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) | 2090 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS); 2091 2092 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2093 2094 set_64bit_val(wqe, 24, temp); 2095 2096 print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16, 2097 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2098 2099 irdma_sc_cqp_post_sq(cqp); 2100 return 0; 2101 } 2102 2103 /** 2104 * irdma_sc_set_up_map - set the up map table 2105 * @cqp: struct for cqp hw 2106 * @info: User priority map info 2107 * @scratch: u64 saved to be used during cqp completion 2108 */ 2109 static enum irdma_status_code irdma_sc_set_up_map(struct irdma_sc_cqp *cqp, 2110 struct irdma_up_info *info, 2111 u64 scratch) 2112 { 2113 __le64 *wqe; 2114 u64 temp = 0; 2115 int i; 2116 2117 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2118 if (!wqe) 2119 return IRDMA_ERR_RING_FULL; 2120 2121 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 2122 temp |= (u64)info->map[i] << (i * 8); 2123 2124 set_64bit_val(wqe, 0, temp); 2125 set_64bit_val(wqe, 40, 2126 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) | 2127 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx)); 2128 2129 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) | 2130 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) | 2131 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE, 2132 info->use_cnp_up_override) | 2133 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP); 2134 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2135 2136 set_64bit_val(wqe, 24, temp); 2137 2138 print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 2139 IRDMA_CQP_WQE_SIZE * 8, false); 2140 irdma_sc_cqp_post_sq(cqp); 2141 2142 return 0; 2143 } 2144 2145 /** 2146 * irdma_sc_manage_ws_node - create/modify/destroy WS node 2147 * @cqp: struct for cqp hw 2148 * @info: node info structure 2149 * @node_op: 0 for add 1 for modify, 2 for delete 2150 * @scratch: u64 saved to be used during cqp completion 2151 */ 2152 static enum irdma_status_code 2153 irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp, 2154 struct irdma_ws_node_info *info, 2155 enum irdma_ws_node_op node_op, u64 scratch) 2156 { 2157 __le64 *wqe; 2158 u64 temp = 0; 2159 2160 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2161 if (!wqe) 2162 return IRDMA_ERR_RING_FULL; 2163 2164 set_64bit_val(wqe, 32, 2165 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) | 2166 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight)); 2167 2168 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) | 2169 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) | 2170 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) | 2171 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) | 2172 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) | 2173 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) | 2174 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) | 2175 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) | 2176 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id); 2177 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2178 2179 set_64bit_val(wqe, 24, temp); 2180 2181 print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, 2182 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2183 irdma_sc_cqp_post_sq(cqp); 2184 2185 return 0; 2186 } 2187 2188 /** 2189 * irdma_sc_qp_flush_wqes - flush qp's wqe 2190 * @qp: sc qp 2191 * @info: dlush information 2192 * @scratch: u64 saved to be used during cqp completion 2193 * @post_sq: flag for cqp db to ring 2194 */ 2195 enum irdma_status_code irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, 2196 struct irdma_qp_flush_info *info, 2197 u64 scratch, bool post_sq) 2198 { 2199 u64 temp = 0; 2200 __le64 *wqe; 2201 struct irdma_sc_cqp *cqp; 2202 u64 hdr; 2203 bool flush_sq = false, flush_rq = false; 2204 2205 if (info->rq && !qp->flush_rq) 2206 flush_rq = true; 2207 if (info->sq && !qp->flush_sq) 2208 flush_sq = true; 2209 qp->flush_sq |= flush_sq; 2210 qp->flush_rq |= flush_rq; 2211 2212 if (!flush_sq && !flush_rq) { 2213 ibdev_dbg(to_ibdev(qp->dev), 2214 "CQP: Additional flush request ignored for qp %x\n", 2215 qp->qp_uk.qp_id); 2216 return IRDMA_ERR_FLUSHED_Q; 2217 } 2218 2219 cqp = qp->pd->dev->cqp; 2220 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2221 if (!wqe) 2222 return IRDMA_ERR_RING_FULL; 2223 2224 if (info->userflushcode) { 2225 if (flush_rq) 2226 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR, 2227 info->rq_minor_code) | 2228 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, 2229 info->rq_major_code); 2230 if (flush_sq) 2231 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR, 2232 info->sq_minor_code) | 2233 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, 2234 info->sq_major_code); 2235 } 2236 set_64bit_val(wqe, 16, temp); 2237 2238 temp = (info->generate_ae) ? 2239 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2240 info->ae_src) : 0; 2241 set_64bit_val(wqe, 8, temp); 2242 2243 hdr = qp->qp_uk.qp_id | 2244 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) | 2245 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) | 2246 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) | 2247 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) | 2248 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) | 2249 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2250 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2251 2252 set_64bit_val(wqe, 24, hdr); 2253 2254 print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8, 2255 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2256 if (post_sq) 2257 irdma_sc_cqp_post_sq(cqp); 2258 2259 return 0; 2260 } 2261 2262 /** 2263 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP 2264 * @qp: sc qp 2265 * @info: gen ae information 2266 * @scratch: u64 saved to be used during cqp completion 2267 * @post_sq: flag for cqp db to ring 2268 */ 2269 static enum irdma_status_code irdma_sc_gen_ae(struct irdma_sc_qp *qp, 2270 struct irdma_gen_ae_info *info, 2271 u64 scratch, bool post_sq) 2272 { 2273 u64 temp; 2274 __le64 *wqe; 2275 struct irdma_sc_cqp *cqp; 2276 u64 hdr; 2277 2278 cqp = qp->pd->dev->cqp; 2279 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2280 if (!wqe) 2281 return IRDMA_ERR_RING_FULL; 2282 2283 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2284 info->ae_src); 2285 set_64bit_val(wqe, 8, temp); 2286 2287 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE, 2288 IRDMA_CQP_OP_GEN_AE) | 2289 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) | 2290 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2291 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2292 2293 set_64bit_val(wqe, 24, hdr); 2294 2295 print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2296 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2297 if (post_sq) 2298 irdma_sc_cqp_post_sq(cqp); 2299 2300 return 0; 2301 } 2302 2303 /*** irdma_sc_qp_upload_context - upload qp's context 2304 * @dev: sc device struct 2305 * @info: upload context info ptr for return 2306 * @scratch: u64 saved to be used during cqp completion 2307 * @post_sq: flag for cqp db to ring 2308 */ 2309 static enum irdma_status_code 2310 irdma_sc_qp_upload_context(struct irdma_sc_dev *dev, 2311 struct irdma_upload_context_info *info, u64 scratch, 2312 bool post_sq) 2313 { 2314 __le64 *wqe; 2315 struct irdma_sc_cqp *cqp; 2316 u64 hdr; 2317 2318 cqp = dev->cqp; 2319 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2320 if (!wqe) 2321 return IRDMA_ERR_RING_FULL; 2322 2323 set_64bit_val(wqe, 16, info->buf_pa); 2324 2325 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) | 2326 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) | 2327 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) | 2328 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) | 2329 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) | 2330 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2331 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2332 2333 set_64bit_val(wqe, 24, hdr); 2334 2335 print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16, 2336 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2337 if (post_sq) 2338 irdma_sc_cqp_post_sq(cqp); 2339 2340 return 0; 2341 } 2342 2343 /** 2344 * irdma_sc_manage_push_page - Handle push page 2345 * @cqp: struct for cqp hw 2346 * @info: push page info 2347 * @scratch: u64 saved to be used during cqp completion 2348 * @post_sq: flag for cqp db to ring 2349 */ 2350 static enum irdma_status_code 2351 irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp, 2352 struct irdma_cqp_manage_push_page_info *info, 2353 u64 scratch, bool post_sq) 2354 { 2355 __le64 *wqe; 2356 u64 hdr; 2357 2358 if (info->free_page && 2359 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages) 2360 return IRDMA_ERR_INVALID_PUSH_PAGE_INDEX; 2361 2362 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2363 if (!wqe) 2364 return IRDMA_ERR_RING_FULL; 2365 2366 set_64bit_val(wqe, 16, info->qs_handle); 2367 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) | 2368 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) | 2369 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) | 2370 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 2371 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page); 2372 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2373 2374 set_64bit_val(wqe, 24, hdr); 2375 2376 print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET, 2377 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2378 if (post_sq) 2379 irdma_sc_cqp_post_sq(cqp); 2380 2381 return 0; 2382 } 2383 2384 /** 2385 * irdma_sc_suspend_qp - suspend qp for param change 2386 * @cqp: struct for cqp hw 2387 * @qp: sc qp struct 2388 * @scratch: u64 saved to be used during cqp completion 2389 */ 2390 static enum irdma_status_code irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, 2391 struct irdma_sc_qp *qp, 2392 u64 scratch) 2393 { 2394 u64 hdr; 2395 __le64 *wqe; 2396 2397 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2398 if (!wqe) 2399 return IRDMA_ERR_RING_FULL; 2400 2401 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) | 2402 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) | 2403 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2404 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2405 2406 set_64bit_val(wqe, 24, hdr); 2407 2408 print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2409 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2410 irdma_sc_cqp_post_sq(cqp); 2411 2412 return 0; 2413 } 2414 2415 /** 2416 * irdma_sc_resume_qp - resume qp after suspend 2417 * @cqp: struct for cqp hw 2418 * @qp: sc qp struct 2419 * @scratch: u64 saved to be used during cqp completion 2420 */ 2421 static enum irdma_status_code irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, 2422 struct irdma_sc_qp *qp, 2423 u64 scratch) 2424 { 2425 u64 hdr; 2426 __le64 *wqe; 2427 2428 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2429 if (!wqe) 2430 return IRDMA_ERR_RING_FULL; 2431 2432 set_64bit_val(wqe, 16, 2433 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle)); 2434 2435 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) | 2436 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) | 2437 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2438 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2439 2440 set_64bit_val(wqe, 24, hdr); 2441 2442 print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2443 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2444 irdma_sc_cqp_post_sq(cqp); 2445 2446 return 0; 2447 } 2448 2449 /** 2450 * irdma_sc_cq_ack - acknowledge completion q 2451 * @cq: cq struct 2452 */ 2453 static inline void irdma_sc_cq_ack(struct irdma_sc_cq *cq) 2454 { 2455 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db); 2456 } 2457 2458 /** 2459 * irdma_sc_cq_init - initialize completion q 2460 * @cq: cq struct 2461 * @info: cq initialization info 2462 */ 2463 enum irdma_status_code irdma_sc_cq_init(struct irdma_sc_cq *cq, 2464 struct irdma_cq_init_info *info) 2465 { 2466 u32 pble_obj_cnt; 2467 2468 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2469 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 2470 return IRDMA_ERR_INVALID_PBLE_INDEX; 2471 2472 cq->cq_pa = info->cq_base_pa; 2473 cq->dev = info->dev; 2474 cq->ceq_id = info->ceq_id; 2475 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db; 2476 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db; 2477 irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info); 2478 2479 cq->virtual_map = info->virtual_map; 2480 cq->pbl_chunk_size = info->pbl_chunk_size; 2481 cq->ceqe_mask = info->ceqe_mask; 2482 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP; 2483 cq->shadow_area_pa = info->shadow_area_pa; 2484 cq->shadow_read_threshold = info->shadow_read_threshold; 2485 cq->ceq_id_valid = info->ceq_id_valid; 2486 cq->tph_en = info->tph_en; 2487 cq->tph_val = info->tph_val; 2488 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2489 cq->vsi = info->vsi; 2490 2491 return 0; 2492 } 2493 2494 /** 2495 * irdma_sc_cq_create - create completion q 2496 * @cq: cq struct 2497 * @scratch: u64 saved to be used during cqp completion 2498 * @check_overflow: flag for overflow check 2499 * @post_sq: flag for cqp db to ring 2500 */ 2501 static enum irdma_status_code irdma_sc_cq_create(struct irdma_sc_cq *cq, 2502 u64 scratch, 2503 bool check_overflow, 2504 bool post_sq) 2505 { 2506 __le64 *wqe; 2507 struct irdma_sc_cqp *cqp; 2508 u64 hdr; 2509 struct irdma_sc_ceq *ceq; 2510 enum irdma_status_code ret_code = 0; 2511 2512 cqp = cq->dev->cqp; 2513 if (cq->cq_uk.cq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt - 1)) 2514 return IRDMA_ERR_INVALID_CQ_ID; 2515 2516 if (cq->ceq_id > (cq->dev->hmc_fpm_misc.max_ceqs - 1)) 2517 return IRDMA_ERR_INVALID_CEQ_ID; 2518 2519 ceq = cq->dev->ceq[cq->ceq_id]; 2520 if (ceq && ceq->reg_cq) 2521 ret_code = irdma_sc_add_cq_ctx(ceq, cq); 2522 2523 if (ret_code) 2524 return ret_code; 2525 2526 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2527 if (!wqe) { 2528 if (ceq && ceq->reg_cq) 2529 irdma_sc_remove_cq_ctx(ceq, cq); 2530 return IRDMA_ERR_RING_FULL; 2531 } 2532 2533 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2534 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2535 set_64bit_val(wqe, 16, 2536 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 2537 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); 2538 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2539 set_64bit_val(wqe, 48, 2540 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0))); 2541 set_64bit_val(wqe, 56, 2542 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2543 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2544 2545 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) | 2546 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2547 IRDMA_CQPSQ_CQ_CEQID) | 2548 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 2549 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2550 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) | 2551 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2552 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2553 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2554 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2555 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2556 cq->cq_uk.avoid_mem_cflct) | 2557 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2558 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2559 2560 set_64bit_val(wqe, 24, hdr); 2561 2562 print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2563 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2564 if (post_sq) 2565 irdma_sc_cqp_post_sq(cqp); 2566 2567 return 0; 2568 } 2569 2570 /** 2571 * irdma_sc_cq_destroy - destroy completion q 2572 * @cq: cq struct 2573 * @scratch: u64 saved to be used during cqp completion 2574 * @post_sq: flag for cqp db to ring 2575 */ 2576 enum irdma_status_code irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, 2577 bool post_sq) 2578 { 2579 struct irdma_sc_cqp *cqp; 2580 __le64 *wqe; 2581 u64 hdr; 2582 struct irdma_sc_ceq *ceq; 2583 2584 cqp = cq->dev->cqp; 2585 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2586 if (!wqe) 2587 return IRDMA_ERR_RING_FULL; 2588 2589 ceq = cq->dev->ceq[cq->ceq_id]; 2590 if (ceq && ceq->reg_cq) 2591 irdma_sc_remove_cq_ctx(ceq, cq); 2592 2593 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2594 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2595 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2596 set_64bit_val(wqe, 48, 2597 (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); 2598 2599 hdr = cq->cq_uk.cq_id | 2600 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2601 IRDMA_CQPSQ_CQ_CEQID) | 2602 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 2603 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2604 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2605 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2606 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2607 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2608 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) | 2609 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2610 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2611 2612 set_64bit_val(wqe, 24, hdr); 2613 2614 print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 2615 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2616 if (post_sq) 2617 irdma_sc_cqp_post_sq(cqp); 2618 2619 return 0; 2620 } 2621 2622 /** 2623 * irdma_sc_cq_resize - set resized cq buffer info 2624 * @cq: resized cq 2625 * @info: resized cq buffer info 2626 */ 2627 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info) 2628 { 2629 cq->virtual_map = info->virtual_map; 2630 cq->cq_pa = info->cq_pa; 2631 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2632 cq->pbl_chunk_size = info->pbl_chunk_size; 2633 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size); 2634 } 2635 2636 /** 2637 * irdma_sc_cq_modify - modify a Completion Queue 2638 * @cq: cq struct 2639 * @info: modification info struct 2640 * @scratch: u64 saved to be used during cqp completion 2641 * @post_sq: flag to post to sq 2642 */ 2643 static enum irdma_status_code 2644 irdma_sc_cq_modify(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info, 2645 u64 scratch, bool post_sq) 2646 { 2647 struct irdma_sc_cqp *cqp; 2648 __le64 *wqe; 2649 u64 hdr; 2650 u32 pble_obj_cnt; 2651 2652 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2653 if (info->cq_resize && info->virtual_map && 2654 info->first_pm_pbl_idx >= pble_obj_cnt) 2655 return IRDMA_ERR_INVALID_PBLE_INDEX; 2656 2657 cqp = cq->dev->cqp; 2658 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2659 if (!wqe) 2660 return IRDMA_ERR_RING_FULL; 2661 2662 set_64bit_val(wqe, 0, info->cq_size); 2663 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2664 set_64bit_val(wqe, 16, 2665 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold)); 2666 set_64bit_val(wqe, 32, info->cq_pa); 2667 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2668 set_64bit_val(wqe, 48, info->first_pm_pbl_idx); 2669 set_64bit_val(wqe, 56, 2670 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2671 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2672 2673 hdr = cq->cq_uk.cq_id | 2674 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) | 2675 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) | 2676 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) | 2677 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) | 2678 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) | 2679 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2680 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2681 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2682 cq->cq_uk.avoid_mem_cflct) | 2683 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2684 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2685 2686 set_64bit_val(wqe, 24, hdr); 2687 2688 print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 2689 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2690 if (post_sq) 2691 irdma_sc_cqp_post_sq(cqp); 2692 2693 return 0; 2694 } 2695 2696 /** 2697 * irdma_check_cqp_progress - check cqp processing progress 2698 * @timeout: timeout info struct 2699 * @dev: sc device struct 2700 */ 2701 void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, struct irdma_sc_dev *dev) 2702 { 2703 if (timeout->compl_cqp_cmds != dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]) { 2704 timeout->compl_cqp_cmds = dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]; 2705 timeout->count = 0; 2706 } else { 2707 if (dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS] != 2708 timeout->compl_cqp_cmds) 2709 timeout->count++; 2710 } 2711 } 2712 2713 /** 2714 * irdma_get_cqp_reg_info - get head and tail for cqp using registers 2715 * @cqp: struct for cqp hw 2716 * @val: cqp tail register value 2717 * @tail: wqtail register value 2718 * @error: cqp processing err 2719 */ 2720 static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val, 2721 u32 *tail, u32 *error) 2722 { 2723 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]); 2724 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val); 2725 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val); 2726 } 2727 2728 /** 2729 * irdma_cqp_poll_registers - poll cqp registers 2730 * @cqp: struct for cqp hw 2731 * @tail: wqtail register value 2732 * @count: how many times to try for completion 2733 */ 2734 static enum irdma_status_code irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, 2735 u32 tail, u32 count) 2736 { 2737 u32 i = 0; 2738 u32 newtail, error, val; 2739 2740 while (i++ < count) { 2741 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error); 2742 if (error) { 2743 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 2744 ibdev_dbg(to_ibdev(cqp->dev), 2745 "CQP: CQPERRCODES error_code[x%08X]\n", 2746 error); 2747 return IRDMA_ERR_CQP_COMPL_ERROR; 2748 } 2749 if (newtail != tail) { 2750 /* SUCCESS */ 2751 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 2752 cqp->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]++; 2753 return 0; 2754 } 2755 udelay(cqp->dev->hw_attrs.max_sleep_count); 2756 } 2757 2758 return IRDMA_ERR_TIMEOUT; 2759 } 2760 2761 /** 2762 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base 2763 * @dev: sc device struct 2764 * @buf: pointer to commit buffer 2765 * @buf_idx: buffer index 2766 * @obj_info: object info pointer 2767 * @rsrc_idx: indexs of memory resource 2768 */ 2769 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, 2770 u32 buf_idx, struct irdma_hmc_obj_info *obj_info, 2771 u32 rsrc_idx) 2772 { 2773 u64 temp; 2774 2775 get_64bit_val(buf, buf_idx, &temp); 2776 2777 switch (rsrc_idx) { 2778 case IRDMA_HMC_IW_QP: 2779 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp); 2780 break; 2781 case IRDMA_HMC_IW_CQ: 2782 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT); 2783 break; 2784 case IRDMA_HMC_IW_APBVT_ENTRY: 2785 obj_info[rsrc_idx].cnt = 1; 2786 break; 2787 default: 2788 obj_info[rsrc_idx].cnt = (u32)temp; 2789 break; 2790 } 2791 2792 obj_info[rsrc_idx].base = (temp >> IRDMA_COMMIT_FPM_BASE_S) * 512; 2793 2794 return temp; 2795 } 2796 2797 /** 2798 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer 2799 * @dev: pointer to dev struct 2800 * @buf: ptr to fpm commit buffer 2801 * @info: ptr to irdma_hmc_obj_info struct 2802 * @sd: number of SDs for HMC objects 2803 * 2804 * parses fpm commit info and copy base value 2805 * of hmc objects in hmc_info 2806 */ 2807 static void 2808 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, 2809 struct irdma_hmc_obj_info *info, u32 *sd) 2810 { 2811 u64 size; 2812 u32 i; 2813 u64 max_base = 0; 2814 u32 last_hmc_obj = 0; 2815 2816 irdma_sc_decode_fpm_commit(dev, buf, 0, info, 2817 IRDMA_HMC_IW_QP); 2818 irdma_sc_decode_fpm_commit(dev, buf, 8, info, 2819 IRDMA_HMC_IW_CQ); 2820 /* skiping RSRVD */ 2821 irdma_sc_decode_fpm_commit(dev, buf, 24, info, 2822 IRDMA_HMC_IW_HTE); 2823 irdma_sc_decode_fpm_commit(dev, buf, 32, info, 2824 IRDMA_HMC_IW_ARP); 2825 irdma_sc_decode_fpm_commit(dev, buf, 40, info, 2826 IRDMA_HMC_IW_APBVT_ENTRY); 2827 irdma_sc_decode_fpm_commit(dev, buf, 48, info, 2828 IRDMA_HMC_IW_MR); 2829 irdma_sc_decode_fpm_commit(dev, buf, 56, info, 2830 IRDMA_HMC_IW_XF); 2831 irdma_sc_decode_fpm_commit(dev, buf, 64, info, 2832 IRDMA_HMC_IW_XFFL); 2833 irdma_sc_decode_fpm_commit(dev, buf, 72, info, 2834 IRDMA_HMC_IW_Q1); 2835 irdma_sc_decode_fpm_commit(dev, buf, 80, info, 2836 IRDMA_HMC_IW_Q1FL); 2837 irdma_sc_decode_fpm_commit(dev, buf, 88, info, 2838 IRDMA_HMC_IW_TIMER); 2839 irdma_sc_decode_fpm_commit(dev, buf, 112, info, 2840 IRDMA_HMC_IW_PBLE); 2841 /* skipping RSVD. */ 2842 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 2843 irdma_sc_decode_fpm_commit(dev, buf, 96, info, 2844 IRDMA_HMC_IW_FSIMC); 2845 irdma_sc_decode_fpm_commit(dev, buf, 104, info, 2846 IRDMA_HMC_IW_FSIAV); 2847 irdma_sc_decode_fpm_commit(dev, buf, 128, info, 2848 IRDMA_HMC_IW_RRF); 2849 irdma_sc_decode_fpm_commit(dev, buf, 136, info, 2850 IRDMA_HMC_IW_RRFFL); 2851 irdma_sc_decode_fpm_commit(dev, buf, 144, info, 2852 IRDMA_HMC_IW_HDR); 2853 irdma_sc_decode_fpm_commit(dev, buf, 152, info, 2854 IRDMA_HMC_IW_MD); 2855 irdma_sc_decode_fpm_commit(dev, buf, 160, info, 2856 IRDMA_HMC_IW_OOISC); 2857 irdma_sc_decode_fpm_commit(dev, buf, 168, info, 2858 IRDMA_HMC_IW_OOISCFFL); 2859 } 2860 2861 /* searching for the last object in HMC to find the size of the HMC area. */ 2862 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 2863 if (info[i].base > max_base) { 2864 max_base = info[i].base; 2865 last_hmc_obj = i; 2866 } 2867 } 2868 2869 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size + 2870 info[last_hmc_obj].base; 2871 2872 if (size & 0x1FFFFF) 2873 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ 2874 else 2875 *sd = (u32)(size >> 21); 2876 2877 } 2878 2879 /** 2880 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size 2881 * @buf: ptr to fpm query buffer 2882 * @buf_idx: index into buf 2883 * @obj_info: ptr to irdma_hmc_obj_info struct 2884 * @rsrc_idx: resource index into info 2885 * 2886 * Decode a 64 bit value from fpm query buffer into max count and size 2887 */ 2888 static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx, 2889 struct irdma_hmc_obj_info *obj_info, 2890 u32 rsrc_idx) 2891 { 2892 u64 temp; 2893 u32 size; 2894 2895 get_64bit_val(buf, buf_idx, &temp); 2896 obj_info[rsrc_idx].max_cnt = (u32)temp; 2897 size = (u32)(temp >> 32); 2898 obj_info[rsrc_idx].size = BIT_ULL(size); 2899 2900 return temp; 2901 } 2902 2903 /** 2904 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer 2905 * @dev: ptr to shared code device 2906 * @buf: ptr to fpm query buffer 2907 * @hmc_info: ptr to irdma_hmc_obj_info struct 2908 * @hmc_fpm_misc: ptr to fpm data 2909 * 2910 * parses fpm query buffer and copy max_cnt and 2911 * size value of hmc objects in hmc_info 2912 */ 2913 static enum irdma_status_code 2914 irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf, 2915 struct irdma_hmc_info *hmc_info, 2916 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 2917 { 2918 struct irdma_hmc_obj_info *obj_info; 2919 u64 temp; 2920 u32 size; 2921 u16 max_pe_sds; 2922 2923 obj_info = hmc_info->hmc_obj; 2924 2925 get_64bit_val(buf, 0, &temp); 2926 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp); 2927 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp); 2928 2929 hmc_fpm_misc->max_sds = max_pe_sds; 2930 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; 2931 get_64bit_val(buf, 8, &temp); 2932 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp); 2933 size = (u32)(temp >> 32); 2934 obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size); 2935 2936 get_64bit_val(buf, 16, &temp); 2937 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp); 2938 size = (u32)(temp >> 32); 2939 obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size); 2940 2941 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE); 2942 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP); 2943 2944 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192; 2945 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1; 2946 2947 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR); 2948 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF); 2949 2950 get_64bit_val(buf, 64, &temp); 2951 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp; 2952 obj_info[IRDMA_HMC_IW_XFFL].size = 4; 2953 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp); 2954 if (!hmc_fpm_misc->xf_block_size) 2955 return IRDMA_ERR_INVALID_SIZE; 2956 2957 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1); 2958 get_64bit_val(buf, 80, &temp); 2959 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp; 2960 obj_info[IRDMA_HMC_IW_Q1FL].size = 4; 2961 2962 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp); 2963 if (!hmc_fpm_misc->q1_block_size) 2964 return IRDMA_ERR_INVALID_SIZE; 2965 2966 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER); 2967 2968 get_64bit_val(buf, 112, &temp); 2969 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp; 2970 obj_info[IRDMA_HMC_IW_PBLE].size = 8; 2971 2972 get_64bit_val(buf, 120, &temp); 2973 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); 2974 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); 2975 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); 2976 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 2977 return 0; 2978 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); 2979 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV); 2980 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF); 2981 2982 get_64bit_val(buf, 136, &temp); 2983 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp; 2984 obj_info[IRDMA_HMC_IW_RRFFL].size = 4; 2985 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp); 2986 if (!hmc_fpm_misc->rrf_block_size && 2987 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt) 2988 return IRDMA_ERR_INVALID_SIZE; 2989 2990 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR); 2991 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD); 2992 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC); 2993 2994 get_64bit_val(buf, 168, &temp); 2995 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp; 2996 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4; 2997 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp); 2998 if (!hmc_fpm_misc->ooiscf_block_size && 2999 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt) 3000 return IRDMA_ERR_INVALID_SIZE; 3001 3002 return 0; 3003 } 3004 3005 /** 3006 * irdma_sc_find_reg_cq - find cq ctx index 3007 * @ceq: ceq sc structure 3008 * @cq: cq sc structure 3009 */ 3010 static u32 irdma_sc_find_reg_cq(struct irdma_sc_ceq *ceq, 3011 struct irdma_sc_cq *cq) 3012 { 3013 u32 i; 3014 3015 for (i = 0; i < ceq->reg_cq_size; i++) { 3016 if (cq == ceq->reg_cq[i]) 3017 return i; 3018 } 3019 3020 return IRDMA_INVALID_CQ_IDX; 3021 } 3022 3023 /** 3024 * irdma_sc_add_cq_ctx - add cq ctx tracking for ceq 3025 * @ceq: ceq sc structure 3026 * @cq: cq sc structure 3027 */ 3028 enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq, 3029 struct irdma_sc_cq *cq) 3030 { 3031 unsigned long flags; 3032 3033 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3034 3035 if (ceq->reg_cq_size == ceq->elem_cnt) { 3036 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3037 return IRDMA_ERR_REG_CQ_FULL; 3038 } 3039 3040 ceq->reg_cq[ceq->reg_cq_size++] = cq; 3041 3042 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3043 3044 return 0; 3045 } 3046 3047 /** 3048 * irdma_sc_remove_cq_ctx - remove cq ctx tracking for ceq 3049 * @ceq: ceq sc structure 3050 * @cq: cq sc structure 3051 */ 3052 void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq) 3053 { 3054 unsigned long flags; 3055 u32 cq_ctx_idx; 3056 3057 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3058 cq_ctx_idx = irdma_sc_find_reg_cq(ceq, cq); 3059 if (cq_ctx_idx == IRDMA_INVALID_CQ_IDX) 3060 goto exit; 3061 3062 ceq->reg_cq_size--; 3063 if (cq_ctx_idx != ceq->reg_cq_size) 3064 ceq->reg_cq[cq_ctx_idx] = ceq->reg_cq[ceq->reg_cq_size]; 3065 ceq->reg_cq[ceq->reg_cq_size] = NULL; 3066 3067 exit: 3068 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3069 } 3070 3071 /** 3072 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair 3073 * @cqp: IWARP control queue pair pointer 3074 * @info: IWARP control queue pair init info pointer 3075 * 3076 * Initializes the object and context buffers for a control Queue Pair. 3077 */ 3078 enum irdma_status_code irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, 3079 struct irdma_cqp_init_info *info) 3080 { 3081 u8 hw_sq_size; 3082 3083 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 || 3084 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 || 3085 ((info->sq_size & (info->sq_size - 1)))) 3086 return IRDMA_ERR_INVALID_SIZE; 3087 3088 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size, 3089 IRDMA_QUEUE_TYPE_CQP); 3090 cqp->size = sizeof(*cqp); 3091 cqp->sq_size = info->sq_size; 3092 cqp->hw_sq_size = hw_sq_size; 3093 cqp->sq_base = info->sq; 3094 cqp->host_ctx = info->host_ctx; 3095 cqp->sq_pa = info->sq_pa; 3096 cqp->host_ctx_pa = info->host_ctx_pa; 3097 cqp->dev = info->dev; 3098 cqp->struct_ver = info->struct_ver; 3099 cqp->hw_maj_ver = info->hw_maj_ver; 3100 cqp->hw_min_ver = info->hw_min_ver; 3101 cqp->scratch_array = info->scratch_array; 3102 cqp->polarity = 0; 3103 cqp->en_datacenter_tcp = info->en_datacenter_tcp; 3104 cqp->ena_vf_count = info->ena_vf_count; 3105 cqp->hmc_profile = info->hmc_profile; 3106 cqp->ceqs_per_vf = info->ceqs_per_vf; 3107 cqp->disable_packed = info->disable_packed; 3108 cqp->rocev2_rto_policy = info->rocev2_rto_policy; 3109 cqp->protocol_used = info->protocol_used; 3110 memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params)); 3111 info->dev->cqp = cqp; 3112 3113 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size); 3114 cqp->dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS] = 0; 3115 cqp->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS] = 0; 3116 /* for the cqp commands backlog. */ 3117 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); 3118 3119 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3120 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); 3121 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3122 3123 ibdev_dbg(to_ibdev(cqp->dev), 3124 "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%pK] cqp[%p] polarity[x%04x]\n", 3125 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base, 3126 (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity); 3127 return 0; 3128 } 3129 3130 /** 3131 * irdma_sc_cqp_create - create cqp during bringup 3132 * @cqp: struct for cqp hw 3133 * @maj_err: If error, major err number 3134 * @min_err: If error, minor err number 3135 */ 3136 enum irdma_status_code irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, 3137 u16 *min_err) 3138 { 3139 u64 temp; 3140 u8 hw_rev; 3141 u32 cnt = 0, p1, p2, val = 0, err_code; 3142 enum irdma_status_code ret_code; 3143 3144 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev; 3145 cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size, 3146 IRDMA_SD_BUF_ALIGNMENT); 3147 cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device, 3148 cqp->sdbuf.size, &cqp->sdbuf.pa, 3149 GFP_KERNEL); 3150 if (!cqp->sdbuf.va) 3151 return IRDMA_ERR_NO_MEMORY; 3152 3153 spin_lock_init(&cqp->dev->cqp_lock); 3154 3155 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) | 3156 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) | 3157 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) | 3158 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf); 3159 if (hw_rev >= IRDMA_GEN_2) { 3160 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY, 3161 cqp->rocev2_rto_policy) | 3162 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, 3163 cqp->protocol_used); 3164 } 3165 3166 set_64bit_val(cqp->host_ctx, 0, temp); 3167 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); 3168 3169 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) | 3170 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile); 3171 set_64bit_val(cqp->host_ctx, 16, temp); 3172 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); 3173 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) | 3174 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver); 3175 if (hw_rev >= IRDMA_GEN_2) { 3176 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) | 3177 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor); 3178 } 3179 set_64bit_val(cqp->host_ctx, 32, temp); 3180 set_64bit_val(cqp->host_ctx, 40, 0); 3181 temp = 0; 3182 if (hw_rev >= IRDMA_GEN_2) { 3183 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) | 3184 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) | 3185 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor); 3186 } 3187 set_64bit_val(cqp->host_ctx, 48, temp); 3188 temp = 0; 3189 if (hw_rev >= IRDMA_GEN_2) { 3190 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) | 3191 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) | 3192 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) | 3193 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod); 3194 } 3195 set_64bit_val(cqp->host_ctx, 56, temp); 3196 print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16, 3197 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false); 3198 p1 = cqp->host_ctx_pa >> 32; 3199 p2 = (u32)cqp->host_ctx_pa; 3200 3201 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3202 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3203 3204 do { 3205 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3206 ret_code = IRDMA_ERR_TIMEOUT; 3207 goto err; 3208 } 3209 udelay(cqp->dev->hw_attrs.max_sleep_count); 3210 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3211 } while (!val); 3212 3213 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) { 3214 ret_code = IRDMA_ERR_DEVICE_NOT_SUPPORTED; 3215 goto err; 3216 } 3217 3218 cqp->process_cqp_sds = irdma_update_sds_noccq; 3219 return 0; 3220 3221 err: 3222 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3223 cqp->sdbuf.va, cqp->sdbuf.pa); 3224 cqp->sdbuf.va = NULL; 3225 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3226 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code); 3227 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code); 3228 return ret_code; 3229 } 3230 3231 /** 3232 * irdma_sc_cqp_post_sq - post of cqp's sq 3233 * @cqp: struct for cqp hw 3234 */ 3235 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp) 3236 { 3237 writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db); 3238 3239 ibdev_dbg(to_ibdev(cqp->dev), 3240 "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 3241 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 3242 } 3243 3244 /** 3245 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq 3246 * and pass back index 3247 * @cqp: CQP HW structure 3248 * @scratch: private data for CQP WQE 3249 * @wqe_idx: WQE index of CQP SQ 3250 */ 3251 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, 3252 u32 *wqe_idx) 3253 { 3254 __le64 *wqe = NULL; 3255 enum irdma_status_code ret_code; 3256 3257 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) { 3258 ibdev_dbg(to_ibdev(cqp->dev), 3259 "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n", 3260 cqp->sq_ring.head, cqp->sq_ring.tail, 3261 cqp->sq_ring.size); 3262 return NULL; 3263 } 3264 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); 3265 if (ret_code) 3266 return NULL; 3267 3268 cqp->dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS]++; 3269 if (!*wqe_idx) 3270 cqp->polarity = !cqp->polarity; 3271 wqe = cqp->sq_base[*wqe_idx].elem; 3272 cqp->scratch_array[*wqe_idx] = scratch; 3273 IRDMA_CQP_INIT_WQE(wqe); 3274 3275 return wqe; 3276 } 3277 3278 /** 3279 * irdma_sc_cqp_destroy - destroy cqp during close 3280 * @cqp: struct for cqp hw 3281 */ 3282 enum irdma_status_code irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp) 3283 { 3284 u32 cnt = 0, val; 3285 enum irdma_status_code ret_code = 0; 3286 3287 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3288 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3289 do { 3290 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3291 ret_code = IRDMA_ERR_TIMEOUT; 3292 break; 3293 } 3294 udelay(cqp->dev->hw_attrs.max_sleep_count); 3295 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3296 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE)); 3297 3298 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3299 cqp->sdbuf.va, cqp->sdbuf.pa); 3300 cqp->sdbuf.va = NULL; 3301 return ret_code; 3302 } 3303 3304 /** 3305 * irdma_sc_ccq_arm - enable intr for control cq 3306 * @ccq: ccq sc struct 3307 */ 3308 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq) 3309 { 3310 u64 temp_val; 3311 u16 sw_cq_sel; 3312 u8 arm_next_se; 3313 u8 arm_seq_num; 3314 3315 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); 3316 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 3317 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 3318 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 3319 arm_seq_num++; 3320 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 3321 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 3322 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 3323 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1); 3324 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); 3325 3326 dma_wmb(); /* make sure shadow area is updated before arming */ 3327 3328 writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db); 3329 } 3330 3331 /** 3332 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry 3333 * @ccq: ccq sc struct 3334 * @info: completion q entry to return 3335 */ 3336 enum irdma_status_code irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, 3337 struct irdma_ccq_cqe_info *info) 3338 { 3339 u64 qp_ctx, temp, temp1; 3340 __le64 *cqe; 3341 struct irdma_sc_cqp *cqp; 3342 u32 wqe_idx; 3343 u32 error; 3344 u8 polarity; 3345 enum irdma_status_code ret_code = 0; 3346 3347 if (ccq->cq_uk.avoid_mem_cflct) 3348 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk); 3349 else 3350 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk); 3351 3352 get_64bit_val(cqe, 24, &temp); 3353 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp); 3354 if (polarity != ccq->cq_uk.polarity) 3355 return IRDMA_ERR_Q_EMPTY; 3356 3357 get_64bit_val(cqe, 8, &qp_ctx); 3358 cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx; 3359 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp); 3360 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR; 3361 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp); 3362 if (info->error) { 3363 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp); 3364 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3365 ibdev_dbg(to_ibdev(cqp->dev), 3366 "CQP: CQPERRCODES error_code[x%08X]\n", error); 3367 } 3368 3369 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp); 3370 info->scratch = cqp->scratch_array[wqe_idx]; 3371 3372 get_64bit_val(cqe, 16, &temp1); 3373 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1); 3374 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); 3375 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1); 3376 info->cqp = cqp; 3377 3378 /* move the head for cq */ 3379 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); 3380 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)) 3381 ccq->cq_uk.polarity ^= 1; 3382 3383 /* update cq tail in cq shadow memory also */ 3384 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); 3385 set_64bit_val(ccq->cq_uk.shadow_area, 0, 3386 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)); 3387 3388 dma_wmb(); /* make sure shadow area is updated before moving tail */ 3389 3390 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 3391 ccq->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]++; 3392 3393 return ret_code; 3394 } 3395 3396 /** 3397 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ 3398 * @cqp: struct for cqp hw 3399 * @op_code: cqp opcode for completion 3400 * @compl_info: completion q entry to return 3401 */ 3402 enum irdma_status_code irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code, 3403 struct irdma_ccq_cqe_info *compl_info) 3404 { 3405 struct irdma_ccq_cqe_info info = {}; 3406 struct irdma_sc_cq *ccq; 3407 enum irdma_status_code ret_code = 0; 3408 u32 cnt = 0; 3409 3410 ccq = cqp->dev->ccq; 3411 while (1) { 3412 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count) 3413 return IRDMA_ERR_TIMEOUT; 3414 3415 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) { 3416 udelay(cqp->dev->hw_attrs.max_sleep_count); 3417 continue; 3418 } 3419 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) { 3420 ret_code = IRDMA_ERR_CQP_COMPL_ERROR; 3421 break; 3422 } 3423 /* make sure op code matches*/ 3424 if (op_code == info.op_code) 3425 break; 3426 ibdev_dbg(to_ibdev(cqp->dev), 3427 "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n", 3428 op_code, info.op_code); 3429 } 3430 3431 if (compl_info) 3432 memcpy(compl_info, &info, sizeof(*compl_info)); 3433 3434 return ret_code; 3435 } 3436 3437 /** 3438 * irdma_sc_manage_hmc_pm_func_table - manage of function table 3439 * @cqp: struct for cqp hw 3440 * @scratch: u64 saved to be used during cqp completion 3441 * @info: info for the manage function table operation 3442 * @post_sq: flag for cqp db to ring 3443 */ 3444 static enum irdma_status_code 3445 irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp, 3446 struct irdma_hmc_fcn_info *info, 3447 u64 scratch, bool post_sq) 3448 { 3449 __le64 *wqe; 3450 u64 hdr; 3451 3452 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3453 if (!wqe) 3454 return IRDMA_ERR_RING_FULL; 3455 3456 set_64bit_val(wqe, 0, 0); 3457 set_64bit_val(wqe, 8, 0); 3458 set_64bit_val(wqe, 16, 0); 3459 set_64bit_val(wqe, 32, 0); 3460 set_64bit_val(wqe, 40, 0); 3461 set_64bit_val(wqe, 48, 0); 3462 set_64bit_val(wqe, 56, 0); 3463 3464 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) | 3465 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 3466 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) | 3467 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) | 3468 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3469 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3470 3471 set_64bit_val(wqe, 24, hdr); 3472 3473 print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE", 3474 DUMP_PREFIX_OFFSET, 16, 8, wqe, 3475 IRDMA_CQP_WQE_SIZE * 8, false); 3476 if (post_sq) 3477 irdma_sc_cqp_post_sq(cqp); 3478 3479 return 0; 3480 } 3481 3482 /** 3483 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion 3484 * for fpm commit 3485 * @cqp: struct for cqp hw 3486 */ 3487 static enum irdma_status_code 3488 irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp) 3489 { 3490 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL, 3491 NULL); 3492 } 3493 3494 /** 3495 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values 3496 * @cqp: struct for cqp hw 3497 * @scratch: u64 saved to be used during cqp completion 3498 * @hmc_fn_id: hmc function id 3499 * @commit_fpm_mem: Memory for fpm values 3500 * @post_sq: flag for cqp db to ring 3501 * @wait_type: poll ccq or cqp registers for cqp completion 3502 */ 3503 static enum irdma_status_code 3504 irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id, 3505 struct irdma_dma_mem *commit_fpm_mem, bool post_sq, 3506 u8 wait_type) 3507 { 3508 __le64 *wqe; 3509 u64 hdr; 3510 u32 tail, val, error; 3511 enum irdma_status_code ret_code = 0; 3512 3513 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3514 if (!wqe) 3515 return IRDMA_ERR_RING_FULL; 3516 3517 set_64bit_val(wqe, 16, hmc_fn_id); 3518 set_64bit_val(wqe, 32, commit_fpm_mem->pa); 3519 3520 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) | 3521 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) | 3522 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3523 3524 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3525 3526 set_64bit_val(wqe, 24, hdr); 3527 3528 print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET, 3529 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3530 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 3531 3532 if (post_sq) { 3533 irdma_sc_cqp_post_sq(cqp); 3534 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 3535 ret_code = irdma_cqp_poll_registers(cqp, tail, 3536 cqp->dev->hw_attrs.max_done_count); 3537 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 3538 ret_code = irdma_sc_commit_fpm_val_done(cqp); 3539 } 3540 3541 return ret_code; 3542 } 3543 3544 /** 3545 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for 3546 * query fpm 3547 * @cqp: struct for cqp hw 3548 */ 3549 static enum irdma_status_code 3550 irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp) 3551 { 3552 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL, 3553 NULL); 3554 } 3555 3556 /** 3557 * irdma_sc_query_fpm_val - cqp wqe query fpm values 3558 * @cqp: struct for cqp hw 3559 * @scratch: u64 saved to be used during cqp completion 3560 * @hmc_fn_id: hmc function id 3561 * @query_fpm_mem: memory for return fpm values 3562 * @post_sq: flag for cqp db to ring 3563 * @wait_type: poll ccq or cqp registers for cqp completion 3564 */ 3565 static enum irdma_status_code 3566 irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id, 3567 struct irdma_dma_mem *query_fpm_mem, bool post_sq, 3568 u8 wait_type) 3569 { 3570 __le64 *wqe; 3571 u64 hdr; 3572 u32 tail, val, error; 3573 enum irdma_status_code ret_code = 0; 3574 3575 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3576 if (!wqe) 3577 return IRDMA_ERR_RING_FULL; 3578 3579 set_64bit_val(wqe, 16, hmc_fn_id); 3580 set_64bit_val(wqe, 32, query_fpm_mem->pa); 3581 3582 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) | 3583 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3584 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3585 3586 set_64bit_val(wqe, 24, hdr); 3587 3588 print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8, 3589 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3590 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 3591 3592 if (post_sq) { 3593 irdma_sc_cqp_post_sq(cqp); 3594 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 3595 ret_code = irdma_cqp_poll_registers(cqp, tail, 3596 cqp->dev->hw_attrs.max_done_count); 3597 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 3598 ret_code = irdma_sc_query_fpm_val_done(cqp); 3599 } 3600 3601 return ret_code; 3602 } 3603 3604 /** 3605 * irdma_sc_ceq_init - initialize ceq 3606 * @ceq: ceq sc structure 3607 * @info: ceq initialization info 3608 */ 3609 enum irdma_status_code irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, 3610 struct irdma_ceq_init_info *info) 3611 { 3612 u32 pble_obj_cnt; 3613 3614 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size || 3615 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size) 3616 return IRDMA_ERR_INVALID_SIZE; 3617 3618 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) 3619 return IRDMA_ERR_INVALID_CEQ_ID; 3620 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3621 3622 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 3623 return IRDMA_ERR_INVALID_PBLE_INDEX; 3624 3625 ceq->size = sizeof(*ceq); 3626 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base; 3627 ceq->ceq_id = info->ceq_id; 3628 ceq->dev = info->dev; 3629 ceq->elem_cnt = info->elem_cnt; 3630 ceq->ceq_elem_pa = info->ceqe_pa; 3631 ceq->virtual_map = info->virtual_map; 3632 ceq->itr_no_expire = info->itr_no_expire; 3633 ceq->reg_cq = info->reg_cq; 3634 ceq->reg_cq_size = 0; 3635 spin_lock_init(&ceq->req_cq_lock); 3636 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); 3637 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); 3638 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); 3639 ceq->tph_en = info->tph_en; 3640 ceq->tph_val = info->tph_val; 3641 ceq->vsi = info->vsi; 3642 ceq->polarity = 1; 3643 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); 3644 ceq->dev->ceq[info->ceq_id] = ceq; 3645 3646 return 0; 3647 } 3648 3649 /** 3650 * irdma_sc_ceq_create - create ceq wqe 3651 * @ceq: ceq sc structure 3652 * @scratch: u64 saved to be used during cqp completion 3653 * @post_sq: flag for cqp db to ring 3654 */ 3655 3656 static enum irdma_status_code irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch, 3657 bool post_sq) 3658 { 3659 struct irdma_sc_cqp *cqp; 3660 __le64 *wqe; 3661 u64 hdr; 3662 3663 cqp = ceq->dev->cqp; 3664 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3665 if (!wqe) 3666 return IRDMA_ERR_RING_FULL; 3667 set_64bit_val(wqe, 16, ceq->elem_cnt); 3668 set_64bit_val(wqe, 32, 3669 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); 3670 set_64bit_val(wqe, 48, 3671 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); 3672 set_64bit_val(wqe, 56, 3673 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) | 3674 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx)); 3675 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) | 3676 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) | 3677 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 3678 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 3679 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) | 3680 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 3681 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3682 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3683 3684 set_64bit_val(wqe, 24, hdr); 3685 3686 print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 3687 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3688 if (post_sq) 3689 irdma_sc_cqp_post_sq(cqp); 3690 3691 return 0; 3692 } 3693 3694 /** 3695 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete 3696 * @ceq: ceq sc structure 3697 */ 3698 static enum irdma_status_code 3699 irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq) 3700 { 3701 struct irdma_sc_cqp *cqp; 3702 3703 cqp = ceq->dev->cqp; 3704 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ, 3705 NULL); 3706 } 3707 3708 /** 3709 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete 3710 * @ceq: ceq sc structure 3711 */ 3712 enum irdma_status_code irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq) 3713 { 3714 struct irdma_sc_cqp *cqp; 3715 3716 if (ceq->reg_cq) 3717 irdma_sc_remove_cq_ctx(ceq, ceq->dev->ccq); 3718 3719 cqp = ceq->dev->cqp; 3720 cqp->process_cqp_sds = irdma_update_sds_noccq; 3721 3722 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ, 3723 NULL); 3724 } 3725 3726 /** 3727 * irdma_sc_cceq_create - create cceq 3728 * @ceq: ceq sc structure 3729 * @scratch: u64 saved to be used during cqp completion 3730 */ 3731 enum irdma_status_code irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch) 3732 { 3733 enum irdma_status_code ret_code; 3734 struct irdma_sc_dev *dev = ceq->dev; 3735 3736 dev->ccq->vsi = ceq->vsi; 3737 if (ceq->reg_cq) { 3738 ret_code = irdma_sc_add_cq_ctx(ceq, ceq->dev->ccq); 3739 if (ret_code) 3740 return ret_code; 3741 } 3742 3743 ret_code = irdma_sc_ceq_create(ceq, scratch, true); 3744 if (!ret_code) 3745 return irdma_sc_cceq_create_done(ceq); 3746 3747 return ret_code; 3748 } 3749 3750 /** 3751 * irdma_sc_ceq_destroy - destroy ceq 3752 * @ceq: ceq sc structure 3753 * @scratch: u64 saved to be used during cqp completion 3754 * @post_sq: flag for cqp db to ring 3755 */ 3756 enum irdma_status_code irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, 3757 bool post_sq) 3758 { 3759 struct irdma_sc_cqp *cqp; 3760 __le64 *wqe; 3761 u64 hdr; 3762 3763 cqp = ceq->dev->cqp; 3764 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3765 if (!wqe) 3766 return IRDMA_ERR_RING_FULL; 3767 3768 set_64bit_val(wqe, 16, ceq->elem_cnt); 3769 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); 3770 hdr = ceq->ceq_id | 3771 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) | 3772 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 3773 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 3774 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 3775 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3776 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3777 3778 set_64bit_val(wqe, 24, hdr); 3779 3780 print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 3781 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3782 if (post_sq) 3783 irdma_sc_cqp_post_sq(cqp); 3784 3785 return 0; 3786 } 3787 3788 /** 3789 * irdma_sc_process_ceq - process ceq 3790 * @dev: sc device struct 3791 * @ceq: ceq sc structure 3792 * 3793 * It is expected caller serializes this function with cleanup_ceqes() 3794 * because these functions manipulate the same ceq 3795 */ 3796 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq) 3797 { 3798 u64 temp; 3799 __le64 *ceqe; 3800 struct irdma_sc_cq *cq = NULL; 3801 struct irdma_sc_cq *temp_cq; 3802 u8 polarity; 3803 u32 cq_idx; 3804 unsigned long flags; 3805 3806 do { 3807 cq_idx = 0; 3808 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq); 3809 get_64bit_val(ceqe, 0, &temp); 3810 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 3811 if (polarity != ceq->polarity) 3812 return NULL; 3813 3814 temp_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1); 3815 if (!temp_cq) { 3816 cq_idx = IRDMA_INVALID_CQ_IDX; 3817 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 3818 3819 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 3820 ceq->polarity ^= 1; 3821 continue; 3822 } 3823 3824 cq = temp_cq; 3825 if (ceq->reg_cq) { 3826 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3827 cq_idx = irdma_sc_find_reg_cq(ceq, cq); 3828 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3829 } 3830 3831 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 3832 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 3833 ceq->polarity ^= 1; 3834 } while (cq_idx == IRDMA_INVALID_CQ_IDX); 3835 3836 if (cq) 3837 irdma_sc_cq_ack(cq); 3838 return cq; 3839 } 3840 3841 /** 3842 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq 3843 * @cq: cq for which the ceqes need to be cleaned up 3844 * @ceq: ceq ptr 3845 * 3846 * The function is called after the cq is destroyed to cleanup 3847 * its pending ceqe entries. It is expected caller serializes this 3848 * function with process_ceq() in interrupt context. 3849 */ 3850 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq) 3851 { 3852 struct irdma_sc_cq *next_cq; 3853 u8 ceq_polarity = ceq->polarity; 3854 __le64 *ceqe; 3855 u8 polarity; 3856 u64 temp; 3857 int next; 3858 u32 i; 3859 3860 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0); 3861 3862 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) { 3863 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next); 3864 3865 get_64bit_val(ceqe, 0, &temp); 3866 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 3867 if (polarity != ceq_polarity) 3868 return; 3869 3870 next_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1); 3871 if (cq == next_cq) 3872 set_64bit_val(ceqe, 0, temp & IRDMA_CEQE_VALID); 3873 3874 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i); 3875 if (!next) 3876 ceq_polarity ^= 1; 3877 } 3878 } 3879 3880 /** 3881 * irdma_sc_aeq_init - initialize aeq 3882 * @aeq: aeq structure ptr 3883 * @info: aeq initialization info 3884 */ 3885 enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, 3886 struct irdma_aeq_init_info *info) 3887 { 3888 u32 pble_obj_cnt; 3889 3890 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size || 3891 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size) 3892 return IRDMA_ERR_INVALID_SIZE; 3893 3894 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3895 3896 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 3897 return IRDMA_ERR_INVALID_PBLE_INDEX; 3898 3899 aeq->size = sizeof(*aeq); 3900 aeq->polarity = 1; 3901 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base; 3902 aeq->dev = info->dev; 3903 aeq->elem_cnt = info->elem_cnt; 3904 aeq->aeq_elem_pa = info->aeq_elem_pa; 3905 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); 3906 aeq->virtual_map = info->virtual_map; 3907 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); 3908 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); 3909 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); 3910 aeq->msix_idx = info->msix_idx; 3911 info->dev->aeq = aeq; 3912 3913 return 0; 3914 } 3915 3916 /** 3917 * irdma_sc_aeq_create - create aeq 3918 * @aeq: aeq structure ptr 3919 * @scratch: u64 saved to be used during cqp completion 3920 * @post_sq: flag for cqp db to ring 3921 */ 3922 static enum irdma_status_code irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, 3923 u64 scratch, bool post_sq) 3924 { 3925 __le64 *wqe; 3926 struct irdma_sc_cqp *cqp; 3927 u64 hdr; 3928 3929 cqp = aeq->dev->cqp; 3930 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3931 if (!wqe) 3932 return IRDMA_ERR_RING_FULL; 3933 set_64bit_val(wqe, 16, aeq->elem_cnt); 3934 set_64bit_val(wqe, 32, 3935 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); 3936 set_64bit_val(wqe, 48, 3937 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); 3938 3939 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) | 3940 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 3941 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 3942 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3943 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3944 3945 set_64bit_val(wqe, 24, hdr); 3946 3947 print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 3948 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3949 if (post_sq) 3950 irdma_sc_cqp_post_sq(cqp); 3951 3952 return 0; 3953 } 3954 3955 /** 3956 * irdma_sc_aeq_destroy - destroy aeq during close 3957 * @aeq: aeq structure ptr 3958 * @scratch: u64 saved to be used during cqp completion 3959 * @post_sq: flag for cqp db to ring 3960 */ 3961 static enum irdma_status_code irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, 3962 u64 scratch, bool post_sq) 3963 { 3964 __le64 *wqe; 3965 struct irdma_sc_cqp *cqp; 3966 struct irdma_sc_dev *dev; 3967 u64 hdr; 3968 3969 dev = aeq->dev; 3970 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 3971 3972 cqp = dev->cqp; 3973 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3974 if (!wqe) 3975 return IRDMA_ERR_RING_FULL; 3976 set_64bit_val(wqe, 16, aeq->elem_cnt); 3977 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); 3978 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) | 3979 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 3980 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 3981 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3982 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3983 3984 set_64bit_val(wqe, 24, hdr); 3985 3986 print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 3987 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3988 if (post_sq) 3989 irdma_sc_cqp_post_sq(cqp); 3990 return 0; 3991 } 3992 3993 /** 3994 * irdma_sc_get_next_aeqe - get next aeq entry 3995 * @aeq: aeq structure ptr 3996 * @info: aeqe info to be returned 3997 */ 3998 enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 3999 struct irdma_aeqe_info *info) 4000 { 4001 u64 temp, compl_ctx; 4002 __le64 *aeqe; 4003 u16 wqe_idx; 4004 u8 ae_src; 4005 u8 polarity; 4006 4007 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq); 4008 get_64bit_val(aeqe, 0, &compl_ctx); 4009 get_64bit_val(aeqe, 8, &temp); 4010 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp); 4011 4012 if (aeq->polarity != polarity) 4013 return IRDMA_ERR_Q_EMPTY; 4014 4015 print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8, 4016 aeqe, 16, false); 4017 4018 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp); 4019 wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp); 4020 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) | 4021 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18); 4022 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp); 4023 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp); 4024 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp); 4025 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp); 4026 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, temp); 4027 4028 info->ae_src = ae_src; 4029 switch (info->ae_id) { 4030 case IRDMA_AE_PRIV_OPERATION_DENIED: 4031 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW: 4032 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW: 4033 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG: 4034 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH: 4035 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 4036 case IRDMA_AE_UDA_XMIT_BAD_PD: 4037 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 4038 case IRDMA_AE_BAD_CLOSE: 4039 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO: 4040 case IRDMA_AE_STAG_ZERO_INVALID: 4041 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 4042 case IRDMA_AE_IB_INVALID_REQUEST: 4043 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 4044 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 4045 case IRDMA_AE_IB_REMOTE_OP_ERROR: 4046 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 4047 case IRDMA_AE_DDP_UBE_INVALID_MO: 4048 case IRDMA_AE_DDP_UBE_INVALID_QN: 4049 case IRDMA_AE_DDP_NO_L_BIT: 4050 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 4051 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 4052 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 4053 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 4054 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 4055 case IRDMA_AE_INVALID_ARP_ENTRY: 4056 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 4057 case IRDMA_AE_STALE_ARP_ENTRY: 4058 case IRDMA_AE_INVALID_AH_ENTRY: 4059 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 4060 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 4061 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 4062 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 4063 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 4064 case IRDMA_AE_RESET_SENT: 4065 case IRDMA_AE_TERMINATE_SENT: 4066 case IRDMA_AE_RESET_NOT_SENT: 4067 case IRDMA_AE_LCE_QP_CATASTROPHIC: 4068 case IRDMA_AE_QP_SUSPEND_COMPLETE: 4069 case IRDMA_AE_UDA_L4LEN_INVALID: 4070 info->qp = true; 4071 info->compl_ctx = compl_ctx; 4072 break; 4073 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 4074 info->cq = true; 4075 info->compl_ctx = compl_ctx << 1; 4076 ae_src = IRDMA_AE_SOURCE_RSVD; 4077 break; 4078 case IRDMA_AE_ROCE_EMPTY_MCG: 4079 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR: 4080 case IRDMA_AE_ROCE_BAD_MC_QPID: 4081 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH: 4082 fallthrough; 4083 case IRDMA_AE_LLP_CONNECTION_RESET: 4084 case IRDMA_AE_LLP_SYN_RECEIVED: 4085 case IRDMA_AE_LLP_FIN_RECEIVED: 4086 case IRDMA_AE_LLP_CLOSE_COMPLETE: 4087 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 4088 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 4089 ae_src = IRDMA_AE_SOURCE_RSVD; 4090 info->qp = true; 4091 info->compl_ctx = compl_ctx; 4092 break; 4093 default: 4094 break; 4095 } 4096 4097 switch (ae_src) { 4098 case IRDMA_AE_SOURCE_RQ: 4099 case IRDMA_AE_SOURCE_RQ_0011: 4100 info->qp = true; 4101 info->rq = true; 4102 info->wqe_idx = wqe_idx; 4103 info->compl_ctx = compl_ctx; 4104 break; 4105 case IRDMA_AE_SOURCE_CQ: 4106 case IRDMA_AE_SOURCE_CQ_0110: 4107 case IRDMA_AE_SOURCE_CQ_1010: 4108 case IRDMA_AE_SOURCE_CQ_1110: 4109 info->cq = true; 4110 info->compl_ctx = compl_ctx << 1; 4111 break; 4112 case IRDMA_AE_SOURCE_SQ: 4113 case IRDMA_AE_SOURCE_SQ_0111: 4114 info->qp = true; 4115 info->sq = true; 4116 info->wqe_idx = wqe_idx; 4117 info->compl_ctx = compl_ctx; 4118 break; 4119 case IRDMA_AE_SOURCE_IN_RR_WR: 4120 case IRDMA_AE_SOURCE_IN_RR_WR_1011: 4121 info->qp = true; 4122 info->compl_ctx = compl_ctx; 4123 info->in_rdrsp_wr = true; 4124 break; 4125 case IRDMA_AE_SOURCE_OUT_RR: 4126 case IRDMA_AE_SOURCE_OUT_RR_1111: 4127 info->qp = true; 4128 info->compl_ctx = compl_ctx; 4129 info->out_rdrsp = true; 4130 break; 4131 case IRDMA_AE_SOURCE_RSVD: 4132 default: 4133 break; 4134 } 4135 4136 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring); 4137 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring)) 4138 aeq->polarity ^= 1; 4139 4140 return 0; 4141 } 4142 4143 /** 4144 * irdma_sc_repost_aeq_entries - repost completed aeq entries 4145 * @dev: sc device struct 4146 * @count: allocate count 4147 */ 4148 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) 4149 { 4150 writel(count, dev->hw_regs[IRDMA_AEQALLOC]); 4151 } 4152 4153 /** 4154 * irdma_sc_ccq_init - initialize control cq 4155 * @cq: sc's cq ctruct 4156 * @info: info for control cq initialization 4157 */ 4158 enum irdma_status_code irdma_sc_ccq_init(struct irdma_sc_cq *cq, 4159 struct irdma_ccq_init_info *info) 4160 { 4161 u32 pble_obj_cnt; 4162 4163 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size || 4164 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size) 4165 return IRDMA_ERR_INVALID_SIZE; 4166 4167 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) 4168 return IRDMA_ERR_INVALID_CEQ_ID; 4169 4170 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4171 4172 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4173 return IRDMA_ERR_INVALID_PBLE_INDEX; 4174 4175 cq->cq_pa = info->cq_pa; 4176 cq->cq_uk.cq_base = info->cq_base; 4177 cq->shadow_area_pa = info->shadow_area_pa; 4178 cq->cq_uk.shadow_area = info->shadow_area; 4179 cq->shadow_read_threshold = info->shadow_read_threshold; 4180 cq->dev = info->dev; 4181 cq->ceq_id = info->ceq_id; 4182 cq->cq_uk.cq_size = info->num_elem; 4183 cq->cq_type = IRDMA_CQ_TYPE_CQP; 4184 cq->ceqe_mask = info->ceqe_mask; 4185 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); 4186 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ 4187 cq->ceq_id_valid = info->ceq_id_valid; 4188 cq->tph_en = info->tph_en; 4189 cq->tph_val = info->tph_val; 4190 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; 4191 cq->pbl_list = info->pbl_list; 4192 cq->virtual_map = info->virtual_map; 4193 cq->pbl_chunk_size = info->pbl_chunk_size; 4194 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 4195 cq->cq_uk.polarity = true; 4196 cq->vsi = info->vsi; 4197 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db; 4198 4199 /* Only applicable to CQs other than CCQ so initialize to zero */ 4200 cq->cq_uk.cqe_alloc_db = NULL; 4201 4202 info->dev->ccq = cq; 4203 return 0; 4204 } 4205 4206 /** 4207 * irdma_sc_ccq_create_done - poll cqp for ccq create 4208 * @ccq: ccq sc struct 4209 */ 4210 static inline enum irdma_status_code irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq) 4211 { 4212 struct irdma_sc_cqp *cqp; 4213 4214 cqp = ccq->dev->cqp; 4215 4216 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL); 4217 } 4218 4219 /** 4220 * irdma_sc_ccq_create - create control cq 4221 * @ccq: ccq sc struct 4222 * @scratch: u64 saved to be used during cqp completion 4223 * @check_overflow: overlow flag for ccq 4224 * @post_sq: flag for cqp db to ring 4225 */ 4226 enum irdma_status_code irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, 4227 bool check_overflow, bool post_sq) 4228 { 4229 enum irdma_status_code ret_code; 4230 4231 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq); 4232 if (ret_code) 4233 return ret_code; 4234 4235 if (post_sq) { 4236 ret_code = irdma_sc_ccq_create_done(ccq); 4237 if (ret_code) 4238 return ret_code; 4239 } 4240 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd; 4241 4242 return 0; 4243 } 4244 4245 /** 4246 * irdma_sc_ccq_destroy - destroy ccq during close 4247 * @ccq: ccq sc struct 4248 * @scratch: u64 saved to be used during cqp completion 4249 * @post_sq: flag for cqp db to ring 4250 */ 4251 enum irdma_status_code irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, 4252 bool post_sq) 4253 { 4254 struct irdma_sc_cqp *cqp; 4255 __le64 *wqe; 4256 u64 hdr; 4257 enum irdma_status_code ret_code = 0; 4258 u32 tail, val, error; 4259 4260 cqp = ccq->dev->cqp; 4261 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4262 if (!wqe) 4263 return IRDMA_ERR_RING_FULL; 4264 4265 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); 4266 set_64bit_val(wqe, 8, (uintptr_t)ccq >> 1); 4267 set_64bit_val(wqe, 40, ccq->shadow_area_pa); 4268 4269 hdr = ccq->cq_uk.cq_id | 4270 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0), 4271 IRDMA_CQPSQ_CQ_CEQID) | 4272 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 4273 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) | 4274 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) | 4275 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) | 4276 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) | 4277 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4278 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4279 4280 set_64bit_val(wqe, 24, hdr); 4281 4282 print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4283 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4284 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4285 4286 if (post_sq) { 4287 irdma_sc_cqp_post_sq(cqp); 4288 ret_code = irdma_cqp_poll_registers(cqp, tail, 4289 cqp->dev->hw_attrs.max_done_count); 4290 } 4291 4292 cqp->process_cqp_sds = irdma_update_sds_noccq; 4293 4294 return ret_code; 4295 } 4296 4297 /** 4298 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info 4299 * @dev : ptr to irdma_dev struct 4300 * @hmc_fn_id: hmc function id 4301 */ 4302 enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, 4303 u8 hmc_fn_id) 4304 { 4305 struct irdma_hmc_info *hmc_info; 4306 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 4307 struct irdma_dma_mem query_fpm_mem; 4308 enum irdma_status_code ret_code = 0; 4309 u8 wait_type; 4310 4311 hmc_info = dev->hmc_info; 4312 hmc_fpm_misc = &dev->hmc_fpm_misc; 4313 query_fpm_mem.pa = dev->fpm_query_buf_pa; 4314 query_fpm_mem.va = dev->fpm_query_buf; 4315 hmc_info->hmc_fn_id = hmc_fn_id; 4316 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 4317 4318 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 4319 &query_fpm_mem, true, wait_type); 4320 if (ret_code) 4321 return ret_code; 4322 4323 /* parse the fpm_query_buf and fill hmc obj info */ 4324 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info, 4325 hmc_fpm_misc); 4326 4327 print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4328 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE, 4329 false); 4330 return ret_code; 4331 } 4332 4333 /** 4334 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp 4335 * command and populates fpm base address in hmc_info 4336 * @dev : ptr to irdma_dev struct 4337 * @hmc_fn_id: hmc function id 4338 */ 4339 static enum irdma_status_code irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, 4340 u8 hmc_fn_id) 4341 { 4342 struct irdma_hmc_info *hmc_info; 4343 struct irdma_hmc_obj_info *obj_info; 4344 __le64 *buf; 4345 struct irdma_dma_mem commit_fpm_mem; 4346 enum irdma_status_code ret_code = 0; 4347 u8 wait_type; 4348 4349 hmc_info = dev->hmc_info; 4350 obj_info = hmc_info->hmc_obj; 4351 buf = dev->fpm_commit_buf; 4352 4353 set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt); 4354 set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt); 4355 set_64bit_val(buf, 16, (u64)0); /* RSRVD */ 4356 set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt); 4357 set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt); 4358 set_64bit_val(buf, 40, (u64)0); /* RSVD */ 4359 set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt); 4360 set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt); 4361 set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt); 4362 set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt); 4363 set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt); 4364 set_64bit_val(buf, 88, 4365 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt); 4366 set_64bit_val(buf, 96, 4367 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt); 4368 set_64bit_val(buf, 104, 4369 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt); 4370 set_64bit_val(buf, 112, 4371 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt); 4372 set_64bit_val(buf, 120, (u64)0); /* RSVD */ 4373 set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt); 4374 set_64bit_val(buf, 136, 4375 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt); 4376 set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt); 4377 set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt); 4378 set_64bit_val(buf, 160, 4379 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt); 4380 set_64bit_val(buf, 168, 4381 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt); 4382 4383 commit_fpm_mem.pa = dev->fpm_commit_buf_pa; 4384 commit_fpm_mem.va = dev->fpm_commit_buf; 4385 4386 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 4387 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4388 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 4389 false); 4390 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 4391 &commit_fpm_mem, true, wait_type); 4392 if (!ret_code) 4393 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, 4394 hmc_info->hmc_obj, 4395 &hmc_info->sd_table.sd_cnt); 4396 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4397 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 4398 false); 4399 4400 return ret_code; 4401 } 4402 4403 /** 4404 * cqp_sds_wqe_fill - fill cqp wqe doe sd 4405 * @cqp: struct for cqp hw 4406 * @info: sd info for wqe 4407 * @scratch: u64 saved to be used during cqp completion 4408 */ 4409 static enum irdma_status_code 4410 cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, struct irdma_update_sds_info *info, 4411 u64 scratch) 4412 { 4413 u64 data; 4414 u64 hdr; 4415 __le64 *wqe; 4416 int mem_entries, wqe_entries; 4417 struct irdma_dma_mem *sdbuf = &cqp->sdbuf; 4418 u64 offset = 0; 4419 u32 wqe_idx; 4420 4421 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); 4422 if (!wqe) 4423 return IRDMA_ERR_RING_FULL; 4424 4425 wqe_entries = (info->cnt > 3) ? 3 : info->cnt; 4426 mem_entries = info->cnt - wqe_entries; 4427 4428 if (mem_entries) { 4429 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE; 4430 memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4); 4431 4432 data = (u64)sdbuf->pa + offset; 4433 } else { 4434 data = 0; 4435 } 4436 data |= FIELD_PREP(IRDMA_CQPSQ_UPESD_HMCFNID, info->hmc_fn_id); 4437 set_64bit_val(wqe, 16, data); 4438 4439 switch (wqe_entries) { 4440 case 3: 4441 set_64bit_val(wqe, 48, 4442 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) | 4443 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 4444 4445 set_64bit_val(wqe, 56, info->entry[2].data); 4446 fallthrough; 4447 case 2: 4448 set_64bit_val(wqe, 32, 4449 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) | 4450 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 4451 4452 set_64bit_val(wqe, 40, info->entry[1].data); 4453 fallthrough; 4454 case 1: 4455 set_64bit_val(wqe, 0, 4456 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd)); 4457 4458 set_64bit_val(wqe, 8, info->entry[0].data); 4459 break; 4460 default: 4461 break; 4462 } 4463 4464 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) | 4465 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 4466 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries); 4467 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4468 4469 set_64bit_val(wqe, 24, hdr); 4470 4471 if (mem_entries) 4472 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer", 4473 DUMP_PREFIX_OFFSET, 16, 8, 4474 (char *)sdbuf->va + offset, 4475 mem_entries << 4, false); 4476 4477 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16, 4478 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4479 4480 return 0; 4481 } 4482 4483 /** 4484 * irdma_update_pe_sds - cqp wqe for sd 4485 * @dev: ptr to irdma_dev struct 4486 * @info: sd info for sd's 4487 * @scratch: u64 saved to be used during cqp completion 4488 */ 4489 static enum irdma_status_code 4490 irdma_update_pe_sds(struct irdma_sc_dev *dev, 4491 struct irdma_update_sds_info *info, u64 scratch) 4492 { 4493 struct irdma_sc_cqp *cqp = dev->cqp; 4494 enum irdma_status_code ret_code; 4495 4496 ret_code = cqp_sds_wqe_fill(cqp, info, scratch); 4497 if (!ret_code) 4498 irdma_sc_cqp_post_sq(cqp); 4499 4500 return ret_code; 4501 } 4502 4503 /** 4504 * irdma_update_sds_noccq - update sd before ccq created 4505 * @dev: sc device struct 4506 * @info: sd info for sd's 4507 */ 4508 enum irdma_status_code 4509 irdma_update_sds_noccq(struct irdma_sc_dev *dev, 4510 struct irdma_update_sds_info *info) 4511 { 4512 u32 error, val, tail; 4513 struct irdma_sc_cqp *cqp = dev->cqp; 4514 enum irdma_status_code ret_code; 4515 4516 ret_code = cqp_sds_wqe_fill(cqp, info, 0); 4517 if (ret_code) 4518 return ret_code; 4519 4520 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4521 4522 irdma_sc_cqp_post_sq(cqp); 4523 return irdma_cqp_poll_registers(cqp, tail, 4524 cqp->dev->hw_attrs.max_done_count); 4525 } 4526 4527 /** 4528 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages 4529 * @cqp: struct for cqp hw 4530 * @scratch: u64 saved to be used during cqp completion 4531 * @hmc_fn_id: hmc function id 4532 * @post_sq: flag for cqp db to ring 4533 * @poll_registers: flag to poll register for cqp completion 4534 */ 4535 enum irdma_status_code 4536 irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, 4537 u8 hmc_fn_id, bool post_sq, 4538 bool poll_registers) 4539 { 4540 u64 hdr; 4541 __le64 *wqe; 4542 u32 tail, val, error; 4543 4544 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4545 if (!wqe) 4546 return IRDMA_ERR_RING_FULL; 4547 4548 set_64bit_val(wqe, 16, 4549 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id)); 4550 4551 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 4552 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) | 4553 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4554 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4555 4556 set_64bit_val(wqe, 24, hdr); 4557 4558 print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE", 4559 DUMP_PREFIX_OFFSET, 16, 8, wqe, 4560 IRDMA_CQP_WQE_SIZE * 8, false); 4561 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4562 4563 if (post_sq) { 4564 irdma_sc_cqp_post_sq(cqp); 4565 if (poll_registers) 4566 /* check for cqp sq tail update */ 4567 return irdma_cqp_poll_registers(cqp, tail, 4568 cqp->dev->hw_attrs.max_done_count); 4569 else 4570 return irdma_sc_poll_for_cqp_op_done(cqp, 4571 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, 4572 NULL); 4573 } 4574 4575 return 0; 4576 } 4577 4578 /** 4579 * irdma_cqp_ring_full - check if cqp ring is full 4580 * @cqp: struct for cqp hw 4581 */ 4582 static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp) 4583 { 4584 return IRDMA_RING_FULL_ERR(cqp->sq_ring); 4585 } 4586 4587 /** 4588 * irdma_est_sd - returns approximate number of SDs for HMC 4589 * @dev: sc device struct 4590 * @hmc_info: hmc structure, size and count for HMC objects 4591 */ 4592 static u32 irdma_est_sd(struct irdma_sc_dev *dev, 4593 struct irdma_hmc_info *hmc_info) 4594 { 4595 int i; 4596 u64 size = 0; 4597 u64 sd; 4598 4599 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 4600 if (i != IRDMA_HMC_IW_PBLE) 4601 size += round_up(hmc_info->hmc_obj[i].cnt * 4602 hmc_info->hmc_obj[i].size, 512); 4603 size += round_up(hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt * 4604 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].size, 512); 4605 if (size & 0x1FFFFF) 4606 sd = (size >> 21) + 1; /* add 1 for remainder */ 4607 else 4608 sd = size >> 21; 4609 if (sd > 0xFFFFFFFF) { 4610 ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd); 4611 sd = 0xFFFFFFFF - 1; 4612 } 4613 4614 return (u32)sd; 4615 } 4616 4617 /** 4618 * irdma_sc_query_rdma_features_done - poll cqp for query features done 4619 * @cqp: struct for cqp hw 4620 */ 4621 static enum irdma_status_code 4622 irdma_sc_query_rdma_features_done(struct irdma_sc_cqp *cqp) 4623 { 4624 return irdma_sc_poll_for_cqp_op_done(cqp, 4625 IRDMA_CQP_OP_QUERY_RDMA_FEATURES, 4626 NULL); 4627 } 4628 4629 /** 4630 * irdma_sc_query_rdma_features - query RDMA features and FW ver 4631 * @cqp: struct for cqp hw 4632 * @buf: buffer to hold query info 4633 * @scratch: u64 saved to be used during cqp completion 4634 */ 4635 static enum irdma_status_code 4636 irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp, 4637 struct irdma_dma_mem *buf, u64 scratch) 4638 { 4639 __le64 *wqe; 4640 u64 temp; 4641 4642 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4643 if (!wqe) 4644 return IRDMA_ERR_RING_FULL; 4645 4646 temp = buf->pa; 4647 set_64bit_val(wqe, 32, temp); 4648 4649 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID, 4650 cqp->polarity) | 4651 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) | 4652 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES); 4653 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4654 4655 set_64bit_val(wqe, 24, temp); 4656 4657 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 4658 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4659 irdma_sc_cqp_post_sq(cqp); 4660 4661 return 0; 4662 } 4663 4664 /** 4665 * irdma_get_rdma_features - get RDMA features 4666 * @dev: sc device struct 4667 */ 4668 enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev) 4669 { 4670 enum irdma_status_code ret_code; 4671 struct irdma_dma_mem feat_buf; 4672 u64 temp; 4673 u16 byte_idx, feat_type, feat_cnt, feat_idx; 4674 4675 feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE, 4676 IRDMA_FEATURE_BUF_ALIGNMENT); 4677 feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size, 4678 &feat_buf.pa, GFP_KERNEL); 4679 if (!feat_buf.va) 4680 return IRDMA_ERR_NO_MEMORY; 4681 4682 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 4683 if (!ret_code) 4684 ret_code = irdma_sc_query_rdma_features_done(dev->cqp); 4685 if (ret_code) 4686 goto exit; 4687 4688 get_64bit_val(feat_buf.va, 0, &temp); 4689 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 4690 if (feat_cnt < 2) { 4691 ret_code = IRDMA_ERR_INVALID_FEAT_CNT; 4692 goto exit; 4693 } else if (feat_cnt > IRDMA_MAX_FEATURES) { 4694 ibdev_dbg(to_ibdev(dev), 4695 "DEV: feature buf size insufficient, retrying with larger buffer\n"); 4696 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 4697 feat_buf.pa); 4698 feat_buf.va = NULL; 4699 feat_buf.size = ALIGN(8 * feat_cnt, 4700 IRDMA_FEATURE_BUF_ALIGNMENT); 4701 feat_buf.va = dma_alloc_coherent(dev->hw->device, 4702 feat_buf.size, &feat_buf.pa, 4703 GFP_KERNEL); 4704 if (!feat_buf.va) 4705 return IRDMA_ERR_NO_MEMORY; 4706 4707 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 4708 if (!ret_code) 4709 ret_code = irdma_sc_query_rdma_features_done(dev->cqp); 4710 if (ret_code) 4711 goto exit; 4712 4713 get_64bit_val(feat_buf.va, 0, &temp); 4714 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 4715 if (feat_cnt < 2) { 4716 ret_code = IRDMA_ERR_INVALID_FEAT_CNT; 4717 goto exit; 4718 } 4719 } 4720 4721 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 4722 16, 8, feat_buf.va, feat_cnt * 8, false); 4723 4724 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES); 4725 feat_idx++, byte_idx += 8) { 4726 get_64bit_val(feat_buf.va, byte_idx, &temp); 4727 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp); 4728 if (feat_type >= IRDMA_MAX_FEATURES) { 4729 ibdev_dbg(to_ibdev(dev), 4730 "DEV: found unrecognized feature type %d\n", 4731 feat_type); 4732 continue; 4733 } 4734 dev->feature_info[feat_type] = temp; 4735 } 4736 exit: 4737 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 4738 feat_buf.pa); 4739 feat_buf.va = NULL; 4740 return ret_code; 4741 } 4742 4743 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev, 4744 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4745 { 4746 u32 q1_cnt; 4747 4748 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 4749 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted); 4750 } else { 4751 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) 4752 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512); 4753 else 4754 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted; 4755 } 4756 4757 return q1_cnt; 4758 } 4759 4760 static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev, 4761 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4762 { 4763 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes); 4764 } 4765 4766 static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev, 4767 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4768 { 4769 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; 4770 4771 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 4772 4 * hmc_fpm_misc->xf_block_size * qpwanted; 4773 4774 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 4775 4776 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt) 4777 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted; 4778 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 4779 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 4780 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 4781 hmc_fpm_misc->rrf_block_size; 4782 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt) 4783 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted; 4784 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt) 4785 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt = 4786 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt / 4787 hmc_fpm_misc->ooiscf_block_size; 4788 } 4789 4790 /** 4791 * irdma_cfg_fpm_val - configure HMC objects 4792 * @dev: sc device struct 4793 * @qp_count: desired qp count 4794 */ 4795 enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count) 4796 { 4797 struct irdma_virt_mem virt_mem; 4798 u32 i, mem_size; 4799 u32 qpwanted, mrwanted, pblewanted; 4800 u32 powerof2, hte; 4801 u32 sd_needed; 4802 u32 sd_diff; 4803 u32 loop_count = 0; 4804 struct irdma_hmc_info *hmc_info; 4805 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 4806 enum irdma_status_code ret_code = 0; 4807 4808 hmc_info = dev->hmc_info; 4809 hmc_fpm_misc = &dev->hmc_fpm_misc; 4810 4811 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id); 4812 if (ret_code) { 4813 ibdev_dbg(to_ibdev(dev), 4814 "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n", 4815 ret_code); 4816 return ret_code; 4817 } 4818 4819 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 4820 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 4821 sd_needed = irdma_est_sd(dev, hmc_info); 4822 ibdev_dbg(to_ibdev(dev), 4823 "HMC: FW max resources sd_needed[%08d] first_sd_index[%04d]\n", 4824 sd_needed, hmc_info->first_sd_index); 4825 ibdev_dbg(to_ibdev(dev), "HMC: sd count %d where max sd is %d\n", 4826 hmc_info->sd_table.sd_cnt, hmc_fpm_misc->max_sds); 4827 4828 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt); 4829 4830 powerof2 = 1; 4831 while (powerof2 <= qpwanted) 4832 powerof2 *= 2; 4833 powerof2 /= 2; 4834 qpwanted = powerof2; 4835 4836 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 4837 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 4838 4839 ibdev_dbg(to_ibdev(dev), 4840 "HMC: req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d, mc=%d, av=%d\n", 4841 qp_count, hmc_fpm_misc->max_sds, 4842 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt, 4843 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt, 4844 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, 4845 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, 4846 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, 4847 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 4848 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = 4849 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; 4850 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 4851 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt; 4852 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt = 4853 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt; 4854 4855 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1; 4856 4857 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt) 4858 qpwanted /= 2; 4859 4860 do { 4861 ++loop_count; 4862 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 4863 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 4864 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt); 4865 hmc_info->hmc_obj[IRDMA_HMC_IW_RESERVED].cnt = 0; /* Reserved */ 4866 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 4867 4868 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512); 4869 powerof2 = 1; 4870 while (powerof2 < hte) 4871 powerof2 *= 2; 4872 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt = 4873 powerof2 * hmc_fpm_misc->ht_multiplier; 4874 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 4875 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); 4876 else 4877 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted); 4878 4879 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted); 4880 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 4881 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; 4882 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 4883 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 4884 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 4885 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket; 4886 4887 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 4888 sd_needed = irdma_est_sd(dev, hmc_info); 4889 ibdev_dbg(to_ibdev(dev), 4890 "HMC: sd_needed = %d, hmc_fpm_misc->max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n", 4891 sd_needed, hmc_fpm_misc->max_sds, mrwanted, 4892 pblewanted, qpwanted); 4893 4894 /* Do not reduce resources further. All objects fit with max SDs */ 4895 if (sd_needed <= hmc_fpm_misc->max_sds) 4896 break; 4897 4898 sd_diff = sd_needed - hmc_fpm_misc->max_sds; 4899 if (sd_diff > 128) { 4900 if (qpwanted > 128 && sd_diff > 144) 4901 qpwanted /= 2; 4902 mrwanted /= 2; 4903 pblewanted /= 2; 4904 continue; 4905 } 4906 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF && 4907 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) { 4908 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff; 4909 continue; 4910 } else if (pblewanted > (100 * FPM_MULTIPLIER)) { 4911 pblewanted -= 10 * FPM_MULTIPLIER; 4912 } else if (pblewanted > FPM_MULTIPLIER) { 4913 pblewanted -= FPM_MULTIPLIER; 4914 } else if (qpwanted <= 128) { 4915 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256) 4916 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2; 4917 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 4918 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 4919 } 4920 if (mrwanted > FPM_MULTIPLIER) 4921 mrwanted -= FPM_MULTIPLIER; 4922 if (!(loop_count % 10) && qpwanted > 128) { 4923 qpwanted /= 2; 4924 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 4925 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 4926 } 4927 } while (loop_count < 2000); 4928 4929 if (sd_needed > hmc_fpm_misc->max_sds) { 4930 ibdev_dbg(to_ibdev(dev), 4931 "HMC: cfg_fpm failed loop_cnt=%d, sd_needed=%d, max sd count %d\n", 4932 loop_count, sd_needed, hmc_info->sd_table.sd_cnt); 4933 return IRDMA_ERR_CFG; 4934 } 4935 4936 if (loop_count > 1 && sd_needed < hmc_fpm_misc->max_sds) { 4937 pblewanted += (hmc_fpm_misc->max_sds - sd_needed) * 256 * 4938 FPM_MULTIPLIER; 4939 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 4940 sd_needed = irdma_est_sd(dev, hmc_info); 4941 } 4942 4943 ibdev_dbg(to_ibdev(dev), 4944 "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n", 4945 loop_count, sd_needed, 4946 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt, 4947 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 4948 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt, 4949 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt, 4950 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 4951 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt, 4952 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index); 4953 4954 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 4955 if (ret_code) { 4956 ibdev_dbg(to_ibdev(dev), 4957 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 4958 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 4959 return ret_code; 4960 } 4961 4962 mem_size = sizeof(struct irdma_hmc_sd_entry) * 4963 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1); 4964 virt_mem.size = mem_size; 4965 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); 4966 if (!virt_mem.va) { 4967 ibdev_dbg(to_ibdev(dev), 4968 "HMC: failed to allocate memory for sd_entry buffer\n"); 4969 return IRDMA_ERR_NO_MEMORY; 4970 } 4971 hmc_info->sd_table.sd_entry = virt_mem.va; 4972 4973 return ret_code; 4974 } 4975 4976 /** 4977 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available 4978 * @dev: rdma device 4979 * @pcmdinfo: cqp command info 4980 */ 4981 static enum irdma_status_code irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, 4982 struct cqp_cmds_info *pcmdinfo) 4983 { 4984 enum irdma_status_code status; 4985 struct irdma_dma_mem val_mem; 4986 bool alloc = false; 4987 4988 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; 4989 switch (pcmdinfo->cqp_cmd) { 4990 case IRDMA_OP_CEQ_DESTROY: 4991 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, 4992 pcmdinfo->in.u.ceq_destroy.scratch, 4993 pcmdinfo->post_sq); 4994 break; 4995 case IRDMA_OP_AEQ_DESTROY: 4996 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, 4997 pcmdinfo->in.u.aeq_destroy.scratch, 4998 pcmdinfo->post_sq); 4999 5000 break; 5001 case IRDMA_OP_CEQ_CREATE: 5002 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, 5003 pcmdinfo->in.u.ceq_create.scratch, 5004 pcmdinfo->post_sq); 5005 break; 5006 case IRDMA_OP_AEQ_CREATE: 5007 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, 5008 pcmdinfo->in.u.aeq_create.scratch, 5009 pcmdinfo->post_sq); 5010 break; 5011 case IRDMA_OP_QP_UPLOAD_CONTEXT: 5012 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev, 5013 &pcmdinfo->in.u.qp_upload_context.info, 5014 pcmdinfo->in.u.qp_upload_context.scratch, 5015 pcmdinfo->post_sq); 5016 break; 5017 case IRDMA_OP_CQ_CREATE: 5018 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq, 5019 pcmdinfo->in.u.cq_create.scratch, 5020 pcmdinfo->in.u.cq_create.check_overflow, 5021 pcmdinfo->post_sq); 5022 break; 5023 case IRDMA_OP_CQ_MODIFY: 5024 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq, 5025 &pcmdinfo->in.u.cq_modify.info, 5026 pcmdinfo->in.u.cq_modify.scratch, 5027 pcmdinfo->post_sq); 5028 break; 5029 case IRDMA_OP_CQ_DESTROY: 5030 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq, 5031 pcmdinfo->in.u.cq_destroy.scratch, 5032 pcmdinfo->post_sq); 5033 break; 5034 case IRDMA_OP_QP_FLUSH_WQES: 5035 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp, 5036 &pcmdinfo->in.u.qp_flush_wqes.info, 5037 pcmdinfo->in.u.qp_flush_wqes.scratch, 5038 pcmdinfo->post_sq); 5039 break; 5040 case IRDMA_OP_GEN_AE: 5041 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp, 5042 &pcmdinfo->in.u.gen_ae.info, 5043 pcmdinfo->in.u.gen_ae.scratch, 5044 pcmdinfo->post_sq); 5045 break; 5046 case IRDMA_OP_MANAGE_PUSH_PAGE: 5047 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp, 5048 &pcmdinfo->in.u.manage_push_page.info, 5049 pcmdinfo->in.u.manage_push_page.scratch, 5050 pcmdinfo->post_sq); 5051 break; 5052 case IRDMA_OP_UPDATE_PE_SDS: 5053 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev, 5054 &pcmdinfo->in.u.update_pe_sds.info, 5055 pcmdinfo->in.u.update_pe_sds.scratch); 5056 break; 5057 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE: 5058 /* switch to calling through the call table */ 5059 status = 5060 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp, 5061 &pcmdinfo->in.u.manage_hmc_pm.info, 5062 pcmdinfo->in.u.manage_hmc_pm.scratch, 5063 true); 5064 break; 5065 case IRDMA_OP_SUSPEND: 5066 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp, 5067 pcmdinfo->in.u.suspend_resume.qp, 5068 pcmdinfo->in.u.suspend_resume.scratch); 5069 break; 5070 case IRDMA_OP_RESUME: 5071 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp, 5072 pcmdinfo->in.u.suspend_resume.qp, 5073 pcmdinfo->in.u.suspend_resume.scratch); 5074 break; 5075 case IRDMA_OP_QUERY_FPM_VAL: 5076 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa; 5077 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va; 5078 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp, 5079 pcmdinfo->in.u.query_fpm_val.scratch, 5080 pcmdinfo->in.u.query_fpm_val.hmc_fn_id, 5081 &val_mem, true, IRDMA_CQP_WAIT_EVENT); 5082 break; 5083 case IRDMA_OP_COMMIT_FPM_VAL: 5084 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa; 5085 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va; 5086 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp, 5087 pcmdinfo->in.u.commit_fpm_val.scratch, 5088 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id, 5089 &val_mem, 5090 true, 5091 IRDMA_CQP_WAIT_EVENT); 5092 break; 5093 case IRDMA_OP_STATS_ALLOCATE: 5094 alloc = true; 5095 fallthrough; 5096 case IRDMA_OP_STATS_FREE: 5097 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp, 5098 &pcmdinfo->in.u.stats_manage.info, 5099 alloc, 5100 pcmdinfo->in.u.stats_manage.scratch); 5101 break; 5102 case IRDMA_OP_STATS_GATHER: 5103 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp, 5104 &pcmdinfo->in.u.stats_gather.info, 5105 pcmdinfo->in.u.stats_gather.scratch); 5106 break; 5107 case IRDMA_OP_WS_MODIFY_NODE: 5108 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5109 &pcmdinfo->in.u.ws_node.info, 5110 IRDMA_MODIFY_NODE, 5111 pcmdinfo->in.u.ws_node.scratch); 5112 break; 5113 case IRDMA_OP_WS_DELETE_NODE: 5114 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5115 &pcmdinfo->in.u.ws_node.info, 5116 IRDMA_DEL_NODE, 5117 pcmdinfo->in.u.ws_node.scratch); 5118 break; 5119 case IRDMA_OP_WS_ADD_NODE: 5120 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5121 &pcmdinfo->in.u.ws_node.info, 5122 IRDMA_ADD_NODE, 5123 pcmdinfo->in.u.ws_node.scratch); 5124 break; 5125 case IRDMA_OP_SET_UP_MAP: 5126 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp, 5127 &pcmdinfo->in.u.up_map.info, 5128 pcmdinfo->in.u.up_map.scratch); 5129 break; 5130 case IRDMA_OP_QUERY_RDMA_FEATURES: 5131 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp, 5132 &pcmdinfo->in.u.query_rdma.query_buff_mem, 5133 pcmdinfo->in.u.query_rdma.scratch); 5134 break; 5135 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY: 5136 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp, 5137 pcmdinfo->in.u.del_arp_cache_entry.scratch, 5138 pcmdinfo->in.u.del_arp_cache_entry.arp_index, 5139 pcmdinfo->post_sq); 5140 break; 5141 case IRDMA_OP_MANAGE_APBVT_ENTRY: 5142 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp, 5143 &pcmdinfo->in.u.manage_apbvt_entry.info, 5144 pcmdinfo->in.u.manage_apbvt_entry.scratch, 5145 pcmdinfo->post_sq); 5146 break; 5147 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY: 5148 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp, 5149 &pcmdinfo->in.u.manage_qhash_table_entry.info, 5150 pcmdinfo->in.u.manage_qhash_table_entry.scratch, 5151 pcmdinfo->post_sq); 5152 break; 5153 case IRDMA_OP_QP_MODIFY: 5154 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp, 5155 &pcmdinfo->in.u.qp_modify.info, 5156 pcmdinfo->in.u.qp_modify.scratch, 5157 pcmdinfo->post_sq); 5158 break; 5159 case IRDMA_OP_QP_CREATE: 5160 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp, 5161 &pcmdinfo->in.u.qp_create.info, 5162 pcmdinfo->in.u.qp_create.scratch, 5163 pcmdinfo->post_sq); 5164 break; 5165 case IRDMA_OP_QP_DESTROY: 5166 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp, 5167 pcmdinfo->in.u.qp_destroy.scratch, 5168 pcmdinfo->in.u.qp_destroy.remove_hash_idx, 5169 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd, 5170 pcmdinfo->post_sq); 5171 break; 5172 case IRDMA_OP_ALLOC_STAG: 5173 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev, 5174 &pcmdinfo->in.u.alloc_stag.info, 5175 pcmdinfo->in.u.alloc_stag.scratch, 5176 pcmdinfo->post_sq); 5177 break; 5178 case IRDMA_OP_MR_REG_NON_SHARED: 5179 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev, 5180 &pcmdinfo->in.u.mr_reg_non_shared.info, 5181 pcmdinfo->in.u.mr_reg_non_shared.scratch, 5182 pcmdinfo->post_sq); 5183 break; 5184 case IRDMA_OP_DEALLOC_STAG: 5185 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev, 5186 &pcmdinfo->in.u.dealloc_stag.info, 5187 pcmdinfo->in.u.dealloc_stag.scratch, 5188 pcmdinfo->post_sq); 5189 break; 5190 case IRDMA_OP_MW_ALLOC: 5191 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev, 5192 &pcmdinfo->in.u.mw_alloc.info, 5193 pcmdinfo->in.u.mw_alloc.scratch, 5194 pcmdinfo->post_sq); 5195 break; 5196 case IRDMA_OP_ADD_ARP_CACHE_ENTRY: 5197 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp, 5198 &pcmdinfo->in.u.add_arp_cache_entry.info, 5199 pcmdinfo->in.u.add_arp_cache_entry.scratch, 5200 pcmdinfo->post_sq); 5201 break; 5202 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY: 5203 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp, 5204 pcmdinfo->in.u.alloc_local_mac_entry.scratch, 5205 pcmdinfo->post_sq); 5206 break; 5207 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY: 5208 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp, 5209 &pcmdinfo->in.u.add_local_mac_entry.info, 5210 pcmdinfo->in.u.add_local_mac_entry.scratch, 5211 pcmdinfo->post_sq); 5212 break; 5213 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY: 5214 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp, 5215 pcmdinfo->in.u.del_local_mac_entry.scratch, 5216 pcmdinfo->in.u.del_local_mac_entry.entry_idx, 5217 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count, 5218 pcmdinfo->post_sq); 5219 break; 5220 case IRDMA_OP_AH_CREATE: 5221 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp, 5222 &pcmdinfo->in.u.ah_create.info, 5223 pcmdinfo->in.u.ah_create.scratch); 5224 break; 5225 case IRDMA_OP_AH_DESTROY: 5226 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp, 5227 &pcmdinfo->in.u.ah_destroy.info, 5228 pcmdinfo->in.u.ah_destroy.scratch); 5229 break; 5230 case IRDMA_OP_MC_CREATE: 5231 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp, 5232 &pcmdinfo->in.u.mc_create.info, 5233 pcmdinfo->in.u.mc_create.scratch); 5234 break; 5235 case IRDMA_OP_MC_DESTROY: 5236 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp, 5237 &pcmdinfo->in.u.mc_destroy.info, 5238 pcmdinfo->in.u.mc_destroy.scratch); 5239 break; 5240 case IRDMA_OP_MC_MODIFY: 5241 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp, 5242 &pcmdinfo->in.u.mc_modify.info, 5243 pcmdinfo->in.u.mc_modify.scratch); 5244 break; 5245 default: 5246 status = IRDMA_NOT_SUPPORTED; 5247 break; 5248 } 5249 5250 return status; 5251 } 5252 5253 /** 5254 * irdma_process_cqp_cmd - process all cqp commands 5255 * @dev: sc device struct 5256 * @pcmdinfo: cqp command info 5257 */ 5258 enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev, 5259 struct cqp_cmds_info *pcmdinfo) 5260 { 5261 enum irdma_status_code status = 0; 5262 unsigned long flags; 5263 5264 spin_lock_irqsave(&dev->cqp_lock, flags); 5265 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp)) 5266 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 5267 else 5268 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); 5269 spin_unlock_irqrestore(&dev->cqp_lock, flags); 5270 return status; 5271 } 5272 5273 /** 5274 * irdma_process_bh - called from tasklet for cqp list 5275 * @dev: sc device struct 5276 */ 5277 enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev) 5278 { 5279 enum irdma_status_code status = 0; 5280 struct cqp_cmds_info *pcmdinfo; 5281 unsigned long flags; 5282 5283 spin_lock_irqsave(&dev->cqp_lock, flags); 5284 while (!list_empty(&dev->cqp_cmd_head) && 5285 !irdma_cqp_ring_full(dev->cqp)) { 5286 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev); 5287 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 5288 if (status) 5289 break; 5290 } 5291 spin_unlock_irqrestore(&dev->cqp_lock, flags); 5292 return status; 5293 } 5294 5295 /** 5296 * irdma_cfg_aeq- Configure AEQ interrupt 5297 * @dev: pointer to the device structure 5298 * @idx: vector index 5299 * @enable: True to enable, False disables 5300 */ 5301 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable) 5302 { 5303 u32 reg_val; 5304 5305 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) | 5306 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) | 5307 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, 3); 5308 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 5309 } 5310 5311 /** 5312 * sc_vsi_update_stats - Update statistics 5313 * @vsi: sc_vsi instance to update 5314 */ 5315 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi) 5316 { 5317 struct irdma_gather_stats *gather_stats; 5318 struct irdma_gather_stats *last_gather_stats; 5319 5320 gather_stats = vsi->pestat->gather_info.gather_stats_va; 5321 last_gather_stats = vsi->pestat->gather_info.last_gather_stats_va; 5322 irdma_update_stats(&vsi->pestat->hw_stats, gather_stats, 5323 last_gather_stats); 5324 } 5325 5326 /** 5327 * irdma_wait_pe_ready - Check if firmware is ready 5328 * @dev: provides access to registers 5329 */ 5330 static int irdma_wait_pe_ready(struct irdma_sc_dev *dev) 5331 { 5332 u32 statuscpu0; 5333 u32 statuscpu1; 5334 u32 statuscpu2; 5335 u32 retrycount = 0; 5336 5337 do { 5338 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]); 5339 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]); 5340 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]); 5341 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 && 5342 statuscpu2 == 0x80) 5343 return 0; 5344 mdelay(1000); 5345 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count); 5346 return -1; 5347 } 5348 5349 static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) 5350 { 5351 switch (dev->hw_attrs.uk_attrs.hw_rev) { 5352 case IRDMA_GEN_1: 5353 i40iw_init_hw(dev); 5354 break; 5355 case IRDMA_GEN_2: 5356 icrdma_init_hw(dev); 5357 break; 5358 } 5359 } 5360 5361 /** 5362 * irdma_sc_dev_init - Initialize control part of device 5363 * @ver: version 5364 * @dev: Device pointer 5365 * @info: Device init info 5366 */ 5367 enum irdma_status_code irdma_sc_dev_init(enum irdma_vers ver, 5368 struct irdma_sc_dev *dev, 5369 struct irdma_device_init_info *info) 5370 { 5371 u32 val; 5372 enum irdma_status_code ret_code = 0; 5373 u8 db_size; 5374 5375 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */ 5376 mutex_init(&dev->ws_mutex); 5377 dev->hmc_fn_id = info->hmc_fn_id; 5378 dev->fpm_query_buf_pa = info->fpm_query_buf_pa; 5379 dev->fpm_query_buf = info->fpm_query_buf; 5380 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; 5381 dev->fpm_commit_buf = info->fpm_commit_buf; 5382 dev->hw = info->hw; 5383 dev->hw->hw_addr = info->bar0; 5384 /* Setup the hardware limits, hmc may limit further */ 5385 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID; 5386 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES; 5387 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES; 5388 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES; 5389 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES; 5390 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE; 5391 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE; 5392 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IRDMA_MAX_WQ_FRAGMENT_COUNT; 5393 dev->hw_attrs.uk_attrs.max_hw_read_sges = IRDMA_MAX_SGE_RD; 5394 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE; 5395 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE; 5396 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE; 5397 dev->hw_attrs.max_hw_device_pages = IRDMA_MAX_PUSH_PAGE_COUNT; 5398 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE; 5399 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES; 5400 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR); 5401 5402 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA; 5403 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA; 5404 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS; 5405 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT; 5406 5407 dev->hw_attrs.max_pe_ready_count = 14; 5408 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT; 5409 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT; 5410 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS; 5411 5412 dev->hw_attrs.uk_attrs.hw_rev = ver; 5413 irdma_sc_init_hw(dev); 5414 5415 if (irdma_wait_pe_ready(dev)) 5416 return IRDMA_ERR_TIMEOUT; 5417 5418 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]); 5419 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val); 5420 if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) { 5421 ibdev_dbg(to_ibdev(dev), 5422 "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n", 5423 val, db_size); 5424 return IRDMA_ERR_PE_DOORBELL_NOT_ENA; 5425 } 5426 dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET]; 5427 5428 return ret_code; 5429 } 5430 5431 /** 5432 * irdma_update_stats - Update statistics 5433 * @hw_stats: hw_stats instance to update 5434 * @gather_stats: updated stat counters 5435 * @last_gather_stats: last stat counters 5436 */ 5437 void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, 5438 struct irdma_gather_stats *gather_stats, 5439 struct irdma_gather_stats *last_gather_stats) 5440 { 5441 u64 *stats_val = hw_stats->stats_val_32; 5442 5443 stats_val[IRDMA_HW_STAT_INDEX_RXVLANERR] += 5444 IRDMA_STATS_DELTA(gather_stats->rxvlanerr, 5445 last_gather_stats->rxvlanerr, 5446 IRDMA_MAX_STATS_32); 5447 stats_val[IRDMA_HW_STAT_INDEX_IP4RXDISCARD] += 5448 IRDMA_STATS_DELTA(gather_stats->ip4rxdiscard, 5449 last_gather_stats->ip4rxdiscard, 5450 IRDMA_MAX_STATS_32); 5451 stats_val[IRDMA_HW_STAT_INDEX_IP4RXTRUNC] += 5452 IRDMA_STATS_DELTA(gather_stats->ip4rxtrunc, 5453 last_gather_stats->ip4rxtrunc, 5454 IRDMA_MAX_STATS_32); 5455 stats_val[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] += 5456 IRDMA_STATS_DELTA(gather_stats->ip4txnoroute, 5457 last_gather_stats->ip4txnoroute, 5458 IRDMA_MAX_STATS_32); 5459 stats_val[IRDMA_HW_STAT_INDEX_IP6RXDISCARD] += 5460 IRDMA_STATS_DELTA(gather_stats->ip6rxdiscard, 5461 last_gather_stats->ip6rxdiscard, 5462 IRDMA_MAX_STATS_32); 5463 stats_val[IRDMA_HW_STAT_INDEX_IP6RXTRUNC] += 5464 IRDMA_STATS_DELTA(gather_stats->ip6rxtrunc, 5465 last_gather_stats->ip6rxtrunc, 5466 IRDMA_MAX_STATS_32); 5467 stats_val[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] += 5468 IRDMA_STATS_DELTA(gather_stats->ip6txnoroute, 5469 last_gather_stats->ip6txnoroute, 5470 IRDMA_MAX_STATS_32); 5471 stats_val[IRDMA_HW_STAT_INDEX_TCPRTXSEG] += 5472 IRDMA_STATS_DELTA(gather_stats->tcprtxseg, 5473 last_gather_stats->tcprtxseg, 5474 IRDMA_MAX_STATS_32); 5475 stats_val[IRDMA_HW_STAT_INDEX_TCPRXOPTERR] += 5476 IRDMA_STATS_DELTA(gather_stats->tcprxopterr, 5477 last_gather_stats->tcprxopterr, 5478 IRDMA_MAX_STATS_32); 5479 stats_val[IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] += 5480 IRDMA_STATS_DELTA(gather_stats->tcprxprotoerr, 5481 last_gather_stats->tcprxprotoerr, 5482 IRDMA_MAX_STATS_32); 5483 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] += 5484 IRDMA_STATS_DELTA(gather_stats->rxrpcnphandled, 5485 last_gather_stats->rxrpcnphandled, 5486 IRDMA_MAX_STATS_32); 5487 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] += 5488 IRDMA_STATS_DELTA(gather_stats->rxrpcnpignored, 5489 last_gather_stats->rxrpcnpignored, 5490 IRDMA_MAX_STATS_32); 5491 stats_val[IRDMA_HW_STAT_INDEX_TXNPCNPSENT] += 5492 IRDMA_STATS_DELTA(gather_stats->txnpcnpsent, 5493 last_gather_stats->txnpcnpsent, 5494 IRDMA_MAX_STATS_32); 5495 stats_val = hw_stats->stats_val_64; 5496 stats_val[IRDMA_HW_STAT_INDEX_IP4RXOCTS] += 5497 IRDMA_STATS_DELTA(gather_stats->ip4rxocts, 5498 last_gather_stats->ip4rxocts, 5499 IRDMA_MAX_STATS_48); 5500 stats_val[IRDMA_HW_STAT_INDEX_IP4RXPKTS] += 5501 IRDMA_STATS_DELTA(gather_stats->ip4rxpkts, 5502 last_gather_stats->ip4rxpkts, 5503 IRDMA_MAX_STATS_48); 5504 stats_val[IRDMA_HW_STAT_INDEX_IP4RXFRAGS] += 5505 IRDMA_STATS_DELTA(gather_stats->ip4txfrag, 5506 last_gather_stats->ip4txfrag, 5507 IRDMA_MAX_STATS_48); 5508 stats_val[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] += 5509 IRDMA_STATS_DELTA(gather_stats->ip4rxmcpkts, 5510 last_gather_stats->ip4rxmcpkts, 5511 IRDMA_MAX_STATS_48); 5512 stats_val[IRDMA_HW_STAT_INDEX_IP4TXOCTS] += 5513 IRDMA_STATS_DELTA(gather_stats->ip4txocts, 5514 last_gather_stats->ip4txocts, 5515 IRDMA_MAX_STATS_48); 5516 stats_val[IRDMA_HW_STAT_INDEX_IP4TXPKTS] += 5517 IRDMA_STATS_DELTA(gather_stats->ip4txpkts, 5518 last_gather_stats->ip4txpkts, 5519 IRDMA_MAX_STATS_48); 5520 stats_val[IRDMA_HW_STAT_INDEX_IP4TXFRAGS] += 5521 IRDMA_STATS_DELTA(gather_stats->ip4txfrag, 5522 last_gather_stats->ip4txfrag, 5523 IRDMA_MAX_STATS_48); 5524 stats_val[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] += 5525 IRDMA_STATS_DELTA(gather_stats->ip4txmcpkts, 5526 last_gather_stats->ip4txmcpkts, 5527 IRDMA_MAX_STATS_48); 5528 stats_val[IRDMA_HW_STAT_INDEX_IP6RXOCTS] += 5529 IRDMA_STATS_DELTA(gather_stats->ip6rxocts, 5530 last_gather_stats->ip6rxocts, 5531 IRDMA_MAX_STATS_48); 5532 stats_val[IRDMA_HW_STAT_INDEX_IP6RXPKTS] += 5533 IRDMA_STATS_DELTA(gather_stats->ip6rxpkts, 5534 last_gather_stats->ip6rxpkts, 5535 IRDMA_MAX_STATS_48); 5536 stats_val[IRDMA_HW_STAT_INDEX_IP6RXFRAGS] += 5537 IRDMA_STATS_DELTA(gather_stats->ip6txfrags, 5538 last_gather_stats->ip6txfrags, 5539 IRDMA_MAX_STATS_48); 5540 stats_val[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] += 5541 IRDMA_STATS_DELTA(gather_stats->ip6rxmcpkts, 5542 last_gather_stats->ip6rxmcpkts, 5543 IRDMA_MAX_STATS_48); 5544 stats_val[IRDMA_HW_STAT_INDEX_IP6TXOCTS] += 5545 IRDMA_STATS_DELTA(gather_stats->ip6txocts, 5546 last_gather_stats->ip6txocts, 5547 IRDMA_MAX_STATS_48); 5548 stats_val[IRDMA_HW_STAT_INDEX_IP6TXPKTS] += 5549 IRDMA_STATS_DELTA(gather_stats->ip6txpkts, 5550 last_gather_stats->ip6txpkts, 5551 IRDMA_MAX_STATS_48); 5552 stats_val[IRDMA_HW_STAT_INDEX_IP6TXFRAGS] += 5553 IRDMA_STATS_DELTA(gather_stats->ip6txfrags, 5554 last_gather_stats->ip6txfrags, 5555 IRDMA_MAX_STATS_48); 5556 stats_val[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] += 5557 IRDMA_STATS_DELTA(gather_stats->ip6txmcpkts, 5558 last_gather_stats->ip6txmcpkts, 5559 IRDMA_MAX_STATS_48); 5560 stats_val[IRDMA_HW_STAT_INDEX_TCPRXSEGS] += 5561 IRDMA_STATS_DELTA(gather_stats->tcprxsegs, 5562 last_gather_stats->tcprxsegs, 5563 IRDMA_MAX_STATS_48); 5564 stats_val[IRDMA_HW_STAT_INDEX_TCPTXSEG] += 5565 IRDMA_STATS_DELTA(gather_stats->tcptxsegs, 5566 last_gather_stats->tcptxsegs, 5567 IRDMA_MAX_STATS_48); 5568 stats_val[IRDMA_HW_STAT_INDEX_RDMARXRDS] += 5569 IRDMA_STATS_DELTA(gather_stats->rdmarxrds, 5570 last_gather_stats->rdmarxrds, 5571 IRDMA_MAX_STATS_48); 5572 stats_val[IRDMA_HW_STAT_INDEX_RDMARXSNDS] += 5573 IRDMA_STATS_DELTA(gather_stats->rdmarxsnds, 5574 last_gather_stats->rdmarxsnds, 5575 IRDMA_MAX_STATS_48); 5576 stats_val[IRDMA_HW_STAT_INDEX_RDMARXWRS] += 5577 IRDMA_STATS_DELTA(gather_stats->rdmarxwrs, 5578 last_gather_stats->rdmarxwrs, 5579 IRDMA_MAX_STATS_48); 5580 stats_val[IRDMA_HW_STAT_INDEX_RDMATXRDS] += 5581 IRDMA_STATS_DELTA(gather_stats->rdmatxrds, 5582 last_gather_stats->rdmatxrds, 5583 IRDMA_MAX_STATS_48); 5584 stats_val[IRDMA_HW_STAT_INDEX_RDMATXSNDS] += 5585 IRDMA_STATS_DELTA(gather_stats->rdmatxsnds, 5586 last_gather_stats->rdmatxsnds, 5587 IRDMA_MAX_STATS_48); 5588 stats_val[IRDMA_HW_STAT_INDEX_RDMATXWRS] += 5589 IRDMA_STATS_DELTA(gather_stats->rdmatxwrs, 5590 last_gather_stats->rdmatxwrs, 5591 IRDMA_MAX_STATS_48); 5592 stats_val[IRDMA_HW_STAT_INDEX_RDMAVBND] += 5593 IRDMA_STATS_DELTA(gather_stats->rdmavbn, 5594 last_gather_stats->rdmavbn, 5595 IRDMA_MAX_STATS_48); 5596 stats_val[IRDMA_HW_STAT_INDEX_RDMAVINV] += 5597 IRDMA_STATS_DELTA(gather_stats->rdmavinv, 5598 last_gather_stats->rdmavinv, 5599 IRDMA_MAX_STATS_48); 5600 stats_val[IRDMA_HW_STAT_INDEX_UDPRXPKTS] += 5601 IRDMA_STATS_DELTA(gather_stats->udprxpkts, 5602 last_gather_stats->udprxpkts, 5603 IRDMA_MAX_STATS_48); 5604 stats_val[IRDMA_HW_STAT_INDEX_UDPTXPKTS] += 5605 IRDMA_STATS_DELTA(gather_stats->udptxpkts, 5606 last_gather_stats->udptxpkts, 5607 IRDMA_MAX_STATS_48); 5608 stats_val[IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] += 5609 IRDMA_STATS_DELTA(gather_stats->rxnpecnmrkpkts, 5610 last_gather_stats->rxnpecnmrkpkts, 5611 IRDMA_MAX_STATS_48); 5612 memcpy(last_gather_stats, gather_stats, sizeof(*last_gather_stats)); 5613 } 5614