1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include <linux/etherdevice.h> 4 5 #include "osdep.h" 6 #include "status.h" 7 #include "hmc.h" 8 #include "defs.h" 9 #include "type.h" 10 #include "ws.h" 11 #include "protos.h" 12 13 /** 14 * irdma_get_qp_from_list - get next qp from a list 15 * @head: Listhead of qp's 16 * @qp: current qp 17 */ 18 struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, 19 struct irdma_sc_qp *qp) 20 { 21 struct list_head *lastentry; 22 struct list_head *entry = NULL; 23 24 if (list_empty(head)) 25 return NULL; 26 27 if (!qp) { 28 entry = head->next; 29 } else { 30 lastentry = &qp->list; 31 entry = lastentry->next; 32 if (entry == head) 33 return NULL; 34 } 35 36 return container_of(entry, struct irdma_sc_qp, list); 37 } 38 39 /** 40 * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI 41 * @vsi: the VSI struct pointer 42 * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND 43 */ 44 void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op) 45 { 46 struct irdma_sc_qp *qp = NULL; 47 u8 i; 48 49 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 50 mutex_lock(&vsi->qos[i].qos_mutex); 51 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 52 while (qp) { 53 if (op == IRDMA_OP_RESUME) { 54 if (!qp->dev->ws_add(vsi, i)) { 55 qp->qs_handle = 56 vsi->qos[qp->user_pri].qs_handle; 57 irdma_cqp_qp_suspend_resume(qp, op); 58 } else { 59 irdma_cqp_qp_suspend_resume(qp, op); 60 irdma_modify_qp_to_err(qp); 61 } 62 } else if (op == IRDMA_OP_SUSPEND) { 63 /* issue cqp suspend command */ 64 if (!irdma_cqp_qp_suspend_resume(qp, op)) 65 atomic_inc(&vsi->qp_suspend_reqs); 66 } 67 qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); 68 } 69 mutex_unlock(&vsi->qos[i].qos_mutex); 70 } 71 } 72 73 /** 74 * irdma_change_l2params - given the new l2 parameters, change all qp 75 * @vsi: RDMA VSI pointer 76 * @l2params: New parameters from l2 77 */ 78 void irdma_change_l2params(struct irdma_sc_vsi *vsi, 79 struct irdma_l2params *l2params) 80 { 81 if (l2params->mtu_changed) { 82 vsi->mtu = l2params->mtu; 83 if (vsi->ieq) 84 irdma_reinitialize_ieq(vsi); 85 } 86 87 if (!l2params->tc_changed) 88 return; 89 90 vsi->tc_change_pending = false; 91 irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME); 92 } 93 94 /** 95 * irdma_qp_rem_qos - remove qp from qos lists during destroy qp 96 * @qp: qp to be removed from qos 97 */ 98 void irdma_qp_rem_qos(struct irdma_sc_qp *qp) 99 { 100 struct irdma_sc_vsi *vsi = qp->vsi; 101 102 ibdev_dbg(to_ibdev(qp->dev), 103 "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 104 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 105 qp->on_qoslist); 106 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 107 if (qp->on_qoslist) { 108 qp->on_qoslist = false; 109 list_del(&qp->list); 110 } 111 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 112 } 113 114 /** 115 * irdma_qp_add_qos - called during setctx for qp to be added to qos 116 * @qp: qp to be added to qos 117 */ 118 void irdma_qp_add_qos(struct irdma_sc_qp *qp) 119 { 120 struct irdma_sc_vsi *vsi = qp->vsi; 121 122 ibdev_dbg(to_ibdev(qp->dev), 123 "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", 124 qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, 125 qp->on_qoslist); 126 mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); 127 if (!qp->on_qoslist) { 128 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); 129 qp->on_qoslist = true; 130 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle; 131 } 132 mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); 133 } 134 135 /** 136 * irdma_sc_pd_init - initialize sc pd struct 137 * @dev: sc device struct 138 * @pd: sc pd ptr 139 * @pd_id: pd_id for allocated pd 140 * @abi_ver: User/Kernel ABI version 141 */ 142 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, 143 int abi_ver) 144 { 145 pd->pd_id = pd_id; 146 pd->abi_ver = abi_ver; 147 pd->dev = dev; 148 } 149 150 /** 151 * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry 152 * @cqp: struct for cqp hw 153 * @info: arp entry information 154 * @scratch: u64 saved to be used during cqp completion 155 * @post_sq: flag for cqp db to ring 156 */ 157 static enum irdma_status_code 158 irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp, 159 struct irdma_add_arp_cache_entry_info *info, 160 u64 scratch, bool post_sq) 161 { 162 __le64 *wqe; 163 u64 hdr; 164 165 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 166 if (!wqe) 167 return IRDMA_ERR_RING_FULL; 168 set_64bit_val(wqe, 8, info->reach_max); 169 set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr)); 170 171 hdr = info->arp_index | 172 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 173 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | 174 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | 175 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 176 dma_wmb(); /* make sure WQE is written before valid bit is set */ 177 178 set_64bit_val(wqe, 24, hdr); 179 180 print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET, 181 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 182 if (post_sq) 183 irdma_sc_cqp_post_sq(cqp); 184 185 return 0; 186 } 187 188 /** 189 * irdma_sc_del_arp_cache_entry - dele arp cache entry 190 * @cqp: struct for cqp hw 191 * @scratch: u64 saved to be used during cqp completion 192 * @arp_index: arp index to delete arp entry 193 * @post_sq: flag for cqp db to ring 194 */ 195 static enum irdma_status_code 196 irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch, 197 u16 arp_index, bool post_sq) 198 { 199 __le64 *wqe; 200 u64 hdr; 201 202 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 203 if (!wqe) 204 return IRDMA_ERR_RING_FULL; 205 206 hdr = arp_index | 207 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | 208 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 209 dma_wmb(); /* make sure WQE is written before valid bit is set */ 210 211 set_64bit_val(wqe, 24, hdr); 212 213 print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE", 214 DUMP_PREFIX_OFFSET, 16, 8, wqe, 215 IRDMA_CQP_WQE_SIZE * 8, false); 216 if (post_sq) 217 irdma_sc_cqp_post_sq(cqp); 218 219 return 0; 220 } 221 222 /** 223 * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries 224 * @cqp: struct for cqp hw 225 * @info: info for apbvt entry to add or delete 226 * @scratch: u64 saved to be used during cqp completion 227 * @post_sq: flag for cqp db to ring 228 */ 229 static enum irdma_status_code 230 irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp, 231 struct irdma_apbvt_info *info, u64 scratch, 232 bool post_sq) 233 { 234 __le64 *wqe; 235 u64 hdr; 236 237 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 238 if (!wqe) 239 return IRDMA_ERR_RING_FULL; 240 241 set_64bit_val(wqe, 16, info->port); 242 243 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | 244 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | 245 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 246 dma_wmb(); /* make sure WQE is written before valid bit is set */ 247 248 set_64bit_val(wqe, 24, hdr); 249 250 print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16, 251 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 252 if (post_sq) 253 irdma_sc_cqp_post_sq(cqp); 254 255 return 0; 256 } 257 258 /** 259 * irdma_sc_manage_qhash_table_entry - manage quad hash entries 260 * @cqp: struct for cqp hw 261 * @info: info for quad hash to manage 262 * @scratch: u64 saved to be used during cqp completion 263 * @post_sq: flag for cqp db to ring 264 * 265 * This is called before connection establishment is started. 266 * For passive connections, when listener is created, it will 267 * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local 268 * ip address and tcp port. When SYN is received (passive 269 * connections) or sent (active connections), this routine is 270 * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED 271 * and quad is passed in info. 272 * 273 * When iwarp connection is done and its state moves to RTS, the 274 * quad hash entry in the hardware will point to iwarp's qp 275 * number and requires no calls from the driver. 276 */ 277 static enum irdma_status_code 278 irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp, 279 struct irdma_qhash_table_info *info, 280 u64 scratch, bool post_sq) 281 { 282 __le64 *wqe; 283 u64 qw1 = 0; 284 u64 qw2 = 0; 285 u64 temp; 286 struct irdma_sc_vsi *vsi = info->vsi; 287 288 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 289 if (!wqe) 290 return IRDMA_ERR_RING_FULL; 291 292 set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr)); 293 294 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | 295 FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port); 296 if (info->ipv4_valid) { 297 set_64bit_val(wqe, 48, 298 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0])); 299 } else { 300 set_64bit_val(wqe, 56, 301 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) | 302 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1])); 303 304 set_64bit_val(wqe, 48, 305 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) | 306 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3])); 307 } 308 qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE, 309 vsi->qos[info->user_pri].qs_handle); 310 if (info->vlan_valid) 311 qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id); 312 set_64bit_val(wqe, 16, qw2); 313 if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) { 314 qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port); 315 if (!info->ipv4_valid) { 316 set_64bit_val(wqe, 40, 317 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) | 318 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1])); 319 set_64bit_val(wqe, 32, 320 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) | 321 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3])); 322 } else { 323 set_64bit_val(wqe, 32, 324 FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0])); 325 } 326 } 327 328 set_64bit_val(wqe, 8, qw1); 329 temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) | 330 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, 331 IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) | 332 FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) | 333 FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) | 334 FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) | 335 FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type); 336 dma_wmb(); /* make sure WQE is written before valid bit is set */ 337 338 set_64bit_val(wqe, 24, temp); 339 340 print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16, 341 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 342 if (post_sq) 343 irdma_sc_cqp_post_sq(cqp); 344 345 return 0; 346 } 347 348 /** 349 * irdma_sc_qp_init - initialize qp 350 * @qp: sc qp 351 * @info: initialization qp info 352 */ 353 enum irdma_status_code irdma_sc_qp_init(struct irdma_sc_qp *qp, 354 struct irdma_qp_init_info *info) 355 { 356 enum irdma_status_code ret_code; 357 u32 pble_obj_cnt; 358 u16 wqe_size; 359 360 if (info->qp_uk_init_info.max_sq_frag_cnt > 361 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags || 362 info->qp_uk_init_info.max_rq_frag_cnt > 363 info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags) 364 return IRDMA_ERR_INVALID_FRAG_COUNT; 365 366 qp->dev = info->pd->dev; 367 qp->vsi = info->vsi; 368 qp->ieq_qp = info->vsi->exception_lan_q; 369 qp->sq_pa = info->sq_pa; 370 qp->rq_pa = info->rq_pa; 371 qp->hw_host_ctx_pa = info->host_ctx_pa; 372 qp->q2_pa = info->q2_pa; 373 qp->shadow_area_pa = info->shadow_area_pa; 374 qp->q2_buf = info->q2; 375 qp->pd = info->pd; 376 qp->hw_host_ctx = info->host_ctx; 377 info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db; 378 ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info); 379 if (ret_code) 380 return ret_code; 381 382 qp->virtual_map = info->virtual_map; 383 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 384 385 if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) || 386 (info->virtual_map && info->rq_pa >= pble_obj_cnt)) 387 return IRDMA_ERR_INVALID_PBLE_INDEX; 388 389 qp->llp_stream_handle = (void *)(-1); 390 qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, 391 IRDMA_QUEUE_TYPE_SQ_RQ); 392 ibdev_dbg(to_ibdev(qp->dev), 393 "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n", 394 qp->hw_sq_size, qp->qp_uk.sq_ring.size); 395 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4) 396 wqe_size = IRDMA_WQE_SIZE_128; 397 else 398 ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, 399 &wqe_size); 400 if (ret_code) 401 return ret_code; 402 403 qp->hw_rq_size = irdma_get_encoded_wqe_size(qp->qp_uk.rq_size * 404 (wqe_size / IRDMA_QP_WQE_MIN_SIZE), IRDMA_QUEUE_TYPE_SQ_RQ); 405 ibdev_dbg(to_ibdev(qp->dev), 406 "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", 407 qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); 408 qp->sq_tph_val = info->sq_tph_val; 409 qp->rq_tph_val = info->rq_tph_val; 410 qp->sq_tph_en = info->sq_tph_en; 411 qp->rq_tph_en = info->rq_tph_en; 412 qp->rcv_tph_en = info->rcv_tph_en; 413 qp->xmit_tph_en = info->xmit_tph_en; 414 qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq; 415 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle; 416 417 return 0; 418 } 419 420 /** 421 * irdma_sc_qp_create - create qp 422 * @qp: sc qp 423 * @info: qp create info 424 * @scratch: u64 saved to be used during cqp completion 425 * @post_sq: flag for cqp db to ring 426 */ 427 enum irdma_status_code irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info, 428 u64 scratch, bool post_sq) 429 { 430 struct irdma_sc_cqp *cqp; 431 __le64 *wqe; 432 u64 hdr; 433 434 cqp = qp->dev->cqp; 435 if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id || 436 qp->qp_uk.qp_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt - 1)) 437 return IRDMA_ERR_INVALID_QP_ID; 438 439 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 440 if (!wqe) 441 return IRDMA_ERR_RING_FULL; 442 443 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 444 set_64bit_val(wqe, 40, qp->shadow_area_pa); 445 446 hdr = qp->qp_uk.qp_id | 447 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | 448 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, (info->ord_valid ? 1 : 0)) | 449 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 450 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 451 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 452 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 453 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 454 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 455 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 456 info->arp_cache_idx_valid) | 457 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 458 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 459 dma_wmb(); /* make sure WQE is written before valid bit is set */ 460 461 set_64bit_val(wqe, 24, hdr); 462 463 print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 464 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 465 if (post_sq) 466 irdma_sc_cqp_post_sq(cqp); 467 468 return 0; 469 } 470 471 /** 472 * irdma_sc_qp_modify - modify qp cqp wqe 473 * @qp: sc qp 474 * @info: modify qp info 475 * @scratch: u64 saved to be used during cqp completion 476 * @post_sq: flag for cqp db to ring 477 */ 478 enum irdma_status_code irdma_sc_qp_modify(struct irdma_sc_qp *qp, 479 struct irdma_modify_qp_info *info, 480 u64 scratch, bool post_sq) 481 { 482 __le64 *wqe; 483 struct irdma_sc_cqp *cqp; 484 u64 hdr; 485 u8 term_actions = 0; 486 u8 term_len = 0; 487 488 cqp = qp->dev->cqp; 489 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 490 if (!wqe) 491 return IRDMA_ERR_RING_FULL; 492 493 if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) { 494 if (info->dont_send_fin) 495 term_actions += IRDMAQP_TERM_SEND_TERM_ONLY; 496 if (info->dont_send_term) 497 term_actions += IRDMAQP_TERM_SEND_FIN_ONLY; 498 if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN || 499 term_actions == IRDMAQP_TERM_SEND_TERM_ONLY) 500 term_len = info->termlen; 501 } 502 503 set_64bit_val(wqe, 8, 504 FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) | 505 FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len)); 506 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 507 set_64bit_val(wqe, 40, qp->shadow_area_pa); 508 509 hdr = qp->qp_uk.qp_id | 510 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) | 511 FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | 512 FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | 513 FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID, 514 info->cached_var_valid) | 515 FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | 516 FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | 517 FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | 518 FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | 519 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 520 FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) | 521 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, 522 info->remove_hash_idx) | 523 FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) | 524 FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) | 525 FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, 526 info->arp_cache_idx_valid) | 527 FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | 528 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 529 dma_wmb(); /* make sure WQE is written before valid bit is set */ 530 531 set_64bit_val(wqe, 24, hdr); 532 533 print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 534 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 535 if (post_sq) 536 irdma_sc_cqp_post_sq(cqp); 537 538 return 0; 539 } 540 541 /** 542 * irdma_sc_qp_destroy - cqp destroy qp 543 * @qp: sc qp 544 * @scratch: u64 saved to be used during cqp completion 545 * @remove_hash_idx: flag if to remove hash idx 546 * @ignore_mw_bnd: memory window bind flag 547 * @post_sq: flag for cqp db to ring 548 */ 549 enum irdma_status_code irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, 550 bool remove_hash_idx, bool ignore_mw_bnd, 551 bool post_sq) 552 { 553 __le64 *wqe; 554 struct irdma_sc_cqp *cqp; 555 u64 hdr; 556 557 cqp = qp->dev->cqp; 558 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 559 if (!wqe) 560 return IRDMA_ERR_RING_FULL; 561 562 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); 563 set_64bit_val(wqe, 40, qp->shadow_area_pa); 564 565 hdr = qp->qp_uk.qp_id | 566 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) | 567 FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | 568 FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) | 569 FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) | 570 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 571 dma_wmb(); /* make sure WQE is written before valid bit is set */ 572 573 set_64bit_val(wqe, 24, hdr); 574 575 print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 576 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 577 if (post_sq) 578 irdma_sc_cqp_post_sq(cqp); 579 580 return 0; 581 } 582 583 /** 584 * irdma_sc_get_encoded_ird_size - 585 * @ird_size: IRD size 586 * The ird from the connection is rounded to a supported HW setting and then encoded 587 * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based 588 * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input 589 */ 590 static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) 591 { 592 switch (ird_size ? 593 roundup_pow_of_two(2 * ird_size) : 4) { 594 case 256: 595 return IRDMA_IRD_HW_SIZE_256; 596 case 128: 597 return IRDMA_IRD_HW_SIZE_128; 598 case 64: 599 case 32: 600 return IRDMA_IRD_HW_SIZE_64; 601 case 16: 602 case 8: 603 return IRDMA_IRD_HW_SIZE_16; 604 case 4: 605 default: 606 break; 607 } 608 609 return IRDMA_IRD_HW_SIZE_4; 610 } 611 612 /** 613 * irdma_sc_qp_setctx_roce - set qp's context 614 * @qp: sc qp 615 * @qp_ctx: context ptr 616 * @info: ctx info 617 */ 618 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, 619 struct irdma_qp_host_ctx_info *info) 620 { 621 struct irdma_roce_offload_info *roce_info; 622 struct irdma_udp_offload_info *udp; 623 u8 push_mode_en; 624 u32 push_idx; 625 626 roce_info = info->roce_info; 627 udp = info->udp_info; 628 qp->user_pri = info->user_pri; 629 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 630 push_mode_en = 0; 631 push_idx = 0; 632 } else { 633 push_mode_en = 1; 634 push_idx = qp->push_idx; 635 } 636 set_64bit_val(qp_ctx, 0, 637 FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 638 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 639 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 640 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 641 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 642 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 643 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | 644 FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) | 645 FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | 646 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) | 647 FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | 648 FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | 649 FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | 650 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag)); 651 set_64bit_val(qp_ctx, 8, qp->sq_pa); 652 set_64bit_val(qp_ctx, 16, qp->rq_pa); 653 if ((roce_info->dcqcn_en || roce_info->dctcp_en) && 654 !(udp->tos & 0x03)) 655 udp->tos |= ECN_CODE_PT_VAL; 656 set_64bit_val(qp_ctx, 24, 657 FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 658 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | 659 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | 660 FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | 661 FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port)); 662 set_64bit_val(qp_ctx, 32, 663 FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | 664 FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); 665 set_64bit_val(qp_ctx, 40, 666 FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | 667 FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); 668 set_64bit_val(qp_ctx, 48, 669 FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | 670 FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | 671 FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); 672 set_64bit_val(qp_ctx, 56, 673 FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | 674 FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) | 675 FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | 676 FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label)); 677 set_64bit_val(qp_ctx, 64, 678 FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | 679 FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp)); 680 set_64bit_val(qp_ctx, 80, 681 FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | 682 FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); 683 set_64bit_val(qp_ctx, 88, 684 FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); 685 set_64bit_val(qp_ctx, 96, 686 FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | 687 FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); 688 set_64bit_val(qp_ctx, 112, 689 FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); 690 set_64bit_val(qp_ctx, 128, 691 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | 692 FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | 693 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | 694 FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); 695 set_64bit_val(qp_ctx, 136, 696 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 697 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 698 set_64bit_val(qp_ctx, 144, 699 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 700 set_64bit_val(qp_ctx, 152, ether_addr_to_u64(roce_info->mac_addr) << 16); 701 set_64bit_val(qp_ctx, 160, 702 FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) | 703 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) | 704 FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | 705 FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | 706 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 707 FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | 708 FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | 709 FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | 710 FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | 711 FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) | 712 FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) | 713 FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | 714 FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); 715 set_64bit_val(qp_ctx, 168, 716 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 717 set_64bit_val(qp_ctx, 176, 718 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 719 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 720 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); 721 set_64bit_val(qp_ctx, 184, 722 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | 723 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); 724 set_64bit_val(qp_ctx, 192, 725 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | 726 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); 727 set_64bit_val(qp_ctx, 200, 728 FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | 729 FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); 730 set_64bit_val(qp_ctx, 208, 731 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 732 733 print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, 734 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); 735 } 736 737 /* irdma_sc_alloc_local_mac_entry - allocate a mac entry 738 * @cqp: struct for cqp hw 739 * @scratch: u64 saved to be used during cqp completion 740 * @post_sq: flag for cqp db to ring 741 */ 742 static enum irdma_status_code 743 irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 744 bool post_sq) 745 { 746 __le64 *wqe; 747 u64 hdr; 748 749 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 750 if (!wqe) 751 return IRDMA_ERR_RING_FULL; 752 753 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 754 IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) | 755 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 756 757 dma_wmb(); /* make sure WQE is written before valid bit is set */ 758 759 set_64bit_val(wqe, 24, hdr); 760 761 print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE", 762 DUMP_PREFIX_OFFSET, 16, 8, wqe, 763 IRDMA_CQP_WQE_SIZE * 8, false); 764 765 if (post_sq) 766 irdma_sc_cqp_post_sq(cqp); 767 return 0; 768 } 769 770 /** 771 * irdma_sc_add_local_mac_entry - add mac enry 772 * @cqp: struct for cqp hw 773 * @info:mac addr info 774 * @scratch: u64 saved to be used during cqp completion 775 * @post_sq: flag for cqp db to ring 776 */ 777 static enum irdma_status_code 778 irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp, 779 struct irdma_local_mac_entry_info *info, 780 u64 scratch, bool post_sq) 781 { 782 __le64 *wqe; 783 u64 header; 784 785 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 786 if (!wqe) 787 return IRDMA_ERR_RING_FULL; 788 789 set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr)); 790 791 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) | 792 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 793 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 794 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 795 796 dma_wmb(); /* make sure WQE is written before valid bit is set */ 797 798 set_64bit_val(wqe, 24, header); 799 800 print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16, 801 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 802 803 if (post_sq) 804 irdma_sc_cqp_post_sq(cqp); 805 return 0; 806 } 807 808 /** 809 * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac 810 * @cqp: struct for cqp hw 811 * @scratch: u64 saved to be used during cqp completion 812 * @entry_idx: index of mac entry 813 * @ignore_ref_count: to force mac adde delete 814 * @post_sq: flag for cqp db to ring 815 */ 816 static enum irdma_status_code 817 irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, 818 u16 entry_idx, u8 ignore_ref_count, bool post_sq) 819 { 820 __le64 *wqe; 821 u64 header; 822 823 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 824 if (!wqe) 825 return IRDMA_ERR_RING_FULL; 826 header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) | 827 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 828 IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | 829 FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) | 830 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 831 FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count); 832 833 dma_wmb(); /* make sure WQE is written before valid bit is set */ 834 835 set_64bit_val(wqe, 24, header); 836 837 print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE", 838 DUMP_PREFIX_OFFSET, 16, 8, wqe, 839 IRDMA_CQP_WQE_SIZE * 8, false); 840 841 if (post_sq) 842 irdma_sc_cqp_post_sq(cqp); 843 return 0; 844 } 845 846 /** 847 * irdma_sc_qp_setctx - set qp's context 848 * @qp: sc qp 849 * @qp_ctx: context ptr 850 * @info: ctx info 851 */ 852 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, 853 struct irdma_qp_host_ctx_info *info) 854 { 855 struct irdma_iwarp_offload_info *iw; 856 struct irdma_tcp_offload_info *tcp; 857 struct irdma_sc_dev *dev; 858 u8 push_mode_en; 859 u32 push_idx; 860 u64 qw0, qw3, qw7 = 0, qw16 = 0; 861 u64 mac = 0; 862 863 iw = info->iwarp_info; 864 tcp = info->tcp_info; 865 dev = qp->dev; 866 if (iw->rcv_mark_en) { 867 qp->pfpdu.marker_len = 4; 868 qp->pfpdu.rcv_start_seq = tcp->rcv_nxt; 869 } 870 qp->user_pri = info->user_pri; 871 if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { 872 push_mode_en = 0; 873 push_idx = 0; 874 } else { 875 push_mode_en = 1; 876 push_idx = qp->push_idx; 877 } 878 qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | 879 FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | 880 FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | 881 FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | 882 FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | 883 FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | 884 FIELD_PREP(IRDMAQPC_PMENA, push_mode_en); 885 886 set_64bit_val(qp_ctx, 8, qp->sq_pa); 887 set_64bit_val(qp_ctx, 16, qp->rq_pa); 888 889 qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | 890 FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size); 891 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 892 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, 893 qp->src_mac_addr_idx); 894 set_64bit_val(qp_ctx, 136, 895 FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | 896 FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); 897 set_64bit_val(qp_ctx, 168, 898 FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); 899 set_64bit_val(qp_ctx, 176, 900 FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | 901 FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | 902 FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) | 903 FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp)); 904 if (info->iwarp_info_valid) { 905 qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) | 906 FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) | 907 FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) | 908 FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) | 909 FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) | 910 FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) | 911 FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, 912 iw->err_rq_idx_valid); 913 qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id); 914 qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) | 915 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); 916 set_64bit_val(qp_ctx, 144, 917 FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) | 918 FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); 919 920 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) 921 mac = ether_addr_to_u64(iw->mac_addr); 922 923 set_64bit_val(qp_ctx, 152, 924 mac << 16 | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent)); 925 set_64bit_val(qp_ctx, 160, 926 FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) | 927 FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) | 928 FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) | 929 FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) | 930 FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) | 931 FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) | 932 FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) | 933 FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) | 934 FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | 935 FIELD_PREP(IRDMAQPC_IWARPMODE, 1) | 936 FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) | 937 FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) | 938 FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) | 939 FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) | 940 FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) | 941 FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en)); 942 } 943 if (info->tcp_info_valid) { 944 qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) | 945 FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) | 946 FIELD_PREP(IRDMAQPC_INSERTVLANTAG, 947 tcp->insert_vlan_tag) | 948 FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) | 949 FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) | 950 FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) | 951 FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh); 952 953 if ((iw->ecn_en || iw->dctcp_en) && !(tcp->tos & 0x03)) 954 tcp->tos |= ECN_CODE_PT_VAL; 955 956 qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) | 957 FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) | 958 FIELD_PREP(IRDMAQPC_TOS, tcp->tos) | 959 FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) | 960 FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port); 961 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 962 qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx); 963 964 qp->src_mac_addr_idx = tcp->src_mac_addr_idx; 965 } 966 set_64bit_val(qp_ctx, 32, 967 FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) | 968 FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3])); 969 set_64bit_val(qp_ctx, 40, 970 FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) | 971 FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1])); 972 set_64bit_val(qp_ctx, 48, 973 FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) | 974 FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) | 975 FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) | 976 FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx)); 977 qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) | 978 FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) | 979 FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT, 980 tcp->ignore_tcp_opt) | 981 FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT, 982 tcp->ignore_tcp_uns_opt) | 983 FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) | 984 FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) | 985 FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale); 986 set_64bit_val(qp_ctx, 72, 987 FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) | 988 FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age)); 989 set_64bit_val(qp_ctx, 80, 990 FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) | 991 FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd)); 992 set_64bit_val(qp_ctx, 88, 993 FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) | 994 FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd)); 995 set_64bit_val(qp_ctx, 96, 996 FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) | 997 FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una)); 998 set_64bit_val(qp_ctx, 104, 999 FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) | 1000 FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var)); 1001 set_64bit_val(qp_ctx, 112, 1002 FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) | 1003 FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd)); 1004 set_64bit_val(qp_ctx, 120, 1005 FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) | 1006 FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2)); 1007 qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) | 1008 FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh); 1009 set_64bit_val(qp_ctx, 184, 1010 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) | 1011 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2])); 1012 set_64bit_val(qp_ctx, 192, 1013 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) | 1014 FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0])); 1015 set_64bit_val(qp_ctx, 200, 1016 FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) | 1017 FIELD_PREP(IRDMAQPC_TLOW, iw->t_low)); 1018 set_64bit_val(qp_ctx, 208, 1019 FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); 1020 } 1021 1022 set_64bit_val(qp_ctx, 0, qw0); 1023 set_64bit_val(qp_ctx, 24, qw3); 1024 set_64bit_val(qp_ctx, 56, qw7); 1025 set_64bit_val(qp_ctx, 128, qw16); 1026 1027 print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8, 1028 qp_ctx, IRDMA_QP_CTX_SIZE, false); 1029 } 1030 1031 /** 1032 * irdma_sc_alloc_stag - mr stag alloc 1033 * @dev: sc device struct 1034 * @info: stag info 1035 * @scratch: u64 saved to be used during cqp completion 1036 * @post_sq: flag for cqp db to ring 1037 */ 1038 static enum irdma_status_code 1039 irdma_sc_alloc_stag(struct irdma_sc_dev *dev, 1040 struct irdma_allocate_stag_info *info, u64 scratch, 1041 bool post_sq) 1042 { 1043 __le64 *wqe; 1044 struct irdma_sc_cqp *cqp; 1045 u64 hdr; 1046 enum irdma_page_size page_size; 1047 1048 if (info->page_size == 0x40000000) 1049 page_size = IRDMA_PAGE_SIZE_1G; 1050 else if (info->page_size == 0x200000) 1051 page_size = IRDMA_PAGE_SIZE_2M; 1052 else 1053 page_size = IRDMA_PAGE_SIZE_4K; 1054 1055 cqp = dev->cqp; 1056 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1057 if (!wqe) 1058 return IRDMA_ERR_RING_FULL; 1059 1060 set_64bit_val(wqe, 8, 1061 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) | 1062 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len)); 1063 set_64bit_val(wqe, 16, 1064 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1065 set_64bit_val(wqe, 40, 1066 FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index)); 1067 1068 if (info->chunk_size) 1069 set_64bit_val(wqe, 48, 1070 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx)); 1071 1072 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1073 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1074 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1075 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1076 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1077 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) | 1078 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1079 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1080 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1081 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1082 1083 set_64bit_val(wqe, 24, hdr); 1084 1085 print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1086 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1087 if (post_sq) 1088 irdma_sc_cqp_post_sq(cqp); 1089 1090 return 0; 1091 } 1092 1093 /** 1094 * irdma_sc_mr_reg_non_shared - non-shared mr registration 1095 * @dev: sc device struct 1096 * @info: mr info 1097 * @scratch: u64 saved to be used during cqp completion 1098 * @post_sq: flag for cqp db to ring 1099 */ 1100 static enum irdma_status_code 1101 irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev, 1102 struct irdma_reg_ns_stag_info *info, u64 scratch, 1103 bool post_sq) 1104 { 1105 __le64 *wqe; 1106 u64 fbo; 1107 struct irdma_sc_cqp *cqp; 1108 u64 hdr; 1109 u32 pble_obj_cnt; 1110 bool remote_access; 1111 u8 addr_type; 1112 enum irdma_page_size page_size; 1113 1114 if (info->page_size == 0x40000000) 1115 page_size = IRDMA_PAGE_SIZE_1G; 1116 else if (info->page_size == 0x200000) 1117 page_size = IRDMA_PAGE_SIZE_2M; 1118 else if (info->page_size == 0x1000) 1119 page_size = IRDMA_PAGE_SIZE_4K; 1120 else 1121 return IRDMA_ERR_PARAM; 1122 1123 if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY | 1124 IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY)) 1125 remote_access = true; 1126 else 1127 remote_access = false; 1128 1129 pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 1130 if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt) 1131 return IRDMA_ERR_INVALID_PBLE_INDEX; 1132 1133 cqp = dev->cqp; 1134 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1135 if (!wqe) 1136 return IRDMA_ERR_RING_FULL; 1137 fbo = info->va & (info->page_size - 1); 1138 1139 set_64bit_val(wqe, 0, 1140 (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ? 1141 info->va : fbo)); 1142 set_64bit_val(wqe, 8, 1143 FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) | 1144 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1145 set_64bit_val(wqe, 16, 1146 FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) | 1147 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1148 if (!info->chunk_size) { 1149 set_64bit_val(wqe, 32, info->reg_addr_pa); 1150 set_64bit_val(wqe, 48, 0); 1151 } else { 1152 set_64bit_val(wqe, 32, 0); 1153 set_64bit_val(wqe, 48, 1154 FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index)); 1155 } 1156 set_64bit_val(wqe, 40, info->hmc_fcn_index); 1157 set_64bit_val(wqe, 56, 0); 1158 1159 addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0; 1160 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) | 1161 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | 1162 FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | 1163 FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | 1164 FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | 1165 FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) | 1166 FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) | 1167 FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | 1168 FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | 1169 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1170 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1171 1172 set_64bit_val(wqe, 24, hdr); 1173 1174 print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8, 1175 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1176 if (post_sq) 1177 irdma_sc_cqp_post_sq(cqp); 1178 1179 return 0; 1180 } 1181 1182 /** 1183 * irdma_sc_dealloc_stag - deallocate stag 1184 * @dev: sc device struct 1185 * @info: dealloc stag info 1186 * @scratch: u64 saved to be used during cqp completion 1187 * @post_sq: flag for cqp db to ring 1188 */ 1189 static enum irdma_status_code 1190 irdma_sc_dealloc_stag(struct irdma_sc_dev *dev, 1191 struct irdma_dealloc_stag_info *info, u64 scratch, 1192 bool post_sq) 1193 { 1194 u64 hdr; 1195 __le64 *wqe; 1196 struct irdma_sc_cqp *cqp; 1197 1198 cqp = dev->cqp; 1199 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1200 if (!wqe) 1201 return IRDMA_ERR_RING_FULL; 1202 1203 set_64bit_val(wqe, 8, 1204 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1205 set_64bit_val(wqe, 16, 1206 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); 1207 1208 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) | 1209 FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) | 1210 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1211 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1212 1213 set_64bit_val(wqe, 24, hdr); 1214 1215 print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 1216 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1217 if (post_sq) 1218 irdma_sc_cqp_post_sq(cqp); 1219 1220 return 0; 1221 } 1222 1223 /** 1224 * irdma_sc_mw_alloc - mw allocate 1225 * @dev: sc device struct 1226 * @info: memory window allocation information 1227 * @scratch: u64 saved to be used during cqp completion 1228 * @post_sq: flag for cqp db to ring 1229 */ 1230 static enum irdma_status_code 1231 irdma_sc_mw_alloc(struct irdma_sc_dev *dev, struct irdma_mw_alloc_info *info, 1232 u64 scratch, bool post_sq) 1233 { 1234 u64 hdr; 1235 struct irdma_sc_cqp *cqp; 1236 __le64 *wqe; 1237 1238 cqp = dev->cqp; 1239 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 1240 if (!wqe) 1241 return IRDMA_ERR_RING_FULL; 1242 1243 set_64bit_val(wqe, 8, 1244 FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); 1245 set_64bit_val(wqe, 16, 1246 FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index)); 1247 1248 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | 1249 FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) | 1250 FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY, 1251 info->mw1_bind_dont_vldt_key) | 1252 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 1253 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1254 1255 set_64bit_val(wqe, 24, hdr); 1256 1257 print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8, 1258 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 1259 if (post_sq) 1260 irdma_sc_cqp_post_sq(cqp); 1261 1262 return 0; 1263 } 1264 1265 /** 1266 * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp 1267 * @qp: sc qp struct 1268 * @info: fast mr info 1269 * @post_sq: flag for cqp db to ring 1270 */ 1271 enum irdma_status_code 1272 irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, 1273 struct irdma_fast_reg_stag_info *info, bool post_sq) 1274 { 1275 u64 temp, hdr; 1276 __le64 *wqe; 1277 u32 wqe_idx; 1278 enum irdma_page_size page_size; 1279 struct irdma_post_sq_info sq_info = {}; 1280 1281 if (info->page_size == 0x40000000) 1282 page_size = IRDMA_PAGE_SIZE_1G; 1283 else if (info->page_size == 0x200000) 1284 page_size = IRDMA_PAGE_SIZE_2M; 1285 else 1286 page_size = IRDMA_PAGE_SIZE_4K; 1287 1288 sq_info.wr_id = info->wr_id; 1289 sq_info.signaled = info->signaled; 1290 sq_info.push_wqe = info->push_wqe; 1291 1292 wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, 1293 IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info); 1294 if (!wqe) 1295 return IRDMA_ERR_QP_TOOMANY_WRS_POSTED; 1296 1297 irdma_clr_wqes(&qp->qp_uk, wqe_idx); 1298 1299 ibdev_dbg(to_ibdev(qp->dev), 1300 "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", 1301 info->wr_id, wqe_idx, 1302 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); 1303 1304 temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1305 (uintptr_t)info->va : info->fbo; 1306 set_64bit_val(wqe, 0, temp); 1307 1308 temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI, 1309 info->first_pm_pbl_index >> 16); 1310 set_64bit_val(wqe, 8, 1311 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) | 1312 FIELD_PREP(IRDMAQPSQ_PBLADDR >> IRDMA_HW_PAGE_SHIFT, info->reg_addr_pa)); 1313 set_64bit_val(wqe, 16, 1314 info->total_len | 1315 FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index)); 1316 1317 hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) | 1318 FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) | 1319 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) | 1320 FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) | 1321 FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) | 1322 FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) | 1323 FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) | 1324 FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) | 1325 FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | 1326 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | 1327 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | 1328 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1329 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1330 1331 set_64bit_val(wqe, 24, hdr); 1332 1333 print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8, 1334 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1335 if (sq_info.push_wqe) { 1336 irdma_qp_push_wqe(&qp->qp_uk, wqe, IRDMA_QP_WQE_MIN_QUANTA, 1337 wqe_idx, post_sq); 1338 } else { 1339 if (post_sq) 1340 irdma_uk_qp_post_wr(&qp->qp_uk); 1341 } 1342 1343 return 0; 1344 } 1345 1346 /** 1347 * irdma_sc_gen_rts_ae - request AE generated after RTS 1348 * @qp: sc qp struct 1349 */ 1350 static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp) 1351 { 1352 __le64 *wqe; 1353 u64 hdr; 1354 struct irdma_qp_uk *qp_uk; 1355 1356 qp_uk = &qp->qp_uk; 1357 1358 wqe = qp_uk->sq_base[1].elem; 1359 1360 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | 1361 FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | 1362 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1363 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1364 1365 set_64bit_val(wqe, 24, hdr); 1366 print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET, 1367 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1368 1369 wqe = qp_uk->sq_base[2].elem; 1370 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) | 1371 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1372 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1373 1374 set_64bit_val(wqe, 24, hdr); 1375 print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8, 1376 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1377 } 1378 1379 /** 1380 * irdma_sc_send_lsmm - send last streaming mode message 1381 * @qp: sc qp struct 1382 * @lsmm_buf: buffer with lsmm message 1383 * @size: size of lsmm buffer 1384 * @stag: stag of lsmm buffer 1385 */ 1386 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, 1387 irdma_stag stag) 1388 { 1389 __le64 *wqe; 1390 u64 hdr; 1391 struct irdma_qp_uk *qp_uk; 1392 1393 qp_uk = &qp->qp_uk; 1394 wqe = qp_uk->sq_base->elem; 1395 1396 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); 1397 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1398 set_64bit_val(wqe, 8, 1399 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) | 1400 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag)); 1401 } else { 1402 set_64bit_val(wqe, 8, 1403 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) | 1404 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) | 1405 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1406 } 1407 set_64bit_val(wqe, 16, 0); 1408 1409 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) | 1410 FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) | 1411 FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) | 1412 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1413 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1414 1415 set_64bit_val(wqe, 24, hdr); 1416 1417 print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8, 1418 wqe, IRDMA_QP_WQE_MIN_SIZE, false); 1419 1420 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1421 irdma_sc_gen_rts_ae(qp); 1422 } 1423 1424 /** 1425 * irdma_sc_send_rtt - send last read0 or write0 1426 * @qp: sc qp struct 1427 * @read: Do read0 or write0 1428 */ 1429 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read) 1430 { 1431 __le64 *wqe; 1432 u64 hdr; 1433 struct irdma_qp_uk *qp_uk; 1434 1435 qp_uk = &qp->qp_uk; 1436 wqe = qp_uk->sq_base->elem; 1437 1438 set_64bit_val(wqe, 0, 0); 1439 set_64bit_val(wqe, 16, 0); 1440 if (read) { 1441 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1442 set_64bit_val(wqe, 8, 1443 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd)); 1444 } else { 1445 set_64bit_val(wqe, 8, 1446 (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1447 } 1448 hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) | 1449 FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) | 1450 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1451 1452 } else { 1453 if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { 1454 set_64bit_val(wqe, 8, 0); 1455 } else { 1456 set_64bit_val(wqe, 8, 1457 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); 1458 } 1459 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) | 1460 FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); 1461 } 1462 1463 dma_wmb(); /* make sure WQE is written before valid bit is set */ 1464 1465 set_64bit_val(wqe, 24, hdr); 1466 1467 print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 1468 IRDMA_QP_WQE_MIN_SIZE, false); 1469 1470 if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) 1471 irdma_sc_gen_rts_ae(qp); 1472 } 1473 1474 /** 1475 * irdma_iwarp_opcode - determine if incoming is rdma layer 1476 * @info: aeq info for the packet 1477 * @pkt: packet for error 1478 */ 1479 static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt) 1480 { 1481 __be16 *mpa; 1482 u32 opcode = 0xffffffff; 1483 1484 if (info->q2_data_written) { 1485 mpa = (__be16 *)pkt; 1486 opcode = ntohs(mpa[1]) & 0xf; 1487 } 1488 1489 return opcode; 1490 } 1491 1492 /** 1493 * irdma_locate_mpa - return pointer to mpa in the pkt 1494 * @pkt: packet with data 1495 */ 1496 static u8 *irdma_locate_mpa(u8 *pkt) 1497 { 1498 /* skip over ethernet header */ 1499 pkt += IRDMA_MAC_HLEN; 1500 1501 /* Skip over IP and TCP headers */ 1502 pkt += 4 * (pkt[0] & 0x0f); 1503 pkt += 4 * ((pkt[12] >> 4) & 0x0f); 1504 1505 return pkt; 1506 } 1507 1508 /** 1509 * irdma_bld_termhdr_ctrl - setup terminate hdr control fields 1510 * @qp: sc qp ptr for pkt 1511 * @hdr: term hdr 1512 * @opcode: flush opcode for termhdr 1513 * @layer_etype: error layer + error type 1514 * @err: error cod ein the header 1515 */ 1516 static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp, 1517 struct irdma_terminate_hdr *hdr, 1518 enum irdma_flush_opcode opcode, 1519 u8 layer_etype, u8 err) 1520 { 1521 qp->flush_code = opcode; 1522 hdr->layer_etype = layer_etype; 1523 hdr->error_code = err; 1524 } 1525 1526 /** 1527 * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr 1528 * @pkt: ptr to mpa in offending pkt 1529 * @hdr: term hdr 1530 * @copy_len: offending pkt length to be copied to term hdr 1531 * @is_tagged: DDP tagged or untagged 1532 */ 1533 static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr, 1534 int *copy_len, u8 *is_tagged) 1535 { 1536 u16 ddp_seg_len; 1537 1538 ddp_seg_len = ntohs(*(__be16 *)pkt); 1539 if (ddp_seg_len) { 1540 *copy_len = 2; 1541 hdr->hdrct = DDP_LEN_FLAG; 1542 if (pkt[2] & 0x80) { 1543 *is_tagged = 1; 1544 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { 1545 *copy_len += TERM_DDP_LEN_TAGGED; 1546 hdr->hdrct |= DDP_HDR_FLAG; 1547 } 1548 } else { 1549 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { 1550 *copy_len += TERM_DDP_LEN_UNTAGGED; 1551 hdr->hdrct |= DDP_HDR_FLAG; 1552 } 1553 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) && 1554 ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) { 1555 *copy_len += TERM_RDMA_LEN; 1556 hdr->hdrct |= RDMA_HDR_FLAG; 1557 } 1558 } 1559 } 1560 } 1561 1562 /** 1563 * irdma_bld_terminate_hdr - build terminate message header 1564 * @qp: qp associated with received terminate AE 1565 * @info: the struct contiaing AE information 1566 */ 1567 static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp, 1568 struct irdma_aeqe_info *info) 1569 { 1570 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1571 int copy_len = 0; 1572 u8 is_tagged = 0; 1573 u32 opcode; 1574 struct irdma_terminate_hdr *termhdr; 1575 1576 termhdr = (struct irdma_terminate_hdr *)qp->q2_buf; 1577 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); 1578 1579 if (info->q2_data_written) { 1580 pkt = irdma_locate_mpa(pkt); 1581 irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged); 1582 } 1583 1584 opcode = irdma_iwarp_opcode(info, pkt); 1585 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 1586 qp->sq_flush_code = info->sq; 1587 qp->rq_flush_code = info->rq; 1588 1589 switch (info->ae_id) { 1590 case IRDMA_AE_AMP_UNALLOCATED_STAG: 1591 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1592 if (opcode == IRDMA_OP_TYPE_RDMA_WRITE) 1593 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1594 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1595 DDP_TAGGED_INV_STAG); 1596 else 1597 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1598 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1599 RDMAP_INV_STAG); 1600 break; 1601 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 1602 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1603 if (info->q2_data_written) 1604 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1605 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1606 DDP_TAGGED_BOUNDS); 1607 else 1608 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1609 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1610 RDMAP_INV_BOUNDS); 1611 break; 1612 case IRDMA_AE_AMP_BAD_PD: 1613 switch (opcode) { 1614 case IRDMA_OP_TYPE_RDMA_WRITE: 1615 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, 1616 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1617 DDP_TAGGED_UNASSOC_STAG); 1618 break; 1619 case IRDMA_OP_TYPE_SEND_INV: 1620 case IRDMA_OP_TYPE_SEND_SOL_INV: 1621 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1622 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1623 RDMAP_CANT_INV_STAG); 1624 break; 1625 default: 1626 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1627 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1628 RDMAP_UNASSOC_STAG); 1629 } 1630 break; 1631 case IRDMA_AE_AMP_INVALID_STAG: 1632 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1633 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1634 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1635 RDMAP_INV_STAG); 1636 break; 1637 case IRDMA_AE_AMP_BAD_QP: 1638 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR, 1639 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1640 DDP_UNTAGGED_INV_QN); 1641 break; 1642 case IRDMA_AE_AMP_BAD_STAG_KEY: 1643 case IRDMA_AE_AMP_BAD_STAG_INDEX: 1644 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1645 switch (opcode) { 1646 case IRDMA_OP_TYPE_SEND_INV: 1647 case IRDMA_OP_TYPE_SEND_SOL_INV: 1648 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 1649 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1650 RDMAP_CANT_INV_STAG); 1651 break; 1652 default: 1653 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1654 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1655 RDMAP_INV_STAG); 1656 } 1657 break; 1658 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 1659 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 1660 case IRDMA_AE_PRIV_OPERATION_DENIED: 1661 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1662 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1663 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1664 RDMAP_ACCESS); 1665 break; 1666 case IRDMA_AE_AMP_TO_WRAP: 1667 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1668 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, 1669 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, 1670 RDMAP_TO_WRAP); 1671 break; 1672 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 1673 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1674 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); 1675 break; 1676 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 1677 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 1678 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 1679 DDP_CATASTROPHIC_LOCAL); 1680 break; 1681 case IRDMA_AE_LCE_QP_CATASTROPHIC: 1682 case IRDMA_AE_DDP_NO_L_BIT: 1683 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 1684 (LAYER_DDP << 4) | DDP_CATASTROPHIC, 1685 DDP_CATASTROPHIC_LOCAL); 1686 break; 1687 case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN: 1688 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1689 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1690 DDP_UNTAGGED_INV_MSN_RANGE); 1691 break; 1692 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 1693 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 1694 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, 1695 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1696 DDP_UNTAGGED_INV_TOO_LONG); 1697 break; 1698 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 1699 if (is_tagged) 1700 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1701 (LAYER_DDP << 4) | DDP_TAGGED_BUF, 1702 DDP_TAGGED_INV_DDP_VER); 1703 else 1704 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1705 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1706 DDP_UNTAGGED_INV_DDP_VER); 1707 break; 1708 case IRDMA_AE_DDP_UBE_INVALID_MO: 1709 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1710 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1711 DDP_UNTAGGED_INV_MO); 1712 break; 1713 case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: 1714 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, 1715 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1716 DDP_UNTAGGED_INV_MSN_NO_BUF); 1717 break; 1718 case IRDMA_AE_DDP_UBE_INVALID_QN: 1719 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1720 (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, 1721 DDP_UNTAGGED_INV_QN); 1722 break; 1723 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 1724 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, 1725 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1726 RDMAP_INV_RDMAP_VER); 1727 break; 1728 default: 1729 irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, 1730 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, 1731 RDMAP_UNSPECIFIED); 1732 break; 1733 } 1734 1735 if (copy_len) 1736 memcpy(termhdr + 1, pkt, copy_len); 1737 1738 return sizeof(struct irdma_terminate_hdr) + copy_len; 1739 } 1740 1741 /** 1742 * irdma_terminate_send_fin() - Send fin for terminate message 1743 * @qp: qp associated with received terminate AE 1744 */ 1745 void irdma_terminate_send_fin(struct irdma_sc_qp *qp) 1746 { 1747 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 1748 IRDMAQP_TERM_SEND_FIN_ONLY, 0); 1749 } 1750 1751 /** 1752 * irdma_terminate_connection() - Bad AE and send terminate to remote QP 1753 * @qp: qp associated with received terminate AE 1754 * @info: the struct contiaing AE information 1755 */ 1756 void irdma_terminate_connection(struct irdma_sc_qp *qp, 1757 struct irdma_aeqe_info *info) 1758 { 1759 u8 termlen = 0; 1760 1761 if (qp->term_flags & IRDMA_TERM_SENT) 1762 return; 1763 1764 termlen = irdma_bld_terminate_hdr(qp, info); 1765 irdma_terminate_start_timer(qp); 1766 qp->term_flags |= IRDMA_TERM_SENT; 1767 irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, 1768 IRDMAQP_TERM_SEND_TERM_ONLY, termlen); 1769 } 1770 1771 /** 1772 * irdma_terminate_received - handle terminate received AE 1773 * @qp: qp associated with received terminate AE 1774 * @info: the struct contiaing AE information 1775 */ 1776 void irdma_terminate_received(struct irdma_sc_qp *qp, 1777 struct irdma_aeqe_info *info) 1778 { 1779 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; 1780 __be32 *mpa; 1781 u8 ddp_ctl; 1782 u8 rdma_ctl; 1783 u16 aeq_id = 0; 1784 struct irdma_terminate_hdr *termhdr; 1785 1786 mpa = (__be32 *)irdma_locate_mpa(pkt); 1787 if (info->q2_data_written) { 1788 /* did not validate the frame - do it now */ 1789 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; 1790 rdma_ctl = ntohl(mpa[0]) & 0xff; 1791 if ((ddp_ctl & 0xc0) != 0x40) 1792 aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC; 1793 else if ((ddp_ctl & 0x03) != 1) 1794 aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION; 1795 else if (ntohl(mpa[2]) != 2) 1796 aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN; 1797 else if (ntohl(mpa[3]) != 1) 1798 aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN; 1799 else if (ntohl(mpa[4]) != 0) 1800 aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO; 1801 else if ((rdma_ctl & 0xc0) != 0x40) 1802 aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; 1803 1804 info->ae_id = aeq_id; 1805 if (info->ae_id) { 1806 /* Bad terminate recvd - send back a terminate */ 1807 irdma_terminate_connection(qp, info); 1808 return; 1809 } 1810 } 1811 1812 qp->term_flags |= IRDMA_TERM_RCVD; 1813 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 1814 termhdr = (struct irdma_terminate_hdr *)&mpa[5]; 1815 if (termhdr->layer_etype == RDMAP_REMOTE_PROT || 1816 termhdr->layer_etype == RDMAP_REMOTE_OP) { 1817 irdma_terminate_done(qp, 0); 1818 } else { 1819 irdma_terminate_start_timer(qp); 1820 irdma_terminate_send_fin(qp); 1821 } 1822 } 1823 1824 static enum irdma_status_code irdma_null_ws_add(struct irdma_sc_vsi *vsi, 1825 u8 user_pri) 1826 { 1827 return 0; 1828 } 1829 1830 static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) 1831 { 1832 /* do nothing */ 1833 } 1834 1835 static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi) 1836 { 1837 /* do nothing */ 1838 } 1839 1840 /** 1841 * irdma_sc_vsi_init - Init the vsi structure 1842 * @vsi: pointer to vsi structure to initialize 1843 * @info: the info used to initialize the vsi struct 1844 */ 1845 void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, 1846 struct irdma_vsi_init_info *info) 1847 { 1848 struct irdma_l2params *l2p; 1849 int i; 1850 1851 vsi->dev = info->dev; 1852 vsi->back_vsi = info->back_vsi; 1853 vsi->register_qset = info->register_qset; 1854 vsi->unregister_qset = info->unregister_qset; 1855 vsi->mtu = info->params->mtu; 1856 vsi->exception_lan_q = info->exception_lan_q; 1857 vsi->vsi_idx = info->pf_data_vsi_num; 1858 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1859 vsi->fcn_id = info->dev->hmc_fn_id; 1860 1861 l2p = info->params; 1862 vsi->qos_rel_bw = l2p->vsi_rel_bw; 1863 vsi->qos_prio_type = l2p->vsi_prio_type; 1864 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { 1865 if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1866 vsi->qos[i].qs_handle = l2p->qs_handle_list[i]; 1867 vsi->qos[i].traffic_class = info->params->up2tc[i]; 1868 vsi->qos[i].rel_bw = 1869 l2p->tc_info[vsi->qos[i].traffic_class].rel_bw; 1870 vsi->qos[i].prio_type = 1871 l2p->tc_info[vsi->qos[i].traffic_class].prio_type; 1872 vsi->qos[i].valid = false; 1873 mutex_init(&vsi->qos[i].qos_mutex); 1874 INIT_LIST_HEAD(&vsi->qos[i].qplist); 1875 } 1876 if (vsi->register_qset) { 1877 vsi->dev->ws_add = irdma_ws_add; 1878 vsi->dev->ws_remove = irdma_ws_remove; 1879 vsi->dev->ws_reset = irdma_ws_reset; 1880 } else { 1881 vsi->dev->ws_add = irdma_null_ws_add; 1882 vsi->dev->ws_remove = irdma_null_ws_remove; 1883 vsi->dev->ws_reset = irdma_null_ws_reset; 1884 } 1885 } 1886 1887 /** 1888 * irdma_get_fcn_id - Return the function id 1889 * @vsi: pointer to the vsi 1890 */ 1891 static u8 irdma_get_fcn_id(struct irdma_sc_vsi *vsi) 1892 { 1893 struct irdma_stats_inst_info stats_info = {}; 1894 struct irdma_sc_dev *dev = vsi->dev; 1895 u8 fcn_id = IRDMA_INVALID_FCN_ID; 1896 u8 start_idx, max_stats, i; 1897 1898 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 1899 if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE, 1900 &stats_info)) 1901 return stats_info.stats_idx; 1902 } 1903 1904 start_idx = 1; 1905 max_stats = 16; 1906 for (i = start_idx; i < max_stats; i++) 1907 if (!dev->fcn_id_array[i]) { 1908 fcn_id = i; 1909 dev->fcn_id_array[i] = true; 1910 break; 1911 } 1912 1913 return fcn_id; 1914 } 1915 1916 /** 1917 * irdma_vsi_stats_init - Initialize the vsi statistics 1918 * @vsi: pointer to the vsi structure 1919 * @info: The info structure used for initialization 1920 */ 1921 enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, 1922 struct irdma_vsi_stats_info *info) 1923 { 1924 u8 fcn_id = info->fcn_id; 1925 struct irdma_dma_mem *stats_buff_mem; 1926 1927 vsi->pestat = info->pestat; 1928 vsi->pestat->hw = vsi->dev->hw; 1929 vsi->pestat->vsi = vsi; 1930 stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem; 1931 stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1); 1932 stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device, 1933 stats_buff_mem->size, 1934 &stats_buff_mem->pa, 1935 GFP_KERNEL); 1936 if (!stats_buff_mem->va) 1937 return IRDMA_ERR_NO_MEMORY; 1938 1939 vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va; 1940 vsi->pestat->gather_info.last_gather_stats_va = 1941 (void *)((uintptr_t)stats_buff_mem->va + 1942 IRDMA_GATHER_STATS_BUF_SIZE); 1943 1944 irdma_hw_stats_start_timer(vsi); 1945 if (info->alloc_fcn_id) 1946 fcn_id = irdma_get_fcn_id(vsi); 1947 if (fcn_id == IRDMA_INVALID_FCN_ID) 1948 goto stats_error; 1949 1950 vsi->stats_fcn_id_alloc = info->alloc_fcn_id; 1951 vsi->fcn_id = fcn_id; 1952 if (info->alloc_fcn_id) { 1953 vsi->pestat->gather_info.use_stats_inst = true; 1954 vsi->pestat->gather_info.stats_inst_index = fcn_id; 1955 } 1956 1957 return 0; 1958 1959 stats_error: 1960 dma_free_coherent(vsi->pestat->hw->device, stats_buff_mem->size, 1961 stats_buff_mem->va, stats_buff_mem->pa); 1962 stats_buff_mem->va = NULL; 1963 1964 return IRDMA_ERR_CQP_COMPL_ERROR; 1965 } 1966 1967 /** 1968 * irdma_vsi_stats_free - Free the vsi stats 1969 * @vsi: pointer to the vsi structure 1970 */ 1971 void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi) 1972 { 1973 struct irdma_stats_inst_info stats_info = {}; 1974 u8 fcn_id = vsi->fcn_id; 1975 struct irdma_sc_dev *dev = vsi->dev; 1976 1977 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 1978 if (vsi->stats_fcn_id_alloc) { 1979 stats_info.stats_idx = vsi->fcn_id; 1980 irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE, 1981 &stats_info); 1982 } 1983 } else { 1984 if (vsi->stats_fcn_id_alloc && 1985 fcn_id < vsi->dev->hw_attrs.max_stat_inst) 1986 vsi->dev->fcn_id_array[fcn_id] = false; 1987 } 1988 1989 if (!vsi->pestat) 1990 return; 1991 irdma_hw_stats_stop_timer(vsi); 1992 dma_free_coherent(vsi->pestat->hw->device, 1993 vsi->pestat->gather_info.stats_buff_mem.size, 1994 vsi->pestat->gather_info.stats_buff_mem.va, 1995 vsi->pestat->gather_info.stats_buff_mem.pa); 1996 vsi->pestat->gather_info.stats_buff_mem.va = NULL; 1997 } 1998 1999 /** 2000 * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size 2001 * @wqsize: size of the wq (sq, rq) to encoded_size 2002 * @queue_type: queue type selected for the calculation algorithm 2003 */ 2004 u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) 2005 { 2006 u8 encoded_size = 0; 2007 2008 /* cqp sq's hw coded value starts from 1 for size of 4 2009 * while it starts from 0 for qp' wq's. 2010 */ 2011 if (queue_type == IRDMA_QUEUE_TYPE_CQP) 2012 encoded_size = 1; 2013 wqsize >>= 2; 2014 while (wqsize >>= 1) 2015 encoded_size++; 2016 2017 return encoded_size; 2018 } 2019 2020 /** 2021 * irdma_sc_gather_stats - collect the statistics 2022 * @cqp: struct for cqp hw 2023 * @info: gather stats info structure 2024 * @scratch: u64 saved to be used during cqp completion 2025 */ 2026 static enum irdma_status_code 2027 irdma_sc_gather_stats(struct irdma_sc_cqp *cqp, 2028 struct irdma_stats_gather_info *info, u64 scratch) 2029 { 2030 __le64 *wqe; 2031 u64 temp; 2032 2033 if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE) 2034 return IRDMA_ERR_BUF_TOO_SHORT; 2035 2036 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2037 if (!wqe) 2038 return IRDMA_ERR_RING_FULL; 2039 2040 set_64bit_val(wqe, 40, 2041 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index)); 2042 set_64bit_val(wqe, 32, info->stats_buff_mem.pa); 2043 2044 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2045 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) | 2046 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, 2047 info->stats_inst_index) | 2048 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2049 info->use_hmc_fcn_index) | 2050 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS); 2051 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2052 2053 set_64bit_val(wqe, 24, temp); 2054 2055 print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET, 2056 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2057 2058 irdma_sc_cqp_post_sq(cqp); 2059 ibdev_dbg(to_ibdev(cqp->dev), 2060 "STATS: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 2061 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 2062 2063 return 0; 2064 } 2065 2066 /** 2067 * irdma_sc_manage_stats_inst - allocate or free stats instance 2068 * @cqp: struct for cqp hw 2069 * @info: stats info structure 2070 * @alloc: alloc vs. delete flag 2071 * @scratch: u64 saved to be used during cqp completion 2072 */ 2073 static enum irdma_status_code 2074 irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp, 2075 struct irdma_stats_inst_info *info, bool alloc, 2076 u64 scratch) 2077 { 2078 __le64 *wqe; 2079 u64 temp; 2080 2081 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2082 if (!wqe) 2083 return IRDMA_ERR_RING_FULL; 2084 2085 set_64bit_val(wqe, 40, 2086 FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id)); 2087 temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | 2088 FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) | 2089 FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, 2090 info->use_hmc_fcn_index) | 2091 FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) | 2092 FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS); 2093 2094 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2095 2096 set_64bit_val(wqe, 24, temp); 2097 2098 print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16, 2099 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2100 2101 irdma_sc_cqp_post_sq(cqp); 2102 return 0; 2103 } 2104 2105 /** 2106 * irdma_sc_set_up_map - set the up map table 2107 * @cqp: struct for cqp hw 2108 * @info: User priority map info 2109 * @scratch: u64 saved to be used during cqp completion 2110 */ 2111 static enum irdma_status_code irdma_sc_set_up_map(struct irdma_sc_cqp *cqp, 2112 struct irdma_up_info *info, 2113 u64 scratch) 2114 { 2115 __le64 *wqe; 2116 u64 temp = 0; 2117 int i; 2118 2119 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2120 if (!wqe) 2121 return IRDMA_ERR_RING_FULL; 2122 2123 for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) 2124 temp |= (u64)info->map[i] << (i * 8); 2125 2126 set_64bit_val(wqe, 0, temp); 2127 set_64bit_val(wqe, 40, 2128 FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) | 2129 FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx)); 2130 2131 temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) | 2132 FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) | 2133 FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE, 2134 info->use_cnp_up_override) | 2135 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP); 2136 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2137 2138 set_64bit_val(wqe, 24, temp); 2139 2140 print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, 2141 IRDMA_CQP_WQE_SIZE * 8, false); 2142 irdma_sc_cqp_post_sq(cqp); 2143 2144 return 0; 2145 } 2146 2147 /** 2148 * irdma_sc_manage_ws_node - create/modify/destroy WS node 2149 * @cqp: struct for cqp hw 2150 * @info: node info structure 2151 * @node_op: 0 for add 1 for modify, 2 for delete 2152 * @scratch: u64 saved to be used during cqp completion 2153 */ 2154 static enum irdma_status_code 2155 irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp, 2156 struct irdma_ws_node_info *info, 2157 enum irdma_ws_node_op node_op, u64 scratch) 2158 { 2159 __le64 *wqe; 2160 u64 temp = 0; 2161 2162 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2163 if (!wqe) 2164 return IRDMA_ERR_RING_FULL; 2165 2166 set_64bit_val(wqe, 32, 2167 FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) | 2168 FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight)); 2169 2170 temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) | 2171 FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) | 2172 FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) | 2173 FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) | 2174 FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) | 2175 FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) | 2176 FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) | 2177 FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) | 2178 FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id); 2179 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2180 2181 set_64bit_val(wqe, 24, temp); 2182 2183 print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, 2184 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2185 irdma_sc_cqp_post_sq(cqp); 2186 2187 return 0; 2188 } 2189 2190 /** 2191 * irdma_sc_qp_flush_wqes - flush qp's wqe 2192 * @qp: sc qp 2193 * @info: dlush information 2194 * @scratch: u64 saved to be used during cqp completion 2195 * @post_sq: flag for cqp db to ring 2196 */ 2197 enum irdma_status_code irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, 2198 struct irdma_qp_flush_info *info, 2199 u64 scratch, bool post_sq) 2200 { 2201 u64 temp = 0; 2202 __le64 *wqe; 2203 struct irdma_sc_cqp *cqp; 2204 u64 hdr; 2205 bool flush_sq = false, flush_rq = false; 2206 2207 if (info->rq && !qp->flush_rq) 2208 flush_rq = true; 2209 if (info->sq && !qp->flush_sq) 2210 flush_sq = true; 2211 qp->flush_sq |= flush_sq; 2212 qp->flush_rq |= flush_rq; 2213 2214 if (!flush_sq && !flush_rq) { 2215 ibdev_dbg(to_ibdev(qp->dev), 2216 "CQP: Additional flush request ignored for qp %x\n", 2217 qp->qp_uk.qp_id); 2218 return IRDMA_ERR_FLUSHED_Q; 2219 } 2220 2221 cqp = qp->pd->dev->cqp; 2222 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2223 if (!wqe) 2224 return IRDMA_ERR_RING_FULL; 2225 2226 if (info->userflushcode) { 2227 if (flush_rq) 2228 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR, 2229 info->rq_minor_code) | 2230 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, 2231 info->rq_major_code); 2232 if (flush_sq) 2233 temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR, 2234 info->sq_minor_code) | 2235 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, 2236 info->sq_major_code); 2237 } 2238 set_64bit_val(wqe, 16, temp); 2239 2240 temp = (info->generate_ae) ? 2241 info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2242 info->ae_src) : 0; 2243 set_64bit_val(wqe, 8, temp); 2244 2245 hdr = qp->qp_uk.qp_id | 2246 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) | 2247 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) | 2248 FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) | 2249 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) | 2250 FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) | 2251 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2252 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2253 2254 set_64bit_val(wqe, 24, hdr); 2255 2256 print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8, 2257 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2258 if (post_sq) 2259 irdma_sc_cqp_post_sq(cqp); 2260 2261 return 0; 2262 } 2263 2264 /** 2265 * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP 2266 * @qp: sc qp 2267 * @info: gen ae information 2268 * @scratch: u64 saved to be used during cqp completion 2269 * @post_sq: flag for cqp db to ring 2270 */ 2271 static enum irdma_status_code irdma_sc_gen_ae(struct irdma_sc_qp *qp, 2272 struct irdma_gen_ae_info *info, 2273 u64 scratch, bool post_sq) 2274 { 2275 u64 temp; 2276 __le64 *wqe; 2277 struct irdma_sc_cqp *cqp; 2278 u64 hdr; 2279 2280 cqp = qp->pd->dev->cqp; 2281 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2282 if (!wqe) 2283 return IRDMA_ERR_RING_FULL; 2284 2285 temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, 2286 info->ae_src); 2287 set_64bit_val(wqe, 8, temp); 2288 2289 hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE, 2290 IRDMA_CQP_OP_GEN_AE) | 2291 FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) | 2292 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2293 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2294 2295 set_64bit_val(wqe, 24, hdr); 2296 2297 print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2298 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2299 if (post_sq) 2300 irdma_sc_cqp_post_sq(cqp); 2301 2302 return 0; 2303 } 2304 2305 /*** irdma_sc_qp_upload_context - upload qp's context 2306 * @dev: sc device struct 2307 * @info: upload context info ptr for return 2308 * @scratch: u64 saved to be used during cqp completion 2309 * @post_sq: flag for cqp db to ring 2310 */ 2311 static enum irdma_status_code 2312 irdma_sc_qp_upload_context(struct irdma_sc_dev *dev, 2313 struct irdma_upload_context_info *info, u64 scratch, 2314 bool post_sq) 2315 { 2316 __le64 *wqe; 2317 struct irdma_sc_cqp *cqp; 2318 u64 hdr; 2319 2320 cqp = dev->cqp; 2321 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2322 if (!wqe) 2323 return IRDMA_ERR_RING_FULL; 2324 2325 set_64bit_val(wqe, 16, info->buf_pa); 2326 2327 hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) | 2328 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) | 2329 FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) | 2330 FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) | 2331 FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) | 2332 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2333 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2334 2335 set_64bit_val(wqe, 24, hdr); 2336 2337 print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16, 2338 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2339 if (post_sq) 2340 irdma_sc_cqp_post_sq(cqp); 2341 2342 return 0; 2343 } 2344 2345 /** 2346 * irdma_sc_manage_push_page - Handle push page 2347 * @cqp: struct for cqp hw 2348 * @info: push page info 2349 * @scratch: u64 saved to be used during cqp completion 2350 * @post_sq: flag for cqp db to ring 2351 */ 2352 static enum irdma_status_code 2353 irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp, 2354 struct irdma_cqp_manage_push_page_info *info, 2355 u64 scratch, bool post_sq) 2356 { 2357 __le64 *wqe; 2358 u64 hdr; 2359 2360 if (info->free_page && 2361 info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages) 2362 return IRDMA_ERR_INVALID_PUSH_PAGE_INDEX; 2363 2364 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2365 if (!wqe) 2366 return IRDMA_ERR_RING_FULL; 2367 2368 set_64bit_val(wqe, 16, info->qs_handle); 2369 hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) | 2370 FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) | 2371 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) | 2372 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 2373 FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page); 2374 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2375 2376 set_64bit_val(wqe, 24, hdr); 2377 2378 print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET, 2379 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2380 if (post_sq) 2381 irdma_sc_cqp_post_sq(cqp); 2382 2383 return 0; 2384 } 2385 2386 /** 2387 * irdma_sc_suspend_qp - suspend qp for param change 2388 * @cqp: struct for cqp hw 2389 * @qp: sc qp struct 2390 * @scratch: u64 saved to be used during cqp completion 2391 */ 2392 static enum irdma_status_code irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, 2393 struct irdma_sc_qp *qp, 2394 u64 scratch) 2395 { 2396 u64 hdr; 2397 __le64 *wqe; 2398 2399 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2400 if (!wqe) 2401 return IRDMA_ERR_RING_FULL; 2402 2403 hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) | 2404 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) | 2405 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2406 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2407 2408 set_64bit_val(wqe, 24, hdr); 2409 2410 print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2411 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2412 irdma_sc_cqp_post_sq(cqp); 2413 2414 return 0; 2415 } 2416 2417 /** 2418 * irdma_sc_resume_qp - resume qp after suspend 2419 * @cqp: struct for cqp hw 2420 * @qp: sc qp struct 2421 * @scratch: u64 saved to be used during cqp completion 2422 */ 2423 static enum irdma_status_code irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, 2424 struct irdma_sc_qp *qp, 2425 u64 scratch) 2426 { 2427 u64 hdr; 2428 __le64 *wqe; 2429 2430 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2431 if (!wqe) 2432 return IRDMA_ERR_RING_FULL; 2433 2434 set_64bit_val(wqe, 16, 2435 FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle)); 2436 2437 hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) | 2438 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) | 2439 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2440 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2441 2442 set_64bit_val(wqe, 24, hdr); 2443 2444 print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, 2445 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2446 irdma_sc_cqp_post_sq(cqp); 2447 2448 return 0; 2449 } 2450 2451 /** 2452 * irdma_sc_cq_ack - acknowledge completion q 2453 * @cq: cq struct 2454 */ 2455 static inline void irdma_sc_cq_ack(struct irdma_sc_cq *cq) 2456 { 2457 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db); 2458 } 2459 2460 /** 2461 * irdma_sc_cq_init - initialize completion q 2462 * @cq: cq struct 2463 * @info: cq initialization info 2464 */ 2465 enum irdma_status_code irdma_sc_cq_init(struct irdma_sc_cq *cq, 2466 struct irdma_cq_init_info *info) 2467 { 2468 u32 pble_obj_cnt; 2469 2470 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2471 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 2472 return IRDMA_ERR_INVALID_PBLE_INDEX; 2473 2474 cq->cq_pa = info->cq_base_pa; 2475 cq->dev = info->dev; 2476 cq->ceq_id = info->ceq_id; 2477 info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db; 2478 info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db; 2479 irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info); 2480 2481 cq->virtual_map = info->virtual_map; 2482 cq->pbl_chunk_size = info->pbl_chunk_size; 2483 cq->ceqe_mask = info->ceqe_mask; 2484 cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP; 2485 cq->shadow_area_pa = info->shadow_area_pa; 2486 cq->shadow_read_threshold = info->shadow_read_threshold; 2487 cq->ceq_id_valid = info->ceq_id_valid; 2488 cq->tph_en = info->tph_en; 2489 cq->tph_val = info->tph_val; 2490 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2491 cq->vsi = info->vsi; 2492 2493 return 0; 2494 } 2495 2496 /** 2497 * irdma_sc_cq_create - create completion q 2498 * @cq: cq struct 2499 * @scratch: u64 saved to be used during cqp completion 2500 * @check_overflow: flag for overflow check 2501 * @post_sq: flag for cqp db to ring 2502 */ 2503 static enum irdma_status_code irdma_sc_cq_create(struct irdma_sc_cq *cq, 2504 u64 scratch, 2505 bool check_overflow, 2506 bool post_sq) 2507 { 2508 __le64 *wqe; 2509 struct irdma_sc_cqp *cqp; 2510 u64 hdr; 2511 struct irdma_sc_ceq *ceq; 2512 enum irdma_status_code ret_code = 0; 2513 2514 cqp = cq->dev->cqp; 2515 if (cq->cq_uk.cq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt - 1)) 2516 return IRDMA_ERR_INVALID_CQ_ID; 2517 2518 if (cq->ceq_id > (cq->dev->hmc_fpm_misc.max_ceqs - 1)) 2519 return IRDMA_ERR_INVALID_CEQ_ID; 2520 2521 ceq = cq->dev->ceq[cq->ceq_id]; 2522 if (ceq && ceq->reg_cq) 2523 ret_code = irdma_sc_add_cq_ctx(ceq, cq); 2524 2525 if (ret_code) 2526 return ret_code; 2527 2528 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2529 if (!wqe) { 2530 if (ceq && ceq->reg_cq) 2531 irdma_sc_remove_cq_ctx(ceq, cq); 2532 return IRDMA_ERR_RING_FULL; 2533 } 2534 2535 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2536 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2537 set_64bit_val(wqe, 16, 2538 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); 2539 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa)); 2540 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2541 set_64bit_val(wqe, 48, 2542 FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0))); 2543 set_64bit_val(wqe, 56, 2544 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2545 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2546 2547 hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) | 2548 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2549 IRDMA_CQPSQ_CQ_CEQID) | 2550 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | 2551 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2552 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) | 2553 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2554 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2555 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2556 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2557 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2558 cq->cq_uk.avoid_mem_cflct) | 2559 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2560 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2561 2562 set_64bit_val(wqe, 24, hdr); 2563 2564 print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 2565 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2566 if (post_sq) 2567 irdma_sc_cqp_post_sq(cqp); 2568 2569 return 0; 2570 } 2571 2572 /** 2573 * irdma_sc_cq_destroy - destroy completion q 2574 * @cq: cq struct 2575 * @scratch: u64 saved to be used during cqp completion 2576 * @post_sq: flag for cqp db to ring 2577 */ 2578 enum irdma_status_code irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, 2579 bool post_sq) 2580 { 2581 struct irdma_sc_cqp *cqp; 2582 __le64 *wqe; 2583 u64 hdr; 2584 struct irdma_sc_ceq *ceq; 2585 2586 cqp = cq->dev->cqp; 2587 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2588 if (!wqe) 2589 return IRDMA_ERR_RING_FULL; 2590 2591 ceq = cq->dev->ceq[cq->ceq_id]; 2592 if (ceq && ceq->reg_cq) 2593 irdma_sc_remove_cq_ctx(ceq, cq); 2594 2595 set_64bit_val(wqe, 0, cq->cq_uk.cq_size); 2596 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2597 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2598 set_64bit_val(wqe, 48, 2599 (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); 2600 2601 hdr = cq->cq_uk.cq_id | 2602 FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), 2603 IRDMA_CQPSQ_CQ_CEQID) | 2604 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 2605 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | 2606 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | 2607 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2608 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | 2609 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2610 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) | 2611 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2612 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2613 2614 set_64bit_val(wqe, 24, hdr); 2615 2616 print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, 2617 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2618 if (post_sq) 2619 irdma_sc_cqp_post_sq(cqp); 2620 2621 return 0; 2622 } 2623 2624 /** 2625 * irdma_sc_cq_resize - set resized cq buffer info 2626 * @cq: resized cq 2627 * @info: resized cq buffer info 2628 */ 2629 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info) 2630 { 2631 cq->virtual_map = info->virtual_map; 2632 cq->cq_pa = info->cq_pa; 2633 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 2634 cq->pbl_chunk_size = info->pbl_chunk_size; 2635 irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size); 2636 } 2637 2638 /** 2639 * irdma_sc_cq_modify - modify a Completion Queue 2640 * @cq: cq struct 2641 * @info: modification info struct 2642 * @scratch: u64 saved to be used during cqp completion 2643 * @post_sq: flag to post to sq 2644 */ 2645 static enum irdma_status_code 2646 irdma_sc_cq_modify(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info, 2647 u64 scratch, bool post_sq) 2648 { 2649 struct irdma_sc_cqp *cqp; 2650 __le64 *wqe; 2651 u64 hdr; 2652 u32 pble_obj_cnt; 2653 2654 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 2655 if (info->cq_resize && info->virtual_map && 2656 info->first_pm_pbl_idx >= pble_obj_cnt) 2657 return IRDMA_ERR_INVALID_PBLE_INDEX; 2658 2659 cqp = cq->dev->cqp; 2660 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 2661 if (!wqe) 2662 return IRDMA_ERR_RING_FULL; 2663 2664 set_64bit_val(wqe, 0, info->cq_size); 2665 set_64bit_val(wqe, 8, (uintptr_t)cq >> 1); 2666 set_64bit_val(wqe, 16, 2667 FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold)); 2668 set_64bit_val(wqe, 32, info->cq_pa); 2669 set_64bit_val(wqe, 40, cq->shadow_area_pa); 2670 set_64bit_val(wqe, 48, info->first_pm_pbl_idx); 2671 set_64bit_val(wqe, 56, 2672 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | 2673 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); 2674 2675 hdr = cq->cq_uk.cq_id | 2676 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) | 2677 FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) | 2678 FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) | 2679 FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) | 2680 FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) | 2681 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | 2682 FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | 2683 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, 2684 cq->cq_uk.avoid_mem_cflct) | 2685 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 2686 dma_wmb(); /* make sure WQE is written before valid bit is set */ 2687 2688 set_64bit_val(wqe, 24, hdr); 2689 2690 print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, 2691 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 2692 if (post_sq) 2693 irdma_sc_cqp_post_sq(cqp); 2694 2695 return 0; 2696 } 2697 2698 /** 2699 * irdma_check_cqp_progress - check cqp processing progress 2700 * @timeout: timeout info struct 2701 * @dev: sc device struct 2702 */ 2703 void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, struct irdma_sc_dev *dev) 2704 { 2705 if (timeout->compl_cqp_cmds != dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]) { 2706 timeout->compl_cqp_cmds = dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]; 2707 timeout->count = 0; 2708 } else { 2709 if (dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS] != 2710 timeout->compl_cqp_cmds) 2711 timeout->count++; 2712 } 2713 } 2714 2715 /** 2716 * irdma_get_cqp_reg_info - get head and tail for cqp using registers 2717 * @cqp: struct for cqp hw 2718 * @val: cqp tail register value 2719 * @tail: wqtail register value 2720 * @error: cqp processing err 2721 */ 2722 static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val, 2723 u32 *tail, u32 *error) 2724 { 2725 *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]); 2726 *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val); 2727 *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val); 2728 } 2729 2730 /** 2731 * irdma_cqp_poll_registers - poll cqp registers 2732 * @cqp: struct for cqp hw 2733 * @tail: wqtail register value 2734 * @count: how many times to try for completion 2735 */ 2736 static enum irdma_status_code irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, 2737 u32 tail, u32 count) 2738 { 2739 u32 i = 0; 2740 u32 newtail, error, val; 2741 2742 while (i++ < count) { 2743 irdma_get_cqp_reg_info(cqp, &val, &newtail, &error); 2744 if (error) { 2745 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 2746 ibdev_dbg(to_ibdev(cqp->dev), 2747 "CQP: CQPERRCODES error_code[x%08X]\n", 2748 error); 2749 return IRDMA_ERR_CQP_COMPL_ERROR; 2750 } 2751 if (newtail != tail) { 2752 /* SUCCESS */ 2753 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 2754 cqp->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]++; 2755 return 0; 2756 } 2757 udelay(cqp->dev->hw_attrs.max_sleep_count); 2758 } 2759 2760 return IRDMA_ERR_TIMEOUT; 2761 } 2762 2763 /** 2764 * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base 2765 * @dev: sc device struct 2766 * @buf: pointer to commit buffer 2767 * @buf_idx: buffer index 2768 * @obj_info: object info pointer 2769 * @rsrc_idx: indexs of memory resource 2770 */ 2771 static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, 2772 u32 buf_idx, struct irdma_hmc_obj_info *obj_info, 2773 u32 rsrc_idx) 2774 { 2775 u64 temp; 2776 2777 get_64bit_val(buf, buf_idx, &temp); 2778 2779 switch (rsrc_idx) { 2780 case IRDMA_HMC_IW_QP: 2781 obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp); 2782 break; 2783 case IRDMA_HMC_IW_CQ: 2784 obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT); 2785 break; 2786 case IRDMA_HMC_IW_APBVT_ENTRY: 2787 obj_info[rsrc_idx].cnt = 1; 2788 break; 2789 default: 2790 obj_info[rsrc_idx].cnt = (u32)temp; 2791 break; 2792 } 2793 2794 obj_info[rsrc_idx].base = (temp >> IRDMA_COMMIT_FPM_BASE_S) * 512; 2795 2796 return temp; 2797 } 2798 2799 /** 2800 * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer 2801 * @dev: pointer to dev struct 2802 * @buf: ptr to fpm commit buffer 2803 * @info: ptr to irdma_hmc_obj_info struct 2804 * @sd: number of SDs for HMC objects 2805 * 2806 * parses fpm commit info and copy base value 2807 * of hmc objects in hmc_info 2808 */ 2809 static void 2810 irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, 2811 struct irdma_hmc_obj_info *info, u32 *sd) 2812 { 2813 u64 size; 2814 u32 i; 2815 u64 max_base = 0; 2816 u32 last_hmc_obj = 0; 2817 2818 irdma_sc_decode_fpm_commit(dev, buf, 0, info, 2819 IRDMA_HMC_IW_QP); 2820 irdma_sc_decode_fpm_commit(dev, buf, 8, info, 2821 IRDMA_HMC_IW_CQ); 2822 /* skiping RSRVD */ 2823 irdma_sc_decode_fpm_commit(dev, buf, 24, info, 2824 IRDMA_HMC_IW_HTE); 2825 irdma_sc_decode_fpm_commit(dev, buf, 32, info, 2826 IRDMA_HMC_IW_ARP); 2827 irdma_sc_decode_fpm_commit(dev, buf, 40, info, 2828 IRDMA_HMC_IW_APBVT_ENTRY); 2829 irdma_sc_decode_fpm_commit(dev, buf, 48, info, 2830 IRDMA_HMC_IW_MR); 2831 irdma_sc_decode_fpm_commit(dev, buf, 56, info, 2832 IRDMA_HMC_IW_XF); 2833 irdma_sc_decode_fpm_commit(dev, buf, 64, info, 2834 IRDMA_HMC_IW_XFFL); 2835 irdma_sc_decode_fpm_commit(dev, buf, 72, info, 2836 IRDMA_HMC_IW_Q1); 2837 irdma_sc_decode_fpm_commit(dev, buf, 80, info, 2838 IRDMA_HMC_IW_Q1FL); 2839 irdma_sc_decode_fpm_commit(dev, buf, 88, info, 2840 IRDMA_HMC_IW_TIMER); 2841 irdma_sc_decode_fpm_commit(dev, buf, 112, info, 2842 IRDMA_HMC_IW_PBLE); 2843 /* skipping RSVD. */ 2844 if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { 2845 irdma_sc_decode_fpm_commit(dev, buf, 96, info, 2846 IRDMA_HMC_IW_FSIMC); 2847 irdma_sc_decode_fpm_commit(dev, buf, 104, info, 2848 IRDMA_HMC_IW_FSIAV); 2849 irdma_sc_decode_fpm_commit(dev, buf, 128, info, 2850 IRDMA_HMC_IW_RRF); 2851 irdma_sc_decode_fpm_commit(dev, buf, 136, info, 2852 IRDMA_HMC_IW_RRFFL); 2853 irdma_sc_decode_fpm_commit(dev, buf, 144, info, 2854 IRDMA_HMC_IW_HDR); 2855 irdma_sc_decode_fpm_commit(dev, buf, 152, info, 2856 IRDMA_HMC_IW_MD); 2857 irdma_sc_decode_fpm_commit(dev, buf, 160, info, 2858 IRDMA_HMC_IW_OOISC); 2859 irdma_sc_decode_fpm_commit(dev, buf, 168, info, 2860 IRDMA_HMC_IW_OOISCFFL); 2861 } 2862 2863 /* searching for the last object in HMC to find the size of the HMC area. */ 2864 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { 2865 if (info[i].base > max_base) { 2866 max_base = info[i].base; 2867 last_hmc_obj = i; 2868 } 2869 } 2870 2871 size = info[last_hmc_obj].cnt * info[last_hmc_obj].size + 2872 info[last_hmc_obj].base; 2873 2874 if (size & 0x1FFFFF) 2875 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ 2876 else 2877 *sd = (u32)(size >> 21); 2878 2879 } 2880 2881 /** 2882 * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size 2883 * @buf: ptr to fpm query buffer 2884 * @buf_idx: index into buf 2885 * @obj_info: ptr to irdma_hmc_obj_info struct 2886 * @rsrc_idx: resource index into info 2887 * 2888 * Decode a 64 bit value from fpm query buffer into max count and size 2889 */ 2890 static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx, 2891 struct irdma_hmc_obj_info *obj_info, 2892 u32 rsrc_idx) 2893 { 2894 u64 temp; 2895 u32 size; 2896 2897 get_64bit_val(buf, buf_idx, &temp); 2898 obj_info[rsrc_idx].max_cnt = (u32)temp; 2899 size = (u32)(temp >> 32); 2900 obj_info[rsrc_idx].size = BIT_ULL(size); 2901 2902 return temp; 2903 } 2904 2905 /** 2906 * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer 2907 * @dev: ptr to shared code device 2908 * @buf: ptr to fpm query buffer 2909 * @hmc_info: ptr to irdma_hmc_obj_info struct 2910 * @hmc_fpm_misc: ptr to fpm data 2911 * 2912 * parses fpm query buffer and copy max_cnt and 2913 * size value of hmc objects in hmc_info 2914 */ 2915 static enum irdma_status_code 2916 irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf, 2917 struct irdma_hmc_info *hmc_info, 2918 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 2919 { 2920 struct irdma_hmc_obj_info *obj_info; 2921 u64 temp; 2922 u32 size; 2923 u16 max_pe_sds; 2924 2925 obj_info = hmc_info->hmc_obj; 2926 2927 get_64bit_val(buf, 0, &temp); 2928 hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp); 2929 max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp); 2930 2931 hmc_fpm_misc->max_sds = max_pe_sds; 2932 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; 2933 get_64bit_val(buf, 8, &temp); 2934 obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp); 2935 size = (u32)(temp >> 32); 2936 obj_info[IRDMA_HMC_IW_QP].size = BIT_ULL(size); 2937 2938 get_64bit_val(buf, 16, &temp); 2939 obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp); 2940 size = (u32)(temp >> 32); 2941 obj_info[IRDMA_HMC_IW_CQ].size = BIT_ULL(size); 2942 2943 irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE); 2944 irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP); 2945 2946 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192; 2947 obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1; 2948 2949 irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR); 2950 irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF); 2951 2952 get_64bit_val(buf, 64, &temp); 2953 obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp; 2954 obj_info[IRDMA_HMC_IW_XFFL].size = 4; 2955 hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp); 2956 if (!hmc_fpm_misc->xf_block_size) 2957 return IRDMA_ERR_INVALID_SIZE; 2958 2959 irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1); 2960 get_64bit_val(buf, 80, &temp); 2961 obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp; 2962 obj_info[IRDMA_HMC_IW_Q1FL].size = 4; 2963 2964 hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp); 2965 if (!hmc_fpm_misc->q1_block_size) 2966 return IRDMA_ERR_INVALID_SIZE; 2967 2968 irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER); 2969 2970 get_64bit_val(buf, 112, &temp); 2971 obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp; 2972 obj_info[IRDMA_HMC_IW_PBLE].size = 8; 2973 2974 get_64bit_val(buf, 120, &temp); 2975 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); 2976 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); 2977 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); 2978 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 2979 return 0; 2980 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); 2981 irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV); 2982 irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF); 2983 2984 get_64bit_val(buf, 136, &temp); 2985 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp; 2986 obj_info[IRDMA_HMC_IW_RRFFL].size = 4; 2987 hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp); 2988 if (!hmc_fpm_misc->rrf_block_size && 2989 obj_info[IRDMA_HMC_IW_RRFFL].max_cnt) 2990 return IRDMA_ERR_INVALID_SIZE; 2991 2992 irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR); 2993 irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD); 2994 irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC); 2995 2996 get_64bit_val(buf, 168, &temp); 2997 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp; 2998 obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4; 2999 hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp); 3000 if (!hmc_fpm_misc->ooiscf_block_size && 3001 obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt) 3002 return IRDMA_ERR_INVALID_SIZE; 3003 3004 return 0; 3005 } 3006 3007 /** 3008 * irdma_sc_find_reg_cq - find cq ctx index 3009 * @ceq: ceq sc structure 3010 * @cq: cq sc structure 3011 */ 3012 static u32 irdma_sc_find_reg_cq(struct irdma_sc_ceq *ceq, 3013 struct irdma_sc_cq *cq) 3014 { 3015 u32 i; 3016 3017 for (i = 0; i < ceq->reg_cq_size; i++) { 3018 if (cq == ceq->reg_cq[i]) 3019 return i; 3020 } 3021 3022 return IRDMA_INVALID_CQ_IDX; 3023 } 3024 3025 /** 3026 * irdma_sc_add_cq_ctx - add cq ctx tracking for ceq 3027 * @ceq: ceq sc structure 3028 * @cq: cq sc structure 3029 */ 3030 enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq, 3031 struct irdma_sc_cq *cq) 3032 { 3033 unsigned long flags; 3034 3035 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3036 3037 if (ceq->reg_cq_size == ceq->elem_cnt) { 3038 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3039 return IRDMA_ERR_REG_CQ_FULL; 3040 } 3041 3042 ceq->reg_cq[ceq->reg_cq_size++] = cq; 3043 3044 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3045 3046 return 0; 3047 } 3048 3049 /** 3050 * irdma_sc_remove_cq_ctx - remove cq ctx tracking for ceq 3051 * @ceq: ceq sc structure 3052 * @cq: cq sc structure 3053 */ 3054 void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq) 3055 { 3056 unsigned long flags; 3057 u32 cq_ctx_idx; 3058 3059 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3060 cq_ctx_idx = irdma_sc_find_reg_cq(ceq, cq); 3061 if (cq_ctx_idx == IRDMA_INVALID_CQ_IDX) 3062 goto exit; 3063 3064 ceq->reg_cq_size--; 3065 if (cq_ctx_idx != ceq->reg_cq_size) 3066 ceq->reg_cq[cq_ctx_idx] = ceq->reg_cq[ceq->reg_cq_size]; 3067 ceq->reg_cq[ceq->reg_cq_size] = NULL; 3068 3069 exit: 3070 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3071 } 3072 3073 /** 3074 * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair 3075 * @cqp: IWARP control queue pair pointer 3076 * @info: IWARP control queue pair init info pointer 3077 * 3078 * Initializes the object and context buffers for a control Queue Pair. 3079 */ 3080 enum irdma_status_code irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, 3081 struct irdma_cqp_init_info *info) 3082 { 3083 u8 hw_sq_size; 3084 3085 if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 || 3086 info->sq_size < IRDMA_CQP_SW_SQSIZE_4 || 3087 ((info->sq_size & (info->sq_size - 1)))) 3088 return IRDMA_ERR_INVALID_SIZE; 3089 3090 hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size, 3091 IRDMA_QUEUE_TYPE_CQP); 3092 cqp->size = sizeof(*cqp); 3093 cqp->sq_size = info->sq_size; 3094 cqp->hw_sq_size = hw_sq_size; 3095 cqp->sq_base = info->sq; 3096 cqp->host_ctx = info->host_ctx; 3097 cqp->sq_pa = info->sq_pa; 3098 cqp->host_ctx_pa = info->host_ctx_pa; 3099 cqp->dev = info->dev; 3100 cqp->struct_ver = info->struct_ver; 3101 cqp->hw_maj_ver = info->hw_maj_ver; 3102 cqp->hw_min_ver = info->hw_min_ver; 3103 cqp->scratch_array = info->scratch_array; 3104 cqp->polarity = 0; 3105 cqp->en_datacenter_tcp = info->en_datacenter_tcp; 3106 cqp->ena_vf_count = info->ena_vf_count; 3107 cqp->hmc_profile = info->hmc_profile; 3108 cqp->ceqs_per_vf = info->ceqs_per_vf; 3109 cqp->disable_packed = info->disable_packed; 3110 cqp->rocev2_rto_policy = info->rocev2_rto_policy; 3111 cqp->protocol_used = info->protocol_used; 3112 memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params)); 3113 info->dev->cqp = cqp; 3114 3115 IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size); 3116 cqp->dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS] = 0; 3117 cqp->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS] = 0; 3118 /* for the cqp commands backlog. */ 3119 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); 3120 3121 writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); 3122 writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); 3123 writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3124 3125 ibdev_dbg(to_ibdev(cqp->dev), 3126 "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%pK] cqp[%p] polarity[x%04x]\n", 3127 cqp->sq_size, cqp->hw_sq_size, cqp->sq_base, 3128 (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity); 3129 return 0; 3130 } 3131 3132 /** 3133 * irdma_sc_cqp_create - create cqp during bringup 3134 * @cqp: struct for cqp hw 3135 * @maj_err: If error, major err number 3136 * @min_err: If error, minor err number 3137 */ 3138 enum irdma_status_code irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, 3139 u16 *min_err) 3140 { 3141 u64 temp; 3142 u8 hw_rev; 3143 u32 cnt = 0, p1, p2, val = 0, err_code; 3144 enum irdma_status_code ret_code; 3145 3146 hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev; 3147 cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size, 3148 IRDMA_SD_BUF_ALIGNMENT); 3149 cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device, 3150 cqp->sdbuf.size, &cqp->sdbuf.pa, 3151 GFP_KERNEL); 3152 if (!cqp->sdbuf.va) 3153 return IRDMA_ERR_NO_MEMORY; 3154 3155 spin_lock_init(&cqp->dev->cqp_lock); 3156 3157 temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) | 3158 FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) | 3159 FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) | 3160 FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf); 3161 if (hw_rev >= IRDMA_GEN_2) { 3162 temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY, 3163 cqp->rocev2_rto_policy) | 3164 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, 3165 cqp->protocol_used); 3166 } 3167 3168 set_64bit_val(cqp->host_ctx, 0, temp); 3169 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); 3170 3171 temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) | 3172 FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile); 3173 set_64bit_val(cqp->host_ctx, 16, temp); 3174 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); 3175 temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) | 3176 FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver); 3177 if (hw_rev >= IRDMA_GEN_2) { 3178 temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) | 3179 FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor); 3180 } 3181 set_64bit_val(cqp->host_ctx, 32, temp); 3182 set_64bit_val(cqp->host_ctx, 40, 0); 3183 temp = 0; 3184 if (hw_rev >= IRDMA_GEN_2) { 3185 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) | 3186 FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) | 3187 FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor); 3188 } 3189 set_64bit_val(cqp->host_ctx, 48, temp); 3190 temp = 0; 3191 if (hw_rev >= IRDMA_GEN_2) { 3192 temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) | 3193 FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) | 3194 FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) | 3195 FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod); 3196 } 3197 set_64bit_val(cqp->host_ctx, 56, temp); 3198 print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16, 3199 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false); 3200 p1 = cqp->host_ctx_pa >> 32; 3201 p2 = (u32)cqp->host_ctx_pa; 3202 3203 writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3204 writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3205 3206 do { 3207 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3208 ret_code = IRDMA_ERR_TIMEOUT; 3209 goto err; 3210 } 3211 udelay(cqp->dev->hw_attrs.max_sleep_count); 3212 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3213 } while (!val); 3214 3215 if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) { 3216 ret_code = IRDMA_ERR_DEVICE_NOT_SUPPORTED; 3217 goto err; 3218 } 3219 3220 cqp->process_cqp_sds = irdma_update_sds_noccq; 3221 return 0; 3222 3223 err: 3224 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3225 cqp->sdbuf.va, cqp->sdbuf.pa); 3226 cqp->sdbuf.va = NULL; 3227 err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3228 *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code); 3229 *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code); 3230 return ret_code; 3231 } 3232 3233 /** 3234 * irdma_sc_cqp_post_sq - post of cqp's sq 3235 * @cqp: struct for cqp hw 3236 */ 3237 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp) 3238 { 3239 writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db); 3240 3241 ibdev_dbg(to_ibdev(cqp->dev), 3242 "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n", 3243 cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); 3244 } 3245 3246 /** 3247 * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq 3248 * and pass back index 3249 * @cqp: CQP HW structure 3250 * @scratch: private data for CQP WQE 3251 * @wqe_idx: WQE index of CQP SQ 3252 */ 3253 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, 3254 u32 *wqe_idx) 3255 { 3256 __le64 *wqe = NULL; 3257 enum irdma_status_code ret_code; 3258 3259 if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) { 3260 ibdev_dbg(to_ibdev(cqp->dev), 3261 "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n", 3262 cqp->sq_ring.head, cqp->sq_ring.tail, 3263 cqp->sq_ring.size); 3264 return NULL; 3265 } 3266 IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); 3267 if (ret_code) 3268 return NULL; 3269 3270 cqp->dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS]++; 3271 if (!*wqe_idx) 3272 cqp->polarity = !cqp->polarity; 3273 wqe = cqp->sq_base[*wqe_idx].elem; 3274 cqp->scratch_array[*wqe_idx] = scratch; 3275 IRDMA_CQP_INIT_WQE(wqe); 3276 3277 return wqe; 3278 } 3279 3280 /** 3281 * irdma_sc_cqp_destroy - destroy cqp during close 3282 * @cqp: struct for cqp hw 3283 */ 3284 enum irdma_status_code irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp) 3285 { 3286 u32 cnt = 0, val; 3287 enum irdma_status_code ret_code = 0; 3288 3289 writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); 3290 writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); 3291 do { 3292 if (cnt++ > cqp->dev->hw_attrs.max_done_count) { 3293 ret_code = IRDMA_ERR_TIMEOUT; 3294 break; 3295 } 3296 udelay(cqp->dev->hw_attrs.max_sleep_count); 3297 val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); 3298 } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE)); 3299 3300 dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, 3301 cqp->sdbuf.va, cqp->sdbuf.pa); 3302 cqp->sdbuf.va = NULL; 3303 return ret_code; 3304 } 3305 3306 /** 3307 * irdma_sc_ccq_arm - enable intr for control cq 3308 * @ccq: ccq sc struct 3309 */ 3310 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq) 3311 { 3312 u64 temp_val; 3313 u16 sw_cq_sel; 3314 u8 arm_next_se; 3315 u8 arm_seq_num; 3316 3317 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); 3318 sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); 3319 arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); 3320 arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); 3321 arm_seq_num++; 3322 temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | 3323 FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | 3324 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | 3325 FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1); 3326 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); 3327 3328 dma_wmb(); /* make sure shadow area is updated before arming */ 3329 3330 writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db); 3331 } 3332 3333 /** 3334 * irdma_sc_ccq_get_cqe_info - get ccq's cq entry 3335 * @ccq: ccq sc struct 3336 * @info: completion q entry to return 3337 */ 3338 enum irdma_status_code irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, 3339 struct irdma_ccq_cqe_info *info) 3340 { 3341 u64 qp_ctx, temp, temp1; 3342 __le64 *cqe; 3343 struct irdma_sc_cqp *cqp; 3344 u32 wqe_idx; 3345 u32 error; 3346 u8 polarity; 3347 enum irdma_status_code ret_code = 0; 3348 3349 if (ccq->cq_uk.avoid_mem_cflct) 3350 cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk); 3351 else 3352 cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk); 3353 3354 get_64bit_val(cqe, 24, &temp); 3355 polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp); 3356 if (polarity != ccq->cq_uk.polarity) 3357 return IRDMA_ERR_Q_EMPTY; 3358 3359 get_64bit_val(cqe, 8, &qp_ctx); 3360 cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx; 3361 info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp); 3362 info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR; 3363 info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp); 3364 if (info->error) { 3365 info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp); 3366 error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); 3367 ibdev_dbg(to_ibdev(cqp->dev), 3368 "CQP: CQPERRCODES error_code[x%08X]\n", error); 3369 } 3370 3371 wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp); 3372 info->scratch = cqp->scratch_array[wqe_idx]; 3373 3374 get_64bit_val(cqe, 16, &temp1); 3375 info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1); 3376 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); 3377 info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1); 3378 info->cqp = cqp; 3379 3380 /* move the head for cq */ 3381 IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); 3382 if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)) 3383 ccq->cq_uk.polarity ^= 1; 3384 3385 /* update cq tail in cq shadow memory also */ 3386 IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); 3387 set_64bit_val(ccq->cq_uk.shadow_area, 0, 3388 IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)); 3389 3390 dma_wmb(); /* make sure shadow area is updated before moving tail */ 3391 3392 IRDMA_RING_MOVE_TAIL(cqp->sq_ring); 3393 ccq->dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]++; 3394 3395 return ret_code; 3396 } 3397 3398 /** 3399 * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ 3400 * @cqp: struct for cqp hw 3401 * @op_code: cqp opcode for completion 3402 * @compl_info: completion q entry to return 3403 */ 3404 enum irdma_status_code irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code, 3405 struct irdma_ccq_cqe_info *compl_info) 3406 { 3407 struct irdma_ccq_cqe_info info = {}; 3408 struct irdma_sc_cq *ccq; 3409 enum irdma_status_code ret_code = 0; 3410 u32 cnt = 0; 3411 3412 ccq = cqp->dev->ccq; 3413 while (1) { 3414 if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count) 3415 return IRDMA_ERR_TIMEOUT; 3416 3417 if (irdma_sc_ccq_get_cqe_info(ccq, &info)) { 3418 udelay(cqp->dev->hw_attrs.max_sleep_count); 3419 continue; 3420 } 3421 if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) { 3422 ret_code = IRDMA_ERR_CQP_COMPL_ERROR; 3423 break; 3424 } 3425 /* make sure op code matches*/ 3426 if (op_code == info.op_code) 3427 break; 3428 ibdev_dbg(to_ibdev(cqp->dev), 3429 "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n", 3430 op_code, info.op_code); 3431 } 3432 3433 if (compl_info) 3434 memcpy(compl_info, &info, sizeof(*compl_info)); 3435 3436 return ret_code; 3437 } 3438 3439 /** 3440 * irdma_sc_manage_hmc_pm_func_table - manage of function table 3441 * @cqp: struct for cqp hw 3442 * @scratch: u64 saved to be used during cqp completion 3443 * @info: info for the manage function table operation 3444 * @post_sq: flag for cqp db to ring 3445 */ 3446 static enum irdma_status_code 3447 irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp, 3448 struct irdma_hmc_fcn_info *info, 3449 u64 scratch, bool post_sq) 3450 { 3451 __le64 *wqe; 3452 u64 hdr; 3453 3454 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3455 if (!wqe) 3456 return IRDMA_ERR_RING_FULL; 3457 3458 set_64bit_val(wqe, 0, 0); 3459 set_64bit_val(wqe, 8, 0); 3460 set_64bit_val(wqe, 16, 0); 3461 set_64bit_val(wqe, 32, 0); 3462 set_64bit_val(wqe, 40, 0); 3463 set_64bit_val(wqe, 48, 0); 3464 set_64bit_val(wqe, 56, 0); 3465 3466 hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) | 3467 FIELD_PREP(IRDMA_CQPSQ_OPCODE, 3468 IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) | 3469 FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) | 3470 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3471 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3472 3473 set_64bit_val(wqe, 24, hdr); 3474 3475 print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE", 3476 DUMP_PREFIX_OFFSET, 16, 8, wqe, 3477 IRDMA_CQP_WQE_SIZE * 8, false); 3478 if (post_sq) 3479 irdma_sc_cqp_post_sq(cqp); 3480 3481 return 0; 3482 } 3483 3484 /** 3485 * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion 3486 * for fpm commit 3487 * @cqp: struct for cqp hw 3488 */ 3489 static enum irdma_status_code 3490 irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp) 3491 { 3492 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL, 3493 NULL); 3494 } 3495 3496 /** 3497 * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values 3498 * @cqp: struct for cqp hw 3499 * @scratch: u64 saved to be used during cqp completion 3500 * @hmc_fn_id: hmc function id 3501 * @commit_fpm_mem: Memory for fpm values 3502 * @post_sq: flag for cqp db to ring 3503 * @wait_type: poll ccq or cqp registers for cqp completion 3504 */ 3505 static enum irdma_status_code 3506 irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id, 3507 struct irdma_dma_mem *commit_fpm_mem, bool post_sq, 3508 u8 wait_type) 3509 { 3510 __le64 *wqe; 3511 u64 hdr; 3512 u32 tail, val, error; 3513 enum irdma_status_code ret_code = 0; 3514 3515 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3516 if (!wqe) 3517 return IRDMA_ERR_RING_FULL; 3518 3519 set_64bit_val(wqe, 16, hmc_fn_id); 3520 set_64bit_val(wqe, 32, commit_fpm_mem->pa); 3521 3522 hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) | 3523 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) | 3524 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3525 3526 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3527 3528 set_64bit_val(wqe, 24, hdr); 3529 3530 print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET, 3531 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3532 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 3533 3534 if (post_sq) { 3535 irdma_sc_cqp_post_sq(cqp); 3536 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 3537 ret_code = irdma_cqp_poll_registers(cqp, tail, 3538 cqp->dev->hw_attrs.max_done_count); 3539 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 3540 ret_code = irdma_sc_commit_fpm_val_done(cqp); 3541 } 3542 3543 return ret_code; 3544 } 3545 3546 /** 3547 * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for 3548 * query fpm 3549 * @cqp: struct for cqp hw 3550 */ 3551 static enum irdma_status_code 3552 irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp) 3553 { 3554 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL, 3555 NULL); 3556 } 3557 3558 /** 3559 * irdma_sc_query_fpm_val - cqp wqe query fpm values 3560 * @cqp: struct for cqp hw 3561 * @scratch: u64 saved to be used during cqp completion 3562 * @hmc_fn_id: hmc function id 3563 * @query_fpm_mem: memory for return fpm values 3564 * @post_sq: flag for cqp db to ring 3565 * @wait_type: poll ccq or cqp registers for cqp completion 3566 */ 3567 static enum irdma_status_code 3568 irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, u8 hmc_fn_id, 3569 struct irdma_dma_mem *query_fpm_mem, bool post_sq, 3570 u8 wait_type) 3571 { 3572 __le64 *wqe; 3573 u64 hdr; 3574 u32 tail, val, error; 3575 enum irdma_status_code ret_code = 0; 3576 3577 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3578 if (!wqe) 3579 return IRDMA_ERR_RING_FULL; 3580 3581 set_64bit_val(wqe, 16, hmc_fn_id); 3582 set_64bit_val(wqe, 32, query_fpm_mem->pa); 3583 3584 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) | 3585 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3586 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3587 3588 set_64bit_val(wqe, 24, hdr); 3589 3590 print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8, 3591 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3592 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 3593 3594 if (post_sq) { 3595 irdma_sc_cqp_post_sq(cqp); 3596 if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) 3597 ret_code = irdma_cqp_poll_registers(cqp, tail, 3598 cqp->dev->hw_attrs.max_done_count); 3599 else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) 3600 ret_code = irdma_sc_query_fpm_val_done(cqp); 3601 } 3602 3603 return ret_code; 3604 } 3605 3606 /** 3607 * irdma_sc_ceq_init - initialize ceq 3608 * @ceq: ceq sc structure 3609 * @info: ceq initialization info 3610 */ 3611 enum irdma_status_code irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, 3612 struct irdma_ceq_init_info *info) 3613 { 3614 u32 pble_obj_cnt; 3615 3616 if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size || 3617 info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size) 3618 return IRDMA_ERR_INVALID_SIZE; 3619 3620 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) 3621 return IRDMA_ERR_INVALID_CEQ_ID; 3622 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3623 3624 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 3625 return IRDMA_ERR_INVALID_PBLE_INDEX; 3626 3627 ceq->size = sizeof(*ceq); 3628 ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base; 3629 ceq->ceq_id = info->ceq_id; 3630 ceq->dev = info->dev; 3631 ceq->elem_cnt = info->elem_cnt; 3632 ceq->ceq_elem_pa = info->ceqe_pa; 3633 ceq->virtual_map = info->virtual_map; 3634 ceq->itr_no_expire = info->itr_no_expire; 3635 ceq->reg_cq = info->reg_cq; 3636 ceq->reg_cq_size = 0; 3637 spin_lock_init(&ceq->req_cq_lock); 3638 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); 3639 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); 3640 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); 3641 ceq->tph_en = info->tph_en; 3642 ceq->tph_val = info->tph_val; 3643 ceq->vsi = info->vsi; 3644 ceq->polarity = 1; 3645 IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); 3646 ceq->dev->ceq[info->ceq_id] = ceq; 3647 3648 return 0; 3649 } 3650 3651 /** 3652 * irdma_sc_ceq_create - create ceq wqe 3653 * @ceq: ceq sc structure 3654 * @scratch: u64 saved to be used during cqp completion 3655 * @post_sq: flag for cqp db to ring 3656 */ 3657 3658 static enum irdma_status_code irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch, 3659 bool post_sq) 3660 { 3661 struct irdma_sc_cqp *cqp; 3662 __le64 *wqe; 3663 u64 hdr; 3664 3665 cqp = ceq->dev->cqp; 3666 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3667 if (!wqe) 3668 return IRDMA_ERR_RING_FULL; 3669 set_64bit_val(wqe, 16, ceq->elem_cnt); 3670 set_64bit_val(wqe, 32, 3671 (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); 3672 set_64bit_val(wqe, 48, 3673 (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); 3674 set_64bit_val(wqe, 56, 3675 FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) | 3676 FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx)); 3677 hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) | 3678 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) | 3679 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 3680 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 3681 FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) | 3682 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 3683 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3684 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3685 3686 set_64bit_val(wqe, 24, hdr); 3687 3688 print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 3689 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3690 if (post_sq) 3691 irdma_sc_cqp_post_sq(cqp); 3692 3693 return 0; 3694 } 3695 3696 /** 3697 * irdma_sc_cceq_create_done - poll for control ceq wqe to complete 3698 * @ceq: ceq sc structure 3699 */ 3700 static enum irdma_status_code 3701 irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq) 3702 { 3703 struct irdma_sc_cqp *cqp; 3704 3705 cqp = ceq->dev->cqp; 3706 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ, 3707 NULL); 3708 } 3709 3710 /** 3711 * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete 3712 * @ceq: ceq sc structure 3713 */ 3714 enum irdma_status_code irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq) 3715 { 3716 struct irdma_sc_cqp *cqp; 3717 3718 if (ceq->reg_cq) 3719 irdma_sc_remove_cq_ctx(ceq, ceq->dev->ccq); 3720 3721 cqp = ceq->dev->cqp; 3722 cqp->process_cqp_sds = irdma_update_sds_noccq; 3723 3724 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ, 3725 NULL); 3726 } 3727 3728 /** 3729 * irdma_sc_cceq_create - create cceq 3730 * @ceq: ceq sc structure 3731 * @scratch: u64 saved to be used during cqp completion 3732 */ 3733 enum irdma_status_code irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch) 3734 { 3735 enum irdma_status_code ret_code; 3736 struct irdma_sc_dev *dev = ceq->dev; 3737 3738 dev->ccq->vsi = ceq->vsi; 3739 if (ceq->reg_cq) { 3740 ret_code = irdma_sc_add_cq_ctx(ceq, ceq->dev->ccq); 3741 if (ret_code) 3742 return ret_code; 3743 } 3744 3745 ret_code = irdma_sc_ceq_create(ceq, scratch, true); 3746 if (!ret_code) 3747 return irdma_sc_cceq_create_done(ceq); 3748 3749 return ret_code; 3750 } 3751 3752 /** 3753 * irdma_sc_ceq_destroy - destroy ceq 3754 * @ceq: ceq sc structure 3755 * @scratch: u64 saved to be used during cqp completion 3756 * @post_sq: flag for cqp db to ring 3757 */ 3758 enum irdma_status_code irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, 3759 bool post_sq) 3760 { 3761 struct irdma_sc_cqp *cqp; 3762 __le64 *wqe; 3763 u64 hdr; 3764 3765 cqp = ceq->dev->cqp; 3766 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3767 if (!wqe) 3768 return IRDMA_ERR_RING_FULL; 3769 3770 set_64bit_val(wqe, 16, ceq->elem_cnt); 3771 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); 3772 hdr = ceq->ceq_id | 3773 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) | 3774 FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | 3775 FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | 3776 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | 3777 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3778 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3779 3780 set_64bit_val(wqe, 24, hdr); 3781 3782 print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 3783 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3784 if (post_sq) 3785 irdma_sc_cqp_post_sq(cqp); 3786 3787 return 0; 3788 } 3789 3790 /** 3791 * irdma_sc_process_ceq - process ceq 3792 * @dev: sc device struct 3793 * @ceq: ceq sc structure 3794 * 3795 * It is expected caller serializes this function with cleanup_ceqes() 3796 * because these functions manipulate the same ceq 3797 */ 3798 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq) 3799 { 3800 u64 temp; 3801 __le64 *ceqe; 3802 struct irdma_sc_cq *cq = NULL; 3803 struct irdma_sc_cq *temp_cq; 3804 u8 polarity; 3805 u32 cq_idx; 3806 unsigned long flags; 3807 3808 do { 3809 cq_idx = 0; 3810 ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq); 3811 get_64bit_val(ceqe, 0, &temp); 3812 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 3813 if (polarity != ceq->polarity) 3814 return NULL; 3815 3816 temp_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1); 3817 if (!temp_cq) { 3818 cq_idx = IRDMA_INVALID_CQ_IDX; 3819 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 3820 3821 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 3822 ceq->polarity ^= 1; 3823 continue; 3824 } 3825 3826 cq = temp_cq; 3827 if (ceq->reg_cq) { 3828 spin_lock_irqsave(&ceq->req_cq_lock, flags); 3829 cq_idx = irdma_sc_find_reg_cq(ceq, cq); 3830 spin_unlock_irqrestore(&ceq->req_cq_lock, flags); 3831 } 3832 3833 IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); 3834 if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) 3835 ceq->polarity ^= 1; 3836 } while (cq_idx == IRDMA_INVALID_CQ_IDX); 3837 3838 if (cq) 3839 irdma_sc_cq_ack(cq); 3840 return cq; 3841 } 3842 3843 /** 3844 * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq 3845 * @cq: cq for which the ceqes need to be cleaned up 3846 * @ceq: ceq ptr 3847 * 3848 * The function is called after the cq is destroyed to cleanup 3849 * its pending ceqe entries. It is expected caller serializes this 3850 * function with process_ceq() in interrupt context. 3851 */ 3852 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq) 3853 { 3854 struct irdma_sc_cq *next_cq; 3855 u8 ceq_polarity = ceq->polarity; 3856 __le64 *ceqe; 3857 u8 polarity; 3858 u64 temp; 3859 int next; 3860 u32 i; 3861 3862 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0); 3863 3864 for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) { 3865 ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next); 3866 3867 get_64bit_val(ceqe, 0, &temp); 3868 polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); 3869 if (polarity != ceq_polarity) 3870 return; 3871 3872 next_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1); 3873 if (cq == next_cq) 3874 set_64bit_val(ceqe, 0, temp & IRDMA_CEQE_VALID); 3875 3876 next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i); 3877 if (!next) 3878 ceq_polarity ^= 1; 3879 } 3880 } 3881 3882 /** 3883 * irdma_sc_aeq_init - initialize aeq 3884 * @aeq: aeq structure ptr 3885 * @info: aeq initialization info 3886 */ 3887 enum irdma_status_code irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, 3888 struct irdma_aeq_init_info *info) 3889 { 3890 u32 pble_obj_cnt; 3891 3892 if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size || 3893 info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size) 3894 return IRDMA_ERR_INVALID_SIZE; 3895 3896 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 3897 3898 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 3899 return IRDMA_ERR_INVALID_PBLE_INDEX; 3900 3901 aeq->size = sizeof(*aeq); 3902 aeq->polarity = 1; 3903 aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base; 3904 aeq->dev = info->dev; 3905 aeq->elem_cnt = info->elem_cnt; 3906 aeq->aeq_elem_pa = info->aeq_elem_pa; 3907 IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); 3908 aeq->virtual_map = info->virtual_map; 3909 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); 3910 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); 3911 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); 3912 aeq->msix_idx = info->msix_idx; 3913 info->dev->aeq = aeq; 3914 3915 return 0; 3916 } 3917 3918 /** 3919 * irdma_sc_aeq_create - create aeq 3920 * @aeq: aeq structure ptr 3921 * @scratch: u64 saved to be used during cqp completion 3922 * @post_sq: flag for cqp db to ring 3923 */ 3924 static enum irdma_status_code irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, 3925 u64 scratch, bool post_sq) 3926 { 3927 __le64 *wqe; 3928 struct irdma_sc_cqp *cqp; 3929 u64 hdr; 3930 3931 cqp = aeq->dev->cqp; 3932 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3933 if (!wqe) 3934 return IRDMA_ERR_RING_FULL; 3935 set_64bit_val(wqe, 16, aeq->elem_cnt); 3936 set_64bit_val(wqe, 32, 3937 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); 3938 set_64bit_val(wqe, 48, 3939 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); 3940 3941 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) | 3942 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 3943 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 3944 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3945 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3946 3947 set_64bit_val(wqe, 24, hdr); 3948 3949 print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, 3950 wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3951 if (post_sq) 3952 irdma_sc_cqp_post_sq(cqp); 3953 3954 return 0; 3955 } 3956 3957 /** 3958 * irdma_sc_aeq_destroy - destroy aeq during close 3959 * @aeq: aeq structure ptr 3960 * @scratch: u64 saved to be used during cqp completion 3961 * @post_sq: flag for cqp db to ring 3962 */ 3963 static enum irdma_status_code irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, 3964 u64 scratch, bool post_sq) 3965 { 3966 __le64 *wqe; 3967 struct irdma_sc_cqp *cqp; 3968 struct irdma_sc_dev *dev; 3969 u64 hdr; 3970 3971 dev = aeq->dev; 3972 writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 3973 3974 cqp = dev->cqp; 3975 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 3976 if (!wqe) 3977 return IRDMA_ERR_RING_FULL; 3978 set_64bit_val(wqe, 16, aeq->elem_cnt); 3979 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); 3980 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) | 3981 FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | 3982 FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | 3983 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 3984 dma_wmb(); /* make sure WQE is written before valid bit is set */ 3985 3986 set_64bit_val(wqe, 24, hdr); 3987 3988 print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 3989 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 3990 if (post_sq) 3991 irdma_sc_cqp_post_sq(cqp); 3992 return 0; 3993 } 3994 3995 /** 3996 * irdma_sc_get_next_aeqe - get next aeq entry 3997 * @aeq: aeq structure ptr 3998 * @info: aeqe info to be returned 3999 */ 4000 enum irdma_status_code irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 4001 struct irdma_aeqe_info *info) 4002 { 4003 u64 temp, compl_ctx; 4004 __le64 *aeqe; 4005 u16 wqe_idx; 4006 u8 ae_src; 4007 u8 polarity; 4008 4009 aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq); 4010 get_64bit_val(aeqe, 0, &compl_ctx); 4011 get_64bit_val(aeqe, 8, &temp); 4012 polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp); 4013 4014 if (aeq->polarity != polarity) 4015 return IRDMA_ERR_Q_EMPTY; 4016 4017 print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8, 4018 aeqe, 16, false); 4019 4020 ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp); 4021 wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp); 4022 info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) | 4023 ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18); 4024 info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp); 4025 info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp); 4026 info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp); 4027 info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp); 4028 info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, temp); 4029 4030 info->ae_src = ae_src; 4031 switch (info->ae_id) { 4032 case IRDMA_AE_PRIV_OPERATION_DENIED: 4033 case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW: 4034 case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW: 4035 case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG: 4036 case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH: 4037 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 4038 case IRDMA_AE_UDA_XMIT_BAD_PD: 4039 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 4040 case IRDMA_AE_BAD_CLOSE: 4041 case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO: 4042 case IRDMA_AE_STAG_ZERO_INVALID: 4043 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 4044 case IRDMA_AE_IB_INVALID_REQUEST: 4045 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 4046 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 4047 case IRDMA_AE_IB_REMOTE_OP_ERROR: 4048 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 4049 case IRDMA_AE_DDP_UBE_INVALID_MO: 4050 case IRDMA_AE_DDP_UBE_INVALID_QN: 4051 case IRDMA_AE_DDP_NO_L_BIT: 4052 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 4053 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 4054 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 4055 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 4056 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 4057 case IRDMA_AE_INVALID_ARP_ENTRY: 4058 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 4059 case IRDMA_AE_STALE_ARP_ENTRY: 4060 case IRDMA_AE_INVALID_AH_ENTRY: 4061 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 4062 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 4063 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 4064 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 4065 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 4066 case IRDMA_AE_RESET_SENT: 4067 case IRDMA_AE_TERMINATE_SENT: 4068 case IRDMA_AE_RESET_NOT_SENT: 4069 case IRDMA_AE_LCE_QP_CATASTROPHIC: 4070 case IRDMA_AE_QP_SUSPEND_COMPLETE: 4071 case IRDMA_AE_UDA_L4LEN_INVALID: 4072 info->qp = true; 4073 info->compl_ctx = compl_ctx; 4074 break; 4075 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 4076 info->cq = true; 4077 info->compl_ctx = compl_ctx << 1; 4078 ae_src = IRDMA_AE_SOURCE_RSVD; 4079 break; 4080 case IRDMA_AE_ROCE_EMPTY_MCG: 4081 case IRDMA_AE_ROCE_BAD_MC_IP_ADDR: 4082 case IRDMA_AE_ROCE_BAD_MC_QPID: 4083 case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH: 4084 fallthrough; 4085 case IRDMA_AE_LLP_CONNECTION_RESET: 4086 case IRDMA_AE_LLP_SYN_RECEIVED: 4087 case IRDMA_AE_LLP_FIN_RECEIVED: 4088 case IRDMA_AE_LLP_CLOSE_COMPLETE: 4089 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 4090 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 4091 ae_src = IRDMA_AE_SOURCE_RSVD; 4092 info->qp = true; 4093 info->compl_ctx = compl_ctx; 4094 break; 4095 default: 4096 break; 4097 } 4098 4099 switch (ae_src) { 4100 case IRDMA_AE_SOURCE_RQ: 4101 case IRDMA_AE_SOURCE_RQ_0011: 4102 info->qp = true; 4103 info->rq = true; 4104 info->wqe_idx = wqe_idx; 4105 info->compl_ctx = compl_ctx; 4106 break; 4107 case IRDMA_AE_SOURCE_CQ: 4108 case IRDMA_AE_SOURCE_CQ_0110: 4109 case IRDMA_AE_SOURCE_CQ_1010: 4110 case IRDMA_AE_SOURCE_CQ_1110: 4111 info->cq = true; 4112 info->compl_ctx = compl_ctx << 1; 4113 break; 4114 case IRDMA_AE_SOURCE_SQ: 4115 case IRDMA_AE_SOURCE_SQ_0111: 4116 info->qp = true; 4117 info->sq = true; 4118 info->wqe_idx = wqe_idx; 4119 info->compl_ctx = compl_ctx; 4120 break; 4121 case IRDMA_AE_SOURCE_IN_RR_WR: 4122 case IRDMA_AE_SOURCE_IN_RR_WR_1011: 4123 info->qp = true; 4124 info->compl_ctx = compl_ctx; 4125 info->in_rdrsp_wr = true; 4126 break; 4127 case IRDMA_AE_SOURCE_OUT_RR: 4128 case IRDMA_AE_SOURCE_OUT_RR_1111: 4129 info->qp = true; 4130 info->compl_ctx = compl_ctx; 4131 info->out_rdrsp = true; 4132 break; 4133 case IRDMA_AE_SOURCE_RSVD: 4134 default: 4135 break; 4136 } 4137 4138 IRDMA_RING_MOVE_TAIL(aeq->aeq_ring); 4139 if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring)) 4140 aeq->polarity ^= 1; 4141 4142 return 0; 4143 } 4144 4145 /** 4146 * irdma_sc_repost_aeq_entries - repost completed aeq entries 4147 * @dev: sc device struct 4148 * @count: allocate count 4149 */ 4150 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) 4151 { 4152 writel(count, dev->hw_regs[IRDMA_AEQALLOC]); 4153 } 4154 4155 /** 4156 * irdma_sc_ccq_init - initialize control cq 4157 * @cq: sc's cq ctruct 4158 * @info: info for control cq initialization 4159 */ 4160 enum irdma_status_code irdma_sc_ccq_init(struct irdma_sc_cq *cq, 4161 struct irdma_ccq_init_info *info) 4162 { 4163 u32 pble_obj_cnt; 4164 4165 if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size || 4166 info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size) 4167 return IRDMA_ERR_INVALID_SIZE; 4168 4169 if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) 4170 return IRDMA_ERR_INVALID_CEQ_ID; 4171 4172 pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; 4173 4174 if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) 4175 return IRDMA_ERR_INVALID_PBLE_INDEX; 4176 4177 cq->cq_pa = info->cq_pa; 4178 cq->cq_uk.cq_base = info->cq_base; 4179 cq->shadow_area_pa = info->shadow_area_pa; 4180 cq->cq_uk.shadow_area = info->shadow_area; 4181 cq->shadow_read_threshold = info->shadow_read_threshold; 4182 cq->dev = info->dev; 4183 cq->ceq_id = info->ceq_id; 4184 cq->cq_uk.cq_size = info->num_elem; 4185 cq->cq_type = IRDMA_CQ_TYPE_CQP; 4186 cq->ceqe_mask = info->ceqe_mask; 4187 IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); 4188 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ 4189 cq->ceq_id_valid = info->ceq_id_valid; 4190 cq->tph_en = info->tph_en; 4191 cq->tph_val = info->tph_val; 4192 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; 4193 cq->pbl_list = info->pbl_list; 4194 cq->virtual_map = info->virtual_map; 4195 cq->pbl_chunk_size = info->pbl_chunk_size; 4196 cq->first_pm_pbl_idx = info->first_pm_pbl_idx; 4197 cq->cq_uk.polarity = true; 4198 cq->vsi = info->vsi; 4199 cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db; 4200 4201 /* Only applicable to CQs other than CCQ so initialize to zero */ 4202 cq->cq_uk.cqe_alloc_db = NULL; 4203 4204 info->dev->ccq = cq; 4205 return 0; 4206 } 4207 4208 /** 4209 * irdma_sc_ccq_create_done - poll cqp for ccq create 4210 * @ccq: ccq sc struct 4211 */ 4212 static inline enum irdma_status_code irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq) 4213 { 4214 struct irdma_sc_cqp *cqp; 4215 4216 cqp = ccq->dev->cqp; 4217 4218 return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL); 4219 } 4220 4221 /** 4222 * irdma_sc_ccq_create - create control cq 4223 * @ccq: ccq sc struct 4224 * @scratch: u64 saved to be used during cqp completion 4225 * @check_overflow: overlow flag for ccq 4226 * @post_sq: flag for cqp db to ring 4227 */ 4228 enum irdma_status_code irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, 4229 bool check_overflow, bool post_sq) 4230 { 4231 enum irdma_status_code ret_code; 4232 4233 ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq); 4234 if (ret_code) 4235 return ret_code; 4236 4237 if (post_sq) { 4238 ret_code = irdma_sc_ccq_create_done(ccq); 4239 if (ret_code) 4240 return ret_code; 4241 } 4242 ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd; 4243 4244 return 0; 4245 } 4246 4247 /** 4248 * irdma_sc_ccq_destroy - destroy ccq during close 4249 * @ccq: ccq sc struct 4250 * @scratch: u64 saved to be used during cqp completion 4251 * @post_sq: flag for cqp db to ring 4252 */ 4253 enum irdma_status_code irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, 4254 bool post_sq) 4255 { 4256 struct irdma_sc_cqp *cqp; 4257 __le64 *wqe; 4258 u64 hdr; 4259 enum irdma_status_code ret_code = 0; 4260 u32 tail, val, error; 4261 4262 cqp = ccq->dev->cqp; 4263 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4264 if (!wqe) 4265 return IRDMA_ERR_RING_FULL; 4266 4267 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); 4268 set_64bit_val(wqe, 8, (uintptr_t)ccq >> 1); 4269 set_64bit_val(wqe, 40, ccq->shadow_area_pa); 4270 4271 hdr = ccq->cq_uk.cq_id | 4272 FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0), 4273 IRDMA_CQPSQ_CQ_CEQID) | 4274 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | 4275 FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) | 4276 FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) | 4277 FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) | 4278 FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) | 4279 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4280 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4281 4282 set_64bit_val(wqe, 24, hdr); 4283 4284 print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 4285 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4286 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4287 4288 if (post_sq) { 4289 irdma_sc_cqp_post_sq(cqp); 4290 ret_code = irdma_cqp_poll_registers(cqp, tail, 4291 cqp->dev->hw_attrs.max_done_count); 4292 } 4293 4294 cqp->process_cqp_sds = irdma_update_sds_noccq; 4295 4296 return ret_code; 4297 } 4298 4299 /** 4300 * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info 4301 * @dev : ptr to irdma_dev struct 4302 * @hmc_fn_id: hmc function id 4303 */ 4304 enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, 4305 u8 hmc_fn_id) 4306 { 4307 struct irdma_hmc_info *hmc_info; 4308 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 4309 struct irdma_dma_mem query_fpm_mem; 4310 enum irdma_status_code ret_code = 0; 4311 u8 wait_type; 4312 4313 hmc_info = dev->hmc_info; 4314 hmc_fpm_misc = &dev->hmc_fpm_misc; 4315 query_fpm_mem.pa = dev->fpm_query_buf_pa; 4316 query_fpm_mem.va = dev->fpm_query_buf; 4317 hmc_info->hmc_fn_id = hmc_fn_id; 4318 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 4319 4320 ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 4321 &query_fpm_mem, true, wait_type); 4322 if (ret_code) 4323 return ret_code; 4324 4325 /* parse the fpm_query_buf and fill hmc obj info */ 4326 ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info, 4327 hmc_fpm_misc); 4328 4329 print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4330 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE, 4331 false); 4332 return ret_code; 4333 } 4334 4335 /** 4336 * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp 4337 * command and populates fpm base address in hmc_info 4338 * @dev : ptr to irdma_dev struct 4339 * @hmc_fn_id: hmc function id 4340 */ 4341 static enum irdma_status_code irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, 4342 u8 hmc_fn_id) 4343 { 4344 struct irdma_hmc_info *hmc_info; 4345 struct irdma_hmc_obj_info *obj_info; 4346 __le64 *buf; 4347 struct irdma_dma_mem commit_fpm_mem; 4348 enum irdma_status_code ret_code = 0; 4349 u8 wait_type; 4350 4351 hmc_info = dev->hmc_info; 4352 obj_info = hmc_info->hmc_obj; 4353 buf = dev->fpm_commit_buf; 4354 4355 set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt); 4356 set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt); 4357 set_64bit_val(buf, 16, (u64)0); /* RSRVD */ 4358 set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt); 4359 set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt); 4360 set_64bit_val(buf, 40, (u64)0); /* RSVD */ 4361 set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt); 4362 set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt); 4363 set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt); 4364 set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt); 4365 set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt); 4366 set_64bit_val(buf, 88, 4367 (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt); 4368 set_64bit_val(buf, 96, 4369 (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt); 4370 set_64bit_val(buf, 104, 4371 (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt); 4372 set_64bit_val(buf, 112, 4373 (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt); 4374 set_64bit_val(buf, 120, (u64)0); /* RSVD */ 4375 set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt); 4376 set_64bit_val(buf, 136, 4377 (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt); 4378 set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt); 4379 set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt); 4380 set_64bit_val(buf, 160, 4381 (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt); 4382 set_64bit_val(buf, 168, 4383 (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt); 4384 4385 commit_fpm_mem.pa = dev->fpm_commit_buf_pa; 4386 commit_fpm_mem.va = dev->fpm_commit_buf; 4387 4388 wait_type = (u8)IRDMA_CQP_WAIT_POLL_REGS; 4389 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4390 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 4391 false); 4392 ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, 4393 &commit_fpm_mem, true, wait_type); 4394 if (!ret_code) 4395 irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, 4396 hmc_info->hmc_obj, 4397 &hmc_info->sd_table.sd_cnt); 4398 print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, 4399 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, 4400 false); 4401 4402 return ret_code; 4403 } 4404 4405 /** 4406 * cqp_sds_wqe_fill - fill cqp wqe doe sd 4407 * @cqp: struct for cqp hw 4408 * @info: sd info for wqe 4409 * @scratch: u64 saved to be used during cqp completion 4410 */ 4411 static enum irdma_status_code 4412 cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, struct irdma_update_sds_info *info, 4413 u64 scratch) 4414 { 4415 u64 data; 4416 u64 hdr; 4417 __le64 *wqe; 4418 int mem_entries, wqe_entries; 4419 struct irdma_dma_mem *sdbuf = &cqp->sdbuf; 4420 u64 offset = 0; 4421 u32 wqe_idx; 4422 4423 wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); 4424 if (!wqe) 4425 return IRDMA_ERR_RING_FULL; 4426 4427 wqe_entries = (info->cnt > 3) ? 3 : info->cnt; 4428 mem_entries = info->cnt - wqe_entries; 4429 4430 if (mem_entries) { 4431 offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE; 4432 memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4); 4433 4434 data = (u64)sdbuf->pa + offset; 4435 } else { 4436 data = 0; 4437 } 4438 data |= FIELD_PREP(IRDMA_CQPSQ_UPESD_HMCFNID, info->hmc_fn_id); 4439 set_64bit_val(wqe, 16, data); 4440 4441 switch (wqe_entries) { 4442 case 3: 4443 set_64bit_val(wqe, 48, 4444 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) | 4445 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 4446 4447 set_64bit_val(wqe, 56, info->entry[2].data); 4448 fallthrough; 4449 case 2: 4450 set_64bit_val(wqe, 32, 4451 (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) | 4452 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); 4453 4454 set_64bit_val(wqe, 40, info->entry[1].data); 4455 fallthrough; 4456 case 1: 4457 set_64bit_val(wqe, 0, 4458 FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd)); 4459 4460 set_64bit_val(wqe, 8, info->entry[0].data); 4461 break; 4462 default: 4463 break; 4464 } 4465 4466 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) | 4467 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | 4468 FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries); 4469 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4470 4471 set_64bit_val(wqe, 24, hdr); 4472 4473 if (mem_entries) 4474 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer", 4475 DUMP_PREFIX_OFFSET, 16, 8, 4476 (char *)sdbuf->va + offset, 4477 mem_entries << 4, false); 4478 4479 print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16, 4480 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4481 4482 return 0; 4483 } 4484 4485 /** 4486 * irdma_update_pe_sds - cqp wqe for sd 4487 * @dev: ptr to irdma_dev struct 4488 * @info: sd info for sd's 4489 * @scratch: u64 saved to be used during cqp completion 4490 */ 4491 static enum irdma_status_code 4492 irdma_update_pe_sds(struct irdma_sc_dev *dev, 4493 struct irdma_update_sds_info *info, u64 scratch) 4494 { 4495 struct irdma_sc_cqp *cqp = dev->cqp; 4496 enum irdma_status_code ret_code; 4497 4498 ret_code = cqp_sds_wqe_fill(cqp, info, scratch); 4499 if (!ret_code) 4500 irdma_sc_cqp_post_sq(cqp); 4501 4502 return ret_code; 4503 } 4504 4505 /** 4506 * irdma_update_sds_noccq - update sd before ccq created 4507 * @dev: sc device struct 4508 * @info: sd info for sd's 4509 */ 4510 enum irdma_status_code 4511 irdma_update_sds_noccq(struct irdma_sc_dev *dev, 4512 struct irdma_update_sds_info *info) 4513 { 4514 u32 error, val, tail; 4515 struct irdma_sc_cqp *cqp = dev->cqp; 4516 enum irdma_status_code ret_code; 4517 4518 ret_code = cqp_sds_wqe_fill(cqp, info, 0); 4519 if (ret_code) 4520 return ret_code; 4521 4522 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4523 4524 irdma_sc_cqp_post_sq(cqp); 4525 return irdma_cqp_poll_registers(cqp, tail, 4526 cqp->dev->hw_attrs.max_done_count); 4527 } 4528 4529 /** 4530 * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages 4531 * @cqp: struct for cqp hw 4532 * @scratch: u64 saved to be used during cqp completion 4533 * @hmc_fn_id: hmc function id 4534 * @post_sq: flag for cqp db to ring 4535 * @poll_registers: flag to poll register for cqp completion 4536 */ 4537 enum irdma_status_code 4538 irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, 4539 u8 hmc_fn_id, bool post_sq, 4540 bool poll_registers) 4541 { 4542 u64 hdr; 4543 __le64 *wqe; 4544 u32 tail, val, error; 4545 4546 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4547 if (!wqe) 4548 return IRDMA_ERR_RING_FULL; 4549 4550 set_64bit_val(wqe, 16, 4551 FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id)); 4552 4553 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, 4554 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) | 4555 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); 4556 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4557 4558 set_64bit_val(wqe, 24, hdr); 4559 4560 print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE", 4561 DUMP_PREFIX_OFFSET, 16, 8, wqe, 4562 IRDMA_CQP_WQE_SIZE * 8, false); 4563 irdma_get_cqp_reg_info(cqp, &val, &tail, &error); 4564 4565 if (post_sq) { 4566 irdma_sc_cqp_post_sq(cqp); 4567 if (poll_registers) 4568 /* check for cqp sq tail update */ 4569 return irdma_cqp_poll_registers(cqp, tail, 4570 cqp->dev->hw_attrs.max_done_count); 4571 else 4572 return irdma_sc_poll_for_cqp_op_done(cqp, 4573 IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, 4574 NULL); 4575 } 4576 4577 return 0; 4578 } 4579 4580 /** 4581 * irdma_cqp_ring_full - check if cqp ring is full 4582 * @cqp: struct for cqp hw 4583 */ 4584 static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp) 4585 { 4586 return IRDMA_RING_FULL_ERR(cqp->sq_ring); 4587 } 4588 4589 /** 4590 * irdma_est_sd - returns approximate number of SDs for HMC 4591 * @dev: sc device struct 4592 * @hmc_info: hmc structure, size and count for HMC objects 4593 */ 4594 static u32 irdma_est_sd(struct irdma_sc_dev *dev, 4595 struct irdma_hmc_info *hmc_info) 4596 { 4597 int i; 4598 u64 size = 0; 4599 u64 sd; 4600 4601 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 4602 if (i != IRDMA_HMC_IW_PBLE) 4603 size += round_up(hmc_info->hmc_obj[i].cnt * 4604 hmc_info->hmc_obj[i].size, 512); 4605 size += round_up(hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt * 4606 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].size, 512); 4607 if (size & 0x1FFFFF) 4608 sd = (size >> 21) + 1; /* add 1 for remainder */ 4609 else 4610 sd = size >> 21; 4611 if (sd > 0xFFFFFFFF) { 4612 ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd); 4613 sd = 0xFFFFFFFF - 1; 4614 } 4615 4616 return (u32)sd; 4617 } 4618 4619 /** 4620 * irdma_sc_query_rdma_features_done - poll cqp for query features done 4621 * @cqp: struct for cqp hw 4622 */ 4623 static enum irdma_status_code 4624 irdma_sc_query_rdma_features_done(struct irdma_sc_cqp *cqp) 4625 { 4626 return irdma_sc_poll_for_cqp_op_done(cqp, 4627 IRDMA_CQP_OP_QUERY_RDMA_FEATURES, 4628 NULL); 4629 } 4630 4631 /** 4632 * irdma_sc_query_rdma_features - query RDMA features and FW ver 4633 * @cqp: struct for cqp hw 4634 * @buf: buffer to hold query info 4635 * @scratch: u64 saved to be used during cqp completion 4636 */ 4637 static enum irdma_status_code 4638 irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp, 4639 struct irdma_dma_mem *buf, u64 scratch) 4640 { 4641 __le64 *wqe; 4642 u64 temp; 4643 4644 wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); 4645 if (!wqe) 4646 return IRDMA_ERR_RING_FULL; 4647 4648 temp = buf->pa; 4649 set_64bit_val(wqe, 32, temp); 4650 4651 temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID, 4652 cqp->polarity) | 4653 FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) | 4654 FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES); 4655 dma_wmb(); /* make sure WQE is written before valid bit is set */ 4656 4657 set_64bit_val(wqe, 24, temp); 4658 4659 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 4660 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); 4661 irdma_sc_cqp_post_sq(cqp); 4662 4663 return 0; 4664 } 4665 4666 /** 4667 * irdma_get_rdma_features - get RDMA features 4668 * @dev: sc device struct 4669 */ 4670 enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev) 4671 { 4672 enum irdma_status_code ret_code; 4673 struct irdma_dma_mem feat_buf; 4674 u64 temp; 4675 u16 byte_idx, feat_type, feat_cnt, feat_idx; 4676 4677 feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE, 4678 IRDMA_FEATURE_BUF_ALIGNMENT); 4679 feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size, 4680 &feat_buf.pa, GFP_KERNEL); 4681 if (!feat_buf.va) 4682 return IRDMA_ERR_NO_MEMORY; 4683 4684 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 4685 if (!ret_code) 4686 ret_code = irdma_sc_query_rdma_features_done(dev->cqp); 4687 if (ret_code) 4688 goto exit; 4689 4690 get_64bit_val(feat_buf.va, 0, &temp); 4691 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 4692 if (feat_cnt < 2) { 4693 ret_code = IRDMA_ERR_INVALID_FEAT_CNT; 4694 goto exit; 4695 } else if (feat_cnt > IRDMA_MAX_FEATURES) { 4696 ibdev_dbg(to_ibdev(dev), 4697 "DEV: feature buf size insufficient, retrying with larger buffer\n"); 4698 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 4699 feat_buf.pa); 4700 feat_buf.va = NULL; 4701 feat_buf.size = ALIGN(8 * feat_cnt, 4702 IRDMA_FEATURE_BUF_ALIGNMENT); 4703 feat_buf.va = dma_alloc_coherent(dev->hw->device, 4704 feat_buf.size, &feat_buf.pa, 4705 GFP_KERNEL); 4706 if (!feat_buf.va) 4707 return IRDMA_ERR_NO_MEMORY; 4708 4709 ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); 4710 if (!ret_code) 4711 ret_code = irdma_sc_query_rdma_features_done(dev->cqp); 4712 if (ret_code) 4713 goto exit; 4714 4715 get_64bit_val(feat_buf.va, 0, &temp); 4716 feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); 4717 if (feat_cnt < 2) { 4718 ret_code = IRDMA_ERR_INVALID_FEAT_CNT; 4719 goto exit; 4720 } 4721 } 4722 4723 print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, 4724 16, 8, feat_buf.va, feat_cnt * 8, false); 4725 4726 for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES); 4727 feat_idx++, byte_idx += 8) { 4728 get_64bit_val(feat_buf.va, byte_idx, &temp); 4729 feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp); 4730 if (feat_type >= IRDMA_MAX_FEATURES) { 4731 ibdev_dbg(to_ibdev(dev), 4732 "DEV: found unrecognized feature type %d\n", 4733 feat_type); 4734 continue; 4735 } 4736 dev->feature_info[feat_type] = temp; 4737 } 4738 exit: 4739 dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, 4740 feat_buf.pa); 4741 feat_buf.va = NULL; 4742 return ret_code; 4743 } 4744 4745 static u32 irdma_q1_cnt(struct irdma_sc_dev *dev, 4746 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4747 { 4748 u32 q1_cnt; 4749 4750 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { 4751 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted); 4752 } else { 4753 if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) 4754 q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512); 4755 else 4756 q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted; 4757 } 4758 4759 return q1_cnt; 4760 } 4761 4762 static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev, 4763 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4764 { 4765 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes); 4766 } 4767 4768 static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev, 4769 struct irdma_hmc_info *hmc_info, u32 qpwanted) 4770 { 4771 struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; 4772 4773 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = 4774 4 * hmc_fpm_misc->xf_block_size * qpwanted; 4775 4776 hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; 4777 4778 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt) 4779 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted; 4780 if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 4781 hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = 4782 hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 4783 hmc_fpm_misc->rrf_block_size; 4784 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt) 4785 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted; 4786 if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt) 4787 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt = 4788 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt / 4789 hmc_fpm_misc->ooiscf_block_size; 4790 } 4791 4792 /** 4793 * irdma_cfg_fpm_val - configure HMC objects 4794 * @dev: sc device struct 4795 * @qp_count: desired qp count 4796 */ 4797 enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count) 4798 { 4799 struct irdma_virt_mem virt_mem; 4800 u32 i, mem_size; 4801 u32 qpwanted, mrwanted, pblewanted; 4802 u32 powerof2, hte; 4803 u32 sd_needed; 4804 u32 sd_diff; 4805 u32 loop_count = 0; 4806 struct irdma_hmc_info *hmc_info; 4807 struct irdma_hmc_fpm_misc *hmc_fpm_misc; 4808 enum irdma_status_code ret_code = 0; 4809 4810 hmc_info = dev->hmc_info; 4811 hmc_fpm_misc = &dev->hmc_fpm_misc; 4812 4813 ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id); 4814 if (ret_code) { 4815 ibdev_dbg(to_ibdev(dev), 4816 "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n", 4817 ret_code); 4818 return ret_code; 4819 } 4820 4821 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 4822 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 4823 sd_needed = irdma_est_sd(dev, hmc_info); 4824 ibdev_dbg(to_ibdev(dev), 4825 "HMC: FW max resources sd_needed[%08d] first_sd_index[%04d]\n", 4826 sd_needed, hmc_info->first_sd_index); 4827 ibdev_dbg(to_ibdev(dev), "HMC: sd count %d where max sd is %d\n", 4828 hmc_info->sd_table.sd_cnt, hmc_fpm_misc->max_sds); 4829 4830 qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt); 4831 4832 powerof2 = 1; 4833 while (powerof2 <= qpwanted) 4834 powerof2 *= 2; 4835 powerof2 /= 2; 4836 qpwanted = powerof2; 4837 4838 mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; 4839 pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; 4840 4841 ibdev_dbg(to_ibdev(dev), 4842 "HMC: req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d, mc=%d, av=%d\n", 4843 qp_count, hmc_fpm_misc->max_sds, 4844 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt, 4845 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt, 4846 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, 4847 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, 4848 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, 4849 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 4850 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = 4851 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; 4852 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = 4853 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt; 4854 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt = 4855 hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt; 4856 4857 hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1; 4858 4859 while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt) 4860 qpwanted /= 2; 4861 4862 do { 4863 ++loop_count; 4864 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; 4865 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = 4866 min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt); 4867 hmc_info->hmc_obj[IRDMA_HMC_IW_RESERVED].cnt = 0; /* Reserved */ 4868 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; 4869 4870 hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512); 4871 powerof2 = 1; 4872 while (powerof2 < hte) 4873 powerof2 *= 2; 4874 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt = 4875 powerof2 * hmc_fpm_misc->ht_multiplier; 4876 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 4877 cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); 4878 else 4879 cfg_fpm_value_gen_2(dev, hmc_info, qpwanted); 4880 4881 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted); 4882 hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = 4883 hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; 4884 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = 4885 hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 4886 hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = 4887 (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket; 4888 4889 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 4890 sd_needed = irdma_est_sd(dev, hmc_info); 4891 ibdev_dbg(to_ibdev(dev), 4892 "HMC: sd_needed = %d, hmc_fpm_misc->max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n", 4893 sd_needed, hmc_fpm_misc->max_sds, mrwanted, 4894 pblewanted, qpwanted); 4895 4896 /* Do not reduce resources further. All objects fit with max SDs */ 4897 if (sd_needed <= hmc_fpm_misc->max_sds) 4898 break; 4899 4900 sd_diff = sd_needed - hmc_fpm_misc->max_sds; 4901 if (sd_diff > 128) { 4902 if (qpwanted > 128 && sd_diff > 144) 4903 qpwanted /= 2; 4904 mrwanted /= 2; 4905 pblewanted /= 2; 4906 continue; 4907 } 4908 if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF && 4909 pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) { 4910 pblewanted -= 256 * FPM_MULTIPLIER * sd_diff; 4911 continue; 4912 } else if (pblewanted > (100 * FPM_MULTIPLIER)) { 4913 pblewanted -= 10 * FPM_MULTIPLIER; 4914 } else if (pblewanted > FPM_MULTIPLIER) { 4915 pblewanted -= FPM_MULTIPLIER; 4916 } else if (qpwanted <= 128) { 4917 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256) 4918 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2; 4919 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 4920 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 4921 } 4922 if (mrwanted > FPM_MULTIPLIER) 4923 mrwanted -= FPM_MULTIPLIER; 4924 if (!(loop_count % 10) && qpwanted > 128) { 4925 qpwanted /= 2; 4926 if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) 4927 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; 4928 } 4929 } while (loop_count < 2000); 4930 4931 if (sd_needed > hmc_fpm_misc->max_sds) { 4932 ibdev_dbg(to_ibdev(dev), 4933 "HMC: cfg_fpm failed loop_cnt=%d, sd_needed=%d, max sd count %d\n", 4934 loop_count, sd_needed, hmc_info->sd_table.sd_cnt); 4935 return IRDMA_ERR_CFG; 4936 } 4937 4938 if (loop_count > 1 && sd_needed < hmc_fpm_misc->max_sds) { 4939 pblewanted += (hmc_fpm_misc->max_sds - sd_needed) * 256 * 4940 FPM_MULTIPLIER; 4941 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 4942 sd_needed = irdma_est_sd(dev, hmc_info); 4943 } 4944 4945 ibdev_dbg(to_ibdev(dev), 4946 "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n", 4947 loop_count, sd_needed, 4948 hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt, 4949 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 4950 hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt, 4951 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt, 4952 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 4953 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt, 4954 hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index); 4955 4956 ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); 4957 if (ret_code) { 4958 ibdev_dbg(to_ibdev(dev), 4959 "HMC: cfg_iw_fpm returned error_code[x%08X]\n", 4960 readl(dev->hw_regs[IRDMA_CQPERRCODES])); 4961 return ret_code; 4962 } 4963 4964 mem_size = sizeof(struct irdma_hmc_sd_entry) * 4965 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1); 4966 virt_mem.size = mem_size; 4967 virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); 4968 if (!virt_mem.va) { 4969 ibdev_dbg(to_ibdev(dev), 4970 "HMC: failed to allocate memory for sd_entry buffer\n"); 4971 return IRDMA_ERR_NO_MEMORY; 4972 } 4973 hmc_info->sd_table.sd_entry = virt_mem.va; 4974 4975 return ret_code; 4976 } 4977 4978 /** 4979 * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available 4980 * @dev: rdma device 4981 * @pcmdinfo: cqp command info 4982 */ 4983 static enum irdma_status_code irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, 4984 struct cqp_cmds_info *pcmdinfo) 4985 { 4986 enum irdma_status_code status; 4987 struct irdma_dma_mem val_mem; 4988 bool alloc = false; 4989 4990 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; 4991 switch (pcmdinfo->cqp_cmd) { 4992 case IRDMA_OP_CEQ_DESTROY: 4993 status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, 4994 pcmdinfo->in.u.ceq_destroy.scratch, 4995 pcmdinfo->post_sq); 4996 break; 4997 case IRDMA_OP_AEQ_DESTROY: 4998 status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, 4999 pcmdinfo->in.u.aeq_destroy.scratch, 5000 pcmdinfo->post_sq); 5001 5002 break; 5003 case IRDMA_OP_CEQ_CREATE: 5004 status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, 5005 pcmdinfo->in.u.ceq_create.scratch, 5006 pcmdinfo->post_sq); 5007 break; 5008 case IRDMA_OP_AEQ_CREATE: 5009 status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, 5010 pcmdinfo->in.u.aeq_create.scratch, 5011 pcmdinfo->post_sq); 5012 break; 5013 case IRDMA_OP_QP_UPLOAD_CONTEXT: 5014 status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev, 5015 &pcmdinfo->in.u.qp_upload_context.info, 5016 pcmdinfo->in.u.qp_upload_context.scratch, 5017 pcmdinfo->post_sq); 5018 break; 5019 case IRDMA_OP_CQ_CREATE: 5020 status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq, 5021 pcmdinfo->in.u.cq_create.scratch, 5022 pcmdinfo->in.u.cq_create.check_overflow, 5023 pcmdinfo->post_sq); 5024 break; 5025 case IRDMA_OP_CQ_MODIFY: 5026 status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq, 5027 &pcmdinfo->in.u.cq_modify.info, 5028 pcmdinfo->in.u.cq_modify.scratch, 5029 pcmdinfo->post_sq); 5030 break; 5031 case IRDMA_OP_CQ_DESTROY: 5032 status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq, 5033 pcmdinfo->in.u.cq_destroy.scratch, 5034 pcmdinfo->post_sq); 5035 break; 5036 case IRDMA_OP_QP_FLUSH_WQES: 5037 status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp, 5038 &pcmdinfo->in.u.qp_flush_wqes.info, 5039 pcmdinfo->in.u.qp_flush_wqes.scratch, 5040 pcmdinfo->post_sq); 5041 break; 5042 case IRDMA_OP_GEN_AE: 5043 status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp, 5044 &pcmdinfo->in.u.gen_ae.info, 5045 pcmdinfo->in.u.gen_ae.scratch, 5046 pcmdinfo->post_sq); 5047 break; 5048 case IRDMA_OP_MANAGE_PUSH_PAGE: 5049 status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp, 5050 &pcmdinfo->in.u.manage_push_page.info, 5051 pcmdinfo->in.u.manage_push_page.scratch, 5052 pcmdinfo->post_sq); 5053 break; 5054 case IRDMA_OP_UPDATE_PE_SDS: 5055 status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev, 5056 &pcmdinfo->in.u.update_pe_sds.info, 5057 pcmdinfo->in.u.update_pe_sds.scratch); 5058 break; 5059 case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE: 5060 /* switch to calling through the call table */ 5061 status = 5062 irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp, 5063 &pcmdinfo->in.u.manage_hmc_pm.info, 5064 pcmdinfo->in.u.manage_hmc_pm.scratch, 5065 true); 5066 break; 5067 case IRDMA_OP_SUSPEND: 5068 status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp, 5069 pcmdinfo->in.u.suspend_resume.qp, 5070 pcmdinfo->in.u.suspend_resume.scratch); 5071 break; 5072 case IRDMA_OP_RESUME: 5073 status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp, 5074 pcmdinfo->in.u.suspend_resume.qp, 5075 pcmdinfo->in.u.suspend_resume.scratch); 5076 break; 5077 case IRDMA_OP_QUERY_FPM_VAL: 5078 val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa; 5079 val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va; 5080 status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp, 5081 pcmdinfo->in.u.query_fpm_val.scratch, 5082 pcmdinfo->in.u.query_fpm_val.hmc_fn_id, 5083 &val_mem, true, IRDMA_CQP_WAIT_EVENT); 5084 break; 5085 case IRDMA_OP_COMMIT_FPM_VAL: 5086 val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa; 5087 val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va; 5088 status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp, 5089 pcmdinfo->in.u.commit_fpm_val.scratch, 5090 pcmdinfo->in.u.commit_fpm_val.hmc_fn_id, 5091 &val_mem, 5092 true, 5093 IRDMA_CQP_WAIT_EVENT); 5094 break; 5095 case IRDMA_OP_STATS_ALLOCATE: 5096 alloc = true; 5097 fallthrough; 5098 case IRDMA_OP_STATS_FREE: 5099 status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp, 5100 &pcmdinfo->in.u.stats_manage.info, 5101 alloc, 5102 pcmdinfo->in.u.stats_manage.scratch); 5103 break; 5104 case IRDMA_OP_STATS_GATHER: 5105 status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp, 5106 &pcmdinfo->in.u.stats_gather.info, 5107 pcmdinfo->in.u.stats_gather.scratch); 5108 break; 5109 case IRDMA_OP_WS_MODIFY_NODE: 5110 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5111 &pcmdinfo->in.u.ws_node.info, 5112 IRDMA_MODIFY_NODE, 5113 pcmdinfo->in.u.ws_node.scratch); 5114 break; 5115 case IRDMA_OP_WS_DELETE_NODE: 5116 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5117 &pcmdinfo->in.u.ws_node.info, 5118 IRDMA_DEL_NODE, 5119 pcmdinfo->in.u.ws_node.scratch); 5120 break; 5121 case IRDMA_OP_WS_ADD_NODE: 5122 status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, 5123 &pcmdinfo->in.u.ws_node.info, 5124 IRDMA_ADD_NODE, 5125 pcmdinfo->in.u.ws_node.scratch); 5126 break; 5127 case IRDMA_OP_SET_UP_MAP: 5128 status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp, 5129 &pcmdinfo->in.u.up_map.info, 5130 pcmdinfo->in.u.up_map.scratch); 5131 break; 5132 case IRDMA_OP_QUERY_RDMA_FEATURES: 5133 status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp, 5134 &pcmdinfo->in.u.query_rdma.query_buff_mem, 5135 pcmdinfo->in.u.query_rdma.scratch); 5136 break; 5137 case IRDMA_OP_DELETE_ARP_CACHE_ENTRY: 5138 status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp, 5139 pcmdinfo->in.u.del_arp_cache_entry.scratch, 5140 pcmdinfo->in.u.del_arp_cache_entry.arp_index, 5141 pcmdinfo->post_sq); 5142 break; 5143 case IRDMA_OP_MANAGE_APBVT_ENTRY: 5144 status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp, 5145 &pcmdinfo->in.u.manage_apbvt_entry.info, 5146 pcmdinfo->in.u.manage_apbvt_entry.scratch, 5147 pcmdinfo->post_sq); 5148 break; 5149 case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY: 5150 status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp, 5151 &pcmdinfo->in.u.manage_qhash_table_entry.info, 5152 pcmdinfo->in.u.manage_qhash_table_entry.scratch, 5153 pcmdinfo->post_sq); 5154 break; 5155 case IRDMA_OP_QP_MODIFY: 5156 status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp, 5157 &pcmdinfo->in.u.qp_modify.info, 5158 pcmdinfo->in.u.qp_modify.scratch, 5159 pcmdinfo->post_sq); 5160 break; 5161 case IRDMA_OP_QP_CREATE: 5162 status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp, 5163 &pcmdinfo->in.u.qp_create.info, 5164 pcmdinfo->in.u.qp_create.scratch, 5165 pcmdinfo->post_sq); 5166 break; 5167 case IRDMA_OP_QP_DESTROY: 5168 status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp, 5169 pcmdinfo->in.u.qp_destroy.scratch, 5170 pcmdinfo->in.u.qp_destroy.remove_hash_idx, 5171 pcmdinfo->in.u.qp_destroy.ignore_mw_bnd, 5172 pcmdinfo->post_sq); 5173 break; 5174 case IRDMA_OP_ALLOC_STAG: 5175 status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev, 5176 &pcmdinfo->in.u.alloc_stag.info, 5177 pcmdinfo->in.u.alloc_stag.scratch, 5178 pcmdinfo->post_sq); 5179 break; 5180 case IRDMA_OP_MR_REG_NON_SHARED: 5181 status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev, 5182 &pcmdinfo->in.u.mr_reg_non_shared.info, 5183 pcmdinfo->in.u.mr_reg_non_shared.scratch, 5184 pcmdinfo->post_sq); 5185 break; 5186 case IRDMA_OP_DEALLOC_STAG: 5187 status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev, 5188 &pcmdinfo->in.u.dealloc_stag.info, 5189 pcmdinfo->in.u.dealloc_stag.scratch, 5190 pcmdinfo->post_sq); 5191 break; 5192 case IRDMA_OP_MW_ALLOC: 5193 status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev, 5194 &pcmdinfo->in.u.mw_alloc.info, 5195 pcmdinfo->in.u.mw_alloc.scratch, 5196 pcmdinfo->post_sq); 5197 break; 5198 case IRDMA_OP_ADD_ARP_CACHE_ENTRY: 5199 status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp, 5200 &pcmdinfo->in.u.add_arp_cache_entry.info, 5201 pcmdinfo->in.u.add_arp_cache_entry.scratch, 5202 pcmdinfo->post_sq); 5203 break; 5204 case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY: 5205 status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp, 5206 pcmdinfo->in.u.alloc_local_mac_entry.scratch, 5207 pcmdinfo->post_sq); 5208 break; 5209 case IRDMA_OP_ADD_LOCAL_MAC_ENTRY: 5210 status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp, 5211 &pcmdinfo->in.u.add_local_mac_entry.info, 5212 pcmdinfo->in.u.add_local_mac_entry.scratch, 5213 pcmdinfo->post_sq); 5214 break; 5215 case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY: 5216 status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp, 5217 pcmdinfo->in.u.del_local_mac_entry.scratch, 5218 pcmdinfo->in.u.del_local_mac_entry.entry_idx, 5219 pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count, 5220 pcmdinfo->post_sq); 5221 break; 5222 case IRDMA_OP_AH_CREATE: 5223 status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp, 5224 &pcmdinfo->in.u.ah_create.info, 5225 pcmdinfo->in.u.ah_create.scratch); 5226 break; 5227 case IRDMA_OP_AH_DESTROY: 5228 status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp, 5229 &pcmdinfo->in.u.ah_destroy.info, 5230 pcmdinfo->in.u.ah_destroy.scratch); 5231 break; 5232 case IRDMA_OP_MC_CREATE: 5233 status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp, 5234 &pcmdinfo->in.u.mc_create.info, 5235 pcmdinfo->in.u.mc_create.scratch); 5236 break; 5237 case IRDMA_OP_MC_DESTROY: 5238 status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp, 5239 &pcmdinfo->in.u.mc_destroy.info, 5240 pcmdinfo->in.u.mc_destroy.scratch); 5241 break; 5242 case IRDMA_OP_MC_MODIFY: 5243 status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp, 5244 &pcmdinfo->in.u.mc_modify.info, 5245 pcmdinfo->in.u.mc_modify.scratch); 5246 break; 5247 default: 5248 status = IRDMA_NOT_SUPPORTED; 5249 break; 5250 } 5251 5252 return status; 5253 } 5254 5255 /** 5256 * irdma_process_cqp_cmd - process all cqp commands 5257 * @dev: sc device struct 5258 * @pcmdinfo: cqp command info 5259 */ 5260 enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev, 5261 struct cqp_cmds_info *pcmdinfo) 5262 { 5263 enum irdma_status_code status = 0; 5264 unsigned long flags; 5265 5266 spin_lock_irqsave(&dev->cqp_lock, flags); 5267 if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp)) 5268 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 5269 else 5270 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); 5271 spin_unlock_irqrestore(&dev->cqp_lock, flags); 5272 return status; 5273 } 5274 5275 /** 5276 * irdma_process_bh - called from tasklet for cqp list 5277 * @dev: sc device struct 5278 */ 5279 enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev) 5280 { 5281 enum irdma_status_code status = 0; 5282 struct cqp_cmds_info *pcmdinfo; 5283 unsigned long flags; 5284 5285 spin_lock_irqsave(&dev->cqp_lock, flags); 5286 while (!list_empty(&dev->cqp_cmd_head) && 5287 !irdma_cqp_ring_full(dev->cqp)) { 5288 pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev); 5289 status = irdma_exec_cqp_cmd(dev, pcmdinfo); 5290 if (status) 5291 break; 5292 } 5293 spin_unlock_irqrestore(&dev->cqp_lock, flags); 5294 return status; 5295 } 5296 5297 /** 5298 * irdma_cfg_aeq- Configure AEQ interrupt 5299 * @dev: pointer to the device structure 5300 * @idx: vector index 5301 * @enable: True to enable, False disables 5302 */ 5303 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable) 5304 { 5305 u32 reg_val; 5306 5307 reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) | 5308 FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) | 5309 FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, 3); 5310 writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); 5311 } 5312 5313 /** 5314 * sc_vsi_update_stats - Update statistics 5315 * @vsi: sc_vsi instance to update 5316 */ 5317 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi) 5318 { 5319 struct irdma_gather_stats *gather_stats; 5320 struct irdma_gather_stats *last_gather_stats; 5321 5322 gather_stats = vsi->pestat->gather_info.gather_stats_va; 5323 last_gather_stats = vsi->pestat->gather_info.last_gather_stats_va; 5324 irdma_update_stats(&vsi->pestat->hw_stats, gather_stats, 5325 last_gather_stats); 5326 } 5327 5328 /** 5329 * irdma_wait_pe_ready - Check if firmware is ready 5330 * @dev: provides access to registers 5331 */ 5332 static int irdma_wait_pe_ready(struct irdma_sc_dev *dev) 5333 { 5334 u32 statuscpu0; 5335 u32 statuscpu1; 5336 u32 statuscpu2; 5337 u32 retrycount = 0; 5338 5339 do { 5340 statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]); 5341 statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]); 5342 statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]); 5343 if (statuscpu0 == 0x80 && statuscpu1 == 0x80 && 5344 statuscpu2 == 0x80) 5345 return 0; 5346 mdelay(1000); 5347 } while (retrycount++ < dev->hw_attrs.max_pe_ready_count); 5348 return -1; 5349 } 5350 5351 static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) 5352 { 5353 switch (dev->hw_attrs.uk_attrs.hw_rev) { 5354 case IRDMA_GEN_1: 5355 i40iw_init_hw(dev); 5356 break; 5357 case IRDMA_GEN_2: 5358 icrdma_init_hw(dev); 5359 break; 5360 } 5361 } 5362 5363 /** 5364 * irdma_sc_dev_init - Initialize control part of device 5365 * @ver: version 5366 * @dev: Device pointer 5367 * @info: Device init info 5368 */ 5369 enum irdma_status_code irdma_sc_dev_init(enum irdma_vers ver, 5370 struct irdma_sc_dev *dev, 5371 struct irdma_device_init_info *info) 5372 { 5373 u32 val; 5374 enum irdma_status_code ret_code = 0; 5375 u8 db_size; 5376 5377 INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */ 5378 mutex_init(&dev->ws_mutex); 5379 dev->hmc_fn_id = info->hmc_fn_id; 5380 dev->fpm_query_buf_pa = info->fpm_query_buf_pa; 5381 dev->fpm_query_buf = info->fpm_query_buf; 5382 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; 5383 dev->fpm_commit_buf = info->fpm_commit_buf; 5384 dev->hw = info->hw; 5385 dev->hw->hw_addr = info->bar0; 5386 /* Setup the hardware limits, hmc may limit further */ 5387 dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID; 5388 dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES; 5389 dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES; 5390 dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES; 5391 dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES; 5392 dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE; 5393 dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE; 5394 dev->hw_attrs.uk_attrs.max_hw_wq_frags = IRDMA_MAX_WQ_FRAGMENT_COUNT; 5395 dev->hw_attrs.uk_attrs.max_hw_read_sges = IRDMA_MAX_SGE_RD; 5396 dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE; 5397 dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE; 5398 dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE; 5399 dev->hw_attrs.max_hw_device_pages = IRDMA_MAX_PUSH_PAGE_COUNT; 5400 dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE; 5401 dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES; 5402 dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR); 5403 5404 dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA; 5405 dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA; 5406 dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS; 5407 dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT; 5408 5409 dev->hw_attrs.max_pe_ready_count = 14; 5410 dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT; 5411 dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT; 5412 dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS; 5413 5414 dev->hw_attrs.uk_attrs.hw_rev = ver; 5415 irdma_sc_init_hw(dev); 5416 5417 if (irdma_wait_pe_ready(dev)) 5418 return IRDMA_ERR_TIMEOUT; 5419 5420 val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]); 5421 db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val); 5422 if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) { 5423 ibdev_dbg(to_ibdev(dev), 5424 "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n", 5425 val, db_size); 5426 return IRDMA_ERR_PE_DOORBELL_NOT_ENA; 5427 } 5428 dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET]; 5429 5430 return ret_code; 5431 } 5432 5433 /** 5434 * irdma_update_stats - Update statistics 5435 * @hw_stats: hw_stats instance to update 5436 * @gather_stats: updated stat counters 5437 * @last_gather_stats: last stat counters 5438 */ 5439 void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, 5440 struct irdma_gather_stats *gather_stats, 5441 struct irdma_gather_stats *last_gather_stats) 5442 { 5443 u64 *stats_val = hw_stats->stats_val_32; 5444 5445 stats_val[IRDMA_HW_STAT_INDEX_RXVLANERR] += 5446 IRDMA_STATS_DELTA(gather_stats->rxvlanerr, 5447 last_gather_stats->rxvlanerr, 5448 IRDMA_MAX_STATS_32); 5449 stats_val[IRDMA_HW_STAT_INDEX_IP4RXDISCARD] += 5450 IRDMA_STATS_DELTA(gather_stats->ip4rxdiscard, 5451 last_gather_stats->ip4rxdiscard, 5452 IRDMA_MAX_STATS_32); 5453 stats_val[IRDMA_HW_STAT_INDEX_IP4RXTRUNC] += 5454 IRDMA_STATS_DELTA(gather_stats->ip4rxtrunc, 5455 last_gather_stats->ip4rxtrunc, 5456 IRDMA_MAX_STATS_32); 5457 stats_val[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] += 5458 IRDMA_STATS_DELTA(gather_stats->ip4txnoroute, 5459 last_gather_stats->ip4txnoroute, 5460 IRDMA_MAX_STATS_32); 5461 stats_val[IRDMA_HW_STAT_INDEX_IP6RXDISCARD] += 5462 IRDMA_STATS_DELTA(gather_stats->ip6rxdiscard, 5463 last_gather_stats->ip6rxdiscard, 5464 IRDMA_MAX_STATS_32); 5465 stats_val[IRDMA_HW_STAT_INDEX_IP6RXTRUNC] += 5466 IRDMA_STATS_DELTA(gather_stats->ip6rxtrunc, 5467 last_gather_stats->ip6rxtrunc, 5468 IRDMA_MAX_STATS_32); 5469 stats_val[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] += 5470 IRDMA_STATS_DELTA(gather_stats->ip6txnoroute, 5471 last_gather_stats->ip6txnoroute, 5472 IRDMA_MAX_STATS_32); 5473 stats_val[IRDMA_HW_STAT_INDEX_TCPRTXSEG] += 5474 IRDMA_STATS_DELTA(gather_stats->tcprtxseg, 5475 last_gather_stats->tcprtxseg, 5476 IRDMA_MAX_STATS_32); 5477 stats_val[IRDMA_HW_STAT_INDEX_TCPRXOPTERR] += 5478 IRDMA_STATS_DELTA(gather_stats->tcprxopterr, 5479 last_gather_stats->tcprxopterr, 5480 IRDMA_MAX_STATS_32); 5481 stats_val[IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] += 5482 IRDMA_STATS_DELTA(gather_stats->tcprxprotoerr, 5483 last_gather_stats->tcprxprotoerr, 5484 IRDMA_MAX_STATS_32); 5485 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] += 5486 IRDMA_STATS_DELTA(gather_stats->rxrpcnphandled, 5487 last_gather_stats->rxrpcnphandled, 5488 IRDMA_MAX_STATS_32); 5489 stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] += 5490 IRDMA_STATS_DELTA(gather_stats->rxrpcnpignored, 5491 last_gather_stats->rxrpcnpignored, 5492 IRDMA_MAX_STATS_32); 5493 stats_val[IRDMA_HW_STAT_INDEX_TXNPCNPSENT] += 5494 IRDMA_STATS_DELTA(gather_stats->txnpcnpsent, 5495 last_gather_stats->txnpcnpsent, 5496 IRDMA_MAX_STATS_32); 5497 stats_val = hw_stats->stats_val_64; 5498 stats_val[IRDMA_HW_STAT_INDEX_IP4RXOCTS] += 5499 IRDMA_STATS_DELTA(gather_stats->ip4rxocts, 5500 last_gather_stats->ip4rxocts, 5501 IRDMA_MAX_STATS_48); 5502 stats_val[IRDMA_HW_STAT_INDEX_IP4RXPKTS] += 5503 IRDMA_STATS_DELTA(gather_stats->ip4rxpkts, 5504 last_gather_stats->ip4rxpkts, 5505 IRDMA_MAX_STATS_48); 5506 stats_val[IRDMA_HW_STAT_INDEX_IP4RXFRAGS] += 5507 IRDMA_STATS_DELTA(gather_stats->ip4txfrag, 5508 last_gather_stats->ip4txfrag, 5509 IRDMA_MAX_STATS_48); 5510 stats_val[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] += 5511 IRDMA_STATS_DELTA(gather_stats->ip4rxmcpkts, 5512 last_gather_stats->ip4rxmcpkts, 5513 IRDMA_MAX_STATS_48); 5514 stats_val[IRDMA_HW_STAT_INDEX_IP4TXOCTS] += 5515 IRDMA_STATS_DELTA(gather_stats->ip4txocts, 5516 last_gather_stats->ip4txocts, 5517 IRDMA_MAX_STATS_48); 5518 stats_val[IRDMA_HW_STAT_INDEX_IP4TXPKTS] += 5519 IRDMA_STATS_DELTA(gather_stats->ip4txpkts, 5520 last_gather_stats->ip4txpkts, 5521 IRDMA_MAX_STATS_48); 5522 stats_val[IRDMA_HW_STAT_INDEX_IP4TXFRAGS] += 5523 IRDMA_STATS_DELTA(gather_stats->ip4txfrag, 5524 last_gather_stats->ip4txfrag, 5525 IRDMA_MAX_STATS_48); 5526 stats_val[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] += 5527 IRDMA_STATS_DELTA(gather_stats->ip4txmcpkts, 5528 last_gather_stats->ip4txmcpkts, 5529 IRDMA_MAX_STATS_48); 5530 stats_val[IRDMA_HW_STAT_INDEX_IP6RXOCTS] += 5531 IRDMA_STATS_DELTA(gather_stats->ip6rxocts, 5532 last_gather_stats->ip6rxocts, 5533 IRDMA_MAX_STATS_48); 5534 stats_val[IRDMA_HW_STAT_INDEX_IP6RXPKTS] += 5535 IRDMA_STATS_DELTA(gather_stats->ip6rxpkts, 5536 last_gather_stats->ip6rxpkts, 5537 IRDMA_MAX_STATS_48); 5538 stats_val[IRDMA_HW_STAT_INDEX_IP6RXFRAGS] += 5539 IRDMA_STATS_DELTA(gather_stats->ip6txfrags, 5540 last_gather_stats->ip6txfrags, 5541 IRDMA_MAX_STATS_48); 5542 stats_val[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] += 5543 IRDMA_STATS_DELTA(gather_stats->ip6rxmcpkts, 5544 last_gather_stats->ip6rxmcpkts, 5545 IRDMA_MAX_STATS_48); 5546 stats_val[IRDMA_HW_STAT_INDEX_IP6TXOCTS] += 5547 IRDMA_STATS_DELTA(gather_stats->ip6txocts, 5548 last_gather_stats->ip6txocts, 5549 IRDMA_MAX_STATS_48); 5550 stats_val[IRDMA_HW_STAT_INDEX_IP6TXPKTS] += 5551 IRDMA_STATS_DELTA(gather_stats->ip6txpkts, 5552 last_gather_stats->ip6txpkts, 5553 IRDMA_MAX_STATS_48); 5554 stats_val[IRDMA_HW_STAT_INDEX_IP6TXFRAGS] += 5555 IRDMA_STATS_DELTA(gather_stats->ip6txfrags, 5556 last_gather_stats->ip6txfrags, 5557 IRDMA_MAX_STATS_48); 5558 stats_val[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] += 5559 IRDMA_STATS_DELTA(gather_stats->ip6txmcpkts, 5560 last_gather_stats->ip6txmcpkts, 5561 IRDMA_MAX_STATS_48); 5562 stats_val[IRDMA_HW_STAT_INDEX_TCPRXSEGS] += 5563 IRDMA_STATS_DELTA(gather_stats->tcprxsegs, 5564 last_gather_stats->tcprxsegs, 5565 IRDMA_MAX_STATS_48); 5566 stats_val[IRDMA_HW_STAT_INDEX_TCPTXSEG] += 5567 IRDMA_STATS_DELTA(gather_stats->tcptxsegs, 5568 last_gather_stats->tcptxsegs, 5569 IRDMA_MAX_STATS_48); 5570 stats_val[IRDMA_HW_STAT_INDEX_RDMARXRDS] += 5571 IRDMA_STATS_DELTA(gather_stats->rdmarxrds, 5572 last_gather_stats->rdmarxrds, 5573 IRDMA_MAX_STATS_48); 5574 stats_val[IRDMA_HW_STAT_INDEX_RDMARXSNDS] += 5575 IRDMA_STATS_DELTA(gather_stats->rdmarxsnds, 5576 last_gather_stats->rdmarxsnds, 5577 IRDMA_MAX_STATS_48); 5578 stats_val[IRDMA_HW_STAT_INDEX_RDMARXWRS] += 5579 IRDMA_STATS_DELTA(gather_stats->rdmarxwrs, 5580 last_gather_stats->rdmarxwrs, 5581 IRDMA_MAX_STATS_48); 5582 stats_val[IRDMA_HW_STAT_INDEX_RDMATXRDS] += 5583 IRDMA_STATS_DELTA(gather_stats->rdmatxrds, 5584 last_gather_stats->rdmatxrds, 5585 IRDMA_MAX_STATS_48); 5586 stats_val[IRDMA_HW_STAT_INDEX_RDMATXSNDS] += 5587 IRDMA_STATS_DELTA(gather_stats->rdmatxsnds, 5588 last_gather_stats->rdmatxsnds, 5589 IRDMA_MAX_STATS_48); 5590 stats_val[IRDMA_HW_STAT_INDEX_RDMATXWRS] += 5591 IRDMA_STATS_DELTA(gather_stats->rdmatxwrs, 5592 last_gather_stats->rdmatxwrs, 5593 IRDMA_MAX_STATS_48); 5594 stats_val[IRDMA_HW_STAT_INDEX_RDMAVBND] += 5595 IRDMA_STATS_DELTA(gather_stats->rdmavbn, 5596 last_gather_stats->rdmavbn, 5597 IRDMA_MAX_STATS_48); 5598 stats_val[IRDMA_HW_STAT_INDEX_RDMAVINV] += 5599 IRDMA_STATS_DELTA(gather_stats->rdmavinv, 5600 last_gather_stats->rdmavinv, 5601 IRDMA_MAX_STATS_48); 5602 stats_val[IRDMA_HW_STAT_INDEX_UDPRXPKTS] += 5603 IRDMA_STATS_DELTA(gather_stats->udprxpkts, 5604 last_gather_stats->udprxpkts, 5605 IRDMA_MAX_STATS_48); 5606 stats_val[IRDMA_HW_STAT_INDEX_UDPTXPKTS] += 5607 IRDMA_STATS_DELTA(gather_stats->udptxpkts, 5608 last_gather_stats->udptxpkts, 5609 IRDMA_MAX_STATS_48); 5610 stats_val[IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] += 5611 IRDMA_STATS_DELTA(gather_stats->rxnpecnmrkpkts, 5612 last_gather_stats->rxnpecnmrkpkts, 5613 IRDMA_MAX_STATS_48); 5614 memcpy(last_gather_stats, gather_stats, sizeof(*last_gather_stats)); 5615 } 5616