1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/platform_device.h> 35 #include <rdma/ib_addr.h> 36 #include <rdma/ib_umem.h> 37 #include "hns_roce_common.h" 38 #include "hns_roce_device.h" 39 #include "hns_roce_hem.h" 40 #include <rdma/hns-abi.h> 41 42 #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS) 43 44 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 45 { 46 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 47 struct device *dev = hr_dev->dev; 48 struct hns_roce_qp *qp; 49 50 spin_lock(&qp_table->lock); 51 52 qp = __hns_roce_qp_lookup(hr_dev, qpn); 53 if (qp) 54 atomic_inc(&qp->refcount); 55 56 spin_unlock(&qp_table->lock); 57 58 if (!qp) { 59 dev_warn(dev, "Async event for bogus QP %08x\n", qpn); 60 return; 61 } 62 63 qp->event(qp, (enum hns_roce_event)event_type); 64 65 if (atomic_dec_and_test(&qp->refcount)) 66 complete(&qp->free); 67 } 68 69 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, 70 enum hns_roce_event type) 71 { 72 struct ib_event event; 73 struct ib_qp *ibqp = &hr_qp->ibqp; 74 75 if (ibqp->event_handler) { 76 event.device = ibqp->device; 77 event.element.qp = ibqp; 78 switch (type) { 79 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 80 event.event = IB_EVENT_PATH_MIG; 81 break; 82 case HNS_ROCE_EVENT_TYPE_COMM_EST: 83 event.event = IB_EVENT_COMM_EST; 84 break; 85 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 86 event.event = IB_EVENT_SQ_DRAINED; 87 break; 88 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 89 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 90 break; 91 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 92 event.event = IB_EVENT_QP_FATAL; 93 break; 94 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 95 event.event = IB_EVENT_PATH_MIG_ERR; 96 break; 97 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 98 event.event = IB_EVENT_QP_REQ_ERR; 99 break; 100 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 101 event.event = IB_EVENT_QP_ACCESS_ERR; 102 break; 103 default: 104 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", 105 type, hr_qp->qpn); 106 return; 107 } 108 ibqp->event_handler(&event, ibqp->qp_context); 109 } 110 } 111 112 static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt, 113 int align, unsigned long *base) 114 { 115 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 116 117 return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align, base); 118 } 119 120 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state) 121 { 122 switch (state) { 123 case IB_QPS_RESET: 124 return HNS_ROCE_QP_STATE_RST; 125 case IB_QPS_INIT: 126 return HNS_ROCE_QP_STATE_INIT; 127 case IB_QPS_RTR: 128 return HNS_ROCE_QP_STATE_RTR; 129 case IB_QPS_RTS: 130 return HNS_ROCE_QP_STATE_RTS; 131 case IB_QPS_SQD: 132 return HNS_ROCE_QP_STATE_SQD; 133 case IB_QPS_ERR: 134 return HNS_ROCE_QP_STATE_ERR; 135 default: 136 return HNS_ROCE_QP_NUM_STATE; 137 } 138 } 139 EXPORT_SYMBOL_GPL(to_hns_roce_state); 140 141 static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn, 142 struct hns_roce_qp *hr_qp) 143 { 144 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 145 int ret; 146 147 if (!qpn) 148 return -EINVAL; 149 150 hr_qp->qpn = qpn; 151 152 spin_lock_irq(&qp_table->lock); 153 ret = radix_tree_insert(&hr_dev->qp_table_tree, 154 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 155 spin_unlock_irq(&qp_table->lock); 156 if (ret) { 157 dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n"); 158 goto err_put_irrl; 159 } 160 161 atomic_set(&hr_qp->refcount, 1); 162 init_completion(&hr_qp->free); 163 164 return 0; 165 166 err_put_irrl: 167 168 return ret; 169 } 170 171 static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn, 172 struct hns_roce_qp *hr_qp) 173 { 174 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 175 struct device *dev = hr_dev->dev; 176 int ret; 177 178 if (!qpn) 179 return -EINVAL; 180 181 hr_qp->qpn = qpn; 182 183 /* Alloc memory for QPC */ 184 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); 185 if (ret) { 186 dev_err(dev, "QPC table get failed\n"); 187 goto err_out; 188 } 189 190 /* Alloc memory for IRRL */ 191 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 192 if (ret) { 193 dev_err(dev, "IRRL table get failed\n"); 194 goto err_put_qp; 195 } 196 197 if (hr_dev->caps.trrl_entry_sz) { 198 /* Alloc memory for TRRL */ 199 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, 200 hr_qp->qpn); 201 if (ret) { 202 dev_err(dev, "TRRL table get failed\n"); 203 goto err_put_irrl; 204 } 205 } 206 207 spin_lock_irq(&qp_table->lock); 208 ret = radix_tree_insert(&hr_dev->qp_table_tree, 209 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 210 spin_unlock_irq(&qp_table->lock); 211 if (ret) { 212 dev_err(dev, "QPC radix_tree_insert failed\n"); 213 goto err_put_trrl; 214 } 215 216 atomic_set(&hr_qp->refcount, 1); 217 init_completion(&hr_qp->free); 218 219 return 0; 220 221 err_put_trrl: 222 if (hr_dev->caps.trrl_entry_sz) 223 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 224 225 err_put_irrl: 226 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 227 228 err_put_qp: 229 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 230 231 err_out: 232 return ret; 233 } 234 235 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 236 { 237 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 238 unsigned long flags; 239 240 spin_lock_irqsave(&qp_table->lock, flags); 241 radix_tree_delete(&hr_dev->qp_table_tree, 242 hr_qp->qpn & (hr_dev->caps.num_qps - 1)); 243 spin_unlock_irqrestore(&qp_table->lock, flags); 244 } 245 EXPORT_SYMBOL_GPL(hns_roce_qp_remove); 246 247 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 248 { 249 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 250 251 if (atomic_dec_and_test(&hr_qp->refcount)) 252 complete(&hr_qp->free); 253 wait_for_completion(&hr_qp->free); 254 255 if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) { 256 if (hr_dev->caps.trrl_entry_sz) 257 hns_roce_table_put(hr_dev, &qp_table->trrl_table, 258 hr_qp->qpn); 259 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 260 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 261 } 262 } 263 EXPORT_SYMBOL_GPL(hns_roce_qp_free); 264 265 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 266 int cnt) 267 { 268 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 269 270 if (base_qpn < SQP_NUM) 271 return; 272 273 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR); 274 } 275 EXPORT_SYMBOL_GPL(hns_roce_release_range_qp); 276 277 static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev, 278 struct ib_qp_cap *cap, int is_user, int has_srq, 279 struct hns_roce_qp *hr_qp) 280 { 281 struct device *dev = hr_dev->dev; 282 u32 max_cnt; 283 284 /* Check the validity of QP support capacity */ 285 if (cap->max_recv_wr > hr_dev->caps.max_wqes || 286 cap->max_recv_sge > hr_dev->caps.max_rq_sg) { 287 dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n", 288 cap->max_recv_wr, cap->max_recv_sge); 289 return -EINVAL; 290 } 291 292 /* If srq exit, set zero for relative number of rq */ 293 if (has_srq) { 294 if (cap->max_recv_wr) { 295 dev_dbg(dev, "srq no need config max_recv_wr\n"); 296 return -EINVAL; 297 } 298 299 hr_qp->rq.wqe_cnt = hr_qp->rq.max_gs = 0; 300 } else { 301 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) { 302 dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n"); 303 return -EINVAL; 304 } 305 306 if (hr_dev->caps.min_wqes) 307 max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes); 308 else 309 max_cnt = cap->max_recv_wr; 310 311 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt); 312 313 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) { 314 dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n"); 315 return -EINVAL; 316 } 317 318 max_cnt = max(1U, cap->max_recv_sge); 319 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt); 320 if (hr_dev->caps.max_rq_sg <= 2) 321 hr_qp->rq.wqe_shift = 322 ilog2(hr_dev->caps.max_rq_desc_sz); 323 else 324 hr_qp->rq.wqe_shift = 325 ilog2(hr_dev->caps.max_rq_desc_sz 326 * hr_qp->rq.max_gs); 327 } 328 329 cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt; 330 cap->max_recv_sge = hr_qp->rq.max_gs; 331 332 return 0; 333 } 334 335 static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev, 336 struct ib_qp_cap *cap, 337 struct hns_roce_qp *hr_qp, 338 struct hns_roce_ib_create_qp *ucmd) 339 { 340 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 341 u8 max_sq_stride = ilog2(roundup_sq_stride); 342 u32 page_size; 343 u32 max_cnt; 344 345 /* Sanity check SQ size before proceeding */ 346 if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes || 347 ucmd->log_sq_stride > max_sq_stride || 348 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 349 dev_err(hr_dev->dev, "check SQ size error!\n"); 350 return -EINVAL; 351 } 352 353 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { 354 dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n", 355 cap->max_send_sge); 356 return -EINVAL; 357 } 358 359 hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 360 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 361 362 max_cnt = max(1U, cap->max_send_sge); 363 if (hr_dev->caps.max_sq_sg <= 2) 364 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); 365 else 366 hr_qp->sq.max_gs = max_cnt; 367 368 if (hr_qp->sq.max_gs > 2) 369 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * 370 (hr_qp->sq.max_gs - 2)); 371 hr_qp->sge.sge_shift = 4; 372 373 /* Get buf size, SQ and RQ are aligned to page_szie */ 374 if (hr_dev->caps.max_sq_sg <= 2) { 375 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 376 hr_qp->rq.wqe_shift), PAGE_SIZE) + 377 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 378 hr_qp->sq.wqe_shift), PAGE_SIZE); 379 380 hr_qp->sq.offset = 0; 381 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 382 hr_qp->sq.wqe_shift), PAGE_SIZE); 383 } else { 384 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 385 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 386 hr_qp->rq.wqe_shift), page_size) + 387 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt << 388 hr_qp->sge.sge_shift), page_size) + 389 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 390 hr_qp->sq.wqe_shift), page_size); 391 392 hr_qp->sq.offset = 0; 393 if (hr_qp->sge.sge_cnt) { 394 hr_qp->sge.offset = HNS_ROCE_ALOGN_UP( 395 (hr_qp->sq.wqe_cnt << 396 hr_qp->sq.wqe_shift), 397 page_size); 398 hr_qp->rq.offset = hr_qp->sge.offset + 399 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt << 400 hr_qp->sge.sge_shift), 401 page_size); 402 } else { 403 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP( 404 (hr_qp->sq.wqe_cnt << 405 hr_qp->sq.wqe_shift), 406 page_size); 407 } 408 } 409 410 return 0; 411 } 412 413 static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev, 414 struct ib_qp_cap *cap, 415 struct hns_roce_qp *hr_qp) 416 { 417 struct device *dev = hr_dev->dev; 418 u32 page_size; 419 u32 max_cnt; 420 int size; 421 422 if (cap->max_send_wr > hr_dev->caps.max_wqes || 423 cap->max_send_sge > hr_dev->caps.max_sq_sg || 424 cap->max_inline_data > hr_dev->caps.max_sq_inline) { 425 dev_err(dev, "SQ WR or sge or inline data error!\n"); 426 return -EINVAL; 427 } 428 429 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); 430 hr_qp->sq_max_wqes_per_wr = 1; 431 hr_qp->sq_spare_wqes = 0; 432 433 if (hr_dev->caps.min_wqes) 434 max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes); 435 else 436 max_cnt = cap->max_send_wr; 437 438 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt); 439 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) { 440 dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n"); 441 return -EINVAL; 442 } 443 444 /* Get data_seg numbers */ 445 max_cnt = max(1U, cap->max_send_sge); 446 if (hr_dev->caps.max_sq_sg <= 2) 447 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); 448 else 449 hr_qp->sq.max_gs = max_cnt; 450 451 if (hr_qp->sq.max_gs > 2) { 452 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * 453 (hr_qp->sq.max_gs - 2)); 454 hr_qp->sge.sge_shift = 4; 455 } 456 457 /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */ 458 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 459 hr_qp->sq.offset = 0; 460 size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift, 461 page_size); 462 463 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) { 464 hr_qp->sge.offset = size; 465 size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt << 466 hr_qp->sge.sge_shift, page_size); 467 } 468 469 hr_qp->rq.offset = size; 470 size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift), 471 page_size); 472 hr_qp->buff_size = size; 473 474 /* Get wr and sge number which send */ 475 cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt; 476 cap->max_send_sge = hr_qp->sq.max_gs; 477 478 /* We don't support inline sends for kernel QPs (yet) */ 479 cap->max_inline_data = 0; 480 481 return 0; 482 } 483 484 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, 485 struct ib_pd *ib_pd, 486 struct ib_qp_init_attr *init_attr, 487 struct ib_udata *udata, unsigned long sqpn, 488 struct hns_roce_qp *hr_qp) 489 { 490 struct device *dev = hr_dev->dev; 491 struct hns_roce_ib_create_qp ucmd; 492 unsigned long qpn = 0; 493 int ret = 0; 494 u32 page_shift; 495 u32 npages; 496 497 mutex_init(&hr_qp->mutex); 498 spin_lock_init(&hr_qp->sq.lock); 499 spin_lock_init(&hr_qp->rq.lock); 500 501 hr_qp->state = IB_QPS_RESET; 502 503 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 504 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR; 505 else 506 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR; 507 508 ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, !!ib_pd->uobject, 509 !!init_attr->srq, hr_qp); 510 if (ret) { 511 dev_err(dev, "hns_roce_set_rq_size failed\n"); 512 goto err_out; 513 } 514 515 if (ib_pd->uobject) { 516 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 517 dev_err(dev, "ib_copy_from_udata error for create qp\n"); 518 ret = -EFAULT; 519 goto err_out; 520 } 521 522 ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, 523 &ucmd); 524 if (ret) { 525 dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n"); 526 goto err_out; 527 } 528 529 hr_qp->umem = ib_umem_get(ib_pd->uobject->context, 530 ucmd.buf_addr, hr_qp->buff_size, 0, 531 0); 532 if (IS_ERR(hr_qp->umem)) { 533 dev_err(dev, "ib_umem_get error for create qp\n"); 534 ret = PTR_ERR(hr_qp->umem); 535 goto err_out; 536 } 537 538 hr_qp->mtt.mtt_type = MTT_TYPE_WQE; 539 if (hr_dev->caps.mtt_buf_pg_sz) { 540 npages = (ib_umem_page_count(hr_qp->umem) + 541 (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) / 542 (1 << hr_dev->caps.mtt_buf_pg_sz); 543 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 544 ret = hns_roce_mtt_init(hr_dev, npages, 545 page_shift, 546 &hr_qp->mtt); 547 } else { 548 ret = hns_roce_mtt_init(hr_dev, 549 ib_umem_page_count(hr_qp->umem), 550 hr_qp->umem->page_shift, 551 &hr_qp->mtt); 552 } 553 if (ret) { 554 dev_err(dev, "hns_roce_mtt_init error for create qp\n"); 555 goto err_buf; 556 } 557 558 ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt, 559 hr_qp->umem); 560 if (ret) { 561 dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n"); 562 goto err_mtt; 563 } 564 } else { 565 if (init_attr->create_flags & 566 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 567 dev_err(dev, "init_attr->create_flags error!\n"); 568 ret = -EINVAL; 569 goto err_out; 570 } 571 572 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) { 573 dev_err(dev, "init_attr->create_flags error!\n"); 574 ret = -EINVAL; 575 goto err_out; 576 } 577 578 /* Set SQ size */ 579 ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap, 580 hr_qp); 581 if (ret) { 582 dev_err(dev, "hns_roce_set_kernel_sq_size error!\n"); 583 goto err_out; 584 } 585 586 /* QP doorbell register address */ 587 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + 588 DB_REG_OFFSET * hr_dev->priv_uar.index; 589 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + 590 DB_REG_OFFSET * hr_dev->priv_uar.index; 591 592 /* Allocate QP buf */ 593 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 594 if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size, 595 (1 << page_shift) * 2, 596 &hr_qp->hr_buf, page_shift)) { 597 dev_err(dev, "hns_roce_buf_alloc error!\n"); 598 ret = -ENOMEM; 599 goto err_out; 600 } 601 602 hr_qp->mtt.mtt_type = MTT_TYPE_WQE; 603 /* Write MTT */ 604 ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages, 605 hr_qp->hr_buf.page_shift, &hr_qp->mtt); 606 if (ret) { 607 dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n"); 608 goto err_buf; 609 } 610 611 ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt, 612 &hr_qp->hr_buf); 613 if (ret) { 614 dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n"); 615 goto err_mtt; 616 } 617 618 hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64), 619 GFP_KERNEL); 620 hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64), 621 GFP_KERNEL); 622 if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) { 623 ret = -ENOMEM; 624 goto err_wrid; 625 } 626 } 627 628 if (sqpn) { 629 qpn = sqpn; 630 } else { 631 /* Get QPN */ 632 ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn); 633 if (ret) { 634 dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n"); 635 goto err_wrid; 636 } 637 } 638 639 if (init_attr->qp_type == IB_QPT_GSI && 640 hr_dev->hw_rev == HNS_ROCE_HW_VER1) { 641 /* In v1 engine, GSI QP context in RoCE engine's register */ 642 ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp); 643 if (ret) { 644 dev_err(dev, "hns_roce_qp_alloc failed!\n"); 645 goto err_qpn; 646 } 647 } else { 648 ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp); 649 if (ret) { 650 dev_err(dev, "hns_roce_qp_alloc failed!\n"); 651 goto err_qpn; 652 } 653 } 654 655 if (sqpn) 656 hr_qp->doorbell_qpn = 1; 657 else 658 hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn); 659 660 hr_qp->event = hns_roce_ib_qp_event; 661 662 return 0; 663 664 err_qpn: 665 if (!sqpn) 666 hns_roce_release_range_qp(hr_dev, qpn, 1); 667 668 err_wrid: 669 kfree(hr_qp->sq.wrid); 670 kfree(hr_qp->rq.wrid); 671 672 err_mtt: 673 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 674 675 err_buf: 676 if (ib_pd->uobject) 677 ib_umem_release(hr_qp->umem); 678 else 679 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 680 681 err_out: 682 return ret; 683 } 684 685 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, 686 struct ib_qp_init_attr *init_attr, 687 struct ib_udata *udata) 688 { 689 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); 690 struct device *dev = hr_dev->dev; 691 struct hns_roce_sqp *hr_sqp; 692 struct hns_roce_qp *hr_qp; 693 int ret; 694 695 switch (init_attr->qp_type) { 696 case IB_QPT_RC: { 697 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 698 if (!hr_qp) 699 return ERR_PTR(-ENOMEM); 700 701 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0, 702 hr_qp); 703 if (ret) { 704 dev_err(dev, "Create RC QP failed\n"); 705 kfree(hr_qp); 706 return ERR_PTR(ret); 707 } 708 709 hr_qp->ibqp.qp_num = hr_qp->qpn; 710 711 break; 712 } 713 case IB_QPT_GSI: { 714 /* Userspace is not allowed to create special QPs: */ 715 if (pd->uobject) { 716 dev_err(dev, "not support usr space GSI\n"); 717 return ERR_PTR(-EINVAL); 718 } 719 720 hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL); 721 if (!hr_sqp) 722 return ERR_PTR(-ENOMEM); 723 724 hr_qp = &hr_sqp->hr_qp; 725 hr_qp->port = init_attr->port_num - 1; 726 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 727 hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS + 728 hr_dev->iboe.phy_port[hr_qp->port]; 729 730 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 731 hr_qp->ibqp.qp_num, hr_qp); 732 if (ret) { 733 dev_err(dev, "Create GSI QP failed!\n"); 734 kfree(hr_sqp); 735 return ERR_PTR(ret); 736 } 737 738 break; 739 } 740 default:{ 741 dev_err(dev, "not support QP type %d\n", init_attr->qp_type); 742 return ERR_PTR(-EINVAL); 743 } 744 } 745 746 return &hr_qp->ibqp; 747 } 748 EXPORT_SYMBOL_GPL(hns_roce_create_qp); 749 750 int to_hr_qp_type(int qp_type) 751 { 752 int transport_type; 753 754 if (qp_type == IB_QPT_RC) 755 transport_type = SERV_TYPE_RC; 756 else if (qp_type == IB_QPT_UC) 757 transport_type = SERV_TYPE_UC; 758 else if (qp_type == IB_QPT_UD) 759 transport_type = SERV_TYPE_UD; 760 else if (qp_type == IB_QPT_GSI) 761 transport_type = SERV_TYPE_UD; 762 else 763 transport_type = -1; 764 765 return transport_type; 766 } 767 EXPORT_SYMBOL_GPL(to_hr_qp_type); 768 769 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 770 int attr_mask, struct ib_udata *udata) 771 { 772 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 773 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 774 enum ib_qp_state cur_state, new_state; 775 struct device *dev = hr_dev->dev; 776 int ret = -EINVAL; 777 int p; 778 enum ib_mtu active_mtu; 779 780 mutex_lock(&hr_qp->mutex); 781 782 cur_state = attr_mask & IB_QP_CUR_STATE ? 783 attr->cur_qp_state : (enum ib_qp_state)hr_qp->state; 784 new_state = attr_mask & IB_QP_STATE ? 785 attr->qp_state : cur_state; 786 787 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask, 788 IB_LINK_LAYER_ETHERNET)) { 789 dev_err(dev, "ib_modify_qp_is_ok failed\n"); 790 goto out; 791 } 792 793 if ((attr_mask & IB_QP_PORT) && 794 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { 795 dev_err(dev, "attr port_num invalid.attr->port_num=%d\n", 796 attr->port_num); 797 goto out; 798 } 799 800 if (attr_mask & IB_QP_PKEY_INDEX) { 801 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 802 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { 803 dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n", 804 attr->pkey_index); 805 goto out; 806 } 807 } 808 809 if (attr_mask & IB_QP_PATH_MTU) { 810 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 811 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 812 813 if ((hr_dev->caps.max_mtu == IB_MTU_4096 && 814 attr->path_mtu > IB_MTU_4096) || 815 (hr_dev->caps.max_mtu == IB_MTU_2048 && 816 attr->path_mtu > IB_MTU_2048) || 817 attr->path_mtu < IB_MTU_256 || 818 attr->path_mtu > active_mtu) { 819 dev_err(dev, "attr path_mtu(%d)invalid while modify qp", 820 attr->path_mtu); 821 goto out; 822 } 823 } 824 825 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 826 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { 827 dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n", 828 attr->max_rd_atomic); 829 goto out; 830 } 831 832 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 833 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { 834 dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n", 835 attr->max_dest_rd_atomic); 836 goto out; 837 } 838 839 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 840 ret = 0; 841 goto out; 842 } 843 844 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, 845 new_state); 846 847 out: 848 mutex_unlock(&hr_qp->mutex); 849 850 return ret; 851 } 852 853 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) 854 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 855 { 856 if (send_cq == recv_cq) { 857 spin_lock_irq(&send_cq->lock); 858 __acquire(&recv_cq->lock); 859 } else if (send_cq->cqn < recv_cq->cqn) { 860 spin_lock_irq(&send_cq->lock); 861 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 862 } else { 863 spin_lock_irq(&recv_cq->lock); 864 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 865 } 866 } 867 EXPORT_SYMBOL_GPL(hns_roce_lock_cqs); 868 869 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 870 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 871 __releases(&recv_cq->lock) 872 { 873 if (send_cq == recv_cq) { 874 __release(&recv_cq->lock); 875 spin_unlock_irq(&send_cq->lock); 876 } else if (send_cq->cqn < recv_cq->cqn) { 877 spin_unlock(&recv_cq->lock); 878 spin_unlock_irq(&send_cq->lock); 879 } else { 880 spin_unlock(&send_cq->lock); 881 spin_unlock_irq(&recv_cq->lock); 882 } 883 } 884 EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs); 885 886 __be32 send_ieth(struct ib_send_wr *wr) 887 { 888 switch (wr->opcode) { 889 case IB_WR_SEND_WITH_IMM: 890 case IB_WR_RDMA_WRITE_WITH_IMM: 891 return cpu_to_le32(wr->ex.imm_data); 892 case IB_WR_SEND_WITH_INV: 893 return cpu_to_le32(wr->ex.invalidate_rkey); 894 default: 895 return 0; 896 } 897 } 898 EXPORT_SYMBOL_GPL(send_ieth); 899 900 static void *get_wqe(struct hns_roce_qp *hr_qp, int offset) 901 { 902 903 return hns_roce_buf_offset(&hr_qp->hr_buf, offset); 904 } 905 906 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n) 907 { 908 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 909 } 910 EXPORT_SYMBOL_GPL(get_recv_wqe); 911 912 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n) 913 { 914 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 915 } 916 EXPORT_SYMBOL_GPL(get_send_wqe); 917 918 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n) 919 { 920 return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset + 921 (n << hr_qp->sge.sge_shift)); 922 } 923 EXPORT_SYMBOL_GPL(get_send_extend_sge); 924 925 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 926 struct ib_cq *ib_cq) 927 { 928 struct hns_roce_cq *hr_cq; 929 u32 cur; 930 931 cur = hr_wq->head - hr_wq->tail; 932 if (likely(cur + nreq < hr_wq->max_post)) 933 return false; 934 935 hr_cq = to_hr_cq(ib_cq); 936 spin_lock(&hr_cq->lock); 937 cur = hr_wq->head - hr_wq->tail; 938 spin_unlock(&hr_cq->lock); 939 940 return cur + nreq >= hr_wq->max_post; 941 } 942 EXPORT_SYMBOL_GPL(hns_roce_wq_overflow); 943 944 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 945 { 946 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 947 int reserved_from_top = 0; 948 int ret; 949 950 spin_lock_init(&qp_table->lock); 951 INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC); 952 953 /* A port include two SQP, six port total 12 */ 954 ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps, 955 hr_dev->caps.num_qps - 1, SQP_NUM, 956 reserved_from_top); 957 if (ret) { 958 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n", 959 ret); 960 return ret; 961 } 962 963 return 0; 964 } 965 966 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) 967 { 968 hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap); 969 } 970