1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/pci.h> 35 #include <rdma/ib_addr.h> 36 #include <rdma/ib_umem.h> 37 #include <rdma/uverbs_ioctl.h> 38 #include "hns_roce_common.h" 39 #include "hns_roce_device.h" 40 #include "hns_roce_hem.h" 41 42 static void flush_work_handle(struct work_struct *work) 43 { 44 struct hns_roce_work *flush_work = container_of(work, 45 struct hns_roce_work, work); 46 struct hns_roce_qp *hr_qp = container_of(flush_work, 47 struct hns_roce_qp, flush_work); 48 struct device *dev = flush_work->hr_dev->dev; 49 struct ib_qp_attr attr; 50 int attr_mask; 51 int ret; 52 53 attr_mask = IB_QP_STATE; 54 attr.qp_state = IB_QPS_ERR; 55 56 if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) { 57 ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL); 58 if (ret) 59 dev_err(dev, "modify QP to error state failed(%d) during CQE flush\n", 60 ret); 61 } 62 63 /* 64 * make sure we signal QP destroy leg that flush QP was completed 65 * so that it can safely proceed ahead now and destroy QP 66 */ 67 if (refcount_dec_and_test(&hr_qp->refcount)) 68 complete(&hr_qp->free); 69 } 70 71 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 72 { 73 struct hns_roce_work *flush_work = &hr_qp->flush_work; 74 75 flush_work->hr_dev = hr_dev; 76 INIT_WORK(&flush_work->work, flush_work_handle); 77 refcount_inc(&hr_qp->refcount); 78 queue_work(hr_dev->irq_workq, &flush_work->work); 79 } 80 81 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp) 82 { 83 /* 84 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state 85 * gets into errored mode. Hence, as a workaround to this 86 * hardware limitation, driver needs to assist in flushing. But 87 * the flushing operation uses mailbox to convey the QP state to 88 * the hardware and which can sleep due to the mutex protection 89 * around the mailbox calls. Hence, use the deferred flush for 90 * now. 91 */ 92 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 93 init_flush_work(dev, qp); 94 } 95 96 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 97 { 98 struct device *dev = hr_dev->dev; 99 struct hns_roce_qp *qp; 100 101 xa_lock(&hr_dev->qp_table_xa); 102 qp = __hns_roce_qp_lookup(hr_dev, qpn); 103 if (qp) 104 refcount_inc(&qp->refcount); 105 xa_unlock(&hr_dev->qp_table_xa); 106 107 if (!qp) { 108 dev_warn(dev, "async event for bogus QP %08x\n", qpn); 109 return; 110 } 111 112 if (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || 113 event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || 114 event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR || 115 event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION || 116 event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH) { 117 qp->state = IB_QPS_ERR; 118 119 flush_cqe(hr_dev, qp); 120 } 121 122 qp->event(qp, (enum hns_roce_event)event_type); 123 124 if (refcount_dec_and_test(&qp->refcount)) 125 complete(&qp->free); 126 } 127 128 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, 129 enum hns_roce_event type) 130 { 131 struct ib_qp *ibqp = &hr_qp->ibqp; 132 struct ib_event event; 133 134 if (ibqp->event_handler) { 135 event.device = ibqp->device; 136 event.element.qp = ibqp; 137 switch (type) { 138 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 139 event.event = IB_EVENT_PATH_MIG; 140 break; 141 case HNS_ROCE_EVENT_TYPE_COMM_EST: 142 event.event = IB_EVENT_COMM_EST; 143 break; 144 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 145 event.event = IB_EVENT_SQ_DRAINED; 146 break; 147 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 148 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 149 break; 150 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 151 event.event = IB_EVENT_QP_FATAL; 152 break; 153 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 154 event.event = IB_EVENT_PATH_MIG_ERR; 155 break; 156 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 157 event.event = IB_EVENT_QP_REQ_ERR; 158 break; 159 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 160 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 161 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 162 event.event = IB_EVENT_QP_ACCESS_ERR; 163 break; 164 default: 165 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", 166 type, hr_qp->qpn); 167 return; 168 } 169 ibqp->event_handler(&event, ibqp->qp_context); 170 } 171 } 172 173 static u8 get_affinity_cq_bank(u8 qp_bank) 174 { 175 return (qp_bank >> 1) & CQ_BANKID_MASK; 176 } 177 178 static u8 get_least_load_bankid_for_qp(struct ib_qp_init_attr *init_attr, 179 struct hns_roce_bank *bank) 180 { 181 #define INVALID_LOAD_QPNUM 0xFFFFFFFF 182 struct ib_cq *scq = init_attr->send_cq; 183 u32 least_load = INVALID_LOAD_QPNUM; 184 unsigned long cqn = 0; 185 u8 bankid = 0; 186 u32 bankcnt; 187 u8 i; 188 189 if (scq) 190 cqn = to_hr_cq(scq)->cqn; 191 192 for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) { 193 if (scq && (get_affinity_cq_bank(i) != (cqn & CQ_BANKID_MASK))) 194 continue; 195 196 bankcnt = bank[i].inuse; 197 if (bankcnt < least_load) { 198 least_load = bankcnt; 199 bankid = i; 200 } 201 } 202 203 return bankid; 204 } 205 206 static int alloc_qpn_with_bankid(struct hns_roce_bank *bank, u8 bankid, 207 unsigned long *qpn) 208 { 209 int id; 210 211 id = ida_alloc_range(&bank->ida, bank->next, bank->max, GFP_KERNEL); 212 if (id < 0) { 213 id = ida_alloc_range(&bank->ida, bank->min, bank->max, 214 GFP_KERNEL); 215 if (id < 0) 216 return id; 217 } 218 219 /* the QPN should keep increasing until the max value is reached. */ 220 bank->next = (id + 1) > bank->max ? bank->min : id + 1; 221 222 /* the lower 3 bits is bankid */ 223 *qpn = (id << 3) | bankid; 224 225 return 0; 226 } 227 static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 228 struct ib_qp_init_attr *init_attr) 229 { 230 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 231 unsigned long num = 0; 232 u8 bankid; 233 int ret; 234 235 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) { 236 num = 1; 237 } else { 238 mutex_lock(&qp_table->bank_mutex); 239 bankid = get_least_load_bankid_for_qp(init_attr, qp_table->bank); 240 241 ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid, 242 &num); 243 if (ret) { 244 ibdev_err(&hr_dev->ib_dev, 245 "failed to alloc QPN, ret = %d\n", ret); 246 mutex_unlock(&qp_table->bank_mutex); 247 return ret; 248 } 249 250 qp_table->bank[bankid].inuse++; 251 mutex_unlock(&qp_table->bank_mutex); 252 } 253 254 hr_qp->qpn = num; 255 256 return 0; 257 } 258 259 static void add_qp_to_list(struct hns_roce_dev *hr_dev, 260 struct hns_roce_qp *hr_qp, 261 struct ib_cq *send_cq, struct ib_cq *recv_cq) 262 { 263 struct hns_roce_cq *hr_send_cq, *hr_recv_cq; 264 unsigned long flags; 265 266 hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL; 267 hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL; 268 269 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 270 hns_roce_lock_cqs(hr_send_cq, hr_recv_cq); 271 272 list_add_tail(&hr_qp->node, &hr_dev->qp_list); 273 if (hr_send_cq) 274 list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list); 275 if (hr_recv_cq) 276 list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list); 277 278 hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq); 279 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 280 } 281 282 static int hns_roce_qp_store(struct hns_roce_dev *hr_dev, 283 struct hns_roce_qp *hr_qp, 284 struct ib_qp_init_attr *init_attr) 285 { 286 struct xarray *xa = &hr_dev->qp_table_xa; 287 int ret; 288 289 if (!hr_qp->qpn) 290 return -EINVAL; 291 292 ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL)); 293 if (ret) 294 dev_err(hr_dev->dev, "failed to xa store for QPC\n"); 295 else 296 /* add QP to device's QP list for softwc */ 297 add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq, 298 init_attr->recv_cq); 299 300 return ret; 301 } 302 303 static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 304 { 305 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 306 struct device *dev = hr_dev->dev; 307 int ret; 308 309 if (!hr_qp->qpn) 310 return -EINVAL; 311 312 /* Alloc memory for QPC */ 313 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); 314 if (ret) { 315 dev_err(dev, "failed to get QPC table\n"); 316 goto err_out; 317 } 318 319 /* Alloc memory for IRRL */ 320 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 321 if (ret) { 322 dev_err(dev, "failed to get IRRL table\n"); 323 goto err_put_qp; 324 } 325 326 if (hr_dev->caps.trrl_entry_sz) { 327 /* Alloc memory for TRRL */ 328 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, 329 hr_qp->qpn); 330 if (ret) { 331 dev_err(dev, "failed to get TRRL table\n"); 332 goto err_put_irrl; 333 } 334 } 335 336 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 337 /* Alloc memory for SCC CTX */ 338 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table, 339 hr_qp->qpn); 340 if (ret) { 341 dev_err(dev, "failed to get SCC CTX table\n"); 342 goto err_put_trrl; 343 } 344 } 345 346 return 0; 347 348 err_put_trrl: 349 if (hr_dev->caps.trrl_entry_sz) 350 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 351 352 err_put_irrl: 353 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 354 355 err_put_qp: 356 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 357 358 err_out: 359 return ret; 360 } 361 362 static void qp_user_mmap_entry_remove(struct hns_roce_qp *hr_qp) 363 { 364 rdma_user_mmap_entry_remove(&hr_qp->dwqe_mmap_entry->rdma_entry); 365 } 366 367 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 368 { 369 struct xarray *xa = &hr_dev->qp_table_xa; 370 unsigned long flags; 371 372 list_del(&hr_qp->node); 373 374 if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) 375 list_del(&hr_qp->sq_node); 376 377 if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI && 378 hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) 379 list_del(&hr_qp->rq_node); 380 381 xa_lock_irqsave(xa, flags); 382 __xa_erase(xa, hr_qp->qpn); 383 xa_unlock_irqrestore(xa, flags); 384 } 385 386 static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 387 { 388 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 389 390 if (hr_dev->caps.trrl_entry_sz) 391 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 392 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 393 } 394 395 static inline u8 get_qp_bankid(unsigned long qpn) 396 { 397 /* The lower 3 bits of QPN are used to hash to different banks */ 398 return (u8)(qpn & GENMASK(2, 0)); 399 } 400 401 static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 402 { 403 u8 bankid; 404 405 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 406 return; 407 408 if (hr_qp->qpn < hr_dev->caps.reserved_qps) 409 return; 410 411 bankid = get_qp_bankid(hr_qp->qpn); 412 413 ida_free(&hr_dev->qp_table.bank[bankid].ida, hr_qp->qpn >> 3); 414 415 mutex_lock(&hr_dev->qp_table.bank_mutex); 416 hr_dev->qp_table.bank[bankid].inuse--; 417 mutex_unlock(&hr_dev->qp_table.bank_mutex); 418 } 419 420 static u32 proc_rq_sge(struct hns_roce_dev *dev, struct hns_roce_qp *hr_qp, 421 bool user) 422 { 423 u32 max_sge = dev->caps.max_rq_sg; 424 425 if (dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 426 return max_sge; 427 428 /* Reserve SGEs only for HIP08 in kernel; The userspace driver will 429 * calculate number of max_sge with reserved SGEs when allocating wqe 430 * buf, so there is no need to do this again in kernel. But the number 431 * may exceed the capacity of SGEs recorded in the firmware, so the 432 * kernel driver should just adapt the value accordingly. 433 */ 434 if (user) 435 max_sge = roundup_pow_of_two(max_sge + 1); 436 else 437 hr_qp->rq.rsv_sge = 1; 438 439 return max_sge; 440 } 441 442 static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, 443 struct hns_roce_qp *hr_qp, int has_rq, bool user) 444 { 445 u32 max_sge = proc_rq_sge(hr_dev, hr_qp, user); 446 u32 cnt; 447 448 /* If srq exist, set zero for relative number of rq */ 449 if (!has_rq) { 450 hr_qp->rq.wqe_cnt = 0; 451 hr_qp->rq.max_gs = 0; 452 cap->max_recv_wr = 0; 453 cap->max_recv_sge = 0; 454 455 return 0; 456 } 457 458 /* Check the validity of QP support capacity */ 459 if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes || 460 cap->max_recv_sge > max_sge) { 461 ibdev_err(&hr_dev->ib_dev, 462 "RQ config error, depth = %u, sge = %u\n", 463 cap->max_recv_wr, cap->max_recv_sge); 464 return -EINVAL; 465 } 466 467 cnt = roundup_pow_of_two(max(cap->max_recv_wr, hr_dev->caps.min_wqes)); 468 if (cnt > hr_dev->caps.max_wqes) { 469 ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n", 470 cap->max_recv_wr); 471 return -EINVAL; 472 } 473 474 hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge) + 475 hr_qp->rq.rsv_sge); 476 477 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz * 478 hr_qp->rq.max_gs); 479 480 hr_qp->rq.wqe_cnt = cnt; 481 482 cap->max_recv_wr = cnt; 483 cap->max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 484 485 return 0; 486 } 487 488 static u32 get_max_inline_data(struct hns_roce_dev *hr_dev, 489 struct ib_qp_cap *cap) 490 { 491 if (cap->max_inline_data) { 492 cap->max_inline_data = roundup_pow_of_two(cap->max_inline_data); 493 return min(cap->max_inline_data, 494 hr_dev->caps.max_sq_inline); 495 } 496 497 return 0; 498 } 499 500 static void update_inline_data(struct hns_roce_qp *hr_qp, 501 struct ib_qp_cap *cap) 502 { 503 u32 sge_num = hr_qp->sq.ext_sge_cnt; 504 505 if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) { 506 if (!(hr_qp->ibqp.qp_type == IB_QPT_GSI || 507 hr_qp->ibqp.qp_type == IB_QPT_UD)) 508 sge_num = max((u32)HNS_ROCE_SGE_IN_WQE, sge_num); 509 510 cap->max_inline_data = max(cap->max_inline_data, 511 sge_num * HNS_ROCE_SGE_SIZE); 512 } 513 514 hr_qp->max_inline_data = cap->max_inline_data; 515 } 516 517 static u32 get_sge_num_from_max_send_sge(bool is_ud_or_gsi, 518 u32 max_send_sge) 519 { 520 unsigned int std_sge_num; 521 unsigned int min_sge; 522 523 std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE; 524 min_sge = is_ud_or_gsi ? 1 : 0; 525 return max_send_sge > std_sge_num ? (max_send_sge - std_sge_num) : 526 min_sge; 527 } 528 529 static unsigned int get_sge_num_from_max_inl_data(bool is_ud_or_gsi, 530 u32 max_inline_data) 531 { 532 unsigned int inline_sge; 533 534 if (!max_inline_data) 535 return 0; 536 537 /* 538 * if max_inline_data less than 539 * HNS_ROCE_SGE_IN_WQE * HNS_ROCE_SGE_SIZE, 540 * In addition to ud's mode, no need to extend sge. 541 */ 542 inline_sge = roundup_pow_of_two(max_inline_data) / HNS_ROCE_SGE_SIZE; 543 if (!is_ud_or_gsi && inline_sge <= HNS_ROCE_SGE_IN_WQE) 544 inline_sge = 0; 545 546 return inline_sge; 547 } 548 549 static void set_ext_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt, 550 struct hns_roce_qp *hr_qp, struct ib_qp_cap *cap) 551 { 552 bool is_ud_or_gsi = (hr_qp->ibqp.qp_type == IB_QPT_GSI || 553 hr_qp->ibqp.qp_type == IB_QPT_UD); 554 unsigned int std_sge_num; 555 u32 inline_ext_sge = 0; 556 u32 ext_wqe_sge_cnt; 557 u32 total_sge_cnt; 558 559 cap->max_inline_data = get_max_inline_data(hr_dev, cap); 560 561 hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT; 562 std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE; 563 ext_wqe_sge_cnt = get_sge_num_from_max_send_sge(is_ud_or_gsi, 564 cap->max_send_sge); 565 566 if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) { 567 inline_ext_sge = max(ext_wqe_sge_cnt, 568 get_sge_num_from_max_inl_data(is_ud_or_gsi, 569 cap->max_inline_data)); 570 hr_qp->sq.ext_sge_cnt = inline_ext_sge ? 571 roundup_pow_of_two(inline_ext_sge) : 0; 572 573 hr_qp->sq.max_gs = max(1U, (hr_qp->sq.ext_sge_cnt + std_sge_num)); 574 hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg); 575 576 ext_wqe_sge_cnt = hr_qp->sq.ext_sge_cnt; 577 } else { 578 hr_qp->sq.max_gs = max(1U, cap->max_send_sge); 579 hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg); 580 hr_qp->sq.ext_sge_cnt = hr_qp->sq.max_gs; 581 } 582 583 /* If the number of extended sge is not zero, they MUST use the 584 * space of HNS_HW_PAGE_SIZE at least. 585 */ 586 if (ext_wqe_sge_cnt) { 587 total_sge_cnt = roundup_pow_of_two(sq_wqe_cnt * ext_wqe_sge_cnt); 588 hr_qp->sge.sge_cnt = max(total_sge_cnt, 589 (u32)HNS_HW_PAGE_SIZE / HNS_ROCE_SGE_SIZE); 590 } 591 592 update_inline_data(hr_qp, cap); 593 } 594 595 static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev, 596 struct ib_qp_cap *cap, 597 struct hns_roce_ib_create_qp *ucmd) 598 { 599 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 600 u8 max_sq_stride = ilog2(roundup_sq_stride); 601 602 /* Sanity check SQ size before proceeding */ 603 if (ucmd->log_sq_stride > max_sq_stride || 604 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 605 ibdev_err(&hr_dev->ib_dev, "failed to check SQ stride size.\n"); 606 return -EINVAL; 607 } 608 609 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { 610 ibdev_err(&hr_dev->ib_dev, "failed to check SQ SGE size %u.\n", 611 cap->max_send_sge); 612 return -EINVAL; 613 } 614 615 return 0; 616 } 617 618 static int set_user_sq_size(struct hns_roce_dev *hr_dev, 619 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp, 620 struct hns_roce_ib_create_qp *ucmd) 621 { 622 struct ib_device *ibdev = &hr_dev->ib_dev; 623 u32 cnt = 0; 624 int ret; 625 626 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || 627 cnt > hr_dev->caps.max_wqes) 628 return -EINVAL; 629 630 ret = check_sq_size_with_integrity(hr_dev, cap, ucmd); 631 if (ret) { 632 ibdev_err(ibdev, "failed to check user SQ size, ret = %d.\n", 633 ret); 634 return ret; 635 } 636 637 set_ext_sge_param(hr_dev, cnt, hr_qp, cap); 638 639 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 640 hr_qp->sq.wqe_cnt = cnt; 641 cap->max_send_sge = hr_qp->sq.max_gs; 642 643 return 0; 644 } 645 646 static int set_wqe_buf_attr(struct hns_roce_dev *hr_dev, 647 struct hns_roce_qp *hr_qp, 648 struct hns_roce_buf_attr *buf_attr) 649 { 650 int buf_size; 651 int idx = 0; 652 653 hr_qp->buff_size = 0; 654 655 /* SQ WQE */ 656 hr_qp->sq.offset = 0; 657 buf_size = to_hr_hem_entries_size(hr_qp->sq.wqe_cnt, 658 hr_qp->sq.wqe_shift); 659 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 660 buf_attr->region[idx].size = buf_size; 661 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sq_hop_num; 662 idx++; 663 hr_qp->buff_size += buf_size; 664 } 665 666 /* extend SGE WQE in SQ */ 667 hr_qp->sge.offset = hr_qp->buff_size; 668 buf_size = to_hr_hem_entries_size(hr_qp->sge.sge_cnt, 669 hr_qp->sge.sge_shift); 670 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 671 buf_attr->region[idx].size = buf_size; 672 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sge_hop_num; 673 idx++; 674 hr_qp->buff_size += buf_size; 675 } 676 677 /* RQ WQE */ 678 hr_qp->rq.offset = hr_qp->buff_size; 679 buf_size = to_hr_hem_entries_size(hr_qp->rq.wqe_cnt, 680 hr_qp->rq.wqe_shift); 681 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 682 buf_attr->region[idx].size = buf_size; 683 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_rq_hop_num; 684 idx++; 685 hr_qp->buff_size += buf_size; 686 } 687 688 if (hr_qp->buff_size < 1) 689 return -EINVAL; 690 691 buf_attr->page_shift = HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 692 buf_attr->region_count = idx; 693 694 return 0; 695 } 696 697 static int set_kernel_sq_size(struct hns_roce_dev *hr_dev, 698 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp) 699 { 700 struct ib_device *ibdev = &hr_dev->ib_dev; 701 u32 cnt; 702 703 if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes || 704 cap->max_send_sge > hr_dev->caps.max_sq_sg) { 705 ibdev_err(ibdev, "failed to check SQ WR or SGE num.\n"); 706 return -EINVAL; 707 } 708 709 cnt = roundup_pow_of_two(max(cap->max_send_wr, hr_dev->caps.min_wqes)); 710 if (cnt > hr_dev->caps.max_wqes) { 711 ibdev_err(ibdev, "failed to check WQE num, WQE num = %u.\n", 712 cnt); 713 return -EINVAL; 714 } 715 716 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); 717 hr_qp->sq.wqe_cnt = cnt; 718 719 set_ext_sge_param(hr_dev, cnt, hr_qp, cap); 720 721 /* sync the parameters of kernel QP to user's configuration */ 722 cap->max_send_wr = cnt; 723 cap->max_send_sge = hr_qp->sq.max_gs; 724 725 return 0; 726 } 727 728 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr) 729 { 730 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr) 731 return 0; 732 733 return 1; 734 } 735 736 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr) 737 { 738 if (attr->qp_type == IB_QPT_XRC_INI || 739 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 740 !attr->cap.max_recv_wr) 741 return 0; 742 743 return 1; 744 } 745 746 static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 747 struct ib_qp_init_attr *init_attr, 748 struct ib_udata *udata, unsigned long addr) 749 { 750 struct ib_device *ibdev = &hr_dev->ib_dev; 751 struct hns_roce_buf_attr buf_attr = {}; 752 int ret; 753 754 ret = set_wqe_buf_attr(hr_dev, hr_qp, &buf_attr); 755 if (ret) { 756 ibdev_err(ibdev, "failed to split WQE buf, ret = %d.\n", ret); 757 goto err_inline; 758 } 759 ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr, 760 PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz, 761 udata, addr); 762 if (ret) { 763 ibdev_err(ibdev, "failed to create WQE mtr, ret = %d.\n", ret); 764 goto err_inline; 765 } 766 767 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_DIRECT_WQE) 768 hr_qp->en_flags |= HNS_ROCE_QP_CAP_DIRECT_WQE; 769 770 return 0; 771 772 err_inline: 773 774 return ret; 775 } 776 777 static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 778 { 779 hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr); 780 } 781 782 static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev, 783 struct ib_qp_init_attr *init_attr, 784 struct ib_udata *udata, 785 struct hns_roce_ib_create_qp_resp *resp, 786 struct hns_roce_ib_create_qp *ucmd) 787 { 788 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 789 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 790 hns_roce_qp_has_sq(init_attr) && 791 udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr)); 792 } 793 794 static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev, 795 struct ib_qp_init_attr *init_attr, 796 struct ib_udata *udata, 797 struct hns_roce_ib_create_qp_resp *resp) 798 { 799 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 800 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 801 hns_roce_qp_has_rq(init_attr)); 802 } 803 804 static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev, 805 struct ib_qp_init_attr *init_attr) 806 { 807 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 808 hns_roce_qp_has_rq(init_attr)); 809 } 810 811 static int qp_mmap_entry(struct hns_roce_qp *hr_qp, 812 struct hns_roce_dev *hr_dev, 813 struct ib_udata *udata, 814 struct hns_roce_ib_create_qp_resp *resp) 815 { 816 struct hns_roce_ucontext *uctx = 817 rdma_udata_to_drv_context(udata, 818 struct hns_roce_ucontext, ibucontext); 819 struct rdma_user_mmap_entry *rdma_entry; 820 u64 address; 821 822 address = hr_dev->dwqe_page + hr_qp->qpn * HNS_ROCE_DWQE_SIZE; 823 824 hr_qp->dwqe_mmap_entry = 825 hns_roce_user_mmap_entry_insert(&uctx->ibucontext, address, 826 HNS_ROCE_DWQE_SIZE, 827 HNS_ROCE_MMAP_TYPE_DWQE); 828 829 if (!hr_qp->dwqe_mmap_entry) { 830 ibdev_err(&hr_dev->ib_dev, "failed to get dwqe mmap entry.\n"); 831 return -ENOMEM; 832 } 833 834 rdma_entry = &hr_qp->dwqe_mmap_entry->rdma_entry; 835 resp->dwqe_mmap_key = rdma_user_mmap_get_offset(rdma_entry); 836 837 return 0; 838 } 839 840 static int alloc_user_qp_db(struct hns_roce_dev *hr_dev, 841 struct hns_roce_qp *hr_qp, 842 struct ib_qp_init_attr *init_attr, 843 struct ib_udata *udata, 844 struct hns_roce_ib_create_qp *ucmd, 845 struct hns_roce_ib_create_qp_resp *resp) 846 { 847 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 848 struct hns_roce_ucontext, ibucontext); 849 struct ib_device *ibdev = &hr_dev->ib_dev; 850 int ret; 851 852 if (user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd)) { 853 ret = hns_roce_db_map_user(uctx, ucmd->sdb_addr, &hr_qp->sdb); 854 if (ret) { 855 ibdev_err(ibdev, 856 "failed to map user SQ doorbell, ret = %d.\n", 857 ret); 858 goto err_out; 859 } 860 hr_qp->en_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB; 861 } 862 863 if (user_qp_has_rdb(hr_dev, init_attr, udata, resp)) { 864 ret = hns_roce_db_map_user(uctx, ucmd->db_addr, &hr_qp->rdb); 865 if (ret) { 866 ibdev_err(ibdev, 867 "failed to map user RQ doorbell, ret = %d.\n", 868 ret); 869 goto err_sdb; 870 } 871 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 872 } 873 874 return 0; 875 876 err_sdb: 877 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 878 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 879 err_out: 880 return ret; 881 } 882 883 static int alloc_kernel_qp_db(struct hns_roce_dev *hr_dev, 884 struct hns_roce_qp *hr_qp, 885 struct ib_qp_init_attr *init_attr) 886 { 887 struct ib_device *ibdev = &hr_dev->ib_dev; 888 int ret; 889 890 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 891 hr_qp->sq.db_reg = hr_dev->mem_base + 892 HNS_ROCE_DWQE_SIZE * hr_qp->qpn; 893 else 894 hr_qp->sq.db_reg = hr_dev->reg_base + hr_dev->sdb_offset + 895 DB_REG_OFFSET * hr_dev->priv_uar.index; 896 897 hr_qp->rq.db_reg = hr_dev->reg_base + hr_dev->odb_offset + 898 DB_REG_OFFSET * hr_dev->priv_uar.index; 899 900 if (kernel_qp_has_rdb(hr_dev, init_attr)) { 901 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0); 902 if (ret) { 903 ibdev_err(ibdev, 904 "failed to alloc kernel RQ doorbell, ret = %d.\n", 905 ret); 906 return ret; 907 } 908 *hr_qp->rdb.db_record = 0; 909 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 910 } 911 912 return 0; 913 } 914 915 static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 916 struct ib_qp_init_attr *init_attr, 917 struct ib_udata *udata, 918 struct hns_roce_ib_create_qp *ucmd, 919 struct hns_roce_ib_create_qp_resp *resp) 920 { 921 int ret; 922 923 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SDI_MODE) 924 hr_qp->en_flags |= HNS_ROCE_QP_CAP_OWNER_DB; 925 926 if (udata) { 927 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) { 928 ret = qp_mmap_entry(hr_qp, hr_dev, udata, resp); 929 if (ret) 930 return ret; 931 } 932 933 ret = alloc_user_qp_db(hr_dev, hr_qp, init_attr, udata, ucmd, 934 resp); 935 if (ret) 936 goto err_remove_qp; 937 } else { 938 ret = alloc_kernel_qp_db(hr_dev, hr_qp, init_attr); 939 if (ret) 940 return ret; 941 } 942 943 return 0; 944 945 err_remove_qp: 946 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) 947 qp_user_mmap_entry_remove(hr_qp); 948 949 return ret; 950 } 951 952 static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 953 struct ib_udata *udata) 954 { 955 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( 956 udata, struct hns_roce_ucontext, ibucontext); 957 958 if (udata) { 959 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 960 hns_roce_db_unmap_user(uctx, &hr_qp->rdb); 961 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 962 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 963 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) 964 qp_user_mmap_entry_remove(hr_qp); 965 } else { 966 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 967 hns_roce_free_db(hr_dev, &hr_qp->rdb); 968 } 969 } 970 971 static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev, 972 struct hns_roce_qp *hr_qp) 973 { 974 struct ib_device *ibdev = &hr_dev->ib_dev; 975 u64 *sq_wrid = NULL; 976 u64 *rq_wrid = NULL; 977 int ret; 978 979 sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL); 980 if (ZERO_OR_NULL_PTR(sq_wrid)) { 981 ibdev_err(ibdev, "failed to alloc SQ wrid.\n"); 982 return -ENOMEM; 983 } 984 985 if (hr_qp->rq.wqe_cnt) { 986 rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL); 987 if (ZERO_OR_NULL_PTR(rq_wrid)) { 988 ibdev_err(ibdev, "failed to alloc RQ wrid.\n"); 989 ret = -ENOMEM; 990 goto err_sq; 991 } 992 } 993 994 hr_qp->sq.wrid = sq_wrid; 995 hr_qp->rq.wrid = rq_wrid; 996 return 0; 997 err_sq: 998 kfree(sq_wrid); 999 1000 return ret; 1001 } 1002 1003 static void free_kernel_wrid(struct hns_roce_qp *hr_qp) 1004 { 1005 kfree(hr_qp->rq.wrid); 1006 kfree(hr_qp->sq.wrid); 1007 } 1008 1009 static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1010 struct ib_qp_init_attr *init_attr, 1011 struct ib_udata *udata, 1012 struct hns_roce_ib_create_qp *ucmd) 1013 { 1014 struct ib_device *ibdev = &hr_dev->ib_dev; 1015 struct hns_roce_ucontext *uctx; 1016 int ret; 1017 1018 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1019 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR; 1020 else 1021 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR; 1022 1023 ret = set_rq_size(hr_dev, &init_attr->cap, hr_qp, 1024 hns_roce_qp_has_rq(init_attr), !!udata); 1025 if (ret) { 1026 ibdev_err(ibdev, "failed to set user RQ size, ret = %d.\n", 1027 ret); 1028 return ret; 1029 } 1030 1031 if (udata) { 1032 ret = ib_copy_from_udata(ucmd, udata, 1033 min(udata->inlen, sizeof(*ucmd))); 1034 if (ret) { 1035 ibdev_err(ibdev, 1036 "failed to copy QP ucmd, ret = %d\n", ret); 1037 return ret; 1038 } 1039 1040 uctx = rdma_udata_to_drv_context(udata, struct hns_roce_ucontext, 1041 ibucontext); 1042 hr_qp->config = uctx->config; 1043 ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd); 1044 if (ret) 1045 ibdev_err(ibdev, 1046 "failed to set user SQ size, ret = %d.\n", 1047 ret); 1048 } else { 1049 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 1050 hr_qp->config = HNS_ROCE_EXSGE_FLAGS; 1051 ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp); 1052 if (ret) 1053 ibdev_err(ibdev, 1054 "failed to set kernel SQ size, ret = %d.\n", 1055 ret); 1056 } 1057 1058 return ret; 1059 } 1060 1061 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, 1062 struct ib_pd *ib_pd, 1063 struct ib_qp_init_attr *init_attr, 1064 struct ib_udata *udata, 1065 struct hns_roce_qp *hr_qp) 1066 { 1067 struct hns_roce_ib_create_qp_resp resp = {}; 1068 struct ib_device *ibdev = &hr_dev->ib_dev; 1069 struct hns_roce_ib_create_qp ucmd = {}; 1070 int ret; 1071 1072 mutex_init(&hr_qp->mutex); 1073 spin_lock_init(&hr_qp->sq.lock); 1074 spin_lock_init(&hr_qp->rq.lock); 1075 1076 hr_qp->state = IB_QPS_RESET; 1077 hr_qp->flush_flag = 0; 1078 1079 if (init_attr->create_flags) 1080 return -EOPNOTSUPP; 1081 1082 ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd); 1083 if (ret) { 1084 ibdev_err(ibdev, "failed to set QP param, ret = %d.\n", ret); 1085 return ret; 1086 } 1087 1088 if (!udata) { 1089 ret = alloc_kernel_wrid(hr_dev, hr_qp); 1090 if (ret) { 1091 ibdev_err(ibdev, "failed to alloc wrid, ret = %d.\n", 1092 ret); 1093 return ret; 1094 } 1095 } 1096 1097 ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr); 1098 if (ret) { 1099 ibdev_err(ibdev, "failed to alloc QP buffer, ret = %d.\n", ret); 1100 goto err_buf; 1101 } 1102 1103 ret = alloc_qpn(hr_dev, hr_qp, init_attr); 1104 if (ret) { 1105 ibdev_err(ibdev, "failed to alloc QPN, ret = %d.\n", ret); 1106 goto err_qpn; 1107 } 1108 1109 ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp); 1110 if (ret) { 1111 ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n", 1112 ret); 1113 goto err_db; 1114 } 1115 1116 ret = alloc_qpc(hr_dev, hr_qp); 1117 if (ret) { 1118 ibdev_err(ibdev, "failed to alloc QP context, ret = %d.\n", 1119 ret); 1120 goto err_qpc; 1121 } 1122 1123 ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr); 1124 if (ret) { 1125 ibdev_err(ibdev, "failed to store QP, ret = %d.\n", ret); 1126 goto err_store; 1127 } 1128 1129 if (udata) { 1130 resp.cap_flags = hr_qp->en_flags; 1131 ret = ib_copy_to_udata(udata, &resp, 1132 min(udata->outlen, sizeof(resp))); 1133 if (ret) { 1134 ibdev_err(ibdev, "copy qp resp failed!\n"); 1135 goto err_store; 1136 } 1137 } 1138 1139 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 1140 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); 1141 if (ret) 1142 goto err_flow_ctrl; 1143 } 1144 1145 hr_qp->ibqp.qp_num = hr_qp->qpn; 1146 hr_qp->event = hns_roce_ib_qp_event; 1147 refcount_set(&hr_qp->refcount, 1); 1148 init_completion(&hr_qp->free); 1149 1150 return 0; 1151 1152 err_flow_ctrl: 1153 hns_roce_qp_remove(hr_dev, hr_qp); 1154 err_store: 1155 free_qpc(hr_dev, hr_qp); 1156 err_qpc: 1157 free_qp_db(hr_dev, hr_qp, udata); 1158 err_db: 1159 free_qpn(hr_dev, hr_qp); 1160 err_qpn: 1161 free_qp_buf(hr_dev, hr_qp); 1162 err_buf: 1163 free_kernel_wrid(hr_qp); 1164 return ret; 1165 } 1166 1167 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1168 struct ib_udata *udata) 1169 { 1170 if (refcount_dec_and_test(&hr_qp->refcount)) 1171 complete(&hr_qp->free); 1172 wait_for_completion(&hr_qp->free); 1173 1174 free_qpc(hr_dev, hr_qp); 1175 free_qpn(hr_dev, hr_qp); 1176 free_qp_buf(hr_dev, hr_qp); 1177 free_kernel_wrid(hr_qp); 1178 free_qp_db(hr_dev, hr_qp, udata); 1179 } 1180 1181 static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type, 1182 bool is_user) 1183 { 1184 switch (type) { 1185 case IB_QPT_XRC_INI: 1186 case IB_QPT_XRC_TGT: 1187 if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) 1188 goto out; 1189 break; 1190 case IB_QPT_UD: 1191 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 && 1192 is_user) 1193 goto out; 1194 break; 1195 case IB_QPT_RC: 1196 case IB_QPT_GSI: 1197 break; 1198 default: 1199 goto out; 1200 } 1201 1202 return 0; 1203 1204 out: 1205 ibdev_err(&hr_dev->ib_dev, "not support QP type %d\n", type); 1206 1207 return -EOPNOTSUPP; 1208 } 1209 1210 int hns_roce_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1211 struct ib_udata *udata) 1212 { 1213 struct ib_device *ibdev = qp->device; 1214 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 1215 struct hns_roce_qp *hr_qp = to_hr_qp(qp); 1216 struct ib_pd *pd = qp->pd; 1217 int ret; 1218 1219 ret = check_qp_type(hr_dev, init_attr->qp_type, !!udata); 1220 if (ret) 1221 return ret; 1222 1223 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1224 hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn; 1225 1226 if (init_attr->qp_type == IB_QPT_GSI) { 1227 hr_qp->port = init_attr->port_num - 1; 1228 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 1229 } 1230 1231 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, hr_qp); 1232 if (ret) 1233 ibdev_err(ibdev, "create QP type 0x%x failed(%d)\n", 1234 init_attr->qp_type, ret); 1235 1236 return ret; 1237 } 1238 1239 int to_hr_qp_type(int qp_type) 1240 { 1241 switch (qp_type) { 1242 case IB_QPT_RC: 1243 return SERV_TYPE_RC; 1244 case IB_QPT_UD: 1245 case IB_QPT_GSI: 1246 return SERV_TYPE_UD; 1247 case IB_QPT_XRC_INI: 1248 case IB_QPT_XRC_TGT: 1249 return SERV_TYPE_XRC; 1250 default: 1251 return -1; 1252 } 1253 } 1254 1255 static int check_mtu_validate(struct hns_roce_dev *hr_dev, 1256 struct hns_roce_qp *hr_qp, 1257 struct ib_qp_attr *attr, int attr_mask) 1258 { 1259 enum ib_mtu active_mtu; 1260 int p; 1261 1262 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1263 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 1264 1265 if ((hr_dev->caps.max_mtu >= IB_MTU_2048 && 1266 attr->path_mtu > hr_dev->caps.max_mtu) || 1267 attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) { 1268 ibdev_err(&hr_dev->ib_dev, 1269 "attr path_mtu(%d)invalid while modify qp", 1270 attr->path_mtu); 1271 return -EINVAL; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1278 int attr_mask) 1279 { 1280 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1281 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1282 int p; 1283 1284 if ((attr_mask & IB_QP_PORT) && 1285 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { 1286 ibdev_err(&hr_dev->ib_dev, "invalid attr, port_num = %u.\n", 1287 attr->port_num); 1288 return -EINVAL; 1289 } 1290 1291 if (attr_mask & IB_QP_PKEY_INDEX) { 1292 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1293 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { 1294 ibdev_err(&hr_dev->ib_dev, 1295 "invalid attr, pkey_index = %u.\n", 1296 attr->pkey_index); 1297 return -EINVAL; 1298 } 1299 } 1300 1301 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1302 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { 1303 ibdev_err(&hr_dev->ib_dev, 1304 "invalid attr, max_rd_atomic = %u.\n", 1305 attr->max_rd_atomic); 1306 return -EINVAL; 1307 } 1308 1309 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1310 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { 1311 ibdev_err(&hr_dev->ib_dev, 1312 "invalid attr, max_dest_rd_atomic = %u.\n", 1313 attr->max_dest_rd_atomic); 1314 return -EINVAL; 1315 } 1316 1317 if (attr_mask & IB_QP_PATH_MTU) 1318 return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask); 1319 1320 return 0; 1321 } 1322 1323 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1324 int attr_mask, struct ib_udata *udata) 1325 { 1326 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1327 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1328 enum ib_qp_state cur_state, new_state; 1329 int ret = -EINVAL; 1330 1331 mutex_lock(&hr_qp->mutex); 1332 1333 if (attr_mask & IB_QP_CUR_STATE && attr->cur_qp_state != hr_qp->state) 1334 goto out; 1335 1336 cur_state = hr_qp->state; 1337 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1338 1339 if (ibqp->uobject && 1340 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) { 1341 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) { 1342 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); 1343 1344 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 1345 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); 1346 } else { 1347 ibdev_warn(&hr_dev->ib_dev, 1348 "flush cqe is not supported in userspace!\n"); 1349 goto out; 1350 } 1351 } 1352 1353 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 1354 attr_mask)) { 1355 ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n"); 1356 goto out; 1357 } 1358 1359 ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask); 1360 if (ret) 1361 goto out; 1362 1363 if (cur_state == new_state && cur_state == IB_QPS_RESET) 1364 goto out; 1365 1366 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, 1367 new_state, udata); 1368 1369 out: 1370 mutex_unlock(&hr_qp->mutex); 1371 1372 return ret; 1373 } 1374 1375 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) 1376 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1377 { 1378 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1379 __acquire(&send_cq->lock); 1380 __acquire(&recv_cq->lock); 1381 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1382 spin_lock_irq(&send_cq->lock); 1383 __acquire(&recv_cq->lock); 1384 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1385 spin_lock_irq(&recv_cq->lock); 1386 __acquire(&send_cq->lock); 1387 } else if (send_cq == recv_cq) { 1388 spin_lock_irq(&send_cq->lock); 1389 __acquire(&recv_cq->lock); 1390 } else if (send_cq->cqn < recv_cq->cqn) { 1391 spin_lock_irq(&send_cq->lock); 1392 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1393 } else { 1394 spin_lock_irq(&recv_cq->lock); 1395 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1396 } 1397 } 1398 1399 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1400 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 1401 __releases(&recv_cq->lock) 1402 { 1403 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1404 __release(&recv_cq->lock); 1405 __release(&send_cq->lock); 1406 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1407 __release(&recv_cq->lock); 1408 spin_unlock(&send_cq->lock); 1409 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1410 __release(&send_cq->lock); 1411 spin_unlock(&recv_cq->lock); 1412 } else if (send_cq == recv_cq) { 1413 __release(&recv_cq->lock); 1414 spin_unlock_irq(&send_cq->lock); 1415 } else if (send_cq->cqn < recv_cq->cqn) { 1416 spin_unlock(&recv_cq->lock); 1417 spin_unlock_irq(&send_cq->lock); 1418 } else { 1419 spin_unlock(&send_cq->lock); 1420 spin_unlock_irq(&recv_cq->lock); 1421 } 1422 } 1423 1424 static inline void *get_wqe(struct hns_roce_qp *hr_qp, u32 offset) 1425 { 1426 return hns_roce_buf_offset(hr_qp->mtr.kmem, offset); 1427 } 1428 1429 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n) 1430 { 1431 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 1432 } 1433 1434 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n) 1435 { 1436 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 1437 } 1438 1439 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n) 1440 { 1441 return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift)); 1442 } 1443 1444 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1445 struct ib_cq *ib_cq) 1446 { 1447 struct hns_roce_cq *hr_cq; 1448 u32 cur; 1449 1450 cur = hr_wq->head - hr_wq->tail; 1451 if (likely(cur + nreq < hr_wq->wqe_cnt)) 1452 return false; 1453 1454 hr_cq = to_hr_cq(ib_cq); 1455 spin_lock(&hr_cq->lock); 1456 cur = hr_wq->head - hr_wq->tail; 1457 spin_unlock(&hr_cq->lock); 1458 1459 return cur + nreq >= hr_wq->wqe_cnt; 1460 } 1461 1462 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 1463 { 1464 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 1465 unsigned int reserved_from_bot; 1466 unsigned int i; 1467 1468 qp_table->idx_table.spare_idx = kcalloc(hr_dev->caps.num_qps, 1469 sizeof(u32), GFP_KERNEL); 1470 if (!qp_table->idx_table.spare_idx) 1471 return -ENOMEM; 1472 1473 mutex_init(&qp_table->scc_mutex); 1474 mutex_init(&qp_table->bank_mutex); 1475 xa_init(&hr_dev->qp_table_xa); 1476 1477 reserved_from_bot = hr_dev->caps.reserved_qps; 1478 1479 for (i = 0; i < reserved_from_bot; i++) { 1480 hr_dev->qp_table.bank[get_qp_bankid(i)].inuse++; 1481 hr_dev->qp_table.bank[get_qp_bankid(i)].min++; 1482 } 1483 1484 for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) { 1485 ida_init(&hr_dev->qp_table.bank[i].ida); 1486 hr_dev->qp_table.bank[i].max = hr_dev->caps.num_qps / 1487 HNS_ROCE_QP_BANK_NUM - 1; 1488 hr_dev->qp_table.bank[i].next = hr_dev->qp_table.bank[i].min; 1489 } 1490 1491 return 0; 1492 } 1493 1494 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) 1495 { 1496 int i; 1497 1498 for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) 1499 ida_destroy(&hr_dev->qp_table.bank[i].ida); 1500 kfree(hr_dev->qp_table.idx_table.spare_idx); 1501 } 1502