1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/pci.h> 35 #include <linux/platform_device.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_umem.h> 38 #include <rdma/uverbs_ioctl.h> 39 #include "hns_roce_common.h" 40 #include "hns_roce_device.h" 41 #include "hns_roce_hem.h" 42 #include <rdma/hns-abi.h> 43 44 #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS) 45 46 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 47 { 48 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 49 struct device *dev = hr_dev->dev; 50 struct hns_roce_qp *qp; 51 52 spin_lock(&qp_table->lock); 53 54 qp = __hns_roce_qp_lookup(hr_dev, qpn); 55 if (qp) 56 atomic_inc(&qp->refcount); 57 58 spin_unlock(&qp_table->lock); 59 60 if (!qp) { 61 dev_warn(dev, "Async event for bogus QP %08x\n", qpn); 62 return; 63 } 64 65 qp->event(qp, (enum hns_roce_event)event_type); 66 67 if (atomic_dec_and_test(&qp->refcount)) 68 complete(&qp->free); 69 } 70 EXPORT_SYMBOL_GPL(hns_roce_qp_event); 71 72 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, 73 enum hns_roce_event type) 74 { 75 struct ib_event event; 76 struct ib_qp *ibqp = &hr_qp->ibqp; 77 78 if (ibqp->event_handler) { 79 event.device = ibqp->device; 80 event.element.qp = ibqp; 81 switch (type) { 82 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 83 event.event = IB_EVENT_PATH_MIG; 84 break; 85 case HNS_ROCE_EVENT_TYPE_COMM_EST: 86 event.event = IB_EVENT_COMM_EST; 87 break; 88 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 89 event.event = IB_EVENT_SQ_DRAINED; 90 break; 91 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 92 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 93 break; 94 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 95 event.event = IB_EVENT_QP_FATAL; 96 break; 97 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 98 event.event = IB_EVENT_PATH_MIG_ERR; 99 break; 100 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 101 event.event = IB_EVENT_QP_REQ_ERR; 102 break; 103 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 104 event.event = IB_EVENT_QP_ACCESS_ERR; 105 break; 106 default: 107 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", 108 type, hr_qp->qpn); 109 return; 110 } 111 ibqp->event_handler(&event, ibqp->qp_context); 112 } 113 } 114 115 static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt, 116 int align, unsigned long *base) 117 { 118 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 119 120 return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align, 121 base) ? 122 -ENOMEM : 123 0; 124 } 125 126 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state) 127 { 128 switch (state) { 129 case IB_QPS_RESET: 130 return HNS_ROCE_QP_STATE_RST; 131 case IB_QPS_INIT: 132 return HNS_ROCE_QP_STATE_INIT; 133 case IB_QPS_RTR: 134 return HNS_ROCE_QP_STATE_RTR; 135 case IB_QPS_RTS: 136 return HNS_ROCE_QP_STATE_RTS; 137 case IB_QPS_SQD: 138 return HNS_ROCE_QP_STATE_SQD; 139 case IB_QPS_ERR: 140 return HNS_ROCE_QP_STATE_ERR; 141 default: 142 return HNS_ROCE_QP_NUM_STATE; 143 } 144 } 145 EXPORT_SYMBOL_GPL(to_hns_roce_state); 146 147 static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn, 148 struct hns_roce_qp *hr_qp) 149 { 150 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 151 int ret; 152 153 if (!qpn) 154 return -EINVAL; 155 156 hr_qp->qpn = qpn; 157 158 spin_lock_irq(&qp_table->lock); 159 ret = radix_tree_insert(&hr_dev->qp_table_tree, 160 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 161 spin_unlock_irq(&qp_table->lock); 162 if (ret) { 163 dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n"); 164 goto err_put_irrl; 165 } 166 167 atomic_set(&hr_qp->refcount, 1); 168 init_completion(&hr_qp->free); 169 170 return 0; 171 172 err_put_irrl: 173 174 return ret; 175 } 176 177 static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn, 178 struct hns_roce_qp *hr_qp) 179 { 180 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 181 struct device *dev = hr_dev->dev; 182 int ret; 183 184 if (!qpn) 185 return -EINVAL; 186 187 hr_qp->qpn = qpn; 188 189 /* Alloc memory for QPC */ 190 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); 191 if (ret) { 192 dev_err(dev, "QPC table get failed\n"); 193 goto err_out; 194 } 195 196 /* Alloc memory for IRRL */ 197 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 198 if (ret) { 199 dev_err(dev, "IRRL table get failed\n"); 200 goto err_put_qp; 201 } 202 203 if (hr_dev->caps.trrl_entry_sz) { 204 /* Alloc memory for TRRL */ 205 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, 206 hr_qp->qpn); 207 if (ret) { 208 dev_err(dev, "TRRL table get failed\n"); 209 goto err_put_irrl; 210 } 211 } 212 213 if (hr_dev->caps.sccc_entry_sz) { 214 /* Alloc memory for SCC CTX */ 215 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table, 216 hr_qp->qpn); 217 if (ret) { 218 dev_err(dev, "SCC CTX table get failed\n"); 219 goto err_put_trrl; 220 } 221 } 222 223 spin_lock_irq(&qp_table->lock); 224 ret = radix_tree_insert(&hr_dev->qp_table_tree, 225 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp); 226 spin_unlock_irq(&qp_table->lock); 227 if (ret) { 228 dev_err(dev, "QPC radix_tree_insert failed\n"); 229 goto err_put_sccc; 230 } 231 232 atomic_set(&hr_qp->refcount, 1); 233 init_completion(&hr_qp->free); 234 235 return 0; 236 237 err_put_sccc: 238 if (hr_dev->caps.sccc_entry_sz) 239 hns_roce_table_put(hr_dev, &qp_table->sccc_table, 240 hr_qp->qpn); 241 242 err_put_trrl: 243 if (hr_dev->caps.trrl_entry_sz) 244 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 245 246 err_put_irrl: 247 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 248 249 err_put_qp: 250 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 251 252 err_out: 253 return ret; 254 } 255 256 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 257 { 258 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 259 unsigned long flags; 260 261 spin_lock_irqsave(&qp_table->lock, flags); 262 radix_tree_delete(&hr_dev->qp_table_tree, 263 hr_qp->qpn & (hr_dev->caps.num_qps - 1)); 264 spin_unlock_irqrestore(&qp_table->lock, flags); 265 } 266 EXPORT_SYMBOL_GPL(hns_roce_qp_remove); 267 268 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 269 { 270 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 271 272 if (atomic_dec_and_test(&hr_qp->refcount)) 273 complete(&hr_qp->free); 274 wait_for_completion(&hr_qp->free); 275 276 if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) { 277 if (hr_dev->caps.trrl_entry_sz) 278 hns_roce_table_put(hr_dev, &qp_table->trrl_table, 279 hr_qp->qpn); 280 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 281 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 282 } 283 } 284 EXPORT_SYMBOL_GPL(hns_roce_qp_free); 285 286 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 287 int cnt) 288 { 289 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 290 291 if (base_qpn < SQP_NUM) 292 return; 293 294 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR); 295 } 296 EXPORT_SYMBOL_GPL(hns_roce_release_range_qp); 297 298 static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev, 299 struct ib_qp_cap *cap, bool is_user, int has_rq, 300 struct hns_roce_qp *hr_qp) 301 { 302 struct device *dev = hr_dev->dev; 303 u32 max_cnt; 304 305 /* Check the validity of QP support capacity */ 306 if (cap->max_recv_wr > hr_dev->caps.max_wqes || 307 cap->max_recv_sge > hr_dev->caps.max_rq_sg) { 308 dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n", 309 cap->max_recv_wr, cap->max_recv_sge); 310 return -EINVAL; 311 } 312 313 /* If srq exist, set zero for relative number of rq */ 314 if (!has_rq) { 315 hr_qp->rq.wqe_cnt = 0; 316 hr_qp->rq.max_gs = 0; 317 cap->max_recv_wr = 0; 318 cap->max_recv_sge = 0; 319 } else { 320 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) { 321 dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n"); 322 return -EINVAL; 323 } 324 325 if (hr_dev->caps.min_wqes) 326 max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes); 327 else 328 max_cnt = cap->max_recv_wr; 329 330 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt); 331 332 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) { 333 dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n"); 334 return -EINVAL; 335 } 336 337 max_cnt = max(1U, cap->max_recv_sge); 338 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt); 339 if (hr_dev->caps.max_rq_sg <= 2) 340 hr_qp->rq.wqe_shift = 341 ilog2(hr_dev->caps.max_rq_desc_sz); 342 else 343 hr_qp->rq.wqe_shift = 344 ilog2(hr_dev->caps.max_rq_desc_sz 345 * hr_qp->rq.max_gs); 346 } 347 348 cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt; 349 cap->max_recv_sge = hr_qp->rq.max_gs; 350 351 return 0; 352 } 353 354 static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev, 355 struct ib_qp_cap *cap, 356 struct hns_roce_qp *hr_qp, 357 struct hns_roce_ib_create_qp *ucmd) 358 { 359 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 360 u8 max_sq_stride = ilog2(roundup_sq_stride); 361 u32 ex_sge_num; 362 u32 page_size; 363 u32 max_cnt; 364 365 /* Sanity check SQ size before proceeding */ 366 if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes || 367 ucmd->log_sq_stride > max_sq_stride || 368 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 369 dev_err(hr_dev->dev, "check SQ size error!\n"); 370 return -EINVAL; 371 } 372 373 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { 374 dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n", 375 cap->max_send_sge); 376 return -EINVAL; 377 } 378 379 hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 380 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 381 382 max_cnt = max(1U, cap->max_send_sge); 383 if (hr_dev->caps.max_sq_sg <= 2) 384 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); 385 else 386 hr_qp->sq.max_gs = max_cnt; 387 388 if (hr_qp->sq.max_gs > 2) 389 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * 390 (hr_qp->sq.max_gs - 2)); 391 392 if ((hr_qp->sq.max_gs > 2) && (hr_dev->pci_dev->revision == 0x20)) { 393 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) { 394 dev_err(hr_dev->dev, 395 "The extended sge cnt error! sge_cnt=%d\n", 396 hr_qp->sge.sge_cnt); 397 return -EINVAL; 398 } 399 } 400 401 hr_qp->sge.sge_shift = 4; 402 ex_sge_num = hr_qp->sge.sge_cnt; 403 404 /* Get buf size, SQ and RQ are aligned to page_szie */ 405 if (hr_dev->caps.max_sq_sg <= 2) { 406 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 407 hr_qp->rq.wqe_shift), PAGE_SIZE) + 408 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 409 hr_qp->sq.wqe_shift), PAGE_SIZE); 410 411 hr_qp->sq.offset = 0; 412 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 413 hr_qp->sq.wqe_shift), PAGE_SIZE); 414 } else { 415 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 416 hr_qp->sge.sge_cnt = 417 max(page_size / (1 << hr_qp->sge.sge_shift), ex_sge_num); 418 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << 419 hr_qp->rq.wqe_shift), page_size) + 420 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt << 421 hr_qp->sge.sge_shift), page_size) + 422 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt << 423 hr_qp->sq.wqe_shift), page_size); 424 425 hr_qp->sq.offset = 0; 426 if (ex_sge_num) { 427 hr_qp->sge.offset = HNS_ROCE_ALOGN_UP( 428 (hr_qp->sq.wqe_cnt << 429 hr_qp->sq.wqe_shift), 430 page_size); 431 hr_qp->rq.offset = hr_qp->sge.offset + 432 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt << 433 hr_qp->sge.sge_shift), 434 page_size); 435 } else { 436 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP( 437 (hr_qp->sq.wqe_cnt << 438 hr_qp->sq.wqe_shift), 439 page_size); 440 } 441 } 442 443 return 0; 444 } 445 446 static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev, 447 struct ib_qp_cap *cap, 448 struct hns_roce_qp *hr_qp) 449 { 450 struct device *dev = hr_dev->dev; 451 u32 page_size; 452 u32 max_cnt; 453 int size; 454 455 if (cap->max_send_wr > hr_dev->caps.max_wqes || 456 cap->max_send_sge > hr_dev->caps.max_sq_sg || 457 cap->max_inline_data > hr_dev->caps.max_sq_inline) { 458 dev_err(dev, "SQ WR or sge or inline data error!\n"); 459 return -EINVAL; 460 } 461 462 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); 463 hr_qp->sq_max_wqes_per_wr = 1; 464 hr_qp->sq_spare_wqes = 0; 465 466 if (hr_dev->caps.min_wqes) 467 max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes); 468 else 469 max_cnt = cap->max_send_wr; 470 471 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt); 472 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) { 473 dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n"); 474 return -EINVAL; 475 } 476 477 /* Get data_seg numbers */ 478 max_cnt = max(1U, cap->max_send_sge); 479 if (hr_dev->caps.max_sq_sg <= 2) 480 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt); 481 else 482 hr_qp->sq.max_gs = max_cnt; 483 484 if (hr_qp->sq.max_gs > 2) { 485 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * 486 (hr_qp->sq.max_gs - 2)); 487 hr_qp->sge.sge_shift = 4; 488 } 489 490 /* ud sqwqe's sge use extend sge */ 491 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) { 492 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt * 493 hr_qp->sq.max_gs); 494 hr_qp->sge.sge_shift = 4; 495 } 496 497 if ((hr_qp->sq.max_gs > 2) && hr_dev->pci_dev->revision == 0x20) { 498 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) { 499 dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n", 500 hr_qp->sge.sge_cnt); 501 return -EINVAL; 502 } 503 } 504 505 /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */ 506 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 507 hr_qp->sq.offset = 0; 508 size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift, 509 page_size); 510 511 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) { 512 hr_qp->sge.sge_cnt = max(page_size/(1 << hr_qp->sge.sge_shift), 513 (u32)hr_qp->sge.sge_cnt); 514 hr_qp->sge.offset = size; 515 size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt << 516 hr_qp->sge.sge_shift, page_size); 517 } 518 519 hr_qp->rq.offset = size; 520 size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift), 521 page_size); 522 hr_qp->buff_size = size; 523 524 /* Get wr and sge number which send */ 525 cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt; 526 cap->max_send_sge = hr_qp->sq.max_gs; 527 528 /* We don't support inline sends for kernel QPs (yet) */ 529 cap->max_inline_data = 0; 530 531 return 0; 532 } 533 534 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr) 535 { 536 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr) 537 return 0; 538 539 return 1; 540 } 541 542 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr) 543 { 544 if (attr->qp_type == IB_QPT_XRC_INI || 545 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 546 !attr->cap.max_recv_wr) 547 return 0; 548 549 return 1; 550 } 551 552 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, 553 struct ib_pd *ib_pd, 554 struct ib_qp_init_attr *init_attr, 555 struct ib_udata *udata, unsigned long sqpn, 556 struct hns_roce_qp *hr_qp) 557 { 558 struct device *dev = hr_dev->dev; 559 struct hns_roce_ib_create_qp ucmd; 560 struct hns_roce_ib_create_qp_resp resp = {}; 561 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( 562 udata, struct hns_roce_ucontext, ibucontext); 563 unsigned long qpn = 0; 564 int ret = 0; 565 u32 page_shift; 566 u32 npages; 567 int i; 568 569 mutex_init(&hr_qp->mutex); 570 spin_lock_init(&hr_qp->sq.lock); 571 spin_lock_init(&hr_qp->rq.lock); 572 573 hr_qp->state = IB_QPS_RESET; 574 575 hr_qp->ibqp.qp_type = init_attr->qp_type; 576 577 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 578 hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_ALL_WR); 579 else 580 hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_REQ_WR); 581 582 ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, udata, 583 hns_roce_qp_has_rq(init_attr), hr_qp); 584 if (ret) { 585 dev_err(dev, "hns_roce_set_rq_size failed\n"); 586 goto err_out; 587 } 588 589 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) && 590 hns_roce_qp_has_rq(init_attr)) { 591 /* allocate recv inline buf */ 592 hr_qp->rq_inl_buf.wqe_list = kcalloc(hr_qp->rq.wqe_cnt, 593 sizeof(struct hns_roce_rinl_wqe), 594 GFP_KERNEL); 595 if (!hr_qp->rq_inl_buf.wqe_list) { 596 ret = -ENOMEM; 597 goto err_out; 598 } 599 600 hr_qp->rq_inl_buf.wqe_cnt = hr_qp->rq.wqe_cnt; 601 602 /* Firstly, allocate a list of sge space buffer */ 603 hr_qp->rq_inl_buf.wqe_list[0].sg_list = 604 kcalloc(hr_qp->rq_inl_buf.wqe_cnt, 605 init_attr->cap.max_recv_sge * 606 sizeof(struct hns_roce_rinl_sge), 607 GFP_KERNEL); 608 if (!hr_qp->rq_inl_buf.wqe_list[0].sg_list) { 609 ret = -ENOMEM; 610 goto err_wqe_list; 611 } 612 613 for (i = 1; i < hr_qp->rq_inl_buf.wqe_cnt; i++) 614 /* Secondly, reallocate the buffer */ 615 hr_qp->rq_inl_buf.wqe_list[i].sg_list = 616 &hr_qp->rq_inl_buf.wqe_list[0].sg_list[i * 617 init_attr->cap.max_recv_sge]; 618 } 619 620 if (udata) { 621 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 622 dev_err(dev, "ib_copy_from_udata error for create qp\n"); 623 ret = -EFAULT; 624 goto err_rq_sge_list; 625 } 626 627 ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, 628 &ucmd); 629 if (ret) { 630 dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n"); 631 goto err_rq_sge_list; 632 } 633 634 hr_qp->umem = ib_umem_get(udata, ucmd.buf_addr, 635 hr_qp->buff_size, 0, 0); 636 if (IS_ERR(hr_qp->umem)) { 637 dev_err(dev, "ib_umem_get error for create qp\n"); 638 ret = PTR_ERR(hr_qp->umem); 639 goto err_rq_sge_list; 640 } 641 642 hr_qp->mtt.mtt_type = MTT_TYPE_WQE; 643 page_shift = PAGE_SHIFT; 644 if (hr_dev->caps.mtt_buf_pg_sz) { 645 npages = (ib_umem_page_count(hr_qp->umem) + 646 (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) / 647 (1 << hr_dev->caps.mtt_buf_pg_sz); 648 page_shift += hr_dev->caps.mtt_buf_pg_sz; 649 ret = hns_roce_mtt_init(hr_dev, npages, 650 page_shift, 651 &hr_qp->mtt); 652 } else { 653 ret = hns_roce_mtt_init(hr_dev, 654 ib_umem_page_count(hr_qp->umem), 655 page_shift, &hr_qp->mtt); 656 } 657 if (ret) { 658 dev_err(dev, "hns_roce_mtt_init error for create qp\n"); 659 goto err_buf; 660 } 661 662 ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt, 663 hr_qp->umem); 664 if (ret) { 665 dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n"); 666 goto err_mtt; 667 } 668 669 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) && 670 (udata->inlen >= sizeof(ucmd)) && 671 (udata->outlen >= sizeof(resp)) && 672 hns_roce_qp_has_sq(init_attr)) { 673 ret = hns_roce_db_map_user(uctx, udata, ucmd.sdb_addr, 674 &hr_qp->sdb); 675 if (ret) { 676 dev_err(dev, "sq record doorbell map failed!\n"); 677 goto err_mtt; 678 } 679 680 /* indicate kernel supports sq record db */ 681 resp.cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB; 682 hr_qp->sdb_en = 1; 683 } 684 685 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 686 (udata->outlen >= sizeof(resp)) && 687 hns_roce_qp_has_rq(init_attr)) { 688 ret = hns_roce_db_map_user(uctx, udata, ucmd.db_addr, 689 &hr_qp->rdb); 690 if (ret) { 691 dev_err(dev, "rq record doorbell map failed!\n"); 692 goto err_sq_dbmap; 693 } 694 695 /* indicate kernel supports rq record db */ 696 resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB; 697 hr_qp->rdb_en = 1; 698 } 699 } else { 700 if (init_attr->create_flags & 701 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 702 dev_err(dev, "init_attr->create_flags error!\n"); 703 ret = -EINVAL; 704 goto err_rq_sge_list; 705 } 706 707 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) { 708 dev_err(dev, "init_attr->create_flags error!\n"); 709 ret = -EINVAL; 710 goto err_rq_sge_list; 711 } 712 713 /* Set SQ size */ 714 ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap, 715 hr_qp); 716 if (ret) { 717 dev_err(dev, "hns_roce_set_kernel_sq_size error!\n"); 718 goto err_rq_sge_list; 719 } 720 721 /* QP doorbell register address */ 722 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + 723 DB_REG_OFFSET * hr_dev->priv_uar.index; 724 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + 725 DB_REG_OFFSET * hr_dev->priv_uar.index; 726 727 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 728 hns_roce_qp_has_rq(init_attr)) { 729 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0); 730 if (ret) { 731 dev_err(dev, "rq record doorbell alloc failed!\n"); 732 goto err_rq_sge_list; 733 } 734 *hr_qp->rdb.db_record = 0; 735 hr_qp->rdb_en = 1; 736 } 737 738 /* Allocate QP buf */ 739 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 740 if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size, 741 (1 << page_shift) * 2, 742 &hr_qp->hr_buf, page_shift)) { 743 dev_err(dev, "hns_roce_buf_alloc error!\n"); 744 ret = -ENOMEM; 745 goto err_db; 746 } 747 748 hr_qp->mtt.mtt_type = MTT_TYPE_WQE; 749 /* Write MTT */ 750 ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages, 751 hr_qp->hr_buf.page_shift, &hr_qp->mtt); 752 if (ret) { 753 dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n"); 754 goto err_buf; 755 } 756 757 ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt, 758 &hr_qp->hr_buf); 759 if (ret) { 760 dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n"); 761 goto err_mtt; 762 } 763 764 hr_qp->sq.wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), 765 GFP_KERNEL); 766 hr_qp->rq.wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), 767 GFP_KERNEL); 768 if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) { 769 ret = -ENOMEM; 770 goto err_wrid; 771 } 772 } 773 774 if (sqpn) { 775 qpn = sqpn; 776 } else { 777 /* Get QPN */ 778 ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn); 779 if (ret) { 780 dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n"); 781 goto err_wrid; 782 } 783 } 784 785 if (init_attr->qp_type == IB_QPT_GSI && 786 hr_dev->hw_rev == HNS_ROCE_HW_VER1) { 787 /* In v1 engine, GSI QP context in RoCE engine's register */ 788 ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp); 789 if (ret) { 790 dev_err(dev, "hns_roce_qp_alloc failed!\n"); 791 goto err_qpn; 792 } 793 } else { 794 ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp); 795 if (ret) { 796 dev_err(dev, "hns_roce_qp_alloc failed!\n"); 797 goto err_qpn; 798 } 799 } 800 801 if (sqpn) 802 hr_qp->doorbell_qpn = 1; 803 else 804 hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn); 805 806 if (udata) { 807 ret = ib_copy_to_udata(udata, &resp, 808 min(udata->outlen, sizeof(resp))); 809 if (ret) 810 goto err_qp; 811 } 812 813 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 814 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); 815 if (ret) 816 goto err_qp; 817 } 818 819 hr_qp->event = hns_roce_ib_qp_event; 820 821 return 0; 822 823 err_qp: 824 if (init_attr->qp_type == IB_QPT_GSI && 825 hr_dev->hw_rev == HNS_ROCE_HW_VER1) 826 hns_roce_qp_remove(hr_dev, hr_qp); 827 else 828 hns_roce_qp_free(hr_dev, hr_qp); 829 830 err_qpn: 831 if (!sqpn) 832 hns_roce_release_range_qp(hr_dev, qpn, 1); 833 834 err_wrid: 835 if (udata) { 836 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 837 (udata->outlen >= sizeof(resp)) && 838 hns_roce_qp_has_rq(init_attr)) 839 hns_roce_db_unmap_user(uctx, &hr_qp->rdb); 840 } else { 841 kfree(hr_qp->sq.wrid); 842 kfree(hr_qp->rq.wrid); 843 } 844 845 err_sq_dbmap: 846 if (udata) 847 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) && 848 (udata->inlen >= sizeof(ucmd)) && 849 (udata->outlen >= sizeof(resp)) && 850 hns_roce_qp_has_sq(init_attr)) 851 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 852 853 err_mtt: 854 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 855 856 err_buf: 857 if (hr_qp->umem) 858 ib_umem_release(hr_qp->umem); 859 else 860 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 861 862 err_db: 863 if (!udata && hns_roce_qp_has_rq(init_attr) && 864 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) 865 hns_roce_free_db(hr_dev, &hr_qp->rdb); 866 867 err_rq_sge_list: 868 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) 869 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 870 871 err_wqe_list: 872 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) 873 kfree(hr_qp->rq_inl_buf.wqe_list); 874 875 err_out: 876 return ret; 877 } 878 879 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, 880 struct ib_qp_init_attr *init_attr, 881 struct ib_udata *udata) 882 { 883 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); 884 struct device *dev = hr_dev->dev; 885 struct hns_roce_sqp *hr_sqp; 886 struct hns_roce_qp *hr_qp; 887 int ret; 888 889 switch (init_attr->qp_type) { 890 case IB_QPT_RC: { 891 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 892 if (!hr_qp) 893 return ERR_PTR(-ENOMEM); 894 895 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0, 896 hr_qp); 897 if (ret) { 898 dev_err(dev, "Create RC QP failed\n"); 899 kfree(hr_qp); 900 return ERR_PTR(ret); 901 } 902 903 hr_qp->ibqp.qp_num = hr_qp->qpn; 904 905 break; 906 } 907 case IB_QPT_GSI: { 908 /* Userspace is not allowed to create special QPs: */ 909 if (udata) { 910 dev_err(dev, "not support usr space GSI\n"); 911 return ERR_PTR(-EINVAL); 912 } 913 914 hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL); 915 if (!hr_sqp) 916 return ERR_PTR(-ENOMEM); 917 918 hr_qp = &hr_sqp->hr_qp; 919 hr_qp->port = init_attr->port_num - 1; 920 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 921 922 /* when hw version is v1, the sqpn is allocated */ 923 if (hr_dev->caps.max_sq_sg <= 2) 924 hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS + 925 hr_dev->iboe.phy_port[hr_qp->port]; 926 else 927 hr_qp->ibqp.qp_num = 1; 928 929 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 930 hr_qp->ibqp.qp_num, hr_qp); 931 if (ret) { 932 dev_err(dev, "Create GSI QP failed!\n"); 933 kfree(hr_sqp); 934 return ERR_PTR(ret); 935 } 936 937 break; 938 } 939 default:{ 940 dev_err(dev, "not support QP type %d\n", init_attr->qp_type); 941 return ERR_PTR(-EINVAL); 942 } 943 } 944 945 return &hr_qp->ibqp; 946 } 947 EXPORT_SYMBOL_GPL(hns_roce_create_qp); 948 949 int to_hr_qp_type(int qp_type) 950 { 951 int transport_type; 952 953 if (qp_type == IB_QPT_RC) 954 transport_type = SERV_TYPE_RC; 955 else if (qp_type == IB_QPT_UC) 956 transport_type = SERV_TYPE_UC; 957 else if (qp_type == IB_QPT_UD) 958 transport_type = SERV_TYPE_UD; 959 else if (qp_type == IB_QPT_GSI) 960 transport_type = SERV_TYPE_UD; 961 else 962 transport_type = -1; 963 964 return transport_type; 965 } 966 EXPORT_SYMBOL_GPL(to_hr_qp_type); 967 968 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 969 int attr_mask, struct ib_udata *udata) 970 { 971 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 972 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 973 enum ib_qp_state cur_state, new_state; 974 struct device *dev = hr_dev->dev; 975 int ret = -EINVAL; 976 int p; 977 enum ib_mtu active_mtu; 978 979 mutex_lock(&hr_qp->mutex); 980 981 cur_state = attr_mask & IB_QP_CUR_STATE ? 982 attr->cur_qp_state : (enum ib_qp_state)hr_qp->state; 983 new_state = attr_mask & IB_QP_STATE ? 984 attr->qp_state : cur_state; 985 986 if (ibqp->uobject && 987 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) { 988 if (hr_qp->sdb_en == 1) { 989 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); 990 991 if (hr_qp->rdb_en == 1) 992 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); 993 } else { 994 dev_warn(dev, "flush cqe is not supported in userspace!\n"); 995 goto out; 996 } 997 } 998 999 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 1000 attr_mask)) { 1001 dev_err(dev, "ib_modify_qp_is_ok failed\n"); 1002 goto out; 1003 } 1004 1005 if ((attr_mask & IB_QP_PORT) && 1006 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { 1007 dev_err(dev, "attr port_num invalid.attr->port_num=%d\n", 1008 attr->port_num); 1009 goto out; 1010 } 1011 1012 if (attr_mask & IB_QP_PKEY_INDEX) { 1013 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1014 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { 1015 dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n", 1016 attr->pkey_index); 1017 goto out; 1018 } 1019 } 1020 1021 if (attr_mask & IB_QP_PATH_MTU) { 1022 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1023 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 1024 1025 if ((hr_dev->caps.max_mtu == IB_MTU_4096 && 1026 attr->path_mtu > IB_MTU_4096) || 1027 (hr_dev->caps.max_mtu == IB_MTU_2048 && 1028 attr->path_mtu > IB_MTU_2048) || 1029 attr->path_mtu < IB_MTU_256 || 1030 attr->path_mtu > active_mtu) { 1031 dev_err(dev, "attr path_mtu(%d)invalid while modify qp", 1032 attr->path_mtu); 1033 goto out; 1034 } 1035 } 1036 1037 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1038 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { 1039 dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n", 1040 attr->max_rd_atomic); 1041 goto out; 1042 } 1043 1044 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1045 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { 1046 dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n", 1047 attr->max_dest_rd_atomic); 1048 goto out; 1049 } 1050 1051 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1052 if (hr_dev->caps.min_wqes) { 1053 ret = -EPERM; 1054 dev_err(dev, "cur_state=%d new_state=%d\n", cur_state, 1055 new_state); 1056 } else { 1057 ret = 0; 1058 } 1059 1060 goto out; 1061 } 1062 1063 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, 1064 new_state); 1065 1066 out: 1067 mutex_unlock(&hr_qp->mutex); 1068 1069 return ret; 1070 } 1071 1072 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) 1073 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1074 { 1075 if (send_cq == recv_cq) { 1076 spin_lock_irq(&send_cq->lock); 1077 __acquire(&recv_cq->lock); 1078 } else if (send_cq->cqn < recv_cq->cqn) { 1079 spin_lock_irq(&send_cq->lock); 1080 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1081 } else { 1082 spin_lock_irq(&recv_cq->lock); 1083 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1084 } 1085 } 1086 EXPORT_SYMBOL_GPL(hns_roce_lock_cqs); 1087 1088 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1089 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 1090 __releases(&recv_cq->lock) 1091 { 1092 if (send_cq == recv_cq) { 1093 __release(&recv_cq->lock); 1094 spin_unlock_irq(&send_cq->lock); 1095 } else if (send_cq->cqn < recv_cq->cqn) { 1096 spin_unlock(&recv_cq->lock); 1097 spin_unlock_irq(&send_cq->lock); 1098 } else { 1099 spin_unlock(&send_cq->lock); 1100 spin_unlock_irq(&recv_cq->lock); 1101 } 1102 } 1103 EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs); 1104 1105 static void *get_wqe(struct hns_roce_qp *hr_qp, int offset) 1106 { 1107 1108 return hns_roce_buf_offset(&hr_qp->hr_buf, offset); 1109 } 1110 1111 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n) 1112 { 1113 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 1114 } 1115 EXPORT_SYMBOL_GPL(get_recv_wqe); 1116 1117 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n) 1118 { 1119 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 1120 } 1121 EXPORT_SYMBOL_GPL(get_send_wqe); 1122 1123 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n) 1124 { 1125 return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset + 1126 (n << hr_qp->sge.sge_shift)); 1127 } 1128 EXPORT_SYMBOL_GPL(get_send_extend_sge); 1129 1130 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1131 struct ib_cq *ib_cq) 1132 { 1133 struct hns_roce_cq *hr_cq; 1134 u32 cur; 1135 1136 cur = hr_wq->head - hr_wq->tail; 1137 if (likely(cur + nreq < hr_wq->max_post)) 1138 return false; 1139 1140 hr_cq = to_hr_cq(ib_cq); 1141 spin_lock(&hr_cq->lock); 1142 cur = hr_wq->head - hr_wq->tail; 1143 spin_unlock(&hr_cq->lock); 1144 1145 return cur + nreq >= hr_wq->max_post; 1146 } 1147 EXPORT_SYMBOL_GPL(hns_roce_wq_overflow); 1148 1149 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 1150 { 1151 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 1152 int reserved_from_top = 0; 1153 int reserved_from_bot; 1154 int ret; 1155 1156 mutex_init(&qp_table->scc_mutex); 1157 spin_lock_init(&qp_table->lock); 1158 INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC); 1159 1160 /* In hw v1, a port include two SQP, six ports total 12 */ 1161 if (hr_dev->caps.max_sq_sg <= 2) 1162 reserved_from_bot = SQP_NUM; 1163 else 1164 reserved_from_bot = hr_dev->caps.reserved_qps; 1165 1166 ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps, 1167 hr_dev->caps.num_qps - 1, reserved_from_bot, 1168 reserved_from_top); 1169 if (ret) { 1170 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n", 1171 ret); 1172 return ret; 1173 } 1174 1175 return 0; 1176 } 1177 1178 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) 1179 { 1180 hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap); 1181 } 1182