1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/pci.h> 35 #include <rdma/ib_addr.h> 36 #include <rdma/ib_umem.h> 37 #include <rdma/uverbs_ioctl.h> 38 #include "hns_roce_common.h" 39 #include "hns_roce_device.h" 40 #include "hns_roce_hem.h" 41 42 static void flush_work_handle(struct work_struct *work) 43 { 44 struct hns_roce_work *flush_work = container_of(work, 45 struct hns_roce_work, work); 46 struct hns_roce_qp *hr_qp = container_of(flush_work, 47 struct hns_roce_qp, flush_work); 48 struct device *dev = flush_work->hr_dev->dev; 49 struct ib_qp_attr attr; 50 int attr_mask; 51 int ret; 52 53 attr_mask = IB_QP_STATE; 54 attr.qp_state = IB_QPS_ERR; 55 56 if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) { 57 ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL); 58 if (ret) 59 dev_err(dev, "modify QP to error state failed(%d) during CQE flush\n", 60 ret); 61 } 62 63 /* 64 * make sure we signal QP destroy leg that flush QP was completed 65 * so that it can safely proceed ahead now and destroy QP 66 */ 67 if (refcount_dec_and_test(&hr_qp->refcount)) 68 complete(&hr_qp->free); 69 } 70 71 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 72 { 73 struct hns_roce_work *flush_work = &hr_qp->flush_work; 74 75 flush_work->hr_dev = hr_dev; 76 INIT_WORK(&flush_work->work, flush_work_handle); 77 refcount_inc(&hr_qp->refcount); 78 queue_work(hr_dev->irq_workq, &flush_work->work); 79 } 80 81 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp) 82 { 83 /* 84 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state 85 * gets into errored mode. Hence, as a workaround to this 86 * hardware limitation, driver needs to assist in flushing. But 87 * the flushing operation uses mailbox to convey the QP state to 88 * the hardware and which can sleep due to the mutex protection 89 * around the mailbox calls. Hence, use the deferred flush for 90 * now. 91 */ 92 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 93 init_flush_work(dev, qp); 94 } 95 96 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 97 { 98 struct device *dev = hr_dev->dev; 99 struct hns_roce_qp *qp; 100 101 xa_lock(&hr_dev->qp_table_xa); 102 qp = __hns_roce_qp_lookup(hr_dev, qpn); 103 if (qp) 104 refcount_inc(&qp->refcount); 105 xa_unlock(&hr_dev->qp_table_xa); 106 107 if (!qp) { 108 dev_warn(dev, "async event for bogus QP %08x\n", qpn); 109 return; 110 } 111 112 if (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || 113 event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || 114 event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR || 115 event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION || 116 event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH) { 117 qp->state = IB_QPS_ERR; 118 119 flush_cqe(hr_dev, qp); 120 } 121 122 qp->event(qp, (enum hns_roce_event)event_type); 123 124 if (refcount_dec_and_test(&qp->refcount)) 125 complete(&qp->free); 126 } 127 128 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, 129 enum hns_roce_event type) 130 { 131 struct ib_qp *ibqp = &hr_qp->ibqp; 132 struct ib_event event; 133 134 if (ibqp->event_handler) { 135 event.device = ibqp->device; 136 event.element.qp = ibqp; 137 switch (type) { 138 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 139 event.event = IB_EVENT_PATH_MIG; 140 break; 141 case HNS_ROCE_EVENT_TYPE_COMM_EST: 142 event.event = IB_EVENT_COMM_EST; 143 break; 144 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 145 event.event = IB_EVENT_SQ_DRAINED; 146 break; 147 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 148 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 149 break; 150 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 151 event.event = IB_EVENT_QP_FATAL; 152 break; 153 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 154 event.event = IB_EVENT_PATH_MIG_ERR; 155 break; 156 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 157 event.event = IB_EVENT_QP_REQ_ERR; 158 break; 159 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 160 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 161 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 162 event.event = IB_EVENT_QP_ACCESS_ERR; 163 break; 164 default: 165 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", 166 type, hr_qp->qpn); 167 return; 168 } 169 ibqp->event_handler(&event, ibqp->qp_context); 170 } 171 } 172 173 static u8 get_least_load_bankid_for_qp(struct hns_roce_bank *bank) 174 { 175 u32 least_load = bank[0].inuse; 176 u8 bankid = 0; 177 u32 bankcnt; 178 u8 i; 179 180 for (i = 1; i < HNS_ROCE_QP_BANK_NUM; i++) { 181 bankcnt = bank[i].inuse; 182 if (bankcnt < least_load) { 183 least_load = bankcnt; 184 bankid = i; 185 } 186 } 187 188 return bankid; 189 } 190 191 static int alloc_qpn_with_bankid(struct hns_roce_bank *bank, u8 bankid, 192 unsigned long *qpn) 193 { 194 int id; 195 196 id = ida_alloc_range(&bank->ida, bank->next, bank->max, GFP_KERNEL); 197 if (id < 0) { 198 id = ida_alloc_range(&bank->ida, bank->min, bank->max, 199 GFP_KERNEL); 200 if (id < 0) 201 return id; 202 } 203 204 /* the QPN should keep increasing until the max value is reached. */ 205 bank->next = (id + 1) > bank->max ? bank->min : id + 1; 206 207 /* the lower 3 bits is bankid */ 208 *qpn = (id << 3) | bankid; 209 210 return 0; 211 } 212 static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 213 { 214 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 215 unsigned long num = 0; 216 u8 bankid; 217 int ret; 218 219 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) { 220 num = 1; 221 } else { 222 mutex_lock(&qp_table->bank_mutex); 223 bankid = get_least_load_bankid_for_qp(qp_table->bank); 224 225 ret = alloc_qpn_with_bankid(&qp_table->bank[bankid], bankid, 226 &num); 227 if (ret) { 228 ibdev_err(&hr_dev->ib_dev, 229 "failed to alloc QPN, ret = %d\n", ret); 230 mutex_unlock(&qp_table->bank_mutex); 231 return ret; 232 } 233 234 qp_table->bank[bankid].inuse++; 235 mutex_unlock(&qp_table->bank_mutex); 236 } 237 238 hr_qp->qpn = num; 239 240 return 0; 241 } 242 243 static void add_qp_to_list(struct hns_roce_dev *hr_dev, 244 struct hns_roce_qp *hr_qp, 245 struct ib_cq *send_cq, struct ib_cq *recv_cq) 246 { 247 struct hns_roce_cq *hr_send_cq, *hr_recv_cq; 248 unsigned long flags; 249 250 hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL; 251 hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL; 252 253 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 254 hns_roce_lock_cqs(hr_send_cq, hr_recv_cq); 255 256 list_add_tail(&hr_qp->node, &hr_dev->qp_list); 257 if (hr_send_cq) 258 list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list); 259 if (hr_recv_cq) 260 list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list); 261 262 hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq); 263 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 264 } 265 266 static int hns_roce_qp_store(struct hns_roce_dev *hr_dev, 267 struct hns_roce_qp *hr_qp, 268 struct ib_qp_init_attr *init_attr) 269 { 270 struct xarray *xa = &hr_dev->qp_table_xa; 271 int ret; 272 273 if (!hr_qp->qpn) 274 return -EINVAL; 275 276 ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL)); 277 if (ret) 278 dev_err(hr_dev->dev, "failed to xa store for QPC\n"); 279 else 280 /* add QP to device's QP list for softwc */ 281 add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq, 282 init_attr->recv_cq); 283 284 return ret; 285 } 286 287 static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 288 { 289 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 290 struct device *dev = hr_dev->dev; 291 int ret; 292 293 if (!hr_qp->qpn) 294 return -EINVAL; 295 296 /* Alloc memory for QPC */ 297 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); 298 if (ret) { 299 dev_err(dev, "failed to get QPC table\n"); 300 goto err_out; 301 } 302 303 /* Alloc memory for IRRL */ 304 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 305 if (ret) { 306 dev_err(dev, "failed to get IRRL table\n"); 307 goto err_put_qp; 308 } 309 310 if (hr_dev->caps.trrl_entry_sz) { 311 /* Alloc memory for TRRL */ 312 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, 313 hr_qp->qpn); 314 if (ret) { 315 dev_err(dev, "failed to get TRRL table\n"); 316 goto err_put_irrl; 317 } 318 } 319 320 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 321 /* Alloc memory for SCC CTX */ 322 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table, 323 hr_qp->qpn); 324 if (ret) { 325 dev_err(dev, "failed to get SCC CTX table\n"); 326 goto err_put_trrl; 327 } 328 } 329 330 return 0; 331 332 err_put_trrl: 333 if (hr_dev->caps.trrl_entry_sz) 334 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 335 336 err_put_irrl: 337 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 338 339 err_put_qp: 340 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 341 342 err_out: 343 return ret; 344 } 345 346 static void qp_user_mmap_entry_remove(struct hns_roce_qp *hr_qp) 347 { 348 rdma_user_mmap_entry_remove(&hr_qp->dwqe_mmap_entry->rdma_entry); 349 } 350 351 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 352 { 353 struct xarray *xa = &hr_dev->qp_table_xa; 354 unsigned long flags; 355 356 list_del(&hr_qp->node); 357 358 if (hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) 359 list_del(&hr_qp->sq_node); 360 361 if (hr_qp->ibqp.qp_type != IB_QPT_XRC_INI && 362 hr_qp->ibqp.qp_type != IB_QPT_XRC_TGT) 363 list_del(&hr_qp->rq_node); 364 365 xa_lock_irqsave(xa, flags); 366 __xa_erase(xa, hr_qp->qpn); 367 xa_unlock_irqrestore(xa, flags); 368 } 369 370 static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 371 { 372 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 373 374 if (hr_dev->caps.trrl_entry_sz) 375 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 376 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 377 } 378 379 static inline u8 get_qp_bankid(unsigned long qpn) 380 { 381 /* The lower 3 bits of QPN are used to hash to different banks */ 382 return (u8)(qpn & GENMASK(2, 0)); 383 } 384 385 static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 386 { 387 u8 bankid; 388 389 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 390 return; 391 392 if (hr_qp->qpn < hr_dev->caps.reserved_qps) 393 return; 394 395 bankid = get_qp_bankid(hr_qp->qpn); 396 397 ida_free(&hr_dev->qp_table.bank[bankid].ida, hr_qp->qpn >> 3); 398 399 mutex_lock(&hr_dev->qp_table.bank_mutex); 400 hr_dev->qp_table.bank[bankid].inuse--; 401 mutex_unlock(&hr_dev->qp_table.bank_mutex); 402 } 403 404 static u32 proc_rq_sge(struct hns_roce_dev *dev, struct hns_roce_qp *hr_qp, 405 bool user) 406 { 407 u32 max_sge = dev->caps.max_rq_sg; 408 409 if (dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 410 return max_sge; 411 412 /* Reserve SGEs only for HIP08 in kernel; The userspace driver will 413 * calculate number of max_sge with reserved SGEs when allocating wqe 414 * buf, so there is no need to do this again in kernel. But the number 415 * may exceed the capacity of SGEs recorded in the firmware, so the 416 * kernel driver should just adapt the value accordingly. 417 */ 418 if (user) 419 max_sge = roundup_pow_of_two(max_sge + 1); 420 else 421 hr_qp->rq.rsv_sge = 1; 422 423 return max_sge; 424 } 425 426 static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, 427 struct hns_roce_qp *hr_qp, int has_rq, bool user) 428 { 429 u32 max_sge = proc_rq_sge(hr_dev, hr_qp, user); 430 u32 cnt; 431 432 /* If srq exist, set zero for relative number of rq */ 433 if (!has_rq) { 434 hr_qp->rq.wqe_cnt = 0; 435 hr_qp->rq.max_gs = 0; 436 cap->max_recv_wr = 0; 437 cap->max_recv_sge = 0; 438 439 return 0; 440 } 441 442 /* Check the validity of QP support capacity */ 443 if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes || 444 cap->max_recv_sge > max_sge) { 445 ibdev_err(&hr_dev->ib_dev, 446 "RQ config error, depth = %u, sge = %u\n", 447 cap->max_recv_wr, cap->max_recv_sge); 448 return -EINVAL; 449 } 450 451 cnt = roundup_pow_of_two(max(cap->max_recv_wr, hr_dev->caps.min_wqes)); 452 if (cnt > hr_dev->caps.max_wqes) { 453 ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n", 454 cap->max_recv_wr); 455 return -EINVAL; 456 } 457 458 hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge) + 459 hr_qp->rq.rsv_sge); 460 461 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz * 462 hr_qp->rq.max_gs); 463 464 hr_qp->rq.wqe_cnt = cnt; 465 466 cap->max_recv_wr = cnt; 467 cap->max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 468 469 return 0; 470 } 471 472 static u32 get_max_inline_data(struct hns_roce_dev *hr_dev, 473 struct ib_qp_cap *cap) 474 { 475 if (cap->max_inline_data) { 476 cap->max_inline_data = roundup_pow_of_two(cap->max_inline_data); 477 return min(cap->max_inline_data, 478 hr_dev->caps.max_sq_inline); 479 } 480 481 return 0; 482 } 483 484 static void update_inline_data(struct hns_roce_qp *hr_qp, 485 struct ib_qp_cap *cap) 486 { 487 u32 sge_num = hr_qp->sq.ext_sge_cnt; 488 489 if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) { 490 if (!(hr_qp->ibqp.qp_type == IB_QPT_GSI || 491 hr_qp->ibqp.qp_type == IB_QPT_UD)) 492 sge_num = max((u32)HNS_ROCE_SGE_IN_WQE, sge_num); 493 494 cap->max_inline_data = max(cap->max_inline_data, 495 sge_num * HNS_ROCE_SGE_SIZE); 496 } 497 498 hr_qp->max_inline_data = cap->max_inline_data; 499 } 500 501 static u32 get_sge_num_from_max_send_sge(bool is_ud_or_gsi, 502 u32 max_send_sge) 503 { 504 unsigned int std_sge_num; 505 unsigned int min_sge; 506 507 std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE; 508 min_sge = is_ud_or_gsi ? 1 : 0; 509 return max_send_sge > std_sge_num ? (max_send_sge - std_sge_num) : 510 min_sge; 511 } 512 513 static unsigned int get_sge_num_from_max_inl_data(bool is_ud_or_gsi, 514 u32 max_inline_data) 515 { 516 unsigned int inline_sge; 517 518 inline_sge = roundup_pow_of_two(max_inline_data) / HNS_ROCE_SGE_SIZE; 519 520 /* 521 * if max_inline_data less than 522 * HNS_ROCE_SGE_IN_WQE * HNS_ROCE_SGE_SIZE, 523 * In addition to ud's mode, no need to extend sge. 524 */ 525 if (!is_ud_or_gsi && inline_sge <= HNS_ROCE_SGE_IN_WQE) 526 inline_sge = 0; 527 528 return inline_sge; 529 } 530 531 static void set_ext_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt, 532 struct hns_roce_qp *hr_qp, struct ib_qp_cap *cap) 533 { 534 bool is_ud_or_gsi = (hr_qp->ibqp.qp_type == IB_QPT_GSI || 535 hr_qp->ibqp.qp_type == IB_QPT_UD); 536 unsigned int std_sge_num; 537 u32 inline_ext_sge = 0; 538 u32 ext_wqe_sge_cnt; 539 u32 total_sge_cnt; 540 541 cap->max_inline_data = get_max_inline_data(hr_dev, cap); 542 543 hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT; 544 std_sge_num = is_ud_or_gsi ? 0 : HNS_ROCE_SGE_IN_WQE; 545 ext_wqe_sge_cnt = get_sge_num_from_max_send_sge(is_ud_or_gsi, 546 cap->max_send_sge); 547 548 if (hr_qp->config & HNS_ROCE_EXSGE_FLAGS) { 549 inline_ext_sge = max(ext_wqe_sge_cnt, 550 get_sge_num_from_max_inl_data(is_ud_or_gsi, 551 cap->max_inline_data)); 552 hr_qp->sq.ext_sge_cnt = inline_ext_sge ? 553 roundup_pow_of_two(inline_ext_sge) : 0; 554 555 hr_qp->sq.max_gs = max(1U, (hr_qp->sq.ext_sge_cnt + std_sge_num)); 556 hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg); 557 558 ext_wqe_sge_cnt = hr_qp->sq.ext_sge_cnt; 559 } else { 560 hr_qp->sq.max_gs = max(1U, cap->max_send_sge); 561 hr_qp->sq.max_gs = min(hr_qp->sq.max_gs, hr_dev->caps.max_sq_sg); 562 hr_qp->sq.ext_sge_cnt = hr_qp->sq.max_gs; 563 } 564 565 /* If the number of extended sge is not zero, they MUST use the 566 * space of HNS_HW_PAGE_SIZE at least. 567 */ 568 if (ext_wqe_sge_cnt) { 569 total_sge_cnt = roundup_pow_of_two(sq_wqe_cnt * ext_wqe_sge_cnt); 570 hr_qp->sge.sge_cnt = max(total_sge_cnt, 571 (u32)HNS_HW_PAGE_SIZE / HNS_ROCE_SGE_SIZE); 572 } 573 574 update_inline_data(hr_qp, cap); 575 } 576 577 static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev, 578 struct ib_qp_cap *cap, 579 struct hns_roce_ib_create_qp *ucmd) 580 { 581 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 582 u8 max_sq_stride = ilog2(roundup_sq_stride); 583 584 /* Sanity check SQ size before proceeding */ 585 if (ucmd->log_sq_stride > max_sq_stride || 586 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 587 ibdev_err(&hr_dev->ib_dev, "failed to check SQ stride size.\n"); 588 return -EINVAL; 589 } 590 591 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { 592 ibdev_err(&hr_dev->ib_dev, "failed to check SQ SGE size %u.\n", 593 cap->max_send_sge); 594 return -EINVAL; 595 } 596 597 return 0; 598 } 599 600 static int set_user_sq_size(struct hns_roce_dev *hr_dev, 601 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp, 602 struct hns_roce_ib_create_qp *ucmd) 603 { 604 struct ib_device *ibdev = &hr_dev->ib_dev; 605 u32 cnt = 0; 606 int ret; 607 608 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || 609 cnt > hr_dev->caps.max_wqes) 610 return -EINVAL; 611 612 ret = check_sq_size_with_integrity(hr_dev, cap, ucmd); 613 if (ret) { 614 ibdev_err(ibdev, "failed to check user SQ size, ret = %d.\n", 615 ret); 616 return ret; 617 } 618 619 set_ext_sge_param(hr_dev, cnt, hr_qp, cap); 620 621 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 622 hr_qp->sq.wqe_cnt = cnt; 623 cap->max_send_sge = hr_qp->sq.max_gs; 624 625 return 0; 626 } 627 628 static int set_wqe_buf_attr(struct hns_roce_dev *hr_dev, 629 struct hns_roce_qp *hr_qp, 630 struct hns_roce_buf_attr *buf_attr) 631 { 632 int buf_size; 633 int idx = 0; 634 635 hr_qp->buff_size = 0; 636 637 /* SQ WQE */ 638 hr_qp->sq.offset = 0; 639 buf_size = to_hr_hem_entries_size(hr_qp->sq.wqe_cnt, 640 hr_qp->sq.wqe_shift); 641 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 642 buf_attr->region[idx].size = buf_size; 643 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sq_hop_num; 644 idx++; 645 hr_qp->buff_size += buf_size; 646 } 647 648 /* extend SGE WQE in SQ */ 649 hr_qp->sge.offset = hr_qp->buff_size; 650 buf_size = to_hr_hem_entries_size(hr_qp->sge.sge_cnt, 651 hr_qp->sge.sge_shift); 652 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 653 buf_attr->region[idx].size = buf_size; 654 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sge_hop_num; 655 idx++; 656 hr_qp->buff_size += buf_size; 657 } 658 659 /* RQ WQE */ 660 hr_qp->rq.offset = hr_qp->buff_size; 661 buf_size = to_hr_hem_entries_size(hr_qp->rq.wqe_cnt, 662 hr_qp->rq.wqe_shift); 663 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 664 buf_attr->region[idx].size = buf_size; 665 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_rq_hop_num; 666 idx++; 667 hr_qp->buff_size += buf_size; 668 } 669 670 if (hr_qp->buff_size < 1) 671 return -EINVAL; 672 673 buf_attr->page_shift = HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 674 buf_attr->region_count = idx; 675 676 return 0; 677 } 678 679 static int set_kernel_sq_size(struct hns_roce_dev *hr_dev, 680 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp) 681 { 682 struct ib_device *ibdev = &hr_dev->ib_dev; 683 u32 cnt; 684 685 if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes || 686 cap->max_send_sge > hr_dev->caps.max_sq_sg) { 687 ibdev_err(ibdev, "failed to check SQ WR or SGE num.\n"); 688 return -EINVAL; 689 } 690 691 cnt = roundup_pow_of_two(max(cap->max_send_wr, hr_dev->caps.min_wqes)); 692 if (cnt > hr_dev->caps.max_wqes) { 693 ibdev_err(ibdev, "failed to check WQE num, WQE num = %u.\n", 694 cnt); 695 return -EINVAL; 696 } 697 698 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); 699 hr_qp->sq.wqe_cnt = cnt; 700 701 set_ext_sge_param(hr_dev, cnt, hr_qp, cap); 702 703 /* sync the parameters of kernel QP to user's configuration */ 704 cap->max_send_wr = cnt; 705 cap->max_send_sge = hr_qp->sq.max_gs; 706 707 return 0; 708 } 709 710 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr) 711 { 712 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr) 713 return 0; 714 715 return 1; 716 } 717 718 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr) 719 { 720 if (attr->qp_type == IB_QPT_XRC_INI || 721 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 722 !attr->cap.max_recv_wr) 723 return 0; 724 725 return 1; 726 } 727 728 static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 729 struct ib_qp_init_attr *init_attr, 730 struct ib_udata *udata, unsigned long addr) 731 { 732 struct ib_device *ibdev = &hr_dev->ib_dev; 733 struct hns_roce_buf_attr buf_attr = {}; 734 int ret; 735 736 ret = set_wqe_buf_attr(hr_dev, hr_qp, &buf_attr); 737 if (ret) { 738 ibdev_err(ibdev, "failed to split WQE buf, ret = %d.\n", ret); 739 goto err_inline; 740 } 741 ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr, 742 PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz, 743 udata, addr); 744 if (ret) { 745 ibdev_err(ibdev, "failed to create WQE mtr, ret = %d.\n", ret); 746 goto err_inline; 747 } 748 749 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_DIRECT_WQE) 750 hr_qp->en_flags |= HNS_ROCE_QP_CAP_DIRECT_WQE; 751 752 return 0; 753 754 err_inline: 755 756 return ret; 757 } 758 759 static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 760 { 761 hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr); 762 } 763 764 static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev, 765 struct ib_qp_init_attr *init_attr, 766 struct ib_udata *udata, 767 struct hns_roce_ib_create_qp_resp *resp, 768 struct hns_roce_ib_create_qp *ucmd) 769 { 770 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 771 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 772 hns_roce_qp_has_sq(init_attr) && 773 udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr)); 774 } 775 776 static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev, 777 struct ib_qp_init_attr *init_attr, 778 struct ib_udata *udata, 779 struct hns_roce_ib_create_qp_resp *resp) 780 { 781 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 782 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 783 hns_roce_qp_has_rq(init_attr)); 784 } 785 786 static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev, 787 struct ib_qp_init_attr *init_attr) 788 { 789 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) && 790 hns_roce_qp_has_rq(init_attr)); 791 } 792 793 static int qp_mmap_entry(struct hns_roce_qp *hr_qp, 794 struct hns_roce_dev *hr_dev, 795 struct ib_udata *udata, 796 struct hns_roce_ib_create_qp_resp *resp) 797 { 798 struct hns_roce_ucontext *uctx = 799 rdma_udata_to_drv_context(udata, 800 struct hns_roce_ucontext, ibucontext); 801 struct rdma_user_mmap_entry *rdma_entry; 802 u64 address; 803 804 address = hr_dev->dwqe_page + hr_qp->qpn * HNS_ROCE_DWQE_SIZE; 805 806 hr_qp->dwqe_mmap_entry = 807 hns_roce_user_mmap_entry_insert(&uctx->ibucontext, address, 808 HNS_ROCE_DWQE_SIZE, 809 HNS_ROCE_MMAP_TYPE_DWQE); 810 811 if (!hr_qp->dwqe_mmap_entry) { 812 ibdev_err(&hr_dev->ib_dev, "failed to get dwqe mmap entry.\n"); 813 return -ENOMEM; 814 } 815 816 rdma_entry = &hr_qp->dwqe_mmap_entry->rdma_entry; 817 resp->dwqe_mmap_key = rdma_user_mmap_get_offset(rdma_entry); 818 819 return 0; 820 } 821 822 static int alloc_user_qp_db(struct hns_roce_dev *hr_dev, 823 struct hns_roce_qp *hr_qp, 824 struct ib_qp_init_attr *init_attr, 825 struct ib_udata *udata, 826 struct hns_roce_ib_create_qp *ucmd, 827 struct hns_roce_ib_create_qp_resp *resp) 828 { 829 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 830 struct hns_roce_ucontext, ibucontext); 831 struct ib_device *ibdev = &hr_dev->ib_dev; 832 int ret; 833 834 if (user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd)) { 835 ret = hns_roce_db_map_user(uctx, ucmd->sdb_addr, &hr_qp->sdb); 836 if (ret) { 837 ibdev_err(ibdev, 838 "failed to map user SQ doorbell, ret = %d.\n", 839 ret); 840 goto err_out; 841 } 842 hr_qp->en_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB; 843 } 844 845 if (user_qp_has_rdb(hr_dev, init_attr, udata, resp)) { 846 ret = hns_roce_db_map_user(uctx, ucmd->db_addr, &hr_qp->rdb); 847 if (ret) { 848 ibdev_err(ibdev, 849 "failed to map user RQ doorbell, ret = %d.\n", 850 ret); 851 goto err_sdb; 852 } 853 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 854 } 855 856 return 0; 857 858 err_sdb: 859 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 860 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 861 err_out: 862 return ret; 863 } 864 865 static int alloc_kernel_qp_db(struct hns_roce_dev *hr_dev, 866 struct hns_roce_qp *hr_qp, 867 struct ib_qp_init_attr *init_attr) 868 { 869 struct ib_device *ibdev = &hr_dev->ib_dev; 870 int ret; 871 872 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 873 hr_qp->sq.db_reg = hr_dev->mem_base + 874 HNS_ROCE_DWQE_SIZE * hr_qp->qpn; 875 else 876 hr_qp->sq.db_reg = hr_dev->reg_base + hr_dev->sdb_offset + 877 DB_REG_OFFSET * hr_dev->priv_uar.index; 878 879 hr_qp->rq.db_reg = hr_dev->reg_base + hr_dev->odb_offset + 880 DB_REG_OFFSET * hr_dev->priv_uar.index; 881 882 if (kernel_qp_has_rdb(hr_dev, init_attr)) { 883 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0); 884 if (ret) { 885 ibdev_err(ibdev, 886 "failed to alloc kernel RQ doorbell, ret = %d.\n", 887 ret); 888 return ret; 889 } 890 *hr_qp->rdb.db_record = 0; 891 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 892 } 893 894 return 0; 895 } 896 897 static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 898 struct ib_qp_init_attr *init_attr, 899 struct ib_udata *udata, 900 struct hns_roce_ib_create_qp *ucmd, 901 struct hns_roce_ib_create_qp_resp *resp) 902 { 903 int ret; 904 905 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SDI_MODE) 906 hr_qp->en_flags |= HNS_ROCE_QP_CAP_OWNER_DB; 907 908 if (udata) { 909 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) { 910 ret = qp_mmap_entry(hr_qp, hr_dev, udata, resp); 911 if (ret) 912 return ret; 913 } 914 915 ret = alloc_user_qp_db(hr_dev, hr_qp, init_attr, udata, ucmd, 916 resp); 917 if (ret) 918 goto err_remove_qp; 919 } else { 920 ret = alloc_kernel_qp_db(hr_dev, hr_qp, init_attr); 921 if (ret) 922 return ret; 923 } 924 925 return 0; 926 927 err_remove_qp: 928 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) 929 qp_user_mmap_entry_remove(hr_qp); 930 931 return ret; 932 } 933 934 static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 935 struct ib_udata *udata) 936 { 937 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( 938 udata, struct hns_roce_ucontext, ibucontext); 939 940 if (udata) { 941 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 942 hns_roce_db_unmap_user(uctx, &hr_qp->rdb); 943 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 944 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 945 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE) 946 qp_user_mmap_entry_remove(hr_qp); 947 } else { 948 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 949 hns_roce_free_db(hr_dev, &hr_qp->rdb); 950 } 951 } 952 953 static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev, 954 struct hns_roce_qp *hr_qp) 955 { 956 struct ib_device *ibdev = &hr_dev->ib_dev; 957 u64 *sq_wrid = NULL; 958 u64 *rq_wrid = NULL; 959 int ret; 960 961 sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL); 962 if (ZERO_OR_NULL_PTR(sq_wrid)) { 963 ibdev_err(ibdev, "failed to alloc SQ wrid.\n"); 964 return -ENOMEM; 965 } 966 967 if (hr_qp->rq.wqe_cnt) { 968 rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL); 969 if (ZERO_OR_NULL_PTR(rq_wrid)) { 970 ibdev_err(ibdev, "failed to alloc RQ wrid.\n"); 971 ret = -ENOMEM; 972 goto err_sq; 973 } 974 } 975 976 hr_qp->sq.wrid = sq_wrid; 977 hr_qp->rq.wrid = rq_wrid; 978 return 0; 979 err_sq: 980 kfree(sq_wrid); 981 982 return ret; 983 } 984 985 static void free_kernel_wrid(struct hns_roce_qp *hr_qp) 986 { 987 kfree(hr_qp->rq.wrid); 988 kfree(hr_qp->sq.wrid); 989 } 990 991 static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 992 struct ib_qp_init_attr *init_attr, 993 struct ib_udata *udata, 994 struct hns_roce_ib_create_qp *ucmd) 995 { 996 struct ib_device *ibdev = &hr_dev->ib_dev; 997 struct hns_roce_ucontext *uctx; 998 int ret; 999 1000 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1001 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR; 1002 else 1003 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR; 1004 1005 ret = set_rq_size(hr_dev, &init_attr->cap, hr_qp, 1006 hns_roce_qp_has_rq(init_attr), !!udata); 1007 if (ret) { 1008 ibdev_err(ibdev, "failed to set user RQ size, ret = %d.\n", 1009 ret); 1010 return ret; 1011 } 1012 1013 if (udata) { 1014 ret = ib_copy_from_udata(ucmd, udata, 1015 min(udata->inlen, sizeof(*ucmd))); 1016 if (ret) { 1017 ibdev_err(ibdev, 1018 "failed to copy QP ucmd, ret = %d\n", ret); 1019 return ret; 1020 } 1021 1022 uctx = rdma_udata_to_drv_context(udata, struct hns_roce_ucontext, 1023 ibucontext); 1024 hr_qp->config = uctx->config; 1025 ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd); 1026 if (ret) 1027 ibdev_err(ibdev, 1028 "failed to set user SQ size, ret = %d.\n", 1029 ret); 1030 } else { 1031 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 1032 hr_qp->config = HNS_ROCE_EXSGE_FLAGS; 1033 ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp); 1034 if (ret) 1035 ibdev_err(ibdev, 1036 "failed to set kernel SQ size, ret = %d.\n", 1037 ret); 1038 } 1039 1040 return ret; 1041 } 1042 1043 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, 1044 struct ib_pd *ib_pd, 1045 struct ib_qp_init_attr *init_attr, 1046 struct ib_udata *udata, 1047 struct hns_roce_qp *hr_qp) 1048 { 1049 struct hns_roce_ib_create_qp_resp resp = {}; 1050 struct ib_device *ibdev = &hr_dev->ib_dev; 1051 struct hns_roce_ib_create_qp ucmd; 1052 int ret; 1053 1054 mutex_init(&hr_qp->mutex); 1055 spin_lock_init(&hr_qp->sq.lock); 1056 spin_lock_init(&hr_qp->rq.lock); 1057 1058 hr_qp->state = IB_QPS_RESET; 1059 hr_qp->flush_flag = 0; 1060 1061 if (init_attr->create_flags) 1062 return -EOPNOTSUPP; 1063 1064 ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd); 1065 if (ret) { 1066 ibdev_err(ibdev, "failed to set QP param, ret = %d.\n", ret); 1067 return ret; 1068 } 1069 1070 if (!udata) { 1071 ret = alloc_kernel_wrid(hr_dev, hr_qp); 1072 if (ret) { 1073 ibdev_err(ibdev, "failed to alloc wrid, ret = %d.\n", 1074 ret); 1075 return ret; 1076 } 1077 } 1078 1079 ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr); 1080 if (ret) { 1081 ibdev_err(ibdev, "failed to alloc QP buffer, ret = %d.\n", ret); 1082 goto err_buf; 1083 } 1084 1085 ret = alloc_qpn(hr_dev, hr_qp); 1086 if (ret) { 1087 ibdev_err(ibdev, "failed to alloc QPN, ret = %d.\n", ret); 1088 goto err_qpn; 1089 } 1090 1091 ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp); 1092 if (ret) { 1093 ibdev_err(ibdev, "failed to alloc QP doorbell, ret = %d.\n", 1094 ret); 1095 goto err_db; 1096 } 1097 1098 ret = alloc_qpc(hr_dev, hr_qp); 1099 if (ret) { 1100 ibdev_err(ibdev, "failed to alloc QP context, ret = %d.\n", 1101 ret); 1102 goto err_qpc; 1103 } 1104 1105 ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr); 1106 if (ret) { 1107 ibdev_err(ibdev, "failed to store QP, ret = %d.\n", ret); 1108 goto err_store; 1109 } 1110 1111 if (udata) { 1112 resp.cap_flags = hr_qp->en_flags; 1113 ret = ib_copy_to_udata(udata, &resp, 1114 min(udata->outlen, sizeof(resp))); 1115 if (ret) { 1116 ibdev_err(ibdev, "copy qp resp failed!\n"); 1117 goto err_store; 1118 } 1119 } 1120 1121 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 1122 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); 1123 if (ret) 1124 goto err_flow_ctrl; 1125 } 1126 1127 hr_qp->ibqp.qp_num = hr_qp->qpn; 1128 hr_qp->event = hns_roce_ib_qp_event; 1129 refcount_set(&hr_qp->refcount, 1); 1130 init_completion(&hr_qp->free); 1131 1132 return 0; 1133 1134 err_flow_ctrl: 1135 hns_roce_qp_remove(hr_dev, hr_qp); 1136 err_store: 1137 free_qpc(hr_dev, hr_qp); 1138 err_qpc: 1139 free_qp_db(hr_dev, hr_qp, udata); 1140 err_db: 1141 free_qpn(hr_dev, hr_qp); 1142 err_qpn: 1143 free_qp_buf(hr_dev, hr_qp); 1144 err_buf: 1145 free_kernel_wrid(hr_qp); 1146 return ret; 1147 } 1148 1149 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1150 struct ib_udata *udata) 1151 { 1152 if (refcount_dec_and_test(&hr_qp->refcount)) 1153 complete(&hr_qp->free); 1154 wait_for_completion(&hr_qp->free); 1155 1156 free_qpc(hr_dev, hr_qp); 1157 free_qpn(hr_dev, hr_qp); 1158 free_qp_buf(hr_dev, hr_qp); 1159 free_kernel_wrid(hr_qp); 1160 free_qp_db(hr_dev, hr_qp, udata); 1161 } 1162 1163 static int check_qp_type(struct hns_roce_dev *hr_dev, enum ib_qp_type type, 1164 bool is_user) 1165 { 1166 switch (type) { 1167 case IB_QPT_XRC_INI: 1168 case IB_QPT_XRC_TGT: 1169 if (!(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)) 1170 goto out; 1171 break; 1172 case IB_QPT_UD: 1173 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 && 1174 is_user) 1175 goto out; 1176 break; 1177 case IB_QPT_RC: 1178 case IB_QPT_GSI: 1179 break; 1180 default: 1181 goto out; 1182 } 1183 1184 return 0; 1185 1186 out: 1187 ibdev_err(&hr_dev->ib_dev, "not support QP type %d\n", type); 1188 1189 return -EOPNOTSUPP; 1190 } 1191 1192 int hns_roce_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1193 struct ib_udata *udata) 1194 { 1195 struct ib_device *ibdev = qp->device; 1196 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 1197 struct hns_roce_qp *hr_qp = to_hr_qp(qp); 1198 struct ib_pd *pd = qp->pd; 1199 int ret; 1200 1201 ret = check_qp_type(hr_dev, init_attr->qp_type, !!udata); 1202 if (ret) 1203 return ret; 1204 1205 if (init_attr->qp_type == IB_QPT_XRC_TGT) 1206 hr_qp->xrcdn = to_hr_xrcd(init_attr->xrcd)->xrcdn; 1207 1208 if (init_attr->qp_type == IB_QPT_GSI) { 1209 hr_qp->port = init_attr->port_num - 1; 1210 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 1211 } 1212 1213 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, hr_qp); 1214 if (ret) 1215 ibdev_err(ibdev, "create QP type 0x%x failed(%d)\n", 1216 init_attr->qp_type, ret); 1217 1218 return ret; 1219 } 1220 1221 int to_hr_qp_type(int qp_type) 1222 { 1223 switch (qp_type) { 1224 case IB_QPT_RC: 1225 return SERV_TYPE_RC; 1226 case IB_QPT_UD: 1227 case IB_QPT_GSI: 1228 return SERV_TYPE_UD; 1229 case IB_QPT_XRC_INI: 1230 case IB_QPT_XRC_TGT: 1231 return SERV_TYPE_XRC; 1232 default: 1233 return -1; 1234 } 1235 } 1236 1237 static int check_mtu_validate(struct hns_roce_dev *hr_dev, 1238 struct hns_roce_qp *hr_qp, 1239 struct ib_qp_attr *attr, int attr_mask) 1240 { 1241 enum ib_mtu active_mtu; 1242 int p; 1243 1244 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1245 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 1246 1247 if ((hr_dev->caps.max_mtu >= IB_MTU_2048 && 1248 attr->path_mtu > hr_dev->caps.max_mtu) || 1249 attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) { 1250 ibdev_err(&hr_dev->ib_dev, 1251 "attr path_mtu(%d)invalid while modify qp", 1252 attr->path_mtu); 1253 return -EINVAL; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1260 int attr_mask) 1261 { 1262 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1263 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1264 int p; 1265 1266 if ((attr_mask & IB_QP_PORT) && 1267 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { 1268 ibdev_err(&hr_dev->ib_dev, "invalid attr, port_num = %u.\n", 1269 attr->port_num); 1270 return -EINVAL; 1271 } 1272 1273 if (attr_mask & IB_QP_PKEY_INDEX) { 1274 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1275 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { 1276 ibdev_err(&hr_dev->ib_dev, 1277 "invalid attr, pkey_index = %u.\n", 1278 attr->pkey_index); 1279 return -EINVAL; 1280 } 1281 } 1282 1283 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1284 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { 1285 ibdev_err(&hr_dev->ib_dev, 1286 "invalid attr, max_rd_atomic = %u.\n", 1287 attr->max_rd_atomic); 1288 return -EINVAL; 1289 } 1290 1291 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1292 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { 1293 ibdev_err(&hr_dev->ib_dev, 1294 "invalid attr, max_dest_rd_atomic = %u.\n", 1295 attr->max_dest_rd_atomic); 1296 return -EINVAL; 1297 } 1298 1299 if (attr_mask & IB_QP_PATH_MTU) 1300 return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask); 1301 1302 return 0; 1303 } 1304 1305 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1306 int attr_mask, struct ib_udata *udata) 1307 { 1308 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1309 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1310 enum ib_qp_state cur_state, new_state; 1311 int ret = -EINVAL; 1312 1313 mutex_lock(&hr_qp->mutex); 1314 1315 if (attr_mask & IB_QP_CUR_STATE && attr->cur_qp_state != hr_qp->state) 1316 goto out; 1317 1318 cur_state = hr_qp->state; 1319 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1320 1321 if (ibqp->uobject && 1322 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) { 1323 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) { 1324 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); 1325 1326 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 1327 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); 1328 } else { 1329 ibdev_warn(&hr_dev->ib_dev, 1330 "flush cqe is not supported in userspace!\n"); 1331 goto out; 1332 } 1333 } 1334 1335 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 1336 attr_mask)) { 1337 ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n"); 1338 goto out; 1339 } 1340 1341 ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask); 1342 if (ret) 1343 goto out; 1344 1345 if (cur_state == new_state && cur_state == IB_QPS_RESET) 1346 goto out; 1347 1348 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, 1349 new_state, udata); 1350 1351 out: 1352 mutex_unlock(&hr_qp->mutex); 1353 1354 return ret; 1355 } 1356 1357 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) 1358 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1359 { 1360 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1361 __acquire(&send_cq->lock); 1362 __acquire(&recv_cq->lock); 1363 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1364 spin_lock_irq(&send_cq->lock); 1365 __acquire(&recv_cq->lock); 1366 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1367 spin_lock_irq(&recv_cq->lock); 1368 __acquire(&send_cq->lock); 1369 } else if (send_cq == recv_cq) { 1370 spin_lock_irq(&send_cq->lock); 1371 __acquire(&recv_cq->lock); 1372 } else if (send_cq->cqn < recv_cq->cqn) { 1373 spin_lock_irq(&send_cq->lock); 1374 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1375 } else { 1376 spin_lock_irq(&recv_cq->lock); 1377 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1378 } 1379 } 1380 1381 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1382 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 1383 __releases(&recv_cq->lock) 1384 { 1385 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1386 __release(&recv_cq->lock); 1387 __release(&send_cq->lock); 1388 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1389 __release(&recv_cq->lock); 1390 spin_unlock(&send_cq->lock); 1391 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1392 __release(&send_cq->lock); 1393 spin_unlock(&recv_cq->lock); 1394 } else if (send_cq == recv_cq) { 1395 __release(&recv_cq->lock); 1396 spin_unlock_irq(&send_cq->lock); 1397 } else if (send_cq->cqn < recv_cq->cqn) { 1398 spin_unlock(&recv_cq->lock); 1399 spin_unlock_irq(&send_cq->lock); 1400 } else { 1401 spin_unlock(&send_cq->lock); 1402 spin_unlock_irq(&recv_cq->lock); 1403 } 1404 } 1405 1406 static inline void *get_wqe(struct hns_roce_qp *hr_qp, u32 offset) 1407 { 1408 return hns_roce_buf_offset(hr_qp->mtr.kmem, offset); 1409 } 1410 1411 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n) 1412 { 1413 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 1414 } 1415 1416 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n) 1417 { 1418 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 1419 } 1420 1421 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n) 1422 { 1423 return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift)); 1424 } 1425 1426 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1427 struct ib_cq *ib_cq) 1428 { 1429 struct hns_roce_cq *hr_cq; 1430 u32 cur; 1431 1432 cur = hr_wq->head - hr_wq->tail; 1433 if (likely(cur + nreq < hr_wq->wqe_cnt)) 1434 return false; 1435 1436 hr_cq = to_hr_cq(ib_cq); 1437 spin_lock(&hr_cq->lock); 1438 cur = hr_wq->head - hr_wq->tail; 1439 spin_unlock(&hr_cq->lock); 1440 1441 return cur + nreq >= hr_wq->wqe_cnt; 1442 } 1443 1444 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 1445 { 1446 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 1447 unsigned int reserved_from_bot; 1448 unsigned int i; 1449 1450 qp_table->idx_table.spare_idx = kcalloc(hr_dev->caps.num_qps, 1451 sizeof(u32), GFP_KERNEL); 1452 if (!qp_table->idx_table.spare_idx) 1453 return -ENOMEM; 1454 1455 mutex_init(&qp_table->scc_mutex); 1456 mutex_init(&qp_table->bank_mutex); 1457 xa_init(&hr_dev->qp_table_xa); 1458 1459 reserved_from_bot = hr_dev->caps.reserved_qps; 1460 1461 for (i = 0; i < reserved_from_bot; i++) { 1462 hr_dev->qp_table.bank[get_qp_bankid(i)].inuse++; 1463 hr_dev->qp_table.bank[get_qp_bankid(i)].min++; 1464 } 1465 1466 for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) { 1467 ida_init(&hr_dev->qp_table.bank[i].ida); 1468 hr_dev->qp_table.bank[i].max = hr_dev->caps.num_qps / 1469 HNS_ROCE_QP_BANK_NUM - 1; 1470 hr_dev->qp_table.bank[i].next = hr_dev->qp_table.bank[i].min; 1471 } 1472 1473 return 0; 1474 } 1475 1476 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) 1477 { 1478 int i; 1479 1480 for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++) 1481 ida_destroy(&hr_dev->qp_table.bank[i].ida); 1482 kfree(hr_dev->qp_table.idx_table.spare_idx); 1483 } 1484