1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/pci.h> 35 #include <linux/platform_device.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_umem.h> 38 #include <rdma/uverbs_ioctl.h> 39 #include "hns_roce_common.h" 40 #include "hns_roce_device.h" 41 #include "hns_roce_hem.h" 42 #include <rdma/hns-abi.h> 43 44 static void flush_work_handle(struct work_struct *work) 45 { 46 struct hns_roce_work *flush_work = container_of(work, 47 struct hns_roce_work, work); 48 struct hns_roce_qp *hr_qp = container_of(flush_work, 49 struct hns_roce_qp, flush_work); 50 struct device *dev = flush_work->hr_dev->dev; 51 struct ib_qp_attr attr; 52 int attr_mask; 53 int ret; 54 55 attr_mask = IB_QP_STATE; 56 attr.qp_state = IB_QPS_ERR; 57 58 if (test_and_clear_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag)) { 59 ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL); 60 if (ret) 61 dev_err(dev, "Modify QP to error state failed(%d) during CQE flush\n", 62 ret); 63 } 64 65 /* 66 * make sure we signal QP destroy leg that flush QP was completed 67 * so that it can safely proceed ahead now and destroy QP 68 */ 69 if (atomic_dec_and_test(&hr_qp->refcount)) 70 complete(&hr_qp->free); 71 } 72 73 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 74 { 75 struct hns_roce_work *flush_work = &hr_qp->flush_work; 76 77 flush_work->hr_dev = hr_dev; 78 INIT_WORK(&flush_work->work, flush_work_handle); 79 atomic_inc(&hr_qp->refcount); 80 queue_work(hr_dev->irq_workq, &flush_work->work); 81 } 82 83 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) 84 { 85 struct device *dev = hr_dev->dev; 86 struct hns_roce_qp *qp; 87 88 xa_lock(&hr_dev->qp_table_xa); 89 qp = __hns_roce_qp_lookup(hr_dev, qpn); 90 if (qp) 91 atomic_inc(&qp->refcount); 92 xa_unlock(&hr_dev->qp_table_xa); 93 94 if (!qp) { 95 dev_warn(dev, "Async event for bogus QP %08x\n", qpn); 96 return; 97 } 98 99 if (hr_dev->hw_rev != HNS_ROCE_HW_VER1 && 100 (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR || 101 event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR || 102 event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)) { 103 qp->state = IB_QPS_ERR; 104 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 105 init_flush_work(hr_dev, qp); 106 } 107 108 qp->event(qp, (enum hns_roce_event)event_type); 109 110 if (atomic_dec_and_test(&qp->refcount)) 111 complete(&qp->free); 112 } 113 114 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, 115 enum hns_roce_event type) 116 { 117 struct ib_event event; 118 struct ib_qp *ibqp = &hr_qp->ibqp; 119 120 if (ibqp->event_handler) { 121 event.device = ibqp->device; 122 event.element.qp = ibqp; 123 switch (type) { 124 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 125 event.event = IB_EVENT_PATH_MIG; 126 break; 127 case HNS_ROCE_EVENT_TYPE_COMM_EST: 128 event.event = IB_EVENT_COMM_EST; 129 break; 130 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 131 event.event = IB_EVENT_SQ_DRAINED; 132 break; 133 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 134 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 135 break; 136 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 137 event.event = IB_EVENT_QP_FATAL; 138 break; 139 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 140 event.event = IB_EVENT_PATH_MIG_ERR; 141 break; 142 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 143 event.event = IB_EVENT_QP_REQ_ERR; 144 break; 145 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 146 event.event = IB_EVENT_QP_ACCESS_ERR; 147 break; 148 default: 149 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n", 150 type, hr_qp->qpn); 151 return; 152 } 153 ibqp->event_handler(&event, ibqp->qp_context); 154 } 155 } 156 157 static int alloc_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 158 { 159 unsigned long num = 0; 160 int ret; 161 162 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) { 163 /* when hw version is v1, the sqpn is allocated */ 164 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) 165 num = HNS_ROCE_MAX_PORTS + 166 hr_dev->iboe.phy_port[hr_qp->port]; 167 else 168 num = 1; 169 170 hr_qp->doorbell_qpn = 1; 171 } else { 172 ret = hns_roce_bitmap_alloc_range(&hr_dev->qp_table.bitmap, 173 1, 1, &num); 174 if (ret) { 175 ibdev_err(&hr_dev->ib_dev, "Failed to alloc bitmap\n"); 176 return -ENOMEM; 177 } 178 179 hr_qp->doorbell_qpn = (u32)num; 180 } 181 182 hr_qp->qpn = num; 183 184 return 0; 185 } 186 187 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state) 188 { 189 switch (state) { 190 case IB_QPS_RESET: 191 return HNS_ROCE_QP_STATE_RST; 192 case IB_QPS_INIT: 193 return HNS_ROCE_QP_STATE_INIT; 194 case IB_QPS_RTR: 195 return HNS_ROCE_QP_STATE_RTR; 196 case IB_QPS_RTS: 197 return HNS_ROCE_QP_STATE_RTS; 198 case IB_QPS_SQD: 199 return HNS_ROCE_QP_STATE_SQD; 200 case IB_QPS_ERR: 201 return HNS_ROCE_QP_STATE_ERR; 202 default: 203 return HNS_ROCE_QP_NUM_STATE; 204 } 205 } 206 207 static void add_qp_to_list(struct hns_roce_dev *hr_dev, 208 struct hns_roce_qp *hr_qp, 209 struct ib_cq *send_cq, struct ib_cq *recv_cq) 210 { 211 struct hns_roce_cq *hr_send_cq, *hr_recv_cq; 212 unsigned long flags; 213 214 hr_send_cq = send_cq ? to_hr_cq(send_cq) : NULL; 215 hr_recv_cq = recv_cq ? to_hr_cq(recv_cq) : NULL; 216 217 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 218 hns_roce_lock_cqs(hr_send_cq, hr_recv_cq); 219 220 list_add_tail(&hr_qp->node, &hr_dev->qp_list); 221 if (hr_send_cq) 222 list_add_tail(&hr_qp->sq_node, &hr_send_cq->sq_list); 223 if (hr_recv_cq) 224 list_add_tail(&hr_qp->rq_node, &hr_recv_cq->rq_list); 225 226 hns_roce_unlock_cqs(hr_send_cq, hr_recv_cq); 227 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 228 } 229 230 static int hns_roce_qp_store(struct hns_roce_dev *hr_dev, 231 struct hns_roce_qp *hr_qp, 232 struct ib_qp_init_attr *init_attr) 233 { 234 struct xarray *xa = &hr_dev->qp_table_xa; 235 int ret; 236 237 if (!hr_qp->qpn) 238 return -EINVAL; 239 240 ret = xa_err(xa_store_irq(xa, hr_qp->qpn, hr_qp, GFP_KERNEL)); 241 if (ret) 242 dev_err(hr_dev->dev, "Failed to xa store for QPC\n"); 243 else 244 /* add QP to device's QP list for softwc */ 245 add_qp_to_list(hr_dev, hr_qp, init_attr->send_cq, 246 init_attr->recv_cq); 247 248 return ret; 249 } 250 251 static int alloc_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 252 { 253 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 254 struct device *dev = hr_dev->dev; 255 int ret; 256 257 if (!hr_qp->qpn) 258 return -EINVAL; 259 260 /* In v1 engine, GSI QP context is saved in the RoCE hw's register */ 261 if (hr_qp->ibqp.qp_type == IB_QPT_GSI && 262 hr_dev->hw_rev == HNS_ROCE_HW_VER1) 263 return 0; 264 265 /* Alloc memory for QPC */ 266 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn); 267 if (ret) { 268 dev_err(dev, "Failed to get QPC table\n"); 269 goto err_out; 270 } 271 272 /* Alloc memory for IRRL */ 273 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 274 if (ret) { 275 dev_err(dev, "Failed to get IRRL table\n"); 276 goto err_put_qp; 277 } 278 279 if (hr_dev->caps.trrl_entry_sz) { 280 /* Alloc memory for TRRL */ 281 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table, 282 hr_qp->qpn); 283 if (ret) { 284 dev_err(dev, "Failed to get TRRL table\n"); 285 goto err_put_irrl; 286 } 287 } 288 289 if (hr_dev->caps.sccc_sz) { 290 /* Alloc memory for SCC CTX */ 291 ret = hns_roce_table_get(hr_dev, &qp_table->sccc_table, 292 hr_qp->qpn); 293 if (ret) { 294 dev_err(dev, "Failed to get SCC CTX table\n"); 295 goto err_put_trrl; 296 } 297 } 298 299 return 0; 300 301 err_put_trrl: 302 if (hr_dev->caps.trrl_entry_sz) 303 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 304 305 err_put_irrl: 306 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 307 308 err_put_qp: 309 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn); 310 311 err_out: 312 return ret; 313 } 314 315 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 316 { 317 struct xarray *xa = &hr_dev->qp_table_xa; 318 unsigned long flags; 319 320 list_del(&hr_qp->node); 321 list_del(&hr_qp->sq_node); 322 list_del(&hr_qp->rq_node); 323 324 xa_lock_irqsave(xa, flags); 325 __xa_erase(xa, hr_qp->qpn & (hr_dev->caps.num_qps - 1)); 326 xa_unlock_irqrestore(xa, flags); 327 } 328 329 static void free_qpc(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 330 { 331 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 332 333 /* In v1 engine, GSI QP context is saved in the RoCE hw's register */ 334 if (hr_qp->ibqp.qp_type == IB_QPT_GSI && 335 hr_dev->hw_rev == HNS_ROCE_HW_VER1) 336 return; 337 338 if (hr_dev->caps.trrl_entry_sz) 339 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn); 340 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn); 341 } 342 343 static void free_qpn(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 344 { 345 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 346 347 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 348 return; 349 350 if (hr_qp->qpn < hr_dev->caps.reserved_qps) 351 return; 352 353 hns_roce_bitmap_free_range(&qp_table->bitmap, hr_qp->qpn, 1, BITMAP_RR); 354 } 355 356 static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, 357 struct hns_roce_qp *hr_qp, int has_rq) 358 { 359 u32 cnt; 360 361 /* If srq exist, set zero for relative number of rq */ 362 if (!has_rq) { 363 hr_qp->rq.wqe_cnt = 0; 364 hr_qp->rq.max_gs = 0; 365 hr_qp->rq_inl_buf.wqe_cnt = 0; 366 cap->max_recv_wr = 0; 367 cap->max_recv_sge = 0; 368 369 return 0; 370 } 371 372 /* Check the validity of QP support capacity */ 373 if (!cap->max_recv_wr || cap->max_recv_wr > hr_dev->caps.max_wqes || 374 cap->max_recv_sge > hr_dev->caps.max_rq_sg) { 375 ibdev_err(&hr_dev->ib_dev, "RQ config error, depth=%u, sge=%d\n", 376 cap->max_recv_wr, cap->max_recv_sge); 377 return -EINVAL; 378 } 379 380 cnt = roundup_pow_of_two(max(cap->max_recv_wr, hr_dev->caps.min_wqes)); 381 if (cnt > hr_dev->caps.max_wqes) { 382 ibdev_err(&hr_dev->ib_dev, "rq depth %u too large\n", 383 cap->max_recv_wr); 384 return -EINVAL; 385 } 386 387 hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 388 389 if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE) 390 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz); 391 else 392 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz * 393 hr_qp->rq.max_gs); 394 395 hr_qp->rq.wqe_cnt = cnt; 396 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) 397 hr_qp->rq_inl_buf.wqe_cnt = cnt; 398 else 399 hr_qp->rq_inl_buf.wqe_cnt = 0; 400 401 cap->max_recv_wr = cnt; 402 cap->max_recv_sge = hr_qp->rq.max_gs; 403 404 return 0; 405 } 406 407 static int set_extend_sge_param(struct hns_roce_dev *hr_dev, u32 sq_wqe_cnt, 408 struct hns_roce_qp *hr_qp, 409 struct ib_qp_cap *cap) 410 { 411 u32 cnt; 412 413 cnt = max(1U, cap->max_send_sge); 414 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) { 415 hr_qp->sq.max_gs = roundup_pow_of_two(cnt); 416 hr_qp->sge.sge_cnt = 0; 417 418 return 0; 419 } 420 421 hr_qp->sq.max_gs = cnt; 422 423 /* UD sqwqe's sge use extend sge */ 424 if (hr_qp->ibqp.qp_type == IB_QPT_GSI || 425 hr_qp->ibqp.qp_type == IB_QPT_UD) { 426 cnt = roundup_pow_of_two(sq_wqe_cnt * hr_qp->sq.max_gs); 427 } else if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) { 428 cnt = roundup_pow_of_two(sq_wqe_cnt * 429 (hr_qp->sq.max_gs - HNS_ROCE_SGE_IN_WQE)); 430 } else { 431 cnt = 0; 432 } 433 434 hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT; 435 hr_qp->sge.sge_cnt = cnt; 436 437 return 0; 438 } 439 440 static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev, 441 struct ib_qp_cap *cap, 442 struct hns_roce_ib_create_qp *ucmd) 443 { 444 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz); 445 u8 max_sq_stride = ilog2(roundup_sq_stride); 446 447 /* Sanity check SQ size before proceeding */ 448 if (ucmd->log_sq_stride > max_sq_stride || 449 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) { 450 ibdev_err(&hr_dev->ib_dev, "Failed to check SQ stride size\n"); 451 return -EINVAL; 452 } 453 454 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) { 455 ibdev_err(&hr_dev->ib_dev, "Failed to check SQ SGE size %d\n", 456 cap->max_send_sge); 457 return -EINVAL; 458 } 459 460 return 0; 461 } 462 463 static int set_user_sq_size(struct hns_roce_dev *hr_dev, 464 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp, 465 struct hns_roce_ib_create_qp *ucmd) 466 { 467 struct ib_device *ibdev = &hr_dev->ib_dev; 468 u32 cnt = 0; 469 int ret; 470 471 if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || 472 cnt > hr_dev->caps.max_wqes) 473 return -EINVAL; 474 475 ret = check_sq_size_with_integrity(hr_dev, cap, ucmd); 476 if (ret) { 477 ibdev_err(ibdev, "failed to check user SQ size, ret = %d.\n", 478 ret); 479 return ret; 480 } 481 482 ret = set_extend_sge_param(hr_dev, cnt, hr_qp, cap); 483 if (ret) 484 return ret; 485 486 hr_qp->sq.wqe_shift = ucmd->log_sq_stride; 487 hr_qp->sq.wqe_cnt = cnt; 488 489 return 0; 490 } 491 492 static int set_wqe_buf_attr(struct hns_roce_dev *hr_dev, 493 struct hns_roce_qp *hr_qp, 494 struct hns_roce_buf_attr *buf_attr) 495 { 496 int buf_size; 497 int idx = 0; 498 499 hr_qp->buff_size = 0; 500 501 /* SQ WQE */ 502 hr_qp->sq.offset = 0; 503 buf_size = to_hr_hem_entries_size(hr_qp->sq.wqe_cnt, 504 hr_qp->sq.wqe_shift); 505 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 506 buf_attr->region[idx].size = buf_size; 507 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sq_hop_num; 508 idx++; 509 hr_qp->buff_size += buf_size; 510 } 511 512 /* extend SGE WQE in SQ */ 513 hr_qp->sge.offset = hr_qp->buff_size; 514 buf_size = to_hr_hem_entries_size(hr_qp->sge.sge_cnt, 515 hr_qp->sge.sge_shift); 516 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 517 buf_attr->region[idx].size = buf_size; 518 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_sge_hop_num; 519 idx++; 520 hr_qp->buff_size += buf_size; 521 } 522 523 /* RQ WQE */ 524 hr_qp->rq.offset = hr_qp->buff_size; 525 buf_size = to_hr_hem_entries_size(hr_qp->rq.wqe_cnt, 526 hr_qp->rq.wqe_shift); 527 if (buf_size > 0 && idx < ARRAY_SIZE(buf_attr->region)) { 528 buf_attr->region[idx].size = buf_size; 529 buf_attr->region[idx].hopnum = hr_dev->caps.wqe_rq_hop_num; 530 idx++; 531 hr_qp->buff_size += buf_size; 532 } 533 534 if (hr_qp->buff_size < 1) 535 return -EINVAL; 536 537 buf_attr->page_shift = HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz; 538 buf_attr->fixed_page = true; 539 buf_attr->region_count = idx; 540 541 return 0; 542 } 543 544 static int set_kernel_sq_size(struct hns_roce_dev *hr_dev, 545 struct ib_qp_cap *cap, struct hns_roce_qp *hr_qp) 546 { 547 struct ib_device *ibdev = &hr_dev->ib_dev; 548 u32 cnt; 549 int ret; 550 551 if (!cap->max_send_wr || cap->max_send_wr > hr_dev->caps.max_wqes || 552 cap->max_send_sge > hr_dev->caps.max_sq_sg) { 553 ibdev_err(ibdev, 554 "failed to check SQ WR or SGE num, ret = %d.\n", 555 -EINVAL); 556 return -EINVAL; 557 } 558 559 cnt = roundup_pow_of_two(max(cap->max_send_wr, hr_dev->caps.min_wqes)); 560 if (cnt > hr_dev->caps.max_wqes) { 561 ibdev_err(ibdev, "failed to check WQE num, WQE num = %d.\n", 562 cnt); 563 return -EINVAL; 564 } 565 566 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz); 567 hr_qp->sq.wqe_cnt = cnt; 568 569 ret = set_extend_sge_param(hr_dev, cnt, hr_qp, cap); 570 if (ret) 571 return ret; 572 573 /* sync the parameters of kernel QP to user's configuration */ 574 cap->max_send_wr = cnt; 575 cap->max_send_sge = hr_qp->sq.max_gs; 576 577 return 0; 578 } 579 580 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr) 581 { 582 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr) 583 return 0; 584 585 return 1; 586 } 587 588 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr) 589 { 590 if (attr->qp_type == IB_QPT_XRC_INI || 591 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 592 !attr->cap.max_recv_wr) 593 return 0; 594 595 return 1; 596 } 597 598 static int alloc_rq_inline_buf(struct hns_roce_qp *hr_qp, 599 struct ib_qp_init_attr *init_attr) 600 { 601 u32 max_recv_sge = init_attr->cap.max_recv_sge; 602 u32 wqe_cnt = hr_qp->rq_inl_buf.wqe_cnt; 603 struct hns_roce_rinl_wqe *wqe_list; 604 int i; 605 606 /* allocate recv inline buf */ 607 wqe_list = kcalloc(wqe_cnt, sizeof(struct hns_roce_rinl_wqe), 608 GFP_KERNEL); 609 610 if (!wqe_list) 611 goto err; 612 613 /* Allocate a continuous buffer for all inline sge we need */ 614 wqe_list[0].sg_list = kcalloc(wqe_cnt, (max_recv_sge * 615 sizeof(struct hns_roce_rinl_sge)), 616 GFP_KERNEL); 617 if (!wqe_list[0].sg_list) 618 goto err_wqe_list; 619 620 /* Assign buffers of sg_list to each inline wqe */ 621 for (i = 1; i < wqe_cnt; i++) 622 wqe_list[i].sg_list = &wqe_list[0].sg_list[i * max_recv_sge]; 623 624 hr_qp->rq_inl_buf.wqe_list = wqe_list; 625 626 return 0; 627 628 err_wqe_list: 629 kfree(wqe_list); 630 631 err: 632 return -ENOMEM; 633 } 634 635 static void free_rq_inline_buf(struct hns_roce_qp *hr_qp) 636 { 637 if (hr_qp->rq_inl_buf.wqe_list) 638 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 639 kfree(hr_qp->rq_inl_buf.wqe_list); 640 } 641 642 static int alloc_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 643 struct ib_qp_init_attr *init_attr, 644 struct ib_udata *udata, unsigned long addr) 645 { 646 struct ib_device *ibdev = &hr_dev->ib_dev; 647 struct hns_roce_buf_attr buf_attr = {}; 648 int ret; 649 650 if (!udata && hr_qp->rq_inl_buf.wqe_cnt) { 651 ret = alloc_rq_inline_buf(hr_qp, init_attr); 652 if (ret) { 653 ibdev_err(ibdev, 654 "failed to alloc inline buf, ret = %d.\n", 655 ret); 656 return ret; 657 } 658 } else { 659 hr_qp->rq_inl_buf.wqe_list = NULL; 660 } 661 662 ret = set_wqe_buf_attr(hr_dev, hr_qp, &buf_attr); 663 if (ret) { 664 ibdev_err(ibdev, "failed to split WQE buf, ret = %d.\n", ret); 665 goto err_inline; 666 } 667 ret = hns_roce_mtr_create(hr_dev, &hr_qp->mtr, &buf_attr, 668 HNS_HW_PAGE_SHIFT + hr_dev->caps.mtt_ba_pg_sz, 669 udata, addr); 670 if (ret) { 671 ibdev_err(ibdev, "failed to create WQE mtr, ret = %d.\n", ret); 672 goto err_inline; 673 } 674 675 return 0; 676 err_inline: 677 free_rq_inline_buf(hr_qp); 678 679 return ret; 680 } 681 682 static void free_qp_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) 683 { 684 hns_roce_mtr_destroy(hr_dev, &hr_qp->mtr); 685 free_rq_inline_buf(hr_qp); 686 } 687 688 static inline bool user_qp_has_sdb(struct hns_roce_dev *hr_dev, 689 struct ib_qp_init_attr *init_attr, 690 struct ib_udata *udata, 691 struct hns_roce_ib_create_qp_resp *resp, 692 struct hns_roce_ib_create_qp *ucmd) 693 { 694 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) && 695 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 696 hns_roce_qp_has_sq(init_attr) && 697 udata->inlen >= offsetofend(typeof(*ucmd), sdb_addr)); 698 } 699 700 static inline bool user_qp_has_rdb(struct hns_roce_dev *hr_dev, 701 struct ib_qp_init_attr *init_attr, 702 struct ib_udata *udata, 703 struct hns_roce_ib_create_qp_resp *resp) 704 { 705 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 706 udata->outlen >= offsetofend(typeof(*resp), cap_flags) && 707 hns_roce_qp_has_rq(init_attr)); 708 } 709 710 static inline bool kernel_qp_has_rdb(struct hns_roce_dev *hr_dev, 711 struct ib_qp_init_attr *init_attr) 712 { 713 return ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) && 714 hns_roce_qp_has_rq(init_attr)); 715 } 716 717 static int alloc_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 718 struct ib_qp_init_attr *init_attr, 719 struct ib_udata *udata, 720 struct hns_roce_ib_create_qp *ucmd, 721 struct hns_roce_ib_create_qp_resp *resp) 722 { 723 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( 724 udata, struct hns_roce_ucontext, ibucontext); 725 struct ib_device *ibdev = &hr_dev->ib_dev; 726 int ret; 727 728 if (udata) { 729 if (user_qp_has_sdb(hr_dev, init_attr, udata, resp, ucmd)) { 730 ret = hns_roce_db_map_user(uctx, udata, ucmd->sdb_addr, 731 &hr_qp->sdb); 732 if (ret) { 733 ibdev_err(ibdev, 734 "Failed to map user SQ doorbell\n"); 735 goto err_out; 736 } 737 hr_qp->en_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB; 738 resp->cap_flags |= HNS_ROCE_QP_CAP_SQ_RECORD_DB; 739 } 740 741 if (user_qp_has_rdb(hr_dev, init_attr, udata, resp)) { 742 ret = hns_roce_db_map_user(uctx, udata, ucmd->db_addr, 743 &hr_qp->rdb); 744 if (ret) { 745 ibdev_err(ibdev, 746 "Failed to map user RQ doorbell\n"); 747 goto err_sdb; 748 } 749 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 750 resp->cap_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 751 } 752 } else { 753 /* QP doorbell register address */ 754 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset + 755 DB_REG_OFFSET * hr_dev->priv_uar.index; 756 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset + 757 DB_REG_OFFSET * hr_dev->priv_uar.index; 758 759 if (kernel_qp_has_rdb(hr_dev, init_attr)) { 760 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0); 761 if (ret) { 762 ibdev_err(ibdev, 763 "Failed to alloc kernel RQ doorbell\n"); 764 goto err_out; 765 } 766 *hr_qp->rdb.db_record = 0; 767 hr_qp->en_flags |= HNS_ROCE_QP_CAP_RQ_RECORD_DB; 768 } 769 } 770 771 return 0; 772 err_sdb: 773 if (udata && hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 774 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 775 err_out: 776 return ret; 777 } 778 779 static void free_qp_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 780 struct ib_udata *udata) 781 { 782 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context( 783 udata, struct hns_roce_ucontext, ibucontext); 784 785 if (udata) { 786 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 787 hns_roce_db_unmap_user(uctx, &hr_qp->rdb); 788 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) 789 hns_roce_db_unmap_user(uctx, &hr_qp->sdb); 790 } else { 791 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 792 hns_roce_free_db(hr_dev, &hr_qp->rdb); 793 } 794 } 795 796 static int alloc_kernel_wrid(struct hns_roce_dev *hr_dev, 797 struct hns_roce_qp *hr_qp) 798 { 799 struct ib_device *ibdev = &hr_dev->ib_dev; 800 u64 *sq_wrid = NULL; 801 u64 *rq_wrid = NULL; 802 int ret; 803 804 sq_wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64), GFP_KERNEL); 805 if (ZERO_OR_NULL_PTR(sq_wrid)) { 806 ibdev_err(ibdev, "Failed to alloc SQ wrid\n"); 807 return -ENOMEM; 808 } 809 810 if (hr_qp->rq.wqe_cnt) { 811 rq_wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64), GFP_KERNEL); 812 if (ZERO_OR_NULL_PTR(rq_wrid)) { 813 ibdev_err(ibdev, "Failed to alloc RQ wrid\n"); 814 ret = -ENOMEM; 815 goto err_sq; 816 } 817 } 818 819 hr_qp->sq.wrid = sq_wrid; 820 hr_qp->rq.wrid = rq_wrid; 821 return 0; 822 err_sq: 823 kfree(sq_wrid); 824 825 return ret; 826 } 827 828 static void free_kernel_wrid(struct hns_roce_qp *hr_qp) 829 { 830 kfree(hr_qp->rq.wrid); 831 kfree(hr_qp->sq.wrid); 832 } 833 834 static int set_qp_param(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 835 struct ib_qp_init_attr *init_attr, 836 struct ib_udata *udata, 837 struct hns_roce_ib_create_qp *ucmd) 838 { 839 struct ib_device *ibdev = &hr_dev->ib_dev; 840 int ret; 841 842 hr_qp->ibqp.qp_type = init_attr->qp_type; 843 844 if (init_attr->cap.max_inline_data > hr_dev->caps.max_sq_inline) 845 init_attr->cap.max_inline_data = hr_dev->caps.max_sq_inline; 846 847 hr_qp->max_inline_data = init_attr->cap.max_inline_data; 848 849 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 850 hr_qp->sq_signal_bits = IB_SIGNAL_ALL_WR; 851 else 852 hr_qp->sq_signal_bits = IB_SIGNAL_REQ_WR; 853 854 ret = set_rq_size(hr_dev, &init_attr->cap, hr_qp, 855 hns_roce_qp_has_rq(init_attr)); 856 if (ret) { 857 ibdev_err(ibdev, "failed to set user RQ size, ret = %d.\n", 858 ret); 859 return ret; 860 } 861 862 if (udata) { 863 if (ib_copy_from_udata(ucmd, udata, sizeof(*ucmd))) { 864 ibdev_err(ibdev, "Failed to copy QP ucmd\n"); 865 return -EFAULT; 866 } 867 868 ret = set_user_sq_size(hr_dev, &init_attr->cap, hr_qp, ucmd); 869 if (ret) 870 ibdev_err(ibdev, "Failed to set user SQ size\n"); 871 } else { 872 if (init_attr->create_flags & 873 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 874 ibdev_err(ibdev, "Failed to check multicast loopback\n"); 875 return -EINVAL; 876 } 877 878 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) { 879 ibdev_err(ibdev, "Failed to check ipoib ud lso\n"); 880 return -EINVAL; 881 } 882 883 ret = set_kernel_sq_size(hr_dev, &init_attr->cap, hr_qp); 884 if (ret) 885 ibdev_err(ibdev, "Failed to set kernel SQ size\n"); 886 } 887 888 return ret; 889 } 890 891 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev, 892 struct ib_pd *ib_pd, 893 struct ib_qp_init_attr *init_attr, 894 struct ib_udata *udata, 895 struct hns_roce_qp *hr_qp) 896 { 897 struct hns_roce_ib_create_qp_resp resp = {}; 898 struct ib_device *ibdev = &hr_dev->ib_dev; 899 struct hns_roce_ib_create_qp ucmd; 900 int ret; 901 902 mutex_init(&hr_qp->mutex); 903 spin_lock_init(&hr_qp->sq.lock); 904 spin_lock_init(&hr_qp->rq.lock); 905 906 hr_qp->state = IB_QPS_RESET; 907 hr_qp->flush_flag = 0; 908 909 ret = set_qp_param(hr_dev, hr_qp, init_attr, udata, &ucmd); 910 if (ret) { 911 ibdev_err(ibdev, "Failed to set QP param\n"); 912 return ret; 913 } 914 915 if (!udata) { 916 ret = alloc_kernel_wrid(hr_dev, hr_qp); 917 if (ret) { 918 ibdev_err(ibdev, "Failed to alloc wrid\n"); 919 return ret; 920 } 921 } 922 923 ret = alloc_qp_db(hr_dev, hr_qp, init_attr, udata, &ucmd, &resp); 924 if (ret) { 925 ibdev_err(ibdev, "Failed to alloc QP doorbell\n"); 926 goto err_wrid; 927 } 928 929 ret = alloc_qp_buf(hr_dev, hr_qp, init_attr, udata, ucmd.buf_addr); 930 if (ret) { 931 ibdev_err(ibdev, "Failed to alloc QP buffer\n"); 932 goto err_db; 933 } 934 935 ret = alloc_qpn(hr_dev, hr_qp); 936 if (ret) { 937 ibdev_err(ibdev, "Failed to alloc QPN\n"); 938 goto err_buf; 939 } 940 941 ret = alloc_qpc(hr_dev, hr_qp); 942 if (ret) { 943 ibdev_err(ibdev, "Failed to alloc QP context\n"); 944 goto err_qpn; 945 } 946 947 ret = hns_roce_qp_store(hr_dev, hr_qp, init_attr); 948 if (ret) { 949 ibdev_err(ibdev, "Failed to store QP\n"); 950 goto err_qpc; 951 } 952 953 if (udata) { 954 ret = ib_copy_to_udata(udata, &resp, 955 min(udata->outlen, sizeof(resp))); 956 if (ret) { 957 ibdev_err(ibdev, "copy qp resp failed!\n"); 958 goto err_store; 959 } 960 } 961 962 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 963 ret = hr_dev->hw->qp_flow_control_init(hr_dev, hr_qp); 964 if (ret) 965 goto err_store; 966 } 967 968 hr_qp->ibqp.qp_num = hr_qp->qpn; 969 hr_qp->event = hns_roce_ib_qp_event; 970 atomic_set(&hr_qp->refcount, 1); 971 init_completion(&hr_qp->free); 972 973 return 0; 974 975 err_store: 976 hns_roce_qp_remove(hr_dev, hr_qp); 977 err_qpc: 978 free_qpc(hr_dev, hr_qp); 979 err_qpn: 980 free_qpn(hr_dev, hr_qp); 981 err_buf: 982 free_qp_buf(hr_dev, hr_qp); 983 err_db: 984 free_qp_db(hr_dev, hr_qp, udata); 985 err_wrid: 986 free_kernel_wrid(hr_qp); 987 return ret; 988 } 989 990 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 991 struct ib_udata *udata) 992 { 993 if (atomic_dec_and_test(&hr_qp->refcount)) 994 complete(&hr_qp->free); 995 wait_for_completion(&hr_qp->free); 996 997 free_qpc(hr_dev, hr_qp); 998 free_qpn(hr_dev, hr_qp); 999 free_qp_buf(hr_dev, hr_qp); 1000 free_kernel_wrid(hr_qp); 1001 free_qp_db(hr_dev, hr_qp, udata); 1002 1003 kfree(hr_qp); 1004 } 1005 1006 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd, 1007 struct ib_qp_init_attr *init_attr, 1008 struct ib_udata *udata) 1009 { 1010 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); 1011 struct ib_device *ibdev = &hr_dev->ib_dev; 1012 struct hns_roce_qp *hr_qp; 1013 int ret; 1014 1015 switch (init_attr->qp_type) { 1016 case IB_QPT_RC: 1017 case IB_QPT_GSI: 1018 break; 1019 default: 1020 ibdev_err(ibdev, "not support QP type %d\n", 1021 init_attr->qp_type); 1022 return ERR_PTR(-EOPNOTSUPP); 1023 } 1024 1025 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 1026 if (!hr_qp) 1027 return ERR_PTR(-ENOMEM); 1028 1029 if (init_attr->qp_type == IB_QPT_GSI) { 1030 hr_qp->port = init_attr->port_num - 1; 1031 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 1032 } 1033 1034 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, hr_qp); 1035 if (ret) { 1036 ibdev_err(ibdev, "Create QP type 0x%x failed(%d)\n", 1037 init_attr->qp_type, ret); 1038 ibdev_err(ibdev, "Create GSI QP failed!\n"); 1039 kfree(hr_qp); 1040 return ERR_PTR(ret); 1041 } 1042 return &hr_qp->ibqp; 1043 } 1044 1045 int to_hr_qp_type(int qp_type) 1046 { 1047 int transport_type; 1048 1049 if (qp_type == IB_QPT_RC) 1050 transport_type = SERV_TYPE_RC; 1051 else if (qp_type == IB_QPT_UC) 1052 transport_type = SERV_TYPE_UC; 1053 else if (qp_type == IB_QPT_UD) 1054 transport_type = SERV_TYPE_UD; 1055 else if (qp_type == IB_QPT_GSI) 1056 transport_type = SERV_TYPE_UD; 1057 else 1058 transport_type = -1; 1059 1060 return transport_type; 1061 } 1062 1063 static int check_mtu_validate(struct hns_roce_dev *hr_dev, 1064 struct hns_roce_qp *hr_qp, 1065 struct ib_qp_attr *attr, int attr_mask) 1066 { 1067 enum ib_mtu active_mtu; 1068 int p; 1069 1070 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1071 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu); 1072 1073 if ((hr_dev->caps.max_mtu >= IB_MTU_2048 && 1074 attr->path_mtu > hr_dev->caps.max_mtu) || 1075 attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) { 1076 ibdev_err(&hr_dev->ib_dev, 1077 "attr path_mtu(%d)invalid while modify qp", 1078 attr->path_mtu); 1079 return -EINVAL; 1080 } 1081 1082 return 0; 1083 } 1084 1085 static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1086 int attr_mask) 1087 { 1088 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1089 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1090 int p; 1091 1092 if ((attr_mask & IB_QP_PORT) && 1093 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) { 1094 ibdev_err(&hr_dev->ib_dev, 1095 "attr port_num invalid.attr->port_num=%d\n", 1096 attr->port_num); 1097 return -EINVAL; 1098 } 1099 1100 if (attr_mask & IB_QP_PKEY_INDEX) { 1101 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port; 1102 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) { 1103 ibdev_err(&hr_dev->ib_dev, 1104 "attr pkey_index invalid.attr->pkey_index=%d\n", 1105 attr->pkey_index); 1106 return -EINVAL; 1107 } 1108 } 1109 1110 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 1111 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) { 1112 ibdev_err(&hr_dev->ib_dev, 1113 "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n", 1114 attr->max_rd_atomic); 1115 return -EINVAL; 1116 } 1117 1118 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 1119 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) { 1120 ibdev_err(&hr_dev->ib_dev, 1121 "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n", 1122 attr->max_dest_rd_atomic); 1123 return -EINVAL; 1124 } 1125 1126 if (attr_mask & IB_QP_PATH_MTU) 1127 return check_mtu_validate(hr_dev, hr_qp, attr, attr_mask); 1128 1129 return 0; 1130 } 1131 1132 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1133 int attr_mask, struct ib_udata *udata) 1134 { 1135 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 1136 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 1137 enum ib_qp_state cur_state, new_state; 1138 int ret = -EINVAL; 1139 1140 mutex_lock(&hr_qp->mutex); 1141 1142 if (attr_mask & IB_QP_CUR_STATE && attr->cur_qp_state != hr_qp->state) 1143 goto out; 1144 1145 cur_state = hr_qp->state; 1146 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 1147 1148 if (ibqp->uobject && 1149 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) { 1150 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_SQ_RECORD_DB) { 1151 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr); 1152 1153 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 1154 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr); 1155 } else { 1156 ibdev_warn(&hr_dev->ib_dev, 1157 "flush cqe is not supported in userspace!\n"); 1158 goto out; 1159 } 1160 } 1161 1162 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 1163 attr_mask)) { 1164 ibdev_err(&hr_dev->ib_dev, "ib_modify_qp_is_ok failed\n"); 1165 goto out; 1166 } 1167 1168 ret = hns_roce_check_qp_attr(ibqp, attr, attr_mask); 1169 if (ret) 1170 goto out; 1171 1172 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 1173 if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) { 1174 ret = -EPERM; 1175 ibdev_err(&hr_dev->ib_dev, 1176 "RST2RST state is not supported\n"); 1177 } else { 1178 ret = 0; 1179 } 1180 1181 goto out; 1182 } 1183 1184 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state, 1185 new_state); 1186 1187 out: 1188 mutex_unlock(&hr_qp->mutex); 1189 1190 return ret; 1191 } 1192 1193 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq) 1194 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1195 { 1196 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1197 __acquire(&send_cq->lock); 1198 __acquire(&recv_cq->lock); 1199 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1200 spin_lock_irq(&send_cq->lock); 1201 __acquire(&recv_cq->lock); 1202 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1203 spin_lock_irq(&recv_cq->lock); 1204 __acquire(&send_cq->lock); 1205 } else if (send_cq == recv_cq) { 1206 spin_lock_irq(&send_cq->lock); 1207 __acquire(&recv_cq->lock); 1208 } else if (send_cq->cqn < recv_cq->cqn) { 1209 spin_lock_irq(&send_cq->lock); 1210 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 1211 } else { 1212 spin_lock_irq(&recv_cq->lock); 1213 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 1214 } 1215 } 1216 1217 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1218 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock) 1219 __releases(&recv_cq->lock) 1220 { 1221 if (unlikely(send_cq == NULL && recv_cq == NULL)) { 1222 __release(&recv_cq->lock); 1223 __release(&send_cq->lock); 1224 } else if (unlikely(send_cq != NULL && recv_cq == NULL)) { 1225 __release(&recv_cq->lock); 1226 spin_unlock(&send_cq->lock); 1227 } else if (unlikely(send_cq == NULL && recv_cq != NULL)) { 1228 __release(&send_cq->lock); 1229 spin_unlock(&recv_cq->lock); 1230 } else if (send_cq == recv_cq) { 1231 __release(&recv_cq->lock); 1232 spin_unlock_irq(&send_cq->lock); 1233 } else if (send_cq->cqn < recv_cq->cqn) { 1234 spin_unlock(&recv_cq->lock); 1235 spin_unlock_irq(&send_cq->lock); 1236 } else { 1237 spin_unlock(&send_cq->lock); 1238 spin_unlock_irq(&recv_cq->lock); 1239 } 1240 } 1241 1242 static inline void *get_wqe(struct hns_roce_qp *hr_qp, int offset) 1243 { 1244 return hns_roce_buf_offset(hr_qp->mtr.kmem, offset); 1245 } 1246 1247 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n) 1248 { 1249 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift)); 1250 } 1251 1252 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n) 1253 { 1254 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift)); 1255 } 1256 1257 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n) 1258 { 1259 return get_wqe(hr_qp, hr_qp->sge.offset + (n << hr_qp->sge.sge_shift)); 1260 } 1261 1262 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1263 struct ib_cq *ib_cq) 1264 { 1265 struct hns_roce_cq *hr_cq; 1266 u32 cur; 1267 1268 cur = hr_wq->head - hr_wq->tail; 1269 if (likely(cur + nreq < hr_wq->wqe_cnt)) 1270 return false; 1271 1272 hr_cq = to_hr_cq(ib_cq); 1273 spin_lock(&hr_cq->lock); 1274 cur = hr_wq->head - hr_wq->tail; 1275 spin_unlock(&hr_cq->lock); 1276 1277 return cur + nreq >= hr_wq->wqe_cnt; 1278 } 1279 1280 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev) 1281 { 1282 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table; 1283 int reserved_from_top = 0; 1284 int reserved_from_bot; 1285 int ret; 1286 1287 mutex_init(&qp_table->scc_mutex); 1288 xa_init(&hr_dev->qp_table_xa); 1289 1290 reserved_from_bot = hr_dev->caps.reserved_qps; 1291 1292 ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps, 1293 hr_dev->caps.num_qps - 1, reserved_from_bot, 1294 reserved_from_top); 1295 if (ret) { 1296 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n", 1297 ret); 1298 return ret; 1299 } 1300 1301 return 0; 1302 } 1303 1304 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev) 1305 { 1306 hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap); 1307 } 1308