1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 EXPORT_SYMBOL_GPL(hns_get_gid_index); 61 62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 63 { 64 u8 phy_port; 65 u32 i = 0; 66 67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM)) 68 return 0; 69 70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++) 71 hr_dev->dev_addr[port][i] = addr[i]; 72 73 phy_port = hr_dev->iboe.phy_port[port]; 74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 75 } 76 77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u8 port = attr->port_num - 1; 81 unsigned long flags; 82 int ret; 83 84 if (port >= hr_dev->caps.num_ports) 85 return -EINVAL; 86 87 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 88 89 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 90 91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 92 93 return ret; 94 } 95 96 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 97 { 98 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 99 struct ib_gid_attr zattr = { }; 100 u8 port = attr->port_num - 1; 101 unsigned long flags; 102 int ret; 103 104 if (port >= hr_dev->caps.num_ports) 105 return -EINVAL; 106 107 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 108 109 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 110 111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 112 113 return ret; 114 } 115 116 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 117 unsigned long event) 118 { 119 struct device *dev = hr_dev->dev; 120 struct net_device *netdev; 121 int ret = 0; 122 123 netdev = hr_dev->iboe.netdevs[port]; 124 if (!netdev) { 125 dev_err(dev, "port(%d) can't find netdev\n", port); 126 return -ENODEV; 127 } 128 129 switch (event) { 130 case NETDEV_UP: 131 case NETDEV_CHANGE: 132 case NETDEV_REGISTER: 133 case NETDEV_CHANGEADDR: 134 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 135 break; 136 case NETDEV_DOWN: 137 /* 138 * In v1 engine, only support all ports closed together. 139 */ 140 break; 141 default: 142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 143 break; 144 } 145 146 return ret; 147 } 148 149 static int hns_roce_netdev_event(struct notifier_block *self, 150 unsigned long event, void *ptr) 151 { 152 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 153 struct hns_roce_ib_iboe *iboe = NULL; 154 struct hns_roce_dev *hr_dev = NULL; 155 u8 port = 0; 156 int ret = 0; 157 158 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 159 iboe = &hr_dev->iboe; 160 161 for (port = 0; port < hr_dev->caps.num_ports; port++) { 162 if (dev == iboe->netdevs[port]) { 163 ret = handle_en_event(hr_dev, port, event); 164 if (ret) 165 return NOTIFY_DONE; 166 break; 167 } 168 } 169 170 return NOTIFY_DONE; 171 } 172 173 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 174 { 175 int ret; 176 u8 i; 177 178 for (i = 0; i < hr_dev->caps.num_ports; i++) { 179 if (hr_dev->hw->set_mtu) 180 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 181 hr_dev->caps.max_mtu); 182 ret = hns_roce_set_mac(hr_dev, i, 183 hr_dev->iboe.netdevs[i]->dev_addr); 184 if (ret) 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int hns_roce_query_device(struct ib_device *ib_dev, 192 struct ib_device_attr *props, 193 struct ib_udata *uhw) 194 { 195 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 196 197 memset(props, 0, sizeof(*props)); 198 199 props->fw_ver = hr_dev->caps.fw_ver; 200 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 201 props->max_mr_size = (u64)(~(0ULL)); 202 props->page_size_cap = hr_dev->caps.page_size_cap; 203 props->vendor_id = hr_dev->vendor_id; 204 props->vendor_part_id = hr_dev->vendor_part_id; 205 props->hw_ver = hr_dev->hw_rev; 206 props->max_qp = hr_dev->caps.num_qps; 207 props->max_qp_wr = hr_dev->caps.max_wqes; 208 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 209 IB_DEVICE_RC_RNR_NAK_GEN; 210 props->max_send_sge = hr_dev->caps.max_sq_sg; 211 props->max_recv_sge = hr_dev->caps.max_rq_sg; 212 props->max_sge_rd = 1; 213 props->max_cq = hr_dev->caps.num_cqs; 214 props->max_cqe = hr_dev->caps.max_cqes; 215 props->max_mr = hr_dev->caps.num_mtpts; 216 props->max_pd = hr_dev->caps.num_pds; 217 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 218 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 219 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 220 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 221 props->max_pkeys = 1; 222 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 223 224 return 0; 225 } 226 227 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev, 228 u8 port_num) 229 { 230 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 231 struct net_device *ndev; 232 233 if (port_num < 1 || port_num > hr_dev->caps.num_ports) 234 return NULL; 235 236 rcu_read_lock(); 237 238 ndev = hr_dev->iboe.netdevs[port_num - 1]; 239 if (ndev) 240 dev_hold(ndev); 241 242 rcu_read_unlock(); 243 return ndev; 244 } 245 246 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 247 struct ib_port_attr *props) 248 { 249 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 250 struct device *dev = hr_dev->dev; 251 struct net_device *net_dev; 252 unsigned long flags; 253 enum ib_mtu mtu; 254 u8 port; 255 256 assert(port_num > 0); 257 port = port_num - 1; 258 259 /* props being zeroed by the caller, avoid zeroing it here */ 260 261 props->max_mtu = hr_dev->caps.max_mtu; 262 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 263 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 264 IB_PORT_VENDOR_CLASS_SUP | 265 IB_PORT_BOOT_MGMT_SUP; 266 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 267 props->pkey_tbl_len = 1; 268 props->active_width = IB_WIDTH_4X; 269 props->active_speed = 1; 270 271 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 272 273 net_dev = hr_dev->iboe.netdevs[port]; 274 if (!net_dev) { 275 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 276 dev_err(dev, "find netdev %d failed!\r\n", port); 277 return -EINVAL; 278 } 279 280 mtu = iboe_get_mtu(net_dev->mtu); 281 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 282 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 283 IB_PORT_ACTIVE : IB_PORT_DOWN; 284 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3; 285 286 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 287 288 return 0; 289 } 290 291 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 292 u8 port_num) 293 { 294 return IB_LINK_LAYER_ETHERNET; 295 } 296 297 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 298 u16 *pkey) 299 { 300 *pkey = PKEY_ID; 301 302 return 0; 303 } 304 305 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 306 struct ib_device_modify *props) 307 { 308 unsigned long flags; 309 310 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 311 return -EOPNOTSUPP; 312 313 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 314 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 315 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 316 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 317 } 318 319 return 0; 320 } 321 322 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, 323 struct ib_port_modify *props) 324 { 325 return 0; 326 } 327 328 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev, 329 struct ib_udata *udata) 330 { 331 int ret = 0; 332 struct hns_roce_ucontext *context; 333 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 334 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 335 336 if (!hr_dev->active) 337 return ERR_PTR(-EAGAIN); 338 339 resp.qp_tab_size = hr_dev->caps.num_qps; 340 341 context = kmalloc(sizeof(*context), GFP_KERNEL); 342 if (!context) 343 return ERR_PTR(-ENOMEM); 344 345 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 346 if (ret) 347 goto error_fail_uar_alloc; 348 349 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 350 INIT_LIST_HEAD(&context->page_list); 351 mutex_init(&context->page_mutex); 352 } 353 354 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 355 if (ret) 356 goto error_fail_copy_to_udata; 357 358 return &context->ibucontext; 359 360 error_fail_copy_to_udata: 361 hns_roce_uar_free(hr_dev, &context->uar); 362 363 error_fail_uar_alloc: 364 kfree(context); 365 366 return ERR_PTR(ret); 367 } 368 369 static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 370 { 371 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 372 373 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 374 kfree(context); 375 376 return 0; 377 } 378 379 static int hns_roce_mmap(struct ib_ucontext *context, 380 struct vm_area_struct *vma) 381 { 382 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 383 384 switch (vma->vm_pgoff) { 385 case 0: 386 return rdma_user_mmap_io(context, vma, 387 to_hr_ucontext(context)->uar.pfn, 388 PAGE_SIZE, 389 pgprot_noncached(vma->vm_page_prot)); 390 391 /* vm_pgoff: 1 -- TPTR */ 392 case 1: 393 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 394 return -EINVAL; 395 /* 396 * FIXME: using io_remap_pfn_range on the dma address returned 397 * by dma_alloc_coherent is totally wrong. 398 */ 399 return rdma_user_mmap_io(context, vma, 400 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 401 hr_dev->tptr_size, 402 vma->vm_page_prot); 403 404 default: 405 return -EINVAL; 406 } 407 } 408 409 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 410 struct ib_port_immutable *immutable) 411 { 412 struct ib_port_attr attr; 413 int ret; 414 415 ret = ib_query_port(ib_dev, port_num, &attr); 416 if (ret) 417 return ret; 418 419 immutable->pkey_tbl_len = attr.pkey_tbl_len; 420 immutable->gid_tbl_len = attr.gid_tbl_len; 421 422 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 423 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 424 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 425 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 426 427 return 0; 428 } 429 430 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 431 { 432 } 433 434 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 435 { 436 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 437 438 hr_dev->active = false; 439 unregister_netdevice_notifier(&iboe->nb); 440 ib_unregister_device(&hr_dev->ib_dev); 441 } 442 443 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 444 { 445 int ret; 446 struct hns_roce_ib_iboe *iboe = NULL; 447 struct ib_device *ib_dev = NULL; 448 struct device *dev = hr_dev->dev; 449 450 iboe = &hr_dev->iboe; 451 spin_lock_init(&iboe->lock); 452 453 ib_dev = &hr_dev->ib_dev; 454 455 ib_dev->owner = THIS_MODULE; 456 ib_dev->node_type = RDMA_NODE_IB_CA; 457 ib_dev->dev.parent = dev; 458 459 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 460 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 461 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 462 ib_dev->uverbs_abi_ver = 1; 463 ib_dev->uverbs_cmd_mask = 464 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 465 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 466 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 467 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 468 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 469 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 470 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 471 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 472 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 473 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 474 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 475 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 476 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 477 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 478 479 ib_dev->uverbs_ex_cmd_mask |= 480 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 481 482 /* HCA||device||port */ 483 ib_dev->modify_device = hns_roce_modify_device; 484 ib_dev->query_device = hns_roce_query_device; 485 ib_dev->query_port = hns_roce_query_port; 486 ib_dev->modify_port = hns_roce_modify_port; 487 ib_dev->get_link_layer = hns_roce_get_link_layer; 488 ib_dev->get_netdev = hns_roce_get_netdev; 489 ib_dev->add_gid = hns_roce_add_gid; 490 ib_dev->del_gid = hns_roce_del_gid; 491 ib_dev->query_pkey = hns_roce_query_pkey; 492 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext; 493 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext; 494 ib_dev->mmap = hns_roce_mmap; 495 496 /* PD */ 497 ib_dev->alloc_pd = hns_roce_alloc_pd; 498 ib_dev->dealloc_pd = hns_roce_dealloc_pd; 499 500 /* AH */ 501 ib_dev->create_ah = hns_roce_create_ah; 502 ib_dev->query_ah = hns_roce_query_ah; 503 ib_dev->destroy_ah = hns_roce_destroy_ah; 504 505 /* QP */ 506 ib_dev->create_qp = hns_roce_create_qp; 507 ib_dev->modify_qp = hns_roce_modify_qp; 508 ib_dev->query_qp = hr_dev->hw->query_qp; 509 ib_dev->destroy_qp = hr_dev->hw->destroy_qp; 510 ib_dev->post_send = hr_dev->hw->post_send; 511 ib_dev->post_recv = hr_dev->hw->post_recv; 512 513 /* CQ */ 514 ib_dev->create_cq = hns_roce_ib_create_cq; 515 ib_dev->modify_cq = hr_dev->hw->modify_cq; 516 ib_dev->destroy_cq = hns_roce_ib_destroy_cq; 517 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq; 518 ib_dev->poll_cq = hr_dev->hw->poll_cq; 519 520 /* MR */ 521 ib_dev->get_dma_mr = hns_roce_get_dma_mr; 522 ib_dev->reg_user_mr = hns_roce_reg_user_mr; 523 ib_dev->dereg_mr = hns_roce_dereg_mr; 524 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 525 ib_dev->rereg_user_mr = hns_roce_rereg_user_mr; 526 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 527 } 528 529 /* MW */ 530 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 531 ib_dev->alloc_mw = hns_roce_alloc_mw; 532 ib_dev->dealloc_mw = hns_roce_dealloc_mw; 533 ib_dev->uverbs_cmd_mask |= 534 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 535 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 536 } 537 538 /* FRMR */ 539 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { 540 ib_dev->alloc_mr = hns_roce_alloc_mr; 541 ib_dev->map_mr_sg = hns_roce_map_mr_sg; 542 } 543 544 /* OTHERS */ 545 ib_dev->get_port_immutable = hns_roce_port_immutable; 546 ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext; 547 548 ib_dev->driver_id = RDMA_DRIVER_HNS; 549 ret = ib_register_device(ib_dev, "hns_%d", NULL); 550 if (ret) { 551 dev_err(dev, "ib_register_device failed!\n"); 552 return ret; 553 } 554 555 ret = hns_roce_setup_mtu_mac(hr_dev); 556 if (ret) { 557 dev_err(dev, "setup_mtu_mac failed!\n"); 558 goto error_failed_setup_mtu_mac; 559 } 560 561 iboe->nb.notifier_call = hns_roce_netdev_event; 562 ret = register_netdevice_notifier(&iboe->nb); 563 if (ret) { 564 dev_err(dev, "register_netdevice_notifier failed!\n"); 565 goto error_failed_setup_mtu_mac; 566 } 567 568 hr_dev->active = true; 569 return 0; 570 571 error_failed_setup_mtu_mac: 572 ib_unregister_device(ib_dev); 573 574 return ret; 575 } 576 577 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 578 { 579 int ret; 580 struct device *dev = hr_dev->dev; 581 582 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 583 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 584 hr_dev->caps.num_mtt_segs, 1); 585 if (ret) { 586 dev_err(dev, "Failed to init MTT context memory, aborting.\n"); 587 return ret; 588 } 589 590 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { 591 ret = hns_roce_init_hem_table(hr_dev, 592 &hr_dev->mr_table.mtt_cqe_table, 593 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz, 594 hr_dev->caps.num_cqe_segs, 1); 595 if (ret) { 596 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n"); 597 goto err_unmap_cqe; 598 } 599 } 600 601 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 602 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 603 hr_dev->caps.num_mtpts, 1); 604 if (ret) { 605 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 606 goto err_unmap_mtt; 607 } 608 609 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 610 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz, 611 hr_dev->caps.num_qps, 1); 612 if (ret) { 613 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 614 goto err_unmap_dmpt; 615 } 616 617 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 618 HEM_TYPE_IRRL, 619 hr_dev->caps.irrl_entry_sz * 620 hr_dev->caps.max_qp_init_rdma, 621 hr_dev->caps.num_qps, 1); 622 if (ret) { 623 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 624 goto err_unmap_qp; 625 } 626 627 if (hr_dev->caps.trrl_entry_sz) { 628 ret = hns_roce_init_hem_table(hr_dev, 629 &hr_dev->qp_table.trrl_table, 630 HEM_TYPE_TRRL, 631 hr_dev->caps.trrl_entry_sz * 632 hr_dev->caps.max_qp_dest_rdma, 633 hr_dev->caps.num_qps, 1); 634 if (ret) { 635 dev_err(dev, 636 "Failed to init trrl_table memory, aborting.\n"); 637 goto err_unmap_irrl; 638 } 639 } 640 641 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 642 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 643 hr_dev->caps.num_cqs, 1); 644 if (ret) { 645 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 646 goto err_unmap_trrl; 647 } 648 649 return 0; 650 651 err_unmap_trrl: 652 if (hr_dev->caps.trrl_entry_sz) 653 hns_roce_cleanup_hem_table(hr_dev, 654 &hr_dev->qp_table.trrl_table); 655 656 err_unmap_irrl: 657 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 658 659 err_unmap_qp: 660 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 661 662 err_unmap_dmpt: 663 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 664 665 err_unmap_mtt: 666 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 667 hns_roce_cleanup_hem_table(hr_dev, 668 &hr_dev->mr_table.mtt_cqe_table); 669 670 err_unmap_cqe: 671 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 672 673 return ret; 674 } 675 676 /** 677 * hns_roce_setup_hca - setup host channel adapter 678 * @hr_dev: pointer to hns roce device 679 * Return : int 680 */ 681 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 682 { 683 int ret; 684 struct device *dev = hr_dev->dev; 685 686 spin_lock_init(&hr_dev->sm_lock); 687 spin_lock_init(&hr_dev->bt_cmd_lock); 688 689 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 690 INIT_LIST_HEAD(&hr_dev->pgdir_list); 691 mutex_init(&hr_dev->pgdir_mutex); 692 } 693 694 ret = hns_roce_init_uar_table(hr_dev); 695 if (ret) { 696 dev_err(dev, "Failed to initialize uar table. aborting\n"); 697 return ret; 698 } 699 700 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 701 if (ret) { 702 dev_err(dev, "Failed to allocate priv_uar.\n"); 703 goto err_uar_table_free; 704 } 705 706 ret = hns_roce_init_pd_table(hr_dev); 707 if (ret) { 708 dev_err(dev, "Failed to init protected domain table.\n"); 709 goto err_uar_alloc_free; 710 } 711 712 ret = hns_roce_init_mr_table(hr_dev); 713 if (ret) { 714 dev_err(dev, "Failed to init memory region table.\n"); 715 goto err_pd_table_free; 716 } 717 718 ret = hns_roce_init_cq_table(hr_dev); 719 if (ret) { 720 dev_err(dev, "Failed to init completion queue table.\n"); 721 goto err_mr_table_free; 722 } 723 724 ret = hns_roce_init_qp_table(hr_dev); 725 if (ret) { 726 dev_err(dev, "Failed to init queue pair table.\n"); 727 goto err_cq_table_free; 728 } 729 730 return 0; 731 732 err_cq_table_free: 733 hns_roce_cleanup_cq_table(hr_dev); 734 735 err_mr_table_free: 736 hns_roce_cleanup_mr_table(hr_dev); 737 738 err_pd_table_free: 739 hns_roce_cleanup_pd_table(hr_dev); 740 741 err_uar_alloc_free: 742 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 743 744 err_uar_table_free: 745 hns_roce_cleanup_uar_table(hr_dev); 746 return ret; 747 } 748 749 int hns_roce_init(struct hns_roce_dev *hr_dev) 750 { 751 int ret; 752 struct device *dev = hr_dev->dev; 753 754 if (hr_dev->hw->reset) { 755 ret = hr_dev->hw->reset(hr_dev, true); 756 if (ret) { 757 dev_err(dev, "Reset RoCE engine failed!\n"); 758 return ret; 759 } 760 } 761 hr_dev->is_reset = false; 762 763 if (hr_dev->hw->cmq_init) { 764 ret = hr_dev->hw->cmq_init(hr_dev); 765 if (ret) { 766 dev_err(dev, "Init RoCE Command Queue failed!\n"); 767 goto error_failed_cmq_init; 768 } 769 } 770 771 ret = hr_dev->hw->hw_profile(hr_dev); 772 if (ret) { 773 dev_err(dev, "Get RoCE engine profile failed!\n"); 774 goto error_failed_cmd_init; 775 } 776 777 ret = hns_roce_cmd_init(hr_dev); 778 if (ret) { 779 dev_err(dev, "cmd init failed!\n"); 780 goto error_failed_cmd_init; 781 } 782 783 ret = hr_dev->hw->init_eq(hr_dev); 784 if (ret) { 785 dev_err(dev, "eq init failed!\n"); 786 goto error_failed_eq_table; 787 } 788 789 if (hr_dev->cmd_mod) { 790 ret = hns_roce_cmd_use_events(hr_dev); 791 if (ret) { 792 dev_err(dev, "Switch to event-driven cmd failed!\n"); 793 goto error_failed_use_event; 794 } 795 } 796 797 ret = hns_roce_init_hem(hr_dev); 798 if (ret) { 799 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 800 goto error_failed_init_hem; 801 } 802 803 ret = hns_roce_setup_hca(hr_dev); 804 if (ret) { 805 dev_err(dev, "setup hca failed!\n"); 806 goto error_failed_setup_hca; 807 } 808 809 if (hr_dev->hw->hw_init) { 810 ret = hr_dev->hw->hw_init(hr_dev); 811 if (ret) { 812 dev_err(dev, "hw_init failed!\n"); 813 goto error_failed_engine_init; 814 } 815 } 816 817 ret = hns_roce_register_device(hr_dev); 818 if (ret) 819 goto error_failed_register_device; 820 821 return 0; 822 823 error_failed_register_device: 824 if (hr_dev->hw->hw_exit) 825 hr_dev->hw->hw_exit(hr_dev); 826 827 error_failed_engine_init: 828 hns_roce_cleanup_bitmap(hr_dev); 829 830 error_failed_setup_hca: 831 hns_roce_cleanup_hem(hr_dev); 832 833 error_failed_init_hem: 834 if (hr_dev->cmd_mod) 835 hns_roce_cmd_use_polling(hr_dev); 836 837 error_failed_use_event: 838 hr_dev->hw->cleanup_eq(hr_dev); 839 840 error_failed_eq_table: 841 hns_roce_cmd_cleanup(hr_dev); 842 843 error_failed_cmd_init: 844 if (hr_dev->hw->cmq_exit) 845 hr_dev->hw->cmq_exit(hr_dev); 846 847 error_failed_cmq_init: 848 if (hr_dev->hw->reset) { 849 if (hr_dev->hw->reset(hr_dev, false)) 850 dev_err(dev, "Dereset RoCE engine failed!\n"); 851 } 852 853 return ret; 854 } 855 EXPORT_SYMBOL_GPL(hns_roce_init); 856 857 void hns_roce_exit(struct hns_roce_dev *hr_dev) 858 { 859 hns_roce_unregister_device(hr_dev); 860 861 if (hr_dev->hw->hw_exit) 862 hr_dev->hw->hw_exit(hr_dev); 863 hns_roce_cleanup_bitmap(hr_dev); 864 hns_roce_cleanup_hem(hr_dev); 865 866 if (hr_dev->cmd_mod) 867 hns_roce_cmd_use_polling(hr_dev); 868 869 hr_dev->hw->cleanup_eq(hr_dev); 870 hns_roce_cmd_cleanup(hr_dev); 871 if (hr_dev->hw->cmq_exit) 872 hr_dev->hw->cmq_exit(hr_dev); 873 if (hr_dev->hw->reset) 874 hr_dev->hw->reset(hr_dev, false); 875 } 876 EXPORT_SYMBOL_GPL(hns_roce_exit); 877 878 MODULE_LICENSE("Dual BSD/GPL"); 879 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 880 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 881 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 882 MODULE_DESCRIPTION("HNS RoCE Driver"); 883