1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 61 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 62 { 63 u8 phy_port; 64 u32 i = 0; 65 66 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 67 return 0; 68 69 for (i = 0; i < ETH_ALEN; i++) 70 hr_dev->dev_addr[port][i] = addr[i]; 71 72 phy_port = hr_dev->iboe.phy_port[port]; 73 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 74 } 75 76 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 77 { 78 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 79 u8 port = attr->port_num - 1; 80 int ret; 81 82 if (port >= hr_dev->caps.num_ports) 83 return -EINVAL; 84 85 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 86 87 return ret; 88 } 89 90 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 91 { 92 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 93 struct ib_gid_attr zattr = { }; 94 u8 port = attr->port_num - 1; 95 int ret; 96 97 if (port >= hr_dev->caps.num_ports) 98 return -EINVAL; 99 100 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 101 102 return ret; 103 } 104 105 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 106 unsigned long event) 107 { 108 struct device *dev = hr_dev->dev; 109 struct net_device *netdev; 110 int ret = 0; 111 112 netdev = hr_dev->iboe.netdevs[port]; 113 if (!netdev) { 114 dev_err(dev, "port(%d) can't find netdev\n", port); 115 return -ENODEV; 116 } 117 118 switch (event) { 119 case NETDEV_UP: 120 case NETDEV_CHANGE: 121 case NETDEV_REGISTER: 122 case NETDEV_CHANGEADDR: 123 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 124 break; 125 case NETDEV_DOWN: 126 /* 127 * In v1 engine, only support all ports closed together. 128 */ 129 break; 130 default: 131 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 132 break; 133 } 134 135 return ret; 136 } 137 138 static int hns_roce_netdev_event(struct notifier_block *self, 139 unsigned long event, void *ptr) 140 { 141 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 142 struct hns_roce_ib_iboe *iboe = NULL; 143 struct hns_roce_dev *hr_dev = NULL; 144 u8 port = 0; 145 int ret = 0; 146 147 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 148 iboe = &hr_dev->iboe; 149 150 for (port = 0; port < hr_dev->caps.num_ports; port++) { 151 if (dev == iboe->netdevs[port]) { 152 ret = handle_en_event(hr_dev, port, event); 153 if (ret) 154 return NOTIFY_DONE; 155 break; 156 } 157 } 158 159 return NOTIFY_DONE; 160 } 161 162 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 163 { 164 int ret; 165 u8 i; 166 167 for (i = 0; i < hr_dev->caps.num_ports; i++) { 168 if (hr_dev->hw->set_mtu) 169 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 170 hr_dev->caps.max_mtu); 171 ret = hns_roce_set_mac(hr_dev, i, 172 hr_dev->iboe.netdevs[i]->dev_addr); 173 if (ret) 174 return ret; 175 } 176 177 return 0; 178 } 179 180 static int hns_roce_query_device(struct ib_device *ib_dev, 181 struct ib_device_attr *props, 182 struct ib_udata *uhw) 183 { 184 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 185 186 memset(props, 0, sizeof(*props)); 187 188 props->fw_ver = hr_dev->caps.fw_ver; 189 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 190 props->max_mr_size = (u64)(~(0ULL)); 191 props->page_size_cap = hr_dev->caps.page_size_cap; 192 props->vendor_id = hr_dev->vendor_id; 193 props->vendor_part_id = hr_dev->vendor_part_id; 194 props->hw_ver = hr_dev->hw_rev; 195 props->max_qp = hr_dev->caps.num_qps; 196 props->max_qp_wr = hr_dev->caps.max_wqes; 197 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 198 IB_DEVICE_RC_RNR_NAK_GEN; 199 props->max_send_sge = hr_dev->caps.max_sq_sg; 200 props->max_recv_sge = hr_dev->caps.max_rq_sg; 201 props->max_sge_rd = 1; 202 props->max_cq = hr_dev->caps.num_cqs; 203 props->max_cqe = hr_dev->caps.max_cqes; 204 props->max_mr = hr_dev->caps.num_mtpts; 205 props->max_pd = hr_dev->caps.num_pds; 206 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 207 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 208 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 209 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 210 props->max_pkeys = 1; 211 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 212 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 213 props->max_srq = hr_dev->caps.max_srqs; 214 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 215 props->max_srq_sge = hr_dev->caps.max_srq_sges; 216 } 217 218 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { 219 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 220 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 221 } 222 223 return 0; 224 } 225 226 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 227 struct ib_port_attr *props) 228 { 229 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 230 struct device *dev = hr_dev->dev; 231 struct net_device *net_dev; 232 unsigned long flags; 233 enum ib_mtu mtu; 234 u8 port; 235 236 assert(port_num > 0); 237 port = port_num - 1; 238 239 /* props being zeroed by the caller, avoid zeroing it here */ 240 241 props->max_mtu = hr_dev->caps.max_mtu; 242 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 243 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 244 IB_PORT_VENDOR_CLASS_SUP | 245 IB_PORT_BOOT_MGMT_SUP; 246 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 247 props->pkey_tbl_len = 1; 248 props->active_width = IB_WIDTH_4X; 249 props->active_speed = 1; 250 251 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 252 253 net_dev = hr_dev->iboe.netdevs[port]; 254 if (!net_dev) { 255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 256 dev_err(dev, "find netdev %d failed!\r\n", port); 257 return -EINVAL; 258 } 259 260 mtu = iboe_get_mtu(net_dev->mtu); 261 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 262 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 263 IB_PORT_ACTIVE : IB_PORT_DOWN; 264 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 265 HNS_ROCE_PHY_LINKUP : HNS_ROCE_PHY_DISABLED; 266 267 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 268 269 return 0; 270 } 271 272 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 273 u8 port_num) 274 { 275 return IB_LINK_LAYER_ETHERNET; 276 } 277 278 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 279 u16 *pkey) 280 { 281 *pkey = PKEY_ID; 282 283 return 0; 284 } 285 286 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 287 struct ib_device_modify *props) 288 { 289 unsigned long flags; 290 291 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 292 return -EOPNOTSUPP; 293 294 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 295 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 296 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 297 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 298 } 299 300 return 0; 301 } 302 303 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, 304 struct ib_port_modify *props) 305 { 306 return 0; 307 } 308 309 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 310 struct ib_udata *udata) 311 { 312 int ret; 313 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 314 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 315 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 316 317 if (!hr_dev->active) 318 return -EAGAIN; 319 320 resp.qp_tab_size = hr_dev->caps.num_qps; 321 322 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 323 if (ret) 324 goto error_fail_uar_alloc; 325 326 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 327 INIT_LIST_HEAD(&context->page_list); 328 mutex_init(&context->page_mutex); 329 } 330 331 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 332 if (ret) 333 goto error_fail_copy_to_udata; 334 335 return 0; 336 337 error_fail_copy_to_udata: 338 hns_roce_uar_free(hr_dev, &context->uar); 339 340 error_fail_uar_alloc: 341 return ret; 342 } 343 344 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 345 { 346 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 347 348 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 349 } 350 351 static int hns_roce_mmap(struct ib_ucontext *context, 352 struct vm_area_struct *vma) 353 { 354 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 355 356 switch (vma->vm_pgoff) { 357 case 0: 358 return rdma_user_mmap_io(context, vma, 359 to_hr_ucontext(context)->uar.pfn, 360 PAGE_SIZE, 361 pgprot_noncached(vma->vm_page_prot)); 362 363 /* vm_pgoff: 1 -- TPTR */ 364 case 1: 365 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 366 return -EINVAL; 367 /* 368 * FIXME: using io_remap_pfn_range on the dma address returned 369 * by dma_alloc_coherent is totally wrong. 370 */ 371 return rdma_user_mmap_io(context, vma, 372 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 373 hr_dev->tptr_size, 374 vma->vm_page_prot); 375 376 default: 377 return -EINVAL; 378 } 379 } 380 381 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 382 struct ib_port_immutable *immutable) 383 { 384 struct ib_port_attr attr; 385 int ret; 386 387 ret = ib_query_port(ib_dev, port_num, &attr); 388 if (ret) 389 return ret; 390 391 immutable->pkey_tbl_len = attr.pkey_tbl_len; 392 immutable->gid_tbl_len = attr.gid_tbl_len; 393 394 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 395 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 396 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 397 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 398 399 return 0; 400 } 401 402 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 403 { 404 } 405 406 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 407 { 408 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 409 410 hr_dev->active = false; 411 unregister_netdevice_notifier(&iboe->nb); 412 ib_unregister_device(&hr_dev->ib_dev); 413 } 414 415 static const struct ib_device_ops hns_roce_dev_ops = { 416 .owner = THIS_MODULE, 417 .driver_id = RDMA_DRIVER_HNS, 418 .uverbs_abi_ver = 1, 419 .uverbs_no_driver_id_binding = 1, 420 421 .add_gid = hns_roce_add_gid, 422 .alloc_pd = hns_roce_alloc_pd, 423 .alloc_ucontext = hns_roce_alloc_ucontext, 424 .create_ah = hns_roce_create_ah, 425 .create_cq = hns_roce_ib_create_cq, 426 .create_qp = hns_roce_create_qp, 427 .dealloc_pd = hns_roce_dealloc_pd, 428 .dealloc_ucontext = hns_roce_dealloc_ucontext, 429 .del_gid = hns_roce_del_gid, 430 .dereg_mr = hns_roce_dereg_mr, 431 .destroy_ah = hns_roce_destroy_ah, 432 .destroy_cq = hns_roce_ib_destroy_cq, 433 .disassociate_ucontext = hns_roce_disassociate_ucontext, 434 .fill_res_entry = hns_roce_fill_res_entry, 435 .get_dma_mr = hns_roce_get_dma_mr, 436 .get_link_layer = hns_roce_get_link_layer, 437 .get_port_immutable = hns_roce_port_immutable, 438 .mmap = hns_roce_mmap, 439 .modify_device = hns_roce_modify_device, 440 .modify_port = hns_roce_modify_port, 441 .modify_qp = hns_roce_modify_qp, 442 .query_ah = hns_roce_query_ah, 443 .query_device = hns_roce_query_device, 444 .query_pkey = hns_roce_query_pkey, 445 .query_port = hns_roce_query_port, 446 .reg_user_mr = hns_roce_reg_user_mr, 447 448 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 449 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 450 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 451 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 452 }; 453 454 static const struct ib_device_ops hns_roce_dev_mr_ops = { 455 .rereg_user_mr = hns_roce_rereg_user_mr, 456 }; 457 458 static const struct ib_device_ops hns_roce_dev_mw_ops = { 459 .alloc_mw = hns_roce_alloc_mw, 460 .dealloc_mw = hns_roce_dealloc_mw, 461 }; 462 463 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 464 .alloc_mr = hns_roce_alloc_mr, 465 .map_mr_sg = hns_roce_map_mr_sg, 466 }; 467 468 static const struct ib_device_ops hns_roce_dev_srq_ops = { 469 .create_srq = hns_roce_create_srq, 470 .destroy_srq = hns_roce_destroy_srq, 471 472 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 473 }; 474 475 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 476 { 477 int ret; 478 struct hns_roce_ib_iboe *iboe = NULL; 479 struct ib_device *ib_dev = NULL; 480 struct device *dev = hr_dev->dev; 481 unsigned int i; 482 483 iboe = &hr_dev->iboe; 484 spin_lock_init(&iboe->lock); 485 486 ib_dev = &hr_dev->ib_dev; 487 488 ib_dev->node_type = RDMA_NODE_IB_CA; 489 ib_dev->dev.parent = dev; 490 491 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 492 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 493 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 494 ib_dev->uverbs_cmd_mask = 495 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 496 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 497 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 498 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 499 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 500 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 501 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 502 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 503 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 504 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 505 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 506 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 507 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 508 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 509 510 ib_dev->uverbs_ex_cmd_mask |= 511 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 512 513 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 514 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 515 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 516 } 517 518 /* MW */ 519 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 520 ib_dev->uverbs_cmd_mask |= 521 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 522 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 523 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 524 } 525 526 /* FRMR */ 527 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 528 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 529 530 /* SRQ */ 531 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 532 ib_dev->uverbs_cmd_mask |= 533 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | 534 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | 535 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | 536 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | 537 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV); 538 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 539 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 540 } 541 542 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 543 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 544 for (i = 0; i < hr_dev->caps.num_ports; i++) { 545 if (!hr_dev->iboe.netdevs[i]) 546 continue; 547 548 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 549 i + 1); 550 if (ret) 551 return ret; 552 } 553 ret = ib_register_device(ib_dev, "hns_%d"); 554 if (ret) { 555 dev_err(dev, "ib_register_device failed!\n"); 556 return ret; 557 } 558 559 ret = hns_roce_setup_mtu_mac(hr_dev); 560 if (ret) { 561 dev_err(dev, "setup_mtu_mac failed!\n"); 562 goto error_failed_setup_mtu_mac; 563 } 564 565 iboe->nb.notifier_call = hns_roce_netdev_event; 566 ret = register_netdevice_notifier(&iboe->nb); 567 if (ret) { 568 dev_err(dev, "register_netdevice_notifier failed!\n"); 569 goto error_failed_setup_mtu_mac; 570 } 571 572 hr_dev->active = true; 573 return 0; 574 575 error_failed_setup_mtu_mac: 576 ib_unregister_device(ib_dev); 577 578 return ret; 579 } 580 581 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 582 { 583 int ret; 584 struct device *dev = hr_dev->dev; 585 586 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 587 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 588 hr_dev->caps.num_mtt_segs, 1); 589 if (ret) { 590 dev_err(dev, "Failed to init MTT context memory, aborting.\n"); 591 return ret; 592 } 593 594 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { 595 ret = hns_roce_init_hem_table(hr_dev, 596 &hr_dev->mr_table.mtt_cqe_table, 597 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz, 598 hr_dev->caps.num_cqe_segs, 1); 599 if (ret) { 600 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n"); 601 goto err_unmap_cqe; 602 } 603 } 604 605 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 606 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 607 hr_dev->caps.num_mtpts, 1); 608 if (ret) { 609 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 610 goto err_unmap_mtt; 611 } 612 613 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 614 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz, 615 hr_dev->caps.num_qps, 1); 616 if (ret) { 617 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 618 goto err_unmap_dmpt; 619 } 620 621 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 622 HEM_TYPE_IRRL, 623 hr_dev->caps.irrl_entry_sz * 624 hr_dev->caps.max_qp_init_rdma, 625 hr_dev->caps.num_qps, 1); 626 if (ret) { 627 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 628 goto err_unmap_qp; 629 } 630 631 if (hr_dev->caps.trrl_entry_sz) { 632 ret = hns_roce_init_hem_table(hr_dev, 633 &hr_dev->qp_table.trrl_table, 634 HEM_TYPE_TRRL, 635 hr_dev->caps.trrl_entry_sz * 636 hr_dev->caps.max_qp_dest_rdma, 637 hr_dev->caps.num_qps, 1); 638 if (ret) { 639 dev_err(dev, 640 "Failed to init trrl_table memory, aborting.\n"); 641 goto err_unmap_irrl; 642 } 643 } 644 645 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 646 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 647 hr_dev->caps.num_cqs, 1); 648 if (ret) { 649 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 650 goto err_unmap_trrl; 651 } 652 653 if (hr_dev->caps.srqc_entry_sz) { 654 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 655 HEM_TYPE_SRQC, 656 hr_dev->caps.srqc_entry_sz, 657 hr_dev->caps.num_srqs, 1); 658 if (ret) { 659 dev_err(dev, 660 "Failed to init SRQ context memory, aborting.\n"); 661 goto err_unmap_cq; 662 } 663 } 664 665 if (hr_dev->caps.num_srqwqe_segs) { 666 ret = hns_roce_init_hem_table(hr_dev, 667 &hr_dev->mr_table.mtt_srqwqe_table, 668 HEM_TYPE_SRQWQE, 669 hr_dev->caps.mtt_entry_sz, 670 hr_dev->caps.num_srqwqe_segs, 1); 671 if (ret) { 672 dev_err(dev, 673 "Failed to init MTT srqwqe memory, aborting.\n"); 674 goto err_unmap_srq; 675 } 676 } 677 678 if (hr_dev->caps.num_idx_segs) { 679 ret = hns_roce_init_hem_table(hr_dev, 680 &hr_dev->mr_table.mtt_idx_table, 681 HEM_TYPE_IDX, 682 hr_dev->caps.idx_entry_sz, 683 hr_dev->caps.num_idx_segs, 1); 684 if (ret) { 685 dev_err(dev, 686 "Failed to init MTT idx memory, aborting.\n"); 687 goto err_unmap_srqwqe; 688 } 689 } 690 691 if (hr_dev->caps.sccc_entry_sz) { 692 ret = hns_roce_init_hem_table(hr_dev, 693 &hr_dev->qp_table.sccc_table, 694 HEM_TYPE_SCCC, 695 hr_dev->caps.sccc_entry_sz, 696 hr_dev->caps.num_qps, 1); 697 if (ret) { 698 dev_err(dev, 699 "Failed to init SCC context memory, aborting.\n"); 700 goto err_unmap_idx; 701 } 702 } 703 704 if (hr_dev->caps.qpc_timer_entry_sz) { 705 ret = hns_roce_init_hem_table(hr_dev, 706 &hr_dev->qpc_timer_table, 707 HEM_TYPE_QPC_TIMER, 708 hr_dev->caps.qpc_timer_entry_sz, 709 hr_dev->caps.num_qpc_timer, 1); 710 if (ret) { 711 dev_err(dev, 712 "Failed to init QPC timer memory, aborting.\n"); 713 goto err_unmap_ctx; 714 } 715 } 716 717 if (hr_dev->caps.cqc_timer_entry_sz) { 718 ret = hns_roce_init_hem_table(hr_dev, 719 &hr_dev->cqc_timer_table, 720 HEM_TYPE_CQC_TIMER, 721 hr_dev->caps.cqc_timer_entry_sz, 722 hr_dev->caps.num_cqc_timer, 1); 723 if (ret) { 724 dev_err(dev, 725 "Failed to init CQC timer memory, aborting.\n"); 726 goto err_unmap_qpc_timer; 727 } 728 } 729 730 return 0; 731 732 err_unmap_qpc_timer: 733 if (hr_dev->caps.qpc_timer_entry_sz) 734 hns_roce_cleanup_hem_table(hr_dev, 735 &hr_dev->qpc_timer_table); 736 737 err_unmap_ctx: 738 if (hr_dev->caps.sccc_entry_sz) 739 hns_roce_cleanup_hem_table(hr_dev, 740 &hr_dev->qp_table.sccc_table); 741 742 err_unmap_idx: 743 if (hr_dev->caps.num_idx_segs) 744 hns_roce_cleanup_hem_table(hr_dev, 745 &hr_dev->mr_table.mtt_idx_table); 746 747 err_unmap_srqwqe: 748 if (hr_dev->caps.num_srqwqe_segs) 749 hns_roce_cleanup_hem_table(hr_dev, 750 &hr_dev->mr_table.mtt_srqwqe_table); 751 752 err_unmap_srq: 753 if (hr_dev->caps.srqc_entry_sz) 754 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 755 756 err_unmap_cq: 757 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 758 759 err_unmap_trrl: 760 if (hr_dev->caps.trrl_entry_sz) 761 hns_roce_cleanup_hem_table(hr_dev, 762 &hr_dev->qp_table.trrl_table); 763 764 err_unmap_irrl: 765 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 766 767 err_unmap_qp: 768 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 769 770 err_unmap_dmpt: 771 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 772 773 err_unmap_mtt: 774 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 775 hns_roce_cleanup_hem_table(hr_dev, 776 &hr_dev->mr_table.mtt_cqe_table); 777 778 err_unmap_cqe: 779 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 780 781 return ret; 782 } 783 784 /** 785 * hns_roce_setup_hca - setup host channel adapter 786 * @hr_dev: pointer to hns roce device 787 * Return : int 788 */ 789 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 790 { 791 int ret; 792 struct device *dev = hr_dev->dev; 793 794 spin_lock_init(&hr_dev->sm_lock); 795 spin_lock_init(&hr_dev->bt_cmd_lock); 796 797 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 798 INIT_LIST_HEAD(&hr_dev->pgdir_list); 799 mutex_init(&hr_dev->pgdir_mutex); 800 } 801 802 ret = hns_roce_init_uar_table(hr_dev); 803 if (ret) { 804 dev_err(dev, "Failed to initialize uar table. aborting\n"); 805 return ret; 806 } 807 808 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 809 if (ret) { 810 dev_err(dev, "Failed to allocate priv_uar.\n"); 811 goto err_uar_table_free; 812 } 813 814 ret = hns_roce_init_pd_table(hr_dev); 815 if (ret) { 816 dev_err(dev, "Failed to init protected domain table.\n"); 817 goto err_uar_alloc_free; 818 } 819 820 ret = hns_roce_init_mr_table(hr_dev); 821 if (ret) { 822 dev_err(dev, "Failed to init memory region table.\n"); 823 goto err_pd_table_free; 824 } 825 826 ret = hns_roce_init_cq_table(hr_dev); 827 if (ret) { 828 dev_err(dev, "Failed to init completion queue table.\n"); 829 goto err_mr_table_free; 830 } 831 832 ret = hns_roce_init_qp_table(hr_dev); 833 if (ret) { 834 dev_err(dev, "Failed to init queue pair table.\n"); 835 goto err_cq_table_free; 836 } 837 838 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 839 ret = hns_roce_init_srq_table(hr_dev); 840 if (ret) { 841 dev_err(dev, 842 "Failed to init share receive queue table.\n"); 843 goto err_qp_table_free; 844 } 845 } 846 847 return 0; 848 849 err_qp_table_free: 850 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 851 hns_roce_cleanup_qp_table(hr_dev); 852 853 err_cq_table_free: 854 hns_roce_cleanup_cq_table(hr_dev); 855 856 err_mr_table_free: 857 hns_roce_cleanup_mr_table(hr_dev); 858 859 err_pd_table_free: 860 hns_roce_cleanup_pd_table(hr_dev); 861 862 err_uar_alloc_free: 863 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 864 865 err_uar_table_free: 866 hns_roce_cleanup_uar_table(hr_dev); 867 return ret; 868 } 869 870 int hns_roce_init(struct hns_roce_dev *hr_dev) 871 { 872 int ret; 873 struct device *dev = hr_dev->dev; 874 875 if (hr_dev->hw->reset) { 876 ret = hr_dev->hw->reset(hr_dev, true); 877 if (ret) { 878 dev_err(dev, "Reset RoCE engine failed!\n"); 879 return ret; 880 } 881 } 882 hr_dev->is_reset = false; 883 884 if (hr_dev->hw->cmq_init) { 885 ret = hr_dev->hw->cmq_init(hr_dev); 886 if (ret) { 887 dev_err(dev, "Init RoCE Command Queue failed!\n"); 888 goto error_failed_cmq_init; 889 } 890 } 891 892 ret = hr_dev->hw->hw_profile(hr_dev); 893 if (ret) { 894 dev_err(dev, "Get RoCE engine profile failed!\n"); 895 goto error_failed_cmd_init; 896 } 897 898 ret = hns_roce_cmd_init(hr_dev); 899 if (ret) { 900 dev_err(dev, "cmd init failed!\n"); 901 goto error_failed_cmd_init; 902 } 903 904 ret = hr_dev->hw->init_eq(hr_dev); 905 if (ret) { 906 dev_err(dev, "eq init failed!\n"); 907 goto error_failed_eq_table; 908 } 909 910 if (hr_dev->cmd_mod) { 911 ret = hns_roce_cmd_use_events(hr_dev); 912 if (ret) { 913 dev_err(dev, "Switch to event-driven cmd failed!\n"); 914 goto error_failed_use_event; 915 } 916 } 917 918 ret = hns_roce_init_hem(hr_dev); 919 if (ret) { 920 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 921 goto error_failed_init_hem; 922 } 923 924 ret = hns_roce_setup_hca(hr_dev); 925 if (ret) { 926 dev_err(dev, "setup hca failed!\n"); 927 goto error_failed_setup_hca; 928 } 929 930 if (hr_dev->hw->hw_init) { 931 ret = hr_dev->hw->hw_init(hr_dev); 932 if (ret) { 933 dev_err(dev, "hw_init failed!\n"); 934 goto error_failed_engine_init; 935 } 936 } 937 938 ret = hns_roce_register_device(hr_dev); 939 if (ret) 940 goto error_failed_register_device; 941 942 return 0; 943 944 error_failed_register_device: 945 if (hr_dev->hw->hw_exit) 946 hr_dev->hw->hw_exit(hr_dev); 947 948 error_failed_engine_init: 949 hns_roce_cleanup_bitmap(hr_dev); 950 951 error_failed_setup_hca: 952 hns_roce_cleanup_hem(hr_dev); 953 954 error_failed_init_hem: 955 if (hr_dev->cmd_mod) 956 hns_roce_cmd_use_polling(hr_dev); 957 958 error_failed_use_event: 959 hr_dev->hw->cleanup_eq(hr_dev); 960 961 error_failed_eq_table: 962 hns_roce_cmd_cleanup(hr_dev); 963 964 error_failed_cmd_init: 965 if (hr_dev->hw->cmq_exit) 966 hr_dev->hw->cmq_exit(hr_dev); 967 968 error_failed_cmq_init: 969 if (hr_dev->hw->reset) { 970 if (hr_dev->hw->reset(hr_dev, false)) 971 dev_err(dev, "Dereset RoCE engine failed!\n"); 972 } 973 974 return ret; 975 } 976 977 void hns_roce_exit(struct hns_roce_dev *hr_dev) 978 { 979 hns_roce_unregister_device(hr_dev); 980 981 if (hr_dev->hw->hw_exit) 982 hr_dev->hw->hw_exit(hr_dev); 983 hns_roce_cleanup_bitmap(hr_dev); 984 hns_roce_cleanup_hem(hr_dev); 985 986 if (hr_dev->cmd_mod) 987 hns_roce_cmd_use_polling(hr_dev); 988 989 hr_dev->hw->cleanup_eq(hr_dev); 990 hns_roce_cmd_cleanup(hr_dev); 991 if (hr_dev->hw->cmq_exit) 992 hr_dev->hw->cmq_exit(hr_dev); 993 if (hr_dev->hw->reset) 994 hr_dev->hw->reset(hr_dev, false); 995 } 996 997 MODULE_LICENSE("Dual BSD/GPL"); 998 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 999 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1000 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1001 MODULE_DESCRIPTION("HNS RoCE Driver"); 1002