1 /*
2  * Copyright (c) 2016 Hisilicon Limited.
3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include <rdma/hns-abi.h>
43 #include "hns_roce_hem.h"
44 
45 /**
46  * hns_get_gid_index - Get gid index.
47  * @hr_dev: pointer to structure hns_roce_dev.
48  * @port:  port, value range: 0 ~ MAX
49  * @gid_index:  gid_index, value range: 0 ~ MAX
50  * Description:
51  *    N ports shared gids, allocation method as follow:
52  *		GID[0][0], GID[1][0],.....GID[N - 1][0],
53  *		GID[0][0], GID[1][0],.....GID[N - 1][0],
54  *		And so on
55  */
56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57 {
58 	return gid_index * hr_dev->caps.num_ports + port;
59 }
60 EXPORT_SYMBOL_GPL(hns_get_gid_index);
61 
62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
63 {
64 	u8 phy_port;
65 	u32 i = 0;
66 
67 	if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
68 		return 0;
69 
70 	for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
71 		hr_dev->dev_addr[port][i] = addr[i];
72 
73 	phy_port = hr_dev->iboe.phy_port[port];
74 	return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
75 }
76 
77 static int hns_roce_add_gid(const union ib_gid *gid,
78 			    const struct ib_gid_attr *attr, void **context)
79 {
80 	struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
81 	u8 port = attr->port_num - 1;
82 	unsigned long flags;
83 	int ret;
84 
85 	if (port >= hr_dev->caps.num_ports)
86 		return -EINVAL;
87 
88 	spin_lock_irqsave(&hr_dev->iboe.lock, flags);
89 
90 	ret = hr_dev->hw->set_gid(hr_dev, port, attr->index,
91 				  (union ib_gid *)gid, attr);
92 
93 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
94 
95 	return ret;
96 }
97 
98 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
99 {
100 	struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
101 	struct ib_gid_attr zattr = { };
102 	union ib_gid zgid = { {0} };
103 	u8 port = attr->port_num - 1;
104 	unsigned long flags;
105 	int ret;
106 
107 	if (port >= hr_dev->caps.num_ports)
108 		return -EINVAL;
109 
110 	spin_lock_irqsave(&hr_dev->iboe.lock, flags);
111 
112 	ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
113 
114 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
115 
116 	return ret;
117 }
118 
119 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
120 			   unsigned long event)
121 {
122 	struct device *dev = hr_dev->dev;
123 	struct net_device *netdev;
124 	int ret = 0;
125 
126 	netdev = hr_dev->iboe.netdevs[port];
127 	if (!netdev) {
128 		dev_err(dev, "port(%d) can't find netdev\n", port);
129 		return -ENODEV;
130 	}
131 
132 	switch (event) {
133 	case NETDEV_UP:
134 	case NETDEV_CHANGE:
135 	case NETDEV_REGISTER:
136 	case NETDEV_CHANGEADDR:
137 		ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
138 		break;
139 	case NETDEV_DOWN:
140 		/*
141 		 * In v1 engine, only support all ports closed together.
142 		 */
143 		break;
144 	default:
145 		dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
146 		break;
147 	}
148 
149 	return ret;
150 }
151 
152 static int hns_roce_netdev_event(struct notifier_block *self,
153 				 unsigned long event, void *ptr)
154 {
155 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
156 	struct hns_roce_ib_iboe *iboe = NULL;
157 	struct hns_roce_dev *hr_dev = NULL;
158 	u8 port = 0;
159 	int ret = 0;
160 
161 	hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
162 	iboe = &hr_dev->iboe;
163 
164 	for (port = 0; port < hr_dev->caps.num_ports; port++) {
165 		if (dev == iboe->netdevs[port]) {
166 			ret = handle_en_event(hr_dev, port, event);
167 			if (ret)
168 				return NOTIFY_DONE;
169 			break;
170 		}
171 	}
172 
173 	return NOTIFY_DONE;
174 }
175 
176 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
177 {
178 	int ret;
179 	u8 i;
180 
181 	for (i = 0; i < hr_dev->caps.num_ports; i++) {
182 		if (hr_dev->hw->set_mtu)
183 			hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
184 					    hr_dev->caps.max_mtu);
185 		ret = hns_roce_set_mac(hr_dev, i,
186 				       hr_dev->iboe.netdevs[i]->dev_addr);
187 		if (ret)
188 			return ret;
189 	}
190 
191 	return 0;
192 }
193 
194 static int hns_roce_query_device(struct ib_device *ib_dev,
195 				 struct ib_device_attr *props,
196 				 struct ib_udata *uhw)
197 {
198 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
199 
200 	memset(props, 0, sizeof(*props));
201 
202 	props->sys_image_guid = cpu_to_be32(hr_dev->sys_image_guid);
203 	props->max_mr_size = (u64)(~(0ULL));
204 	props->page_size_cap = hr_dev->caps.page_size_cap;
205 	props->vendor_id = hr_dev->vendor_id;
206 	props->vendor_part_id = hr_dev->vendor_part_id;
207 	props->hw_ver = hr_dev->hw_rev;
208 	props->max_qp = hr_dev->caps.num_qps;
209 	props->max_qp_wr = hr_dev->caps.max_wqes;
210 	props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
211 				  IB_DEVICE_RC_RNR_NAK_GEN;
212 	props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
213 	props->max_sge_rd = 1;
214 	props->max_cq = hr_dev->caps.num_cqs;
215 	props->max_cqe = hr_dev->caps.max_cqes;
216 	props->max_mr = hr_dev->caps.num_mtpts;
217 	props->max_pd = hr_dev->caps.num_pds;
218 	props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
219 	props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
220 	props->atomic_cap = IB_ATOMIC_NONE;
221 	props->max_pkeys = 1;
222 	props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
223 
224 	return 0;
225 }
226 
227 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
228 					      u8 port_num)
229 {
230 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
231 	struct net_device *ndev;
232 
233 	if (port_num < 1 || port_num > hr_dev->caps.num_ports)
234 		return NULL;
235 
236 	rcu_read_lock();
237 
238 	ndev = hr_dev->iboe.netdevs[port_num - 1];
239 	if (ndev)
240 		dev_hold(ndev);
241 
242 	rcu_read_unlock();
243 	return ndev;
244 }
245 
246 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
247 			       struct ib_port_attr *props)
248 {
249 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
250 	struct device *dev = hr_dev->dev;
251 	struct net_device *net_dev;
252 	unsigned long flags;
253 	enum ib_mtu mtu;
254 	u8 port;
255 
256 	assert(port_num > 0);
257 	port = port_num - 1;
258 
259 	/* props being zeroed by the caller, avoid zeroing it here */
260 
261 	props->max_mtu = hr_dev->caps.max_mtu;
262 	props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
263 	props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
264 				IB_PORT_VENDOR_CLASS_SUP |
265 				IB_PORT_BOOT_MGMT_SUP;
266 	props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
267 	props->pkey_tbl_len = 1;
268 	props->active_width = IB_WIDTH_4X;
269 	props->active_speed = 1;
270 
271 	spin_lock_irqsave(&hr_dev->iboe.lock, flags);
272 
273 	net_dev = hr_dev->iboe.netdevs[port];
274 	if (!net_dev) {
275 		spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
276 		dev_err(dev, "find netdev %d failed!\r\n", port);
277 		return -EINVAL;
278 	}
279 
280 	mtu = iboe_get_mtu(net_dev->mtu);
281 	props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
282 	props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
283 			IB_PORT_ACTIVE : IB_PORT_DOWN;
284 	props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
285 
286 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
287 
288 	return 0;
289 }
290 
291 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
292 						    u8 port_num)
293 {
294 	return IB_LINK_LAYER_ETHERNET;
295 }
296 
297 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
298 			       u16 *pkey)
299 {
300 	*pkey = PKEY_ID;
301 
302 	return 0;
303 }
304 
305 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
306 				  struct ib_device_modify *props)
307 {
308 	unsigned long flags;
309 
310 	if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
311 		return -EOPNOTSUPP;
312 
313 	if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
314 		spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
315 		memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
316 		spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
317 	}
318 
319 	return 0;
320 }
321 
322 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
323 				struct ib_port_modify *props)
324 {
325 	return 0;
326 }
327 
328 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
329 						   struct ib_udata *udata)
330 {
331 	int ret = 0;
332 	struct hns_roce_ucontext *context;
333 	struct hns_roce_ib_alloc_ucontext_resp resp = {};
334 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
335 
336 	resp.qp_tab_size = hr_dev->caps.num_qps;
337 
338 	context = kmalloc(sizeof(*context), GFP_KERNEL);
339 	if (!context)
340 		return ERR_PTR(-ENOMEM);
341 
342 	ret = hns_roce_uar_alloc(hr_dev, &context->uar);
343 	if (ret)
344 		goto error_fail_uar_alloc;
345 
346 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
347 		INIT_LIST_HEAD(&context->page_list);
348 		mutex_init(&context->page_mutex);
349 	}
350 
351 	ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
352 	if (ret)
353 		goto error_fail_copy_to_udata;
354 
355 	return &context->ibucontext;
356 
357 error_fail_copy_to_udata:
358 	hns_roce_uar_free(hr_dev, &context->uar);
359 
360 error_fail_uar_alloc:
361 	kfree(context);
362 
363 	return ERR_PTR(ret);
364 }
365 
366 static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
367 {
368 	struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
369 
370 	hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
371 	kfree(context);
372 
373 	return 0;
374 }
375 
376 static int hns_roce_mmap(struct ib_ucontext *context,
377 			 struct vm_area_struct *vma)
378 {
379 	struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
380 
381 	if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
382 		return -EINVAL;
383 
384 	if (vma->vm_pgoff == 0) {
385 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
386 		if (io_remap_pfn_range(vma, vma->vm_start,
387 				       to_hr_ucontext(context)->uar.pfn,
388 				       PAGE_SIZE, vma->vm_page_prot))
389 			return -EAGAIN;
390 	} else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
391 		   hr_dev->tptr_size) {
392 		/* vm_pgoff: 1 -- TPTR */
393 		if (io_remap_pfn_range(vma, vma->vm_start,
394 				       hr_dev->tptr_dma_addr >> PAGE_SHIFT,
395 				       hr_dev->tptr_size,
396 				       vma->vm_page_prot))
397 			return -EAGAIN;
398 	} else
399 		return -EINVAL;
400 
401 	return 0;
402 }
403 
404 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
405 				   struct ib_port_immutable *immutable)
406 {
407 	struct ib_port_attr attr;
408 	int ret;
409 
410 	ret = ib_query_port(ib_dev, port_num, &attr);
411 	if (ret)
412 		return ret;
413 
414 	immutable->pkey_tbl_len = attr.pkey_tbl_len;
415 	immutable->gid_tbl_len = attr.gid_tbl_len;
416 
417 	immutable->max_mad_size = IB_MGMT_MAD_SIZE;
418 	immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
419 	if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
420 		immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
421 
422 	return 0;
423 }
424 
425 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
426 {
427 	struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
428 
429 	unregister_netdevice_notifier(&iboe->nb);
430 	ib_unregister_device(&hr_dev->ib_dev);
431 }
432 
433 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
434 {
435 	int ret;
436 	struct hns_roce_ib_iboe *iboe = NULL;
437 	struct ib_device *ib_dev = NULL;
438 	struct device *dev = hr_dev->dev;
439 
440 	iboe = &hr_dev->iboe;
441 	spin_lock_init(&iboe->lock);
442 
443 	ib_dev = &hr_dev->ib_dev;
444 	strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
445 
446 	ib_dev->owner			= THIS_MODULE;
447 	ib_dev->node_type		= RDMA_NODE_IB_CA;
448 	ib_dev->dev.parent		= dev;
449 
450 	ib_dev->phys_port_cnt		= hr_dev->caps.num_ports;
451 	ib_dev->local_dma_lkey		= hr_dev->caps.reserved_lkey;
452 	ib_dev->num_comp_vectors	= hr_dev->caps.num_comp_vectors;
453 	ib_dev->uverbs_abi_ver		= 1;
454 	ib_dev->uverbs_cmd_mask		=
455 		(1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
456 		(1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
457 		(1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
458 		(1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
459 		(1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
460 		(1ULL << IB_USER_VERBS_CMD_REG_MR) |
461 		(1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
462 		(1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
463 		(1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
464 		(1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
465 		(1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
466 		(1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
467 		(1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
468 		(1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
469 
470 	/* HCA||device||port */
471 	ib_dev->modify_device		= hns_roce_modify_device;
472 	ib_dev->query_device		= hns_roce_query_device;
473 	ib_dev->query_port		= hns_roce_query_port;
474 	ib_dev->modify_port		= hns_roce_modify_port;
475 	ib_dev->get_link_layer		= hns_roce_get_link_layer;
476 	ib_dev->get_netdev		= hns_roce_get_netdev;
477 	ib_dev->add_gid			= hns_roce_add_gid;
478 	ib_dev->del_gid			= hns_roce_del_gid;
479 	ib_dev->query_pkey		= hns_roce_query_pkey;
480 	ib_dev->alloc_ucontext		= hns_roce_alloc_ucontext;
481 	ib_dev->dealloc_ucontext	= hns_roce_dealloc_ucontext;
482 	ib_dev->mmap			= hns_roce_mmap;
483 
484 	/* PD */
485 	ib_dev->alloc_pd		= hns_roce_alloc_pd;
486 	ib_dev->dealloc_pd		= hns_roce_dealloc_pd;
487 
488 	/* AH */
489 	ib_dev->create_ah		= hns_roce_create_ah;
490 	ib_dev->query_ah		= hns_roce_query_ah;
491 	ib_dev->destroy_ah		= hns_roce_destroy_ah;
492 
493 	/* QP */
494 	ib_dev->create_qp		= hns_roce_create_qp;
495 	ib_dev->modify_qp		= hns_roce_modify_qp;
496 	ib_dev->query_qp		= hr_dev->hw->query_qp;
497 	ib_dev->destroy_qp		= hr_dev->hw->destroy_qp;
498 	ib_dev->post_send		= hr_dev->hw->post_send;
499 	ib_dev->post_recv		= hr_dev->hw->post_recv;
500 
501 	/* CQ */
502 	ib_dev->create_cq		= hns_roce_ib_create_cq;
503 	ib_dev->modify_cq		= hr_dev->hw->modify_cq;
504 	ib_dev->destroy_cq		= hns_roce_ib_destroy_cq;
505 	ib_dev->req_notify_cq		= hr_dev->hw->req_notify_cq;
506 	ib_dev->poll_cq			= hr_dev->hw->poll_cq;
507 
508 	/* MR */
509 	ib_dev->get_dma_mr		= hns_roce_get_dma_mr;
510 	ib_dev->reg_user_mr		= hns_roce_reg_user_mr;
511 	ib_dev->dereg_mr		= hns_roce_dereg_mr;
512 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
513 		ib_dev->rereg_user_mr	= hns_roce_rereg_user_mr;
514 		ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
515 	}
516 
517 	/* OTHERS */
518 	ib_dev->get_port_immutable	= hns_roce_port_immutable;
519 
520 	ib_dev->driver_id = RDMA_DRIVER_HNS;
521 	ret = ib_register_device(ib_dev, NULL);
522 	if (ret) {
523 		dev_err(dev, "ib_register_device failed!\n");
524 		return ret;
525 	}
526 
527 	ret = hns_roce_setup_mtu_mac(hr_dev);
528 	if (ret) {
529 		dev_err(dev, "setup_mtu_mac failed!\n");
530 		goto error_failed_setup_mtu_mac;
531 	}
532 
533 	iboe->nb.notifier_call = hns_roce_netdev_event;
534 	ret = register_netdevice_notifier(&iboe->nb);
535 	if (ret) {
536 		dev_err(dev, "register_netdevice_notifier failed!\n");
537 		goto error_failed_setup_mtu_mac;
538 	}
539 
540 	return 0;
541 
542 error_failed_setup_mtu_mac:
543 	ib_unregister_device(ib_dev);
544 
545 	return ret;
546 }
547 
548 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
549 {
550 	int ret;
551 	struct device *dev = hr_dev->dev;
552 
553 	ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
554 				      HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
555 				      hr_dev->caps.num_mtt_segs, 1);
556 	if (ret) {
557 		dev_err(dev, "Failed to init MTT context memory, aborting.\n");
558 		return ret;
559 	}
560 
561 	if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
562 		ret = hns_roce_init_hem_table(hr_dev,
563 				      &hr_dev->mr_table.mtt_cqe_table,
564 				      HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
565 				      hr_dev->caps.num_cqe_segs, 1);
566 		if (ret) {
567 			dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
568 			goto err_unmap_cqe;
569 		}
570 	}
571 
572 	ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
573 				      HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
574 				      hr_dev->caps.num_mtpts, 1);
575 	if (ret) {
576 		dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
577 		goto err_unmap_mtt;
578 	}
579 
580 	ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
581 				      HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
582 				      hr_dev->caps.num_qps, 1);
583 	if (ret) {
584 		dev_err(dev, "Failed to init QP context memory, aborting.\n");
585 		goto err_unmap_dmpt;
586 	}
587 
588 	ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
589 				      HEM_TYPE_IRRL,
590 				      hr_dev->caps.irrl_entry_sz *
591 				      hr_dev->caps.max_qp_init_rdma,
592 				      hr_dev->caps.num_qps, 1);
593 	if (ret) {
594 		dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
595 		goto err_unmap_qp;
596 	}
597 
598 	if (hr_dev->caps.trrl_entry_sz) {
599 		ret = hns_roce_init_hem_table(hr_dev,
600 					      &hr_dev->qp_table.trrl_table,
601 					      HEM_TYPE_TRRL,
602 					      hr_dev->caps.trrl_entry_sz *
603 					      hr_dev->caps.max_qp_dest_rdma,
604 					      hr_dev->caps.num_qps, 1);
605 		if (ret) {
606 			dev_err(dev,
607 			       "Failed to init trrl_table memory, aborting.\n");
608 			goto err_unmap_irrl;
609 		}
610 	}
611 
612 	ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
613 				      HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
614 				      hr_dev->caps.num_cqs, 1);
615 	if (ret) {
616 		dev_err(dev, "Failed to init CQ context memory, aborting.\n");
617 		goto err_unmap_trrl;
618 	}
619 
620 	return 0;
621 
622 err_unmap_trrl:
623 	if (hr_dev->caps.trrl_entry_sz)
624 		hns_roce_cleanup_hem_table(hr_dev,
625 					   &hr_dev->qp_table.trrl_table);
626 
627 err_unmap_irrl:
628 	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
629 
630 err_unmap_qp:
631 	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
632 
633 err_unmap_dmpt:
634 	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
635 
636 err_unmap_mtt:
637 	if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
638 		hns_roce_cleanup_hem_table(hr_dev,
639 					   &hr_dev->mr_table.mtt_cqe_table);
640 
641 err_unmap_cqe:
642 	hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
643 
644 	return ret;
645 }
646 
647 /**
648  * hns_roce_setup_hca - setup host channel adapter
649  * @hr_dev: pointer to hns roce device
650  * Return : int
651  */
652 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
653 {
654 	int ret;
655 	struct device *dev = hr_dev->dev;
656 
657 	spin_lock_init(&hr_dev->sm_lock);
658 	spin_lock_init(&hr_dev->bt_cmd_lock);
659 
660 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
661 		INIT_LIST_HEAD(&hr_dev->pgdir_list);
662 		mutex_init(&hr_dev->pgdir_mutex);
663 	}
664 
665 	ret = hns_roce_init_uar_table(hr_dev);
666 	if (ret) {
667 		dev_err(dev, "Failed to initialize uar table. aborting\n");
668 		return ret;
669 	}
670 
671 	ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
672 	if (ret) {
673 		dev_err(dev, "Failed to allocate priv_uar.\n");
674 		goto err_uar_table_free;
675 	}
676 
677 	ret = hns_roce_init_pd_table(hr_dev);
678 	if (ret) {
679 		dev_err(dev, "Failed to init protected domain table.\n");
680 		goto err_uar_alloc_free;
681 	}
682 
683 	ret = hns_roce_init_mr_table(hr_dev);
684 	if (ret) {
685 		dev_err(dev, "Failed to init memory region table.\n");
686 		goto err_pd_table_free;
687 	}
688 
689 	ret = hns_roce_init_cq_table(hr_dev);
690 	if (ret) {
691 		dev_err(dev, "Failed to init completion queue table.\n");
692 		goto err_mr_table_free;
693 	}
694 
695 	ret = hns_roce_init_qp_table(hr_dev);
696 	if (ret) {
697 		dev_err(dev, "Failed to init queue pair table.\n");
698 		goto err_cq_table_free;
699 	}
700 
701 	return 0;
702 
703 err_cq_table_free:
704 	hns_roce_cleanup_cq_table(hr_dev);
705 
706 err_mr_table_free:
707 	hns_roce_cleanup_mr_table(hr_dev);
708 
709 err_pd_table_free:
710 	hns_roce_cleanup_pd_table(hr_dev);
711 
712 err_uar_alloc_free:
713 	hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
714 
715 err_uar_table_free:
716 	hns_roce_cleanup_uar_table(hr_dev);
717 	return ret;
718 }
719 
720 int hns_roce_init(struct hns_roce_dev *hr_dev)
721 {
722 	int ret;
723 	struct device *dev = hr_dev->dev;
724 
725 	if (hr_dev->hw->reset) {
726 		ret = hr_dev->hw->reset(hr_dev, true);
727 		if (ret) {
728 			dev_err(dev, "Reset RoCE engine failed!\n");
729 			return ret;
730 		}
731 	}
732 
733 	if (hr_dev->hw->cmq_init) {
734 		ret = hr_dev->hw->cmq_init(hr_dev);
735 		if (ret) {
736 			dev_err(dev, "Init RoCE Command Queue failed!\n");
737 			goto error_failed_cmq_init;
738 		}
739 	}
740 
741 	ret = hr_dev->hw->hw_profile(hr_dev);
742 	if (ret) {
743 		dev_err(dev, "Get RoCE engine profile failed!\n");
744 		goto error_failed_cmd_init;
745 	}
746 
747 	ret = hns_roce_cmd_init(hr_dev);
748 	if (ret) {
749 		dev_err(dev, "cmd init failed!\n");
750 		goto error_failed_cmd_init;
751 	}
752 
753 	ret = hr_dev->hw->init_eq(hr_dev);
754 	if (ret) {
755 		dev_err(dev, "eq init failed!\n");
756 		goto error_failed_eq_table;
757 	}
758 
759 	if (hr_dev->cmd_mod) {
760 		ret = hns_roce_cmd_use_events(hr_dev);
761 		if (ret) {
762 			dev_err(dev, "Switch to event-driven cmd failed!\n");
763 			goto error_failed_use_event;
764 		}
765 	}
766 
767 	ret = hns_roce_init_hem(hr_dev);
768 	if (ret) {
769 		dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
770 		goto error_failed_init_hem;
771 	}
772 
773 	ret = hns_roce_setup_hca(hr_dev);
774 	if (ret) {
775 		dev_err(dev, "setup hca failed!\n");
776 		goto error_failed_setup_hca;
777 	}
778 
779 	if (hr_dev->hw->hw_init) {
780 		ret = hr_dev->hw->hw_init(hr_dev);
781 		if (ret) {
782 			dev_err(dev, "hw_init failed!\n");
783 			goto error_failed_engine_init;
784 		}
785 	}
786 
787 	ret = hns_roce_register_device(hr_dev);
788 	if (ret)
789 		goto error_failed_register_device;
790 
791 	return 0;
792 
793 error_failed_register_device:
794 	if (hr_dev->hw->hw_exit)
795 		hr_dev->hw->hw_exit(hr_dev);
796 
797 error_failed_engine_init:
798 	hns_roce_cleanup_bitmap(hr_dev);
799 
800 error_failed_setup_hca:
801 	hns_roce_cleanup_hem(hr_dev);
802 
803 error_failed_init_hem:
804 	if (hr_dev->cmd_mod)
805 		hns_roce_cmd_use_polling(hr_dev);
806 
807 error_failed_use_event:
808 	hr_dev->hw->cleanup_eq(hr_dev);
809 
810 error_failed_eq_table:
811 	hns_roce_cmd_cleanup(hr_dev);
812 
813 error_failed_cmd_init:
814 	if (hr_dev->hw->cmq_exit)
815 		hr_dev->hw->cmq_exit(hr_dev);
816 
817 error_failed_cmq_init:
818 	if (hr_dev->hw->reset) {
819 		ret = hr_dev->hw->reset(hr_dev, false);
820 		if (ret)
821 			dev_err(dev, "Dereset RoCE engine failed!\n");
822 	}
823 
824 	return ret;
825 }
826 EXPORT_SYMBOL_GPL(hns_roce_init);
827 
828 void hns_roce_exit(struct hns_roce_dev *hr_dev)
829 {
830 	hns_roce_unregister_device(hr_dev);
831 	if (hr_dev->hw->hw_exit)
832 		hr_dev->hw->hw_exit(hr_dev);
833 	hns_roce_cleanup_bitmap(hr_dev);
834 	hns_roce_cleanup_hem(hr_dev);
835 
836 	if (hr_dev->cmd_mod)
837 		hns_roce_cmd_use_polling(hr_dev);
838 
839 	hr_dev->hw->cleanup_eq(hr_dev);
840 	hns_roce_cmd_cleanup(hr_dev);
841 	if (hr_dev->hw->cmq_exit)
842 		hr_dev->hw->cmq_exit(hr_dev);
843 	if (hr_dev->hw->reset)
844 		hr_dev->hw->reset(hr_dev, false);
845 }
846 EXPORT_SYMBOL_GPL(hns_roce_exit);
847 
848 MODULE_LICENSE("Dual BSD/GPL");
849 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
850 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
851 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
852 MODULE_DESCRIPTION("HNS RoCE Driver");
853