1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 EXPORT_SYMBOL_GPL(hns_get_gid_index); 61 62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 63 { 64 u8 phy_port; 65 u32 i = 0; 66 67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM)) 68 return 0; 69 70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++) 71 hr_dev->dev_addr[port][i] = addr[i]; 72 73 phy_port = hr_dev->iboe.phy_port[port]; 74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 75 } 76 77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u8 port = attr->port_num - 1; 81 unsigned long flags; 82 int ret; 83 84 if (port >= hr_dev->caps.num_ports) 85 return -EINVAL; 86 87 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 88 89 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 90 91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 92 93 return ret; 94 } 95 96 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 97 { 98 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 99 struct ib_gid_attr zattr = { }; 100 u8 port = attr->port_num - 1; 101 unsigned long flags; 102 int ret; 103 104 if (port >= hr_dev->caps.num_ports) 105 return -EINVAL; 106 107 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 108 109 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 110 111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 112 113 return ret; 114 } 115 116 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 117 unsigned long event) 118 { 119 struct device *dev = hr_dev->dev; 120 struct net_device *netdev; 121 int ret = 0; 122 123 netdev = hr_dev->iboe.netdevs[port]; 124 if (!netdev) { 125 dev_err(dev, "port(%d) can't find netdev\n", port); 126 return -ENODEV; 127 } 128 129 switch (event) { 130 case NETDEV_UP: 131 case NETDEV_CHANGE: 132 case NETDEV_REGISTER: 133 case NETDEV_CHANGEADDR: 134 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 135 break; 136 case NETDEV_DOWN: 137 /* 138 * In v1 engine, only support all ports closed together. 139 */ 140 break; 141 default: 142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 143 break; 144 } 145 146 return ret; 147 } 148 149 static int hns_roce_netdev_event(struct notifier_block *self, 150 unsigned long event, void *ptr) 151 { 152 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 153 struct hns_roce_ib_iboe *iboe = NULL; 154 struct hns_roce_dev *hr_dev = NULL; 155 u8 port = 0; 156 int ret = 0; 157 158 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 159 iboe = &hr_dev->iboe; 160 161 for (port = 0; port < hr_dev->caps.num_ports; port++) { 162 if (dev == iboe->netdevs[port]) { 163 ret = handle_en_event(hr_dev, port, event); 164 if (ret) 165 return NOTIFY_DONE; 166 break; 167 } 168 } 169 170 return NOTIFY_DONE; 171 } 172 173 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 174 { 175 int ret; 176 u8 i; 177 178 for (i = 0; i < hr_dev->caps.num_ports; i++) { 179 if (hr_dev->hw->set_mtu) 180 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 181 hr_dev->caps.max_mtu); 182 ret = hns_roce_set_mac(hr_dev, i, 183 hr_dev->iboe.netdevs[i]->dev_addr); 184 if (ret) 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int hns_roce_query_device(struct ib_device *ib_dev, 192 struct ib_device_attr *props, 193 struct ib_udata *uhw) 194 { 195 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 196 197 memset(props, 0, sizeof(*props)); 198 199 props->fw_ver = hr_dev->caps.fw_ver; 200 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 201 props->max_mr_size = (u64)(~(0ULL)); 202 props->page_size_cap = hr_dev->caps.page_size_cap; 203 props->vendor_id = hr_dev->vendor_id; 204 props->vendor_part_id = hr_dev->vendor_part_id; 205 props->hw_ver = hr_dev->hw_rev; 206 props->max_qp = hr_dev->caps.num_qps; 207 props->max_qp_wr = hr_dev->caps.max_wqes; 208 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 209 IB_DEVICE_RC_RNR_NAK_GEN; 210 props->max_send_sge = hr_dev->caps.max_sq_sg; 211 props->max_recv_sge = hr_dev->caps.max_rq_sg; 212 props->max_sge_rd = 1; 213 props->max_cq = hr_dev->caps.num_cqs; 214 props->max_cqe = hr_dev->caps.max_cqes; 215 props->max_mr = hr_dev->caps.num_mtpts; 216 props->max_pd = hr_dev->caps.num_pds; 217 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 218 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 219 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 220 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 221 props->max_pkeys = 1; 222 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 223 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 224 props->max_srq = hr_dev->caps.max_srqs; 225 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 226 props->max_srq_sge = hr_dev->caps.max_srq_sges; 227 } 228 229 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { 230 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 231 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 232 } 233 234 return 0; 235 } 236 237 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev, 238 u8 port_num) 239 { 240 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 241 struct net_device *ndev; 242 243 if (port_num < 1 || port_num > hr_dev->caps.num_ports) 244 return NULL; 245 246 rcu_read_lock(); 247 248 ndev = hr_dev->iboe.netdevs[port_num - 1]; 249 if (ndev) 250 dev_hold(ndev); 251 252 rcu_read_unlock(); 253 return ndev; 254 } 255 256 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 257 struct ib_port_attr *props) 258 { 259 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 260 struct device *dev = hr_dev->dev; 261 struct net_device *net_dev; 262 unsigned long flags; 263 enum ib_mtu mtu; 264 u8 port; 265 266 assert(port_num > 0); 267 port = port_num - 1; 268 269 /* props being zeroed by the caller, avoid zeroing it here */ 270 271 props->max_mtu = hr_dev->caps.max_mtu; 272 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 273 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 274 IB_PORT_VENDOR_CLASS_SUP | 275 IB_PORT_BOOT_MGMT_SUP; 276 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 277 props->pkey_tbl_len = 1; 278 props->active_width = IB_WIDTH_4X; 279 props->active_speed = 1; 280 281 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 282 283 net_dev = hr_dev->iboe.netdevs[port]; 284 if (!net_dev) { 285 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 286 dev_err(dev, "find netdev %d failed!\r\n", port); 287 return -EINVAL; 288 } 289 290 mtu = iboe_get_mtu(net_dev->mtu); 291 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 292 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 293 IB_PORT_ACTIVE : IB_PORT_DOWN; 294 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3; 295 296 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 297 298 return 0; 299 } 300 301 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 302 u8 port_num) 303 { 304 return IB_LINK_LAYER_ETHERNET; 305 } 306 307 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 308 u16 *pkey) 309 { 310 *pkey = PKEY_ID; 311 312 return 0; 313 } 314 315 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 316 struct ib_device_modify *props) 317 { 318 unsigned long flags; 319 320 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 321 return -EOPNOTSUPP; 322 323 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 324 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 325 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 326 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 327 } 328 329 return 0; 330 } 331 332 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, 333 struct ib_port_modify *props) 334 { 335 return 0; 336 } 337 338 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 339 struct ib_udata *udata) 340 { 341 int ret = 0; 342 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 343 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 344 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 345 346 if (!hr_dev->active) 347 return -EAGAIN; 348 349 resp.qp_tab_size = hr_dev->caps.num_qps; 350 351 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 352 if (ret) 353 goto error_fail_uar_alloc; 354 355 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 356 INIT_LIST_HEAD(&context->page_list); 357 mutex_init(&context->page_mutex); 358 } 359 360 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 361 if (ret) 362 goto error_fail_copy_to_udata; 363 364 return 0; 365 366 error_fail_copy_to_udata: 367 hns_roce_uar_free(hr_dev, &context->uar); 368 369 error_fail_uar_alloc: 370 return ret; 371 } 372 373 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 374 { 375 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 376 377 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 378 } 379 380 static int hns_roce_mmap(struct ib_ucontext *context, 381 struct vm_area_struct *vma) 382 { 383 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 384 385 switch (vma->vm_pgoff) { 386 case 0: 387 return rdma_user_mmap_io(context, vma, 388 to_hr_ucontext(context)->uar.pfn, 389 PAGE_SIZE, 390 pgprot_noncached(vma->vm_page_prot)); 391 392 /* vm_pgoff: 1 -- TPTR */ 393 case 1: 394 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 395 return -EINVAL; 396 /* 397 * FIXME: using io_remap_pfn_range on the dma address returned 398 * by dma_alloc_coherent is totally wrong. 399 */ 400 return rdma_user_mmap_io(context, vma, 401 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 402 hr_dev->tptr_size, 403 vma->vm_page_prot); 404 405 default: 406 return -EINVAL; 407 } 408 } 409 410 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 411 struct ib_port_immutable *immutable) 412 { 413 struct ib_port_attr attr; 414 int ret; 415 416 ret = ib_query_port(ib_dev, port_num, &attr); 417 if (ret) 418 return ret; 419 420 immutable->pkey_tbl_len = attr.pkey_tbl_len; 421 immutable->gid_tbl_len = attr.gid_tbl_len; 422 423 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 424 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 425 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 426 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 427 428 return 0; 429 } 430 431 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 432 { 433 } 434 435 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 436 { 437 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 438 439 hr_dev->active = false; 440 unregister_netdevice_notifier(&iboe->nb); 441 ib_unregister_device(&hr_dev->ib_dev); 442 } 443 444 static const struct ib_device_ops hns_roce_dev_ops = { 445 .add_gid = hns_roce_add_gid, 446 .alloc_pd = hns_roce_alloc_pd, 447 .alloc_ucontext = hns_roce_alloc_ucontext, 448 .create_ah = hns_roce_create_ah, 449 .create_cq = hns_roce_ib_create_cq, 450 .create_qp = hns_roce_create_qp, 451 .dealloc_pd = hns_roce_dealloc_pd, 452 .dealloc_ucontext = hns_roce_dealloc_ucontext, 453 .del_gid = hns_roce_del_gid, 454 .dereg_mr = hns_roce_dereg_mr, 455 .destroy_ah = hns_roce_destroy_ah, 456 .destroy_cq = hns_roce_ib_destroy_cq, 457 .disassociate_ucontext = hns_roce_disassociate_ucontext, 458 .get_dma_mr = hns_roce_get_dma_mr, 459 .get_link_layer = hns_roce_get_link_layer, 460 .get_netdev = hns_roce_get_netdev, 461 .get_port_immutable = hns_roce_port_immutable, 462 .mmap = hns_roce_mmap, 463 .modify_device = hns_roce_modify_device, 464 .modify_port = hns_roce_modify_port, 465 .modify_qp = hns_roce_modify_qp, 466 .query_ah = hns_roce_query_ah, 467 .query_device = hns_roce_query_device, 468 .query_pkey = hns_roce_query_pkey, 469 .query_port = hns_roce_query_port, 470 .reg_user_mr = hns_roce_reg_user_mr, 471 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 472 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 473 }; 474 475 static const struct ib_device_ops hns_roce_dev_mr_ops = { 476 .rereg_user_mr = hns_roce_rereg_user_mr, 477 }; 478 479 static const struct ib_device_ops hns_roce_dev_mw_ops = { 480 .alloc_mw = hns_roce_alloc_mw, 481 .dealloc_mw = hns_roce_dealloc_mw, 482 }; 483 484 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 485 .alloc_mr = hns_roce_alloc_mr, 486 .map_mr_sg = hns_roce_map_mr_sg, 487 }; 488 489 static const struct ib_device_ops hns_roce_dev_srq_ops = { 490 .create_srq = hns_roce_create_srq, 491 .destroy_srq = hns_roce_destroy_srq, 492 }; 493 494 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 495 { 496 int ret; 497 struct hns_roce_ib_iboe *iboe = NULL; 498 struct ib_device *ib_dev = NULL; 499 struct device *dev = hr_dev->dev; 500 501 iboe = &hr_dev->iboe; 502 spin_lock_init(&iboe->lock); 503 504 ib_dev = &hr_dev->ib_dev; 505 506 ib_dev->owner = THIS_MODULE; 507 ib_dev->node_type = RDMA_NODE_IB_CA; 508 ib_dev->dev.parent = dev; 509 510 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 511 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 512 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 513 ib_dev->uverbs_abi_ver = 1; 514 ib_dev->uverbs_cmd_mask = 515 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 516 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 517 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 518 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 519 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 520 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 521 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 522 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 523 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 524 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 525 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 526 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 527 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 528 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 529 530 ib_dev->uverbs_ex_cmd_mask |= 531 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 532 533 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 534 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 535 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 536 } 537 538 /* MW */ 539 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 540 ib_dev->uverbs_cmd_mask |= 541 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 542 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 543 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 544 } 545 546 /* FRMR */ 547 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 548 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 549 550 /* SRQ */ 551 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 552 ib_dev->uverbs_cmd_mask |= 553 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | 554 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | 555 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | 556 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | 557 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV); 558 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 559 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 560 } 561 562 ib_dev->driver_id = RDMA_DRIVER_HNS; 563 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 564 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 565 ret = ib_register_device(ib_dev, "hns_%d"); 566 if (ret) { 567 dev_err(dev, "ib_register_device failed!\n"); 568 return ret; 569 } 570 571 ret = hns_roce_setup_mtu_mac(hr_dev); 572 if (ret) { 573 dev_err(dev, "setup_mtu_mac failed!\n"); 574 goto error_failed_setup_mtu_mac; 575 } 576 577 iboe->nb.notifier_call = hns_roce_netdev_event; 578 ret = register_netdevice_notifier(&iboe->nb); 579 if (ret) { 580 dev_err(dev, "register_netdevice_notifier failed!\n"); 581 goto error_failed_setup_mtu_mac; 582 } 583 584 hr_dev->active = true; 585 return 0; 586 587 error_failed_setup_mtu_mac: 588 ib_unregister_device(ib_dev); 589 590 return ret; 591 } 592 593 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 594 { 595 int ret; 596 struct device *dev = hr_dev->dev; 597 598 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 599 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 600 hr_dev->caps.num_mtt_segs, 1); 601 if (ret) { 602 dev_err(dev, "Failed to init MTT context memory, aborting.\n"); 603 return ret; 604 } 605 606 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { 607 ret = hns_roce_init_hem_table(hr_dev, 608 &hr_dev->mr_table.mtt_cqe_table, 609 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz, 610 hr_dev->caps.num_cqe_segs, 1); 611 if (ret) { 612 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n"); 613 goto err_unmap_cqe; 614 } 615 } 616 617 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 618 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 619 hr_dev->caps.num_mtpts, 1); 620 if (ret) { 621 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 622 goto err_unmap_mtt; 623 } 624 625 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 626 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz, 627 hr_dev->caps.num_qps, 1); 628 if (ret) { 629 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 630 goto err_unmap_dmpt; 631 } 632 633 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 634 HEM_TYPE_IRRL, 635 hr_dev->caps.irrl_entry_sz * 636 hr_dev->caps.max_qp_init_rdma, 637 hr_dev->caps.num_qps, 1); 638 if (ret) { 639 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 640 goto err_unmap_qp; 641 } 642 643 if (hr_dev->caps.trrl_entry_sz) { 644 ret = hns_roce_init_hem_table(hr_dev, 645 &hr_dev->qp_table.trrl_table, 646 HEM_TYPE_TRRL, 647 hr_dev->caps.trrl_entry_sz * 648 hr_dev->caps.max_qp_dest_rdma, 649 hr_dev->caps.num_qps, 1); 650 if (ret) { 651 dev_err(dev, 652 "Failed to init trrl_table memory, aborting.\n"); 653 goto err_unmap_irrl; 654 } 655 } 656 657 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 658 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 659 hr_dev->caps.num_cqs, 1); 660 if (ret) { 661 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 662 goto err_unmap_trrl; 663 } 664 665 if (hr_dev->caps.srqc_entry_sz) { 666 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 667 HEM_TYPE_SRQC, 668 hr_dev->caps.srqc_entry_sz, 669 hr_dev->caps.num_srqs, 1); 670 if (ret) { 671 dev_err(dev, 672 "Failed to init SRQ context memory, aborting.\n"); 673 goto err_unmap_cq; 674 } 675 } 676 677 if (hr_dev->caps.num_srqwqe_segs) { 678 ret = hns_roce_init_hem_table(hr_dev, 679 &hr_dev->mr_table.mtt_srqwqe_table, 680 HEM_TYPE_SRQWQE, 681 hr_dev->caps.mtt_entry_sz, 682 hr_dev->caps.num_srqwqe_segs, 1); 683 if (ret) { 684 dev_err(dev, 685 "Failed to init MTT srqwqe memory, aborting.\n"); 686 goto err_unmap_srq; 687 } 688 } 689 690 if (hr_dev->caps.num_idx_segs) { 691 ret = hns_roce_init_hem_table(hr_dev, 692 &hr_dev->mr_table.mtt_idx_table, 693 HEM_TYPE_IDX, 694 hr_dev->caps.idx_entry_sz, 695 hr_dev->caps.num_idx_segs, 1); 696 if (ret) { 697 dev_err(dev, 698 "Failed to init MTT idx memory, aborting.\n"); 699 goto err_unmap_srqwqe; 700 } 701 } 702 703 if (hr_dev->caps.sccc_entry_sz) { 704 ret = hns_roce_init_hem_table(hr_dev, 705 &hr_dev->qp_table.sccc_table, 706 HEM_TYPE_SCCC, 707 hr_dev->caps.sccc_entry_sz, 708 hr_dev->caps.num_qps, 1); 709 if (ret) { 710 dev_err(dev, 711 "Failed to init SCC context memory, aborting.\n"); 712 goto err_unmap_idx; 713 } 714 } 715 716 if (hr_dev->caps.qpc_timer_entry_sz) { 717 ret = hns_roce_init_hem_table(hr_dev, 718 &hr_dev->qpc_timer_table, 719 HEM_TYPE_QPC_TIMER, 720 hr_dev->caps.qpc_timer_entry_sz, 721 hr_dev->caps.num_qpc_timer, 1); 722 if (ret) { 723 dev_err(dev, 724 "Failed to init QPC timer memory, aborting.\n"); 725 goto err_unmap_ctx; 726 } 727 } 728 729 if (hr_dev->caps.cqc_timer_entry_sz) { 730 ret = hns_roce_init_hem_table(hr_dev, 731 &hr_dev->cqc_timer_table, 732 HEM_TYPE_CQC_TIMER, 733 hr_dev->caps.cqc_timer_entry_sz, 734 hr_dev->caps.num_cqc_timer, 1); 735 if (ret) { 736 dev_err(dev, 737 "Failed to init CQC timer memory, aborting.\n"); 738 goto err_unmap_qpc_timer; 739 } 740 } 741 742 return 0; 743 744 err_unmap_qpc_timer: 745 if (hr_dev->caps.qpc_timer_entry_sz) 746 hns_roce_cleanup_hem_table(hr_dev, 747 &hr_dev->qpc_timer_table); 748 749 err_unmap_ctx: 750 if (hr_dev->caps.sccc_entry_sz) 751 hns_roce_cleanup_hem_table(hr_dev, 752 &hr_dev->qp_table.sccc_table); 753 754 err_unmap_idx: 755 if (hr_dev->caps.num_idx_segs) 756 hns_roce_cleanup_hem_table(hr_dev, 757 &hr_dev->mr_table.mtt_idx_table); 758 759 err_unmap_srqwqe: 760 if (hr_dev->caps.num_srqwqe_segs) 761 hns_roce_cleanup_hem_table(hr_dev, 762 &hr_dev->mr_table.mtt_srqwqe_table); 763 764 err_unmap_srq: 765 if (hr_dev->caps.srqc_entry_sz) 766 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 767 768 err_unmap_cq: 769 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 770 771 err_unmap_trrl: 772 if (hr_dev->caps.trrl_entry_sz) 773 hns_roce_cleanup_hem_table(hr_dev, 774 &hr_dev->qp_table.trrl_table); 775 776 err_unmap_irrl: 777 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 778 779 err_unmap_qp: 780 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 781 782 err_unmap_dmpt: 783 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 784 785 err_unmap_mtt: 786 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 787 hns_roce_cleanup_hem_table(hr_dev, 788 &hr_dev->mr_table.mtt_cqe_table); 789 790 err_unmap_cqe: 791 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 792 793 return ret; 794 } 795 796 /** 797 * hns_roce_setup_hca - setup host channel adapter 798 * @hr_dev: pointer to hns roce device 799 * Return : int 800 */ 801 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 802 { 803 int ret; 804 struct device *dev = hr_dev->dev; 805 806 spin_lock_init(&hr_dev->sm_lock); 807 spin_lock_init(&hr_dev->bt_cmd_lock); 808 809 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 810 INIT_LIST_HEAD(&hr_dev->pgdir_list); 811 mutex_init(&hr_dev->pgdir_mutex); 812 } 813 814 ret = hns_roce_init_uar_table(hr_dev); 815 if (ret) { 816 dev_err(dev, "Failed to initialize uar table. aborting\n"); 817 return ret; 818 } 819 820 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 821 if (ret) { 822 dev_err(dev, "Failed to allocate priv_uar.\n"); 823 goto err_uar_table_free; 824 } 825 826 ret = hns_roce_init_pd_table(hr_dev); 827 if (ret) { 828 dev_err(dev, "Failed to init protected domain table.\n"); 829 goto err_uar_alloc_free; 830 } 831 832 ret = hns_roce_init_mr_table(hr_dev); 833 if (ret) { 834 dev_err(dev, "Failed to init memory region table.\n"); 835 goto err_pd_table_free; 836 } 837 838 ret = hns_roce_init_cq_table(hr_dev); 839 if (ret) { 840 dev_err(dev, "Failed to init completion queue table.\n"); 841 goto err_mr_table_free; 842 } 843 844 ret = hns_roce_init_qp_table(hr_dev); 845 if (ret) { 846 dev_err(dev, "Failed to init queue pair table.\n"); 847 goto err_cq_table_free; 848 } 849 850 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 851 ret = hns_roce_init_srq_table(hr_dev); 852 if (ret) { 853 dev_err(dev, 854 "Failed to init share receive queue table.\n"); 855 goto err_qp_table_free; 856 } 857 } 858 859 return 0; 860 861 err_qp_table_free: 862 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 863 hns_roce_cleanup_qp_table(hr_dev); 864 865 err_cq_table_free: 866 hns_roce_cleanup_cq_table(hr_dev); 867 868 err_mr_table_free: 869 hns_roce_cleanup_mr_table(hr_dev); 870 871 err_pd_table_free: 872 hns_roce_cleanup_pd_table(hr_dev); 873 874 err_uar_alloc_free: 875 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 876 877 err_uar_table_free: 878 hns_roce_cleanup_uar_table(hr_dev); 879 return ret; 880 } 881 882 int hns_roce_init(struct hns_roce_dev *hr_dev) 883 { 884 int ret; 885 struct device *dev = hr_dev->dev; 886 887 if (hr_dev->hw->reset) { 888 ret = hr_dev->hw->reset(hr_dev, true); 889 if (ret) { 890 dev_err(dev, "Reset RoCE engine failed!\n"); 891 return ret; 892 } 893 } 894 hr_dev->is_reset = false; 895 896 if (hr_dev->hw->cmq_init) { 897 ret = hr_dev->hw->cmq_init(hr_dev); 898 if (ret) { 899 dev_err(dev, "Init RoCE Command Queue failed!\n"); 900 goto error_failed_cmq_init; 901 } 902 } 903 904 ret = hr_dev->hw->hw_profile(hr_dev); 905 if (ret) { 906 dev_err(dev, "Get RoCE engine profile failed!\n"); 907 goto error_failed_cmd_init; 908 } 909 910 ret = hns_roce_cmd_init(hr_dev); 911 if (ret) { 912 dev_err(dev, "cmd init failed!\n"); 913 goto error_failed_cmd_init; 914 } 915 916 ret = hr_dev->hw->init_eq(hr_dev); 917 if (ret) { 918 dev_err(dev, "eq init failed!\n"); 919 goto error_failed_eq_table; 920 } 921 922 if (hr_dev->cmd_mod) { 923 ret = hns_roce_cmd_use_events(hr_dev); 924 if (ret) { 925 dev_err(dev, "Switch to event-driven cmd failed!\n"); 926 goto error_failed_use_event; 927 } 928 } 929 930 ret = hns_roce_init_hem(hr_dev); 931 if (ret) { 932 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 933 goto error_failed_init_hem; 934 } 935 936 ret = hns_roce_setup_hca(hr_dev); 937 if (ret) { 938 dev_err(dev, "setup hca failed!\n"); 939 goto error_failed_setup_hca; 940 } 941 942 if (hr_dev->hw->hw_init) { 943 ret = hr_dev->hw->hw_init(hr_dev); 944 if (ret) { 945 dev_err(dev, "hw_init failed!\n"); 946 goto error_failed_engine_init; 947 } 948 } 949 950 ret = hns_roce_register_device(hr_dev); 951 if (ret) 952 goto error_failed_register_device; 953 954 return 0; 955 956 error_failed_register_device: 957 if (hr_dev->hw->hw_exit) 958 hr_dev->hw->hw_exit(hr_dev); 959 960 error_failed_engine_init: 961 hns_roce_cleanup_bitmap(hr_dev); 962 963 error_failed_setup_hca: 964 hns_roce_cleanup_hem(hr_dev); 965 966 error_failed_init_hem: 967 if (hr_dev->cmd_mod) 968 hns_roce_cmd_use_polling(hr_dev); 969 970 error_failed_use_event: 971 hr_dev->hw->cleanup_eq(hr_dev); 972 973 error_failed_eq_table: 974 hns_roce_cmd_cleanup(hr_dev); 975 976 error_failed_cmd_init: 977 if (hr_dev->hw->cmq_exit) 978 hr_dev->hw->cmq_exit(hr_dev); 979 980 error_failed_cmq_init: 981 if (hr_dev->hw->reset) { 982 if (hr_dev->hw->reset(hr_dev, false)) 983 dev_err(dev, "Dereset RoCE engine failed!\n"); 984 } 985 986 return ret; 987 } 988 EXPORT_SYMBOL_GPL(hns_roce_init); 989 990 void hns_roce_exit(struct hns_roce_dev *hr_dev) 991 { 992 hns_roce_unregister_device(hr_dev); 993 994 if (hr_dev->hw->hw_exit) 995 hr_dev->hw->hw_exit(hr_dev); 996 hns_roce_cleanup_bitmap(hr_dev); 997 hns_roce_cleanup_hem(hr_dev); 998 999 if (hr_dev->cmd_mod) 1000 hns_roce_cmd_use_polling(hr_dev); 1001 1002 hr_dev->hw->cleanup_eq(hr_dev); 1003 hns_roce_cmd_cleanup(hr_dev); 1004 if (hr_dev->hw->cmq_exit) 1005 hr_dev->hw->cmq_exit(hr_dev); 1006 if (hr_dev->hw->reset) 1007 hr_dev->hw->reset(hr_dev, false); 1008 } 1009 EXPORT_SYMBOL_GPL(hns_roce_exit); 1010 1011 MODULE_LICENSE("Dual BSD/GPL"); 1012 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 1013 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1014 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1015 MODULE_DESCRIPTION("HNS RoCE Driver"); 1016