1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include "hns_roce_hem.h" 43 44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, 45 const u8 *addr) 46 { 47 u8 phy_port; 48 u32 i; 49 50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 51 return 0; 52 53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 54 return 0; 55 56 for (i = 0; i < ETH_ALEN; i++) 57 hr_dev->dev_addr[port][i] = addr[i]; 58 59 phy_port = hr_dev->iboe.phy_port[port]; 60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 61 } 62 63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 64 { 65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 66 u32 port = attr->port_num - 1; 67 int ret; 68 69 if (port >= hr_dev->caps.num_ports) 70 return -EINVAL; 71 72 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr); 73 74 return ret; 75 } 76 77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u32 port = attr->port_num - 1; 81 int ret; 82 83 if (port >= hr_dev->caps.num_ports) 84 return -EINVAL; 85 86 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL); 87 88 return ret; 89 } 90 91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port, 92 unsigned long event) 93 { 94 struct device *dev = hr_dev->dev; 95 struct net_device *netdev; 96 int ret = 0; 97 98 netdev = hr_dev->iboe.netdevs[port]; 99 if (!netdev) { 100 dev_err(dev, "can't find netdev on port(%u)!\n", port); 101 return -ENODEV; 102 } 103 104 switch (event) { 105 case NETDEV_UP: 106 case NETDEV_CHANGE: 107 case NETDEV_REGISTER: 108 case NETDEV_CHANGEADDR: 109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 110 break; 111 case NETDEV_DOWN: 112 /* 113 * In v1 engine, only support all ports closed together. 114 */ 115 break; 116 default: 117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 118 break; 119 } 120 121 return ret; 122 } 123 124 static int hns_roce_netdev_event(struct notifier_block *self, 125 unsigned long event, void *ptr) 126 { 127 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 128 struct hns_roce_ib_iboe *iboe = NULL; 129 struct hns_roce_dev *hr_dev = NULL; 130 int ret; 131 u32 port; 132 133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 134 iboe = &hr_dev->iboe; 135 136 for (port = 0; port < hr_dev->caps.num_ports; port++) { 137 if (dev == iboe->netdevs[port]) { 138 ret = handle_en_event(hr_dev, port, event); 139 if (ret) 140 return NOTIFY_DONE; 141 break; 142 } 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 149 { 150 int ret; 151 u8 i; 152 153 for (i = 0; i < hr_dev->caps.num_ports; i++) { 154 ret = hns_roce_set_mac(hr_dev, i, 155 hr_dev->iboe.netdevs[i]->dev_addr); 156 if (ret) 157 return ret; 158 } 159 160 return 0; 161 } 162 163 static int hns_roce_query_device(struct ib_device *ib_dev, 164 struct ib_device_attr *props, 165 struct ib_udata *uhw) 166 { 167 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 168 169 memset(props, 0, sizeof(*props)); 170 171 props->fw_ver = hr_dev->caps.fw_ver; 172 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 173 props->max_mr_size = (u64)(~(0ULL)); 174 props->page_size_cap = hr_dev->caps.page_size_cap; 175 props->vendor_id = hr_dev->vendor_id; 176 props->vendor_part_id = hr_dev->vendor_part_id; 177 props->hw_ver = hr_dev->hw_rev; 178 props->max_qp = hr_dev->caps.num_qps; 179 props->max_qp_wr = hr_dev->caps.max_wqes; 180 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 181 IB_DEVICE_RC_RNR_NAK_GEN; 182 props->max_send_sge = hr_dev->caps.max_sq_sg; 183 props->max_recv_sge = hr_dev->caps.max_rq_sg; 184 props->max_sge_rd = 1; 185 props->max_cq = hr_dev->caps.num_cqs; 186 props->max_cqe = hr_dev->caps.max_cqes; 187 props->max_mr = hr_dev->caps.num_mtpts; 188 props->max_pd = hr_dev->caps.num_pds; 189 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 190 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 191 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 192 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 193 props->max_pkeys = 1; 194 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 195 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 196 props->max_srq = hr_dev->caps.num_srqs; 197 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 198 props->max_srq_sge = hr_dev->caps.max_srq_sges; 199 } 200 201 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && 202 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 203 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 204 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 205 } 206 207 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 208 props->device_cap_flags |= IB_DEVICE_XRC; 209 210 return 0; 211 } 212 213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num, 214 struct ib_port_attr *props) 215 { 216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 217 struct device *dev = hr_dev->dev; 218 struct net_device *net_dev; 219 unsigned long flags; 220 enum ib_mtu mtu; 221 u32 port; 222 223 port = port_num - 1; 224 225 /* props being zeroed by the caller, avoid zeroing it here */ 226 227 props->max_mtu = hr_dev->caps.max_mtu; 228 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 229 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 230 IB_PORT_VENDOR_CLASS_SUP | 231 IB_PORT_BOOT_MGMT_SUP; 232 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 233 props->pkey_tbl_len = 1; 234 props->active_width = IB_WIDTH_4X; 235 props->active_speed = 1; 236 237 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 238 239 net_dev = hr_dev->iboe.netdevs[port]; 240 if (!net_dev) { 241 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 242 dev_err(dev, "find netdev %u failed!\n", port); 243 return -EINVAL; 244 } 245 246 mtu = iboe_get_mtu(net_dev->mtu); 247 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 248 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 249 IB_PORT_ACTIVE : 250 IB_PORT_DOWN; 251 props->phys_state = props->state == IB_PORT_ACTIVE ? 252 IB_PORT_PHYS_STATE_LINK_UP : 253 IB_PORT_PHYS_STATE_DISABLED; 254 255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 256 257 return 0; 258 } 259 260 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 261 u32 port_num) 262 { 263 return IB_LINK_LAYER_ETHERNET; 264 } 265 266 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index, 267 u16 *pkey) 268 { 269 if (index > 0) 270 return -EINVAL; 271 272 *pkey = PKEY_ID; 273 274 return 0; 275 } 276 277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 278 struct ib_device_modify *props) 279 { 280 unsigned long flags; 281 282 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 283 return -EOPNOTSUPP; 284 285 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 286 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 287 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 288 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 289 } 290 291 return 0; 292 } 293 294 struct hns_user_mmap_entry * 295 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 296 size_t length, 297 enum hns_roce_mmap_type mmap_type) 298 { 299 struct hns_user_mmap_entry *entry; 300 int ret; 301 302 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 303 if (!entry) 304 return NULL; 305 306 entry->address = address; 307 entry->mmap_type = mmap_type; 308 309 switch (mmap_type) { 310 /* pgoff 0 must be used by DB for compatibility */ 311 case HNS_ROCE_MMAP_TYPE_DB: 312 ret = rdma_user_mmap_entry_insert_exact( 313 ucontext, &entry->rdma_entry, length, 0); 314 break; 315 case HNS_ROCE_MMAP_TYPE_DWQE: 316 ret = rdma_user_mmap_entry_insert_range( 317 ucontext, &entry->rdma_entry, length, 1, 318 U32_MAX); 319 break; 320 default: 321 ret = -EINVAL; 322 break; 323 } 324 325 if (ret) { 326 kfree(entry); 327 return NULL; 328 } 329 330 return entry; 331 } 332 333 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context) 334 { 335 if (context->db_mmap_entry) 336 rdma_user_mmap_entry_remove( 337 &context->db_mmap_entry->rdma_entry); 338 } 339 340 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx) 341 { 342 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 343 u64 address; 344 345 address = context->uar.pfn << PAGE_SHIFT; 346 context->db_mmap_entry = hns_roce_user_mmap_entry_insert( 347 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB); 348 if (!context->db_mmap_entry) 349 return -ENOMEM; 350 351 return 0; 352 } 353 354 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 355 struct ib_udata *udata) 356 { 357 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 358 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 359 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 360 struct hns_roce_ib_alloc_ucontext ucmd = {}; 361 int ret; 362 363 if (!hr_dev->active) 364 return -EAGAIN; 365 366 resp.qp_tab_size = hr_dev->caps.num_qps; 367 resp.srq_tab_size = hr_dev->caps.num_srqs; 368 369 ret = ib_copy_from_udata(&ucmd, udata, 370 min(udata->inlen, sizeof(ucmd))); 371 if (ret) 372 return ret; 373 374 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 375 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS; 376 377 if (context->config & HNS_ROCE_EXSGE_FLAGS) { 378 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS; 379 resp.max_inline_data = hr_dev->caps.max_sq_inline; 380 } 381 382 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 383 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS; 384 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS) 385 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS; 386 } 387 388 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) { 389 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS; 390 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS) 391 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS; 392 } 393 394 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 395 if (ret) 396 goto error_fail_uar_alloc; 397 398 ret = hns_roce_alloc_uar_entry(uctx); 399 if (ret) 400 goto error_fail_uar_entry; 401 402 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 403 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 404 INIT_LIST_HEAD(&context->page_list); 405 mutex_init(&context->page_mutex); 406 } 407 408 resp.cqe_size = hr_dev->caps.cqe_sz; 409 410 ret = ib_copy_to_udata(udata, &resp, 411 min(udata->outlen, sizeof(resp))); 412 if (ret) 413 goto error_fail_copy_to_udata; 414 415 return 0; 416 417 error_fail_copy_to_udata: 418 hns_roce_dealloc_uar_entry(context); 419 420 error_fail_uar_entry: 421 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 422 423 error_fail_uar_alloc: 424 return ret; 425 } 426 427 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 428 { 429 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 430 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device); 431 432 hns_roce_dealloc_uar_entry(context); 433 434 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 435 } 436 437 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma) 438 { 439 struct rdma_user_mmap_entry *rdma_entry; 440 struct hns_user_mmap_entry *entry; 441 phys_addr_t pfn; 442 pgprot_t prot; 443 int ret; 444 445 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff); 446 if (!rdma_entry) 447 return -EINVAL; 448 449 entry = to_hns_mmap(rdma_entry); 450 pfn = entry->address >> PAGE_SHIFT; 451 452 switch (entry->mmap_type) { 453 case HNS_ROCE_MMAP_TYPE_DB: 454 case HNS_ROCE_MMAP_TYPE_DWQE: 455 prot = pgprot_device(vma->vm_page_prot); 456 break; 457 default: 458 ret = -EINVAL; 459 goto out; 460 } 461 462 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE, 463 prot, rdma_entry); 464 465 out: 466 rdma_user_mmap_entry_put(rdma_entry); 467 return ret; 468 } 469 470 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry) 471 { 472 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry); 473 474 kfree(entry); 475 } 476 477 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num, 478 struct ib_port_immutable *immutable) 479 { 480 struct ib_port_attr attr; 481 int ret; 482 483 ret = ib_query_port(ib_dev, port_num, &attr); 484 if (ret) 485 return ret; 486 487 immutable->pkey_tbl_len = attr.pkey_tbl_len; 488 immutable->gid_tbl_len = attr.gid_tbl_len; 489 490 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 491 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 492 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 493 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 494 495 return 0; 496 } 497 498 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 499 { 500 } 501 502 static void hns_roce_get_fw_ver(struct ib_device *device, char *str) 503 { 504 u64 fw_ver = to_hr_dev(device)->caps.fw_ver; 505 unsigned int major, minor, sub_minor; 506 507 major = upper_32_bits(fw_ver); 508 minor = high_16_bits(lower_32_bits(fw_ver)); 509 sub_minor = low_16_bits(fw_ver); 510 511 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor, 512 sub_minor); 513 } 514 515 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 516 { 517 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 518 519 hr_dev->active = false; 520 unregister_netdevice_notifier(&iboe->nb); 521 ib_unregister_device(&hr_dev->ib_dev); 522 } 523 524 static const struct ib_device_ops hns_roce_dev_ops = { 525 .owner = THIS_MODULE, 526 .driver_id = RDMA_DRIVER_HNS, 527 .uverbs_abi_ver = 1, 528 .uverbs_no_driver_id_binding = 1, 529 530 .get_dev_fw_str = hns_roce_get_fw_ver, 531 .add_gid = hns_roce_add_gid, 532 .alloc_pd = hns_roce_alloc_pd, 533 .alloc_ucontext = hns_roce_alloc_ucontext, 534 .create_ah = hns_roce_create_ah, 535 .create_user_ah = hns_roce_create_ah, 536 .create_cq = hns_roce_create_cq, 537 .create_qp = hns_roce_create_qp, 538 .dealloc_pd = hns_roce_dealloc_pd, 539 .dealloc_ucontext = hns_roce_dealloc_ucontext, 540 .del_gid = hns_roce_del_gid, 541 .dereg_mr = hns_roce_dereg_mr, 542 .destroy_ah = hns_roce_destroy_ah, 543 .destroy_cq = hns_roce_destroy_cq, 544 .disassociate_ucontext = hns_roce_disassociate_ucontext, 545 .get_dma_mr = hns_roce_get_dma_mr, 546 .get_link_layer = hns_roce_get_link_layer, 547 .get_port_immutable = hns_roce_port_immutable, 548 .mmap = hns_roce_mmap, 549 .mmap_free = hns_roce_free_mmap, 550 .modify_device = hns_roce_modify_device, 551 .modify_qp = hns_roce_modify_qp, 552 .query_ah = hns_roce_query_ah, 553 .query_device = hns_roce_query_device, 554 .query_pkey = hns_roce_query_pkey, 555 .query_port = hns_roce_query_port, 556 .reg_user_mr = hns_roce_reg_user_mr, 557 558 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 559 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 560 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 561 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp), 562 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 563 }; 564 565 static const struct ib_device_ops hns_roce_dev_mr_ops = { 566 .rereg_user_mr = hns_roce_rereg_user_mr, 567 }; 568 569 static const struct ib_device_ops hns_roce_dev_mw_ops = { 570 .alloc_mw = hns_roce_alloc_mw, 571 .dealloc_mw = hns_roce_dealloc_mw, 572 573 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 574 }; 575 576 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 577 .alloc_mr = hns_roce_alloc_mr, 578 .map_mr_sg = hns_roce_map_mr_sg, 579 }; 580 581 static const struct ib_device_ops hns_roce_dev_srq_ops = { 582 .create_srq = hns_roce_create_srq, 583 .destroy_srq = hns_roce_destroy_srq, 584 585 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 586 }; 587 588 static const struct ib_device_ops hns_roce_dev_xrcd_ops = { 589 .alloc_xrcd = hns_roce_alloc_xrcd, 590 .dealloc_xrcd = hns_roce_dealloc_xrcd, 591 592 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), 593 }; 594 595 static const struct ib_device_ops hns_roce_dev_restrack_ops = { 596 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 597 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw, 598 .fill_res_qp_entry = hns_roce_fill_res_qp_entry, 599 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw, 600 .fill_res_mr_entry = hns_roce_fill_res_mr_entry, 601 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw, 602 }; 603 604 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 605 { 606 int ret; 607 struct hns_roce_ib_iboe *iboe = NULL; 608 struct ib_device *ib_dev = NULL; 609 struct device *dev = hr_dev->dev; 610 unsigned int i; 611 612 iboe = &hr_dev->iboe; 613 spin_lock_init(&iboe->lock); 614 615 ib_dev = &hr_dev->ib_dev; 616 617 ib_dev->node_type = RDMA_NODE_IB_CA; 618 ib_dev->dev.parent = dev; 619 620 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 621 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 622 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 623 624 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) 625 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 626 627 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) 628 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 629 630 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 631 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 632 633 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 634 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 635 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 636 } 637 638 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 639 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); 640 641 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 642 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 643 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops); 644 for (i = 0; i < hr_dev->caps.num_ports; i++) { 645 if (!hr_dev->iboe.netdevs[i]) 646 continue; 647 648 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 649 i + 1); 650 if (ret) 651 return ret; 652 } 653 dma_set_max_seg_size(dev, UINT_MAX); 654 ret = ib_register_device(ib_dev, "hns_%d", dev); 655 if (ret) { 656 dev_err(dev, "ib_register_device failed!\n"); 657 return ret; 658 } 659 660 ret = hns_roce_setup_mtu_mac(hr_dev); 661 if (ret) { 662 dev_err(dev, "setup_mtu_mac failed!\n"); 663 goto error_failed_setup_mtu_mac; 664 } 665 666 iboe->nb.notifier_call = hns_roce_netdev_event; 667 ret = register_netdevice_notifier(&iboe->nb); 668 if (ret) { 669 dev_err(dev, "register_netdevice_notifier failed!\n"); 670 goto error_failed_setup_mtu_mac; 671 } 672 673 hr_dev->active = true; 674 return 0; 675 676 error_failed_setup_mtu_mac: 677 ib_unregister_device(ib_dev); 678 679 return ret; 680 } 681 682 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 683 { 684 struct device *dev = hr_dev->dev; 685 int ret; 686 687 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 688 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 689 hr_dev->caps.num_mtpts); 690 if (ret) { 691 dev_err(dev, "failed to init MTPT context memory, aborting.\n"); 692 return ret; 693 } 694 695 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 696 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 697 hr_dev->caps.num_qps); 698 if (ret) { 699 dev_err(dev, "failed to init QP context memory, aborting.\n"); 700 goto err_unmap_dmpt; 701 } 702 703 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 704 HEM_TYPE_IRRL, 705 hr_dev->caps.irrl_entry_sz * 706 hr_dev->caps.max_qp_init_rdma, 707 hr_dev->caps.num_qps); 708 if (ret) { 709 dev_err(dev, "failed to init irrl_table memory, aborting.\n"); 710 goto err_unmap_qp; 711 } 712 713 if (hr_dev->caps.trrl_entry_sz) { 714 ret = hns_roce_init_hem_table(hr_dev, 715 &hr_dev->qp_table.trrl_table, 716 HEM_TYPE_TRRL, 717 hr_dev->caps.trrl_entry_sz * 718 hr_dev->caps.max_qp_dest_rdma, 719 hr_dev->caps.num_qps); 720 if (ret) { 721 dev_err(dev, 722 "failed to init trrl_table memory, aborting.\n"); 723 goto err_unmap_irrl; 724 } 725 } 726 727 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 728 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 729 hr_dev->caps.num_cqs); 730 if (ret) { 731 dev_err(dev, "failed to init CQ context memory, aborting.\n"); 732 goto err_unmap_trrl; 733 } 734 735 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 736 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 737 HEM_TYPE_SRQC, 738 hr_dev->caps.srqc_entry_sz, 739 hr_dev->caps.num_srqs); 740 if (ret) { 741 dev_err(dev, 742 "failed to init SRQ context memory, aborting.\n"); 743 goto err_unmap_cq; 744 } 745 } 746 747 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 748 ret = hns_roce_init_hem_table(hr_dev, 749 &hr_dev->qp_table.sccc_table, 750 HEM_TYPE_SCCC, 751 hr_dev->caps.sccc_sz, 752 hr_dev->caps.num_qps); 753 if (ret) { 754 dev_err(dev, 755 "failed to init SCC context memory, aborting.\n"); 756 goto err_unmap_srq; 757 } 758 } 759 760 if (hr_dev->caps.qpc_timer_entry_sz) { 761 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 762 HEM_TYPE_QPC_TIMER, 763 hr_dev->caps.qpc_timer_entry_sz, 764 hr_dev->caps.qpc_timer_bt_num); 765 if (ret) { 766 dev_err(dev, 767 "failed to init QPC timer memory, aborting.\n"); 768 goto err_unmap_ctx; 769 } 770 } 771 772 if (hr_dev->caps.cqc_timer_entry_sz) { 773 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 774 HEM_TYPE_CQC_TIMER, 775 hr_dev->caps.cqc_timer_entry_sz, 776 hr_dev->caps.cqc_timer_bt_num); 777 if (ret) { 778 dev_err(dev, 779 "failed to init CQC timer memory, aborting.\n"); 780 goto err_unmap_qpc_timer; 781 } 782 } 783 784 if (hr_dev->caps.gmv_entry_sz) { 785 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table, 786 HEM_TYPE_GMV, 787 hr_dev->caps.gmv_entry_sz, 788 hr_dev->caps.gmv_entry_num); 789 if (ret) { 790 dev_err(dev, 791 "failed to init gmv table memory, ret = %d\n", 792 ret); 793 goto err_unmap_cqc_timer; 794 } 795 } 796 797 return 0; 798 799 err_unmap_cqc_timer: 800 if (hr_dev->caps.cqc_timer_entry_sz) 801 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table); 802 803 err_unmap_qpc_timer: 804 if (hr_dev->caps.qpc_timer_entry_sz) 805 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 806 807 err_unmap_ctx: 808 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 809 hns_roce_cleanup_hem_table(hr_dev, 810 &hr_dev->qp_table.sccc_table); 811 err_unmap_srq: 812 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 813 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 814 815 err_unmap_cq: 816 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 817 818 err_unmap_trrl: 819 if (hr_dev->caps.trrl_entry_sz) 820 hns_roce_cleanup_hem_table(hr_dev, 821 &hr_dev->qp_table.trrl_table); 822 823 err_unmap_irrl: 824 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 825 826 err_unmap_qp: 827 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 828 829 err_unmap_dmpt: 830 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 831 832 return ret; 833 } 834 835 /** 836 * hns_roce_setup_hca - setup host channel adapter 837 * @hr_dev: pointer to hns roce device 838 * Return : int 839 */ 840 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 841 { 842 struct device *dev = hr_dev->dev; 843 int ret; 844 845 spin_lock_init(&hr_dev->sm_lock); 846 847 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 848 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 849 INIT_LIST_HEAD(&hr_dev->pgdir_list); 850 mutex_init(&hr_dev->pgdir_mutex); 851 } 852 853 hns_roce_init_uar_table(hr_dev); 854 855 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 856 if (ret) { 857 dev_err(dev, "failed to allocate priv_uar.\n"); 858 goto err_uar_table_free; 859 } 860 861 ret = hns_roce_init_qp_table(hr_dev); 862 if (ret) { 863 dev_err(dev, "failed to init qp_table.\n"); 864 goto err_uar_table_free; 865 } 866 867 hns_roce_init_pd_table(hr_dev); 868 869 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 870 hns_roce_init_xrcd_table(hr_dev); 871 872 hns_roce_init_mr_table(hr_dev); 873 874 hns_roce_init_cq_table(hr_dev); 875 876 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 877 hns_roce_init_srq_table(hr_dev); 878 879 return 0; 880 881 err_uar_table_free: 882 ida_destroy(&hr_dev->uar_ida.ida); 883 return ret; 884 } 885 886 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 887 { 888 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 889 unsigned long flags; 890 891 spin_lock_irqsave(&hr_cq->lock, flags); 892 if (cq->comp_handler) { 893 if (!hr_cq->is_armed) { 894 hr_cq->is_armed = 1; 895 list_add_tail(&hr_cq->node, cq_list); 896 } 897 } 898 spin_unlock_irqrestore(&hr_cq->lock, flags); 899 } 900 901 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 902 { 903 struct hns_roce_qp *hr_qp; 904 struct hns_roce_cq *hr_cq; 905 struct list_head cq_list; 906 unsigned long flags_qp; 907 unsigned long flags; 908 909 INIT_LIST_HEAD(&cq_list); 910 911 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 912 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 913 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 914 if (hr_qp->sq.tail != hr_qp->sq.head) 915 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 916 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 917 918 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 919 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 920 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 921 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 922 } 923 924 list_for_each_entry(hr_cq, &cq_list, node) 925 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 926 927 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 928 } 929 930 int hns_roce_init(struct hns_roce_dev *hr_dev) 931 { 932 struct device *dev = hr_dev->dev; 933 int ret; 934 935 hr_dev->is_reset = false; 936 937 if (hr_dev->hw->cmq_init) { 938 ret = hr_dev->hw->cmq_init(hr_dev); 939 if (ret) { 940 dev_err(dev, "init RoCE Command Queue failed!\n"); 941 return ret; 942 } 943 } 944 945 ret = hr_dev->hw->hw_profile(hr_dev); 946 if (ret) { 947 dev_err(dev, "get RoCE engine profile failed!\n"); 948 goto error_failed_cmd_init; 949 } 950 951 ret = hns_roce_cmd_init(hr_dev); 952 if (ret) { 953 dev_err(dev, "cmd init failed!\n"); 954 goto error_failed_cmd_init; 955 } 956 957 /* EQ depends on poll mode, event mode depends on EQ */ 958 ret = hr_dev->hw->init_eq(hr_dev); 959 if (ret) { 960 dev_err(dev, "eq init failed!\n"); 961 goto error_failed_eq_table; 962 } 963 964 if (hr_dev->cmd_mod) { 965 ret = hns_roce_cmd_use_events(hr_dev); 966 if (ret) 967 dev_warn(dev, 968 "Cmd event mode failed, set back to poll!\n"); 969 } 970 971 ret = hns_roce_init_hem(hr_dev); 972 if (ret) { 973 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 974 goto error_failed_init_hem; 975 } 976 977 ret = hns_roce_setup_hca(hr_dev); 978 if (ret) { 979 dev_err(dev, "setup hca failed!\n"); 980 goto error_failed_setup_hca; 981 } 982 983 if (hr_dev->hw->hw_init) { 984 ret = hr_dev->hw->hw_init(hr_dev); 985 if (ret) { 986 dev_err(dev, "hw_init failed!\n"); 987 goto error_failed_engine_init; 988 } 989 } 990 991 INIT_LIST_HEAD(&hr_dev->qp_list); 992 spin_lock_init(&hr_dev->qp_list_lock); 993 INIT_LIST_HEAD(&hr_dev->dip_list); 994 spin_lock_init(&hr_dev->dip_list_lock); 995 996 ret = hns_roce_register_device(hr_dev); 997 if (ret) 998 goto error_failed_register_device; 999 1000 return 0; 1001 1002 error_failed_register_device: 1003 if (hr_dev->hw->hw_exit) 1004 hr_dev->hw->hw_exit(hr_dev); 1005 1006 error_failed_engine_init: 1007 hns_roce_cleanup_bitmap(hr_dev); 1008 1009 error_failed_setup_hca: 1010 hns_roce_cleanup_hem(hr_dev); 1011 1012 error_failed_init_hem: 1013 if (hr_dev->cmd_mod) 1014 hns_roce_cmd_use_polling(hr_dev); 1015 hr_dev->hw->cleanup_eq(hr_dev); 1016 1017 error_failed_eq_table: 1018 hns_roce_cmd_cleanup(hr_dev); 1019 1020 error_failed_cmd_init: 1021 if (hr_dev->hw->cmq_exit) 1022 hr_dev->hw->cmq_exit(hr_dev); 1023 1024 return ret; 1025 } 1026 1027 void hns_roce_exit(struct hns_roce_dev *hr_dev) 1028 { 1029 hns_roce_unregister_device(hr_dev); 1030 1031 if (hr_dev->hw->hw_exit) 1032 hr_dev->hw->hw_exit(hr_dev); 1033 hns_roce_cleanup_bitmap(hr_dev); 1034 hns_roce_cleanup_hem(hr_dev); 1035 1036 if (hr_dev->cmd_mod) 1037 hns_roce_cmd_use_polling(hr_dev); 1038 1039 hr_dev->hw->cleanup_eq(hr_dev); 1040 hns_roce_cmd_cleanup(hr_dev); 1041 if (hr_dev->hw->cmq_exit) 1042 hr_dev->hw->cmq_exit(hr_dev); 1043 } 1044 1045 MODULE_LICENSE("Dual BSD/GPL"); 1046 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 1047 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1048 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1049 MODULE_DESCRIPTION("HNS RoCE Driver"); 1050