1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <rdma/ib_addr.h> 38 #include <rdma/ib_smi.h> 39 #include <rdma/ib_user_verbs.h> 40 #include <rdma/ib_cache.h> 41 #include "hns_roce_common.h" 42 #include "hns_roce_device.h" 43 #include "hns_roce_hem.h" 44 45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 46 { 47 u8 phy_port; 48 u32 i; 49 50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 51 return 0; 52 53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 54 return 0; 55 56 for (i = 0; i < ETH_ALEN; i++) 57 hr_dev->dev_addr[port][i] = addr[i]; 58 59 phy_port = hr_dev->iboe.phy_port[port]; 60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 61 } 62 63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 64 { 65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 66 u8 port = attr->port_num - 1; 67 int ret; 68 69 if (port >= hr_dev->caps.num_ports) 70 return -EINVAL; 71 72 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 73 74 return ret; 75 } 76 77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u8 port = attr->port_num - 1; 81 int ret; 82 83 if (port >= hr_dev->caps.num_ports) 84 return -EINVAL; 85 86 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, NULL, NULL); 87 88 return ret; 89 } 90 91 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 92 unsigned long event) 93 { 94 struct device *dev = hr_dev->dev; 95 struct net_device *netdev; 96 int ret = 0; 97 98 netdev = hr_dev->iboe.netdevs[port]; 99 if (!netdev) { 100 dev_err(dev, "Can't find netdev on port(%u)!\n", port); 101 return -ENODEV; 102 } 103 104 switch (event) { 105 case NETDEV_UP: 106 case NETDEV_CHANGE: 107 case NETDEV_REGISTER: 108 case NETDEV_CHANGEADDR: 109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 110 break; 111 case NETDEV_DOWN: 112 /* 113 * In v1 engine, only support all ports closed together. 114 */ 115 break; 116 default: 117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 118 break; 119 } 120 121 return ret; 122 } 123 124 static int hns_roce_netdev_event(struct notifier_block *self, 125 unsigned long event, void *ptr) 126 { 127 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 128 struct hns_roce_ib_iboe *iboe = NULL; 129 struct hns_roce_dev *hr_dev = NULL; 130 int ret; 131 u8 port; 132 133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 134 iboe = &hr_dev->iboe; 135 136 for (port = 0; port < hr_dev->caps.num_ports; port++) { 137 if (dev == iboe->netdevs[port]) { 138 ret = handle_en_event(hr_dev, port, event); 139 if (ret) 140 return NOTIFY_DONE; 141 break; 142 } 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 149 { 150 int ret; 151 u8 i; 152 153 for (i = 0; i < hr_dev->caps.num_ports; i++) { 154 if (hr_dev->hw->set_mtu) 155 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 156 hr_dev->caps.max_mtu); 157 ret = hns_roce_set_mac(hr_dev, i, 158 hr_dev->iboe.netdevs[i]->dev_addr); 159 if (ret) 160 return ret; 161 } 162 163 return 0; 164 } 165 166 static int hns_roce_query_device(struct ib_device *ib_dev, 167 struct ib_device_attr *props, 168 struct ib_udata *uhw) 169 { 170 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 171 172 memset(props, 0, sizeof(*props)); 173 174 props->fw_ver = hr_dev->caps.fw_ver; 175 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 176 props->max_mr_size = (u64)(~(0ULL)); 177 props->page_size_cap = hr_dev->caps.page_size_cap; 178 props->vendor_id = hr_dev->vendor_id; 179 props->vendor_part_id = hr_dev->vendor_part_id; 180 props->hw_ver = hr_dev->hw_rev; 181 props->max_qp = hr_dev->caps.num_qps; 182 props->max_qp_wr = hr_dev->caps.max_wqes; 183 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 184 IB_DEVICE_RC_RNR_NAK_GEN; 185 props->max_send_sge = hr_dev->caps.max_sq_sg; 186 props->max_recv_sge = hr_dev->caps.max_rq_sg; 187 props->max_sge_rd = 1; 188 props->max_cq = hr_dev->caps.num_cqs; 189 props->max_cqe = hr_dev->caps.max_cqes; 190 props->max_mr = hr_dev->caps.num_mtpts; 191 props->max_pd = hr_dev->caps.num_pds; 192 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 193 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 194 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 195 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 196 props->max_pkeys = 1; 197 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 198 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 199 props->max_srq = hr_dev->caps.num_srqs; 200 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 201 props->max_srq_sge = hr_dev->caps.max_srq_sges; 202 } 203 204 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && 205 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 206 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 207 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 208 } 209 210 return 0; 211 } 212 213 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 214 struct ib_port_attr *props) 215 { 216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 217 struct device *dev = hr_dev->dev; 218 struct net_device *net_dev; 219 unsigned long flags; 220 enum ib_mtu mtu; 221 u8 port; 222 223 port = port_num - 1; 224 225 /* props being zeroed by the caller, avoid zeroing it here */ 226 227 props->max_mtu = hr_dev->caps.max_mtu; 228 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 229 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 230 IB_PORT_VENDOR_CLASS_SUP | 231 IB_PORT_BOOT_MGMT_SUP; 232 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 233 props->pkey_tbl_len = 1; 234 props->active_width = IB_WIDTH_4X; 235 props->active_speed = 1; 236 237 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 238 239 net_dev = hr_dev->iboe.netdevs[port]; 240 if (!net_dev) { 241 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 242 dev_err(dev, "Find netdev %u failed!\n", port); 243 return -EINVAL; 244 } 245 246 mtu = iboe_get_mtu(net_dev->mtu); 247 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 248 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 249 IB_PORT_ACTIVE : 250 IB_PORT_DOWN; 251 props->phys_state = props->state == IB_PORT_ACTIVE ? 252 IB_PORT_PHYS_STATE_LINK_UP : 253 IB_PORT_PHYS_STATE_DISABLED; 254 255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 256 257 return 0; 258 } 259 260 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 261 u8 port_num) 262 { 263 return IB_LINK_LAYER_ETHERNET; 264 } 265 266 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 267 u16 *pkey) 268 { 269 *pkey = PKEY_ID; 270 271 return 0; 272 } 273 274 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 275 struct ib_device_modify *props) 276 { 277 unsigned long flags; 278 279 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 280 return -EOPNOTSUPP; 281 282 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 283 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 284 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 285 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 286 } 287 288 return 0; 289 } 290 291 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 292 struct ib_udata *udata) 293 { 294 int ret; 295 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 296 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 297 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 298 299 if (!hr_dev->active) 300 return -EAGAIN; 301 302 resp.qp_tab_size = hr_dev->caps.num_qps; 303 304 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 305 if (ret) 306 goto error_fail_uar_alloc; 307 308 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 309 INIT_LIST_HEAD(&context->page_list); 310 mutex_init(&context->page_mutex); 311 } 312 313 resp.cqe_size = hr_dev->caps.cqe_sz; 314 315 ret = ib_copy_to_udata(udata, &resp, 316 min(udata->outlen, sizeof(resp))); 317 if (ret) 318 goto error_fail_copy_to_udata; 319 320 return 0; 321 322 error_fail_copy_to_udata: 323 hns_roce_uar_free(hr_dev, &context->uar); 324 325 error_fail_uar_alloc: 326 return ret; 327 } 328 329 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 330 { 331 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 332 333 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 334 } 335 336 static int hns_roce_mmap(struct ib_ucontext *context, 337 struct vm_area_struct *vma) 338 { 339 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 340 341 switch (vma->vm_pgoff) { 342 case 0: 343 return rdma_user_mmap_io(context, vma, 344 to_hr_ucontext(context)->uar.pfn, 345 PAGE_SIZE, 346 pgprot_noncached(vma->vm_page_prot), 347 NULL); 348 349 /* vm_pgoff: 1 -- TPTR */ 350 case 1: 351 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 352 return -EINVAL; 353 /* 354 * FIXME: using io_remap_pfn_range on the dma address returned 355 * by dma_alloc_coherent is totally wrong. 356 */ 357 return rdma_user_mmap_io(context, vma, 358 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 359 hr_dev->tptr_size, 360 vma->vm_page_prot, 361 NULL); 362 363 default: 364 return -EINVAL; 365 } 366 } 367 368 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 369 struct ib_port_immutable *immutable) 370 { 371 struct ib_port_attr attr; 372 int ret; 373 374 ret = ib_query_port(ib_dev, port_num, &attr); 375 if (ret) 376 return ret; 377 378 immutable->pkey_tbl_len = attr.pkey_tbl_len; 379 immutable->gid_tbl_len = attr.gid_tbl_len; 380 381 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 382 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 383 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 384 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 385 386 return 0; 387 } 388 389 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 390 { 391 } 392 393 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 394 { 395 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 396 397 hr_dev->active = false; 398 unregister_netdevice_notifier(&iboe->nb); 399 ib_unregister_device(&hr_dev->ib_dev); 400 } 401 402 static const struct ib_device_ops hns_roce_dev_ops = { 403 .owner = THIS_MODULE, 404 .driver_id = RDMA_DRIVER_HNS, 405 .uverbs_abi_ver = 1, 406 .uverbs_no_driver_id_binding = 1, 407 408 .add_gid = hns_roce_add_gid, 409 .alloc_pd = hns_roce_alloc_pd, 410 .alloc_ucontext = hns_roce_alloc_ucontext, 411 .create_ah = hns_roce_create_ah, 412 .create_user_ah = hns_roce_create_ah, 413 .create_cq = hns_roce_create_cq, 414 .create_qp = hns_roce_create_qp, 415 .dealloc_pd = hns_roce_dealloc_pd, 416 .dealloc_ucontext = hns_roce_dealloc_ucontext, 417 .del_gid = hns_roce_del_gid, 418 .dereg_mr = hns_roce_dereg_mr, 419 .destroy_ah = hns_roce_destroy_ah, 420 .destroy_cq = hns_roce_destroy_cq, 421 .disassociate_ucontext = hns_roce_disassociate_ucontext, 422 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 423 .get_dma_mr = hns_roce_get_dma_mr, 424 .get_link_layer = hns_roce_get_link_layer, 425 .get_port_immutable = hns_roce_port_immutable, 426 .mmap = hns_roce_mmap, 427 .modify_device = hns_roce_modify_device, 428 .modify_qp = hns_roce_modify_qp, 429 .query_ah = hns_roce_query_ah, 430 .query_device = hns_roce_query_device, 431 .query_pkey = hns_roce_query_pkey, 432 .query_port = hns_roce_query_port, 433 .reg_user_mr = hns_roce_reg_user_mr, 434 435 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 436 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 437 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 438 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 439 }; 440 441 static const struct ib_device_ops hns_roce_dev_mr_ops = { 442 .rereg_user_mr = hns_roce_rereg_user_mr, 443 }; 444 445 static const struct ib_device_ops hns_roce_dev_mw_ops = { 446 .alloc_mw = hns_roce_alloc_mw, 447 .dealloc_mw = hns_roce_dealloc_mw, 448 449 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 450 }; 451 452 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 453 .alloc_mr = hns_roce_alloc_mr, 454 .map_mr_sg = hns_roce_map_mr_sg, 455 }; 456 457 static const struct ib_device_ops hns_roce_dev_srq_ops = { 458 .create_srq = hns_roce_create_srq, 459 .destroy_srq = hns_roce_destroy_srq, 460 461 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 462 }; 463 464 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 465 { 466 int ret; 467 struct hns_roce_ib_iboe *iboe = NULL; 468 struct ib_device *ib_dev = NULL; 469 struct device *dev = hr_dev->dev; 470 unsigned int i; 471 472 iboe = &hr_dev->iboe; 473 spin_lock_init(&iboe->lock); 474 475 ib_dev = &hr_dev->ib_dev; 476 477 ib_dev->node_type = RDMA_NODE_IB_CA; 478 ib_dev->dev.parent = dev; 479 480 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 481 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 482 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 483 484 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) 485 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 486 487 /* MW */ 488 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) 489 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 490 491 /* FRMR */ 492 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 493 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 494 495 /* SRQ */ 496 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 497 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 498 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 499 } 500 501 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 502 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 503 for (i = 0; i < hr_dev->caps.num_ports; i++) { 504 if (!hr_dev->iboe.netdevs[i]) 505 continue; 506 507 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 508 i + 1); 509 if (ret) 510 return ret; 511 } 512 dma_set_max_seg_size(dev, UINT_MAX); 513 ret = ib_register_device(ib_dev, "hns_%d", dev); 514 if (ret) { 515 dev_err(dev, "ib_register_device failed!\n"); 516 return ret; 517 } 518 519 ret = hns_roce_setup_mtu_mac(hr_dev); 520 if (ret) { 521 dev_err(dev, "setup_mtu_mac failed!\n"); 522 goto error_failed_setup_mtu_mac; 523 } 524 525 iboe->nb.notifier_call = hns_roce_netdev_event; 526 ret = register_netdevice_notifier(&iboe->nb); 527 if (ret) { 528 dev_err(dev, "register_netdevice_notifier failed!\n"); 529 goto error_failed_setup_mtu_mac; 530 } 531 532 hr_dev->active = true; 533 return 0; 534 535 error_failed_setup_mtu_mac: 536 ib_unregister_device(ib_dev); 537 538 return ret; 539 } 540 541 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 542 { 543 struct device *dev = hr_dev->dev; 544 int ret; 545 546 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 547 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 548 hr_dev->caps.num_mtpts, 1); 549 if (ret) { 550 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 551 return ret; 552 } 553 554 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 555 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 556 hr_dev->caps.num_qps, 1); 557 if (ret) { 558 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 559 goto err_unmap_dmpt; 560 } 561 562 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 563 HEM_TYPE_IRRL, 564 hr_dev->caps.irrl_entry_sz * 565 hr_dev->caps.max_qp_init_rdma, 566 hr_dev->caps.num_qps, 1); 567 if (ret) { 568 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 569 goto err_unmap_qp; 570 } 571 572 if (hr_dev->caps.trrl_entry_sz) { 573 ret = hns_roce_init_hem_table(hr_dev, 574 &hr_dev->qp_table.trrl_table, 575 HEM_TYPE_TRRL, 576 hr_dev->caps.trrl_entry_sz * 577 hr_dev->caps.max_qp_dest_rdma, 578 hr_dev->caps.num_qps, 1); 579 if (ret) { 580 dev_err(dev, 581 "Failed to init trrl_table memory, aborting.\n"); 582 goto err_unmap_irrl; 583 } 584 } 585 586 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 587 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 588 hr_dev->caps.num_cqs, 1); 589 if (ret) { 590 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 591 goto err_unmap_trrl; 592 } 593 594 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 595 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 596 HEM_TYPE_SRQC, 597 hr_dev->caps.srqc_entry_sz, 598 hr_dev->caps.num_srqs, 1); 599 if (ret) { 600 dev_err(dev, 601 "Failed to init SRQ context memory, aborting.\n"); 602 goto err_unmap_cq; 603 } 604 } 605 606 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 607 ret = hns_roce_init_hem_table(hr_dev, 608 &hr_dev->qp_table.sccc_table, 609 HEM_TYPE_SCCC, 610 hr_dev->caps.sccc_sz, 611 hr_dev->caps.num_qps, 1); 612 if (ret) { 613 dev_err(dev, 614 "Failed to init SCC context memory, aborting.\n"); 615 goto err_unmap_srq; 616 } 617 } 618 619 if (hr_dev->caps.qpc_timer_entry_sz) { 620 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 621 HEM_TYPE_QPC_TIMER, 622 hr_dev->caps.qpc_timer_entry_sz, 623 hr_dev->caps.num_qpc_timer, 1); 624 if (ret) { 625 dev_err(dev, 626 "Failed to init QPC timer memory, aborting.\n"); 627 goto err_unmap_ctx; 628 } 629 } 630 631 if (hr_dev->caps.cqc_timer_entry_sz) { 632 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 633 HEM_TYPE_CQC_TIMER, 634 hr_dev->caps.cqc_timer_entry_sz, 635 hr_dev->caps.num_cqc_timer, 1); 636 if (ret) { 637 dev_err(dev, 638 "Failed to init CQC timer memory, aborting.\n"); 639 goto err_unmap_qpc_timer; 640 } 641 } 642 643 if (hr_dev->caps.gmv_entry_sz) { 644 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table, 645 HEM_TYPE_GMV, 646 hr_dev->caps.gmv_entry_sz, 647 hr_dev->caps.gmv_entry_num, 1); 648 if (ret) { 649 dev_err(dev, 650 "failed to init gmv table memory, ret = %d\n", 651 ret); 652 goto err_unmap_cqc_timer; 653 } 654 } 655 656 return 0; 657 658 err_unmap_cqc_timer: 659 if (hr_dev->caps.cqc_timer_entry_sz) 660 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table); 661 662 err_unmap_qpc_timer: 663 if (hr_dev->caps.qpc_timer_entry_sz) 664 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 665 666 err_unmap_ctx: 667 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 668 hns_roce_cleanup_hem_table(hr_dev, 669 &hr_dev->qp_table.sccc_table); 670 err_unmap_srq: 671 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 672 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 673 674 err_unmap_cq: 675 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 676 677 err_unmap_trrl: 678 if (hr_dev->caps.trrl_entry_sz) 679 hns_roce_cleanup_hem_table(hr_dev, 680 &hr_dev->qp_table.trrl_table); 681 682 err_unmap_irrl: 683 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 684 685 err_unmap_qp: 686 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 687 688 err_unmap_dmpt: 689 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 690 691 return ret; 692 } 693 694 /** 695 * hns_roce_setup_hca - setup host channel adapter 696 * @hr_dev: pointer to hns roce device 697 * Return : int 698 */ 699 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 700 { 701 struct device *dev = hr_dev->dev; 702 int ret; 703 704 spin_lock_init(&hr_dev->sm_lock); 705 spin_lock_init(&hr_dev->bt_cmd_lock); 706 707 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 708 INIT_LIST_HEAD(&hr_dev->pgdir_list); 709 mutex_init(&hr_dev->pgdir_mutex); 710 } 711 712 ret = hns_roce_init_uar_table(hr_dev); 713 if (ret) { 714 dev_err(dev, "Failed to initialize uar table. aborting\n"); 715 return ret; 716 } 717 718 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 719 if (ret) { 720 dev_err(dev, "Failed to allocate priv_uar.\n"); 721 goto err_uar_table_free; 722 } 723 724 ret = hns_roce_init_pd_table(hr_dev); 725 if (ret) { 726 dev_err(dev, "Failed to init protected domain table.\n"); 727 goto err_uar_alloc_free; 728 } 729 730 ret = hns_roce_init_mr_table(hr_dev); 731 if (ret) { 732 dev_err(dev, "Failed to init memory region table.\n"); 733 goto err_pd_table_free; 734 } 735 736 hns_roce_init_cq_table(hr_dev); 737 738 ret = hns_roce_init_qp_table(hr_dev); 739 if (ret) { 740 dev_err(dev, "Failed to init queue pair table.\n"); 741 goto err_cq_table_free; 742 } 743 744 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 745 ret = hns_roce_init_srq_table(hr_dev); 746 if (ret) { 747 dev_err(dev, 748 "Failed to init share receive queue table.\n"); 749 goto err_qp_table_free; 750 } 751 } 752 753 return 0; 754 755 err_qp_table_free: 756 hns_roce_cleanup_qp_table(hr_dev); 757 758 err_cq_table_free: 759 hns_roce_cleanup_cq_table(hr_dev); 760 hns_roce_cleanup_mr_table(hr_dev); 761 762 err_pd_table_free: 763 hns_roce_cleanup_pd_table(hr_dev); 764 765 err_uar_alloc_free: 766 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 767 768 err_uar_table_free: 769 hns_roce_cleanup_uar_table(hr_dev); 770 return ret; 771 } 772 773 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 774 { 775 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 776 unsigned long flags; 777 778 spin_lock_irqsave(&hr_cq->lock, flags); 779 if (cq->comp_handler) { 780 if (!hr_cq->is_armed) { 781 hr_cq->is_armed = 1; 782 list_add_tail(&hr_cq->node, cq_list); 783 } 784 } 785 spin_unlock_irqrestore(&hr_cq->lock, flags); 786 } 787 788 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 789 { 790 struct hns_roce_qp *hr_qp; 791 struct hns_roce_cq *hr_cq; 792 struct list_head cq_list; 793 unsigned long flags_qp; 794 unsigned long flags; 795 796 INIT_LIST_HEAD(&cq_list); 797 798 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 799 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 800 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 801 if (hr_qp->sq.tail != hr_qp->sq.head) 802 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 803 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 804 805 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 806 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 807 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 808 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 809 } 810 811 list_for_each_entry(hr_cq, &cq_list, node) 812 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 813 814 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 815 } 816 817 int hns_roce_init(struct hns_roce_dev *hr_dev) 818 { 819 struct device *dev = hr_dev->dev; 820 int ret; 821 822 if (hr_dev->hw->reset) { 823 ret = hr_dev->hw->reset(hr_dev, true); 824 if (ret) { 825 dev_err(dev, "Reset RoCE engine failed!\n"); 826 return ret; 827 } 828 } 829 hr_dev->is_reset = false; 830 831 if (hr_dev->hw->cmq_init) { 832 ret = hr_dev->hw->cmq_init(hr_dev); 833 if (ret) { 834 dev_err(dev, "Init RoCE Command Queue failed!\n"); 835 goto error_failed_cmq_init; 836 } 837 } 838 839 ret = hr_dev->hw->hw_profile(hr_dev); 840 if (ret) { 841 dev_err(dev, "Get RoCE engine profile failed!\n"); 842 goto error_failed_cmd_init; 843 } 844 845 ret = hns_roce_cmd_init(hr_dev); 846 if (ret) { 847 dev_err(dev, "cmd init failed!\n"); 848 goto error_failed_cmd_init; 849 } 850 851 /* EQ depends on poll mode, event mode depends on EQ */ 852 ret = hr_dev->hw->init_eq(hr_dev); 853 if (ret) { 854 dev_err(dev, "eq init failed!\n"); 855 goto error_failed_eq_table; 856 } 857 858 if (hr_dev->cmd_mod) { 859 ret = hns_roce_cmd_use_events(hr_dev); 860 if (ret) { 861 dev_warn(dev, 862 "Cmd event mode failed, set back to poll!\n"); 863 hns_roce_cmd_use_polling(hr_dev); 864 } 865 } 866 867 ret = hns_roce_init_hem(hr_dev); 868 if (ret) { 869 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 870 goto error_failed_init_hem; 871 } 872 873 ret = hns_roce_setup_hca(hr_dev); 874 if (ret) { 875 dev_err(dev, "setup hca failed!\n"); 876 goto error_failed_setup_hca; 877 } 878 879 if (hr_dev->hw->hw_init) { 880 ret = hr_dev->hw->hw_init(hr_dev); 881 if (ret) { 882 dev_err(dev, "hw_init failed!\n"); 883 goto error_failed_engine_init; 884 } 885 } 886 887 INIT_LIST_HEAD(&hr_dev->qp_list); 888 spin_lock_init(&hr_dev->qp_list_lock); 889 890 ret = hns_roce_register_device(hr_dev); 891 if (ret) 892 goto error_failed_register_device; 893 894 return 0; 895 896 error_failed_register_device: 897 if (hr_dev->hw->hw_exit) 898 hr_dev->hw->hw_exit(hr_dev); 899 900 error_failed_engine_init: 901 hns_roce_cleanup_bitmap(hr_dev); 902 903 error_failed_setup_hca: 904 hns_roce_cleanup_hem(hr_dev); 905 906 error_failed_init_hem: 907 if (hr_dev->cmd_mod) 908 hns_roce_cmd_use_polling(hr_dev); 909 hr_dev->hw->cleanup_eq(hr_dev); 910 911 error_failed_eq_table: 912 hns_roce_cmd_cleanup(hr_dev); 913 914 error_failed_cmd_init: 915 if (hr_dev->hw->cmq_exit) 916 hr_dev->hw->cmq_exit(hr_dev); 917 918 error_failed_cmq_init: 919 if (hr_dev->hw->reset) { 920 if (hr_dev->hw->reset(hr_dev, false)) 921 dev_err(dev, "Dereset RoCE engine failed!\n"); 922 } 923 924 return ret; 925 } 926 927 void hns_roce_exit(struct hns_roce_dev *hr_dev) 928 { 929 hns_roce_unregister_device(hr_dev); 930 931 if (hr_dev->hw->hw_exit) 932 hr_dev->hw->hw_exit(hr_dev); 933 hns_roce_cleanup_bitmap(hr_dev); 934 hns_roce_cleanup_hem(hr_dev); 935 936 if (hr_dev->cmd_mod) 937 hns_roce_cmd_use_polling(hr_dev); 938 939 hr_dev->hw->cleanup_eq(hr_dev); 940 hns_roce_cmd_cleanup(hr_dev); 941 if (hr_dev->hw->cmq_exit) 942 hr_dev->hw->cmq_exit(hr_dev); 943 if (hr_dev->hw->reset) 944 hr_dev->hw->reset(hr_dev, false); 945 } 946 947 MODULE_LICENSE("Dual BSD/GPL"); 948 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 949 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 950 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 951 MODULE_DESCRIPTION("HNS RoCE Driver"); 952