1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include "hns_roce_hem.h" 43 44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, 45 const u8 *addr) 46 { 47 u8 phy_port; 48 u32 i; 49 50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 51 return 0; 52 53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 54 return 0; 55 56 for (i = 0; i < ETH_ALEN; i++) 57 hr_dev->dev_addr[port][i] = addr[i]; 58 59 phy_port = hr_dev->iboe.phy_port[port]; 60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 61 } 62 63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 64 { 65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 66 u32 port = attr->port_num - 1; 67 int ret; 68 69 if (port >= hr_dev->caps.num_ports) 70 return -EINVAL; 71 72 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr); 73 74 return ret; 75 } 76 77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u32 port = attr->port_num - 1; 81 int ret; 82 83 if (port >= hr_dev->caps.num_ports) 84 return -EINVAL; 85 86 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL); 87 88 return ret; 89 } 90 91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port, 92 unsigned long event) 93 { 94 struct device *dev = hr_dev->dev; 95 struct net_device *netdev; 96 int ret = 0; 97 98 netdev = hr_dev->iboe.netdevs[port]; 99 if (!netdev) { 100 dev_err(dev, "Can't find netdev on port(%u)!\n", port); 101 return -ENODEV; 102 } 103 104 switch (event) { 105 case NETDEV_UP: 106 case NETDEV_CHANGE: 107 case NETDEV_REGISTER: 108 case NETDEV_CHANGEADDR: 109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 110 break; 111 case NETDEV_DOWN: 112 /* 113 * In v1 engine, only support all ports closed together. 114 */ 115 break; 116 default: 117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 118 break; 119 } 120 121 return ret; 122 } 123 124 static int hns_roce_netdev_event(struct notifier_block *self, 125 unsigned long event, void *ptr) 126 { 127 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 128 struct hns_roce_ib_iboe *iboe = NULL; 129 struct hns_roce_dev *hr_dev = NULL; 130 int ret; 131 u32 port; 132 133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 134 iboe = &hr_dev->iboe; 135 136 for (port = 0; port < hr_dev->caps.num_ports; port++) { 137 if (dev == iboe->netdevs[port]) { 138 ret = handle_en_event(hr_dev, port, event); 139 if (ret) 140 return NOTIFY_DONE; 141 break; 142 } 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 149 { 150 int ret; 151 u8 i; 152 153 for (i = 0; i < hr_dev->caps.num_ports; i++) { 154 ret = hns_roce_set_mac(hr_dev, i, 155 hr_dev->iboe.netdevs[i]->dev_addr); 156 if (ret) 157 return ret; 158 } 159 160 return 0; 161 } 162 163 static int hns_roce_query_device(struct ib_device *ib_dev, 164 struct ib_device_attr *props, 165 struct ib_udata *uhw) 166 { 167 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 168 169 memset(props, 0, sizeof(*props)); 170 171 props->fw_ver = hr_dev->caps.fw_ver; 172 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 173 props->max_mr_size = (u64)(~(0ULL)); 174 props->page_size_cap = hr_dev->caps.page_size_cap; 175 props->vendor_id = hr_dev->vendor_id; 176 props->vendor_part_id = hr_dev->vendor_part_id; 177 props->hw_ver = hr_dev->hw_rev; 178 props->max_qp = hr_dev->caps.num_qps; 179 props->max_qp_wr = hr_dev->caps.max_wqes; 180 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 181 IB_DEVICE_RC_RNR_NAK_GEN; 182 props->max_send_sge = hr_dev->caps.max_sq_sg; 183 props->max_recv_sge = hr_dev->caps.max_rq_sg; 184 props->max_sge_rd = 1; 185 props->max_cq = hr_dev->caps.num_cqs; 186 props->max_cqe = hr_dev->caps.max_cqes; 187 props->max_mr = hr_dev->caps.num_mtpts; 188 props->max_pd = hr_dev->caps.num_pds; 189 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 190 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 191 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 192 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 193 props->max_pkeys = 1; 194 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 195 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 196 props->max_srq = hr_dev->caps.num_srqs; 197 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 198 props->max_srq_sge = hr_dev->caps.max_srq_sges; 199 } 200 201 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && 202 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 203 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 204 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 205 } 206 207 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 208 props->device_cap_flags |= IB_DEVICE_XRC; 209 210 return 0; 211 } 212 213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num, 214 struct ib_port_attr *props) 215 { 216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 217 struct device *dev = hr_dev->dev; 218 struct net_device *net_dev; 219 unsigned long flags; 220 enum ib_mtu mtu; 221 u32 port; 222 223 port = port_num - 1; 224 225 /* props being zeroed by the caller, avoid zeroing it here */ 226 227 props->max_mtu = hr_dev->caps.max_mtu; 228 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 229 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 230 IB_PORT_VENDOR_CLASS_SUP | 231 IB_PORT_BOOT_MGMT_SUP; 232 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 233 props->pkey_tbl_len = 1; 234 props->active_width = IB_WIDTH_4X; 235 props->active_speed = 1; 236 237 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 238 239 net_dev = hr_dev->iboe.netdevs[port]; 240 if (!net_dev) { 241 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 242 dev_err(dev, "Find netdev %u failed!\n", port); 243 return -EINVAL; 244 } 245 246 mtu = iboe_get_mtu(net_dev->mtu); 247 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 248 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 249 IB_PORT_ACTIVE : 250 IB_PORT_DOWN; 251 props->phys_state = props->state == IB_PORT_ACTIVE ? 252 IB_PORT_PHYS_STATE_LINK_UP : 253 IB_PORT_PHYS_STATE_DISABLED; 254 255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 256 257 return 0; 258 } 259 260 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 261 u32 port_num) 262 { 263 return IB_LINK_LAYER_ETHERNET; 264 } 265 266 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index, 267 u16 *pkey) 268 { 269 if (index > 0) 270 return -EINVAL; 271 272 *pkey = PKEY_ID; 273 274 return 0; 275 } 276 277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 278 struct ib_device_modify *props) 279 { 280 unsigned long flags; 281 282 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 283 return -EOPNOTSUPP; 284 285 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 286 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 287 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 288 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 289 } 290 291 return 0; 292 } 293 294 struct hns_user_mmap_entry * 295 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 296 size_t length, 297 enum hns_roce_mmap_type mmap_type) 298 { 299 struct hns_user_mmap_entry *entry; 300 int ret; 301 302 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 303 if (!entry) 304 return NULL; 305 306 entry->address = address; 307 entry->mmap_type = mmap_type; 308 309 switch (mmap_type) { 310 /* pgoff 0 must be used by DB for compatibility */ 311 case HNS_ROCE_MMAP_TYPE_DB: 312 ret = rdma_user_mmap_entry_insert_exact( 313 ucontext, &entry->rdma_entry, length, 0); 314 break; 315 case HNS_ROCE_MMAP_TYPE_DWQE: 316 ret = rdma_user_mmap_entry_insert_range( 317 ucontext, &entry->rdma_entry, length, 1, 318 U32_MAX); 319 break; 320 default: 321 ret = -EINVAL; 322 break; 323 } 324 325 if (ret) { 326 kfree(entry); 327 return NULL; 328 } 329 330 return entry; 331 } 332 333 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context) 334 { 335 if (context->db_mmap_entry) 336 rdma_user_mmap_entry_remove( 337 &context->db_mmap_entry->rdma_entry); 338 } 339 340 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx) 341 { 342 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 343 u64 address; 344 345 address = context->uar.pfn << PAGE_SHIFT; 346 context->db_mmap_entry = hns_roce_user_mmap_entry_insert( 347 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB); 348 if (!context->db_mmap_entry) 349 return -ENOMEM; 350 351 return 0; 352 } 353 354 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 355 struct ib_udata *udata) 356 { 357 int ret; 358 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 359 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 360 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 361 362 if (!hr_dev->active) 363 return -EAGAIN; 364 365 resp.qp_tab_size = hr_dev->caps.num_qps; 366 resp.srq_tab_size = hr_dev->caps.num_srqs; 367 368 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 369 if (ret) 370 goto error_fail_uar_alloc; 371 372 ret = hns_roce_alloc_uar_entry(uctx); 373 if (ret) 374 goto error_fail_uar_entry; 375 376 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 377 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 378 INIT_LIST_HEAD(&context->page_list); 379 mutex_init(&context->page_mutex); 380 } 381 382 resp.cqe_size = hr_dev->caps.cqe_sz; 383 384 ret = ib_copy_to_udata(udata, &resp, 385 min(udata->outlen, sizeof(resp))); 386 if (ret) 387 goto error_fail_copy_to_udata; 388 389 return 0; 390 391 error_fail_copy_to_udata: 392 hns_roce_dealloc_uar_entry(context); 393 394 error_fail_uar_entry: 395 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 396 397 error_fail_uar_alloc: 398 return ret; 399 } 400 401 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 402 { 403 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 404 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device); 405 406 hns_roce_dealloc_uar_entry(context); 407 408 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 409 } 410 411 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma) 412 { 413 struct rdma_user_mmap_entry *rdma_entry; 414 struct hns_user_mmap_entry *entry; 415 phys_addr_t pfn; 416 pgprot_t prot; 417 int ret; 418 419 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff); 420 if (!rdma_entry) 421 return -EINVAL; 422 423 entry = to_hns_mmap(rdma_entry); 424 pfn = entry->address >> PAGE_SHIFT; 425 426 switch (entry->mmap_type) { 427 case HNS_ROCE_MMAP_TYPE_DB: 428 case HNS_ROCE_MMAP_TYPE_DWQE: 429 prot = pgprot_device(vma->vm_page_prot); 430 break; 431 default: 432 return -EINVAL; 433 } 434 435 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE, 436 prot, rdma_entry); 437 438 rdma_user_mmap_entry_put(rdma_entry); 439 440 return ret; 441 } 442 443 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry) 444 { 445 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry); 446 447 kfree(entry); 448 } 449 450 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num, 451 struct ib_port_immutable *immutable) 452 { 453 struct ib_port_attr attr; 454 int ret; 455 456 ret = ib_query_port(ib_dev, port_num, &attr); 457 if (ret) 458 return ret; 459 460 immutable->pkey_tbl_len = attr.pkey_tbl_len; 461 immutable->gid_tbl_len = attr.gid_tbl_len; 462 463 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 464 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 465 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 466 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 467 468 return 0; 469 } 470 471 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 472 { 473 } 474 475 static void hns_roce_get_fw_ver(struct ib_device *device, char *str) 476 { 477 u64 fw_ver = to_hr_dev(device)->caps.fw_ver; 478 unsigned int major, minor, sub_minor; 479 480 major = upper_32_bits(fw_ver); 481 minor = high_16_bits(lower_32_bits(fw_ver)); 482 sub_minor = low_16_bits(fw_ver); 483 484 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor, 485 sub_minor); 486 } 487 488 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 489 { 490 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 491 492 hr_dev->active = false; 493 unregister_netdevice_notifier(&iboe->nb); 494 ib_unregister_device(&hr_dev->ib_dev); 495 } 496 497 static const struct ib_device_ops hns_roce_dev_ops = { 498 .owner = THIS_MODULE, 499 .driver_id = RDMA_DRIVER_HNS, 500 .uverbs_abi_ver = 1, 501 .uverbs_no_driver_id_binding = 1, 502 503 .get_dev_fw_str = hns_roce_get_fw_ver, 504 .add_gid = hns_roce_add_gid, 505 .alloc_pd = hns_roce_alloc_pd, 506 .alloc_ucontext = hns_roce_alloc_ucontext, 507 .create_ah = hns_roce_create_ah, 508 .create_user_ah = hns_roce_create_ah, 509 .create_cq = hns_roce_create_cq, 510 .create_qp = hns_roce_create_qp, 511 .dealloc_pd = hns_roce_dealloc_pd, 512 .dealloc_ucontext = hns_roce_dealloc_ucontext, 513 .del_gid = hns_roce_del_gid, 514 .dereg_mr = hns_roce_dereg_mr, 515 .destroy_ah = hns_roce_destroy_ah, 516 .destroy_cq = hns_roce_destroy_cq, 517 .disassociate_ucontext = hns_roce_disassociate_ucontext, 518 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 519 .get_dma_mr = hns_roce_get_dma_mr, 520 .get_link_layer = hns_roce_get_link_layer, 521 .get_port_immutable = hns_roce_port_immutable, 522 .mmap = hns_roce_mmap, 523 .mmap_free = hns_roce_free_mmap, 524 .modify_device = hns_roce_modify_device, 525 .modify_qp = hns_roce_modify_qp, 526 .query_ah = hns_roce_query_ah, 527 .query_device = hns_roce_query_device, 528 .query_pkey = hns_roce_query_pkey, 529 .query_port = hns_roce_query_port, 530 .reg_user_mr = hns_roce_reg_user_mr, 531 532 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 533 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 534 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 535 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp), 536 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 537 }; 538 539 static const struct ib_device_ops hns_roce_dev_mr_ops = { 540 .rereg_user_mr = hns_roce_rereg_user_mr, 541 }; 542 543 static const struct ib_device_ops hns_roce_dev_mw_ops = { 544 .alloc_mw = hns_roce_alloc_mw, 545 .dealloc_mw = hns_roce_dealloc_mw, 546 547 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 548 }; 549 550 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 551 .alloc_mr = hns_roce_alloc_mr, 552 .map_mr_sg = hns_roce_map_mr_sg, 553 }; 554 555 static const struct ib_device_ops hns_roce_dev_srq_ops = { 556 .create_srq = hns_roce_create_srq, 557 .destroy_srq = hns_roce_destroy_srq, 558 559 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 560 }; 561 562 static const struct ib_device_ops hns_roce_dev_xrcd_ops = { 563 .alloc_xrcd = hns_roce_alloc_xrcd, 564 .dealloc_xrcd = hns_roce_dealloc_xrcd, 565 566 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), 567 }; 568 569 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 570 { 571 int ret; 572 struct hns_roce_ib_iboe *iboe = NULL; 573 struct ib_device *ib_dev = NULL; 574 struct device *dev = hr_dev->dev; 575 unsigned int i; 576 577 iboe = &hr_dev->iboe; 578 spin_lock_init(&iboe->lock); 579 580 ib_dev = &hr_dev->ib_dev; 581 582 ib_dev->node_type = RDMA_NODE_IB_CA; 583 ib_dev->dev.parent = dev; 584 585 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 586 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 587 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 588 589 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) 590 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 591 592 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) 593 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 594 595 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 596 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 597 598 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 599 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 600 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 601 } 602 603 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 604 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); 605 606 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 607 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 608 for (i = 0; i < hr_dev->caps.num_ports; i++) { 609 if (!hr_dev->iboe.netdevs[i]) 610 continue; 611 612 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 613 i + 1); 614 if (ret) 615 return ret; 616 } 617 dma_set_max_seg_size(dev, UINT_MAX); 618 ret = ib_register_device(ib_dev, "hns_%d", dev); 619 if (ret) { 620 dev_err(dev, "ib_register_device failed!\n"); 621 return ret; 622 } 623 624 ret = hns_roce_setup_mtu_mac(hr_dev); 625 if (ret) { 626 dev_err(dev, "setup_mtu_mac failed!\n"); 627 goto error_failed_setup_mtu_mac; 628 } 629 630 iboe->nb.notifier_call = hns_roce_netdev_event; 631 ret = register_netdevice_notifier(&iboe->nb); 632 if (ret) { 633 dev_err(dev, "register_netdevice_notifier failed!\n"); 634 goto error_failed_setup_mtu_mac; 635 } 636 637 hr_dev->active = true; 638 return 0; 639 640 error_failed_setup_mtu_mac: 641 ib_unregister_device(ib_dev); 642 643 return ret; 644 } 645 646 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 647 { 648 struct device *dev = hr_dev->dev; 649 int ret; 650 651 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 652 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 653 hr_dev->caps.num_mtpts, 1); 654 if (ret) { 655 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 656 return ret; 657 } 658 659 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 660 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 661 hr_dev->caps.num_qps, 1); 662 if (ret) { 663 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 664 goto err_unmap_dmpt; 665 } 666 667 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 668 HEM_TYPE_IRRL, 669 hr_dev->caps.irrl_entry_sz * 670 hr_dev->caps.max_qp_init_rdma, 671 hr_dev->caps.num_qps, 1); 672 if (ret) { 673 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 674 goto err_unmap_qp; 675 } 676 677 if (hr_dev->caps.trrl_entry_sz) { 678 ret = hns_roce_init_hem_table(hr_dev, 679 &hr_dev->qp_table.trrl_table, 680 HEM_TYPE_TRRL, 681 hr_dev->caps.trrl_entry_sz * 682 hr_dev->caps.max_qp_dest_rdma, 683 hr_dev->caps.num_qps, 1); 684 if (ret) { 685 dev_err(dev, 686 "Failed to init trrl_table memory, aborting.\n"); 687 goto err_unmap_irrl; 688 } 689 } 690 691 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 692 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 693 hr_dev->caps.num_cqs, 1); 694 if (ret) { 695 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 696 goto err_unmap_trrl; 697 } 698 699 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 700 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 701 HEM_TYPE_SRQC, 702 hr_dev->caps.srqc_entry_sz, 703 hr_dev->caps.num_srqs, 1); 704 if (ret) { 705 dev_err(dev, 706 "Failed to init SRQ context memory, aborting.\n"); 707 goto err_unmap_cq; 708 } 709 } 710 711 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 712 ret = hns_roce_init_hem_table(hr_dev, 713 &hr_dev->qp_table.sccc_table, 714 HEM_TYPE_SCCC, 715 hr_dev->caps.sccc_sz, 716 hr_dev->caps.num_qps, 1); 717 if (ret) { 718 dev_err(dev, 719 "Failed to init SCC context memory, aborting.\n"); 720 goto err_unmap_srq; 721 } 722 } 723 724 if (hr_dev->caps.qpc_timer_entry_sz) { 725 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 726 HEM_TYPE_QPC_TIMER, 727 hr_dev->caps.qpc_timer_entry_sz, 728 hr_dev->caps.num_qpc_timer, 1); 729 if (ret) { 730 dev_err(dev, 731 "Failed to init QPC timer memory, aborting.\n"); 732 goto err_unmap_ctx; 733 } 734 } 735 736 if (hr_dev->caps.cqc_timer_entry_sz) { 737 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 738 HEM_TYPE_CQC_TIMER, 739 hr_dev->caps.cqc_timer_entry_sz, 740 hr_dev->caps.cqc_timer_bt_num, 1); 741 if (ret) { 742 dev_err(dev, 743 "Failed to init CQC timer memory, aborting.\n"); 744 goto err_unmap_qpc_timer; 745 } 746 } 747 748 if (hr_dev->caps.gmv_entry_sz) { 749 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table, 750 HEM_TYPE_GMV, 751 hr_dev->caps.gmv_entry_sz, 752 hr_dev->caps.gmv_entry_num, 1); 753 if (ret) { 754 dev_err(dev, 755 "failed to init gmv table memory, ret = %d\n", 756 ret); 757 goto err_unmap_cqc_timer; 758 } 759 } 760 761 return 0; 762 763 err_unmap_cqc_timer: 764 if (hr_dev->caps.cqc_timer_entry_sz) 765 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table); 766 767 err_unmap_qpc_timer: 768 if (hr_dev->caps.qpc_timer_entry_sz) 769 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 770 771 err_unmap_ctx: 772 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 773 hns_roce_cleanup_hem_table(hr_dev, 774 &hr_dev->qp_table.sccc_table); 775 err_unmap_srq: 776 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 777 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 778 779 err_unmap_cq: 780 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 781 782 err_unmap_trrl: 783 if (hr_dev->caps.trrl_entry_sz) 784 hns_roce_cleanup_hem_table(hr_dev, 785 &hr_dev->qp_table.trrl_table); 786 787 err_unmap_irrl: 788 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 789 790 err_unmap_qp: 791 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 792 793 err_unmap_dmpt: 794 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 795 796 return ret; 797 } 798 799 /** 800 * hns_roce_setup_hca - setup host channel adapter 801 * @hr_dev: pointer to hns roce device 802 * Return : int 803 */ 804 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 805 { 806 struct device *dev = hr_dev->dev; 807 int ret; 808 809 spin_lock_init(&hr_dev->sm_lock); 810 811 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 812 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 813 INIT_LIST_HEAD(&hr_dev->pgdir_list); 814 mutex_init(&hr_dev->pgdir_mutex); 815 } 816 817 hns_roce_init_uar_table(hr_dev); 818 819 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 820 if (ret) { 821 dev_err(dev, "Failed to allocate priv_uar.\n"); 822 goto err_uar_table_free; 823 } 824 825 ret = hns_roce_init_qp_table(hr_dev); 826 if (ret) { 827 dev_err(dev, "Failed to init qp_table.\n"); 828 goto err_uar_table_free; 829 } 830 831 hns_roce_init_pd_table(hr_dev); 832 833 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 834 hns_roce_init_xrcd_table(hr_dev); 835 836 hns_roce_init_mr_table(hr_dev); 837 838 hns_roce_init_cq_table(hr_dev); 839 840 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 841 hns_roce_init_srq_table(hr_dev); 842 } 843 844 return 0; 845 846 err_uar_table_free: 847 ida_destroy(&hr_dev->uar_ida.ida); 848 return ret; 849 } 850 851 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 852 { 853 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 854 unsigned long flags; 855 856 spin_lock_irqsave(&hr_cq->lock, flags); 857 if (cq->comp_handler) { 858 if (!hr_cq->is_armed) { 859 hr_cq->is_armed = 1; 860 list_add_tail(&hr_cq->node, cq_list); 861 } 862 } 863 spin_unlock_irqrestore(&hr_cq->lock, flags); 864 } 865 866 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 867 { 868 struct hns_roce_qp *hr_qp; 869 struct hns_roce_cq *hr_cq; 870 struct list_head cq_list; 871 unsigned long flags_qp; 872 unsigned long flags; 873 874 INIT_LIST_HEAD(&cq_list); 875 876 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 877 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 878 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 879 if (hr_qp->sq.tail != hr_qp->sq.head) 880 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 881 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 882 883 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 884 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 885 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 886 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 887 } 888 889 list_for_each_entry(hr_cq, &cq_list, node) 890 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 891 892 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 893 } 894 895 int hns_roce_init(struct hns_roce_dev *hr_dev) 896 { 897 struct device *dev = hr_dev->dev; 898 int ret; 899 900 hr_dev->is_reset = false; 901 902 if (hr_dev->hw->cmq_init) { 903 ret = hr_dev->hw->cmq_init(hr_dev); 904 if (ret) { 905 dev_err(dev, "Init RoCE Command Queue failed!\n"); 906 return ret; 907 } 908 } 909 910 ret = hr_dev->hw->hw_profile(hr_dev); 911 if (ret) { 912 dev_err(dev, "Get RoCE engine profile failed!\n"); 913 goto error_failed_cmd_init; 914 } 915 916 ret = hns_roce_cmd_init(hr_dev); 917 if (ret) { 918 dev_err(dev, "cmd init failed!\n"); 919 goto error_failed_cmd_init; 920 } 921 922 /* EQ depends on poll mode, event mode depends on EQ */ 923 ret = hr_dev->hw->init_eq(hr_dev); 924 if (ret) { 925 dev_err(dev, "eq init failed!\n"); 926 goto error_failed_eq_table; 927 } 928 929 if (hr_dev->cmd_mod) { 930 ret = hns_roce_cmd_use_events(hr_dev); 931 if (ret) 932 dev_warn(dev, 933 "Cmd event mode failed, set back to poll!\n"); 934 } 935 936 ret = hns_roce_init_hem(hr_dev); 937 if (ret) { 938 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 939 goto error_failed_init_hem; 940 } 941 942 ret = hns_roce_setup_hca(hr_dev); 943 if (ret) { 944 dev_err(dev, "setup hca failed!\n"); 945 goto error_failed_setup_hca; 946 } 947 948 if (hr_dev->hw->hw_init) { 949 ret = hr_dev->hw->hw_init(hr_dev); 950 if (ret) { 951 dev_err(dev, "hw_init failed!\n"); 952 goto error_failed_engine_init; 953 } 954 } 955 956 INIT_LIST_HEAD(&hr_dev->qp_list); 957 spin_lock_init(&hr_dev->qp_list_lock); 958 INIT_LIST_HEAD(&hr_dev->dip_list); 959 spin_lock_init(&hr_dev->dip_list_lock); 960 961 ret = hns_roce_register_device(hr_dev); 962 if (ret) 963 goto error_failed_register_device; 964 965 return 0; 966 967 error_failed_register_device: 968 if (hr_dev->hw->hw_exit) 969 hr_dev->hw->hw_exit(hr_dev); 970 971 error_failed_engine_init: 972 hns_roce_cleanup_bitmap(hr_dev); 973 974 error_failed_setup_hca: 975 hns_roce_cleanup_hem(hr_dev); 976 977 error_failed_init_hem: 978 if (hr_dev->cmd_mod) 979 hns_roce_cmd_use_polling(hr_dev); 980 hr_dev->hw->cleanup_eq(hr_dev); 981 982 error_failed_eq_table: 983 hns_roce_cmd_cleanup(hr_dev); 984 985 error_failed_cmd_init: 986 if (hr_dev->hw->cmq_exit) 987 hr_dev->hw->cmq_exit(hr_dev); 988 989 return ret; 990 } 991 992 void hns_roce_exit(struct hns_roce_dev *hr_dev) 993 { 994 hns_roce_unregister_device(hr_dev); 995 996 if (hr_dev->hw->hw_exit) 997 hr_dev->hw->hw_exit(hr_dev); 998 hns_roce_cleanup_bitmap(hr_dev); 999 hns_roce_cleanup_hem(hr_dev); 1000 1001 if (hr_dev->cmd_mod) 1002 hns_roce_cmd_use_polling(hr_dev); 1003 1004 hr_dev->hw->cleanup_eq(hr_dev); 1005 hns_roce_cmd_cleanup(hr_dev); 1006 if (hr_dev->hw->cmq_exit) 1007 hr_dev->hw->cmq_exit(hr_dev); 1008 } 1009 1010 MODULE_LICENSE("Dual BSD/GPL"); 1011 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 1012 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1013 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1014 MODULE_DESCRIPTION("HNS RoCE Driver"); 1015