1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <rdma/ib_addr.h> 38 #include <rdma/ib_smi.h> 39 #include <rdma/ib_user_verbs.h> 40 #include <rdma/ib_cache.h> 41 #include "hns_roce_common.h" 42 #include "hns_roce_device.h" 43 #include "hns_roce_hem.h" 44 45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, u8 *addr) 46 { 47 u8 phy_port; 48 u32 i; 49 50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 51 return 0; 52 53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 54 return 0; 55 56 for (i = 0; i < ETH_ALEN; i++) 57 hr_dev->dev_addr[port][i] = addr[i]; 58 59 phy_port = hr_dev->iboe.phy_port[port]; 60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 61 } 62 63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 64 { 65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 66 u32 port = attr->port_num - 1; 67 int ret; 68 69 if (port >= hr_dev->caps.num_ports) 70 return -EINVAL; 71 72 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 73 74 return ret; 75 } 76 77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u32 port = attr->port_num - 1; 81 int ret; 82 83 if (port >= hr_dev->caps.num_ports) 84 return -EINVAL; 85 86 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, NULL, NULL); 87 88 return ret; 89 } 90 91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port, 92 unsigned long event) 93 { 94 struct device *dev = hr_dev->dev; 95 struct net_device *netdev; 96 int ret = 0; 97 98 netdev = hr_dev->iboe.netdevs[port]; 99 if (!netdev) { 100 dev_err(dev, "Can't find netdev on port(%u)!\n", port); 101 return -ENODEV; 102 } 103 104 switch (event) { 105 case NETDEV_UP: 106 case NETDEV_CHANGE: 107 case NETDEV_REGISTER: 108 case NETDEV_CHANGEADDR: 109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 110 break; 111 case NETDEV_DOWN: 112 /* 113 * In v1 engine, only support all ports closed together. 114 */ 115 break; 116 default: 117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 118 break; 119 } 120 121 return ret; 122 } 123 124 static int hns_roce_netdev_event(struct notifier_block *self, 125 unsigned long event, void *ptr) 126 { 127 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 128 struct hns_roce_ib_iboe *iboe = NULL; 129 struct hns_roce_dev *hr_dev = NULL; 130 int ret; 131 u32 port; 132 133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 134 iboe = &hr_dev->iboe; 135 136 for (port = 0; port < hr_dev->caps.num_ports; port++) { 137 if (dev == iboe->netdevs[port]) { 138 ret = handle_en_event(hr_dev, port, event); 139 if (ret) 140 return NOTIFY_DONE; 141 break; 142 } 143 } 144 145 return NOTIFY_DONE; 146 } 147 148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 149 { 150 int ret; 151 u8 i; 152 153 for (i = 0; i < hr_dev->caps.num_ports; i++) { 154 if (hr_dev->hw->set_mtu) 155 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 156 hr_dev->caps.max_mtu); 157 ret = hns_roce_set_mac(hr_dev, i, 158 hr_dev->iboe.netdevs[i]->dev_addr); 159 if (ret) 160 return ret; 161 } 162 163 return 0; 164 } 165 166 static int hns_roce_query_device(struct ib_device *ib_dev, 167 struct ib_device_attr *props, 168 struct ib_udata *uhw) 169 { 170 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 171 172 memset(props, 0, sizeof(*props)); 173 174 props->fw_ver = hr_dev->caps.fw_ver; 175 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 176 props->max_mr_size = (u64)(~(0ULL)); 177 props->page_size_cap = hr_dev->caps.page_size_cap; 178 props->vendor_id = hr_dev->vendor_id; 179 props->vendor_part_id = hr_dev->vendor_part_id; 180 props->hw_ver = hr_dev->hw_rev; 181 props->max_qp = hr_dev->caps.num_qps; 182 props->max_qp_wr = hr_dev->caps.max_wqes; 183 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 184 IB_DEVICE_RC_RNR_NAK_GEN; 185 props->max_send_sge = hr_dev->caps.max_sq_sg; 186 props->max_recv_sge = hr_dev->caps.max_rq_sg; 187 props->max_sge_rd = 1; 188 props->max_cq = hr_dev->caps.num_cqs; 189 props->max_cqe = hr_dev->caps.max_cqes; 190 props->max_mr = hr_dev->caps.num_mtpts; 191 props->max_pd = hr_dev->caps.num_pds; 192 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 193 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 194 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 195 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 196 props->max_pkeys = 1; 197 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 198 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 199 props->max_srq = hr_dev->caps.num_srqs; 200 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 201 props->max_srq_sge = hr_dev->caps.max_srq_sges; 202 } 203 204 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && 205 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 206 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 207 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 208 } 209 210 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 211 props->device_cap_flags |= IB_DEVICE_XRC; 212 213 return 0; 214 } 215 216 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num, 217 struct ib_port_attr *props) 218 { 219 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 220 struct device *dev = hr_dev->dev; 221 struct net_device *net_dev; 222 unsigned long flags; 223 enum ib_mtu mtu; 224 u32 port; 225 226 port = port_num - 1; 227 228 /* props being zeroed by the caller, avoid zeroing it here */ 229 230 props->max_mtu = hr_dev->caps.max_mtu; 231 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 232 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 233 IB_PORT_VENDOR_CLASS_SUP | 234 IB_PORT_BOOT_MGMT_SUP; 235 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 236 props->pkey_tbl_len = 1; 237 props->active_width = IB_WIDTH_4X; 238 props->active_speed = 1; 239 240 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 241 242 net_dev = hr_dev->iboe.netdevs[port]; 243 if (!net_dev) { 244 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 245 dev_err(dev, "Find netdev %u failed!\n", port); 246 return -EINVAL; 247 } 248 249 mtu = iboe_get_mtu(net_dev->mtu); 250 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 251 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 252 IB_PORT_ACTIVE : 253 IB_PORT_DOWN; 254 props->phys_state = props->state == IB_PORT_ACTIVE ? 255 IB_PORT_PHYS_STATE_LINK_UP : 256 IB_PORT_PHYS_STATE_DISABLED; 257 258 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 259 260 return 0; 261 } 262 263 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 264 u32 port_num) 265 { 266 return IB_LINK_LAYER_ETHERNET; 267 } 268 269 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index, 270 u16 *pkey) 271 { 272 *pkey = PKEY_ID; 273 274 return 0; 275 } 276 277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 278 struct ib_device_modify *props) 279 { 280 unsigned long flags; 281 282 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 283 return -EOPNOTSUPP; 284 285 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 286 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 287 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 288 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 289 } 290 291 return 0; 292 } 293 294 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 295 struct ib_udata *udata) 296 { 297 int ret; 298 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 299 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 300 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 301 302 if (!hr_dev->active) 303 return -EAGAIN; 304 305 resp.qp_tab_size = hr_dev->caps.num_qps; 306 resp.srq_tab_size = hr_dev->caps.num_srqs; 307 308 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 309 if (ret) 310 goto error_fail_uar_alloc; 311 312 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 313 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 314 INIT_LIST_HEAD(&context->page_list); 315 mutex_init(&context->page_mutex); 316 } 317 318 resp.cqe_size = hr_dev->caps.cqe_sz; 319 320 ret = ib_copy_to_udata(udata, &resp, 321 min(udata->outlen, sizeof(resp))); 322 if (ret) 323 goto error_fail_copy_to_udata; 324 325 return 0; 326 327 error_fail_copy_to_udata: 328 hns_roce_uar_free(hr_dev, &context->uar); 329 330 error_fail_uar_alloc: 331 return ret; 332 } 333 334 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 335 { 336 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 337 338 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 339 } 340 341 static int hns_roce_mmap(struct ib_ucontext *context, 342 struct vm_area_struct *vma) 343 { 344 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 345 346 switch (vma->vm_pgoff) { 347 case 0: 348 return rdma_user_mmap_io(context, vma, 349 to_hr_ucontext(context)->uar.pfn, 350 PAGE_SIZE, 351 pgprot_noncached(vma->vm_page_prot), 352 NULL); 353 354 /* vm_pgoff: 1 -- TPTR */ 355 case 1: 356 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 357 return -EINVAL; 358 /* 359 * FIXME: using io_remap_pfn_range on the dma address returned 360 * by dma_alloc_coherent is totally wrong. 361 */ 362 return rdma_user_mmap_io(context, vma, 363 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 364 hr_dev->tptr_size, 365 vma->vm_page_prot, 366 NULL); 367 368 default: 369 return -EINVAL; 370 } 371 } 372 373 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num, 374 struct ib_port_immutable *immutable) 375 { 376 struct ib_port_attr attr; 377 int ret; 378 379 ret = ib_query_port(ib_dev, port_num, &attr); 380 if (ret) 381 return ret; 382 383 immutable->pkey_tbl_len = attr.pkey_tbl_len; 384 immutable->gid_tbl_len = attr.gid_tbl_len; 385 386 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 387 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 388 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 389 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 390 391 return 0; 392 } 393 394 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 395 { 396 } 397 398 static void hns_roce_get_fw_ver(struct ib_device *device, char *str) 399 { 400 u64 fw_ver = to_hr_dev(device)->caps.fw_ver; 401 unsigned int major, minor, sub_minor; 402 403 major = upper_32_bits(fw_ver); 404 minor = high_16_bits(lower_32_bits(fw_ver)); 405 sub_minor = low_16_bits(fw_ver); 406 407 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor, 408 sub_minor); 409 } 410 411 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 412 { 413 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 414 415 hr_dev->active = false; 416 unregister_netdevice_notifier(&iboe->nb); 417 ib_unregister_device(&hr_dev->ib_dev); 418 } 419 420 static const struct ib_device_ops hns_roce_dev_ops = { 421 .owner = THIS_MODULE, 422 .driver_id = RDMA_DRIVER_HNS, 423 .uverbs_abi_ver = 1, 424 .uverbs_no_driver_id_binding = 1, 425 426 .get_dev_fw_str = hns_roce_get_fw_ver, 427 .add_gid = hns_roce_add_gid, 428 .alloc_pd = hns_roce_alloc_pd, 429 .alloc_ucontext = hns_roce_alloc_ucontext, 430 .create_ah = hns_roce_create_ah, 431 .create_user_ah = hns_roce_create_ah, 432 .create_cq = hns_roce_create_cq, 433 .create_qp = hns_roce_create_qp, 434 .dealloc_pd = hns_roce_dealloc_pd, 435 .dealloc_ucontext = hns_roce_dealloc_ucontext, 436 .del_gid = hns_roce_del_gid, 437 .dereg_mr = hns_roce_dereg_mr, 438 .destroy_ah = hns_roce_destroy_ah, 439 .destroy_cq = hns_roce_destroy_cq, 440 .disassociate_ucontext = hns_roce_disassociate_ucontext, 441 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 442 .get_dma_mr = hns_roce_get_dma_mr, 443 .get_link_layer = hns_roce_get_link_layer, 444 .get_port_immutable = hns_roce_port_immutable, 445 .mmap = hns_roce_mmap, 446 .modify_device = hns_roce_modify_device, 447 .modify_qp = hns_roce_modify_qp, 448 .query_ah = hns_roce_query_ah, 449 .query_device = hns_roce_query_device, 450 .query_pkey = hns_roce_query_pkey, 451 .query_port = hns_roce_query_port, 452 .reg_user_mr = hns_roce_reg_user_mr, 453 454 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 455 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 456 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 457 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 458 }; 459 460 static const struct ib_device_ops hns_roce_dev_mr_ops = { 461 .rereg_user_mr = hns_roce_rereg_user_mr, 462 }; 463 464 static const struct ib_device_ops hns_roce_dev_mw_ops = { 465 .alloc_mw = hns_roce_alloc_mw, 466 .dealloc_mw = hns_roce_dealloc_mw, 467 468 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 469 }; 470 471 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 472 .alloc_mr = hns_roce_alloc_mr, 473 .map_mr_sg = hns_roce_map_mr_sg, 474 }; 475 476 static const struct ib_device_ops hns_roce_dev_srq_ops = { 477 .create_srq = hns_roce_create_srq, 478 .destroy_srq = hns_roce_destroy_srq, 479 480 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 481 }; 482 483 static const struct ib_device_ops hns_roce_dev_xrcd_ops = { 484 .alloc_xrcd = hns_roce_alloc_xrcd, 485 .dealloc_xrcd = hns_roce_dealloc_xrcd, 486 487 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), 488 }; 489 490 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 491 { 492 int ret; 493 struct hns_roce_ib_iboe *iboe = NULL; 494 struct ib_device *ib_dev = NULL; 495 struct device *dev = hr_dev->dev; 496 unsigned int i; 497 498 iboe = &hr_dev->iboe; 499 spin_lock_init(&iboe->lock); 500 501 ib_dev = &hr_dev->ib_dev; 502 503 ib_dev->node_type = RDMA_NODE_IB_CA; 504 ib_dev->dev.parent = dev; 505 506 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 507 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 508 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 509 510 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) 511 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 512 513 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) 514 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 515 516 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 517 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 518 519 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 520 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 521 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 522 } 523 524 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 525 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); 526 527 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 528 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 529 for (i = 0; i < hr_dev->caps.num_ports; i++) { 530 if (!hr_dev->iboe.netdevs[i]) 531 continue; 532 533 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 534 i + 1); 535 if (ret) 536 return ret; 537 } 538 dma_set_max_seg_size(dev, UINT_MAX); 539 ret = ib_register_device(ib_dev, "hns_%d", dev); 540 if (ret) { 541 dev_err(dev, "ib_register_device failed!\n"); 542 return ret; 543 } 544 545 ret = hns_roce_setup_mtu_mac(hr_dev); 546 if (ret) { 547 dev_err(dev, "setup_mtu_mac failed!\n"); 548 goto error_failed_setup_mtu_mac; 549 } 550 551 iboe->nb.notifier_call = hns_roce_netdev_event; 552 ret = register_netdevice_notifier(&iboe->nb); 553 if (ret) { 554 dev_err(dev, "register_netdevice_notifier failed!\n"); 555 goto error_failed_setup_mtu_mac; 556 } 557 558 hr_dev->active = true; 559 return 0; 560 561 error_failed_setup_mtu_mac: 562 ib_unregister_device(ib_dev); 563 564 return ret; 565 } 566 567 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 568 { 569 struct device *dev = hr_dev->dev; 570 int ret; 571 572 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 573 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 574 hr_dev->caps.num_mtpts, 1); 575 if (ret) { 576 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 577 return ret; 578 } 579 580 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 581 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 582 hr_dev->caps.num_qps, 1); 583 if (ret) { 584 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 585 goto err_unmap_dmpt; 586 } 587 588 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 589 HEM_TYPE_IRRL, 590 hr_dev->caps.irrl_entry_sz * 591 hr_dev->caps.max_qp_init_rdma, 592 hr_dev->caps.num_qps, 1); 593 if (ret) { 594 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 595 goto err_unmap_qp; 596 } 597 598 if (hr_dev->caps.trrl_entry_sz) { 599 ret = hns_roce_init_hem_table(hr_dev, 600 &hr_dev->qp_table.trrl_table, 601 HEM_TYPE_TRRL, 602 hr_dev->caps.trrl_entry_sz * 603 hr_dev->caps.max_qp_dest_rdma, 604 hr_dev->caps.num_qps, 1); 605 if (ret) { 606 dev_err(dev, 607 "Failed to init trrl_table memory, aborting.\n"); 608 goto err_unmap_irrl; 609 } 610 } 611 612 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 613 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 614 hr_dev->caps.num_cqs, 1); 615 if (ret) { 616 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 617 goto err_unmap_trrl; 618 } 619 620 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 621 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 622 HEM_TYPE_SRQC, 623 hr_dev->caps.srqc_entry_sz, 624 hr_dev->caps.num_srqs, 1); 625 if (ret) { 626 dev_err(dev, 627 "Failed to init SRQ context memory, aborting.\n"); 628 goto err_unmap_cq; 629 } 630 } 631 632 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 633 ret = hns_roce_init_hem_table(hr_dev, 634 &hr_dev->qp_table.sccc_table, 635 HEM_TYPE_SCCC, 636 hr_dev->caps.sccc_sz, 637 hr_dev->caps.num_qps, 1); 638 if (ret) { 639 dev_err(dev, 640 "Failed to init SCC context memory, aborting.\n"); 641 goto err_unmap_srq; 642 } 643 } 644 645 if (hr_dev->caps.qpc_timer_entry_sz) { 646 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 647 HEM_TYPE_QPC_TIMER, 648 hr_dev->caps.qpc_timer_entry_sz, 649 hr_dev->caps.num_qpc_timer, 1); 650 if (ret) { 651 dev_err(dev, 652 "Failed to init QPC timer memory, aborting.\n"); 653 goto err_unmap_ctx; 654 } 655 } 656 657 if (hr_dev->caps.cqc_timer_entry_sz) { 658 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 659 HEM_TYPE_CQC_TIMER, 660 hr_dev->caps.cqc_timer_entry_sz, 661 hr_dev->caps.num_cqc_timer, 1); 662 if (ret) { 663 dev_err(dev, 664 "Failed to init CQC timer memory, aborting.\n"); 665 goto err_unmap_qpc_timer; 666 } 667 } 668 669 if (hr_dev->caps.gmv_entry_sz) { 670 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table, 671 HEM_TYPE_GMV, 672 hr_dev->caps.gmv_entry_sz, 673 hr_dev->caps.gmv_entry_num, 1); 674 if (ret) { 675 dev_err(dev, 676 "failed to init gmv table memory, ret = %d\n", 677 ret); 678 goto err_unmap_cqc_timer; 679 } 680 } 681 682 return 0; 683 684 err_unmap_cqc_timer: 685 if (hr_dev->caps.cqc_timer_entry_sz) 686 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table); 687 688 err_unmap_qpc_timer: 689 if (hr_dev->caps.qpc_timer_entry_sz) 690 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 691 692 err_unmap_ctx: 693 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 694 hns_roce_cleanup_hem_table(hr_dev, 695 &hr_dev->qp_table.sccc_table); 696 err_unmap_srq: 697 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 698 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 699 700 err_unmap_cq: 701 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 702 703 err_unmap_trrl: 704 if (hr_dev->caps.trrl_entry_sz) 705 hns_roce_cleanup_hem_table(hr_dev, 706 &hr_dev->qp_table.trrl_table); 707 708 err_unmap_irrl: 709 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 710 711 err_unmap_qp: 712 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 713 714 err_unmap_dmpt: 715 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 716 717 return ret; 718 } 719 720 /** 721 * hns_roce_setup_hca - setup host channel adapter 722 * @hr_dev: pointer to hns roce device 723 * Return : int 724 */ 725 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 726 { 727 struct device *dev = hr_dev->dev; 728 int ret; 729 730 spin_lock_init(&hr_dev->sm_lock); 731 spin_lock_init(&hr_dev->bt_cmd_lock); 732 733 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 734 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 735 INIT_LIST_HEAD(&hr_dev->pgdir_list); 736 mutex_init(&hr_dev->pgdir_mutex); 737 } 738 739 ret = hns_roce_init_uar_table(hr_dev); 740 if (ret) { 741 dev_err(dev, "Failed to initialize uar table. aborting\n"); 742 return ret; 743 } 744 745 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 746 if (ret) { 747 dev_err(dev, "Failed to allocate priv_uar.\n"); 748 goto err_uar_table_free; 749 } 750 751 ret = hns_roce_init_pd_table(hr_dev); 752 if (ret) { 753 dev_err(dev, "Failed to init protected domain table.\n"); 754 goto err_uar_alloc_free; 755 } 756 757 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) { 758 ret = hns_roce_init_xrcd_table(hr_dev); 759 if (ret) { 760 dev_err(dev, "failed to init xrcd table, ret = %d.\n", 761 ret); 762 goto err_pd_table_free; 763 } 764 } 765 766 ret = hns_roce_init_mr_table(hr_dev); 767 if (ret) { 768 dev_err(dev, "Failed to init memory region table.\n"); 769 goto err_xrcd_table_free; 770 } 771 772 hns_roce_init_cq_table(hr_dev); 773 774 ret = hns_roce_init_qp_table(hr_dev); 775 if (ret) { 776 dev_err(dev, "Failed to init queue pair table.\n"); 777 goto err_cq_table_free; 778 } 779 780 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 781 ret = hns_roce_init_srq_table(hr_dev); 782 if (ret) { 783 dev_err(dev, 784 "Failed to init share receive queue table.\n"); 785 goto err_qp_table_free; 786 } 787 } 788 789 return 0; 790 791 err_qp_table_free: 792 hns_roce_cleanup_qp_table(hr_dev); 793 794 err_cq_table_free: 795 hns_roce_cleanup_cq_table(hr_dev); 796 hns_roce_cleanup_mr_table(hr_dev); 797 798 err_xrcd_table_free: 799 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 800 hns_roce_cleanup_xrcd_table(hr_dev); 801 802 err_pd_table_free: 803 hns_roce_cleanup_pd_table(hr_dev); 804 805 err_uar_alloc_free: 806 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 807 808 err_uar_table_free: 809 hns_roce_cleanup_uar_table(hr_dev); 810 return ret; 811 } 812 813 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 814 { 815 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 816 unsigned long flags; 817 818 spin_lock_irqsave(&hr_cq->lock, flags); 819 if (cq->comp_handler) { 820 if (!hr_cq->is_armed) { 821 hr_cq->is_armed = 1; 822 list_add_tail(&hr_cq->node, cq_list); 823 } 824 } 825 spin_unlock_irqrestore(&hr_cq->lock, flags); 826 } 827 828 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 829 { 830 struct hns_roce_qp *hr_qp; 831 struct hns_roce_cq *hr_cq; 832 struct list_head cq_list; 833 unsigned long flags_qp; 834 unsigned long flags; 835 836 INIT_LIST_HEAD(&cq_list); 837 838 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 839 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 840 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 841 if (hr_qp->sq.tail != hr_qp->sq.head) 842 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 843 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 844 845 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 846 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 847 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 848 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 849 } 850 851 list_for_each_entry(hr_cq, &cq_list, node) 852 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 853 854 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 855 } 856 857 int hns_roce_init(struct hns_roce_dev *hr_dev) 858 { 859 struct device *dev = hr_dev->dev; 860 int ret; 861 862 if (hr_dev->hw->reset) { 863 ret = hr_dev->hw->reset(hr_dev, true); 864 if (ret) { 865 dev_err(dev, "Reset RoCE engine failed!\n"); 866 return ret; 867 } 868 } 869 hr_dev->is_reset = false; 870 871 if (hr_dev->hw->cmq_init) { 872 ret = hr_dev->hw->cmq_init(hr_dev); 873 if (ret) { 874 dev_err(dev, "Init RoCE Command Queue failed!\n"); 875 goto error_failed_cmq_init; 876 } 877 } 878 879 ret = hr_dev->hw->hw_profile(hr_dev); 880 if (ret) { 881 dev_err(dev, "Get RoCE engine profile failed!\n"); 882 goto error_failed_cmd_init; 883 } 884 885 ret = hns_roce_cmd_init(hr_dev); 886 if (ret) { 887 dev_err(dev, "cmd init failed!\n"); 888 goto error_failed_cmd_init; 889 } 890 891 /* EQ depends on poll mode, event mode depends on EQ */ 892 ret = hr_dev->hw->init_eq(hr_dev); 893 if (ret) { 894 dev_err(dev, "eq init failed!\n"); 895 goto error_failed_eq_table; 896 } 897 898 if (hr_dev->cmd_mod) { 899 ret = hns_roce_cmd_use_events(hr_dev); 900 if (ret) { 901 dev_warn(dev, 902 "Cmd event mode failed, set back to poll!\n"); 903 hns_roce_cmd_use_polling(hr_dev); 904 } 905 } 906 907 ret = hns_roce_init_hem(hr_dev); 908 if (ret) { 909 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 910 goto error_failed_init_hem; 911 } 912 913 ret = hns_roce_setup_hca(hr_dev); 914 if (ret) { 915 dev_err(dev, "setup hca failed!\n"); 916 goto error_failed_setup_hca; 917 } 918 919 if (hr_dev->hw->hw_init) { 920 ret = hr_dev->hw->hw_init(hr_dev); 921 if (ret) { 922 dev_err(dev, "hw_init failed!\n"); 923 goto error_failed_engine_init; 924 } 925 } 926 927 INIT_LIST_HEAD(&hr_dev->qp_list); 928 spin_lock_init(&hr_dev->qp_list_lock); 929 INIT_LIST_HEAD(&hr_dev->dip_list); 930 spin_lock_init(&hr_dev->dip_list_lock); 931 932 ret = hns_roce_register_device(hr_dev); 933 if (ret) 934 goto error_failed_register_device; 935 936 return 0; 937 938 error_failed_register_device: 939 if (hr_dev->hw->hw_exit) 940 hr_dev->hw->hw_exit(hr_dev); 941 942 error_failed_engine_init: 943 hns_roce_cleanup_bitmap(hr_dev); 944 945 error_failed_setup_hca: 946 hns_roce_cleanup_hem(hr_dev); 947 948 error_failed_init_hem: 949 if (hr_dev->cmd_mod) 950 hns_roce_cmd_use_polling(hr_dev); 951 hr_dev->hw->cleanup_eq(hr_dev); 952 953 error_failed_eq_table: 954 hns_roce_cmd_cleanup(hr_dev); 955 956 error_failed_cmd_init: 957 if (hr_dev->hw->cmq_exit) 958 hr_dev->hw->cmq_exit(hr_dev); 959 960 error_failed_cmq_init: 961 if (hr_dev->hw->reset) { 962 if (hr_dev->hw->reset(hr_dev, false)) 963 dev_err(dev, "Dereset RoCE engine failed!\n"); 964 } 965 966 return ret; 967 } 968 969 void hns_roce_exit(struct hns_roce_dev *hr_dev) 970 { 971 hns_roce_unregister_device(hr_dev); 972 973 if (hr_dev->hw->hw_exit) 974 hr_dev->hw->hw_exit(hr_dev); 975 hns_roce_cleanup_bitmap(hr_dev); 976 hns_roce_cleanup_hem(hr_dev); 977 978 if (hr_dev->cmd_mod) 979 hns_roce_cmd_use_polling(hr_dev); 980 981 hr_dev->hw->cleanup_eq(hr_dev); 982 hns_roce_cmd_cleanup(hr_dev); 983 if (hr_dev->hw->cmq_exit) 984 hr_dev->hw->cmq_exit(hr_dev); 985 if (hr_dev->hw->reset) 986 hr_dev->hw->reset(hr_dev, false); 987 } 988 989 MODULE_LICENSE("Dual BSD/GPL"); 990 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 991 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 992 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 993 MODULE_DESCRIPTION("HNS RoCE Driver"); 994