1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 EXPORT_SYMBOL_GPL(hns_get_gid_index); 61 62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 63 { 64 u8 phy_port; 65 u32 i = 0; 66 67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM)) 68 return 0; 69 70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++) 71 hr_dev->dev_addr[port][i] = addr[i]; 72 73 phy_port = hr_dev->iboe.phy_port[port]; 74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 75 } 76 77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 78 { 79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 80 u8 port = attr->port_num - 1; 81 unsigned long flags; 82 int ret; 83 84 if (port >= hr_dev->caps.num_ports) 85 return -EINVAL; 86 87 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 88 89 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 90 91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 92 93 return ret; 94 } 95 96 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 97 { 98 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 99 struct ib_gid_attr zattr = { }; 100 u8 port = attr->port_num - 1; 101 unsigned long flags; 102 int ret; 103 104 if (port >= hr_dev->caps.num_ports) 105 return -EINVAL; 106 107 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 108 109 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 110 111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 112 113 return ret; 114 } 115 116 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 117 unsigned long event) 118 { 119 struct device *dev = hr_dev->dev; 120 struct net_device *netdev; 121 int ret = 0; 122 123 netdev = hr_dev->iboe.netdevs[port]; 124 if (!netdev) { 125 dev_err(dev, "port(%d) can't find netdev\n", port); 126 return -ENODEV; 127 } 128 129 switch (event) { 130 case NETDEV_UP: 131 case NETDEV_CHANGE: 132 case NETDEV_REGISTER: 133 case NETDEV_CHANGEADDR: 134 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 135 break; 136 case NETDEV_DOWN: 137 /* 138 * In v1 engine, only support all ports closed together. 139 */ 140 break; 141 default: 142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 143 break; 144 } 145 146 return ret; 147 } 148 149 static int hns_roce_netdev_event(struct notifier_block *self, 150 unsigned long event, void *ptr) 151 { 152 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 153 struct hns_roce_ib_iboe *iboe = NULL; 154 struct hns_roce_dev *hr_dev = NULL; 155 u8 port = 0; 156 int ret = 0; 157 158 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 159 iboe = &hr_dev->iboe; 160 161 for (port = 0; port < hr_dev->caps.num_ports; port++) { 162 if (dev == iboe->netdevs[port]) { 163 ret = handle_en_event(hr_dev, port, event); 164 if (ret) 165 return NOTIFY_DONE; 166 break; 167 } 168 } 169 170 return NOTIFY_DONE; 171 } 172 173 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 174 { 175 int ret; 176 u8 i; 177 178 for (i = 0; i < hr_dev->caps.num_ports; i++) { 179 if (hr_dev->hw->set_mtu) 180 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 181 hr_dev->caps.max_mtu); 182 ret = hns_roce_set_mac(hr_dev, i, 183 hr_dev->iboe.netdevs[i]->dev_addr); 184 if (ret) 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int hns_roce_query_device(struct ib_device *ib_dev, 192 struct ib_device_attr *props, 193 struct ib_udata *uhw) 194 { 195 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 196 197 memset(props, 0, sizeof(*props)); 198 199 props->fw_ver = hr_dev->caps.fw_ver; 200 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 201 props->max_mr_size = (u64)(~(0ULL)); 202 props->page_size_cap = hr_dev->caps.page_size_cap; 203 props->vendor_id = hr_dev->vendor_id; 204 props->vendor_part_id = hr_dev->vendor_part_id; 205 props->hw_ver = hr_dev->hw_rev; 206 props->max_qp = hr_dev->caps.num_qps; 207 props->max_qp_wr = hr_dev->caps.max_wqes; 208 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 209 IB_DEVICE_RC_RNR_NAK_GEN; 210 props->max_send_sge = hr_dev->caps.max_sq_sg; 211 props->max_recv_sge = hr_dev->caps.max_rq_sg; 212 props->max_sge_rd = 1; 213 props->max_cq = hr_dev->caps.num_cqs; 214 props->max_cqe = hr_dev->caps.max_cqes; 215 props->max_mr = hr_dev->caps.num_mtpts; 216 props->max_pd = hr_dev->caps.num_pds; 217 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 218 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 219 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 220 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 221 props->max_pkeys = 1; 222 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 223 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 224 props->max_srq = hr_dev->caps.max_srqs; 225 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 226 props->max_srq_sge = hr_dev->caps.max_srq_sges; 227 } 228 229 return 0; 230 } 231 232 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev, 233 u8 port_num) 234 { 235 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 236 struct net_device *ndev; 237 238 if (port_num < 1 || port_num > hr_dev->caps.num_ports) 239 return NULL; 240 241 rcu_read_lock(); 242 243 ndev = hr_dev->iboe.netdevs[port_num - 1]; 244 if (ndev) 245 dev_hold(ndev); 246 247 rcu_read_unlock(); 248 return ndev; 249 } 250 251 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 252 struct ib_port_attr *props) 253 { 254 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 255 struct device *dev = hr_dev->dev; 256 struct net_device *net_dev; 257 unsigned long flags; 258 enum ib_mtu mtu; 259 u8 port; 260 261 assert(port_num > 0); 262 port = port_num - 1; 263 264 /* props being zeroed by the caller, avoid zeroing it here */ 265 266 props->max_mtu = hr_dev->caps.max_mtu; 267 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 268 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 269 IB_PORT_VENDOR_CLASS_SUP | 270 IB_PORT_BOOT_MGMT_SUP; 271 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 272 props->pkey_tbl_len = 1; 273 props->active_width = IB_WIDTH_4X; 274 props->active_speed = 1; 275 276 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 277 278 net_dev = hr_dev->iboe.netdevs[port]; 279 if (!net_dev) { 280 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 281 dev_err(dev, "find netdev %d failed!\r\n", port); 282 return -EINVAL; 283 } 284 285 mtu = iboe_get_mtu(net_dev->mtu); 286 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 287 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 288 IB_PORT_ACTIVE : IB_PORT_DOWN; 289 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3; 290 291 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 292 293 return 0; 294 } 295 296 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 297 u8 port_num) 298 { 299 return IB_LINK_LAYER_ETHERNET; 300 } 301 302 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 303 u16 *pkey) 304 { 305 *pkey = PKEY_ID; 306 307 return 0; 308 } 309 310 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 311 struct ib_device_modify *props) 312 { 313 unsigned long flags; 314 315 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 316 return -EOPNOTSUPP; 317 318 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 319 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 320 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 321 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 322 } 323 324 return 0; 325 } 326 327 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, 328 struct ib_port_modify *props) 329 { 330 return 0; 331 } 332 333 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev, 334 struct ib_udata *udata) 335 { 336 int ret = 0; 337 struct hns_roce_ucontext *context; 338 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 339 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 340 341 if (!hr_dev->active) 342 return ERR_PTR(-EAGAIN); 343 344 resp.qp_tab_size = hr_dev->caps.num_qps; 345 346 context = kmalloc(sizeof(*context), GFP_KERNEL); 347 if (!context) 348 return ERR_PTR(-ENOMEM); 349 350 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 351 if (ret) 352 goto error_fail_uar_alloc; 353 354 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 355 INIT_LIST_HEAD(&context->page_list); 356 mutex_init(&context->page_mutex); 357 } 358 359 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 360 if (ret) 361 goto error_fail_copy_to_udata; 362 363 return &context->ibucontext; 364 365 error_fail_copy_to_udata: 366 hns_roce_uar_free(hr_dev, &context->uar); 367 368 error_fail_uar_alloc: 369 kfree(context); 370 371 return ERR_PTR(ret); 372 } 373 374 static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 375 { 376 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 377 378 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 379 kfree(context); 380 381 return 0; 382 } 383 384 static int hns_roce_mmap(struct ib_ucontext *context, 385 struct vm_area_struct *vma) 386 { 387 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 388 389 switch (vma->vm_pgoff) { 390 case 0: 391 return rdma_user_mmap_io(context, vma, 392 to_hr_ucontext(context)->uar.pfn, 393 PAGE_SIZE, 394 pgprot_noncached(vma->vm_page_prot)); 395 396 /* vm_pgoff: 1 -- TPTR */ 397 case 1: 398 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 399 return -EINVAL; 400 /* 401 * FIXME: using io_remap_pfn_range on the dma address returned 402 * by dma_alloc_coherent is totally wrong. 403 */ 404 return rdma_user_mmap_io(context, vma, 405 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 406 hr_dev->tptr_size, 407 vma->vm_page_prot); 408 409 default: 410 return -EINVAL; 411 } 412 } 413 414 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 415 struct ib_port_immutable *immutable) 416 { 417 struct ib_port_attr attr; 418 int ret; 419 420 ret = ib_query_port(ib_dev, port_num, &attr); 421 if (ret) 422 return ret; 423 424 immutable->pkey_tbl_len = attr.pkey_tbl_len; 425 immutable->gid_tbl_len = attr.gid_tbl_len; 426 427 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 428 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 429 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 430 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 431 432 return 0; 433 } 434 435 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 436 { 437 } 438 439 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 440 { 441 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 442 443 hr_dev->active = false; 444 unregister_netdevice_notifier(&iboe->nb); 445 ib_unregister_device(&hr_dev->ib_dev); 446 } 447 448 static const struct ib_device_ops hns_roce_dev_ops = { 449 .add_gid = hns_roce_add_gid, 450 .alloc_pd = hns_roce_alloc_pd, 451 .alloc_ucontext = hns_roce_alloc_ucontext, 452 .create_ah = hns_roce_create_ah, 453 .create_cq = hns_roce_ib_create_cq, 454 .create_qp = hns_roce_create_qp, 455 .dealloc_pd = hns_roce_dealloc_pd, 456 .dealloc_ucontext = hns_roce_dealloc_ucontext, 457 .del_gid = hns_roce_del_gid, 458 .dereg_mr = hns_roce_dereg_mr, 459 .destroy_ah = hns_roce_destroy_ah, 460 .destroy_cq = hns_roce_ib_destroy_cq, 461 .disassociate_ucontext = hns_roce_disassociate_ucontext, 462 .get_dma_mr = hns_roce_get_dma_mr, 463 .get_link_layer = hns_roce_get_link_layer, 464 .get_netdev = hns_roce_get_netdev, 465 .get_port_immutable = hns_roce_port_immutable, 466 .mmap = hns_roce_mmap, 467 .modify_device = hns_roce_modify_device, 468 .modify_port = hns_roce_modify_port, 469 .modify_qp = hns_roce_modify_qp, 470 .query_ah = hns_roce_query_ah, 471 .query_device = hns_roce_query_device, 472 .query_pkey = hns_roce_query_pkey, 473 .query_port = hns_roce_query_port, 474 .reg_user_mr = hns_roce_reg_user_mr, 475 }; 476 477 static const struct ib_device_ops hns_roce_dev_mr_ops = { 478 .rereg_user_mr = hns_roce_rereg_user_mr, 479 }; 480 481 static const struct ib_device_ops hns_roce_dev_mw_ops = { 482 .alloc_mw = hns_roce_alloc_mw, 483 .dealloc_mw = hns_roce_dealloc_mw, 484 }; 485 486 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 487 .alloc_mr = hns_roce_alloc_mr, 488 .map_mr_sg = hns_roce_map_mr_sg, 489 }; 490 491 static const struct ib_device_ops hns_roce_dev_srq_ops = { 492 .create_srq = hns_roce_create_srq, 493 .destroy_srq = hns_roce_destroy_srq, 494 }; 495 496 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 497 { 498 int ret; 499 struct hns_roce_ib_iboe *iboe = NULL; 500 struct ib_device *ib_dev = NULL; 501 struct device *dev = hr_dev->dev; 502 503 iboe = &hr_dev->iboe; 504 spin_lock_init(&iboe->lock); 505 506 ib_dev = &hr_dev->ib_dev; 507 508 ib_dev->owner = THIS_MODULE; 509 ib_dev->node_type = RDMA_NODE_IB_CA; 510 ib_dev->dev.parent = dev; 511 512 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 513 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 514 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 515 ib_dev->uverbs_abi_ver = 1; 516 ib_dev->uverbs_cmd_mask = 517 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 518 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 519 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 520 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 521 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 522 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 523 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 524 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 525 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 526 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 527 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 528 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 529 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 530 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 531 532 ib_dev->uverbs_ex_cmd_mask |= 533 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 534 535 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 536 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 537 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 538 } 539 540 /* MW */ 541 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 542 ib_dev->uverbs_cmd_mask |= 543 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 544 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 545 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 546 } 547 548 /* FRMR */ 549 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 550 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 551 552 /* SRQ */ 553 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 554 ib_dev->uverbs_cmd_mask |= 555 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | 556 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | 557 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | 558 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | 559 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV); 560 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 561 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 562 } 563 564 ib_dev->driver_id = RDMA_DRIVER_HNS; 565 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 566 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 567 ret = ib_register_device(ib_dev, "hns_%d", NULL); 568 if (ret) { 569 dev_err(dev, "ib_register_device failed!\n"); 570 return ret; 571 } 572 573 ret = hns_roce_setup_mtu_mac(hr_dev); 574 if (ret) { 575 dev_err(dev, "setup_mtu_mac failed!\n"); 576 goto error_failed_setup_mtu_mac; 577 } 578 579 iboe->nb.notifier_call = hns_roce_netdev_event; 580 ret = register_netdevice_notifier(&iboe->nb); 581 if (ret) { 582 dev_err(dev, "register_netdevice_notifier failed!\n"); 583 goto error_failed_setup_mtu_mac; 584 } 585 586 hr_dev->active = true; 587 return 0; 588 589 error_failed_setup_mtu_mac: 590 ib_unregister_device(ib_dev); 591 592 return ret; 593 } 594 595 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 596 { 597 int ret; 598 struct device *dev = hr_dev->dev; 599 600 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table, 601 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz, 602 hr_dev->caps.num_mtt_segs, 1); 603 if (ret) { 604 dev_err(dev, "Failed to init MTT context memory, aborting.\n"); 605 return ret; 606 } 607 608 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { 609 ret = hns_roce_init_hem_table(hr_dev, 610 &hr_dev->mr_table.mtt_cqe_table, 611 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz, 612 hr_dev->caps.num_cqe_segs, 1); 613 if (ret) { 614 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n"); 615 goto err_unmap_cqe; 616 } 617 } 618 619 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 620 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 621 hr_dev->caps.num_mtpts, 1); 622 if (ret) { 623 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 624 goto err_unmap_mtt; 625 } 626 627 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 628 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz, 629 hr_dev->caps.num_qps, 1); 630 if (ret) { 631 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 632 goto err_unmap_dmpt; 633 } 634 635 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 636 HEM_TYPE_IRRL, 637 hr_dev->caps.irrl_entry_sz * 638 hr_dev->caps.max_qp_init_rdma, 639 hr_dev->caps.num_qps, 1); 640 if (ret) { 641 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 642 goto err_unmap_qp; 643 } 644 645 if (hr_dev->caps.trrl_entry_sz) { 646 ret = hns_roce_init_hem_table(hr_dev, 647 &hr_dev->qp_table.trrl_table, 648 HEM_TYPE_TRRL, 649 hr_dev->caps.trrl_entry_sz * 650 hr_dev->caps.max_qp_dest_rdma, 651 hr_dev->caps.num_qps, 1); 652 if (ret) { 653 dev_err(dev, 654 "Failed to init trrl_table memory, aborting.\n"); 655 goto err_unmap_irrl; 656 } 657 } 658 659 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 660 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 661 hr_dev->caps.num_cqs, 1); 662 if (ret) { 663 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 664 goto err_unmap_trrl; 665 } 666 667 if (hr_dev->caps.srqc_entry_sz) { 668 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 669 HEM_TYPE_SRQC, 670 hr_dev->caps.srqc_entry_sz, 671 hr_dev->caps.num_srqs, 1); 672 if (ret) { 673 dev_err(dev, 674 "Failed to init SRQ context memory, aborting.\n"); 675 goto err_unmap_cq; 676 } 677 } 678 679 if (hr_dev->caps.num_srqwqe_segs) { 680 ret = hns_roce_init_hem_table(hr_dev, 681 &hr_dev->mr_table.mtt_srqwqe_table, 682 HEM_TYPE_SRQWQE, 683 hr_dev->caps.mtt_entry_sz, 684 hr_dev->caps.num_srqwqe_segs, 1); 685 if (ret) { 686 dev_err(dev, 687 "Failed to init MTT srqwqe memory, aborting.\n"); 688 goto err_unmap_srq; 689 } 690 } 691 692 if (hr_dev->caps.num_idx_segs) { 693 ret = hns_roce_init_hem_table(hr_dev, 694 &hr_dev->mr_table.mtt_idx_table, 695 HEM_TYPE_IDX, 696 hr_dev->caps.idx_entry_sz, 697 hr_dev->caps.num_idx_segs, 1); 698 if (ret) { 699 dev_err(dev, 700 "Failed to init MTT idx memory, aborting.\n"); 701 goto err_unmap_srqwqe; 702 } 703 } 704 705 return 0; 706 707 err_unmap_srqwqe: 708 if (hr_dev->caps.num_srqwqe_segs) 709 hns_roce_cleanup_hem_table(hr_dev, 710 &hr_dev->mr_table.mtt_srqwqe_table); 711 712 err_unmap_srq: 713 if (hr_dev->caps.srqc_entry_sz) 714 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 715 716 err_unmap_cq: 717 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 718 719 err_unmap_trrl: 720 if (hr_dev->caps.trrl_entry_sz) 721 hns_roce_cleanup_hem_table(hr_dev, 722 &hr_dev->qp_table.trrl_table); 723 724 err_unmap_irrl: 725 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 726 727 err_unmap_qp: 728 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 729 730 err_unmap_dmpt: 731 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 732 733 err_unmap_mtt: 734 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) 735 hns_roce_cleanup_hem_table(hr_dev, 736 &hr_dev->mr_table.mtt_cqe_table); 737 738 err_unmap_cqe: 739 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table); 740 741 return ret; 742 } 743 744 /** 745 * hns_roce_setup_hca - setup host channel adapter 746 * @hr_dev: pointer to hns roce device 747 * Return : int 748 */ 749 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 750 { 751 int ret; 752 struct device *dev = hr_dev->dev; 753 754 spin_lock_init(&hr_dev->sm_lock); 755 spin_lock_init(&hr_dev->bt_cmd_lock); 756 757 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 758 INIT_LIST_HEAD(&hr_dev->pgdir_list); 759 mutex_init(&hr_dev->pgdir_mutex); 760 } 761 762 ret = hns_roce_init_uar_table(hr_dev); 763 if (ret) { 764 dev_err(dev, "Failed to initialize uar table. aborting\n"); 765 return ret; 766 } 767 768 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 769 if (ret) { 770 dev_err(dev, "Failed to allocate priv_uar.\n"); 771 goto err_uar_table_free; 772 } 773 774 ret = hns_roce_init_pd_table(hr_dev); 775 if (ret) { 776 dev_err(dev, "Failed to init protected domain table.\n"); 777 goto err_uar_alloc_free; 778 } 779 780 ret = hns_roce_init_mr_table(hr_dev); 781 if (ret) { 782 dev_err(dev, "Failed to init memory region table.\n"); 783 goto err_pd_table_free; 784 } 785 786 ret = hns_roce_init_cq_table(hr_dev); 787 if (ret) { 788 dev_err(dev, "Failed to init completion queue table.\n"); 789 goto err_mr_table_free; 790 } 791 792 ret = hns_roce_init_qp_table(hr_dev); 793 if (ret) { 794 dev_err(dev, "Failed to init queue pair table.\n"); 795 goto err_cq_table_free; 796 } 797 798 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 799 ret = hns_roce_init_srq_table(hr_dev); 800 if (ret) { 801 dev_err(dev, 802 "Failed to init share receive queue table.\n"); 803 goto err_qp_table_free; 804 } 805 } 806 807 return 0; 808 809 err_qp_table_free: 810 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 811 hns_roce_cleanup_qp_table(hr_dev); 812 813 err_cq_table_free: 814 hns_roce_cleanup_cq_table(hr_dev); 815 816 err_mr_table_free: 817 hns_roce_cleanup_mr_table(hr_dev); 818 819 err_pd_table_free: 820 hns_roce_cleanup_pd_table(hr_dev); 821 822 err_uar_alloc_free: 823 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 824 825 err_uar_table_free: 826 hns_roce_cleanup_uar_table(hr_dev); 827 return ret; 828 } 829 830 int hns_roce_init(struct hns_roce_dev *hr_dev) 831 { 832 int ret; 833 struct device *dev = hr_dev->dev; 834 835 if (hr_dev->hw->reset) { 836 ret = hr_dev->hw->reset(hr_dev, true); 837 if (ret) { 838 dev_err(dev, "Reset RoCE engine failed!\n"); 839 return ret; 840 } 841 } 842 hr_dev->is_reset = false; 843 844 if (hr_dev->hw->cmq_init) { 845 ret = hr_dev->hw->cmq_init(hr_dev); 846 if (ret) { 847 dev_err(dev, "Init RoCE Command Queue failed!\n"); 848 goto error_failed_cmq_init; 849 } 850 } 851 852 ret = hr_dev->hw->hw_profile(hr_dev); 853 if (ret) { 854 dev_err(dev, "Get RoCE engine profile failed!\n"); 855 goto error_failed_cmd_init; 856 } 857 858 ret = hns_roce_cmd_init(hr_dev); 859 if (ret) { 860 dev_err(dev, "cmd init failed!\n"); 861 goto error_failed_cmd_init; 862 } 863 864 ret = hr_dev->hw->init_eq(hr_dev); 865 if (ret) { 866 dev_err(dev, "eq init failed!\n"); 867 goto error_failed_eq_table; 868 } 869 870 if (hr_dev->cmd_mod) { 871 ret = hns_roce_cmd_use_events(hr_dev); 872 if (ret) { 873 dev_err(dev, "Switch to event-driven cmd failed!\n"); 874 goto error_failed_use_event; 875 } 876 } 877 878 ret = hns_roce_init_hem(hr_dev); 879 if (ret) { 880 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 881 goto error_failed_init_hem; 882 } 883 884 ret = hns_roce_setup_hca(hr_dev); 885 if (ret) { 886 dev_err(dev, "setup hca failed!\n"); 887 goto error_failed_setup_hca; 888 } 889 890 if (hr_dev->hw->hw_init) { 891 ret = hr_dev->hw->hw_init(hr_dev); 892 if (ret) { 893 dev_err(dev, "hw_init failed!\n"); 894 goto error_failed_engine_init; 895 } 896 } 897 898 ret = hns_roce_register_device(hr_dev); 899 if (ret) 900 goto error_failed_register_device; 901 902 return 0; 903 904 error_failed_register_device: 905 if (hr_dev->hw->hw_exit) 906 hr_dev->hw->hw_exit(hr_dev); 907 908 error_failed_engine_init: 909 hns_roce_cleanup_bitmap(hr_dev); 910 911 error_failed_setup_hca: 912 hns_roce_cleanup_hem(hr_dev); 913 914 error_failed_init_hem: 915 if (hr_dev->cmd_mod) 916 hns_roce_cmd_use_polling(hr_dev); 917 918 error_failed_use_event: 919 hr_dev->hw->cleanup_eq(hr_dev); 920 921 error_failed_eq_table: 922 hns_roce_cmd_cleanup(hr_dev); 923 924 error_failed_cmd_init: 925 if (hr_dev->hw->cmq_exit) 926 hr_dev->hw->cmq_exit(hr_dev); 927 928 error_failed_cmq_init: 929 if (hr_dev->hw->reset) { 930 if (hr_dev->hw->reset(hr_dev, false)) 931 dev_err(dev, "Dereset RoCE engine failed!\n"); 932 } 933 934 return ret; 935 } 936 EXPORT_SYMBOL_GPL(hns_roce_init); 937 938 void hns_roce_exit(struct hns_roce_dev *hr_dev) 939 { 940 hns_roce_unregister_device(hr_dev); 941 942 if (hr_dev->hw->hw_exit) 943 hr_dev->hw->hw_exit(hr_dev); 944 hns_roce_cleanup_bitmap(hr_dev); 945 hns_roce_cleanup_hem(hr_dev); 946 947 if (hr_dev->cmd_mod) 948 hns_roce_cmd_use_polling(hr_dev); 949 950 hr_dev->hw->cleanup_eq(hr_dev); 951 hns_roce_cmd_cleanup(hr_dev); 952 if (hr_dev->hw->cmq_exit) 953 hr_dev->hw->cmq_exit(hr_dev); 954 if (hr_dev->hw->reset) 955 hr_dev->hw->reset(hr_dev, false); 956 } 957 EXPORT_SYMBOL_GPL(hns_roce_exit); 958 959 MODULE_LICENSE("Dual BSD/GPL"); 960 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 961 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 962 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 963 MODULE_DESCRIPTION("HNS RoCE Driver"); 964