1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/of_platform.h> 35 #include <linux/module.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include <rdma/hns-abi.h> 43 #include "hns_roce_hem.h" 44 45 /** 46 * hns_get_gid_index - Get gid index. 47 * @hr_dev: pointer to structure hns_roce_dev. 48 * @port: port, value range: 0 ~ MAX 49 * @gid_index: gid_index, value range: 0 ~ MAX 50 * Description: 51 * N ports shared gids, allocation method as follow: 52 * GID[0][0], GID[1][0],.....GID[N - 1][0], 53 * GID[0][0], GID[1][0],.....GID[N - 1][0], 54 * And so on 55 */ 56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index) 57 { 58 return gid_index * hr_dev->caps.num_ports + port; 59 } 60 61 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 62 { 63 u8 phy_port; 64 u32 i = 0; 65 66 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 67 return 0; 68 69 for (i = 0; i < ETH_ALEN; i++) 70 hr_dev->dev_addr[port][i] = addr[i]; 71 72 phy_port = hr_dev->iboe.phy_port[port]; 73 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 74 } 75 76 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 77 { 78 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 79 u8 port = attr->port_num - 1; 80 int ret; 81 82 if (port >= hr_dev->caps.num_ports) 83 return -EINVAL; 84 85 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr); 86 87 return ret; 88 } 89 90 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 91 { 92 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 93 struct ib_gid_attr zattr = {}; 94 u8 port = attr->port_num - 1; 95 int ret; 96 97 if (port >= hr_dev->caps.num_ports) 98 return -EINVAL; 99 100 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr); 101 102 return ret; 103 } 104 105 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 106 unsigned long event) 107 { 108 struct device *dev = hr_dev->dev; 109 struct net_device *netdev; 110 int ret = 0; 111 112 netdev = hr_dev->iboe.netdevs[port]; 113 if (!netdev) { 114 dev_err(dev, "Can't find netdev on port(%u)!\n", port); 115 return -ENODEV; 116 } 117 118 switch (event) { 119 case NETDEV_UP: 120 case NETDEV_CHANGE: 121 case NETDEV_REGISTER: 122 case NETDEV_CHANGEADDR: 123 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 124 break; 125 case NETDEV_DOWN: 126 /* 127 * In v1 engine, only support all ports closed together. 128 */ 129 break; 130 default: 131 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 132 break; 133 } 134 135 return ret; 136 } 137 138 static int hns_roce_netdev_event(struct notifier_block *self, 139 unsigned long event, void *ptr) 140 { 141 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 142 struct hns_roce_ib_iboe *iboe = NULL; 143 struct hns_roce_dev *hr_dev = NULL; 144 int ret; 145 u8 port; 146 147 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 148 iboe = &hr_dev->iboe; 149 150 for (port = 0; port < hr_dev->caps.num_ports; port++) { 151 if (dev == iboe->netdevs[port]) { 152 ret = handle_en_event(hr_dev, port, event); 153 if (ret) 154 return NOTIFY_DONE; 155 break; 156 } 157 } 158 159 return NOTIFY_DONE; 160 } 161 162 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 163 { 164 int ret; 165 u8 i; 166 167 for (i = 0; i < hr_dev->caps.num_ports; i++) { 168 if (hr_dev->hw->set_mtu) 169 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i], 170 hr_dev->caps.max_mtu); 171 ret = hns_roce_set_mac(hr_dev, i, 172 hr_dev->iboe.netdevs[i]->dev_addr); 173 if (ret) 174 return ret; 175 } 176 177 return 0; 178 } 179 180 static int hns_roce_query_device(struct ib_device *ib_dev, 181 struct ib_device_attr *props, 182 struct ib_udata *uhw) 183 { 184 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 185 186 memset(props, 0, sizeof(*props)); 187 188 props->fw_ver = hr_dev->caps.fw_ver; 189 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 190 props->max_mr_size = (u64)(~(0ULL)); 191 props->page_size_cap = hr_dev->caps.page_size_cap; 192 props->vendor_id = hr_dev->vendor_id; 193 props->vendor_part_id = hr_dev->vendor_part_id; 194 props->hw_ver = hr_dev->hw_rev; 195 props->max_qp = hr_dev->caps.num_qps; 196 props->max_qp_wr = hr_dev->caps.max_wqes; 197 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 198 IB_DEVICE_RC_RNR_NAK_GEN; 199 props->max_send_sge = hr_dev->caps.max_sq_sg; 200 props->max_recv_sge = hr_dev->caps.max_rq_sg; 201 props->max_sge_rd = 1; 202 props->max_cq = hr_dev->caps.num_cqs; 203 props->max_cqe = hr_dev->caps.max_cqes; 204 props->max_mr = hr_dev->caps.num_mtpts; 205 props->max_pd = hr_dev->caps.num_pds; 206 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 207 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 208 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 209 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 210 props->max_pkeys = 1; 211 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 212 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 213 props->max_srq = hr_dev->caps.num_srqs; 214 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 215 props->max_srq_sge = hr_dev->caps.max_srq_sges; 216 } 217 218 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) { 219 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 220 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 221 } 222 223 return 0; 224 } 225 226 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num, 227 struct ib_port_attr *props) 228 { 229 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 230 struct device *dev = hr_dev->dev; 231 struct net_device *net_dev; 232 unsigned long flags; 233 enum ib_mtu mtu; 234 u8 port; 235 236 port = port_num - 1; 237 238 /* props being zeroed by the caller, avoid zeroing it here */ 239 240 props->max_mtu = hr_dev->caps.max_mtu; 241 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 242 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 243 IB_PORT_VENDOR_CLASS_SUP | 244 IB_PORT_BOOT_MGMT_SUP; 245 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 246 props->pkey_tbl_len = 1; 247 props->active_width = IB_WIDTH_4X; 248 props->active_speed = 1; 249 250 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 251 252 net_dev = hr_dev->iboe.netdevs[port]; 253 if (!net_dev) { 254 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 255 dev_err(dev, "Find netdev %u failed!\n", port); 256 return -EINVAL; 257 } 258 259 mtu = iboe_get_mtu(net_dev->mtu); 260 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 261 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 262 IB_PORT_ACTIVE : 263 IB_PORT_DOWN; 264 props->phys_state = props->state == IB_PORT_ACTIVE ? 265 IB_PORT_PHYS_STATE_LINK_UP : 266 IB_PORT_PHYS_STATE_DISABLED; 267 268 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 269 270 return 0; 271 } 272 273 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 274 u8 port_num) 275 { 276 return IB_LINK_LAYER_ETHERNET; 277 } 278 279 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index, 280 u16 *pkey) 281 { 282 *pkey = PKEY_ID; 283 284 return 0; 285 } 286 287 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 288 struct ib_device_modify *props) 289 { 290 unsigned long flags; 291 292 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 293 return -EOPNOTSUPP; 294 295 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 296 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 297 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 298 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 299 } 300 301 return 0; 302 } 303 304 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 305 struct ib_udata *udata) 306 { 307 int ret; 308 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 309 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 310 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 311 312 if (!hr_dev->active) 313 return -EAGAIN; 314 315 resp.qp_tab_size = hr_dev->caps.num_qps; 316 317 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 318 if (ret) 319 goto error_fail_uar_alloc; 320 321 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 322 INIT_LIST_HEAD(&context->page_list); 323 mutex_init(&context->page_mutex); 324 } 325 326 resp.cqe_size = hr_dev->caps.cqe_sz; 327 328 ret = ib_copy_to_udata(udata, &resp, sizeof(resp)); 329 if (ret) 330 goto error_fail_copy_to_udata; 331 332 return 0; 333 334 error_fail_copy_to_udata: 335 hns_roce_uar_free(hr_dev, &context->uar); 336 337 error_fail_uar_alloc: 338 return ret; 339 } 340 341 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 342 { 343 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 344 345 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar); 346 } 347 348 static int hns_roce_mmap(struct ib_ucontext *context, 349 struct vm_area_struct *vma) 350 { 351 struct hns_roce_dev *hr_dev = to_hr_dev(context->device); 352 353 switch (vma->vm_pgoff) { 354 case 0: 355 return rdma_user_mmap_io(context, vma, 356 to_hr_ucontext(context)->uar.pfn, 357 PAGE_SIZE, 358 pgprot_noncached(vma->vm_page_prot), 359 NULL); 360 361 /* vm_pgoff: 1 -- TPTR */ 362 case 1: 363 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size) 364 return -EINVAL; 365 /* 366 * FIXME: using io_remap_pfn_range on the dma address returned 367 * by dma_alloc_coherent is totally wrong. 368 */ 369 return rdma_user_mmap_io(context, vma, 370 hr_dev->tptr_dma_addr >> PAGE_SHIFT, 371 hr_dev->tptr_size, 372 vma->vm_page_prot, 373 NULL); 374 375 default: 376 return -EINVAL; 377 } 378 } 379 380 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num, 381 struct ib_port_immutable *immutable) 382 { 383 struct ib_port_attr attr; 384 int ret; 385 386 ret = ib_query_port(ib_dev, port_num, &attr); 387 if (ret) 388 return ret; 389 390 immutable->pkey_tbl_len = attr.pkey_tbl_len; 391 immutable->gid_tbl_len = attr.gid_tbl_len; 392 393 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 394 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 395 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 396 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 397 398 return 0; 399 } 400 401 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 402 { 403 } 404 405 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 406 { 407 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 408 409 hr_dev->active = false; 410 unregister_netdevice_notifier(&iboe->nb); 411 ib_unregister_device(&hr_dev->ib_dev); 412 } 413 414 static const struct ib_device_ops hns_roce_dev_ops = { 415 .owner = THIS_MODULE, 416 .driver_id = RDMA_DRIVER_HNS, 417 .uverbs_abi_ver = 1, 418 .uverbs_no_driver_id_binding = 1, 419 420 .add_gid = hns_roce_add_gid, 421 .alloc_pd = hns_roce_alloc_pd, 422 .alloc_ucontext = hns_roce_alloc_ucontext, 423 .create_ah = hns_roce_create_ah, 424 .create_cq = hns_roce_create_cq, 425 .create_qp = hns_roce_create_qp, 426 .dealloc_pd = hns_roce_dealloc_pd, 427 .dealloc_ucontext = hns_roce_dealloc_ucontext, 428 .del_gid = hns_roce_del_gid, 429 .dereg_mr = hns_roce_dereg_mr, 430 .destroy_ah = hns_roce_destroy_ah, 431 .destroy_cq = hns_roce_destroy_cq, 432 .disassociate_ucontext = hns_roce_disassociate_ucontext, 433 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 434 .get_dma_mr = hns_roce_get_dma_mr, 435 .get_link_layer = hns_roce_get_link_layer, 436 .get_port_immutable = hns_roce_port_immutable, 437 .mmap = hns_roce_mmap, 438 .modify_device = hns_roce_modify_device, 439 .modify_qp = hns_roce_modify_qp, 440 .query_ah = hns_roce_query_ah, 441 .query_device = hns_roce_query_device, 442 .query_pkey = hns_roce_query_pkey, 443 .query_port = hns_roce_query_port, 444 .reg_user_mr = hns_roce_reg_user_mr, 445 446 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 447 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 448 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 449 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 450 }; 451 452 static const struct ib_device_ops hns_roce_dev_mr_ops = { 453 .rereg_user_mr = hns_roce_rereg_user_mr, 454 }; 455 456 static const struct ib_device_ops hns_roce_dev_mw_ops = { 457 .alloc_mw = hns_roce_alloc_mw, 458 .dealloc_mw = hns_roce_dealloc_mw, 459 460 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 461 }; 462 463 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 464 .alloc_mr = hns_roce_alloc_mr, 465 .map_mr_sg = hns_roce_map_mr_sg, 466 }; 467 468 static const struct ib_device_ops hns_roce_dev_srq_ops = { 469 .create_srq = hns_roce_create_srq, 470 .destroy_srq = hns_roce_destroy_srq, 471 472 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 473 }; 474 475 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 476 { 477 int ret; 478 struct hns_roce_ib_iboe *iboe = NULL; 479 struct ib_device *ib_dev = NULL; 480 struct device *dev = hr_dev->dev; 481 unsigned int i; 482 483 iboe = &hr_dev->iboe; 484 spin_lock_init(&iboe->lock); 485 486 ib_dev = &hr_dev->ib_dev; 487 488 ib_dev->node_type = RDMA_NODE_IB_CA; 489 ib_dev->dev.parent = dev; 490 491 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 492 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 493 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 494 ib_dev->uverbs_cmd_mask = 495 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | 496 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | 497 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | 498 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | 499 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | 500 (1ULL << IB_USER_VERBS_CMD_REG_MR) | 501 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | 502 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 503 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | 504 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | 505 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | 506 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | 507 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | 508 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP); 509 510 ib_dev->uverbs_ex_cmd_mask |= (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ); 511 512 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) { 513 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR); 514 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 515 } 516 517 /* MW */ 518 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) { 519 ib_dev->uverbs_cmd_mask |= 520 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | 521 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); 522 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 523 } 524 525 /* FRMR */ 526 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 527 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 528 529 /* SRQ */ 530 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 531 ib_dev->uverbs_cmd_mask |= 532 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | 533 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | 534 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | 535 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | 536 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV); 537 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 538 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 539 } 540 541 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 542 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 543 for (i = 0; i < hr_dev->caps.num_ports; i++) { 544 if (!hr_dev->iboe.netdevs[i]) 545 continue; 546 547 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 548 i + 1); 549 if (ret) 550 return ret; 551 } 552 dma_set_max_seg_size(dev, UINT_MAX); 553 ret = ib_register_device(ib_dev, "hns_%d", dev); 554 if (ret) { 555 dev_err(dev, "ib_register_device failed!\n"); 556 return ret; 557 } 558 559 ret = hns_roce_setup_mtu_mac(hr_dev); 560 if (ret) { 561 dev_err(dev, "setup_mtu_mac failed!\n"); 562 goto error_failed_setup_mtu_mac; 563 } 564 565 iboe->nb.notifier_call = hns_roce_netdev_event; 566 ret = register_netdevice_notifier(&iboe->nb); 567 if (ret) { 568 dev_err(dev, "register_netdevice_notifier failed!\n"); 569 goto error_failed_setup_mtu_mac; 570 } 571 572 hr_dev->active = true; 573 return 0; 574 575 error_failed_setup_mtu_mac: 576 ib_unregister_device(ib_dev); 577 578 return ret; 579 } 580 581 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 582 { 583 int ret; 584 struct device *dev = hr_dev->dev; 585 586 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 587 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 588 hr_dev->caps.num_mtpts, 1); 589 if (ret) { 590 dev_err(dev, "Failed to init MTPT context memory, aborting.\n"); 591 return ret; 592 } 593 594 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 595 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 596 hr_dev->caps.num_qps, 1); 597 if (ret) { 598 dev_err(dev, "Failed to init QP context memory, aborting.\n"); 599 goto err_unmap_dmpt; 600 } 601 602 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 603 HEM_TYPE_IRRL, 604 hr_dev->caps.irrl_entry_sz * 605 hr_dev->caps.max_qp_init_rdma, 606 hr_dev->caps.num_qps, 1); 607 if (ret) { 608 dev_err(dev, "Failed to init irrl_table memory, aborting.\n"); 609 goto err_unmap_qp; 610 } 611 612 if (hr_dev->caps.trrl_entry_sz) { 613 ret = hns_roce_init_hem_table(hr_dev, 614 &hr_dev->qp_table.trrl_table, 615 HEM_TYPE_TRRL, 616 hr_dev->caps.trrl_entry_sz * 617 hr_dev->caps.max_qp_dest_rdma, 618 hr_dev->caps.num_qps, 1); 619 if (ret) { 620 dev_err(dev, 621 "Failed to init trrl_table memory, aborting.\n"); 622 goto err_unmap_irrl; 623 } 624 } 625 626 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 627 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 628 hr_dev->caps.num_cqs, 1); 629 if (ret) { 630 dev_err(dev, "Failed to init CQ context memory, aborting.\n"); 631 goto err_unmap_trrl; 632 } 633 634 if (hr_dev->caps.srqc_entry_sz) { 635 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 636 HEM_TYPE_SRQC, 637 hr_dev->caps.srqc_entry_sz, 638 hr_dev->caps.num_srqs, 1); 639 if (ret) { 640 dev_err(dev, 641 "Failed to init SRQ context memory, aborting.\n"); 642 goto err_unmap_cq; 643 } 644 } 645 646 if (hr_dev->caps.sccc_sz) { 647 ret = hns_roce_init_hem_table(hr_dev, 648 &hr_dev->qp_table.sccc_table, 649 HEM_TYPE_SCCC, 650 hr_dev->caps.sccc_sz, 651 hr_dev->caps.num_qps, 1); 652 if (ret) { 653 dev_err(dev, 654 "Failed to init SCC context memory, aborting.\n"); 655 goto err_unmap_srq; 656 } 657 } 658 659 if (hr_dev->caps.qpc_timer_entry_sz) { 660 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 661 HEM_TYPE_QPC_TIMER, 662 hr_dev->caps.qpc_timer_entry_sz, 663 hr_dev->caps.num_qpc_timer, 1); 664 if (ret) { 665 dev_err(dev, 666 "Failed to init QPC timer memory, aborting.\n"); 667 goto err_unmap_ctx; 668 } 669 } 670 671 if (hr_dev->caps.cqc_timer_entry_sz) { 672 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 673 HEM_TYPE_CQC_TIMER, 674 hr_dev->caps.cqc_timer_entry_sz, 675 hr_dev->caps.num_cqc_timer, 1); 676 if (ret) { 677 dev_err(dev, 678 "Failed to init CQC timer memory, aborting.\n"); 679 goto err_unmap_qpc_timer; 680 } 681 } 682 683 return 0; 684 685 err_unmap_qpc_timer: 686 if (hr_dev->caps.qpc_timer_entry_sz) 687 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 688 689 err_unmap_ctx: 690 if (hr_dev->caps.sccc_sz) 691 hns_roce_cleanup_hem_table(hr_dev, 692 &hr_dev->qp_table.sccc_table); 693 err_unmap_srq: 694 if (hr_dev->caps.srqc_entry_sz) 695 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 696 697 err_unmap_cq: 698 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 699 700 err_unmap_trrl: 701 if (hr_dev->caps.trrl_entry_sz) 702 hns_roce_cleanup_hem_table(hr_dev, 703 &hr_dev->qp_table.trrl_table); 704 705 err_unmap_irrl: 706 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 707 708 err_unmap_qp: 709 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 710 711 err_unmap_dmpt: 712 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 713 714 return ret; 715 } 716 717 /** 718 * hns_roce_setup_hca - setup host channel adapter 719 * @hr_dev: pointer to hns roce device 720 * Return : int 721 */ 722 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 723 { 724 int ret; 725 struct device *dev = hr_dev->dev; 726 727 spin_lock_init(&hr_dev->sm_lock); 728 spin_lock_init(&hr_dev->bt_cmd_lock); 729 730 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) { 731 INIT_LIST_HEAD(&hr_dev->pgdir_list); 732 mutex_init(&hr_dev->pgdir_mutex); 733 } 734 735 ret = hns_roce_init_uar_table(hr_dev); 736 if (ret) { 737 dev_err(dev, "Failed to initialize uar table. aborting\n"); 738 return ret; 739 } 740 741 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 742 if (ret) { 743 dev_err(dev, "Failed to allocate priv_uar.\n"); 744 goto err_uar_table_free; 745 } 746 747 ret = hns_roce_init_pd_table(hr_dev); 748 if (ret) { 749 dev_err(dev, "Failed to init protected domain table.\n"); 750 goto err_uar_alloc_free; 751 } 752 753 ret = hns_roce_init_mr_table(hr_dev); 754 if (ret) { 755 dev_err(dev, "Failed to init memory region table.\n"); 756 goto err_pd_table_free; 757 } 758 759 ret = hns_roce_init_cq_table(hr_dev); 760 if (ret) { 761 dev_err(dev, "Failed to init completion queue table.\n"); 762 goto err_mr_table_free; 763 } 764 765 ret = hns_roce_init_qp_table(hr_dev); 766 if (ret) { 767 dev_err(dev, "Failed to init queue pair table.\n"); 768 goto err_cq_table_free; 769 } 770 771 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 772 ret = hns_roce_init_srq_table(hr_dev); 773 if (ret) { 774 dev_err(dev, 775 "Failed to init share receive queue table.\n"); 776 goto err_qp_table_free; 777 } 778 } 779 780 return 0; 781 782 err_qp_table_free: 783 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 784 hns_roce_cleanup_qp_table(hr_dev); 785 786 err_cq_table_free: 787 hns_roce_cleanup_cq_table(hr_dev); 788 789 err_mr_table_free: 790 hns_roce_cleanup_mr_table(hr_dev); 791 792 err_pd_table_free: 793 hns_roce_cleanup_pd_table(hr_dev); 794 795 err_uar_alloc_free: 796 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); 797 798 err_uar_table_free: 799 hns_roce_cleanup_uar_table(hr_dev); 800 return ret; 801 } 802 803 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 804 { 805 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 806 unsigned long flags; 807 808 spin_lock_irqsave(&hr_cq->lock, flags); 809 if (cq->comp_handler) { 810 if (!hr_cq->is_armed) { 811 hr_cq->is_armed = 1; 812 list_add_tail(&hr_cq->node, cq_list); 813 } 814 } 815 spin_unlock_irqrestore(&hr_cq->lock, flags); 816 } 817 818 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 819 { 820 struct hns_roce_qp *hr_qp; 821 struct hns_roce_cq *hr_cq; 822 struct list_head cq_list; 823 unsigned long flags_qp; 824 unsigned long flags; 825 826 INIT_LIST_HEAD(&cq_list); 827 828 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 829 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 830 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 831 if (hr_qp->sq.tail != hr_qp->sq.head) 832 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 833 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 834 835 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 836 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 837 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 838 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 839 } 840 841 list_for_each_entry(hr_cq, &cq_list, node) 842 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 843 844 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 845 } 846 847 int hns_roce_init(struct hns_roce_dev *hr_dev) 848 { 849 int ret; 850 struct device *dev = hr_dev->dev; 851 852 if (hr_dev->hw->reset) { 853 ret = hr_dev->hw->reset(hr_dev, true); 854 if (ret) { 855 dev_err(dev, "Reset RoCE engine failed!\n"); 856 return ret; 857 } 858 } 859 hr_dev->is_reset = false; 860 861 if (hr_dev->hw->cmq_init) { 862 ret = hr_dev->hw->cmq_init(hr_dev); 863 if (ret) { 864 dev_err(dev, "Init RoCE Command Queue failed!\n"); 865 goto error_failed_cmq_init; 866 } 867 } 868 869 ret = hr_dev->hw->hw_profile(hr_dev); 870 if (ret) { 871 dev_err(dev, "Get RoCE engine profile failed!\n"); 872 goto error_failed_cmd_init; 873 } 874 875 ret = hns_roce_cmd_init(hr_dev); 876 if (ret) { 877 dev_err(dev, "cmd init failed!\n"); 878 goto error_failed_cmd_init; 879 } 880 881 /* EQ depends on poll mode, event mode depends on EQ */ 882 ret = hr_dev->hw->init_eq(hr_dev); 883 if (ret) { 884 dev_err(dev, "eq init failed!\n"); 885 goto error_failed_eq_table; 886 } 887 888 if (hr_dev->cmd_mod) { 889 ret = hns_roce_cmd_use_events(hr_dev); 890 if (ret) { 891 dev_warn(dev, 892 "Cmd event mode failed, set back to poll!\n"); 893 hns_roce_cmd_use_polling(hr_dev); 894 } 895 } 896 897 ret = hns_roce_init_hem(hr_dev); 898 if (ret) { 899 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 900 goto error_failed_init_hem; 901 } 902 903 ret = hns_roce_setup_hca(hr_dev); 904 if (ret) { 905 dev_err(dev, "setup hca failed!\n"); 906 goto error_failed_setup_hca; 907 } 908 909 if (hr_dev->hw->hw_init) { 910 ret = hr_dev->hw->hw_init(hr_dev); 911 if (ret) { 912 dev_err(dev, "hw_init failed!\n"); 913 goto error_failed_engine_init; 914 } 915 } 916 917 INIT_LIST_HEAD(&hr_dev->qp_list); 918 spin_lock_init(&hr_dev->qp_list_lock); 919 920 ret = hns_roce_register_device(hr_dev); 921 if (ret) 922 goto error_failed_register_device; 923 924 return 0; 925 926 error_failed_register_device: 927 if (hr_dev->hw->hw_exit) 928 hr_dev->hw->hw_exit(hr_dev); 929 930 error_failed_engine_init: 931 hns_roce_cleanup_bitmap(hr_dev); 932 933 error_failed_setup_hca: 934 hns_roce_cleanup_hem(hr_dev); 935 936 error_failed_init_hem: 937 if (hr_dev->cmd_mod) 938 hns_roce_cmd_use_polling(hr_dev); 939 hr_dev->hw->cleanup_eq(hr_dev); 940 941 error_failed_eq_table: 942 hns_roce_cmd_cleanup(hr_dev); 943 944 error_failed_cmd_init: 945 if (hr_dev->hw->cmq_exit) 946 hr_dev->hw->cmq_exit(hr_dev); 947 948 error_failed_cmq_init: 949 if (hr_dev->hw->reset) { 950 if (hr_dev->hw->reset(hr_dev, false)) 951 dev_err(dev, "Dereset RoCE engine failed!\n"); 952 } 953 954 return ret; 955 } 956 957 void hns_roce_exit(struct hns_roce_dev *hr_dev) 958 { 959 hns_roce_unregister_device(hr_dev); 960 961 if (hr_dev->hw->hw_exit) 962 hr_dev->hw->hw_exit(hr_dev); 963 hns_roce_cleanup_bitmap(hr_dev); 964 hns_roce_cleanup_hem(hr_dev); 965 966 if (hr_dev->cmd_mod) 967 hns_roce_cmd_use_polling(hr_dev); 968 969 hr_dev->hw->cleanup_eq(hr_dev); 970 hns_roce_cmd_cleanup(hr_dev); 971 if (hr_dev->hw->cmq_exit) 972 hr_dev->hw->cmq_exit(hr_dev); 973 if (hr_dev->hw->reset) 974 hr_dev->hw->reset(hr_dev, false); 975 } 976 977 MODULE_LICENSE("Dual BSD/GPL"); 978 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 979 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 980 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 981 MODULE_DESCRIPTION("HNS RoCE Driver"); 982