1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_HW_V2_H 34 #define _HNS_ROCE_HW_V2_H 35 36 #include <linux/bitops.h> 37 38 #define HNS_ROCE_VF_QPC_BT_NUM 256 39 #define HNS_ROCE_VF_SRQC_BT_NUM 64 40 #define HNS_ROCE_VF_CQC_BT_NUM 64 41 #define HNS_ROCE_VF_MPT_BT_NUM 64 42 #define HNS_ROCE_VF_EQC_NUM 64 43 #define HNS_ROCE_VF_SMAC_NUM 32 44 #define HNS_ROCE_VF_SGID_NUM 32 45 #define HNS_ROCE_VF_SL_NUM 8 46 47 #define HNS_ROCE_V2_MAX_QP_NUM 0x2000 48 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 49 #define HNS_ROCE_V2_MAX_CQ_NUM 0x8000 50 #define HNS_ROCE_V2_MAX_CQE_NUM 0x10000 51 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100 52 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff 53 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 54 #define HNS_ROCE_V2_UAR_NUM 256 55 #define HNS_ROCE_V2_PHY_UAR_NUM 1 56 #define HNS_ROCE_V2_MAX_IRQ_NUM 65 57 #define HNS_ROCE_V2_COMP_VEC_NUM 63 58 #define HNS_ROCE_V2_AEQE_VEC_NUM 1 59 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 60 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000 61 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 62 #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 63 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 64 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 65 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 66 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 67 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 68 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 69 #define HNS_ROCE_V2_QPC_ENTRY_SZ 256 70 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 71 #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48 72 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64 73 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 74 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 75 #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32 76 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 77 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 78 #define HNS_ROCE_INVALID_LKEY 0x100 79 #define HNS_ROCE_CMQ_TX_TIMEOUT 200 80 81 #define HNS_ROCE_CONTEXT_HOP_NUM 1 82 #define HNS_ROCE_MTT_HOP_NUM 1 83 #define HNS_ROCE_CQE_HOP_NUM 1 84 #define HNS_ROCE_PBL_HOP_NUM 2 85 #define HNS_ROCE_EQE_HOP_NUM 2 86 87 #define HNS_ROCE_V2_GID_INDEX_NUM 256 88 89 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) 90 91 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0 92 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 93 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 94 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 95 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 96 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 97 98 #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) 99 #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) 100 #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) 101 #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) 102 #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) 103 #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) 104 105 #define HNS_ROCE_CMQ_DESC_NUM_S 3 106 #define HNS_ROCE_CMQ_EN_B 16 107 #define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B) 108 109 #define check_whether_last_step(hop_num, step_idx) \ 110 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ 111 (step_idx == 1 && hop_num == 1) || \ 112 (step_idx == 2 && hop_num == 2)) 113 114 enum { 115 NO_ARMED = 0x0, 116 REG_NXT_CEQE = 0x2, 117 REG_NXT_SE_CEQE = 0x3 118 }; 119 120 #define V2_CQ_DB_REQ_NOT_SOL 0 121 #define V2_CQ_DB_REQ_NOT 1 122 123 #define V2_CQ_STATE_VALID 1 124 #define V2_QKEY_VAL 0x80010000 125 126 #define GID_LEN_V2 16 127 128 #define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff 129 130 enum { 131 HNS_ROCE_V2_WQE_OP_SEND = 0x0, 132 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, 133 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, 134 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, 135 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, 136 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, 137 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, 138 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, 139 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, 140 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, 141 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, 142 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, 143 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc, 144 HNS_ROCE_V2_WQE_OP_MASK = 0x1f, 145 }; 146 147 enum { 148 HNS_ROCE_SQ_OPCODE_SEND = 0x0, 149 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1, 150 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2, 151 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3, 152 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4, 153 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5, 154 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6, 155 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7, 156 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8, 157 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9, 158 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa, 159 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb, 160 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc, 161 }; 162 163 enum { 164 /* rq operations */ 165 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, 166 HNS_ROCE_V2_OPCODE_SEND = 0x1, 167 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, 168 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, 169 }; 170 171 enum { 172 HNS_ROCE_V2_SQ_DB = 0x0, 173 HNS_ROCE_V2_RQ_DB = 0x1, 174 HNS_ROCE_V2_SRQ_DB = 0x2, 175 HNS_ROCE_V2_CQ_DB_PTR = 0x3, 176 HNS_ROCE_V2_CQ_DB_NTR = 0x4, 177 }; 178 179 enum { 180 HNS_ROCE_CQE_V2_SUCCESS = 0x00, 181 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, 182 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, 183 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, 184 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, 185 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, 186 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, 187 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, 188 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, 189 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, 190 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, 191 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, 192 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, 193 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, 194 195 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, 196 }; 197 198 /* CMQ command */ 199 enum hns_roce_opcode_type { 200 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, 201 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, 202 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, 203 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, 204 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, 205 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, 206 }; 207 208 enum { 209 TYPE_CRQ, 210 TYPE_CSQ, 211 }; 212 213 enum hns_roce_cmd_return_status { 214 CMD_EXEC_SUCCESS = 0, 215 CMD_NO_AUTH = 1, 216 CMD_NOT_EXEC = 2, 217 CMD_QUEUE_FULL = 3, 218 }; 219 220 enum hns_roce_sgid_type { 221 GID_TYPE_FLAG_ROCE_V1 = 0, 222 GID_TYPE_FLAG_ROCE_V2_IPV4, 223 GID_TYPE_FLAG_ROCE_V2_IPV6, 224 }; 225 226 struct hns_roce_v2_cq_context { 227 __le32 byte_4_pg_ceqn; 228 __le32 byte_8_cqn; 229 __le32 cqe_cur_blk_addr; 230 __le32 byte_16_hop_addr; 231 __le32 cqe_nxt_blk_addr; 232 __le32 byte_24_pgsz_addr; 233 __le32 byte_28_cq_pi; 234 __le32 byte_32_cq_ci; 235 __le32 cqe_ba; 236 __le32 byte_40_cqe_ba; 237 __le32 byte_44_db_record; 238 __le32 db_record_addr; 239 __le32 byte_52_cqe_cnt; 240 __le32 byte_56_cqe_period_maxcnt; 241 __le32 cqe_report_timer; 242 __le32 byte_64_se_cqe_idx; 243 }; 244 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 245 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 246 247 #define V2_CQC_BYTE_4_CQ_ST_S 0 248 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0) 249 250 #define V2_CQC_BYTE_4_POLL_S 2 251 252 #define V2_CQC_BYTE_4_SE_S 3 253 254 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4 255 256 #define V2_CQC_BYTE_4_COALESCE_S 5 257 258 #define V2_CQC_BYTE_4_ARM_ST_S 6 259 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) 260 261 #define V2_CQC_BYTE_4_SHIFT_S 8 262 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8) 263 264 #define V2_CQC_BYTE_4_CMD_SN_S 13 265 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13) 266 267 #define V2_CQC_BYTE_4_CEQN_S 15 268 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) 269 270 #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24 271 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24) 272 273 #define V2_CQC_BYTE_8_CQN_S 0 274 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) 275 276 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0 277 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0) 278 279 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 280 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) 281 282 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0 283 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0) 284 285 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24 286 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24) 287 288 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28 289 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28) 290 291 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 292 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) 293 294 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 295 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) 296 297 #define V2_CQC_BYTE_40_CQE_BA_S 0 298 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0) 299 300 #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0 301 302 #define V2_CQC_BYTE_52_CQE_CNT_S 0 303 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) 304 305 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 306 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) 307 308 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16 309 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) 310 311 #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0 312 #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0) 313 314 enum{ 315 V2_MPT_ST_VALID = 0x1, 316 }; 317 318 enum hns_roce_v2_qp_state { 319 HNS_ROCE_QP_ST_RST, 320 HNS_ROCE_QP_ST_INIT, 321 HNS_ROCE_QP_ST_RTR, 322 HNS_ROCE_QP_ST_RTS, 323 HNS_ROCE_QP_ST_SQER, 324 HNS_ROCE_QP_ST_SQD, 325 HNS_ROCE_QP_ST_ERR, 326 HNS_ROCE_QP_ST_SQ_DRAINING, 327 HNS_ROCE_QP_NUM_ST 328 }; 329 330 struct hns_roce_v2_qp_context { 331 __le32 byte_4_sqpn_tst; 332 __le32 wqe_sge_ba; 333 __le32 byte_12_sq_hop; 334 __le32 byte_16_buf_ba_pg_sz; 335 __le32 byte_20_smac_sgid_idx; 336 __le32 byte_24_mtu_tc; 337 __le32 byte_28_at_fl; 338 u8 dgid[GID_LEN_V2]; 339 __le32 dmac; 340 __le32 byte_52_udpspn_dmac; 341 __le32 byte_56_dqpn_err; 342 __le32 byte_60_qpst_mapid; 343 __le32 qkey_xrcd; 344 __le32 byte_68_rq_db; 345 __le32 rq_db_record_addr; 346 __le32 byte_76_srqn_op_en; 347 __le32 byte_80_rnr_rx_cqn; 348 __le32 byte_84_rq_ci_pi; 349 __le32 rq_cur_blk_addr; 350 __le32 byte_92_srq_info; 351 __le32 byte_96_rx_reqmsn; 352 __le32 rq_nxt_blk_addr; 353 __le32 byte_104_rq_sge; 354 __le32 byte_108_rx_reqepsn; 355 __le32 rq_rnr_timer; 356 __le32 rx_msg_len; 357 __le32 rx_rkey_pkt_info; 358 __le64 rx_va; 359 __le32 byte_132_trrl; 360 __le32 trrl_ba; 361 __le32 byte_140_raq; 362 __le32 byte_144_raq; 363 __le32 byte_148_raq; 364 __le32 byte_152_raq; 365 __le32 byte_156_raq; 366 __le32 byte_160_sq_ci_pi; 367 __le32 sq_cur_blk_addr; 368 __le32 byte_168_irrl_idx; 369 __le32 byte_172_sq_psn; 370 __le32 byte_176_msg_pktn; 371 __le32 sq_cur_sge_blk_addr; 372 __le32 byte_184_irrl_idx; 373 __le32 cur_sge_offset; 374 __le32 byte_192_ext_sge; 375 __le32 byte_196_sq_psn; 376 __le32 byte_200_sq_max; 377 __le32 irrl_ba; 378 __le32 byte_208_irrl; 379 __le32 byte_212_lsn; 380 __le32 sq_timer; 381 __le32 byte_220_retry_psn_msn; 382 __le32 byte_224_retry_msg; 383 __le32 rx_sq_cur_blk_addr; 384 __le32 byte_232_irrl_sge; 385 __le32 irrl_cur_sge_offset; 386 __le32 byte_240_irrl_tail; 387 __le32 byte_244_rnr_rxack; 388 __le32 byte_248_ack_psn; 389 __le32 byte_252_err_txcqn; 390 __le32 byte_256_sqflush_rqcqe; 391 }; 392 393 #define V2_QPC_BYTE_4_TST_S 0 394 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0) 395 396 #define V2_QPC_BYTE_4_SGE_SHIFT_S 3 397 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3) 398 399 #define V2_QPC_BYTE_4_SQPN_S 8 400 #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8) 401 402 #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0 403 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0) 404 405 #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29 406 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29) 407 408 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31 409 410 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0 411 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0) 412 413 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4 414 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4) 415 416 #define V2_QPC_BYTE_16_PD_S 8 417 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8) 418 419 #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0 420 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0) 421 422 #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2 423 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2) 424 425 #define V2_QPC_BYTE_20_RQWS_S 4 426 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4) 427 428 #define V2_QPC_BYTE_20_SQ_SHIFT_S 8 429 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8) 430 431 #define V2_QPC_BYTE_20_RQ_SHIFT_S 12 432 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12) 433 434 #define V2_QPC_BYTE_20_SGID_IDX_S 16 435 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16) 436 437 #define V2_QPC_BYTE_20_SMAC_IDX_S 24 438 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24) 439 440 #define V2_QPC_BYTE_24_HOP_LIMIT_S 0 441 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0) 442 443 #define V2_QPC_BYTE_24_TC_S 8 444 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8) 445 446 #define V2_QPC_BYTE_24_VLAN_IDX_S 16 447 #define V2_QPC_BYTE_24_VLAN_IDX_M GENMASK(27, 16) 448 449 #define V2_QPC_BYTE_24_MTU_S 28 450 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28) 451 452 #define V2_QPC_BYTE_28_FL_S 0 453 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0) 454 455 #define V2_QPC_BYTE_28_SL_S 20 456 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20) 457 458 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24 459 460 #define V2_QPC_BYTE_28_CE_FLAG_S 25 461 462 #define V2_QPC_BYTE_28_LBI_S 26 463 464 #define V2_QPC_BYTE_28_AT_S 27 465 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27) 466 467 #define V2_QPC_BYTE_52_DMAC_S 0 468 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0) 469 470 #define V2_QPC_BYTE_52_UDPSPN_S 16 471 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16) 472 473 #define V2_QPC_BYTE_56_DQPN_S 0 474 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0) 475 476 #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24 477 #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25 478 #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26 479 #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27 480 481 #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28 482 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28) 483 484 #define V2_QPC_BYTE_60_MAPID_S 0 485 #define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0) 486 487 #define V2_QPC_BYTE_60_INNER_MAP_IND_S 13 488 489 #define V2_QPC_BYTE_60_SQ_MAP_IND_S 14 490 491 #define V2_QPC_BYTE_60_RQ_MAP_IND_S 15 492 493 #define V2_QPC_BYTE_60_TEMPID_S 16 494 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16) 495 496 #define V2_QPC_BYTE_60_EXT_MAP_IND_S 23 497 498 #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24 499 #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24) 500 501 #define V2_QPC_BYTE_60_SQ_RLS_IND_S 27 502 503 #define V2_QPC_BYTE_60_SQ_EXT_IND_S 28 504 505 #define V2_QPC_BYTE_60_QP_ST_S 29 506 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29) 507 508 #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0 509 510 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1 511 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1) 512 513 #define V2_QPC_BYTE_76_SRQN_S 0 514 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0) 515 516 #define V2_QPC_BYTE_76_SRQ_EN_S 24 517 518 #define V2_QPC_BYTE_76_RRE_S 25 519 520 #define V2_QPC_BYTE_76_RWE_S 26 521 522 #define V2_QPC_BYTE_76_ATE_S 27 523 524 #define V2_QPC_BYTE_76_RQIE_S 28 525 526 #define V2_QPC_BYTE_80_RX_CQN_S 0 527 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0) 528 529 #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27 530 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27) 531 532 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0 533 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0) 534 535 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16 536 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16) 537 538 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0 539 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0) 540 541 #define V2_QPC_BYTE_92_SRQ_INFO_S 20 542 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20) 543 544 #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0 545 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0) 546 547 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0 548 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0) 549 550 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24 551 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24) 552 553 #define V2_QPC_BYTE_108_INV_CREDIT_S 0 554 555 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3 556 557 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4 558 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4) 559 560 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7 561 562 #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8 563 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8) 564 565 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0 566 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0) 567 568 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8 569 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8) 570 571 #define V2_QPC_BYTE_132_TRRL_BA_S 16 572 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16) 573 574 #define V2_QPC_BYTE_140_TRRL_BA_S 0 575 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0) 576 577 #define V2_QPC_BYTE_140_RR_MAX_S 12 578 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12) 579 580 #define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15 581 582 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16 583 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16) 584 585 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24 586 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24) 587 588 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0 589 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0) 590 591 #define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24 592 593 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25 594 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25) 595 596 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31 597 598 #define V2_QPC_BYTE_148_RQ_MSN_S 0 599 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0) 600 601 #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24 602 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24) 603 604 #define V2_QPC_BYTE_152_RAQ_PSN_S 8 605 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8) 606 607 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24 608 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24) 609 610 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0 611 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0) 612 613 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0 614 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0) 615 616 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16 617 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16) 618 619 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0 620 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) 621 622 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 623 624 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 625 626 #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 627 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) 628 629 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24 630 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24) 631 632 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28 633 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28) 634 635 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0 636 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0) 637 638 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6 639 640 #define V2_QPC_BYTE_172_FRE_S 7 641 642 #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8 643 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8) 644 645 #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0 646 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0) 647 648 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24 649 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24) 650 651 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0 652 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0) 653 654 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20 655 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20) 656 657 #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0 658 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0) 659 660 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24 661 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24) 662 663 #define V2_QPC_BYTE_196_IRRL_HEAD_S 0 664 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0) 665 666 #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8 667 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8) 668 669 #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0 670 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0) 671 672 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16 673 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16) 674 675 #define V2_QPC_BYTE_208_IRRL_BA_S 0 676 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0) 677 678 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26 679 680 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27 681 682 #define V2_QPC_BYTE_208_RMT_E2E_S 28 683 684 #define V2_QPC_BYTE_208_SR_MAX_S 29 685 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29) 686 687 #define V2_QPC_BYTE_212_LSN_S 0 688 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0) 689 690 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24 691 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24) 692 693 #define V2_QPC_BYTE_212_CHECK_FLG_S 27 694 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27) 695 696 #define V2_QPC_BYTE_212_RETRY_CNT_S 29 697 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29) 698 699 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0 700 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0) 701 702 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16 703 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16) 704 705 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0 706 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0) 707 708 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8 709 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8) 710 711 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0 712 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) 713 714 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20 715 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20) 716 717 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0 718 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0) 719 720 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8 721 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8) 722 723 #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16 724 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16) 725 726 #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0 727 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0) 728 729 #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24 730 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24) 731 732 #define V2_QPC_BYTE_244_RNR_CNT_S 27 733 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27) 734 735 #define V2_QPC_BYTE_248_IRRL_PSN_S 0 736 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0) 737 738 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24 739 740 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25 741 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25) 742 743 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27 744 745 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28 746 747 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31 748 749 #define V2_QPC_BYTE_252_TX_CQN_S 0 750 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0) 751 752 #define V2_QPC_BYTE_252_SIG_TYPE_S 24 753 754 #define V2_QPC_BYTE_252_ERR_TYPE_S 25 755 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25) 756 757 #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0 758 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0) 759 760 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16 761 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16) 762 763 struct hns_roce_v2_cqe { 764 __le32 byte_4; 765 union { 766 __le32 rkey; 767 __be32 immtdata; 768 }; 769 __le32 byte_12; 770 __le32 byte_16; 771 __le32 byte_cnt; 772 u8 smac[4]; 773 __le32 byte_28; 774 __le32 byte_32; 775 }; 776 777 #define V2_CQE_BYTE_4_OPCODE_S 0 778 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0) 779 780 #define V2_CQE_BYTE_4_RQ_INLINE_S 5 781 782 #define V2_CQE_BYTE_4_S_R_S 6 783 784 #define V2_CQE_BYTE_4_OWNER_S 7 785 786 #define V2_CQE_BYTE_4_STATUS_S 8 787 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8) 788 789 #define V2_CQE_BYTE_4_WQE_INDX_S 16 790 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16) 791 792 #define V2_CQE_BYTE_12_XRC_SRQN_S 0 793 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0) 794 795 #define V2_CQE_BYTE_16_LCL_QPN_S 0 796 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0) 797 798 #define V2_CQE_BYTE_16_SUB_STATUS_S 24 799 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24) 800 801 #define V2_CQE_BYTE_28_SMAC_4_S 0 802 #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0) 803 804 #define V2_CQE_BYTE_28_SMAC_5_S 8 805 #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8) 806 807 #define V2_CQE_BYTE_28_PORT_TYPE_S 16 808 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16) 809 810 #define V2_CQE_BYTE_32_RMT_QPN_S 0 811 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0) 812 813 #define V2_CQE_BYTE_32_SL_S 24 814 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24) 815 816 #define V2_CQE_BYTE_32_PORTN_S 27 817 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27) 818 819 #define V2_CQE_BYTE_32_GRH_S 30 820 821 #define V2_CQE_BYTE_32_LPK_S 31 822 823 struct hns_roce_v2_mpt_entry { 824 __le32 byte_4_pd_hop_st; 825 __le32 byte_8_mw_cnt_en; 826 __le32 byte_12_mw_pa; 827 __le32 bound_lkey; 828 __le32 len_l; 829 __le32 len_h; 830 __le32 lkey; 831 __le32 va_l; 832 __le32 va_h; 833 __le32 pbl_size; 834 __le32 pbl_ba_l; 835 __le32 byte_48_mode_ba; 836 __le32 pa0_l; 837 __le32 byte_56_pa0_h; 838 __le32 pa1_l; 839 __le32 byte_64_buf_pa1; 840 }; 841 842 #define V2_MPT_BYTE_4_MPT_ST_S 0 843 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) 844 845 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 846 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) 847 848 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 849 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) 850 851 #define V2_MPT_BYTE_4_PD_S 8 852 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) 853 854 #define V2_MPT_BYTE_8_RA_EN_S 0 855 856 #define V2_MPT_BYTE_8_R_INV_EN_S 1 857 858 #define V2_MPT_BYTE_8_L_INV_EN_S 2 859 860 #define V2_MPT_BYTE_8_BIND_EN_S 3 861 862 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4 863 864 #define V2_MPT_BYTE_8_RR_EN_S 5 865 866 #define V2_MPT_BYTE_8_RW_EN_S 6 867 868 #define V2_MPT_BYTE_8_LW_EN_S 7 869 870 #define V2_MPT_BYTE_12_PA_S 1 871 872 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 873 874 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 875 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) 876 877 #define V2_MPT_BYTE_48_PBL_BA_H_S 0 878 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) 879 880 #define V2_MPT_BYTE_48_BLK_MODE_S 29 881 882 #define V2_MPT_BYTE_56_PA0_H_S 0 883 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) 884 885 #define V2_MPT_BYTE_64_PA1_H_S 0 886 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) 887 888 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 889 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) 890 891 #define V2_DB_BYTE_4_TAG_S 0 892 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0) 893 894 #define V2_DB_BYTE_4_CMD_S 24 895 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) 896 897 #define V2_DB_PARAMETER_CONS_IDX_S 0 898 #define V2_DB_PARAMETER_CONS_IDX_M GENMASK(15, 0) 899 900 #define V2_DB_PARAMETER_SL_S 16 901 #define V2_DB_PARAMETER_SL_M GENMASK(18, 16) 902 903 struct hns_roce_v2_cq_db { 904 __le32 byte_4; 905 __le32 parameter; 906 }; 907 908 #define V2_CQ_DB_BYTE_4_TAG_S 0 909 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0) 910 911 #define V2_CQ_DB_BYTE_4_CMD_S 24 912 #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24) 913 914 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0 915 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0) 916 917 #define V2_CQ_DB_PARAMETER_CMD_SN_S 25 918 #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25) 919 920 #define V2_CQ_DB_PARAMETER_NOTIFY_S 24 921 922 struct hns_roce_v2_ud_send_wqe { 923 __le32 byte_4; 924 __le32 msg_len; 925 __be32 immtdata; 926 __le32 byte_16; 927 __le32 byte_20; 928 __le32 byte_24; 929 __le32 qkey; 930 __le32 byte_32; 931 __le32 byte_36; 932 __le32 byte_40; 933 __le32 dmac; 934 __le32 byte_48; 935 u8 dgid[GID_LEN_V2]; 936 937 }; 938 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 939 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) 940 941 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 942 943 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 944 945 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11 946 947 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0 948 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) 949 950 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 951 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) 952 953 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 954 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) 955 956 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 957 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) 958 959 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 960 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) 961 962 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 963 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) 964 965 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 966 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) 967 968 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 969 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) 970 971 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 972 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) 973 974 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20 975 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) 976 977 #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24 978 #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24) 979 980 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 981 982 #define V2_UD_SEND_WQE_DMAC_0_S 0 983 #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0) 984 985 #define V2_UD_SEND_WQE_DMAC_1_S 8 986 #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8) 987 988 #define V2_UD_SEND_WQE_DMAC_2_S 16 989 #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16) 990 991 #define V2_UD_SEND_WQE_DMAC_3_S 24 992 #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24) 993 994 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0 995 #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0) 996 997 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8 998 #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8) 999 1000 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16 1001 #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16) 1002 1003 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24 1004 #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24) 1005 1006 struct hns_roce_v2_rc_send_wqe { 1007 __le32 byte_4; 1008 __le32 msg_len; 1009 union { 1010 __le32 inv_key; 1011 __be32 immtdata; 1012 }; 1013 __le32 byte_16; 1014 __le32 byte_20; 1015 __le32 rkey; 1016 __le64 va; 1017 }; 1018 1019 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 1020 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) 1021 1022 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 1023 1024 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 1025 1026 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 1027 1028 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10 1029 1030 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11 1031 1032 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 1033 1034 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 1035 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) 1036 1037 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 1038 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) 1039 1040 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 1041 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) 1042 1043 struct hns_roce_v2_wqe_data_seg { 1044 __le32 len; 1045 __le32 lkey; 1046 __le64 addr; 1047 }; 1048 1049 struct hns_roce_v2_db { 1050 __le32 byte_4; 1051 __le32 parameter; 1052 }; 1053 1054 struct hns_roce_query_version { 1055 __le16 rocee_vendor_id; 1056 __le16 rocee_hw_version; 1057 __le32 rsv[5]; 1058 }; 1059 1060 struct hns_roce_cfg_global_param { 1061 __le32 time_cfg_udp_port; 1062 __le32 rsv[5]; 1063 }; 1064 1065 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0 1066 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0) 1067 1068 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16 1069 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16) 1070 1071 struct hns_roce_pf_res { 1072 __le32 rsv; 1073 __le32 qpc_bt_idx_num; 1074 __le32 srqc_bt_idx_num; 1075 __le32 cqc_bt_idx_num; 1076 __le32 mpt_bt_idx_num; 1077 __le32 eqc_bt_idx_num; 1078 }; 1079 1080 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0 1081 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0) 1082 1083 #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16 1084 #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16) 1085 1086 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0 1087 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0) 1088 1089 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16 1090 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16) 1091 1092 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0 1093 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0) 1094 1095 #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16 1096 #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16) 1097 1098 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0 1099 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0) 1100 1101 #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16 1102 #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16) 1103 1104 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0 1105 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0) 1106 1107 #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16 1108 #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16) 1109 1110 struct hns_roce_vf_res_a { 1111 __le32 vf_id; 1112 __le32 vf_qpc_bt_idx_num; 1113 __le32 vf_srqc_bt_idx_num; 1114 __le32 vf_cqc_bt_idx_num; 1115 __le32 vf_mpt_bt_idx_num; 1116 __le32 vf_eqc_bt_idx_num; 1117 }; 1118 1119 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0 1120 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0) 1121 1122 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16 1123 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16) 1124 1125 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0 1126 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0) 1127 1128 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16 1129 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16) 1130 1131 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0 1132 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0) 1133 1134 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16 1135 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16) 1136 1137 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0 1138 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0) 1139 1140 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16 1141 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16) 1142 1143 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0 1144 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0) 1145 1146 #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16 1147 #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16) 1148 1149 struct hns_roce_vf_res_b { 1150 __le32 rsv0; 1151 __le32 vf_smac_idx_num; 1152 __le32 vf_sgid_idx_num; 1153 __le32 vf_qid_idx_sl_num; 1154 __le32 rsv[2]; 1155 }; 1156 1157 #define VF_RES_B_DATA_0_VF_ID_S 0 1158 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0) 1159 1160 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0 1161 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0) 1162 1163 #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8 1164 #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8) 1165 1166 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0 1167 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0) 1168 1169 #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8 1170 #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8) 1171 1172 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0 1173 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0) 1174 1175 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16 1176 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) 1177 1178 /* Reg field definition */ 1179 #define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0 1180 #define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0) 1181 1182 #define ROCEE_VF_SGID_CFG4_SGID_TYPE_S 0 1183 #define ROCEE_VF_SGID_CFG4_SGID_TYPE_M GENMASK(1, 0) 1184 1185 struct hns_roce_cfg_bt_attr { 1186 __le32 vf_qpc_cfg; 1187 __le32 vf_srqc_cfg; 1188 __le32 vf_cqc_cfg; 1189 __le32 vf_mpt_cfg; 1190 __le32 rsv[2]; 1191 }; 1192 1193 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0 1194 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0) 1195 1196 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4 1197 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4) 1198 1199 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8 1200 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8) 1201 1202 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0 1203 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0) 1204 1205 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4 1206 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4) 1207 1208 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8 1209 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8) 1210 1211 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0 1212 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0) 1213 1214 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4 1215 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4) 1216 1217 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8 1218 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8) 1219 1220 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0 1221 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0) 1222 1223 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4 1224 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4) 1225 1226 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8 1227 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8) 1228 1229 struct hns_roce_cmq_desc { 1230 __le16 opcode; 1231 __le16 flag; 1232 __le16 retval; 1233 __le16 rsv; 1234 __le32 data[6]; 1235 }; 1236 1237 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 1238 1239 #define HNS_ROCE_HW_RUN_BIT_SHIFT 31 1240 #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF 1241 1242 #define HNS_ROCE_VF_MB4_TAG_MASK 0xFFFFFF00 1243 #define HNS_ROCE_VF_MB4_TAG_SHIFT 8 1244 1245 #define HNS_ROCE_VF_MB4_CMD_MASK 0xFF 1246 #define HNS_ROCE_VF_MB4_CMD_SHIFT 0 1247 1248 #define HNS_ROCE_VF_MB5_EVENT_MASK 0x10000 1249 #define HNS_ROCE_VF_MB5_EVENT_SHIFT 16 1250 1251 #define HNS_ROCE_VF_MB5_TOKEN_MASK 0xFFFF 1252 #define HNS_ROCE_VF_MB5_TOKEN_SHIFT 0 1253 1254 struct hns_roce_v2_cmq_ring { 1255 dma_addr_t desc_dma_addr; 1256 struct hns_roce_cmq_desc *desc; 1257 u32 head; 1258 u32 tail; 1259 1260 u16 buf_size; 1261 u16 desc_num; 1262 int next_to_use; 1263 int next_to_clean; 1264 u8 flag; 1265 spinlock_t lock; /* command queue lock */ 1266 }; 1267 1268 struct hns_roce_v2_cmq { 1269 struct hns_roce_v2_cmq_ring csq; 1270 struct hns_roce_v2_cmq_ring crq; 1271 u16 tx_timeout; 1272 u16 last_status; 1273 }; 1274 1275 struct hns_roce_v2_priv { 1276 struct hns_roce_v2_cmq cmq; 1277 }; 1278 1279 struct hns_roce_eq_context { 1280 __le32 byte_4; 1281 __le32 byte_8; 1282 __le32 byte_12; 1283 __le32 eqe_report_timer; 1284 __le32 eqe_ba0; 1285 __le32 eqe_ba1; 1286 __le32 byte_28; 1287 __le32 byte_32; 1288 __le32 byte_36; 1289 __le32 nxt_eqe_ba0; 1290 __le32 nxt_eqe_ba1; 1291 __le32 rsv[5]; 1292 }; 1293 1294 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 1295 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 1296 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 1297 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 1298 1299 #define HNS_ROCE_V2_EQ_STATE_INVALID 0 1300 #define HNS_ROCE_V2_EQ_STATE_VALID 1 1301 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 1302 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3 1303 1304 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 1305 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 1306 1307 #define HNS_ROCE_V2_EQ_COALESCE_0 0 1308 #define HNS_ROCE_V2_EQ_COALESCE_1 1 1309 1310 #define HNS_ROCE_V2_EQ_FIRED 0 1311 #define HNS_ROCE_V2_EQ_ARMED 1 1312 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 1313 1314 #define HNS_ROCE_EQ_INIT_EQE_CNT 0 1315 #define HNS_ROCE_EQ_INIT_PROD_IDX 0 1316 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 1317 #define HNS_ROCE_EQ_INIT_MSI_IDX 0 1318 #define HNS_ROCE_EQ_INIT_CONS_IDX 0 1319 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 1320 1321 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 1322 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 1323 1324 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 1325 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 1326 1327 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 1328 #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1 1329 #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2 1330 1331 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 1332 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 1333 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 1334 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 1335 1336 #define EQ_ENABLE 1 1337 #define EQ_DISABLE 0 1338 1339 #define EQ_REG_OFFSET 0x4 1340 1341 #define HNS_ROCE_INT_NAME_LEN 32 1342 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0) 1343 1344 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0) 1345 1346 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 1347 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) 1348 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) 1349 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) 1350 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) 1351 1352 /* WORD0 */ 1353 #define HNS_ROCE_EQC_EQ_ST_S 0 1354 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) 1355 1356 #define HNS_ROCE_EQC_HOP_NUM_S 2 1357 #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) 1358 1359 #define HNS_ROCE_EQC_OVER_IGNORE_S 4 1360 #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) 1361 1362 #define HNS_ROCE_EQC_COALESCE_S 5 1363 #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) 1364 1365 #define HNS_ROCE_EQC_ARM_ST_S 6 1366 #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) 1367 1368 #define HNS_ROCE_EQC_EQN_S 8 1369 #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) 1370 1371 #define HNS_ROCE_EQC_EQE_CNT_S 16 1372 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) 1373 1374 /* WORD1 */ 1375 #define HNS_ROCE_EQC_BA_PG_SZ_S 0 1376 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) 1377 1378 #define HNS_ROCE_EQC_BUF_PG_SZ_S 4 1379 #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4) 1380 1381 #define HNS_ROCE_EQC_PROD_INDX_S 8 1382 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8) 1383 1384 /* WORD2 */ 1385 #define HNS_ROCE_EQC_MAX_CNT_S 0 1386 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0) 1387 1388 #define HNS_ROCE_EQC_PERIOD_S 16 1389 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16) 1390 1391 /* WORD3 */ 1392 #define HNS_ROCE_EQC_REPORT_TIMER_S 0 1393 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0) 1394 1395 /* WORD4 */ 1396 #define HNS_ROCE_EQC_EQE_BA_L_S 0 1397 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0) 1398 1399 /* WORD5 */ 1400 #define HNS_ROCE_EQC_EQE_BA_H_S 0 1401 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0) 1402 1403 /* WORD6 */ 1404 #define HNS_ROCE_EQC_SHIFT_S 0 1405 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0) 1406 1407 #define HNS_ROCE_EQC_MSI_INDX_S 8 1408 #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8) 1409 1410 #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16 1411 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16) 1412 1413 /* WORD7 */ 1414 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0 1415 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0) 1416 1417 /* WORD8 */ 1418 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0 1419 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0) 1420 1421 #define HNS_ROCE_EQC_CONS_INDX_S 8 1422 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8) 1423 1424 /* WORD9 */ 1425 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0 1426 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0) 1427 1428 /* WORD10 */ 1429 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0 1430 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0) 1431 1432 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 1433 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) 1434 1435 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 1436 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) 1437 1438 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 1439 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) 1440 1441 #define HNS_ROCE_V2_EQ_DB_CMD_S 16 1442 #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16) 1443 1444 #define HNS_ROCE_V2_EQ_DB_TAG_S 0 1445 #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0) 1446 1447 #define HNS_ROCE_V2_EQ_DB_PARA_S 0 1448 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0) 1449 1450 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 1451 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) 1452 1453 #endif 1454