1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_HW_V2_H 34 #define _HNS_ROCE_HW_V2_H 35 36 #include <linux/bitops.h> 37 38 #define HNS_ROCE_V2_MAX_QP_NUM 0x1000 39 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200 40 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 41 #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000 42 #define HNS_ROCE_V2_MAX_SRQ_SGE 64 43 #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000 44 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100 45 #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000 46 #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000 47 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64 48 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 49 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 50 #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 51 #define HNS_ROCE_V3_MAX_SQ_INLINE 0x400 52 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32 53 #define HNS_ROCE_V2_UAR_NUM 256 54 #define HNS_ROCE_V2_PHY_UAR_NUM 1 55 #define HNS_ROCE_V2_AEQE_VEC_NUM 1 56 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 57 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000 58 #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 59 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 60 #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 61 #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 62 #define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000 63 #define HNS_ROCE_V2_RSV_XRCD_NUM 0 64 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 65 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 66 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 67 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 68 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 69 #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 70 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100 71 #define HNS_ROCE_V2_CQC_ENTRY_SZ 64 72 #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64 73 #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 74 #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 75 #define HNS_ROCE_V2_IDX_ENTRY_SZ 4 76 77 #define HNS_ROCE_V2_SCCC_SZ 32 78 #define HNS_ROCE_V3_SCCC_SZ 64 79 #define HNS_ROCE_V3_GMV_ENTRY_SZ 32 80 81 #define HNS_ROCE_V2_EXT_LLM_ENTRY_SZ 8 82 #define HNS_ROCE_V2_EXT_LLM_MAX_DEPTH 4096 83 84 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE 85 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE 86 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 87 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 88 #define HNS_ROCE_INVALID_LKEY 0x0 89 #define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000 90 #define HNS_ROCE_CMQ_TX_TIMEOUT 30000 91 #define HNS_ROCE_V2_RSV_QPS 8 92 93 #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000 94 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100 95 96 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20 97 98 #define HNS_ROCE_CONTEXT_HOP_NUM 1 99 #define HNS_ROCE_SCCC_HOP_NUM 1 100 #define HNS_ROCE_MTT_HOP_NUM 1 101 #define HNS_ROCE_CQE_HOP_NUM 1 102 #define HNS_ROCE_SRQWQE_HOP_NUM 1 103 #define HNS_ROCE_PBL_HOP_NUM 2 104 #define HNS_ROCE_IDX_HOP_NUM 1 105 #define HNS_ROCE_SQWQE_HOP_NUM 2 106 #define HNS_ROCE_EXT_SGE_HOP_NUM 1 107 #define HNS_ROCE_RQWQE_HOP_NUM 2 108 109 #define HNS_ROCE_V2_EQE_HOP_NUM 2 110 #define HNS_ROCE_V3_EQE_HOP_NUM 1 111 112 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6 113 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2 114 #define HNS_ROCE_V2_GID_INDEX_NUM 16 115 116 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) 117 118 enum { 119 HNS_ROCE_CMD_FLAG_IN = BIT(0), 120 HNS_ROCE_CMD_FLAG_OUT = BIT(1), 121 HNS_ROCE_CMD_FLAG_NEXT = BIT(2), 122 HNS_ROCE_CMD_FLAG_WR = BIT(3), 123 HNS_ROCE_CMD_FLAG_ERR_INTR = BIT(5), 124 }; 125 126 #define HNS_ROCE_CMQ_DESC_NUM_S 3 127 128 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5 129 130 #define HNS_ROCE_CONG_SIZE 64 131 132 #define check_whether_last_step(hop_num, step_idx) \ 133 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ 134 (step_idx == 1 && hop_num == 1) || \ 135 (step_idx == 2 && hop_num == 2)) 136 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0 137 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT) 138 139 #define CMD_CSQ_DESC_NUM 1024 140 #define CMD_CRQ_DESC_NUM 1024 141 142 /* Free mr used parameters */ 143 #define HNS_ROCE_FREE_MR_USED_CQE_NUM 128 144 #define HNS_ROCE_FREE_MR_USED_QP_NUM 0x8 145 #define HNS_ROCE_FREE_MR_USED_PSN 0x0808 146 #define HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT 0x7 147 #define HNS_ROCE_FREE_MR_USED_QP_TIMEOUT 0x12 148 #define HNS_ROCE_FREE_MR_USED_SQWQE_NUM 128 149 #define HNS_ROCE_FREE_MR_USED_SQSGE_NUM 0x2 150 #define HNS_ROCE_FREE_MR_USED_RQWQE_NUM 128 151 #define HNS_ROCE_FREE_MR_USED_RQSGE_NUM 0x2 152 #define HNS_ROCE_V2_FREE_MR_TIMEOUT 4500 153 154 enum { 155 NO_ARMED = 0x0, 156 REG_NXT_CEQE = 0x2, 157 REG_NXT_SE_CEQE = 0x3 158 }; 159 160 enum { 161 CQE_SIZE_32B = 0x0, 162 CQE_SIZE_64B = 0x1 163 }; 164 165 #define V2_CQ_DB_REQ_NOT_SOL 0 166 #define V2_CQ_DB_REQ_NOT 1 167 168 #define V2_CQ_STATE_VALID 1 169 #define V2_QKEY_VAL 0x80010000 170 171 #define GID_LEN_V2 16 172 173 enum { 174 HNS_ROCE_V2_WQE_OP_SEND = 0x0, 175 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, 176 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, 177 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, 178 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, 179 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, 180 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, 181 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, 182 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, 183 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, 184 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, 185 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, 186 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc, 187 HNS_ROCE_V2_WQE_OP_MASK = 0x1f, 188 }; 189 190 enum { 191 /* rq operations */ 192 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, 193 HNS_ROCE_V2_OPCODE_SEND = 0x1, 194 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, 195 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, 196 }; 197 198 enum { 199 HNS_ROCE_V2_SQ_DB, 200 HNS_ROCE_V2_RQ_DB, 201 HNS_ROCE_V2_SRQ_DB, 202 HNS_ROCE_V2_CQ_DB, 203 HNS_ROCE_V2_CQ_DB_NOTIFY 204 }; 205 206 enum { 207 HNS_ROCE_CQE_V2_SUCCESS = 0x00, 208 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, 209 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, 210 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, 211 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, 212 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, 213 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, 214 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, 215 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, 216 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, 217 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, 218 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, 219 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, 220 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, 221 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23, 222 223 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, 224 }; 225 226 /* CMQ command */ 227 enum hns_roce_opcode_type { 228 HNS_QUERY_FW_VER = 0x0001, 229 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, 230 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, 231 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, 232 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, 233 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, 234 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403, 235 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406, 236 HNS_ROCE_OPC_QUERY_FUNC_INFO = 0x8407, 237 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408, 238 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409, 239 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500, 240 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501, 241 HNS_ROCE_OPC_POST_MB = 0x8504, 242 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505, 243 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, 244 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508, 245 HNS_ROCE_OPC_CLR_SCCC = 0x8509, 246 HNS_ROCE_OPC_QUERY_SCCC = 0x850a, 247 HNS_ROCE_OPC_RESET_SCCC = 0x850b, 248 HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO = 0x850d, 249 HNS_ROCE_OPC_QUERY_VF_RES = 0x850e, 250 HNS_ROCE_OPC_CFG_GMV_TBL = 0x850f, 251 HNS_ROCE_OPC_CFG_GMV_BT = 0x8510, 252 HNS_ROCE_OPC_EXT_CFG = 0x8512, 253 HNS_SWITCH_PARAMETER_CFG = 0x1033, 254 }; 255 256 enum { 257 TYPE_CRQ, 258 TYPE_CSQ, 259 }; 260 261 enum hns_roce_cmd_return_status { 262 CMD_EXEC_SUCCESS, 263 CMD_NO_AUTH, 264 CMD_NOT_EXIST, 265 CMD_CRQ_FULL, 266 CMD_NEXT_ERR, 267 CMD_NOT_EXEC, 268 CMD_PARA_ERR, 269 CMD_RESULT_ERR, 270 CMD_TIMEOUT, 271 CMD_HILINK_ERR, 272 CMD_INFO_ILLEGAL, 273 CMD_INVALID, 274 CMD_ROH_CHECK_FAIL, 275 CMD_OTHER_ERR = 0xff 276 }; 277 278 enum hns_roce_sgid_type { 279 GID_TYPE_FLAG_ROCE_V1 = 0, 280 GID_TYPE_FLAG_ROCE_V2_IPV4, 281 GID_TYPE_FLAG_ROCE_V2_IPV6, 282 }; 283 284 struct hns_roce_v2_cq_context { 285 __le32 byte_4_pg_ceqn; 286 __le32 byte_8_cqn; 287 __le32 cqe_cur_blk_addr; 288 __le32 byte_16_hop_addr; 289 __le32 cqe_nxt_blk_addr; 290 __le32 byte_24_pgsz_addr; 291 __le32 byte_28_cq_pi; 292 __le32 byte_32_cq_ci; 293 __le32 cqe_ba; 294 __le32 byte_40_cqe_ba; 295 __le32 byte_44_db_record; 296 __le32 db_record_addr; 297 __le32 byte_52_cqe_cnt; 298 __le32 byte_56_cqe_period_maxcnt; 299 __le32 cqe_report_timer; 300 __le32 byte_64_se_cqe_idx; 301 }; 302 303 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 304 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 305 306 #define V2_CQC_BYTE_4_ARM_ST_S 6 307 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) 308 309 #define V2_CQC_BYTE_4_CEQN_S 15 310 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) 311 312 #define V2_CQC_BYTE_8_CQN_S 0 313 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) 314 315 #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 316 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) 317 318 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 319 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) 320 321 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 322 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) 323 324 #define V2_CQC_BYTE_52_CQE_CNT_S 0 325 #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) 326 327 #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 328 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) 329 330 #define V2_CQC_BYTE_56_CQ_PERIOD_S 16 331 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) 332 333 #define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l) 334 335 #define CQC_CQ_ST CQC_FIELD_LOC(1, 0) 336 #define CQC_POLL CQC_FIELD_LOC(2, 2) 337 #define CQC_SE CQC_FIELD_LOC(3, 3) 338 #define CQC_OVER_IGNORE CQC_FIELD_LOC(4, 4) 339 #define CQC_ARM_ST CQC_FIELD_LOC(7, 6) 340 #define CQC_SHIFT CQC_FIELD_LOC(12, 8) 341 #define CQC_CMD_SN CQC_FIELD_LOC(14, 13) 342 #define CQC_CEQN CQC_FIELD_LOC(23, 15) 343 #define CQC_CQN CQC_FIELD_LOC(55, 32) 344 #define CQC_POE_EN CQC_FIELD_LOC(56, 56) 345 #define CQC_POE_NUM CQC_FIELD_LOC(58, 57) 346 #define CQC_CQE_SIZE CQC_FIELD_LOC(60, 59) 347 #define CQC_CQ_CNT_MODE CQC_FIELD_LOC(61, 61) 348 #define CQC_STASH CQC_FIELD_LOC(63, 63) 349 #define CQC_CQE_CUR_BLK_ADDR_L CQC_FIELD_LOC(95, 64) 350 #define CQC_CQE_CUR_BLK_ADDR_H CQC_FIELD_LOC(115, 96) 351 #define CQC_POE_QID CQC_FIELD_LOC(125, 116) 352 #define CQC_CQE_HOP_NUM CQC_FIELD_LOC(127, 126) 353 #define CQC_CQE_NEX_BLK_ADDR_L CQC_FIELD_LOC(159, 128) 354 #define CQC_CQE_NEX_BLK_ADDR_H CQC_FIELD_LOC(179, 160) 355 #define CQC_CQE_BAR_PG_SZ CQC_FIELD_LOC(187, 184) 356 #define CQC_CQE_BUF_PG_SZ CQC_FIELD_LOC(191, 188) 357 #define CQC_CQ_PRODUCER_IDX CQC_FIELD_LOC(215, 192) 358 #define CQC_CQ_CONSUMER_IDX CQC_FIELD_LOC(247, 224) 359 #define CQC_CQE_BA_L CQC_FIELD_LOC(287, 256) 360 #define CQC_CQE_BA_H CQC_FIELD_LOC(316, 288) 361 #define CQC_POE_QID_H_0 CQC_FIELD_LOC(319, 317) 362 #define CQC_DB_RECORD_EN CQC_FIELD_LOC(320, 320) 363 #define CQC_CQE_DB_RECORD_ADDR_L CQC_FIELD_LOC(351, 321) 364 #define CQC_CQE_DB_RECORD_ADDR_H CQC_FIELD_LOC(383, 352) 365 #define CQC_CQE_CNT CQC_FIELD_LOC(407, 384) 366 #define CQC_CQ_MAX_CNT CQC_FIELD_LOC(431, 416) 367 #define CQC_CQ_PERIOD CQC_FIELD_LOC(447, 432) 368 #define CQC_CQE_REPORT_TIMER CQC_FIELD_LOC(471, 448) 369 #define CQC_WR_CQE_IDX CQC_FIELD_LOC(479, 472) 370 #define CQC_SE_CQE_IDX CQC_FIELD_LOC(503, 480) 371 #define CQC_POE_QID_H_1 CQC_FIELD_LOC(511, 511) 372 373 struct hns_roce_srq_context { 374 __le32 data[16]; 375 }; 376 377 #define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l) 378 379 #define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0) 380 #define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2) 381 #define SRQC_SHIFT SRQC_FIELD_LOC(7, 4) 382 #define SRQC_SRQN SRQC_FIELD_LOC(31, 8) 383 #define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32) 384 #define SRQC_RSV0 SRQC_FIELD_LOC(63, 48) 385 #define SRQC_XRCD SRQC_FIELD_LOC(87, 64) 386 #define SRQC_RSV1 SRQC_FIELD_LOC(95, 88) 387 #define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96) 388 #define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112) 389 #define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128) 390 #define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160) 391 #define SRQC_RSV2 SRQC_FIELD_LOC(190, 189) 392 #define SRQC_SRQ_TYPE SRQC_FIELD_LOC(191, 191) 393 #define SRQC_PD SRQC_FIELD_LOC(215, 192) 394 #define SRQC_RQWS SRQC_FIELD_LOC(219, 216) 395 #define SRQC_RSV3 SRQC_FIELD_LOC(223, 220) 396 #define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224) 397 #define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256) 398 #define SRQC_RSV4 SRQC_FIELD_LOC(287, 285) 399 #define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288) 400 #define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320) 401 #define SRQC_RSV5 SRQC_FIELD_LOC(341, 340) 402 #define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342) 403 #define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344) 404 #define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348) 405 #define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352) 406 #define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384) 407 #define SRQC_RSV6 SRQC_FIELD_LOC(415, 404) 408 #define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416) 409 #define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440) 410 #define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444) 411 #define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448) 412 #define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449) 413 #define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480) 414 415 enum { 416 V2_MPT_ST_VALID = 0x1, 417 V2_MPT_ST_FREE = 0x2, 418 }; 419 420 enum hns_roce_v2_qp_state { 421 HNS_ROCE_QP_ST_RST, 422 HNS_ROCE_QP_ST_INIT, 423 HNS_ROCE_QP_ST_RTR, 424 HNS_ROCE_QP_ST_RTS, 425 HNS_ROCE_QP_ST_SQD, 426 HNS_ROCE_QP_ST_SQER, 427 HNS_ROCE_QP_ST_ERR, 428 HNS_ROCE_QP_ST_SQ_DRAINING, 429 HNS_ROCE_QP_NUM_ST 430 }; 431 432 struct hns_roce_v2_qp_context_ex { 433 __le32 data[64]; 434 }; 435 struct hns_roce_v2_qp_context { 436 __le32 byte_4_sqpn_tst; 437 __le32 wqe_sge_ba; 438 __le32 byte_12_sq_hop; 439 __le32 byte_16_buf_ba_pg_sz; 440 __le32 byte_20_smac_sgid_idx; 441 __le32 byte_24_mtu_tc; 442 __le32 byte_28_at_fl; 443 u8 dgid[GID_LEN_V2]; 444 __le32 dmac; 445 __le32 byte_52_udpspn_dmac; 446 __le32 byte_56_dqpn_err; 447 __le32 byte_60_qpst_tempid; 448 __le32 qkey_xrcd; 449 __le32 byte_68_rq_db; 450 __le32 rq_db_record_addr; 451 __le32 byte_76_srqn_op_en; 452 __le32 byte_80_rnr_rx_cqn; 453 __le32 byte_84_rq_ci_pi; 454 __le32 rq_cur_blk_addr; 455 __le32 byte_92_srq_info; 456 __le32 byte_96_rx_reqmsn; 457 __le32 rq_nxt_blk_addr; 458 __le32 byte_104_rq_sge; 459 __le32 byte_108_rx_reqepsn; 460 __le32 rq_rnr_timer; 461 __le32 rx_msg_len; 462 __le32 rx_rkey_pkt_info; 463 __le64 rx_va; 464 __le32 byte_132_trrl; 465 __le32 trrl_ba; 466 __le32 byte_140_raq; 467 __le32 byte_144_raq; 468 __le32 byte_148_raq; 469 __le32 byte_152_raq; 470 __le32 byte_156_raq; 471 __le32 byte_160_sq_ci_pi; 472 __le32 sq_cur_blk_addr; 473 __le32 byte_168_irrl_idx; 474 __le32 byte_172_sq_psn; 475 __le32 byte_176_msg_pktn; 476 __le32 sq_cur_sge_blk_addr; 477 __le32 byte_184_irrl_idx; 478 __le32 cur_sge_offset; 479 __le32 byte_192_ext_sge; 480 __le32 byte_196_sq_psn; 481 __le32 byte_200_sq_max; 482 __le32 irrl_ba; 483 __le32 byte_208_irrl; 484 __le32 byte_212_lsn; 485 __le32 sq_timer; 486 __le32 byte_220_retry_psn_msn; 487 __le32 byte_224_retry_msg; 488 __le32 rx_sq_cur_blk_addr; 489 __le32 byte_232_irrl_sge; 490 __le32 irrl_cur_sge_offset; 491 __le32 byte_240_irrl_tail; 492 __le32 byte_244_rnr_rxack; 493 __le32 byte_248_ack_psn; 494 __le32 byte_252_err_txcqn; 495 __le32 byte_256_sqflush_rqcqe; 496 497 struct hns_roce_v2_qp_context_ex ext; 498 }; 499 500 #define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l) 501 502 #define QPC_TST QPC_FIELD_LOC(2, 0) 503 #define QPC_SGE_SHIFT QPC_FIELD_LOC(7, 3) 504 #define QPC_CNP_TIMER QPC_FIELD_LOC(31, 8) 505 #define QPC_WQE_SGE_BA_L QPC_FIELD_LOC(63, 32) 506 #define QPC_WQE_SGE_BA_H QPC_FIELD_LOC(92, 64) 507 #define QPC_SQ_HOP_NUM QPC_FIELD_LOC(94, 93) 508 #define QPC_CIRE_EN QPC_FIELD_LOC(95, 95) 509 #define QPC_WQE_SGE_BA_PG_SZ QPC_FIELD_LOC(99, 96) 510 #define QPC_WQE_SGE_BUF_PG_SZ QPC_FIELD_LOC(103, 100) 511 #define QPC_PD QPC_FIELD_LOC(127, 104) 512 #define QPC_RQ_HOP_NUM QPC_FIELD_LOC(129, 128) 513 #define QPC_SGE_HOP_NUM QPC_FIELD_LOC(131, 130) 514 #define QPC_RQWS QPC_FIELD_LOC(135, 132) 515 #define QPC_SQ_SHIFT QPC_FIELD_LOC(139, 136) 516 #define QPC_RQ_SHIFT QPC_FIELD_LOC(143, 140) 517 #define QPC_GMV_IDX QPC_FIELD_LOC(159, 144) 518 #define QPC_HOPLIMIT QPC_FIELD_LOC(167, 160) 519 #define QPC_TC QPC_FIELD_LOC(175, 168) 520 #define QPC_VLAN_ID QPC_FIELD_LOC(187, 176) 521 #define QPC_MTU QPC_FIELD_LOC(191, 188) 522 #define QPC_FL QPC_FIELD_LOC(211, 192) 523 #define QPC_SL QPC_FIELD_LOC(215, 212) 524 #define QPC_CNP_TX_FLAG QPC_FIELD_LOC(216, 216) 525 #define QPC_CE_FLAG QPC_FIELD_LOC(217, 217) 526 #define QPC_LBI QPC_FIELD_LOC(218, 218) 527 #define QPC_AT QPC_FIELD_LOC(223, 219) 528 #define QPC_DGID QPC_FIELD_LOC(351, 224) 529 #define QPC_DMAC_L QPC_FIELD_LOC(383, 352) 530 #define QPC_DMAC_H QPC_FIELD_LOC(399, 384) 531 #define QPC_UDPSPN QPC_FIELD_LOC(415, 400) 532 #define QPC_DQPN QPC_FIELD_LOC(439, 416) 533 #define QPC_SQ_TX_ERR QPC_FIELD_LOC(440, 440) 534 #define QPC_SQ_RX_ERR QPC_FIELD_LOC(441, 441) 535 #define QPC_RQ_TX_ERR QPC_FIELD_LOC(442, 442) 536 #define QPC_RQ_RX_ERR QPC_FIELD_LOC(443, 443) 537 #define QPC_LP_PKTN_INI QPC_FIELD_LOC(447, 444) 538 #define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448) 539 #define QPC_SCC_TOKEN QPC_FIELD_LOC(474, 456) 540 #define QPC_SQ_DB_DOING QPC_FIELD_LOC(475, 475) 541 #define QPC_RQ_DB_DOING QPC_FIELD_LOC(476, 476) 542 #define QPC_QP_ST QPC_FIELD_LOC(479, 477) 543 #define QPC_QKEY_XRCD QPC_FIELD_LOC(511, 480) 544 #define QPC_RQ_RECORD_EN QPC_FIELD_LOC(512, 512) 545 #define QPC_RQ_DB_RECORD_ADDR_L QPC_FIELD_LOC(543, 513) 546 #define QPC_RQ_DB_RECORD_ADDR_H QPC_FIELD_LOC(575, 544) 547 #define QPC_SRQN QPC_FIELD_LOC(599, 576) 548 #define QPC_SRQ_EN QPC_FIELD_LOC(600, 600) 549 #define QPC_RRE QPC_FIELD_LOC(601, 601) 550 #define QPC_RWE QPC_FIELD_LOC(602, 602) 551 #define QPC_ATE QPC_FIELD_LOC(603, 603) 552 #define QPC_RQIE QPC_FIELD_LOC(604, 604) 553 #define QPC_EXT_ATE QPC_FIELD_LOC(605, 605) 554 #define QPC_RQ_VLAN_EN QPC_FIELD_LOC(606, 606) 555 #define QPC_RQ_RTY_TX_ERR QPC_FIELD_LOC(607, 607) 556 #define QPC_RX_CQN QPC_FIELD_LOC(631, 608) 557 #define QPC_XRC_QP_TYPE QPC_FIELD_LOC(632, 632) 558 #define QPC_RSV3 QPC_FIELD_LOC(634, 633) 559 #define QPC_MIN_RNR_TIME QPC_FIELD_LOC(639, 635) 560 #define QPC_RQ_PRODUCER_IDX QPC_FIELD_LOC(655, 640) 561 #define QPC_RQ_CONSUMER_IDX QPC_FIELD_LOC(671, 656) 562 #define QPC_RQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(703, 672) 563 #define QPC_RQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(723, 704) 564 #define QPC_SRQ_INFO QPC_FIELD_LOC(735, 724) 565 #define QPC_RX_REQ_MSN QPC_FIELD_LOC(759, 736) 566 #define QPC_REDUCE_CODE QPC_FIELD_LOC(766, 760) 567 #define QPC_RX_XRC_PKT_CQE_FLG QPC_FIELD_LOC(767, 767) 568 #define QPC_RQ_NXT_BLK_ADDR_L QPC_FIELD_LOC(799, 768) 569 #define QPC_RQ_NXT_BLK_ADDR_H QPC_FIELD_LOC(819, 800) 570 #define QPC_REDUCE_EN QPC_FIELD_LOC(820, 820) 571 #define QPC_FLUSH_EN QPC_FIELD_LOC(821, 821) 572 #define QPC_AW_EN QPC_FIELD_LOC(822, 822) 573 #define QPC_WN_EN QPC_FIELD_LOC(823, 823) 574 #define QPC_RQ_CUR_WQE_SGE_NUM QPC_FIELD_LOC(831, 824) 575 #define QPC_INV_CREDIT QPC_FIELD_LOC(832, 832) 576 #define QPC_LAST_WRITE_TYPE QPC_FIELD_LOC(834, 833) 577 #define QPC_RX_REQ_PSN_ERR QPC_FIELD_LOC(835, 835) 578 #define QPC_RX_REQ_LAST_OPTYPE QPC_FIELD_LOC(838, 836) 579 #define QPC_RX_REQ_RNR QPC_FIELD_LOC(839, 839) 580 #define QPC_RX_REQ_EPSN QPC_FIELD_LOC(863, 840) 581 #define QPC_RQ_RNR_TIMER QPC_FIELD_LOC(895, 864) 582 #define QPC_RX_MSG_LEN QPC_FIELD_LOC(927, 896) 583 #define QPC_RX_RKEY_PKT_INFO QPC_FIELD_LOC(959, 928) 584 #define QPC_RX_VA QPC_FIELD_LOC(1023, 960) 585 #define QPC_TRRL_HEAD_MAX QPC_FIELD_LOC(1031, 1024) 586 #define QPC_TRRL_TAIL_MAX QPC_FIELD_LOC(1039, 1032) 587 #define QPC_TRRL_BA_L QPC_FIELD_LOC(1055, 1040) 588 #define QPC_TRRL_BA_M QPC_FIELD_LOC(1087, 1056) 589 #define QPC_TRRL_BA_H QPC_FIELD_LOC(1099, 1088) 590 #define QPC_RR_MAX QPC_FIELD_LOC(1102, 1100) 591 #define QPC_RQ_RTY_WAIT_DO QPC_FIELD_LOC(1103, 1103) 592 #define QPC_RAQ_TRRL_HEAD QPC_FIELD_LOC(1111, 1104) 593 #define QPC_RAQ_TRRL_TAIL QPC_FIELD_LOC(1119, 1112) 594 #define QPC_RAQ_RTY_INI_PSN QPC_FIELD_LOC(1143, 1120) 595 #define QPC_CIRE_SLV_RQ_EN QPC_FIELD_LOC(1144, 1144) 596 #define QPC_RAQ_CREDIT QPC_FIELD_LOC(1149, 1145) 597 #define QPC_RQ_DB_IN_EXT QPC_FIELD_LOC(1150, 1150) 598 #define QPC_RESP_RTY_FLG QPC_FIELD_LOC(1151, 1151) 599 #define QPC_RAQ_MSN QPC_FIELD_LOC(1175, 1152) 600 #define QPC_RAQ_SYNDROME QPC_FIELD_LOC(1183, 1176) 601 #define QPC_RAQ_PSN QPC_FIELD_LOC(1207, 1184) 602 #define QPC_RAQ_TRRL_RTY_HEAD QPC_FIELD_LOC(1215, 1208) 603 #define QPC_RAQ_USE_PKTN QPC_FIELD_LOC(1239, 1216) 604 #define QPC_RQ_SCC_TOKEN QPC_FIELD_LOC(1245, 1240) 605 #define QPC_RVD10 QPC_FIELD_LOC(1247, 1246) 606 #define QPC_SQ_PRODUCER_IDX QPC_FIELD_LOC(1263, 1248) 607 #define QPC_SQ_CONSUMER_IDX QPC_FIELD_LOC(1279, 1264) 608 #define QPC_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1311, 1280) 609 #define QPC_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1331, 1312) 610 #define QPC_MSG_RTY_LP_FLG QPC_FIELD_LOC(1332, 1332) 611 #define QPC_SQ_INVLD_FLG QPC_FIELD_LOC(1333, 1333) 612 #define QPC_LP_SGEN_INI QPC_FIELD_LOC(1335, 1334) 613 #define QPC_SQ_VLAN_EN QPC_FIELD_LOC(1336, 1336) 614 #define QPC_POLL_DB_WAIT_DO QPC_FIELD_LOC(1337, 1337) 615 #define QPC_SCC_TOKEN_FORBID_SQ_DEQ QPC_FIELD_LOC(1338, 1338) 616 #define QPC_WAIT_ACK_TIMEOUT QPC_FIELD_LOC(1339, 1339) 617 #define QPC_IRRL_IDX_LSB QPC_FIELD_LOC(1343, 1340) 618 #define QPC_ACK_REQ_FREQ QPC_FIELD_LOC(1349, 1344) 619 #define QPC_MSG_RNR_FLG QPC_FIELD_LOC(1350, 1350) 620 #define QPC_FRE QPC_FIELD_LOC(1351, 1351) 621 #define QPC_SQ_CUR_PSN QPC_FIELD_LOC(1375, 1352) 622 #define QPC_MSG_USE_PKTN QPC_FIELD_LOC(1399, 1376) 623 #define QPC_IRRL_HEAD_PRE QPC_FIELD_LOC(1407, 1400) 624 #define QPC_SQ_CUR_SGE_BLK_ADDR_L QPC_FIELD_LOC(1439, 1408) 625 #define QPC_SQ_CUR_SGE_BLK_ADDR_H QPC_FIELD_LOC(1459, 1440) 626 #define QPC_IRRL_IDX_MSB QPC_FIELD_LOC(1471, 1460) 627 #define QPC_CUR_SGE_OFFSET QPC_FIELD_LOC(1503, 1472) 628 #define QPC_CUR_SGE_IDX QPC_FIELD_LOC(1527, 1504) 629 #define QPC_EXT_SGE_NUM_LEFT QPC_FIELD_LOC(1535, 1528) 630 #define QPC_OWNER_MODE QPC_FIELD_LOC(1536, 1536) 631 #define QPC_CIRE_SLV_SQ_EN QPC_FIELD_LOC(1537, 1537) 632 #define QPC_CIRE_DOING QPC_FIELD_LOC(1538, 1538) 633 #define QPC_CIRE_RESULT QPC_FIELD_LOC(1539, 1539) 634 #define QPC_OWNER_DB_WAIT_DO QPC_FIELD_LOC(1540, 1540) 635 #define QPC_SQ_WQE_INVLD QPC_FIELD_LOC(1541, 1541) 636 #define QPC_DCA_MODE QPC_FIELD_LOC(1542, 1542) 637 #define QPC_RTY_OWNER_NOCHK QPC_FIELD_LOC(1543, 1543) 638 #define QPC_V2_IRRL_HEAD QPC_FIELD_LOC(1543, 1536) 639 #define QPC_SQ_MAX_PSN QPC_FIELD_LOC(1567, 1544) 640 #define QPC_SQ_MAX_IDX QPC_FIELD_LOC(1583, 1568) 641 #define QPC_LCL_OPERATED_CNT QPC_FIELD_LOC(1599, 1584) 642 #define QPC_IRRL_BA_L QPC_FIELD_LOC(1631, 1600) 643 #define QPC_IRRL_BA_H QPC_FIELD_LOC(1657, 1632) 644 #define QPC_PKT_RNR_FLG QPC_FIELD_LOC(1658, 1658) 645 #define QPC_PKT_RTY_FLG QPC_FIELD_LOC(1659, 1659) 646 #define QPC_RMT_E2E QPC_FIELD_LOC(1660, 1660) 647 #define QPC_SR_MAX QPC_FIELD_LOC(1663, 1661) 648 #define QPC_LSN QPC_FIELD_LOC(1687, 1664) 649 #define QPC_RETRY_NUM_INIT QPC_FIELD_LOC(1690, 1688) 650 #define QPC_CHECK_FLG QPC_FIELD_LOC(1692, 1691) 651 #define QPC_RETRY_CNT QPC_FIELD_LOC(1695, 1693) 652 #define QPC_SQ_TIMER QPC_FIELD_LOC(1727, 1696) 653 #define QPC_RETRY_MSG_MSN QPC_FIELD_LOC(1743, 1728) 654 #define QPC_RETRY_MSG_PSN_L QPC_FIELD_LOC(1759, 1744) 655 #define QPC_RETRY_MSG_PSN_H QPC_FIELD_LOC(1767, 1760) 656 #define QPC_RETRY_MSG_FPKT_PSN QPC_FIELD_LOC(1791, 1768) 657 #define QPC_RX_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1823, 1792) 658 #define QPC_RX_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1843, 1824) 659 #define QPC_IRRL_SGE_IDX QPC_FIELD_LOC(1851, 1844) 660 #define QPC_LSAN_EN QPC_FIELD_LOC(1852, 1852) 661 #define QPC_SO_LP_VLD QPC_FIELD_LOC(1853, 1853) 662 #define QPC_FENCE_LP_VLD QPC_FIELD_LOC(1854, 1854) 663 #define QPC_IRRL_LP_VLD QPC_FIELD_LOC(1855, 1855) 664 #define QPC_IRRL_CUR_SGE_OFFSET QPC_FIELD_LOC(1887, 1856) 665 #define QPC_IRRL_TAIL_REAL QPC_FIELD_LOC(1895, 1888) 666 #define QPC_IRRL_TAIL_RD QPC_FIELD_LOC(1903, 1896) 667 #define QPC_RX_ACK_MSN QPC_FIELD_LOC(1919, 1904) 668 #define QPC_RX_ACK_EPSN QPC_FIELD_LOC(1943, 1920) 669 #define QPC_RNR_NUM_INIT QPC_FIELD_LOC(1946, 1944) 670 #define QPC_RNR_CNT QPC_FIELD_LOC(1949, 1947) 671 #define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950) 672 #define QPC_IRRL_RD_FLG QPC_FIELD_LOC(1951, 1951) 673 #define QPC_IRRL_PSN QPC_FIELD_LOC(1975, 1952) 674 #define QPC_ACK_PSN_ERR QPC_FIELD_LOC(1976, 1976) 675 #define QPC_ACK_LAST_OPTYPE QPC_FIELD_LOC(1978, 1977) 676 #define QPC_IRRL_PSN_VLD QPC_FIELD_LOC(1979, 1979) 677 #define QPC_RNR_RETRY_FLAG QPC_FIELD_LOC(1980, 1980) 678 #define QPC_SQ_RTY_TX_ERR QPC_FIELD_LOC(1981, 1981) 679 #define QPC_LAST_IND QPC_FIELD_LOC(1982, 1982) 680 #define QPC_CQ_ERR_IND QPC_FIELD_LOC(1983, 1983) 681 #define QPC_TX_CQN QPC_FIELD_LOC(2007, 1984) 682 #define QPC_SIG_TYPE QPC_FIELD_LOC(2008, 2008) 683 #define QPC_ERR_TYPE QPC_FIELD_LOC(2015, 2009) 684 #define QPC_RQ_CQE_IDX QPC_FIELD_LOC(2031, 2016) 685 #define QPC_SQ_FLUSH_IDX QPC_FIELD_LOC(2047, 2032) 686 687 #define RETRY_MSG_PSN_SHIFT 16 688 689 #define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l) 690 691 #define QPCEX_CONG_ALG_SEL QPCEX_FIELD_LOC(0, 0) 692 #define QPCEX_CONG_ALG_SUB_SEL QPCEX_FIELD_LOC(1, 1) 693 #define QPCEX_DIP_CTX_IDX_VLD QPCEX_FIELD_LOC(2, 2) 694 #define QPCEX_DIP_CTX_IDX QPCEX_FIELD_LOC(22, 3) 695 #define QPCEX_SQ_RQ_NOT_FORBID_EN QPCEX_FIELD_LOC(23, 23) 696 #define QPCEX_STASH QPCEX_FIELD_LOC(82, 82) 697 698 #define V2_QP_RWE_S 1 /* rdma write enable */ 699 #define V2_QP_RRE_S 2 /* rdma read enable */ 700 #define V2_QP_ATE_S 3 /* rdma atomic enable */ 701 702 struct hns_roce_v2_cqe { 703 __le32 byte_4; 704 union { 705 __le32 rkey; 706 __le32 immtdata; 707 }; 708 __le32 byte_12; 709 __le32 byte_16; 710 __le32 byte_cnt; 711 u8 smac[4]; 712 __le32 byte_28; 713 __le32 byte_32; 714 __le32 rsv[8]; 715 }; 716 717 #define CQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cqe, h, l) 718 719 #define CQE_OPCODE CQE_FIELD_LOC(4, 0) 720 #define CQE_RQ_INLINE CQE_FIELD_LOC(5, 5) 721 #define CQE_S_R CQE_FIELD_LOC(6, 6) 722 #define CQE_OWNER CQE_FIELD_LOC(7, 7) 723 #define CQE_STATUS CQE_FIELD_LOC(15, 8) 724 #define CQE_WQE_IDX CQE_FIELD_LOC(31, 16) 725 #define CQE_RKEY_IMMTDATA CQE_FIELD_LOC(63, 32) 726 #define CQE_XRC_SRQN CQE_FIELD_LOC(87, 64) 727 #define CQE_RSV0 CQE_FIELD_LOC(95, 88) 728 #define CQE_LCL_QPN CQE_FIELD_LOC(119, 96) 729 #define CQE_SUB_STATUS CQE_FIELD_LOC(127, 120) 730 #define CQE_BYTE_CNT CQE_FIELD_LOC(159, 128) 731 #define CQE_SMAC CQE_FIELD_LOC(207, 160) 732 #define CQE_PORT_TYPE CQE_FIELD_LOC(209, 208) 733 #define CQE_VID CQE_FIELD_LOC(221, 210) 734 #define CQE_VID_VLD CQE_FIELD_LOC(222, 222) 735 #define CQE_RSV2 CQE_FIELD_LOC(223, 223) 736 #define CQE_RMT_QPN CQE_FIELD_LOC(247, 224) 737 #define CQE_SL CQE_FIELD_LOC(250, 248) 738 #define CQE_PORTN CQE_FIELD_LOC(253, 251) 739 #define CQE_GRH CQE_FIELD_LOC(254, 254) 740 #define CQE_LPK CQE_FIELD_LOC(255, 255) 741 #define CQE_RSV3 CQE_FIELD_LOC(511, 256) 742 743 struct hns_roce_v2_mpt_entry { 744 __le32 byte_4_pd_hop_st; 745 __le32 byte_8_mw_cnt_en; 746 __le32 byte_12_mw_pa; 747 __le32 bound_lkey; 748 __le32 len_l; 749 __le32 len_h; 750 __le32 lkey; 751 __le32 va_l; 752 __le32 va_h; 753 __le32 pbl_size; 754 __le32 pbl_ba_l; 755 __le32 byte_48_mode_ba; 756 __le32 pa0_l; 757 __le32 byte_56_pa0_h; 758 __le32 pa1_l; 759 __le32 byte_64_buf_pa1; 760 }; 761 762 #define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l) 763 764 #define MPT_ST MPT_FIELD_LOC(1, 0) 765 #define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2) 766 #define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4) 767 #define MPT_PD MPT_FIELD_LOC(31, 8) 768 #define MPT_RA_EN MPT_FIELD_LOC(32, 32) 769 #define MPT_R_INV_EN MPT_FIELD_LOC(33, 33) 770 #define MPT_L_INV_EN MPT_FIELD_LOC(34, 34) 771 #define MPT_BIND_EN MPT_FIELD_LOC(35, 35) 772 #define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36) 773 #define MPT_RR_EN MPT_FIELD_LOC(37, 37) 774 #define MPT_RW_EN MPT_FIELD_LOC(38, 38) 775 #define MPT_LW_EN MPT_FIELD_LOC(39, 39) 776 #define MPT_MW_CNT MPT_FIELD_LOC(63, 40) 777 #define MPT_FRE MPT_FIELD_LOC(64, 64) 778 #define MPT_PA MPT_FIELD_LOC(65, 65) 779 #define MPT_ZBVA MPT_FIELD_LOC(66, 66) 780 #define MPT_SHARE MPT_FIELD_LOC(67, 67) 781 #define MPT_MR_MW MPT_FIELD_LOC(68, 68) 782 #define MPT_BPD MPT_FIELD_LOC(69, 69) 783 #define MPT_BQP MPT_FIELD_LOC(70, 70) 784 #define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71) 785 #define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72) 786 #define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96) 787 #define MPT_LEN MPT_FIELD_LOC(191, 128) 788 #define MPT_LKEY MPT_FIELD_LOC(223, 192) 789 #define MPT_VA MPT_FIELD_LOC(287, 224) 790 #define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288) 791 #define MPT_PBL_BA MPT_FIELD_LOC(380, 320) 792 #define MPT_BLK_MODE MPT_FIELD_LOC(381, 381) 793 #define MPT_RSV0 MPT_FIELD_LOC(383, 382) 794 #define MPT_PA0 MPT_FIELD_LOC(441, 384) 795 #define MPT_BOUND_VA MPT_FIELD_LOC(447, 442) 796 #define MPT_PA1 MPT_FIELD_LOC(505, 448) 797 #define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506) 798 #define MPT_RSV2 MPT_FIELD_LOC(507, 507) 799 #define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508) 800 801 #define V2_MPT_BYTE_4_MPT_ST_S 0 802 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) 803 804 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 805 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) 806 807 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 808 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) 809 810 #define V2_MPT_BYTE_4_PD_S 8 811 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) 812 813 #define V2_MPT_BYTE_8_RA_EN_S 0 814 815 #define V2_MPT_BYTE_8_R_INV_EN_S 1 816 817 #define V2_MPT_BYTE_8_L_INV_EN_S 2 818 819 #define V2_MPT_BYTE_8_BIND_EN_S 3 820 821 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4 822 823 #define V2_MPT_BYTE_8_RR_EN_S 5 824 825 #define V2_MPT_BYTE_8_RW_EN_S 6 826 827 #define V2_MPT_BYTE_8_LW_EN_S 7 828 829 #define V2_MPT_BYTE_8_MW_CNT_S 8 830 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8) 831 832 #define V2_MPT_BYTE_12_FRE_S 0 833 834 #define V2_MPT_BYTE_12_PA_S 1 835 836 #define V2_MPT_BYTE_12_MR_MW_S 4 837 838 #define V2_MPT_BYTE_12_BPD_S 5 839 840 #define V2_MPT_BYTE_12_BQP_S 6 841 842 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 843 844 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 845 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) 846 847 #define V2_MPT_BYTE_48_PBL_BA_H_S 0 848 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) 849 850 #define V2_MPT_BYTE_48_BLK_MODE_S 29 851 852 #define V2_MPT_BYTE_56_PA0_H_S 0 853 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) 854 855 #define V2_MPT_BYTE_64_PA1_H_S 0 856 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) 857 858 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 859 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) 860 861 struct hns_roce_v2_db { 862 __le32 data[2]; 863 }; 864 865 #define DB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_db, h, l) 866 867 #define DB_TAG DB_FIELD_LOC(23, 0) 868 #define DB_CMD DB_FIELD_LOC(27, 24) 869 #define DB_FLAG DB_FIELD_LOC(31, 31) 870 #define DB_PI DB_FIELD_LOC(47, 32) 871 #define DB_SL DB_FIELD_LOC(50, 48) 872 #define DB_CQ_CI DB_FIELD_LOC(55, 32) 873 #define DB_CQ_NOTIFY DB_FIELD_LOC(56, 56) 874 #define DB_CQ_CMD_SN DB_FIELD_LOC(58, 57) 875 #define EQ_DB_TAG DB_FIELD_LOC(7, 0) 876 #define EQ_DB_CMD DB_FIELD_LOC(17, 16) 877 #define EQ_DB_CI DB_FIELD_LOC(55, 32) 878 879 #define V2_DB_PRODUCER_IDX_S 0 880 #define V2_DB_PRODUCER_IDX_M GENMASK(15, 0) 881 882 #define V2_CQ_DB_CONS_IDX_S 0 883 #define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0) 884 885 struct hns_roce_v2_ud_send_wqe { 886 __le32 byte_4; 887 __le32 msg_len; 888 __le32 immtdata; 889 __le32 byte_16; 890 __le32 byte_20; 891 __le32 byte_24; 892 __le32 qkey; 893 __le32 byte_32; 894 __le32 byte_36; 895 __le32 byte_40; 896 u8 dmac[ETH_ALEN]; 897 u8 sgid_index; 898 u8 smac_index; 899 u8 dgid[GID_LEN_V2]; 900 }; 901 902 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 903 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) 904 905 #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 906 907 #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 908 909 #define V2_UD_SEND_WQE_BYTE_4_SE_S 11 910 911 #define V2_UD_SEND_WQE_BYTE_16_PD_S 0 912 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) 913 914 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 915 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) 916 917 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 918 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) 919 920 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 921 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) 922 923 #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 924 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) 925 926 #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 927 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) 928 929 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 930 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) 931 932 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 933 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) 934 935 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 936 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) 937 938 #define V2_UD_SEND_WQE_BYTE_40_SL_S 20 939 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) 940 941 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30 942 943 #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 944 945 struct hns_roce_v2_rc_send_wqe { 946 __le32 byte_4; 947 __le32 msg_len; 948 union { 949 __le32 inv_key; 950 __le32 immtdata; 951 }; 952 __le32 byte_16; 953 __le32 byte_20; 954 __le32 rkey; 955 __le64 va; 956 }; 957 958 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 959 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) 960 961 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5 962 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5) 963 964 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13 965 #define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13) 966 967 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15 968 #define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15) 969 970 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 971 972 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 973 974 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 975 976 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10 977 978 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11 979 980 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 981 982 #define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 983 984 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 985 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) 986 987 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 988 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) 989 990 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 991 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) 992 993 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31 994 995 struct hns_roce_wqe_frmr_seg { 996 __le32 pbl_size; 997 __le32 byte_40; 998 }; 999 1000 #define FRMR_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_wqe_frmr_seg, h, l) 1001 1002 #define FRMR_PBL_SIZE FRMR_WQE_FIELD_LOC(31, 0) 1003 #define FRMR_BLOCK_SIZE FRMR_WQE_FIELD_LOC(35, 32) 1004 #define FRMR_PBL_BUF_PG_SZ FRMR_WQE_FIELD_LOC(39, 36) 1005 #define FRMR_BLK_MODE FRMR_WQE_FIELD_LOC(40, 40) 1006 #define FRMR_ZBVA FRMR_WQE_FIELD_LOC(41, 41) 1007 #define FRMR_BIND_EN FRMR_WQE_FIELD_LOC(42, 42) 1008 #define FRMR_ATOMIC FRMR_WQE_FIELD_LOC(43, 43) 1009 #define FRMR_RR FRMR_WQE_FIELD_LOC(44, 44) 1010 #define FRMR_RW FRMR_WQE_FIELD_LOC(45, 45) 1011 #define FRMR_LW FRMR_WQE_FIELD_LOC(46, 46) 1012 1013 struct hns_roce_v2_wqe_data_seg { 1014 __le32 len; 1015 __le32 lkey; 1016 __le64 addr; 1017 }; 1018 1019 struct hns_roce_query_version { 1020 __le16 rocee_vendor_id; 1021 __le16 rocee_hw_version; 1022 __le32 rsv[5]; 1023 }; 1024 1025 struct hns_roce_query_fw_info { 1026 __le32 fw_ver; 1027 __le32 rsv[5]; 1028 }; 1029 1030 struct hns_roce_func_clear { 1031 __le32 rst_funcid_en; 1032 __le32 func_done; 1033 __le32 rsv[4]; 1034 }; 1035 1036 #define FUNC_CLEAR_RST_FUN_DONE_S 0 1037 /* Each physical function manages up to 248 virtual functions, it takes up to 1038 * 100ms for each function to execute clear. If an abnormal reset occurs, it is 1039 * executed twice at most, so it takes up to 249 * 2 * 100ms. 1040 */ 1041 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100) 1042 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40 1043 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20 1044 1045 /* Fields of HNS_ROCE_OPC_EXT_CFG */ 1046 #define EXT_CFG_VF_ID CMQ_REQ_FIELD_LOC(31, 0) 1047 #define EXT_CFG_QP_PI_IDX CMQ_REQ_FIELD_LOC(45, 32) 1048 #define EXT_CFG_QP_PI_NUM CMQ_REQ_FIELD_LOC(63, 48) 1049 #define EXT_CFG_QP_NUM CMQ_REQ_FIELD_LOC(87, 64) 1050 #define EXT_CFG_QP_IDX CMQ_REQ_FIELD_LOC(119, 96) 1051 #define EXT_CFG_LLM_IDX CMQ_REQ_FIELD_LOC(139, 128) 1052 #define EXT_CFG_LLM_NUM CMQ_REQ_FIELD_LOC(156, 144) 1053 1054 #define CFG_LLM_A_BA_L CMQ_REQ_FIELD_LOC(31, 0) 1055 #define CFG_LLM_A_BA_H CMQ_REQ_FIELD_LOC(63, 32) 1056 #define CFG_LLM_A_DEPTH CMQ_REQ_FIELD_LOC(76, 64) 1057 #define CFG_LLM_A_PGSZ CMQ_REQ_FIELD_LOC(83, 80) 1058 #define CFG_LLM_A_INIT_EN CMQ_REQ_FIELD_LOC(84, 84) 1059 #define CFG_LLM_A_HEAD_BA_L CMQ_REQ_FIELD_LOC(127, 96) 1060 #define CFG_LLM_A_HEAD_BA_H CMQ_REQ_FIELD_LOC(147, 128) 1061 #define CFG_LLM_A_HEAD_NXTPTR CMQ_REQ_FIELD_LOC(159, 148) 1062 #define CFG_LLM_A_HEAD_PTR CMQ_REQ_FIELD_LOC(171, 160) 1063 #define CFG_LLM_B_TAIL_BA_L CMQ_REQ_FIELD_LOC(31, 0) 1064 #define CFG_LLM_B_TAIL_BA_H CMQ_REQ_FIELD_LOC(63, 32) 1065 #define CFG_LLM_B_TAIL_PTR CMQ_REQ_FIELD_LOC(75, 64) 1066 1067 /* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */ 1068 #define CFG_GLOBAL_PARAM_1US_CYCLES CMQ_REQ_FIELD_LOC(9, 0) 1069 #define CFG_GLOBAL_PARAM_UDP_PORT CMQ_REQ_FIELD_LOC(31, 16) 1070 1071 /* 1072 * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES 1073 * and HNS_ROCE_OPC_ALLOC_VF_RES 1074 */ 1075 #define FUNC_RES_A_VF_ID CMQ_REQ_FIELD_LOC(7, 0) 1076 #define FUNC_RES_A_QPC_BT_IDX CMQ_REQ_FIELD_LOC(42, 32) 1077 #define FUNC_RES_A_QPC_BT_NUM CMQ_REQ_FIELD_LOC(59, 48) 1078 #define FUNC_RES_A_SRQC_BT_IDX CMQ_REQ_FIELD_LOC(72, 64) 1079 #define FUNC_RES_A_SRQC_BT_NUM CMQ_REQ_FIELD_LOC(89, 80) 1080 #define FUNC_RES_A_CQC_BT_IDX CMQ_REQ_FIELD_LOC(104, 96) 1081 #define FUNC_RES_A_CQC_BT_NUM CMQ_REQ_FIELD_LOC(121, 112) 1082 #define FUNC_RES_A_MPT_BT_IDX CMQ_REQ_FIELD_LOC(136, 128) 1083 #define FUNC_RES_A_MPT_BT_NUM CMQ_REQ_FIELD_LOC(153, 144) 1084 #define FUNC_RES_A_EQC_BT_IDX CMQ_REQ_FIELD_LOC(168, 160) 1085 #define FUNC_RES_A_EQC_BT_NUM CMQ_REQ_FIELD_LOC(185, 176) 1086 #define FUNC_RES_B_SMAC_IDX CMQ_REQ_FIELD_LOC(39, 32) 1087 #define FUNC_RES_B_SMAC_NUM CMQ_REQ_FIELD_LOC(48, 40) 1088 #define FUNC_RES_B_SGID_IDX CMQ_REQ_FIELD_LOC(71, 64) 1089 #define FUNC_RES_B_SGID_NUM CMQ_REQ_FIELD_LOC(80, 72) 1090 #define FUNC_RES_B_QID_IDX CMQ_REQ_FIELD_LOC(105, 96) 1091 #define FUNC_RES_B_QID_NUM CMQ_REQ_FIELD_LOC(122, 112) 1092 #define FUNC_RES_V_QID_NUM CMQ_REQ_FIELD_LOC(115, 112) 1093 1094 #define FUNC_RES_B_SCCC_BT_IDX CMQ_REQ_FIELD_LOC(136, 128) 1095 #define FUNC_RES_B_SCCC_BT_NUM CMQ_REQ_FIELD_LOC(145, 137) 1096 #define FUNC_RES_B_GMV_BT_IDX CMQ_REQ_FIELD_LOC(167, 160) 1097 #define FUNC_RES_B_GMV_BT_NUM CMQ_REQ_FIELD_LOC(176, 168) 1098 #define FUNC_RES_V_GMV_BT_NUM CMQ_REQ_FIELD_LOC(184, 176) 1099 1100 /* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */ 1101 #define PF_TIMER_RES_QPC_ITEM_IDX CMQ_REQ_FIELD_LOC(43, 32) 1102 #define PF_TIMER_RES_QPC_ITEM_NUM CMQ_REQ_FIELD_LOC(60, 48) 1103 #define PF_TIMER_RES_CQC_ITEM_IDX CMQ_REQ_FIELD_LOC(74, 64) 1104 #define PF_TIMER_RES_CQC_ITEM_NUM CMQ_REQ_FIELD_LOC(91, 80) 1105 1106 struct hns_roce_vf_switch { 1107 __le32 rocee_sel; 1108 __le32 fun_id; 1109 __le32 cfg; 1110 __le32 resv1; 1111 __le32 resv2; 1112 __le32 resv3; 1113 }; 1114 1115 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3 1116 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3) 1117 1118 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1 1119 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2 1120 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3 1121 1122 struct hns_roce_post_mbox { 1123 __le32 in_param_l; 1124 __le32 in_param_h; 1125 __le32 out_param_l; 1126 __le32 out_param_h; 1127 __le32 cmd_tag; 1128 __le32 token_event_en; 1129 }; 1130 1131 struct hns_roce_mbox_status { 1132 __le32 mb_status_hw_run; 1133 __le32 rsv[5]; 1134 }; 1135 1136 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 1137 1138 #define MB_ST_HW_RUN_M BIT(31) 1139 #define MB_ST_COMPLETE_M GENMASK(7, 0) 1140 1141 #define MB_ST_COMPLETE_SUCC 1 1142 1143 /* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */ 1144 #define CFG_BT_ATTR_QPC_BA_PGSZ CMQ_REQ_FIELD_LOC(3, 0) 1145 #define CFG_BT_ATTR_QPC_BUF_PGSZ CMQ_REQ_FIELD_LOC(7, 4) 1146 #define CFG_BT_ATTR_QPC_HOPNUM CMQ_REQ_FIELD_LOC(9, 8) 1147 #define CFG_BT_ATTR_SRQC_BA_PGSZ CMQ_REQ_FIELD_LOC(35, 32) 1148 #define CFG_BT_ATTR_SRQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(39, 36) 1149 #define CFG_BT_ATTR_SRQC_HOPNUM CMQ_REQ_FIELD_LOC(41, 40) 1150 #define CFG_BT_ATTR_CQC_BA_PGSZ CMQ_REQ_FIELD_LOC(67, 64) 1151 #define CFG_BT_ATTR_CQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(71, 68) 1152 #define CFG_BT_ATTR_CQC_HOPNUM CMQ_REQ_FIELD_LOC(73, 72) 1153 #define CFG_BT_ATTR_MPT_BA_PGSZ CMQ_REQ_FIELD_LOC(99, 96) 1154 #define CFG_BT_ATTR_MPT_BUF_PGSZ CMQ_REQ_FIELD_LOC(103, 100) 1155 #define CFG_BT_ATTR_MPT_HOPNUM CMQ_REQ_FIELD_LOC(105, 104) 1156 #define CFG_BT_ATTR_SCCC_BA_PGSZ CMQ_REQ_FIELD_LOC(131, 128) 1157 #define CFG_BT_ATTR_SCCC_BUF_PGSZ CMQ_REQ_FIELD_LOC(135, 132) 1158 #define CFG_BT_ATTR_SCCC_HOPNUM CMQ_REQ_FIELD_LOC(137, 136) 1159 1160 /* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */ 1161 #define CFG_HEM_ENTRY_SIZE_TYPE CMQ_REQ_FIELD_LOC(31, 0) 1162 enum { 1163 HNS_ROCE_CFG_QPC_SIZE = BIT(0), 1164 HNS_ROCE_CFG_SCCC_SIZE = BIT(1), 1165 }; 1166 1167 #define CFG_HEM_ENTRY_SIZE_VALUE CMQ_REQ_FIELD_LOC(191, 160) 1168 1169 /* Fields of HNS_ROCE_OPC_CFG_GMV_BT */ 1170 #define CFG_GMV_BT_BA_L CMQ_REQ_FIELD_LOC(31, 0) 1171 #define CFG_GMV_BT_BA_H CMQ_REQ_FIELD_LOC(51, 32) 1172 #define CFG_GMV_BT_IDX CMQ_REQ_FIELD_LOC(95, 64) 1173 1174 struct hns_roce_cfg_sgid_tb { 1175 __le32 table_idx_rsv; 1176 __le32 vf_sgid_l; 1177 __le32 vf_sgid_ml; 1178 __le32 vf_sgid_mh; 1179 __le32 vf_sgid_h; 1180 __le32 vf_sgid_type_rsv; 1181 }; 1182 1183 #define CFG_SGID_TB_TABLE_IDX_S 0 1184 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0) 1185 1186 #define CFG_SGID_TB_VF_SGID_TYPE_S 0 1187 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0) 1188 1189 struct hns_roce_cfg_smac_tb { 1190 __le32 tb_idx_rsv; 1191 __le32 vf_smac_l; 1192 __le32 vf_smac_h_rsv; 1193 __le32 rsv[3]; 1194 }; 1195 #define CFG_SMAC_TB_IDX_S 0 1196 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0) 1197 1198 #define CFG_SMAC_TB_VF_SMAC_H_S 0 1199 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0) 1200 1201 struct hns_roce_cfg_gmv_tb_a { 1202 __le32 vf_sgid_l; 1203 __le32 vf_sgid_ml; 1204 __le32 vf_sgid_mh; 1205 __le32 vf_sgid_h; 1206 __le32 vf_sgid_type_vlan; 1207 __le32 resv; 1208 }; 1209 1210 #define CFG_GMV_TB_SGID_IDX_S 0 1211 #define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0) 1212 1213 #define CFG_GMV_TB_VF_SGID_TYPE_S 0 1214 #define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0) 1215 1216 #define CFG_GMV_TB_VF_VLAN_EN_S 2 1217 1218 #define CFG_GMV_TB_VF_VLAN_ID_S 16 1219 #define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16) 1220 1221 struct hns_roce_cfg_gmv_tb_b { 1222 __le32 vf_smac_l; 1223 __le32 vf_smac_h; 1224 __le32 table_idx_rsv; 1225 __le32 resv[3]; 1226 }; 1227 1228 #define CFG_GMV_TB_SMAC_H_S 0 1229 #define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0) 1230 1231 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5 1232 struct hns_roce_query_pf_caps_a { 1233 u8 number_ports; 1234 u8 local_ca_ack_delay; 1235 __le16 max_sq_sg; 1236 __le16 max_sq_inline; 1237 __le16 max_rq_sg; 1238 __le32 max_extend_sg; 1239 __le16 num_qpc_timer; 1240 __le16 num_cqc_timer; 1241 __le16 max_srq_sges; 1242 u8 num_aeq_vectors; 1243 u8 num_other_vectors; 1244 u8 max_sq_desc_sz; 1245 u8 max_rq_desc_sz; 1246 u8 max_srq_desc_sz; 1247 u8 cqe_sz; 1248 }; 1249 1250 struct hns_roce_query_pf_caps_b { 1251 u8 mtpt_entry_sz; 1252 u8 irrl_entry_sz; 1253 u8 trrl_entry_sz; 1254 u8 cqc_entry_sz; 1255 u8 srqc_entry_sz; 1256 u8 idx_entry_sz; 1257 u8 sccc_sz; 1258 u8 max_mtu; 1259 __le16 qpc_sz; 1260 __le16 qpc_timer_entry_sz; 1261 __le16 cqc_timer_entry_sz; 1262 u8 min_cqes; 1263 u8 min_wqes; 1264 __le32 page_size_cap; 1265 u8 pkey_table_len; 1266 u8 phy_num_uars; 1267 u8 ctx_hop_num; 1268 u8 pbl_hop_num; 1269 }; 1270 1271 struct hns_roce_query_pf_caps_c { 1272 __le32 cap_flags_num_pds; 1273 __le32 max_gid_num_cqs; 1274 __le32 cq_depth; 1275 __le32 num_mrws; 1276 __le32 ord_num_qps; 1277 __le16 sq_depth; 1278 __le16 rq_depth; 1279 }; 1280 1281 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0 1282 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0) 1283 1284 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20 1285 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20) 1286 1287 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0 1288 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0) 1289 1290 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20 1291 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20) 1292 1293 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0 1294 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0) 1295 1296 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0 1297 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0) 1298 1299 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0 1300 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0) 1301 1302 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20 1303 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20) 1304 1305 struct hns_roce_query_pf_caps_d { 1306 __le32 wq_hop_num_max_srqs; 1307 __le16 srq_depth; 1308 __le16 cap_flags_ex; 1309 __le32 num_ceqs_ceq_depth; 1310 __le32 arm_st_aeq_depth; 1311 __le32 num_uars_rsv_pds; 1312 __le32 rsv_uars_rsv_qps; 1313 }; 1314 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0 1315 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0) 1316 1317 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20 1318 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20) 1319 1320 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22 1321 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22) 1322 1323 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24 1324 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24) 1325 1326 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_S 26 1327 #define V2_QUERY_PF_CAPS_D_CONG_TYPE_M GENMASK(29, 26) 1328 1329 struct hns_roce_congestion_algorithm { 1330 u8 alg_sel; 1331 u8 alg_sub_sel; 1332 u8 dip_vld; 1333 u8 wnd_mode_sel; 1334 }; 1335 1336 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0 1337 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0) 1338 1339 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22 1340 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22) 1341 1342 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0 1343 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0) 1344 1345 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22 1346 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22) 1347 1348 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24 1349 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24) 1350 1351 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0 1352 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0) 1353 1354 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20 1355 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20) 1356 1357 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0 1358 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0) 1359 1360 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20 1361 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20) 1362 1363 struct hns_roce_query_pf_caps_e { 1364 __le32 chunk_size_shift_rsv_mrws; 1365 __le32 rsv_cqs; 1366 __le32 rsv_srqs; 1367 __le32 rsv_lkey; 1368 __le16 ceq_max_cnt; 1369 __le16 ceq_period; 1370 __le16 aeq_max_cnt; 1371 __le16 aeq_period; 1372 }; 1373 1374 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0 1375 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0) 1376 1377 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20 1378 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20) 1379 1380 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0 1381 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0) 1382 1383 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0 1384 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0) 1385 1386 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0 1387 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0) 1388 1389 struct hns_roce_cmq_req { 1390 __le32 data[6]; 1391 }; 1392 1393 #define CMQ_REQ_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cmq_req, h, l) 1394 1395 struct hns_roce_cmq_desc { 1396 __le16 opcode; 1397 __le16 flag; 1398 __le16 retval; 1399 __le16 rsv; 1400 union { 1401 __le32 data[6]; 1402 struct { 1403 __le32 own_func_num; 1404 __le32 own_mac_id; 1405 __le32 rsv[4]; 1406 } func_info; 1407 }; 1408 }; 1409 1410 struct hns_roce_v2_cmq_ring { 1411 dma_addr_t desc_dma_addr; 1412 struct hns_roce_cmq_desc *desc; 1413 u32 head; 1414 u16 buf_size; 1415 u16 desc_num; 1416 u8 flag; 1417 spinlock_t lock; /* command queue lock */ 1418 }; 1419 1420 struct hns_roce_v2_cmq { 1421 struct hns_roce_v2_cmq_ring csq; 1422 u16 tx_timeout; 1423 }; 1424 1425 struct hns_roce_link_table { 1426 struct hns_roce_buf_list table; 1427 struct hns_roce_buf *buf; 1428 }; 1429 1430 #define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) | ((addr) >> 12)) 1431 #define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2) 1432 1433 struct hns_roce_v2_free_mr { 1434 struct ib_qp *rsv_qp[HNS_ROCE_FREE_MR_USED_QP_NUM]; 1435 struct ib_cq *rsv_cq; 1436 struct ib_pd *rsv_pd; 1437 struct mutex mutex; 1438 }; 1439 1440 struct hns_roce_v2_priv { 1441 struct hnae3_handle *handle; 1442 struct hns_roce_v2_cmq cmq; 1443 struct hns_roce_link_table ext_llm; 1444 struct hns_roce_v2_free_mr free_mr; 1445 }; 1446 1447 struct hns_roce_dip { 1448 u8 dgid[GID_LEN_V2]; 1449 u32 dip_idx; 1450 struct list_head node; /* all dips are on a list */ 1451 }; 1452 1453 /* only for RNR timeout issue of HIP08 */ 1454 #define HNS_ROCE_CLOCK_ADJUST 1000 1455 #define HNS_ROCE_MAX_CQ_PERIOD 65 1456 #define HNS_ROCE_MAX_EQ_PERIOD 65 1457 #define HNS_ROCE_RNR_TIMER_10NS 1 1458 #define HNS_ROCE_1US_CFG 999 1459 #define HNS_ROCE_1NS_CFG 0 1460 1461 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 1462 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 1463 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 1464 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 1465 1466 #define HNS_ROCE_V2_EQ_STATE_INVALID 0 1467 #define HNS_ROCE_V2_EQ_STATE_VALID 1 1468 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 1469 #define HNS_ROCE_V2_EQ_STATE_FAILURE 3 1470 1471 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 1472 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 1473 1474 #define HNS_ROCE_V2_EQ_COALESCE_0 0 1475 #define HNS_ROCE_V2_EQ_COALESCE_1 1 1476 1477 #define HNS_ROCE_V2_EQ_FIRED 0 1478 #define HNS_ROCE_V2_EQ_ARMED 1 1479 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 1480 1481 #define HNS_ROCE_EQ_INIT_EQE_CNT 0 1482 #define HNS_ROCE_EQ_INIT_PROD_IDX 0 1483 #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 1484 #define HNS_ROCE_EQ_INIT_MSI_IDX 0 1485 #define HNS_ROCE_EQ_INIT_CONS_IDX 0 1486 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 1487 1488 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 1489 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 1490 1491 #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 1492 #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 1493 1494 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 1495 #define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S 1 1496 1497 #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 1498 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 1499 #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 1500 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 1501 1502 #define EQ_ENABLE 1 1503 #define EQ_DISABLE 0 1504 1505 #define EQ_REG_OFFSET 0x4 1506 1507 #define HNS_ROCE_INT_NAME_LEN 32 1508 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0) 1509 1510 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 1511 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) 1512 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) 1513 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) 1514 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) 1515 1516 struct hns_roce_eq_context { 1517 __le32 data[16]; 1518 }; 1519 1520 #define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l) 1521 1522 #define EQC_EQ_ST EQC_FIELD_LOC(1, 0) 1523 #define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2) 1524 #define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4) 1525 #define EQC_COALESCE EQC_FIELD_LOC(5, 5) 1526 #define EQC_ARM_ST EQC_FIELD_LOC(7, 6) 1527 #define EQC_EQN EQC_FIELD_LOC(15, 8) 1528 #define EQC_EQE_CNT EQC_FIELD_LOC(31, 16) 1529 #define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32) 1530 #define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36) 1531 #define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40) 1532 #define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64) 1533 #define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80) 1534 #define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96) 1535 #define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128) 1536 #define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160) 1537 #define EQC_SHIFT EQC_FIELD_LOC(199, 192) 1538 #define EQC_MSI_INDX EQC_FIELD_LOC(207, 200) 1539 #define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208) 1540 #define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224) 1541 #define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256) 1542 #define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264) 1543 #define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288) 1544 #define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320) 1545 #define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340) 1546 1547 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 1548 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) 1549 1550 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 1551 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) 1552 1553 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 1554 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) 1555 1556 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 1557 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) 1558 1559 #define MAX_SERVICE_LEVEL 0x7 1560 1561 struct hns_roce_wqe_atomic_seg { 1562 __le64 fetchadd_swap_data; 1563 __le64 cmp_data; 1564 }; 1565 1566 struct hns_roce_sccc_clr { 1567 __le32 qpn; 1568 __le32 rsv[5]; 1569 }; 1570 1571 struct hns_roce_sccc_clr_done { 1572 __le32 clr_done; 1573 __le32 rsv[5]; 1574 }; 1575 1576 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn, 1577 int *buffer); 1578 1579 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2], 1580 void __iomem *dest) 1581 { 1582 struct hns_roce_v2_priv *priv = hr_dev->priv; 1583 struct hnae3_handle *handle = priv->handle; 1584 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1585 1586 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 1587 hns_roce_write64_k(val, dest); 1588 } 1589 1590 #endif 1591