1 /*
2  * Copyright (c) 2016-2017 Hisilicon Limited.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _HNS_ROCE_HW_V2_H
34 #define _HNS_ROCE_HW_V2_H
35 
36 #include <linux/bitops.h>
37 
38 #define HNS_ROCE_VF_QPC_BT_NUM			256
39 #define HNS_ROCE_VF_SCCC_BT_NUM			64
40 #define HNS_ROCE_VF_SRQC_BT_NUM			64
41 #define HNS_ROCE_VF_CQC_BT_NUM			64
42 #define HNS_ROCE_VF_MPT_BT_NUM			64
43 #define HNS_ROCE_VF_EQC_NUM			64
44 #define HNS_ROCE_VF_SMAC_NUM			32
45 #define HNS_ROCE_VF_SGID_NUM			32
46 #define HNS_ROCE_VF_SL_NUM			8
47 #define HNS_ROCE_VF_GMV_BT_NUM			256
48 
49 #define HNS_ROCE_V2_MAX_QP_NUM			0x100000
50 #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM		0x200
51 #define HNS_ROCE_V2_MAX_WQE_NUM			0x8000
52 #define	HNS_ROCE_V2_MAX_SRQ			0x100000
53 #define HNS_ROCE_V2_MAX_SRQ_WR			0x8000
54 #define HNS_ROCE_V2_MAX_SRQ_SGE			64
55 #define HNS_ROCE_V2_MAX_CQ_NUM			0x100000
56 #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM		0x100
57 #define HNS_ROCE_V2_MAX_SRQ_NUM			0x100000
58 #define HNS_ROCE_V2_MAX_CQE_NUM			0x400000
59 #define HNS_ROCE_V2_MAX_SRQWQE_NUM		0x8000
60 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM		64
61 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM		64
62 #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM		0x200000
63 #define HNS_ROCE_V2_MAX_SQ_INLINE		0x20
64 #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ		32
65 #define HNS_ROCE_V2_UAR_NUM			256
66 #define HNS_ROCE_V2_PHY_UAR_NUM			1
67 #define HNS_ROCE_V2_MAX_IRQ_NUM			65
68 #define HNS_ROCE_V2_COMP_VEC_NUM		63
69 #define HNS_ROCE_V2_AEQE_VEC_NUM		1
70 #define HNS_ROCE_V2_ABNORMAL_VEC_NUM		1
71 #define HNS_ROCE_V2_MAX_MTPT_NUM		0x100000
72 #define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000
73 #define HNS_ROCE_V2_MAX_CQE_SEGS		0x1000000
74 #define HNS_ROCE_V2_MAX_SRQWQE_SEGS		0x1000000
75 #define HNS_ROCE_V2_MAX_IDX_SEGS		0x1000000
76 #define HNS_ROCE_V2_MAX_PD_NUM			0x1000000
77 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA		128
78 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA		128
79 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ		64
80 #define HNS_ROCE_V2_MAX_RQ_DESC_SZ		16
81 #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ		64
82 #define HNS_ROCE_V2_IRRL_ENTRY_SZ		64
83 #define HNS_ROCE_V2_TRRL_ENTRY_SZ		48
84 #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ	100
85 #define HNS_ROCE_V2_CQC_ENTRY_SZ		64
86 #define HNS_ROCE_V2_SRQC_ENTRY_SZ		64
87 #define HNS_ROCE_V2_MTPT_ENTRY_SZ		64
88 #define HNS_ROCE_V2_MTT_ENTRY_SZ		64
89 #define HNS_ROCE_V2_IDX_ENTRY_SZ		4
90 
91 #define HNS_ROCE_V2_SCCC_SZ			32
92 #define HNS_ROCE_V3_SCCC_SZ			64
93 #define HNS_ROCE_V3_GMV_ENTRY_SZ		32
94 
95 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ		PAGE_SIZE
96 #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ		PAGE_SIZE
97 #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED		0xFFFFF000
98 #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM		2
99 #define HNS_ROCE_INVALID_LKEY			0x100
100 #define HNS_ROCE_CMQ_TX_TIMEOUT			30000
101 #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE	2
102 #define HNS_ROCE_V2_RSV_QPS			8
103 
104 #define HNS_ROCE_V2_HW_RST_TIMEOUT		1000
105 #define HNS_ROCE_V2_HW_RST_UNINT_DELAY		100
106 
107 #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT	20
108 
109 #define HNS_ROCE_CONTEXT_HOP_NUM		1
110 #define HNS_ROCE_SCCC_HOP_NUM			1
111 #define HNS_ROCE_MTT_HOP_NUM			1
112 #define HNS_ROCE_CQE_HOP_NUM			1
113 #define HNS_ROCE_SRQWQE_HOP_NUM			1
114 #define HNS_ROCE_PBL_HOP_NUM			2
115 #define HNS_ROCE_EQE_HOP_NUM			2
116 #define HNS_ROCE_IDX_HOP_NUM			1
117 #define HNS_ROCE_SQWQE_HOP_NUM			2
118 #define HNS_ROCE_EXT_SGE_HOP_NUM		1
119 #define HNS_ROCE_RQWQE_HOP_NUM			2
120 
121 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K	6
122 #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K		2
123 #define HNS_ROCE_V2_GID_INDEX_NUM		256
124 
125 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)
126 
127 #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT	0
128 #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT	1
129 #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT		2
130 #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT	3
131 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT		4
132 #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT	5
133 
134 #define HNS_ROCE_CMD_FLAG_IN		BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
135 #define HNS_ROCE_CMD_FLAG_OUT		BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
136 #define HNS_ROCE_CMD_FLAG_NEXT		BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
137 #define HNS_ROCE_CMD_FLAG_WR		BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
138 #define HNS_ROCE_CMD_FLAG_NO_INTR	BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
139 #define HNS_ROCE_CMD_FLAG_ERR_INTR	BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
140 
141 #define HNS_ROCE_CMQ_DESC_NUM_S		3
142 
143 #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT		5
144 
145 #define check_whether_last_step(hop_num, step_idx) \
146 	((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
147 	(step_idx == 1 && hop_num == 1) || \
148 	(step_idx == 2 && hop_num == 2))
149 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT	0
150 #define HNS_ICL_SWITCH_CMD_ROCEE_SEL	BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
151 
152 #define CMD_CSQ_DESC_NUM		1024
153 #define CMD_CRQ_DESC_NUM		1024
154 
155 enum {
156 	NO_ARMED = 0x0,
157 	REG_NXT_CEQE = 0x2,
158 	REG_NXT_SE_CEQE = 0x3
159 };
160 
161 #define V2_CQ_DB_REQ_NOT_SOL			0
162 #define V2_CQ_DB_REQ_NOT			1
163 
164 #define V2_CQ_STATE_VALID			1
165 #define V2_QKEY_VAL				0x80010000
166 
167 #define	GID_LEN_V2				16
168 
169 #define HNS_ROCE_V2_CQE_QPN_MASK		0xfffff
170 
171 enum {
172 	HNS_ROCE_V2_WQE_OP_SEND				= 0x0,
173 	HNS_ROCE_V2_WQE_OP_SEND_WITH_INV		= 0x1,
174 	HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM		= 0x2,
175 	HNS_ROCE_V2_WQE_OP_RDMA_WRITE			= 0x3,
176 	HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM		= 0x4,
177 	HNS_ROCE_V2_WQE_OP_RDMA_READ			= 0x5,
178 	HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP		= 0x6,
179 	HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD		= 0x7,
180 	HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP	= 0x8,
181 	HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD	= 0x9,
182 	HNS_ROCE_V2_WQE_OP_FAST_REG_PMR			= 0xa,
183 	HNS_ROCE_V2_WQE_OP_LOCAL_INV			= 0xb,
184 	HNS_ROCE_V2_WQE_OP_BIND_MW			= 0xc,
185 	HNS_ROCE_V2_WQE_OP_MASK				= 0x1f,
186 };
187 
188 enum {
189 	/* rq operations */
190 	HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
191 	HNS_ROCE_V2_OPCODE_SEND = 0x1,
192 	HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
193 	HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
194 };
195 
196 enum {
197 	HNS_ROCE_V2_SQ_DB	= 0x0,
198 	HNS_ROCE_V2_RQ_DB	= 0x1,
199 	HNS_ROCE_V2_SRQ_DB	= 0x2,
200 	HNS_ROCE_V2_CQ_DB_PTR	= 0x3,
201 	HNS_ROCE_V2_CQ_DB_NTR	= 0x4,
202 };
203 
204 enum {
205 	HNS_ROCE_CQE_V2_SUCCESS				= 0x00,
206 	HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR		= 0x01,
207 	HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR			= 0x02,
208 	HNS_ROCE_CQE_V2_LOCAL_PROT_ERR			= 0x04,
209 	HNS_ROCE_CQE_V2_WR_FLUSH_ERR			= 0x05,
210 	HNS_ROCE_CQE_V2_MW_BIND_ERR			= 0x06,
211 	HNS_ROCE_CQE_V2_BAD_RESP_ERR			= 0x10,
212 	HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR		= 0x11,
213 	HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR		= 0x12,
214 	HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR		= 0x13,
215 	HNS_ROCE_CQE_V2_REMOTE_OP_ERR			= 0x14,
216 	HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR		= 0x15,
217 	HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR		= 0x16,
218 	HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR		= 0x22,
219 	HNS_ROCE_CQE_V2_GENERAL_ERR			= 0x23,
220 
221 	HNS_ROCE_V2_CQE_STATUS_MASK			= 0xff,
222 };
223 
224 /* CMQ command */
225 enum hns_roce_opcode_type {
226 	HNS_QUERY_FW_VER				= 0x0001,
227 	HNS_ROCE_OPC_QUERY_HW_VER			= 0x8000,
228 	HNS_ROCE_OPC_CFG_GLOBAL_PARAM			= 0x8001,
229 	HNS_ROCE_OPC_ALLOC_PF_RES			= 0x8004,
230 	HNS_ROCE_OPC_QUERY_PF_RES			= 0x8400,
231 	HNS_ROCE_OPC_ALLOC_VF_RES			= 0x8401,
232 	HNS_ROCE_OPC_CFG_EXT_LLM			= 0x8403,
233 	HNS_ROCE_OPC_CFG_TMOUT_LLM			= 0x8404,
234 	HNS_ROCE_OPC_QUERY_PF_TIMER_RES			= 0x8406,
235 	HNS_ROCE_OPC_QUERY_PF_CAPS_NUM                  = 0x8408,
236 	HNS_ROCE_OPC_CFG_ENTRY_SIZE			= 0x8409,
237 	HNS_ROCE_OPC_CFG_SGID_TB			= 0x8500,
238 	HNS_ROCE_OPC_CFG_SMAC_TB			= 0x8501,
239 	HNS_ROCE_OPC_POST_MB				= 0x8504,
240 	HNS_ROCE_OPC_QUERY_MB_ST			= 0x8505,
241 	HNS_ROCE_OPC_CFG_BT_ATTR			= 0x8506,
242 	HNS_ROCE_OPC_FUNC_CLEAR				= 0x8508,
243 	HNS_ROCE_OPC_CLR_SCCC				= 0x8509,
244 	HNS_ROCE_OPC_QUERY_SCCC				= 0x850a,
245 	HNS_ROCE_OPC_RESET_SCCC				= 0x850b,
246 	HNS_ROCE_OPC_CFG_GMV_TBL			= 0x850f,
247 	HNS_ROCE_OPC_CFG_GMV_BT				= 0x8510,
248 	HNS_SWITCH_PARAMETER_CFG			= 0x1033,
249 };
250 
251 enum {
252 	TYPE_CRQ,
253 	TYPE_CSQ,
254 };
255 
256 enum hns_roce_cmd_return_status {
257 	CMD_EXEC_SUCCESS	= 0,
258 	CMD_NO_AUTH		= 1,
259 	CMD_NOT_EXEC		= 2,
260 	CMD_QUEUE_FULL		= 3,
261 };
262 
263 enum hns_roce_sgid_type {
264 	GID_TYPE_FLAG_ROCE_V1 = 0,
265 	GID_TYPE_FLAG_ROCE_V2_IPV4,
266 	GID_TYPE_FLAG_ROCE_V2_IPV6,
267 };
268 
269 struct hns_roce_v2_cq_context {
270 	__le32 byte_4_pg_ceqn;
271 	__le32 byte_8_cqn;
272 	__le32 cqe_cur_blk_addr;
273 	__le32 byte_16_hop_addr;
274 	__le32 cqe_nxt_blk_addr;
275 	__le32 byte_24_pgsz_addr;
276 	__le32 byte_28_cq_pi;
277 	__le32 byte_32_cq_ci;
278 	__le32 cqe_ba;
279 	__le32 byte_40_cqe_ba;
280 	__le32 byte_44_db_record;
281 	__le32 db_record_addr;
282 	__le32 byte_52_cqe_cnt;
283 	__le32 byte_56_cqe_period_maxcnt;
284 	__le32 cqe_report_timer;
285 	__le32 byte_64_se_cqe_idx;
286 };
287 
288 #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
289 #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL	0x0
290 
291 #define	V2_CQC_BYTE_4_CQ_ST_S 0
292 #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
293 
294 #define	V2_CQC_BYTE_4_POLL_S 2
295 
296 #define	V2_CQC_BYTE_4_SE_S 3
297 
298 #define	V2_CQC_BYTE_4_OVER_IGNORE_S 4
299 
300 #define	V2_CQC_BYTE_4_COALESCE_S 5
301 
302 #define	V2_CQC_BYTE_4_ARM_ST_S 6
303 #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
304 
305 #define	V2_CQC_BYTE_4_SHIFT_S 8
306 #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
307 
308 #define	V2_CQC_BYTE_4_CMD_SN_S 13
309 #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
310 
311 #define	V2_CQC_BYTE_4_CEQN_S 15
312 #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
313 
314 #define	V2_CQC_BYTE_4_PAGE_OFFSET_S 24
315 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
316 
317 #define	V2_CQC_BYTE_8_CQN_S 0
318 #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
319 
320 #define V2_CQC_BYTE_8_CQE_SIZE_S 27
321 #define V2_CQC_BYTE_8_CQE_SIZE_M GENMASK(28, 27)
322 
323 #define	V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
324 #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
325 
326 #define	V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
327 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
328 
329 #define	V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
330 #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
331 
332 #define	V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
333 #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
334 
335 #define	V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
336 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
337 
338 #define	V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
339 #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
340 
341 #define	V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
342 #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
343 
344 #define	V2_CQC_BYTE_40_CQE_BA_S 0
345 #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
346 
347 #define	V2_CQC_BYTE_44_DB_RECORD_EN_S 0
348 
349 #define	V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
350 #define	V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
351 
352 #define	V2_CQC_BYTE_52_CQE_CNT_S 0
353 #define	V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
354 
355 #define	V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
356 #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
357 
358 #define	V2_CQC_BYTE_56_CQ_PERIOD_S 16
359 #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
360 
361 #define	V2_CQC_BYTE_64_SE_CQE_IDX_S 0
362 #define	V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
363 
364 #define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)
365 
366 #define CQC_STASH CQC_FIELD_LOC(63, 63)
367 
368 struct hns_roce_srq_context {
369 	__le32	byte_4_srqn_srqst;
370 	__le32	byte_8_limit_wl;
371 	__le32	byte_12_xrcd;
372 	__le32	byte_16_pi_ci;
373 	__le32	wqe_bt_ba;
374 	__le32	byte_24_wqe_bt_ba;
375 	__le32	byte_28_rqws_pd;
376 	__le32	idx_bt_ba;
377 	__le32	rsv_idx_bt_ba;
378 	__le32	idx_cur_blk_addr;
379 	__le32	byte_44_idxbufpgsz_addr;
380 	__le32	idx_nxt_blk_addr;
381 	__le32	rsv_idxnxtblkaddr;
382 	__le32	byte_56_xrc_cqn;
383 	__le32	db_record_addr_record_en;
384 	__le32	db_record_addr;
385 };
386 
387 #define SRQC_BYTE_4_SRQ_ST_S 0
388 #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
389 
390 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
391 #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
392 
393 #define SRQC_BYTE_4_SRQ_SHIFT_S 4
394 #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
395 
396 #define SRQC_BYTE_4_SRQN_S 8
397 #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
398 
399 #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
400 #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
401 
402 #define SRQC_BYTE_12_SRQ_XRCD_S 0
403 #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
404 
405 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
406 #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
407 
408 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
409 #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
410 
411 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
412 #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
413 
414 #define SRQC_BYTE_28_PD_S 0
415 #define SRQC_BYTE_28_PD_M GENMASK(23, 0)
416 
417 #define SRQC_BYTE_28_RQWS_S 24
418 #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
419 
420 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
421 #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
422 
423 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
424 #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
425 
426 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
427 #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
428 
429 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
430 #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
431 
432 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
433 #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
434 
435 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
436 #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
437 
438 #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
439 #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
440 
441 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
442 #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
443 
444 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
445 #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
446 
447 #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
448 
449 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
450 #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
451 
452 enum {
453 	V2_MPT_ST_VALID = 0x1,
454 	V2_MPT_ST_FREE	= 0x2,
455 };
456 
457 enum hns_roce_v2_qp_state {
458 	HNS_ROCE_QP_ST_RST,
459 	HNS_ROCE_QP_ST_INIT,
460 	HNS_ROCE_QP_ST_RTR,
461 	HNS_ROCE_QP_ST_RTS,
462 	HNS_ROCE_QP_ST_SQD,
463 	HNS_ROCE_QP_ST_SQER,
464 	HNS_ROCE_QP_ST_ERR,
465 	HNS_ROCE_QP_ST_SQ_DRAINING,
466 	HNS_ROCE_QP_NUM_ST
467 };
468 
469 struct hns_roce_v2_qp_context_ex {
470 	__le32 data[64];
471 };
472 struct hns_roce_v2_qp_context {
473 	__le32 byte_4_sqpn_tst;
474 	__le32 wqe_sge_ba;
475 	__le32 byte_12_sq_hop;
476 	__le32 byte_16_buf_ba_pg_sz;
477 	__le32 byte_20_smac_sgid_idx;
478 	__le32 byte_24_mtu_tc;
479 	__le32 byte_28_at_fl;
480 	u8 dgid[GID_LEN_V2];
481 	__le32 dmac;
482 	__le32 byte_52_udpspn_dmac;
483 	__le32 byte_56_dqpn_err;
484 	__le32 byte_60_qpst_tempid;
485 	__le32 qkey_xrcd;
486 	__le32 byte_68_rq_db;
487 	__le32 rq_db_record_addr;
488 	__le32 byte_76_srqn_op_en;
489 	__le32 byte_80_rnr_rx_cqn;
490 	__le32 byte_84_rq_ci_pi;
491 	__le32 rq_cur_blk_addr;
492 	__le32 byte_92_srq_info;
493 	__le32 byte_96_rx_reqmsn;
494 	__le32 rq_nxt_blk_addr;
495 	__le32 byte_104_rq_sge;
496 	__le32 byte_108_rx_reqepsn;
497 	__le32 rq_rnr_timer;
498 	__le32 rx_msg_len;
499 	__le32 rx_rkey_pkt_info;
500 	__le64 rx_va;
501 	__le32 byte_132_trrl;
502 	__le32 trrl_ba;
503 	__le32 byte_140_raq;
504 	__le32 byte_144_raq;
505 	__le32 byte_148_raq;
506 	__le32 byte_152_raq;
507 	__le32 byte_156_raq;
508 	__le32 byte_160_sq_ci_pi;
509 	__le32 sq_cur_blk_addr;
510 	__le32 byte_168_irrl_idx;
511 	__le32 byte_172_sq_psn;
512 	__le32 byte_176_msg_pktn;
513 	__le32 sq_cur_sge_blk_addr;
514 	__le32 byte_184_irrl_idx;
515 	__le32 cur_sge_offset;
516 	__le32 byte_192_ext_sge;
517 	__le32 byte_196_sq_psn;
518 	__le32 byte_200_sq_max;
519 	__le32 irrl_ba;
520 	__le32 byte_208_irrl;
521 	__le32 byte_212_lsn;
522 	__le32 sq_timer;
523 	__le32 byte_220_retry_psn_msn;
524 	__le32 byte_224_retry_msg;
525 	__le32 rx_sq_cur_blk_addr;
526 	__le32 byte_232_irrl_sge;
527 	__le32 irrl_cur_sge_offset;
528 	__le32 byte_240_irrl_tail;
529 	__le32 byte_244_rnr_rxack;
530 	__le32 byte_248_ack_psn;
531 	__le32 byte_252_err_txcqn;
532 	__le32 byte_256_sqflush_rqcqe;
533 
534 	struct hns_roce_v2_qp_context_ex ext;
535 };
536 
537 #define	V2_QPC_BYTE_4_TST_S 0
538 #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
539 
540 #define	V2_QPC_BYTE_4_SGE_SHIFT_S 3
541 #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
542 
543 #define	V2_QPC_BYTE_4_SQPN_S 8
544 #define V2_QPC_BYTE_4_SQPN_M  GENMASK(31, 8)
545 
546 #define	V2_QPC_BYTE_12_WQE_SGE_BA_S 0
547 #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
548 
549 #define	V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
550 #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
551 
552 #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
553 
554 #define	V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
555 #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
556 
557 #define	V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
558 #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
559 
560 #define	V2_QPC_BYTE_16_PD_S 8
561 #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
562 
563 #define	V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
564 #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
565 
566 #define	V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
567 #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
568 
569 #define	V2_QPC_BYTE_20_RQWS_S 4
570 #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
571 
572 #define	V2_QPC_BYTE_20_SQ_SHIFT_S 8
573 #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
574 
575 #define	V2_QPC_BYTE_20_RQ_SHIFT_S 12
576 #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
577 
578 #define	V2_QPC_BYTE_20_SGID_IDX_S 16
579 #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
580 
581 #define	V2_QPC_BYTE_20_SMAC_IDX_S 24
582 #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
583 
584 #define	V2_QPC_BYTE_24_HOP_LIMIT_S 0
585 #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
586 
587 #define	V2_QPC_BYTE_24_TC_S 8
588 #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
589 
590 #define	V2_QPC_BYTE_24_VLAN_ID_S 16
591 #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
592 
593 #define	V2_QPC_BYTE_24_MTU_S 28
594 #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
595 
596 #define	V2_QPC_BYTE_28_FL_S 0
597 #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
598 
599 #define	V2_QPC_BYTE_28_SL_S 20
600 #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
601 
602 #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
603 
604 #define V2_QPC_BYTE_28_CE_FLAG_S 25
605 
606 #define V2_QPC_BYTE_28_LBI_S 26
607 
608 #define	V2_QPC_BYTE_28_AT_S 27
609 #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
610 
611 #define	V2_QPC_BYTE_52_DMAC_S 0
612 #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
613 
614 #define V2_QPC_BYTE_52_UDPSPN_S 16
615 #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
616 
617 #define	V2_QPC_BYTE_56_DQPN_S 0
618 #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
619 
620 #define	V2_QPC_BYTE_56_SQ_TX_ERR_S 24
621 #define	V2_QPC_BYTE_56_SQ_RX_ERR_S 25
622 #define	V2_QPC_BYTE_56_RQ_TX_ERR_S 26
623 #define	V2_QPC_BYTE_56_RQ_RX_ERR_S 27
624 
625 #define	V2_QPC_BYTE_56_LP_PKTN_INI_S 28
626 #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
627 
628 #define	V2_QPC_BYTE_60_TEMPID_S 0
629 #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
630 
631 #define V2_QPC_BYTE_60_SCC_TOKEN_S 8
632 #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
633 
634 #define	V2_QPC_BYTE_60_SQ_DB_DOING_S 27
635 
636 #define	V2_QPC_BYTE_60_RQ_DB_DOING_S 28
637 
638 #define	V2_QPC_BYTE_60_QP_ST_S 29
639 #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
640 
641 #define	V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
642 
643 #define	V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
644 #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
645 
646 #define	V2_QPC_BYTE_76_SRQN_S 0
647 #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
648 
649 #define	V2_QPC_BYTE_76_SRQ_EN_S 24
650 
651 #define	V2_QPC_BYTE_76_RRE_S 25
652 
653 #define	V2_QPC_BYTE_76_RWE_S 26
654 
655 #define	V2_QPC_BYTE_76_ATE_S 27
656 
657 #define	V2_QPC_BYTE_76_RQIE_S 28
658 #define	V2_QPC_BYTE_76_EXT_ATE_S 29
659 #define	V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
660 #define	V2_QPC_BYTE_80_RX_CQN_S 0
661 #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
662 
663 #define	V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
664 #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
665 
666 #define	V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
667 #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
668 
669 #define	V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
670 #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
671 
672 #define	V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
673 #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
674 
675 #define	V2_QPC_BYTE_92_SRQ_INFO_S 20
676 #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
677 
678 #define	V2_QPC_BYTE_96_RX_REQ_MSN_S 0
679 #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
680 
681 #define	V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
682 #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
683 
684 #define	V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
685 #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
686 
687 #define V2_QPC_BYTE_108_INV_CREDIT_S 0
688 
689 #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
690 
691 #define	V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
692 #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
693 
694 #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
695 
696 #define	V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
697 #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
698 
699 #define	V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
700 #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
701 
702 #define	V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
703 #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
704 
705 #define	V2_QPC_BYTE_132_TRRL_BA_S 16
706 #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
707 
708 #define	V2_QPC_BYTE_140_TRRL_BA_S 0
709 #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
710 
711 #define	V2_QPC_BYTE_140_RR_MAX_S 12
712 #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
713 
714 #define	V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
715 
716 #define	V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
717 #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
718 
719 #define	V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
720 #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
721 
722 #define	V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
723 #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
724 
725 #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
726 #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
727 
728 #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
729 
730 #define	V2_QPC_BYTE_148_RQ_MSN_S 0
731 #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
732 
733 #define	V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
734 #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
735 
736 #define	V2_QPC_BYTE_152_RAQ_PSN_S 0
737 #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
738 
739 #define	V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
740 #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
741 
742 #define	V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
743 #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
744 
745 #define	V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
746 #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
747 
748 #define	V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
749 #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
750 
751 #define	V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
752 #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
753 
754 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
755 
756 #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
757 
758 #define	V2_QPC_BYTE_168_LP_SGEN_INI_S 22
759 #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
760 
761 #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
762 #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
763 #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
764 #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
765 #define	V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
766 #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
767 
768 #define	V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
769 #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
770 
771 #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
772 
773 #define V2_QPC_BYTE_172_FRE_S 7
774 
775 #define	V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
776 #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
777 
778 #define	V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
779 #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
780 
781 #define	V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
782 #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
783 
784 #define	V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
785 #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
786 
787 #define	V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
788 #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
789 
790 #define	V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
791 #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
792 
793 #define	V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
794 #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
795 
796 #define	V2_QPC_BYTE_196_IRRL_HEAD_S 0
797 #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
798 
799 #define	V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
800 #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
801 
802 #define	V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
803 #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
804 
805 #define	V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
806 #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
807 
808 #define	V2_QPC_BYTE_208_IRRL_BA_S 0
809 #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
810 
811 #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
812 
813 #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
814 
815 #define V2_QPC_BYTE_208_RMT_E2E_S 28
816 
817 #define	V2_QPC_BYTE_208_SR_MAX_S 29
818 #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
819 
820 #define	V2_QPC_BYTE_212_LSN_S 0
821 #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
822 
823 #define	V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
824 #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
825 
826 #define	V2_QPC_BYTE_212_CHECK_FLG_S 27
827 #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
828 
829 #define	V2_QPC_BYTE_212_RETRY_CNT_S 29
830 #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
831 
832 #define	V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
833 #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
834 
835 #define	V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
836 #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
837 
838 #define	V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
839 #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
840 
841 #define	V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
842 #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
843 
844 #define	V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
845 #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
846 
847 #define	V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
848 #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
849 
850 #define V2_QPC_BYTE_232_SO_LP_VLD_S 29
851 #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
852 #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
853 
854 #define	V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
855 #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
856 
857 #define	V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
858 #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
859 
860 #define	V2_QPC_BYTE_240_RX_ACK_MSN_S 16
861 #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
862 
863 #define	V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
864 #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
865 
866 #define	V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
867 #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
868 
869 #define	V2_QPC_BYTE_244_RNR_CNT_S 27
870 #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
871 
872 #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
873 #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
874 
875 #define	V2_QPC_BYTE_248_IRRL_PSN_S 0
876 #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
877 
878 #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
879 
880 #define	V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
881 #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
882 
883 #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
884 
885 #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
886 
887 #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
888 
889 #define	V2_QPC_BYTE_252_TX_CQN_S 0
890 #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
891 
892 #define	V2_QPC_BYTE_252_SIG_TYPE_S 24
893 
894 #define	V2_QPC_BYTE_252_ERR_TYPE_S 25
895 #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
896 
897 #define	V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
898 #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
899 
900 #define	V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
901 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
902 
903 #define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)
904 
905 #define QPCEX_STASH QPCEX_FIELD_LOC(82, 82)
906 
907 #define	V2_QP_RWE_S 1 /* rdma write enable */
908 #define	V2_QP_RRE_S 2 /* rdma read enable */
909 #define	V2_QP_ATE_S 3 /* rdma atomic enable */
910 
911 struct hns_roce_v2_cqe {
912 	__le32	byte_4;
913 	union {
914 		__le32 rkey;
915 		__le32 immtdata;
916 	};
917 	__le32	byte_12;
918 	__le32	byte_16;
919 	__le32	byte_cnt;
920 	u8	smac[4];
921 	__le32	byte_28;
922 	__le32	byte_32;
923 	__le32	rsv[8];
924 };
925 
926 #define	V2_CQE_BYTE_4_OPCODE_S 0
927 #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
928 
929 #define	V2_CQE_BYTE_4_RQ_INLINE_S 5
930 
931 #define	V2_CQE_BYTE_4_S_R_S 6
932 
933 #define	V2_CQE_BYTE_4_OWNER_S 7
934 
935 #define	V2_CQE_BYTE_4_STATUS_S 8
936 #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
937 
938 #define	V2_CQE_BYTE_4_WQE_INDX_S 16
939 #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
940 
941 #define	V2_CQE_BYTE_12_XRC_SRQN_S 0
942 #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
943 
944 #define	V2_CQE_BYTE_16_LCL_QPN_S 0
945 #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
946 
947 #define	V2_CQE_BYTE_16_SUB_STATUS_S 24
948 #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
949 
950 #define	V2_CQE_BYTE_28_SMAC_4_S 0
951 #define V2_CQE_BYTE_28_SMAC_4_M	GENMASK(7, 0)
952 
953 #define	V2_CQE_BYTE_28_SMAC_5_S 8
954 #define V2_CQE_BYTE_28_SMAC_5_M	GENMASK(15, 8)
955 
956 #define	V2_CQE_BYTE_28_PORT_TYPE_S 16
957 #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
958 
959 #define V2_CQE_BYTE_28_VID_S 18
960 #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
961 
962 #define V2_CQE_BYTE_28_VID_VLD_S 30
963 
964 #define	V2_CQE_BYTE_32_RMT_QPN_S 0
965 #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
966 
967 #define	V2_CQE_BYTE_32_SL_S 24
968 #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
969 
970 #define	V2_CQE_BYTE_32_PORTN_S 27
971 #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
972 
973 #define	V2_CQE_BYTE_32_GRH_S 30
974 
975 #define	V2_CQE_BYTE_32_LPK_S 31
976 
977 struct hns_roce_v2_mpt_entry {
978 	__le32	byte_4_pd_hop_st;
979 	__le32	byte_8_mw_cnt_en;
980 	__le32	byte_12_mw_pa;
981 	__le32	bound_lkey;
982 	__le32	len_l;
983 	__le32	len_h;
984 	__le32	lkey;
985 	__le32	va_l;
986 	__le32	va_h;
987 	__le32	pbl_size;
988 	__le32	pbl_ba_l;
989 	__le32	byte_48_mode_ba;
990 	__le32	pa0_l;
991 	__le32	byte_56_pa0_h;
992 	__le32	pa1_l;
993 	__le32	byte_64_buf_pa1;
994 };
995 
996 #define V2_MPT_BYTE_4_MPT_ST_S 0
997 #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
998 
999 #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
1000 #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
1001 
1002 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
1003 #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
1004 
1005 #define V2_MPT_BYTE_4_PD_S 8
1006 #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
1007 
1008 #define V2_MPT_BYTE_8_RA_EN_S 0
1009 
1010 #define V2_MPT_BYTE_8_R_INV_EN_S 1
1011 
1012 #define V2_MPT_BYTE_8_L_INV_EN_S 2
1013 
1014 #define V2_MPT_BYTE_8_BIND_EN_S 3
1015 
1016 #define V2_MPT_BYTE_8_ATOMIC_EN_S 4
1017 
1018 #define V2_MPT_BYTE_8_RR_EN_S 5
1019 
1020 #define V2_MPT_BYTE_8_RW_EN_S 6
1021 
1022 #define V2_MPT_BYTE_8_LW_EN_S 7
1023 
1024 #define V2_MPT_BYTE_8_MW_CNT_S 8
1025 #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1026 
1027 #define V2_MPT_BYTE_12_FRE_S 0
1028 
1029 #define V2_MPT_BYTE_12_PA_S 1
1030 
1031 #define V2_MPT_BYTE_12_MR_MW_S 4
1032 
1033 #define V2_MPT_BYTE_12_BPD_S 5
1034 
1035 #define V2_MPT_BYTE_12_BQP_S 6
1036 
1037 #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
1038 
1039 #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
1040 #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1041 
1042 #define V2_MPT_BYTE_48_PBL_BA_H_S 0
1043 #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1044 
1045 #define V2_MPT_BYTE_48_BLK_MODE_S 29
1046 
1047 #define V2_MPT_BYTE_56_PA0_H_S 0
1048 #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1049 
1050 #define V2_MPT_BYTE_64_PA1_H_S 0
1051 #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1052 
1053 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
1054 #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1055 
1056 #define	V2_DB_BYTE_4_TAG_S 0
1057 #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1058 
1059 #define	V2_DB_BYTE_4_CMD_S 24
1060 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
1061 
1062 #define V2_DB_PARAMETER_IDX_S 0
1063 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
1064 
1065 #define V2_DB_PARAMETER_SL_S 16
1066 #define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
1067 
1068 #define	V2_CQ_DB_BYTE_4_TAG_S 0
1069 #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1070 
1071 #define	V2_CQ_DB_BYTE_4_CMD_S 24
1072 #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
1073 
1074 #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
1075 #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1076 
1077 #define V2_CQ_DB_PARAMETER_CMD_SN_S 25
1078 #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
1079 
1080 #define V2_CQ_DB_PARAMETER_NOTIFY_S 24
1081 
1082 struct hns_roce_v2_ud_send_wqe {
1083 	__le32	byte_4;
1084 	__le32	msg_len;
1085 	__le32	immtdata;
1086 	__le32	byte_16;
1087 	__le32	byte_20;
1088 	__le32	byte_24;
1089 	__le32	qkey;
1090 	__le32	byte_32;
1091 	__le32	byte_36;
1092 	__le32	byte_40;
1093 	u8	dmac[ETH_ALEN];
1094 	u8	sgid_index;
1095 	u8	smac_index;
1096 	u8	dgid[GID_LEN_V2];
1097 };
1098 
1099 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1100 #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1101 
1102 #define	V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
1103 
1104 #define	V2_UD_SEND_WQE_BYTE_4_CQE_S 8
1105 
1106 #define	V2_UD_SEND_WQE_BYTE_4_SE_S 11
1107 
1108 #define	V2_UD_SEND_WQE_BYTE_16_PD_S 0
1109 #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1110 
1111 #define	V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
1112 #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1113 
1114 #define	V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1115 #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1116 
1117 #define	V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
1118 #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1119 
1120 #define	V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1121 #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1122 
1123 #define	V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1124 #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1125 
1126 #define	V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
1127 #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1128 
1129 #define	V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
1130 #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1131 
1132 #define	V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1133 #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1134 
1135 #define	V2_UD_SEND_WQE_BYTE_40_SL_S 20
1136 #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1137 
1138 #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
1139 
1140 #define	V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1141 
1142 struct hns_roce_v2_rc_send_wqe {
1143 	__le32		byte_4;
1144 	__le32		msg_len;
1145 	union {
1146 		__le32  inv_key;
1147 		__le32  immtdata;
1148 	};
1149 	__le32		byte_16;
1150 	__le32		byte_20;
1151 	__le32		rkey;
1152 	__le64		va;
1153 };
1154 
1155 #define	V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1156 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1157 
1158 #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1159 
1160 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1161 
1162 #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1163 
1164 #define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1165 
1166 #define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1167 
1168 #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1169 
1170 #define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
1171 
1172 #define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
1173 
1174 #define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
1175 
1176 #define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
1177 
1178 #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
1179 
1180 #define	V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1181 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1182 
1183 #define	V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1184 #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1185 
1186 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1187 #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1188 
1189 #define V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S 31
1190 
1191 struct hns_roce_wqe_frmr_seg {
1192 	__le32	pbl_size;
1193 	__le32	mode_buf_pg_sz;
1194 };
1195 
1196 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S	4
1197 #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M	GENMASK(7, 4)
1198 
1199 #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1200 
1201 struct hns_roce_v2_wqe_data_seg {
1202 	__le32    len;
1203 	__le32    lkey;
1204 	__le64    addr;
1205 };
1206 
1207 struct hns_roce_v2_db {
1208 	__le32	byte_4;
1209 	__le32	parameter;
1210 };
1211 
1212 struct hns_roce_query_version {
1213 	__le16 rocee_vendor_id;
1214 	__le16 rocee_hw_version;
1215 	__le32 rsv[5];
1216 };
1217 
1218 struct hns_roce_query_fw_info {
1219 	__le32 fw_ver;
1220 	__le32 rsv[5];
1221 };
1222 
1223 struct hns_roce_func_clear {
1224 	__le32 rst_funcid_en;
1225 	__le32 func_done;
1226 	__le32 rsv[4];
1227 };
1228 
1229 #define FUNC_CLEAR_RST_FUN_DONE_S 0
1230 /* Each physical function manages up to 248 virtual functions, it takes up to
1231  * 100ms for each function to execute clear. If an abnormal reset occurs, it is
1232  * executed twice at most, so it takes up to 249 * 2 * 100ms.
1233  */
1234 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS	(249 * 2 * 100)
1235 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL	40
1236 #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT	20
1237 
1238 struct hns_roce_cfg_llm_a {
1239 	__le32 base_addr_l;
1240 	__le32 base_addr_h;
1241 	__le32 depth_pgsz_init_en;
1242 	__le32 head_ba_l;
1243 	__le32 head_ba_h_nxtptr;
1244 	__le32 head_ptr;
1245 };
1246 
1247 #define CFG_LLM_QUE_DEPTH_S 0
1248 #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1249 
1250 #define CFG_LLM_QUE_PGSZ_S 16
1251 #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1252 
1253 #define CFG_LLM_INIT_EN_S 20
1254 #define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1255 
1256 #define CFG_LLM_HEAD_PTR_S 0
1257 #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1258 
1259 struct hns_roce_cfg_llm_b {
1260 	__le32 tail_ba_l;
1261 	__le32 tail_ba_h;
1262 	__le32 tail_ptr;
1263 	__le32 rsv[3];
1264 };
1265 
1266 #define CFG_LLM_TAIL_BA_H_S 0
1267 #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1268 
1269 #define CFG_LLM_TAIL_PTR_S 0
1270 #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1271 
1272 struct hns_roce_cfg_global_param {
1273 	__le32 time_cfg_udp_port;
1274 	__le32 rsv[5];
1275 };
1276 
1277 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1278 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1279 
1280 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1281 #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1282 
1283 struct hns_roce_pf_res_a {
1284 	__le32	rsv;
1285 	__le32	qpc_bt_idx_num;
1286 	__le32	srqc_bt_idx_num;
1287 	__le32	cqc_bt_idx_num;
1288 	__le32	mpt_bt_idx_num;
1289 	__le32	eqc_bt_idx_num;
1290 };
1291 
1292 #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1293 #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1294 
1295 #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1296 #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1297 
1298 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1299 #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1300 
1301 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1302 #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1303 
1304 #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1305 #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1306 
1307 #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1308 #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1309 
1310 #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1311 #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1312 
1313 #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1314 #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1315 
1316 #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1317 #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1318 
1319 #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1320 #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1321 
1322 struct hns_roce_pf_res_b {
1323 	__le32	rsv0;
1324 	__le32	smac_idx_num;
1325 	__le32	sgid_idx_num;
1326 	__le32	qid_idx_sl_num;
1327 	__le32	sccc_bt_idx_num;
1328 	__le32	gmv_idx_num;
1329 };
1330 
1331 #define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1332 #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1333 
1334 #define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1335 #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1336 
1337 #define PF_RES_DATA_2_PF_SGID_IDX_S 0
1338 #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1339 
1340 #define PF_RES_DATA_2_PF_SGID_NUM_S 8
1341 #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1342 
1343 #define PF_RES_DATA_3_PF_QID_IDX_S 0
1344 #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1345 
1346 #define PF_RES_DATA_3_PF_SL_NUM_S 16
1347 #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1348 
1349 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
1350 #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
1351 
1352 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9
1353 #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
1354 
1355 #define PF_RES_DATA_5_PF_GMV_BT_IDX_S 0
1356 #define PF_RES_DATA_5_PF_GMV_BT_IDX_M GENMASK(7, 0)
1357 
1358 #define PF_RES_DATA_5_PF_GMV_BT_NUM_S 8
1359 #define PF_RES_DATA_5_PF_GMV_BT_NUM_M GENMASK(16, 8)
1360 
1361 struct hns_roce_pf_timer_res_a {
1362 	__le32	rsv0;
1363 	__le32	qpc_timer_bt_idx_num;
1364 	__le32	cqc_timer_bt_idx_num;
1365 	__le32	rsv[3];
1366 };
1367 
1368 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
1369 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
1370 
1371 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16
1372 #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
1373 
1374 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
1375 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
1376 
1377 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16
1378 #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
1379 
1380 struct hns_roce_vf_res_a {
1381 	__le32 vf_id;
1382 	__le32 vf_qpc_bt_idx_num;
1383 	__le32 vf_srqc_bt_idx_num;
1384 	__le32 vf_cqc_bt_idx_num;
1385 	__le32 vf_mpt_bt_idx_num;
1386 	__le32 vf_eqc_bt_idx_num;
1387 };
1388 
1389 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1390 #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1391 
1392 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1393 #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1394 
1395 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1396 #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1397 
1398 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1399 #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1400 
1401 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1402 #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1403 
1404 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1405 #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1406 
1407 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1408 #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1409 
1410 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1411 #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1412 
1413 #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1414 #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1415 
1416 #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1417 #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1418 
1419 struct hns_roce_vf_res_b {
1420 	__le32 rsv0;
1421 	__le32 vf_smac_idx_num;
1422 	__le32 vf_sgid_idx_num;
1423 	__le32 vf_qid_idx_sl_num;
1424 	__le32 vf_sccc_idx_num;
1425 	__le32 vf_gmv_idx_num;
1426 };
1427 
1428 #define VF_RES_B_DATA_0_VF_ID_S 0
1429 #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1430 
1431 #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1432 #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1433 
1434 #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1435 #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1436 
1437 #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1438 #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1439 
1440 #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1441 #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1442 
1443 #define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1444 #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1445 
1446 #define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1447 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1448 
1449 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
1450 #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
1451 
1452 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9
1453 #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
1454 
1455 #define VF_RES_B_DATA_5_VF_GMV_BT_IDX_S 0
1456 #define VF_RES_B_DATA_5_VF_GMV_BT_IDX_M GENMASK(7, 0)
1457 
1458 #define VF_RES_B_DATA_5_VF_GMV_BT_NUM_S 16
1459 #define VF_RES_B_DATA_5_VF_GMV_BT_NUM_M GENMASK(24, 16)
1460 
1461 struct hns_roce_vf_switch {
1462 	__le32 rocee_sel;
1463 	__le32 fun_id;
1464 	__le32 cfg;
1465 	__le32 resv1;
1466 	__le32 resv2;
1467 	__le32 resv3;
1468 };
1469 
1470 #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1471 #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1472 
1473 #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1474 #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1475 #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1476 
1477 struct hns_roce_post_mbox {
1478 	__le32	in_param_l;
1479 	__le32	in_param_h;
1480 	__le32	out_param_l;
1481 	__le32	out_param_h;
1482 	__le32	cmd_tag;
1483 	__le32	token_event_en;
1484 };
1485 
1486 struct hns_roce_mbox_status {
1487 	__le32	mb_status_hw_run;
1488 	__le32	rsv[5];
1489 };
1490 
1491 struct hns_roce_cfg_bt_attr {
1492 	__le32 vf_qpc_cfg;
1493 	__le32 vf_srqc_cfg;
1494 	__le32 vf_cqc_cfg;
1495 	__le32 vf_mpt_cfg;
1496 	__le32 vf_sccc_cfg;
1497 	__le32 rsv;
1498 };
1499 
1500 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1501 #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1502 
1503 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1504 #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1505 
1506 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1507 #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1508 
1509 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1510 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1511 
1512 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1513 #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1514 
1515 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1516 #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1517 
1518 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1519 #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1520 
1521 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1522 #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1523 
1524 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1525 #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1526 
1527 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1528 #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1529 
1530 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1531 #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1532 
1533 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1534 #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1535 
1536 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
1537 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
1538 
1539 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4
1540 #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
1541 
1542 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8
1543 #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
1544 
1545 struct hns_roce_cfg_sgid_tb {
1546 	__le32	table_idx_rsv;
1547 	__le32	vf_sgid_l;
1548 	__le32	vf_sgid_ml;
1549 	__le32	vf_sgid_mh;
1550 	__le32	vf_sgid_h;
1551 	__le32	vf_sgid_type_rsv;
1552 };
1553 
1554 enum {
1555 	HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1556 	HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1557 };
1558 
1559 struct hns_roce_cfg_entry_size {
1560 	__le32	type;
1561 	__le32	rsv[4];
1562 	__le32	size;
1563 };
1564 
1565 #define CFG_SGID_TB_TABLE_IDX_S 0
1566 #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1567 
1568 #define CFG_SGID_TB_VF_SGID_TYPE_S 0
1569 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1570 
1571 struct hns_roce_cfg_smac_tb {
1572 	__le32	tb_idx_rsv;
1573 	__le32	vf_smac_l;
1574 	__le32	vf_smac_h_rsv;
1575 	__le32	rsv[3];
1576 };
1577 #define CFG_SMAC_TB_IDX_S 0
1578 #define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1579 
1580 #define CFG_SMAC_TB_VF_SMAC_H_S 0
1581 #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1582 
1583 struct hns_roce_cfg_gmv_bt {
1584 	__le32 gmv_ba_l;
1585 	__le32 gmv_ba_h;
1586 	__le32 gmv_bt_idx;
1587 	__le32 rsv[3];
1588 };
1589 
1590 #define CFG_GMV_BA_H_S 0
1591 #define CFG_GMV_BA_H_M GENMASK(19, 0)
1592 
1593 struct hns_roce_cfg_gmv_tb_a {
1594 	__le32 vf_sgid_l;
1595 	__le32 vf_sgid_ml;
1596 	__le32 vf_sgid_mh;
1597 	__le32 vf_sgid_h;
1598 	__le32 vf_sgid_type_vlan;
1599 	__le32 resv;
1600 };
1601 
1602 #define CFG_GMV_TB_SGID_IDX_S 0
1603 #define CFG_GMV_TB_SGID_IDX_M GENMASK(7, 0)
1604 
1605 #define CFG_GMV_TB_VF_SGID_TYPE_S 0
1606 #define CFG_GMV_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1607 
1608 #define CFG_GMV_TB_VF_VLAN_EN_S 2
1609 
1610 #define CFG_GMV_TB_VF_VLAN_ID_S 16
1611 #define CFG_GMV_TB_VF_VLAN_ID_M GENMASK(27, 16)
1612 
1613 struct hns_roce_cfg_gmv_tb_b {
1614 	__le32	vf_smac_l;
1615 	__le32	vf_smac_h;
1616 	__le32	table_idx_rsv;
1617 	__le32	resv[3];
1618 };
1619 
1620 #define CFG_GMV_TB_SMAC_H_S 0
1621 #define CFG_GMV_TB_SMAC_H_M GENMASK(15, 0)
1622 
1623 #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1624 struct hns_roce_query_pf_caps_a {
1625 	u8 number_ports;
1626 	u8 local_ca_ack_delay;
1627 	__le16 max_sq_sg;
1628 	__le16 max_sq_inline;
1629 	__le16 max_rq_sg;
1630 	__le32 max_extend_sg;
1631 	__le16 num_qpc_timer;
1632 	__le16 num_cqc_timer;
1633 	__le16 max_srq_sges;
1634 	u8 num_aeq_vectors;
1635 	u8 num_other_vectors;
1636 	u8 max_sq_desc_sz;
1637 	u8 max_rq_desc_sz;
1638 	u8 max_srq_desc_sz;
1639 	u8 cqe_sz;
1640 };
1641 
1642 struct hns_roce_query_pf_caps_b {
1643 	u8 mtpt_entry_sz;
1644 	u8 irrl_entry_sz;
1645 	u8 trrl_entry_sz;
1646 	u8 cqc_entry_sz;
1647 	u8 srqc_entry_sz;
1648 	u8 idx_entry_sz;
1649 	u8 sccc_sz;
1650 	u8 max_mtu;
1651 	__le16 qpc_sz;
1652 	__le16 qpc_timer_entry_sz;
1653 	__le16 cqc_timer_entry_sz;
1654 	u8 min_cqes;
1655 	u8 min_wqes;
1656 	__le32 page_size_cap;
1657 	u8 pkey_table_len;
1658 	u8 phy_num_uars;
1659 	u8 ctx_hop_num;
1660 	u8 pbl_hop_num;
1661 };
1662 
1663 struct hns_roce_query_pf_caps_c {
1664 	__le32 cap_flags_num_pds;
1665 	__le32 max_gid_num_cqs;
1666 	__le32 cq_depth;
1667 	__le32 num_mrws;
1668 	__le32 ord_num_qps;
1669 	__le16 sq_depth;
1670 	__le16 rq_depth;
1671 };
1672 
1673 #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0
1674 #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0)
1675 
1676 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20
1677 #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20)
1678 
1679 #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0
1680 #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0)
1681 
1682 #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20
1683 #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20)
1684 
1685 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0
1686 #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0)
1687 
1688 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0
1689 #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0)
1690 
1691 #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0
1692 #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0)
1693 
1694 #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20
1695 #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20)
1696 
1697 struct hns_roce_query_pf_caps_d {
1698 	__le32 wq_hop_num_max_srqs;
1699 	__le16 srq_depth;
1700 	__le16 cap_flags_ex;
1701 	__le32 num_ceqs_ceq_depth;
1702 	__le32 arm_st_aeq_depth;
1703 	__le32 num_uars_rsv_pds;
1704 	__le32 rsv_uars_rsv_qps;
1705 };
1706 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0
1707 #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(19, 0)
1708 
1709 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20
1710 #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20)
1711 
1712 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22
1713 #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22)
1714 
1715 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24
1716 #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24)
1717 
1718 
1719 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0
1720 #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0)
1721 
1722 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22
1723 #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22)
1724 
1725 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0
1726 #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0)
1727 
1728 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22
1729 #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22)
1730 
1731 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24
1732 #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24)
1733 
1734 #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0
1735 #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0)
1736 
1737 #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20
1738 #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20)
1739 
1740 #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0
1741 #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0)
1742 
1743 #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20
1744 #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20)
1745 
1746 struct hns_roce_query_pf_caps_e {
1747 	__le32 chunk_size_shift_rsv_mrws;
1748 	__le32 rsv_cqs;
1749 	__le32 rsv_srqs;
1750 	__le32 rsv_lkey;
1751 	__le16 ceq_max_cnt;
1752 	__le16 ceq_period;
1753 	__le16 aeq_max_cnt;
1754 	__le16 aeq_period;
1755 };
1756 
1757 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0
1758 #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0)
1759 
1760 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20
1761 #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20)
1762 
1763 #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0
1764 #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0)
1765 
1766 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0
1767 #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0)
1768 
1769 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0
1770 #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0)
1771 
1772 struct hns_roce_cmq_desc {
1773 	__le16 opcode;
1774 	__le16 flag;
1775 	__le16 retval;
1776 	__le16 rsv;
1777 	__le32 data[6];
1778 };
1779 
1780 #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS	10000
1781 
1782 #define HNS_ROCE_HW_RUN_BIT_SHIFT	31
1783 #define HNS_ROCE_HW_MB_STATUS_MASK	0xFF
1784 
1785 struct hns_roce_v2_cmq_ring {
1786 	dma_addr_t desc_dma_addr;
1787 	struct hns_roce_cmq_desc *desc;
1788 	u32 head;
1789 	u32 tail;
1790 
1791 	u16 buf_size;
1792 	u16 desc_num;
1793 	int next_to_use;
1794 	int next_to_clean;
1795 	u8 flag;
1796 	spinlock_t lock; /* command queue lock */
1797 };
1798 
1799 struct hns_roce_v2_cmq {
1800 	struct hns_roce_v2_cmq_ring csq;
1801 	struct hns_roce_v2_cmq_ring crq;
1802 	u16 tx_timeout;
1803 	u16 last_status;
1804 };
1805 
1806 enum hns_roce_link_table_type {
1807 	TSQ_LINK_TABLE,
1808 	TPQ_LINK_TABLE,
1809 };
1810 
1811 struct hns_roce_link_table {
1812 	struct hns_roce_buf_list table;
1813 	struct hns_roce_buf_list *pg_list;
1814 	u32 npages;
1815 	u32 pg_sz;
1816 };
1817 
1818 struct hns_roce_link_table_entry {
1819 	u32 blk_ba0;
1820 	u32 blk_ba1_nxt_ptr;
1821 };
1822 #define HNS_ROCE_LINK_TABLE_BA1_S 0
1823 #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1824 
1825 #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1826 #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1827 
1828 struct hns_roce_v2_priv {
1829 	struct hnae3_handle *handle;
1830 	struct hns_roce_v2_cmq cmq;
1831 	struct hns_roce_link_table tsq;
1832 	struct hns_roce_link_table tpq;
1833 };
1834 
1835 struct hns_roce_eq_context {
1836 	__le32	byte_4;
1837 	__le32	byte_8;
1838 	__le32	byte_12;
1839 	__le32	eqe_report_timer;
1840 	__le32	eqe_ba0;
1841 	__le32	eqe_ba1;
1842 	__le32	byte_28;
1843 	__le32	byte_32;
1844 	__le32	byte_36;
1845 	__le32	byte_40;
1846 	__le32	byte_44;
1847 	__le32	rsv[5];
1848 };
1849 
1850 #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM	0x0
1851 #define HNS_ROCE_AEQ_DEFAULT_INTERVAL	0x0
1852 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM	0x0
1853 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL	0x0
1854 
1855 #define HNS_ROCE_V2_EQ_STATE_INVALID		0
1856 #define HNS_ROCE_V2_EQ_STATE_VALID		1
1857 #define HNS_ROCE_V2_EQ_STATE_OVERFLOW		2
1858 #define HNS_ROCE_V2_EQ_STATE_FAILURE		3
1859 
1860 #define HNS_ROCE_V2_EQ_OVER_IGNORE_0		0
1861 #define HNS_ROCE_V2_EQ_OVER_IGNORE_1		1
1862 
1863 #define HNS_ROCE_V2_EQ_COALESCE_0		0
1864 #define HNS_ROCE_V2_EQ_COALESCE_1		1
1865 
1866 #define HNS_ROCE_V2_EQ_FIRED			0
1867 #define HNS_ROCE_V2_EQ_ARMED			1
1868 #define HNS_ROCE_V2_EQ_ALWAYS_ARMED		3
1869 
1870 #define HNS_ROCE_EQ_INIT_EQE_CNT		0
1871 #define HNS_ROCE_EQ_INIT_PROD_IDX		0
1872 #define HNS_ROCE_EQ_INIT_REPORT_TIMER		0
1873 #define HNS_ROCE_EQ_INIT_MSI_IDX		0
1874 #define HNS_ROCE_EQ_INIT_CONS_IDX		0
1875 #define HNS_ROCE_EQ_INIT_NXT_EQE_BA		0
1876 
1877 #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S		31
1878 #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S		31
1879 
1880 #define HNS_ROCE_V2_COMP_EQE_NUM		0x1000
1881 #define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000
1882 
1883 #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S	0
1884 #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S		1
1885 #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S	2
1886 
1887 #define HNS_ROCE_EQ_DB_CMD_AEQ			0x0
1888 #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED		0x1
1889 #define HNS_ROCE_EQ_DB_CMD_CEQ			0x2
1890 #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED		0x3
1891 
1892 #define EQ_ENABLE				1
1893 #define EQ_DISABLE				0
1894 
1895 #define EQ_REG_OFFSET				0x4
1896 
1897 #define HNS_ROCE_INT_NAME_LEN			32
1898 #define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1899 
1900 #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1901 
1902 #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1903 #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1904 #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1905 #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1906 #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1907 
1908 /* WORD0 */
1909 #define HNS_ROCE_EQC_EQ_ST_S 0
1910 #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1911 
1912 #define HNS_ROCE_EQC_HOP_NUM_S 2
1913 #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1914 
1915 #define HNS_ROCE_EQC_OVER_IGNORE_S 4
1916 #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1917 
1918 #define HNS_ROCE_EQC_COALESCE_S 5
1919 #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1920 
1921 #define HNS_ROCE_EQC_ARM_ST_S 6
1922 #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1923 
1924 #define HNS_ROCE_EQC_EQN_S 8
1925 #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1926 
1927 #define HNS_ROCE_EQC_EQE_CNT_S 16
1928 #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1929 
1930 /* WORD1 */
1931 #define HNS_ROCE_EQC_BA_PG_SZ_S 0
1932 #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1933 
1934 #define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1935 #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1936 
1937 #define HNS_ROCE_EQC_PROD_INDX_S 8
1938 #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1939 
1940 /* WORD2 */
1941 #define HNS_ROCE_EQC_MAX_CNT_S 0
1942 #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1943 
1944 #define HNS_ROCE_EQC_PERIOD_S 16
1945 #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1946 
1947 /* WORD3 */
1948 #define HNS_ROCE_EQC_REPORT_TIMER_S 0
1949 #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1950 
1951 /* WORD4 */
1952 #define HNS_ROCE_EQC_EQE_BA_L_S 0
1953 #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1954 
1955 /* WORD5 */
1956 #define HNS_ROCE_EQC_EQE_BA_H_S 0
1957 #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1958 
1959 /* WORD6 */
1960 #define HNS_ROCE_EQC_SHIFT_S 0
1961 #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1962 
1963 #define HNS_ROCE_EQC_MSI_INDX_S 8
1964 #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1965 
1966 #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1967 #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1968 
1969 /* WORD7 */
1970 #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1971 #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1972 
1973 /* WORD8 */
1974 #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1975 #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1976 
1977 #define HNS_ROCE_EQC_CONS_INDX_S 8
1978 #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1979 
1980 /* WORD9 */
1981 #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1982 #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1983 
1984 /* WORD10 */
1985 #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1986 #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1987 
1988 #define HNS_ROCE_EQC_EQE_SIZE_S 20
1989 #define HNS_ROCE_EQC_EQE_SIZE_M GENMASK(21, 20)
1990 
1991 #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1992 #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1993 
1994 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1995 #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1996 
1997 #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1998 #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1999 
2000 #define HNS_ROCE_V2_EQ_DB_CMD_S	16
2001 #define HNS_ROCE_V2_EQ_DB_CMD_M	GENMASK(17, 16)
2002 
2003 #define HNS_ROCE_V2_EQ_DB_TAG_S	0
2004 #define HNS_ROCE_V2_EQ_DB_TAG_M	GENMASK(7, 0)
2005 
2006 #define HNS_ROCE_V2_EQ_DB_PARA_S 0
2007 #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
2008 
2009 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
2010 #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
2011 
2012 #define MAX_SERVICE_LEVEL 0x7
2013 
2014 struct hns_roce_wqe_atomic_seg {
2015 	__le64          fetchadd_swap_data;
2016 	__le64          cmp_data;
2017 };
2018 
2019 struct hns_roce_sccc_clr {
2020 	__le32 qpn;
2021 	__le32 rsv[5];
2022 };
2023 
2024 struct hns_roce_sccc_clr_done {
2025 	__le32 clr_done;
2026 	__le32 rsv[5];
2027 };
2028 
2029 int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
2030 			       int *buffer);
2031 
2032 static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
2033 				    void __iomem *dest)
2034 {
2035 	struct hns_roce_v2_priv *priv = hr_dev->priv;
2036 	struct hnae3_handle *handle = priv->handle;
2037 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
2038 
2039 	if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
2040 		hns_roce_write64_k(val, dest);
2041 }
2042 
2043 #endif
2044