1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 52 struct ib_sge *sg) 53 { 54 dseg->lkey = cpu_to_le32(sg->lkey); 55 dseg->addr = cpu_to_le64(sg->addr); 56 dseg->len = cpu_to_le32(sg->length); 57 } 58 59 /* 60 * mapped-value = 1 + real-value 61 * The hns wr opcode real value is start from 0, In order to distinguish between 62 * initialized and uninitialized map values, we plus 1 to the actual value when 63 * defining the mapping, so that the validity can be identified by checking the 64 * mapped value is greater than 0. 65 */ 66 #define HR_OPC_MAP(ib_key, hr_key) \ 67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 68 69 static const u32 hns_roce_op_code[] = { 70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 72 HR_OPC_MAP(SEND, SEND), 73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 74 HR_OPC_MAP(RDMA_READ, RDMA_READ), 75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 81 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 82 }; 83 84 static u32 to_hr_opcode(u32 ib_opcode) 85 { 86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 87 return HNS_ROCE_V2_WQE_OP_MASK; 88 89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 90 HNS_ROCE_V2_WQE_OP_MASK; 91 } 92 93 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 94 const struct ib_reg_wr *wr) 95 { 96 struct hns_roce_wqe_frmr_seg *fseg = 97 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 98 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 99 u64 pbl_ba; 100 101 /* use ib_access_flags */ 102 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, 103 wr->access & IB_ACCESS_MW_BIND ? 1 : 0); 104 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, 105 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 106 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, 107 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); 108 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, 109 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 110 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, 111 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 112 113 /* Data structure reuse may lead to confusion */ 114 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 115 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 116 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 117 118 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 119 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 120 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 121 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 122 123 fseg->pbl_size = cpu_to_le32(mr->npages); 124 roce_set_field(fseg->mode_buf_pg_sz, 125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, 126 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, 127 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 128 roce_set_bit(fseg->mode_buf_pg_sz, 129 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); 130 } 131 132 static void set_atomic_seg(const struct ib_send_wr *wr, 133 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 134 unsigned int valid_num_sge) 135 { 136 struct hns_roce_v2_wqe_data_seg *dseg = 137 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 138 struct hns_roce_wqe_atomic_seg *aseg = 139 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 140 141 set_data_seg_v2(dseg, wr->sg_list); 142 143 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 144 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 145 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 146 } else { 147 aseg->fetchadd_swap_data = 148 cpu_to_le64(atomic_wr(wr)->compare_add); 149 aseg->cmp_data = 0; 150 } 151 152 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 153 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 154 } 155 156 static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 157 unsigned int *sge_ind, unsigned int valid_num_sge) 158 { 159 struct hns_roce_v2_wqe_data_seg *dseg; 160 unsigned int cnt = valid_num_sge; 161 struct ib_sge *sge = wr->sg_list; 162 unsigned int idx = *sge_ind; 163 164 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 165 cnt -= HNS_ROCE_SGE_IN_WQE; 166 sge += HNS_ROCE_SGE_IN_WQE; 167 } 168 169 while (cnt > 0) { 170 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 171 set_data_seg_v2(dseg, sge); 172 idx++; 173 sge++; 174 cnt--; 175 } 176 177 *sge_ind = idx; 178 } 179 180 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 181 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 182 unsigned int *sge_ind, 183 unsigned int valid_num_sge) 184 { 185 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 186 struct hns_roce_v2_wqe_data_seg *dseg = 187 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 188 struct ib_device *ibdev = &hr_dev->ib_dev; 189 struct hns_roce_qp *qp = to_hr_qp(ibqp); 190 void *wqe = dseg; 191 int j = 0; 192 int i; 193 194 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) { 195 if (unlikely(le32_to_cpu(rc_sq_wqe->msg_len) > 196 hr_dev->caps.max_sq_inline)) { 197 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal", 198 rc_sq_wqe->msg_len, 199 hr_dev->caps.max_sq_inline); 200 return -EINVAL; 201 } 202 203 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 204 ibdev_err(ibdev, "Not support inline data!\n"); 205 return -EINVAL; 206 } 207 208 for (i = 0; i < wr->num_sge; i++) { 209 memcpy(wqe, ((void *)wr->sg_list[i].addr), 210 wr->sg_list[i].length); 211 wqe += wr->sg_list[i].length; 212 } 213 214 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 215 1); 216 } else { 217 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 218 for (i = 0; i < wr->num_sge; i++) { 219 if (likely(wr->sg_list[i].length)) { 220 set_data_seg_v2(dseg, wr->sg_list + i); 221 dseg++; 222 } 223 } 224 } else { 225 roce_set_field(rc_sq_wqe->byte_20, 226 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 227 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 228 (*sge_ind) & (qp->sge.sge_cnt - 1)); 229 230 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; 231 i++) { 232 if (likely(wr->sg_list[i].length)) { 233 set_data_seg_v2(dseg, wr->sg_list + i); 234 dseg++; 235 j++; 236 } 237 } 238 239 set_extend_sge(qp, wr, sge_ind, valid_num_sge); 240 } 241 242 roce_set_field(rc_sq_wqe->byte_16, 243 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 244 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 245 } 246 247 return 0; 248 } 249 250 static int check_send_valid(struct hns_roce_dev *hr_dev, 251 struct hns_roce_qp *hr_qp) 252 { 253 struct ib_device *ibdev = &hr_dev->ib_dev; 254 struct ib_qp *ibqp = &hr_qp->ibqp; 255 256 if (unlikely(ibqp->qp_type != IB_QPT_RC && 257 ibqp->qp_type != IB_QPT_GSI && 258 ibqp->qp_type != IB_QPT_UD)) { 259 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 260 ibqp->qp_type); 261 return -EOPNOTSUPP; 262 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 263 hr_qp->state == IB_QPS_INIT || 264 hr_qp->state == IB_QPS_RTR)) { 265 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n", 266 hr_qp->state); 267 return -EINVAL; 268 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 269 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 270 hr_dev->state); 271 return -EIO; 272 } 273 274 return 0; 275 } 276 277 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 278 unsigned int *sge_len) 279 { 280 unsigned int valid_num = 0; 281 unsigned int len = 0; 282 int i; 283 284 for (i = 0; i < wr->num_sge; i++) { 285 if (likely(wr->sg_list[i].length)) { 286 len += wr->sg_list[i].length; 287 valid_num++; 288 } 289 } 290 291 *sge_len = len; 292 return valid_num; 293 } 294 295 static inline int set_ud_wqe(struct hns_roce_qp *qp, 296 const struct ib_send_wr *wr, 297 void *wqe, unsigned int *sge_idx, 298 unsigned int owner_bit) 299 { 300 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 301 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 302 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 303 unsigned int curr_idx = *sge_idx; 304 int valid_num_sge; 305 u32 msg_len = 0; 306 bool loopback; 307 u8 *smac; 308 309 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 310 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 311 312 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 313 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 314 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 315 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 316 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 317 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 318 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 319 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 320 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 321 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]); 322 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 323 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]); 324 325 /* MAC loopback */ 326 smac = (u8 *)hr_dev->dev_addr[qp->port]; 327 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0; 328 329 roce_set_bit(ud_sq_wqe->byte_40, 330 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 331 332 roce_set_field(ud_sq_wqe->byte_4, 333 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 334 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 335 HNS_ROCE_V2_WQE_OP_SEND); 336 337 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 338 339 switch (wr->opcode) { 340 case IB_WR_SEND_WITH_IMM: 341 case IB_WR_RDMA_WRITE_WITH_IMM: 342 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 343 break; 344 default: 345 ud_sq_wqe->immtdata = 0; 346 break; 347 } 348 349 /* Set sig attr */ 350 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 352 353 /* Set se attr */ 354 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 355 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 356 357 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 358 owner_bit); 359 360 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 361 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 362 363 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 364 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 365 366 roce_set_field(ud_sq_wqe->byte_20, 367 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 368 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 369 curr_idx & (qp->sge.sge_cnt - 1)); 370 371 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 372 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 373 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 374 qp->qkey : ud_wr(wr)->remote_qkey); 375 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 376 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 377 378 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 379 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 380 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 381 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 382 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 383 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 384 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 385 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 386 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 387 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 388 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M, 389 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port); 390 391 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 392 ah->av.vlan_en ? 1 : 0); 393 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 394 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index); 395 396 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2); 397 398 set_extend_sge(qp, wr, &curr_idx, valid_num_sge); 399 400 *sge_idx = curr_idx; 401 402 return 0; 403 } 404 405 static inline int set_rc_wqe(struct hns_roce_qp *qp, 406 const struct ib_send_wr *wr, 407 void *wqe, unsigned int *sge_idx, 408 unsigned int owner_bit) 409 { 410 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 411 unsigned int curr_idx = *sge_idx; 412 unsigned int valid_num_sge; 413 u32 msg_len = 0; 414 int ret = 0; 415 416 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 417 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 418 419 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 420 421 switch (wr->opcode) { 422 case IB_WR_SEND_WITH_IMM: 423 case IB_WR_RDMA_WRITE_WITH_IMM: 424 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 425 break; 426 case IB_WR_SEND_WITH_INV: 427 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 428 break; 429 default: 430 rc_sq_wqe->immtdata = 0; 431 break; 432 } 433 434 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 435 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 436 437 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 438 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 439 440 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 441 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 442 443 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 444 owner_bit); 445 446 switch (wr->opcode) { 447 case IB_WR_RDMA_READ: 448 case IB_WR_RDMA_WRITE: 449 case IB_WR_RDMA_WRITE_WITH_IMM: 450 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 451 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 452 break; 453 case IB_WR_LOCAL_INV: 454 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 455 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 456 break; 457 case IB_WR_REG_MR: 458 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 459 break; 460 case IB_WR_ATOMIC_CMP_AND_SWP: 461 case IB_WR_ATOMIC_FETCH_AND_ADD: 462 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 463 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 464 break; 465 default: 466 break; 467 } 468 469 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 470 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 471 to_hr_opcode(wr->opcode)); 472 473 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 474 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 475 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 476 else if (wr->opcode != IB_WR_REG_MR) 477 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 478 &curr_idx, valid_num_sge); 479 480 *sge_idx = curr_idx; 481 482 return ret; 483 } 484 485 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 486 struct hns_roce_qp *qp) 487 { 488 /* 489 * Hip08 hardware cannot flush the WQEs in SQ if the QP state 490 * gets into errored mode. Hence, as a workaround to this 491 * hardware limitation, driver needs to assist in flushing. But 492 * the flushing operation uses mailbox to convey the QP state to 493 * the hardware and which can sleep due to the mutex protection 494 * around the mailbox calls. Hence, use the deferred flush for 495 * now. 496 */ 497 if (qp->state == IB_QPS_ERR) { 498 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 499 init_flush_work(hr_dev, qp); 500 } else { 501 struct hns_roce_v2_db sq_db = {}; 502 503 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 504 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 505 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 506 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 507 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, 508 V2_DB_PARAMETER_IDX_S, qp->sq.head); 509 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 510 V2_DB_PARAMETER_SL_S, qp->sl); 511 512 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l); 513 } 514 } 515 516 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 517 const struct ib_send_wr *wr, 518 const struct ib_send_wr **bad_wr) 519 { 520 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 521 struct ib_device *ibdev = &hr_dev->ib_dev; 522 struct hns_roce_qp *qp = to_hr_qp(ibqp); 523 unsigned long flags = 0; 524 unsigned int owner_bit; 525 unsigned int sge_idx; 526 unsigned int wqe_idx; 527 void *wqe = NULL; 528 int nreq; 529 int ret; 530 531 spin_lock_irqsave(&qp->sq.lock, flags); 532 533 ret = check_send_valid(hr_dev, qp); 534 if (unlikely(ret)) { 535 *bad_wr = wr; 536 nreq = 0; 537 goto out; 538 } 539 540 sge_idx = qp->next_sge; 541 542 for (nreq = 0; wr; ++nreq, wr = wr->next) { 543 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 544 ret = -ENOMEM; 545 *bad_wr = wr; 546 goto out; 547 } 548 549 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 550 551 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 552 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n", 553 wr->num_sge, qp->sq.max_gs); 554 ret = -EINVAL; 555 *bad_wr = wr; 556 goto out; 557 } 558 559 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 560 qp->sq.wrid[wqe_idx] = wr->wr_id; 561 owner_bit = 562 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 563 564 /* Corresponding to the QP type, wqe process separately */ 565 if (ibqp->qp_type == IB_QPT_GSI) 566 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 567 else if (ibqp->qp_type == IB_QPT_RC) 568 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 569 570 if (unlikely(ret)) { 571 *bad_wr = wr; 572 goto out; 573 } 574 } 575 576 out: 577 if (likely(nreq)) { 578 qp->sq.head += nreq; 579 qp->next_sge = sge_idx; 580 /* Memory barrier */ 581 wmb(); 582 update_sq_db(hr_dev, qp); 583 } 584 585 spin_unlock_irqrestore(&qp->sq.lock, flags); 586 587 return ret; 588 } 589 590 static int check_recv_valid(struct hns_roce_dev *hr_dev, 591 struct hns_roce_qp *hr_qp) 592 { 593 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 594 return -EIO; 595 else if (hr_qp->state == IB_QPS_RESET) 596 return -EINVAL; 597 598 return 0; 599 } 600 601 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 602 const struct ib_recv_wr *wr, 603 const struct ib_recv_wr **bad_wr) 604 { 605 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 606 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 607 struct ib_device *ibdev = &hr_dev->ib_dev; 608 struct hns_roce_v2_wqe_data_seg *dseg; 609 struct hns_roce_rinl_sge *sge_list; 610 unsigned long flags; 611 void *wqe = NULL; 612 u32 wqe_idx; 613 int nreq; 614 int ret; 615 int i; 616 617 spin_lock_irqsave(&hr_qp->rq.lock, flags); 618 619 ret = check_recv_valid(hr_dev, hr_qp); 620 if (unlikely(ret)) { 621 *bad_wr = wr; 622 nreq = 0; 623 goto out; 624 } 625 626 for (nreq = 0; wr; ++nreq, wr = wr->next) { 627 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 628 hr_qp->ibqp.recv_cq))) { 629 ret = -ENOMEM; 630 *bad_wr = wr; 631 goto out; 632 } 633 634 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 635 636 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { 637 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n", 638 wr->num_sge, hr_qp->rq.max_gs); 639 ret = -EINVAL; 640 *bad_wr = wr; 641 goto out; 642 } 643 644 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 645 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 646 for (i = 0; i < wr->num_sge; i++) { 647 if (!wr->sg_list[i].length) 648 continue; 649 set_data_seg_v2(dseg, wr->sg_list + i); 650 dseg++; 651 } 652 653 if (wr->num_sge < hr_qp->rq.max_gs) { 654 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 655 dseg->addr = 0; 656 } 657 658 /* rq support inline data */ 659 if (hr_qp->rq_inl_buf.wqe_cnt) { 660 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 661 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = 662 (u32)wr->num_sge; 663 for (i = 0; i < wr->num_sge; i++) { 664 sge_list[i].addr = 665 (void *)(u64)wr->sg_list[i].addr; 666 sge_list[i].len = wr->sg_list[i].length; 667 } 668 } 669 670 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 671 } 672 673 out: 674 if (likely(nreq)) { 675 hr_qp->rq.head += nreq; 676 /* Memory barrier */ 677 wmb(); 678 679 /* 680 * Hip08 hardware cannot flush the WQEs in RQ if the QP state 681 * gets into errored mode. Hence, as a workaround to this 682 * hardware limitation, driver needs to assist in flushing. But 683 * the flushing operation uses mailbox to convey the QP state to 684 * the hardware and which can sleep due to the mutex protection 685 * around the mailbox calls. Hence, use the deferred flush for 686 * now. 687 */ 688 if (hr_qp->state == IB_QPS_ERR) { 689 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, 690 &hr_qp->flush_flag)) 691 init_flush_work(hr_dev, hr_qp); 692 } else { 693 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 694 } 695 } 696 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 697 698 return ret; 699 } 700 701 static void *get_srq_wqe(struct hns_roce_srq *srq, int n) 702 { 703 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 704 } 705 706 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n) 707 { 708 return hns_roce_buf_offset(idx_que->mtr.kmem, 709 n << idx_que->entry_shift); 710 } 711 712 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index) 713 { 714 /* always called with interrupts disabled. */ 715 spin_lock(&srq->lock); 716 717 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 718 srq->tail++; 719 720 spin_unlock(&srq->lock); 721 } 722 723 static int find_empty_entry(struct hns_roce_idx_que *idx_que, 724 unsigned long size) 725 { 726 int wqe_idx; 727 728 if (unlikely(bitmap_full(idx_que->bitmap, size))) 729 return -ENOSPC; 730 731 wqe_idx = find_first_zero_bit(idx_que->bitmap, size); 732 733 bitmap_set(idx_que->bitmap, wqe_idx, 1); 734 735 return wqe_idx; 736 } 737 738 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 739 const struct ib_recv_wr *wr, 740 const struct ib_recv_wr **bad_wr) 741 { 742 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 743 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 744 struct hns_roce_v2_wqe_data_seg *dseg; 745 struct hns_roce_v2_db srq_db; 746 unsigned long flags; 747 __le32 *srq_idx; 748 int ret = 0; 749 int wqe_idx; 750 void *wqe; 751 int nreq; 752 int ind; 753 int i; 754 755 spin_lock_irqsave(&srq->lock, flags); 756 757 ind = srq->head & (srq->wqe_cnt - 1); 758 759 for (nreq = 0; wr; ++nreq, wr = wr->next) { 760 if (unlikely(wr->num_sge >= srq->max_gs)) { 761 ret = -EINVAL; 762 *bad_wr = wr; 763 break; 764 } 765 766 if (unlikely(srq->head == srq->tail)) { 767 ret = -ENOMEM; 768 *bad_wr = wr; 769 break; 770 } 771 772 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt); 773 if (unlikely(wqe_idx < 0)) { 774 ret = -ENOMEM; 775 *bad_wr = wr; 776 break; 777 } 778 779 wqe = get_srq_wqe(srq, wqe_idx); 780 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 781 782 for (i = 0; i < wr->num_sge; ++i) { 783 dseg[i].len = cpu_to_le32(wr->sg_list[i].length); 784 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey); 785 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr); 786 } 787 788 if (wr->num_sge < srq->max_gs) { 789 dseg[i].len = 0; 790 dseg[i].lkey = cpu_to_le32(0x100); 791 dseg[i].addr = 0; 792 } 793 794 srq_idx = get_idx_buf(&srq->idx_que, ind); 795 *srq_idx = cpu_to_le32(wqe_idx); 796 797 srq->wrid[wqe_idx] = wr->wr_id; 798 ind = (ind + 1) & (srq->wqe_cnt - 1); 799 } 800 801 if (likely(nreq)) { 802 srq->head += nreq; 803 804 /* 805 * Make sure that descriptors are written before 806 * doorbell record. 807 */ 808 wmb(); 809 810 srq_db.byte_4 = 811 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S | 812 (srq->srqn & V2_DB_BYTE_4_TAG_M)); 813 srq_db.parameter = 814 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M); 815 816 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l); 817 } 818 819 spin_unlock_irqrestore(&srq->lock, flags); 820 821 return ret; 822 } 823 824 static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 825 unsigned long instance_stage, 826 unsigned long reset_stage) 827 { 828 /* When hardware reset has been completed once or more, we should stop 829 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 830 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 831 * stage of soft reset process, we should exit with error, and then 832 * HNAE3_INIT_CLIENT related process can rollback the operation like 833 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 834 * process will exit with error to notify NIC driver to reschedule soft 835 * reset process once again. 836 */ 837 hr_dev->is_reset = true; 838 hr_dev->dis_db = true; 839 840 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 841 instance_stage == HNS_ROCE_STATE_INIT) 842 return CMD_RST_PRC_EBUSY; 843 844 return CMD_RST_PRC_SUCCESS; 845 } 846 847 static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 848 unsigned long instance_stage, 849 unsigned long reset_stage) 850 { 851 struct hns_roce_v2_priv *priv = hr_dev->priv; 852 struct hnae3_handle *handle = priv->handle; 853 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 854 855 /* When hardware reset is detected, we should stop sending mailbox&cmq& 856 * doorbell to hardware. If now in .init_instance() function, we should 857 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 858 * process, we should exit with error, and then HNAE3_INIT_CLIENT 859 * related process can rollback the operation like notifing hardware to 860 * free resources, HNAE3_INIT_CLIENT related process will exit with 861 * error to notify NIC driver to reschedule soft reset process once 862 * again. 863 */ 864 hr_dev->dis_db = true; 865 if (!ops->get_hw_reset_stat(handle)) 866 hr_dev->is_reset = true; 867 868 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 869 instance_stage == HNS_ROCE_STATE_INIT) 870 return CMD_RST_PRC_EBUSY; 871 872 return CMD_RST_PRC_SUCCESS; 873 } 874 875 static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 876 { 877 struct hns_roce_v2_priv *priv = hr_dev->priv; 878 struct hnae3_handle *handle = priv->handle; 879 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 880 881 /* When software reset is detected at .init_instance() function, we 882 * should stop sending mailbox&cmq&doorbell to hardware, and exit 883 * with error. 884 */ 885 hr_dev->dis_db = true; 886 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 887 hr_dev->is_reset = true; 888 889 return CMD_RST_PRC_EBUSY; 890 } 891 892 static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev) 893 { 894 struct hns_roce_v2_priv *priv = hr_dev->priv; 895 struct hnae3_handle *handle = priv->handle; 896 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 897 unsigned long instance_stage; /* the current instance stage */ 898 unsigned long reset_stage; /* the current reset stage */ 899 unsigned long reset_cnt; 900 bool sw_resetting; 901 bool hw_resetting; 902 903 if (hr_dev->is_reset) 904 return CMD_RST_PRC_SUCCESS; 905 906 /* Get information about reset from NIC driver or RoCE driver itself, 907 * the meaning of the following variables from NIC driver are described 908 * as below: 909 * reset_cnt -- The count value of completed hardware reset. 910 * hw_resetting -- Whether hardware device is resetting now. 911 * sw_resetting -- Whether NIC's software reset process is running now. 912 */ 913 instance_stage = handle->rinfo.instance_state; 914 reset_stage = handle->rinfo.reset_state; 915 reset_cnt = ops->ae_dev_reset_cnt(handle); 916 hw_resetting = ops->get_cmdq_stat(handle); 917 sw_resetting = ops->ae_dev_resetting(handle); 918 919 if (reset_cnt != hr_dev->reset_cnt) 920 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 921 reset_stage); 922 else if (hw_resetting) 923 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 924 reset_stage); 925 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 926 return hns_roce_v2_cmd_sw_resetting(hr_dev); 927 928 return 0; 929 } 930 931 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 932 { 933 int ntu = ring->next_to_use; 934 int ntc = ring->next_to_clean; 935 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 936 937 return ring->desc_num - used - 1; 938 } 939 940 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 941 struct hns_roce_v2_cmq_ring *ring) 942 { 943 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 944 945 ring->desc = kzalloc(size, GFP_KERNEL); 946 if (!ring->desc) 947 return -ENOMEM; 948 949 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 950 DMA_BIDIRECTIONAL); 951 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 952 ring->desc_dma_addr = 0; 953 kfree(ring->desc); 954 ring->desc = NULL; 955 return -ENOMEM; 956 } 957 958 return 0; 959 } 960 961 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 962 struct hns_roce_v2_cmq_ring *ring) 963 { 964 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 965 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 966 DMA_BIDIRECTIONAL); 967 968 ring->desc_dma_addr = 0; 969 kfree(ring->desc); 970 } 971 972 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 973 { 974 struct hns_roce_v2_priv *priv = hr_dev->priv; 975 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 976 &priv->cmq.csq : &priv->cmq.crq; 977 978 ring->flag = ring_type; 979 ring->next_to_clean = 0; 980 ring->next_to_use = 0; 981 982 return hns_roce_alloc_cmq_desc(hr_dev, ring); 983 } 984 985 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 986 { 987 struct hns_roce_v2_priv *priv = hr_dev->priv; 988 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 989 &priv->cmq.csq : &priv->cmq.crq; 990 dma_addr_t dma = ring->desc_dma_addr; 991 992 if (ring_type == TYPE_CSQ) { 993 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 994 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 995 upper_32_bits(dma)); 996 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 997 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 998 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 999 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 1000 } else { 1001 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 1002 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 1003 upper_32_bits(dma)); 1004 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 1005 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1006 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 1007 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 1008 } 1009 } 1010 1011 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1012 { 1013 struct hns_roce_v2_priv *priv = hr_dev->priv; 1014 int ret; 1015 1016 /* Setup the queue entries for command queue */ 1017 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; 1018 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; 1019 1020 /* Setup the lock for command queue */ 1021 spin_lock_init(&priv->cmq.csq.lock); 1022 spin_lock_init(&priv->cmq.crq.lock); 1023 1024 /* Setup Tx write back timeout */ 1025 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1026 1027 /* Init CSQ */ 1028 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 1029 if (ret) { 1030 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 1031 return ret; 1032 } 1033 1034 /* Init CRQ */ 1035 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 1036 if (ret) { 1037 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 1038 goto err_crq; 1039 } 1040 1041 /* Init CSQ REG */ 1042 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 1043 1044 /* Init CRQ REG */ 1045 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 1046 1047 return 0; 1048 1049 err_crq: 1050 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1051 1052 return ret; 1053 } 1054 1055 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1056 { 1057 struct hns_roce_v2_priv *priv = hr_dev->priv; 1058 1059 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1060 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 1061 } 1062 1063 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1064 enum hns_roce_opcode_type opcode, 1065 bool is_read) 1066 { 1067 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1068 desc->opcode = cpu_to_le16(opcode); 1069 desc->flag = 1070 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1071 if (is_read) 1072 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1073 else 1074 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1075 } 1076 1077 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1078 { 1079 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1080 struct hns_roce_v2_priv *priv = hr_dev->priv; 1081 1082 return head == priv->cmq.csq.next_to_use; 1083 } 1084 1085 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 1086 { 1087 struct hns_roce_v2_priv *priv = hr_dev->priv; 1088 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1089 struct hns_roce_cmq_desc *desc; 1090 u16 ntc = csq->next_to_clean; 1091 u32 head; 1092 int clean = 0; 1093 1094 desc = &csq->desc[ntc]; 1095 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1096 while (head != ntc) { 1097 memset(desc, 0, sizeof(*desc)); 1098 ntc++; 1099 if (ntc == csq->desc_num) 1100 ntc = 0; 1101 desc = &csq->desc[ntc]; 1102 clean++; 1103 } 1104 csq->next_to_clean = ntc; 1105 1106 return clean; 1107 } 1108 1109 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1110 struct hns_roce_cmq_desc *desc, int num) 1111 { 1112 struct hns_roce_v2_priv *priv = hr_dev->priv; 1113 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1114 struct hns_roce_cmq_desc *desc_to_use; 1115 bool complete = false; 1116 u32 timeout = 0; 1117 int handle = 0; 1118 u16 desc_ret; 1119 int ret = 0; 1120 int ntc; 1121 1122 spin_lock_bh(&csq->lock); 1123 1124 if (num > hns_roce_cmq_space(csq)) { 1125 spin_unlock_bh(&csq->lock); 1126 return -EBUSY; 1127 } 1128 1129 /* 1130 * Record the location of desc in the cmq for this time 1131 * which will be use for hardware to write back 1132 */ 1133 ntc = csq->next_to_use; 1134 1135 while (handle < num) { 1136 desc_to_use = &csq->desc[csq->next_to_use]; 1137 *desc_to_use = desc[handle]; 1138 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 1139 csq->next_to_use++; 1140 if (csq->next_to_use == csq->desc_num) 1141 csq->next_to_use = 0; 1142 handle++; 1143 } 1144 1145 /* Write to hardware */ 1146 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 1147 1148 /* 1149 * If the command is sync, wait for the firmware to write back, 1150 * if multi descriptors to be sent, use the first one to check 1151 */ 1152 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 1153 do { 1154 if (hns_roce_cmq_csq_done(hr_dev)) 1155 break; 1156 udelay(1); 1157 timeout++; 1158 } while (timeout < priv->cmq.tx_timeout); 1159 } 1160 1161 if (hns_roce_cmq_csq_done(hr_dev)) { 1162 complete = true; 1163 handle = 0; 1164 while (handle < num) { 1165 /* get the result of hardware write back */ 1166 desc_to_use = &csq->desc[ntc]; 1167 desc[handle] = *desc_to_use; 1168 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 1169 desc_ret = le16_to_cpu(desc[handle].retval); 1170 if (desc_ret == CMD_EXEC_SUCCESS) 1171 ret = 0; 1172 else 1173 ret = -EIO; 1174 priv->cmq.last_status = desc_ret; 1175 ntc++; 1176 handle++; 1177 if (ntc == csq->desc_num) 1178 ntc = 0; 1179 } 1180 } 1181 1182 if (!complete) 1183 ret = -EAGAIN; 1184 1185 /* clean the command send queue */ 1186 handle = hns_roce_cmq_csq_clean(hr_dev); 1187 if (handle != num) 1188 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 1189 handle, num); 1190 1191 spin_unlock_bh(&csq->lock); 1192 1193 return ret; 1194 } 1195 1196 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1197 struct hns_roce_cmq_desc *desc, int num) 1198 { 1199 int retval; 1200 int ret; 1201 1202 ret = hns_roce_v2_rst_process_cmd(hr_dev); 1203 if (ret == CMD_RST_PRC_SUCCESS) 1204 return 0; 1205 if (ret == CMD_RST_PRC_EBUSY) 1206 return -EBUSY; 1207 1208 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1209 if (ret) { 1210 retval = hns_roce_v2_rst_process_cmd(hr_dev); 1211 if (retval == CMD_RST_PRC_SUCCESS) 1212 return 0; 1213 else if (retval == CMD_RST_PRC_EBUSY) 1214 return -EBUSY; 1215 } 1216 1217 return ret; 1218 } 1219 1220 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1221 { 1222 struct hns_roce_query_version *resp; 1223 struct hns_roce_cmq_desc desc; 1224 int ret; 1225 1226 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1227 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1228 if (ret) 1229 return ret; 1230 1231 resp = (struct hns_roce_query_version *)desc.data; 1232 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1233 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1234 1235 return 0; 1236 } 1237 1238 static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev) 1239 { 1240 struct hns_roce_v2_priv *priv = hr_dev->priv; 1241 struct hnae3_handle *handle = priv->handle; 1242 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1243 unsigned long reset_cnt; 1244 bool sw_resetting; 1245 bool hw_resetting; 1246 1247 reset_cnt = ops->ae_dev_reset_cnt(handle); 1248 hw_resetting = ops->get_hw_reset_stat(handle); 1249 sw_resetting = ops->ae_dev_resetting(handle); 1250 1251 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting) 1252 return true; 1253 1254 return false; 1255 } 1256 1257 static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval, 1258 int flag) 1259 { 1260 struct hns_roce_v2_priv *priv = hr_dev->priv; 1261 struct hnae3_handle *handle = priv->handle; 1262 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1263 unsigned long instance_stage; 1264 unsigned long reset_cnt; 1265 unsigned long end; 1266 bool sw_resetting; 1267 bool hw_resetting; 1268 1269 instance_stage = handle->rinfo.instance_state; 1270 reset_cnt = ops->ae_dev_reset_cnt(handle); 1271 hw_resetting = ops->get_hw_reset_stat(handle); 1272 sw_resetting = ops->ae_dev_resetting(handle); 1273 1274 if (reset_cnt != hr_dev->reset_cnt) { 1275 hr_dev->dis_db = true; 1276 hr_dev->is_reset = true; 1277 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1278 } else if (hw_resetting) { 1279 hr_dev->dis_db = true; 1280 1281 dev_warn(hr_dev->dev, 1282 "Func clear is pending, device in resetting state.\n"); 1283 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1284 while (end) { 1285 if (!ops->get_hw_reset_stat(handle)) { 1286 hr_dev->is_reset = true; 1287 dev_info(hr_dev->dev, 1288 "Func clear success after reset.\n"); 1289 return; 1290 } 1291 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1292 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1293 } 1294 1295 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1296 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) { 1297 hr_dev->dis_db = true; 1298 1299 dev_warn(hr_dev->dev, 1300 "Func clear is pending, device in resetting state.\n"); 1301 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1302 while (end) { 1303 if (ops->ae_dev_reset_cnt(handle) != 1304 hr_dev->reset_cnt) { 1305 hr_dev->is_reset = true; 1306 dev_info(hr_dev->dev, 1307 "Func clear success after sw reset\n"); 1308 return; 1309 } 1310 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1311 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1312 } 1313 1314 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1315 } else { 1316 if (retval && !flag) 1317 dev_warn(hr_dev->dev, 1318 "Func clear read failed, ret = %d.\n", retval); 1319 1320 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1321 } 1322 } 1323 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1324 { 1325 bool fclr_write_fail_flag = false; 1326 struct hns_roce_func_clear *resp; 1327 struct hns_roce_cmq_desc desc; 1328 unsigned long end; 1329 int ret = 0; 1330 1331 if (hns_roce_func_clr_chk_rst(hr_dev)) 1332 goto out; 1333 1334 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1335 resp = (struct hns_roce_func_clear *)desc.data; 1336 1337 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1338 if (ret) { 1339 fclr_write_fail_flag = true; 1340 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1341 ret); 1342 goto out; 1343 } 1344 1345 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1346 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1347 while (end) { 1348 if (hns_roce_func_clr_chk_rst(hr_dev)) 1349 goto out; 1350 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1351 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1352 1353 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1354 true); 1355 1356 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1357 if (ret) 1358 continue; 1359 1360 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1361 hr_dev->is_reset = true; 1362 return; 1363 } 1364 } 1365 1366 out: 1367 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag); 1368 } 1369 1370 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1371 { 1372 struct hns_roce_query_fw_info *resp; 1373 struct hns_roce_cmq_desc desc; 1374 int ret; 1375 1376 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1377 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1378 if (ret) 1379 return ret; 1380 1381 resp = (struct hns_roce_query_fw_info *)desc.data; 1382 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1383 1384 return 0; 1385 } 1386 1387 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1388 { 1389 struct hns_roce_cfg_global_param *req; 1390 struct hns_roce_cmq_desc desc; 1391 1392 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1393 false); 1394 1395 req = (struct hns_roce_cfg_global_param *)desc.data; 1396 memset(req, 0, sizeof(*req)); 1397 roce_set_field(req->time_cfg_udp_port, 1398 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 1399 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 1400 roce_set_field(req->time_cfg_udp_port, 1401 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 1402 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 1403 1404 return hns_roce_cmq_send(hr_dev, &desc, 1); 1405 } 1406 1407 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1408 { 1409 struct hns_roce_cmq_desc desc[2]; 1410 struct hns_roce_pf_res_a *req_a; 1411 struct hns_roce_pf_res_b *req_b; 1412 int ret; 1413 int i; 1414 1415 for (i = 0; i < 2; i++) { 1416 hns_roce_cmq_setup_basic_desc(&desc[i], 1417 HNS_ROCE_OPC_QUERY_PF_RES, true); 1418 1419 if (i == 0) 1420 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1421 else 1422 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1423 } 1424 1425 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1426 if (ret) 1427 return ret; 1428 1429 req_a = (struct hns_roce_pf_res_a *)desc[0].data; 1430 req_b = (struct hns_roce_pf_res_b *)desc[1].data; 1431 1432 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, 1433 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 1434 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 1435 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, 1436 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 1437 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 1438 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, 1439 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 1440 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 1441 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, 1442 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 1443 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 1444 1445 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, 1446 PF_RES_DATA_3_PF_SL_NUM_M, 1447 PF_RES_DATA_3_PF_SL_NUM_S); 1448 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, 1449 PF_RES_DATA_4_PF_SCCC_BT_NUM_M, 1450 PF_RES_DATA_4_PF_SCCC_BT_NUM_S); 1451 1452 return 0; 1453 } 1454 1455 static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev) 1456 { 1457 struct hns_roce_pf_timer_res_a *req_a; 1458 struct hns_roce_cmq_desc desc; 1459 int ret; 1460 1461 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1462 true); 1463 1464 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1465 if (ret) 1466 return ret; 1467 1468 req_a = (struct hns_roce_pf_timer_res_a *)desc.data; 1469 1470 hr_dev->caps.qpc_timer_bt_num = 1471 roce_get_field(req_a->qpc_timer_bt_idx_num, 1472 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M, 1473 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S); 1474 hr_dev->caps.cqc_timer_bt_num = 1475 roce_get_field(req_a->cqc_timer_bt_idx_num, 1476 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M, 1477 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S); 1478 1479 return 0; 1480 } 1481 1482 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) 1483 { 1484 struct hns_roce_cmq_desc desc; 1485 struct hns_roce_vf_switch *swt; 1486 int ret; 1487 1488 swt = (struct hns_roce_vf_switch *)desc.data; 1489 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1490 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1491 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1492 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1493 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1494 if (ret) 1495 return ret; 1496 1497 desc.flag = 1498 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1499 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1500 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1501 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1502 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1503 1504 return hns_roce_cmq_send(hr_dev, &desc, 1); 1505 } 1506 1507 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1508 { 1509 struct hns_roce_cmq_desc desc[2]; 1510 struct hns_roce_vf_res_a *req_a; 1511 struct hns_roce_vf_res_b *req_b; 1512 int i; 1513 1514 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 1515 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 1516 for (i = 0; i < 2; i++) { 1517 hns_roce_cmq_setup_basic_desc(&desc[i], 1518 HNS_ROCE_OPC_ALLOC_VF_RES, false); 1519 1520 if (i == 0) 1521 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1522 else 1523 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1524 } 1525 1526 roce_set_field(req_a->vf_qpc_bt_idx_num, 1527 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 1528 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 1529 roce_set_field(req_a->vf_qpc_bt_idx_num, 1530 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 1531 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM); 1532 1533 roce_set_field(req_a->vf_srqc_bt_idx_num, 1534 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 1535 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 1536 roce_set_field(req_a->vf_srqc_bt_idx_num, 1537 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 1538 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 1539 HNS_ROCE_VF_SRQC_BT_NUM); 1540 1541 roce_set_field(req_a->vf_cqc_bt_idx_num, 1542 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 1543 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 1544 roce_set_field(req_a->vf_cqc_bt_idx_num, 1545 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 1546 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM); 1547 1548 roce_set_field(req_a->vf_mpt_bt_idx_num, 1549 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 1550 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 1551 roce_set_field(req_a->vf_mpt_bt_idx_num, 1552 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 1553 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM); 1554 1555 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M, 1556 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 1557 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M, 1558 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM); 1559 1560 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M, 1561 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 1562 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M, 1563 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM); 1564 1565 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M, 1566 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1567 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M, 1568 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM); 1569 1570 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M, 1571 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1572 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M, 1573 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM); 1574 1575 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M, 1576 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0); 1577 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M, 1578 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S, 1579 HNS_ROCE_VF_SCCC_BT_NUM); 1580 1581 return hns_roce_cmq_send(hr_dev, desc, 2); 1582 } 1583 1584 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1585 { 1586 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1587 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1588 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1589 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1590 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num; 1591 struct hns_roce_cfg_bt_attr *req; 1592 struct hns_roce_cmq_desc desc; 1593 1594 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1595 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1596 memset(req, 0, sizeof(*req)); 1597 1598 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1599 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1600 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1601 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1602 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1603 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1604 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1605 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1606 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1607 1608 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1609 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1610 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1611 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1612 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1613 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1614 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1615 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1616 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1617 1618 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1619 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1620 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1621 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1622 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1623 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1624 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1625 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1626 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1627 1628 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1629 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1630 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1631 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1632 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1633 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1634 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1635 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1636 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1637 1638 roce_set_field(req->vf_sccc_cfg, 1639 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M, 1640 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S, 1641 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1642 roce_set_field(req->vf_sccc_cfg, 1643 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M, 1644 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S, 1645 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1646 roce_set_field(req->vf_sccc_cfg, 1647 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M, 1648 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S, 1649 sccc_hop_num == 1650 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num); 1651 1652 return hns_roce_cmq_send(hr_dev, &desc, 1); 1653 } 1654 1655 static void set_default_caps(struct hns_roce_dev *hr_dev) 1656 { 1657 struct hns_roce_caps *caps = &hr_dev->caps; 1658 1659 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1660 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1661 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1662 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1663 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1664 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1665 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1666 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1667 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1668 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1669 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1670 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1671 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1672 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1673 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1674 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1675 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1676 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1677 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1678 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1679 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1680 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1681 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1682 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1683 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1684 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1685 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1686 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1687 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1688 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1689 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1690 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1691 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1692 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1693 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1694 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1695 caps->reserved_lkey = 0; 1696 caps->reserved_pds = 0; 1697 caps->reserved_mrws = 1; 1698 caps->reserved_uars = 0; 1699 caps->reserved_cqs = 0; 1700 caps->reserved_srqs = 0; 1701 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1702 1703 caps->qpc_ba_pg_sz = 0; 1704 caps->qpc_buf_pg_sz = 0; 1705 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1706 caps->srqc_ba_pg_sz = 0; 1707 caps->srqc_buf_pg_sz = 0; 1708 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1709 caps->cqc_ba_pg_sz = 0; 1710 caps->cqc_buf_pg_sz = 0; 1711 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1712 caps->mpt_ba_pg_sz = 0; 1713 caps->mpt_buf_pg_sz = 0; 1714 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1715 caps->mtt_ba_pg_sz = 0; 1716 caps->mtt_buf_pg_sz = 0; 1717 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1718 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1719 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1720 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1721 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 1722 caps->cqe_buf_pg_sz = 0; 1723 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1724 caps->srqwqe_ba_pg_sz = 0; 1725 caps->srqwqe_buf_pg_sz = 0; 1726 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1727 caps->idx_ba_pg_sz = 0; 1728 caps->idx_buf_pg_sz = 0; 1729 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1730 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1731 1732 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1733 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1734 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1735 HNS_ROCE_CAP_FLAG_RECORD_DB | 1736 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; 1737 1738 caps->pkey_table_len[0] = 1; 1739 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1740 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1741 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1742 caps->local_ca_ack_delay = 0; 1743 caps->max_mtu = IB_MTU_4096; 1744 1745 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1746 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1747 1748 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1749 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1750 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; 1751 1752 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1753 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1754 caps->qpc_timer_ba_pg_sz = 0; 1755 caps->qpc_timer_buf_pg_sz = 0; 1756 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1757 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1758 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1759 caps->cqc_timer_ba_pg_sz = 0; 1760 caps->cqc_timer_buf_pg_sz = 0; 1761 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1762 1763 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ; 1764 caps->sccc_ba_pg_sz = 0; 1765 caps->sccc_buf_pg_sz = 0; 1766 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1767 } 1768 1769 static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num, 1770 int *buf_page_size, int *bt_page_size, u32 hem_type) 1771 { 1772 u64 obj_per_chunk; 1773 int bt_chunk_size = 1 << PAGE_SHIFT; 1774 int buf_chunk_size = 1 << PAGE_SHIFT; 1775 int obj_per_chunk_default = buf_chunk_size / obj_size; 1776 1777 *buf_page_size = 0; 1778 *bt_page_size = 0; 1779 1780 switch (hop_num) { 1781 case 3: 1782 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1783 (bt_chunk_size / BA_BYTE_LEN) * 1784 (bt_chunk_size / BA_BYTE_LEN) * 1785 obj_per_chunk_default; 1786 break; 1787 case 2: 1788 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1789 (bt_chunk_size / BA_BYTE_LEN) * 1790 obj_per_chunk_default; 1791 break; 1792 case 1: 1793 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1794 obj_per_chunk_default; 1795 break; 1796 case HNS_ROCE_HOP_NUM_0: 1797 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1798 break; 1799 default: 1800 pr_err("Table %d not support hop_num = %d!\n", hem_type, 1801 hop_num); 1802 return; 1803 } 1804 1805 if (hem_type >= HEM_TYPE_MTT) 1806 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1807 else 1808 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1809 } 1810 1811 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 1812 { 1813 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 1814 struct hns_roce_caps *caps = &hr_dev->caps; 1815 struct hns_roce_query_pf_caps_a *resp_a; 1816 struct hns_roce_query_pf_caps_b *resp_b; 1817 struct hns_roce_query_pf_caps_c *resp_c; 1818 struct hns_roce_query_pf_caps_d *resp_d; 1819 struct hns_roce_query_pf_caps_e *resp_e; 1820 int ctx_hop_num; 1821 int pbl_hop_num; 1822 int ret; 1823 int i; 1824 1825 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 1826 hns_roce_cmq_setup_basic_desc(&desc[i], 1827 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 1828 true); 1829 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 1830 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1831 else 1832 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1833 } 1834 1835 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 1836 if (ret) 1837 return ret; 1838 1839 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 1840 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 1841 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 1842 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 1843 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 1844 1845 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 1846 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 1847 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 1848 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 1849 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 1850 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 1851 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 1852 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 1853 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 1854 caps->num_other_vectors = resp_a->num_other_vectors; 1855 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 1856 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 1857 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 1858 caps->cq_entry_sz = resp_a->cq_entry_sz; 1859 1860 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 1861 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 1862 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 1863 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 1864 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 1865 caps->idx_entry_sz = resp_b->idx_entry_sz; 1866 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz; 1867 caps->max_mtu = resp_b->max_mtu; 1868 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz); 1869 caps->min_cqes = resp_b->min_cqes; 1870 caps->min_wqes = resp_b->min_wqes; 1871 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 1872 caps->pkey_table_len[0] = resp_b->pkey_table_len; 1873 caps->phy_num_uars = resp_b->phy_num_uars; 1874 ctx_hop_num = resp_b->ctx_hop_num; 1875 pbl_hop_num = resp_b->pbl_hop_num; 1876 1877 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 1878 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 1879 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 1880 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 1881 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 1882 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 1883 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 1884 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 1885 1886 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 1887 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 1888 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 1889 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 1890 V2_QUERY_PF_CAPS_C_MAX_GID_M, 1891 V2_QUERY_PF_CAPS_C_MAX_GID_S); 1892 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 1893 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 1894 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 1895 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 1896 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 1897 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 1898 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 1899 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 1900 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 1901 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 1902 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 1903 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 1904 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 1905 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 1906 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 1907 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 1908 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 1909 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 1910 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 1911 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 1912 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 1913 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 1914 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 1915 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 1916 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 1917 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 1918 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 1919 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1920 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 1921 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 1922 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1923 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 1924 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 1925 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 1926 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 1927 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 1928 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 1929 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 1930 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 1931 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 1932 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 1933 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 1934 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 1935 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 1936 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 1937 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1938 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 1939 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 1940 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1941 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 1942 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 1943 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 1944 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 1945 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 1946 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 1947 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 1948 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 1949 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 1950 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 1951 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 1952 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 1953 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 1954 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 1955 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 1956 1957 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1958 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1959 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1960 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1961 caps->mtt_ba_pg_sz = 0; 1962 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1963 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1964 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1965 1966 caps->qpc_hop_num = ctx_hop_num; 1967 caps->srqc_hop_num = ctx_hop_num; 1968 caps->cqc_hop_num = ctx_hop_num; 1969 caps->mpt_hop_num = ctx_hop_num; 1970 caps->mtt_hop_num = pbl_hop_num; 1971 caps->cqe_hop_num = pbl_hop_num; 1972 caps->srqwqe_hop_num = pbl_hop_num; 1973 caps->idx_hop_num = pbl_hop_num; 1974 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1975 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 1976 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 1977 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1978 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 1979 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 1980 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1981 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 1982 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 1983 1984 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num, 1985 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 1986 HEM_TYPE_QPC); 1987 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1988 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1989 HEM_TYPE_MTPT); 1990 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 1991 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 1992 HEM_TYPE_CQC); 1993 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num, 1994 caps->srqc_bt_num, &caps->srqc_buf_pg_sz, 1995 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC); 1996 1997 caps->sccc_hop_num = ctx_hop_num; 1998 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1999 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2000 2001 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz, 2002 caps->sccc_hop_num, caps->sccc_bt_num, 2003 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz, 2004 HEM_TYPE_SCCC); 2005 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, 2006 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, 2007 &caps->cqc_timer_buf_pg_sz, 2008 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); 2009 2010 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num, 2011 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2012 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2013 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2014 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2015 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num, 2016 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2017 2018 return 0; 2019 } 2020 2021 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2022 { 2023 struct hns_roce_caps *caps = &hr_dev->caps; 2024 int ret; 2025 2026 ret = hns_roce_cmq_query_hw_info(hr_dev); 2027 if (ret) { 2028 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n", 2029 ret); 2030 return ret; 2031 } 2032 2033 ret = hns_roce_query_fw_ver(hr_dev); 2034 if (ret) { 2035 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 2036 ret); 2037 return ret; 2038 } 2039 2040 ret = hns_roce_config_global_param(hr_dev); 2041 if (ret) { 2042 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 2043 ret); 2044 return ret; 2045 } 2046 2047 /* Get pf resource owned by every pf */ 2048 ret = hns_roce_query_pf_resource(hr_dev); 2049 if (ret) { 2050 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 2051 ret); 2052 return ret; 2053 } 2054 2055 ret = hns_roce_query_pf_timer_resource(hr_dev); 2056 if (ret) { 2057 dev_err(hr_dev->dev, 2058 "failed to query pf timer resource, ret = %d.\n", ret); 2059 return ret; 2060 } 2061 2062 ret = hns_roce_set_vf_switch_param(hr_dev, 0); 2063 if (ret) { 2064 dev_err(hr_dev->dev, 2065 "failed to set function switch param, ret = %d.\n", 2066 ret); 2067 return ret; 2068 } 2069 2070 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2071 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2072 2073 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2074 caps->pbl_buf_pg_sz = 0; 2075 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2076 caps->eqe_ba_pg_sz = 0; 2077 caps->eqe_buf_pg_sz = 0; 2078 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2079 caps->tsq_buf_pg_sz = 0; 2080 2081 ret = hns_roce_query_pf_caps(hr_dev); 2082 if (ret) 2083 set_default_caps(hr_dev); 2084 2085 ret = hns_roce_alloc_vf_resource(hr_dev); 2086 if (ret) { 2087 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 2088 ret); 2089 return ret; 2090 } 2091 2092 ret = hns_roce_v2_set_bt(hr_dev); 2093 if (ret) 2094 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 2095 ret); 2096 2097 return ret; 2098 } 2099 2100 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, 2101 enum hns_roce_link_table_type type) 2102 { 2103 struct hns_roce_cmq_desc desc[2]; 2104 struct hns_roce_cfg_llm_a *req_a = 2105 (struct hns_roce_cfg_llm_a *)desc[0].data; 2106 struct hns_roce_cfg_llm_b *req_b = 2107 (struct hns_roce_cfg_llm_b *)desc[1].data; 2108 struct hns_roce_v2_priv *priv = hr_dev->priv; 2109 struct hns_roce_link_table *link_tbl; 2110 struct hns_roce_link_table_entry *entry; 2111 enum hns_roce_opcode_type opcode; 2112 u32 page_num; 2113 int i; 2114 2115 switch (type) { 2116 case TSQ_LINK_TABLE: 2117 link_tbl = &priv->tsq; 2118 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2119 break; 2120 case TPQ_LINK_TABLE: 2121 link_tbl = &priv->tpq; 2122 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; 2123 break; 2124 default: 2125 return -EINVAL; 2126 } 2127 2128 page_num = link_tbl->npages; 2129 entry = link_tbl->table.buf; 2130 2131 for (i = 0; i < 2; i++) { 2132 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false); 2133 2134 if (i == 0) 2135 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2136 else 2137 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2138 } 2139 2140 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff); 2141 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32); 2142 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M, 2143 CFG_LLM_QUE_DEPTH_S, link_tbl->npages); 2144 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M, 2145 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz); 2146 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M, 2147 CFG_LLM_INIT_EN_S, 1); 2148 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0); 2149 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr); 2150 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S, 2151 0); 2152 2153 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0); 2154 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M, 2155 CFG_LLM_TAIL_BA_H_S, 2156 entry[page_num - 1].blk_ba1_nxt_ptr & 2157 HNS_ROCE_LINK_TABLE_BA1_M); 2158 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S, 2159 (entry[page_num - 2].blk_ba1_nxt_ptr & 2160 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> 2161 HNS_ROCE_LINK_TABLE_NXT_PTR_S); 2162 2163 return hns_roce_cmq_send(hr_dev, desc, 2); 2164 } 2165 2166 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, 2167 enum hns_roce_link_table_type type) 2168 { 2169 struct hns_roce_v2_priv *priv = hr_dev->priv; 2170 struct hns_roce_link_table *link_tbl; 2171 struct hns_roce_link_table_entry *entry; 2172 struct device *dev = hr_dev->dev; 2173 u32 buf_chk_sz; 2174 dma_addr_t t; 2175 int func_num = 1; 2176 int pg_num_a; 2177 int pg_num_b; 2178 int pg_num; 2179 int size; 2180 int i; 2181 2182 switch (type) { 2183 case TSQ_LINK_TABLE: 2184 link_tbl = &priv->tsq; 2185 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); 2186 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; 2187 pg_num_b = hr_dev->caps.sl_num * 4 + 2; 2188 break; 2189 case TPQ_LINK_TABLE: 2190 link_tbl = &priv->tpq; 2191 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); 2192 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; 2193 pg_num_b = 2 * 4 * func_num + 2; 2194 break; 2195 default: 2196 return -EINVAL; 2197 } 2198 2199 pg_num = max(pg_num_a, pg_num_b); 2200 size = pg_num * sizeof(struct hns_roce_link_table_entry); 2201 2202 link_tbl->table.buf = dma_alloc_coherent(dev, size, 2203 &link_tbl->table.map, 2204 GFP_KERNEL); 2205 if (!link_tbl->table.buf) 2206 goto out; 2207 2208 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), 2209 GFP_KERNEL); 2210 if (!link_tbl->pg_list) 2211 goto err_kcalloc_failed; 2212 2213 entry = link_tbl->table.buf; 2214 for (i = 0; i < pg_num; ++i) { 2215 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, 2216 &t, GFP_KERNEL); 2217 if (!link_tbl->pg_list[i].buf) 2218 goto err_alloc_buf_failed; 2219 2220 link_tbl->pg_list[i].map = t; 2221 2222 entry[i].blk_ba0 = (u32)(t >> 12); 2223 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44); 2224 2225 if (i < (pg_num - 1)) 2226 entry[i].blk_ba1_nxt_ptr |= 2227 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S; 2228 2229 } 2230 link_tbl->npages = pg_num; 2231 link_tbl->pg_sz = buf_chk_sz; 2232 2233 return hns_roce_config_link_table(hr_dev, type); 2234 2235 err_alloc_buf_failed: 2236 for (i -= 1; i >= 0; i--) 2237 dma_free_coherent(dev, buf_chk_sz, 2238 link_tbl->pg_list[i].buf, 2239 link_tbl->pg_list[i].map); 2240 kfree(link_tbl->pg_list); 2241 2242 err_kcalloc_failed: 2243 dma_free_coherent(dev, size, link_tbl->table.buf, 2244 link_tbl->table.map); 2245 2246 out: 2247 return -ENOMEM; 2248 } 2249 2250 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, 2251 struct hns_roce_link_table *link_tbl) 2252 { 2253 struct device *dev = hr_dev->dev; 2254 int size; 2255 int i; 2256 2257 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); 2258 2259 for (i = 0; i < link_tbl->npages; ++i) 2260 if (link_tbl->pg_list[i].buf) 2261 dma_free_coherent(dev, link_tbl->pg_sz, 2262 link_tbl->pg_list[i].buf, 2263 link_tbl->pg_list[i].map); 2264 kfree(link_tbl->pg_list); 2265 2266 dma_free_coherent(dev, size, link_tbl->table.buf, 2267 link_tbl->table.map); 2268 } 2269 2270 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2271 { 2272 struct hns_roce_v2_priv *priv = hr_dev->priv; 2273 int qpc_count, cqc_count; 2274 int ret, i; 2275 2276 /* TSQ includes SQ doorbell and ack doorbell */ 2277 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); 2278 if (ret) { 2279 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret); 2280 return ret; 2281 } 2282 2283 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); 2284 if (ret) { 2285 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret); 2286 goto err_tpq_init_failed; 2287 } 2288 2289 /* Alloc memory for QPC Timer buffer space chunk */ 2290 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2291 qpc_count++) { 2292 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2293 qpc_count); 2294 if (ret) { 2295 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2296 goto err_qpc_timer_failed; 2297 } 2298 } 2299 2300 /* Alloc memory for CQC Timer buffer space chunk */ 2301 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2302 cqc_count++) { 2303 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2304 cqc_count); 2305 if (ret) { 2306 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2307 goto err_cqc_timer_failed; 2308 } 2309 } 2310 2311 return 0; 2312 2313 err_cqc_timer_failed: 2314 for (i = 0; i < cqc_count; i++) 2315 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2316 2317 err_qpc_timer_failed: 2318 for (i = 0; i < qpc_count; i++) 2319 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2320 2321 hns_roce_free_link_table(hr_dev, &priv->tpq); 2322 2323 err_tpq_init_failed: 2324 hns_roce_free_link_table(hr_dev, &priv->tsq); 2325 2326 return ret; 2327 } 2328 2329 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2330 { 2331 struct hns_roce_v2_priv *priv = hr_dev->priv; 2332 2333 hns_roce_function_clear(hr_dev); 2334 2335 hns_roce_free_link_table(hr_dev, &priv->tpq); 2336 hns_roce_free_link_table(hr_dev, &priv->tsq); 2337 } 2338 2339 static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev) 2340 { 2341 struct hns_roce_cmq_desc desc; 2342 struct hns_roce_mbox_status *mb_st = 2343 (struct hns_roce_mbox_status *)desc.data; 2344 enum hns_roce_cmd_return_status status; 2345 2346 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true); 2347 2348 status = hns_roce_cmq_send(hr_dev, &desc, 1); 2349 if (status) 2350 return status; 2351 2352 return le32_to_cpu(mb_st->mb_status_hw_run); 2353 } 2354 2355 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 2356 { 2357 u32 status = hns_roce_query_mbox_status(hr_dev); 2358 2359 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 2360 } 2361 2362 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 2363 { 2364 u32 status = hns_roce_query_mbox_status(hr_dev); 2365 2366 return status & HNS_ROCE_HW_MB_STATUS_MASK; 2367 } 2368 2369 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2370 u64 out_param, u32 in_modifier, u8 op_modifier, 2371 u16 op, u16 token, int event) 2372 { 2373 struct hns_roce_cmq_desc desc; 2374 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2375 2376 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2377 2378 mb->in_param_l = cpu_to_le32(in_param); 2379 mb->in_param_h = cpu_to_le32(in_param >> 32); 2380 mb->out_param_l = cpu_to_le32(out_param); 2381 mb->out_param_h = cpu_to_le32(out_param >> 32); 2382 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2383 mb->token_event_en = cpu_to_le32(event << 16 | token); 2384 2385 return hns_roce_cmq_send(hr_dev, &desc, 1); 2386 } 2387 2388 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2389 u64 out_param, u32 in_modifier, u8 op_modifier, 2390 u16 op, u16 token, int event) 2391 { 2392 struct device *dev = hr_dev->dev; 2393 unsigned long end; 2394 int ret; 2395 2396 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 2397 while (hns_roce_v2_cmd_pending(hr_dev)) { 2398 if (time_after(jiffies, end)) { 2399 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 2400 (int)end); 2401 return -EAGAIN; 2402 } 2403 cond_resched(); 2404 } 2405 2406 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2407 op_modifier, op, token, event); 2408 if (ret) 2409 dev_err(dev, "Post mailbox fail(%d)\n", ret); 2410 2411 return ret; 2412 } 2413 2414 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 2415 unsigned long timeout) 2416 { 2417 struct device *dev = hr_dev->dev; 2418 unsigned long end; 2419 u32 status; 2420 2421 end = msecs_to_jiffies(timeout) + jiffies; 2422 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 2423 cond_resched(); 2424 2425 if (hns_roce_v2_cmd_pending(hr_dev)) { 2426 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 2427 return -ETIMEDOUT; 2428 } 2429 2430 status = hns_roce_v2_cmd_complete(hr_dev); 2431 if (status != 0x1) { 2432 if (status == CMD_RST_PRC_EBUSY) 2433 return status; 2434 2435 dev_err(dev, "mailbox status 0x%x!\n", status); 2436 return -EBUSY; 2437 } 2438 2439 return 0; 2440 } 2441 2442 static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev, 2443 int gid_index, const union ib_gid *gid, 2444 enum hns_roce_sgid_type sgid_type) 2445 { 2446 struct hns_roce_cmq_desc desc; 2447 struct hns_roce_cfg_sgid_tb *sgid_tb = 2448 (struct hns_roce_cfg_sgid_tb *)desc.data; 2449 u32 *p; 2450 2451 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2452 2453 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2454 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2455 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2456 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2457 2458 p = (u32 *)&gid->raw[0]; 2459 sgid_tb->vf_sgid_l = cpu_to_le32(*p); 2460 2461 p = (u32 *)&gid->raw[4]; 2462 sgid_tb->vf_sgid_ml = cpu_to_le32(*p); 2463 2464 p = (u32 *)&gid->raw[8]; 2465 sgid_tb->vf_sgid_mh = cpu_to_le32(*p); 2466 2467 p = (u32 *)&gid->raw[0xc]; 2468 sgid_tb->vf_sgid_h = cpu_to_le32(*p); 2469 2470 return hns_roce_cmq_send(hr_dev, &desc, 1); 2471 } 2472 2473 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 2474 int gid_index, const union ib_gid *gid, 2475 const struct ib_gid_attr *attr) 2476 { 2477 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2478 int ret; 2479 2480 if (!gid || !attr) 2481 return -EINVAL; 2482 2483 if (attr->gid_type == IB_GID_TYPE_ROCE) 2484 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2485 2486 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2487 if (ipv6_addr_v4mapped((void *)gid)) 2488 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2489 else 2490 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2491 } 2492 2493 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2494 if (ret) 2495 ibdev_err(&hr_dev->ib_dev, 2496 "failed to configure sgid table, ret = %d!\n", 2497 ret); 2498 2499 return ret; 2500 } 2501 2502 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2503 u8 *addr) 2504 { 2505 struct hns_roce_cmq_desc desc; 2506 struct hns_roce_cfg_smac_tb *smac_tb = 2507 (struct hns_roce_cfg_smac_tb *)desc.data; 2508 u16 reg_smac_h; 2509 u32 reg_smac_l; 2510 2511 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 2512 2513 reg_smac_l = *(u32 *)(&addr[0]); 2514 reg_smac_h = *(u16 *)(&addr[4]); 2515 2516 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 2517 CFG_SMAC_TB_IDX_S, phy_port); 2518 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 2519 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 2520 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 2521 2522 return hns_roce_cmq_send(hr_dev, &desc, 1); 2523 } 2524 2525 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 2526 struct hns_roce_v2_mpt_entry *mpt_entry, 2527 struct hns_roce_mr *mr) 2528 { 2529 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 2530 struct ib_device *ibdev = &hr_dev->ib_dev; 2531 dma_addr_t pbl_ba; 2532 int i, count; 2533 2534 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 2535 ARRAY_SIZE(pages), &pbl_ba); 2536 if (count < 1) { 2537 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 2538 count); 2539 return -ENOBUFS; 2540 } 2541 2542 /* Aligned to the hardware address access unit */ 2543 for (i = 0; i < count; i++) 2544 pages[i] >>= 6; 2545 2546 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2547 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 2548 roce_set_field(mpt_entry->byte_48_mode_ba, 2549 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 2550 upper_32_bits(pbl_ba >> 3)); 2551 2552 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 2553 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 2554 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 2555 2556 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 2557 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 2558 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 2559 roce_set_field(mpt_entry->byte_64_buf_pa1, 2560 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2561 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2562 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2563 2564 return 0; 2565 } 2566 2567 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 2568 void *mb_buf, struct hns_roce_mr *mr, 2569 unsigned long mtpt_idx) 2570 { 2571 struct hns_roce_v2_mpt_entry *mpt_entry; 2572 int ret; 2573 2574 mpt_entry = mb_buf; 2575 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2576 2577 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2578 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2579 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2580 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 2581 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 2582 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2583 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2584 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2585 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2586 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2587 V2_MPT_BYTE_4_PD_S, mr->pd); 2588 2589 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 2590 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0); 2591 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2592 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 2593 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 2594 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 2595 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2596 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2597 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 2598 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2599 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 2600 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2601 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 2602 2603 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 2604 mr->type == MR_TYPE_MR ? 0 : 1); 2605 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, 2606 1); 2607 2608 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 2609 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 2610 mpt_entry->lkey = cpu_to_le32(mr->key); 2611 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 2612 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 2613 2614 if (mr->type == MR_TYPE_DMA) 2615 return 0; 2616 2617 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2618 2619 return ret; 2620 } 2621 2622 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 2623 struct hns_roce_mr *mr, int flags, 2624 u32 pdn, int mr_access_flags, u64 iova, 2625 u64 size, void *mb_buf) 2626 { 2627 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 2628 int ret = 0; 2629 2630 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2631 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2632 2633 if (flags & IB_MR_REREG_PD) { 2634 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2635 V2_MPT_BYTE_4_PD_S, pdn); 2636 mr->pd = pdn; 2637 } 2638 2639 if (flags & IB_MR_REREG_ACCESS) { 2640 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2641 V2_MPT_BYTE_8_BIND_EN_S, 2642 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 2643 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2644 V2_MPT_BYTE_8_ATOMIC_EN_S, 2645 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2646 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2647 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 2648 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2649 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 2650 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2651 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 2652 } 2653 2654 if (flags & IB_MR_REREG_TRANS) { 2655 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 2656 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 2657 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 2658 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 2659 2660 mr->iova = iova; 2661 mr->size = size; 2662 2663 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2664 } 2665 2666 return ret; 2667 } 2668 2669 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 2670 void *mb_buf, struct hns_roce_mr *mr) 2671 { 2672 struct ib_device *ibdev = &hr_dev->ib_dev; 2673 struct hns_roce_v2_mpt_entry *mpt_entry; 2674 dma_addr_t pbl_ba = 0; 2675 2676 mpt_entry = mb_buf; 2677 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2678 2679 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 2680 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 2681 return -ENOBUFS; 2682 } 2683 2684 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2685 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2686 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2687 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 2688 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2689 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2690 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2691 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2692 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2693 V2_MPT_BYTE_4_PD_S, mr->pd); 2694 2695 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 2696 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2697 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2698 2699 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 2700 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2701 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 2702 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2703 2704 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2705 2706 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 2707 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 2708 V2_MPT_BYTE_48_PBL_BA_H_S, 2709 upper_32_bits(pbl_ba >> 3)); 2710 2711 roce_set_field(mpt_entry->byte_64_buf_pa1, 2712 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2713 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2714 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2715 2716 return 0; 2717 } 2718 2719 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 2720 { 2721 struct hns_roce_v2_mpt_entry *mpt_entry; 2722 2723 mpt_entry = mb_buf; 2724 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2725 2726 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2727 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2728 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2729 V2_MPT_BYTE_4_PD_S, mw->pdn); 2730 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2731 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 2732 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 2733 mw->pbl_hop_num); 2734 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2735 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2736 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2737 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 2738 2739 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2740 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2741 2742 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2743 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 2744 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2745 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 2746 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 2747 2748 roce_set_field(mpt_entry->byte_64_buf_pa1, 2749 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2750 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2751 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 2752 2753 mpt_entry->lkey = cpu_to_le32(mw->rkey); 2754 2755 return 0; 2756 } 2757 2758 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2759 { 2760 return hns_roce_buf_offset(hr_cq->mtr.kmem, 2761 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 2762 } 2763 2764 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2765 { 2766 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 2767 2768 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 2769 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 2770 !!(n & hr_cq->cq_depth)) ? cqe : NULL; 2771 } 2772 2773 static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci) 2774 { 2775 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M; 2776 } 2777 2778 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2779 struct hns_roce_srq *srq) 2780 { 2781 struct hns_roce_v2_cqe *cqe, *dest; 2782 u32 prod_index; 2783 int nfreed = 0; 2784 int wqe_index; 2785 u8 owner_bit; 2786 2787 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 2788 ++prod_index) { 2789 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 2790 break; 2791 } 2792 2793 /* 2794 * Now backwards through the CQ, removing CQ entries 2795 * that match our QP by overwriting them with next entries. 2796 */ 2797 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 2798 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 2799 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 2800 V2_CQE_BYTE_16_LCL_QPN_S) & 2801 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 2802 if (srq && 2803 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) { 2804 wqe_index = roce_get_field(cqe->byte_4, 2805 V2_CQE_BYTE_4_WQE_INDX_M, 2806 V2_CQE_BYTE_4_WQE_INDX_S); 2807 hns_roce_free_srq_wqe(srq, wqe_index); 2808 } 2809 ++nfreed; 2810 } else if (nfreed) { 2811 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 2812 hr_cq->ib_cq.cqe); 2813 owner_bit = roce_get_bit(dest->byte_4, 2814 V2_CQE_BYTE_4_OWNER_S); 2815 memcpy(dest, cqe, sizeof(*cqe)); 2816 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 2817 owner_bit); 2818 } 2819 } 2820 2821 if (nfreed) { 2822 hr_cq->cons_index += nfreed; 2823 /* 2824 * Make sure update of buffer contents is done before 2825 * updating consumer index. 2826 */ 2827 wmb(); 2828 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 2829 } 2830 } 2831 2832 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2833 struct hns_roce_srq *srq) 2834 { 2835 spin_lock_irq(&hr_cq->lock); 2836 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 2837 spin_unlock_irq(&hr_cq->lock); 2838 } 2839 2840 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 2841 struct hns_roce_cq *hr_cq, void *mb_buf, 2842 u64 *mtts, dma_addr_t dma_handle) 2843 { 2844 struct hns_roce_v2_cq_context *cq_context; 2845 2846 cq_context = mb_buf; 2847 memset(cq_context, 0, sizeof(*cq_context)); 2848 2849 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 2850 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 2851 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 2852 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 2853 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 2854 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); 2855 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 2856 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); 2857 2858 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 2859 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 2860 2861 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 2862 2863 roce_set_field(cq_context->byte_16_hop_addr, 2864 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 2865 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 2866 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 2867 roce_set_field(cq_context->byte_16_hop_addr, 2868 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 2869 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 2870 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 2871 2872 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 2873 roce_set_field(cq_context->byte_24_pgsz_addr, 2874 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 2875 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 2876 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 2877 roce_set_field(cq_context->byte_24_pgsz_addr, 2878 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 2879 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 2880 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 2881 roce_set_field(cq_context->byte_24_pgsz_addr, 2882 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 2883 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 2884 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 2885 2886 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); 2887 2888 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 2889 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 2890 2891 roce_set_bit(cq_context->byte_44_db_record, 2892 V2_CQC_BYTE_44_DB_RECORD_EN_S, 2893 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0); 2894 2895 roce_set_field(cq_context->byte_44_db_record, 2896 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 2897 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 2898 ((u32)hr_cq->db.dma) >> 1); 2899 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); 2900 2901 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2902 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 2903 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 2904 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 2905 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2906 V2_CQC_BYTE_56_CQ_PERIOD_M, 2907 V2_CQC_BYTE_56_CQ_PERIOD_S, 2908 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 2909 } 2910 2911 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 2912 enum ib_cq_notify_flags flags) 2913 { 2914 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 2915 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 2916 u32 notification_flag; 2917 __le32 doorbell[2]; 2918 2919 doorbell[0] = 0; 2920 doorbell[1] = 0; 2921 2922 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 2923 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 2924 /* 2925 * flags = 0; Notification Flag = 1, next 2926 * flags = 1; Notification Flag = 0, solocited 2927 */ 2928 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 2929 hr_cq->cqn); 2930 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 2931 HNS_ROCE_V2_CQ_DB_NTR); 2932 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 2933 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index); 2934 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 2935 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 2936 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 2937 notification_flag); 2938 2939 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l); 2940 2941 return 0; 2942 } 2943 2944 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 2945 struct hns_roce_qp **cur_qp, 2946 struct ib_wc *wc) 2947 { 2948 struct hns_roce_rinl_sge *sge_list; 2949 u32 wr_num, wr_cnt, sge_num; 2950 u32 sge_cnt, data_len, size; 2951 void *wqe_buf; 2952 2953 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 2954 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 2955 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 2956 2957 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 2958 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 2959 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt); 2960 data_len = wc->byte_len; 2961 2962 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 2963 size = min(sge_list[sge_cnt].len, data_len); 2964 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 2965 2966 data_len -= size; 2967 wqe_buf += size; 2968 } 2969 2970 if (unlikely(data_len)) { 2971 wc->status = IB_WC_LOC_LEN_ERR; 2972 return -EAGAIN; 2973 } 2974 2975 return 0; 2976 } 2977 2978 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 2979 int num_entries, struct ib_wc *wc) 2980 { 2981 unsigned int left; 2982 int npolled = 0; 2983 2984 left = wq->head - wq->tail; 2985 if (left == 0) 2986 return 0; 2987 2988 left = min_t(unsigned int, (unsigned int)num_entries, left); 2989 while (npolled < left) { 2990 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 2991 wc->status = IB_WC_WR_FLUSH_ERR; 2992 wc->vendor_err = 0; 2993 wc->qp = &hr_qp->ibqp; 2994 2995 wq->tail++; 2996 wc++; 2997 npolled++; 2998 } 2999 3000 return npolled; 3001 } 3002 3003 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3004 struct ib_wc *wc) 3005 { 3006 struct hns_roce_qp *hr_qp; 3007 int npolled = 0; 3008 3009 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3010 npolled += sw_comp(hr_qp, &hr_qp->sq, 3011 num_entries - npolled, wc + npolled); 3012 if (npolled >= num_entries) 3013 goto out; 3014 } 3015 3016 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3017 npolled += sw_comp(hr_qp, &hr_qp->rq, 3018 num_entries - npolled, wc + npolled); 3019 if (npolled >= num_entries) 3020 goto out; 3021 } 3022 3023 out: 3024 return npolled; 3025 } 3026 3027 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3028 struct hns_roce_v2_cqe *cqe, struct ib_wc *wc) 3029 { 3030 static const struct { 3031 u32 cqe_status; 3032 enum ib_wc_status wc_status; 3033 } map[] = { 3034 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3035 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3036 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3037 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3038 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3039 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3040 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3041 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3042 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3043 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3044 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3045 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3046 IB_WC_RETRY_EXC_ERR }, 3047 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3048 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3049 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3050 }; 3051 3052 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 3053 V2_CQE_BYTE_4_STATUS_S); 3054 int i; 3055 3056 wc->status = IB_WC_GENERAL_ERR; 3057 for (i = 0; i < ARRAY_SIZE(map); i++) 3058 if (cqe_status == map[i].cqe_status) { 3059 wc->status = map[i].wc_status; 3060 break; 3061 } 3062 3063 if (likely(wc->status == IB_WC_SUCCESS || 3064 wc->status == IB_WC_WR_FLUSH_ERR)) 3065 return; 3066 3067 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3068 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3069 sizeof(*cqe), false); 3070 3071 /* 3072 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3073 * the standard protocol, the driver must ignore it and needn't to set 3074 * the QP to an error state. 3075 */ 3076 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3077 return; 3078 3079 /* 3080 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets 3081 * into errored mode. Hence, as a workaround to this hardware 3082 * limitation, driver needs to assist in flushing. But the flushing 3083 * operation uses mailbox to convey the QP state to the hardware and 3084 * which can sleep due to the mutex protection around the mailbox calls. 3085 * Hence, use the deferred flush for now. Once wc error detected, the 3086 * flushing operation is needed. 3087 */ 3088 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 3089 init_flush_work(hr_dev, qp); 3090 } 3091 3092 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3093 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3094 { 3095 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3096 struct hns_roce_srq *srq = NULL; 3097 struct hns_roce_v2_cqe *cqe; 3098 struct hns_roce_qp *hr_qp; 3099 struct hns_roce_wq *wq; 3100 int is_send; 3101 u16 wqe_ctr; 3102 u32 opcode; 3103 int qpn; 3104 int ret; 3105 3106 /* Find cqe according to consumer index */ 3107 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3108 if (!cqe) 3109 return -EAGAIN; 3110 3111 ++hr_cq->cons_index; 3112 /* Memory barrier */ 3113 rmb(); 3114 3115 /* 0->SQ, 1->RQ */ 3116 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 3117 3118 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 3119 V2_CQE_BYTE_16_LCL_QPN_S); 3120 3121 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 3122 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3123 if (unlikely(!hr_qp)) { 3124 ibdev_err(&hr_dev->ib_dev, 3125 "CQ %06lx with entry for unknown QPN %06x\n", 3126 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK); 3127 return -EINVAL; 3128 } 3129 *cur_qp = hr_qp; 3130 } 3131 3132 wc->qp = &(*cur_qp)->ibqp; 3133 wc->vendor_err = 0; 3134 3135 if (is_send) { 3136 wq = &(*cur_qp)->sq; 3137 if ((*cur_qp)->sq_signal_bits) { 3138 /* 3139 * If sg_signal_bit is 1, 3140 * firstly tail pointer updated to wqe 3141 * which current cqe correspond to 3142 */ 3143 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3144 V2_CQE_BYTE_4_WQE_INDX_M, 3145 V2_CQE_BYTE_4_WQE_INDX_S); 3146 wq->tail += (wqe_ctr - (u16)wq->tail) & 3147 (wq->wqe_cnt - 1); 3148 } 3149 3150 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3151 ++wq->tail; 3152 } else if ((*cur_qp)->ibqp.srq) { 3153 srq = to_hr_srq((*cur_qp)->ibqp.srq); 3154 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3155 V2_CQE_BYTE_4_WQE_INDX_M, 3156 V2_CQE_BYTE_4_WQE_INDX_S); 3157 wc->wr_id = srq->wrid[wqe_ctr]; 3158 hns_roce_free_srq_wqe(srq, wqe_ctr); 3159 } else { 3160 /* Update tail pointer, record wr_id */ 3161 wq = &(*cur_qp)->rq; 3162 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3163 ++wq->tail; 3164 } 3165 3166 get_cqe_status(hr_dev, *cur_qp, cqe, wc); 3167 if (unlikely(wc->status != IB_WC_SUCCESS)) 3168 return 0; 3169 3170 if (is_send) { 3171 wc->wc_flags = 0; 3172 /* SQ corresponding to CQE */ 3173 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3174 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 3175 case HNS_ROCE_V2_WQE_OP_SEND: 3176 wc->opcode = IB_WC_SEND; 3177 break; 3178 case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV: 3179 wc->opcode = IB_WC_SEND; 3180 break; 3181 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3182 wc->opcode = IB_WC_SEND; 3183 wc->wc_flags |= IB_WC_WITH_IMM; 3184 break; 3185 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3186 wc->opcode = IB_WC_RDMA_READ; 3187 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3188 break; 3189 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE: 3190 wc->opcode = IB_WC_RDMA_WRITE; 3191 break; 3192 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3193 wc->opcode = IB_WC_RDMA_WRITE; 3194 wc->wc_flags |= IB_WC_WITH_IMM; 3195 break; 3196 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3197 wc->opcode = IB_WC_LOCAL_INV; 3198 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3199 break; 3200 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3201 wc->opcode = IB_WC_COMP_SWAP; 3202 wc->byte_len = 8; 3203 break; 3204 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3205 wc->opcode = IB_WC_FETCH_ADD; 3206 wc->byte_len = 8; 3207 break; 3208 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3209 wc->opcode = IB_WC_MASKED_COMP_SWAP; 3210 wc->byte_len = 8; 3211 break; 3212 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3213 wc->opcode = IB_WC_MASKED_FETCH_ADD; 3214 wc->byte_len = 8; 3215 break; 3216 case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR: 3217 wc->opcode = IB_WC_REG_MR; 3218 break; 3219 case HNS_ROCE_V2_WQE_OP_BIND_MW: 3220 wc->opcode = IB_WC_REG_MR; 3221 break; 3222 default: 3223 wc->status = IB_WC_GENERAL_ERR; 3224 break; 3225 } 3226 } else { 3227 /* RQ correspond to CQE */ 3228 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3229 3230 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3231 V2_CQE_BYTE_4_OPCODE_S); 3232 switch (opcode & 0x1f) { 3233 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3234 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3235 wc->wc_flags = IB_WC_WITH_IMM; 3236 wc->ex.imm_data = 3237 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3238 break; 3239 case HNS_ROCE_V2_OPCODE_SEND: 3240 wc->opcode = IB_WC_RECV; 3241 wc->wc_flags = 0; 3242 break; 3243 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3244 wc->opcode = IB_WC_RECV; 3245 wc->wc_flags = IB_WC_WITH_IMM; 3246 wc->ex.imm_data = 3247 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3248 break; 3249 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3250 wc->opcode = IB_WC_RECV; 3251 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3252 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3253 break; 3254 default: 3255 wc->status = IB_WC_GENERAL_ERR; 3256 break; 3257 } 3258 3259 if ((wc->qp->qp_type == IB_QPT_RC || 3260 wc->qp->qp_type == IB_QPT_UC) && 3261 (opcode == HNS_ROCE_V2_OPCODE_SEND || 3262 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3263 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3264 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 3265 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 3266 if (unlikely(ret)) 3267 return -EAGAIN; 3268 } 3269 3270 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 3271 V2_CQE_BYTE_32_SL_S); 3272 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 3273 V2_CQE_BYTE_32_RMT_QPN_M, 3274 V2_CQE_BYTE_32_RMT_QPN_S); 3275 wc->slid = 0; 3276 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 3277 V2_CQE_BYTE_32_GRH_S) ? 3278 IB_WC_GRH : 0); 3279 wc->port_num = roce_get_field(cqe->byte_32, 3280 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 3281 wc->pkey_index = 0; 3282 3283 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) { 3284 wc->vlan_id = (u16)roce_get_field(cqe->byte_28, 3285 V2_CQE_BYTE_28_VID_M, 3286 V2_CQE_BYTE_28_VID_S); 3287 wc->wc_flags |= IB_WC_WITH_VLAN; 3288 } else { 3289 wc->vlan_id = 0xffff; 3290 } 3291 3292 wc->network_hdr_type = roce_get_field(cqe->byte_28, 3293 V2_CQE_BYTE_28_PORT_TYPE_M, 3294 V2_CQE_BYTE_28_PORT_TYPE_S); 3295 } 3296 3297 return 0; 3298 } 3299 3300 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3301 struct ib_wc *wc) 3302 { 3303 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3304 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3305 struct hns_roce_qp *cur_qp = NULL; 3306 unsigned long flags; 3307 int npolled; 3308 3309 spin_lock_irqsave(&hr_cq->lock, flags); 3310 3311 /* 3312 * When the device starts to reset, the state is RST_DOWN. At this time, 3313 * there may still be some valid CQEs in the hardware that are not 3314 * polled. Therefore, it is not allowed to switch to the software mode 3315 * immediately. When the state changes to UNINIT, CQE no longer exists 3316 * in the hardware, and then switch to software mode. 3317 */ 3318 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3319 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3320 goto out; 3321 } 3322 3323 for (npolled = 0; npolled < num_entries; ++npolled) { 3324 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3325 break; 3326 } 3327 3328 if (npolled) { 3329 /* Memory barrier */ 3330 wmb(); 3331 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 3332 } 3333 3334 out: 3335 spin_unlock_irqrestore(&hr_cq->lock, flags); 3336 3337 return npolled; 3338 } 3339 3340 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3341 int step_idx) 3342 { 3343 int op; 3344 3345 if (type == HEM_TYPE_SCCC && step_idx) 3346 return -EINVAL; 3347 3348 switch (type) { 3349 case HEM_TYPE_QPC: 3350 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3351 break; 3352 case HEM_TYPE_MTPT: 3353 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3354 break; 3355 case HEM_TYPE_CQC: 3356 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3357 break; 3358 case HEM_TYPE_SRQC: 3359 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3360 break; 3361 case HEM_TYPE_SCCC: 3362 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3363 break; 3364 case HEM_TYPE_QPC_TIMER: 3365 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3366 break; 3367 case HEM_TYPE_CQC_TIMER: 3368 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3369 break; 3370 default: 3371 dev_warn(hr_dev->dev, 3372 "Table %d not to be written by mailbox!\n", type); 3373 return -EINVAL; 3374 } 3375 3376 return op + step_idx; 3377 } 3378 3379 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba, 3380 u32 hem_type, int step_idx) 3381 { 3382 struct hns_roce_cmd_mailbox *mailbox; 3383 int ret; 3384 int op; 3385 3386 op = get_op_for_set_hem(hr_dev, hem_type, step_idx); 3387 if (op < 0) 3388 return 0; 3389 3390 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3391 if (IS_ERR(mailbox)) 3392 return PTR_ERR(mailbox); 3393 3394 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 3395 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 3396 3397 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3398 3399 return ret; 3400 } 3401 3402 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3403 struct hns_roce_hem_table *table, int obj, 3404 int step_idx) 3405 { 3406 struct hns_roce_hem_iter iter; 3407 struct hns_roce_hem_mhop mhop; 3408 struct hns_roce_hem *hem; 3409 unsigned long mhop_obj = obj; 3410 int i, j, k; 3411 int ret = 0; 3412 u64 hem_idx = 0; 3413 u64 l1_idx = 0; 3414 u64 bt_ba = 0; 3415 u32 chunk_ba_num; 3416 u32 hop_num; 3417 3418 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3419 return 0; 3420 3421 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3422 i = mhop.l0_idx; 3423 j = mhop.l1_idx; 3424 k = mhop.l2_idx; 3425 hop_num = mhop.hop_num; 3426 chunk_ba_num = mhop.bt_chunk_size / 8; 3427 3428 if (hop_num == 2) { 3429 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3430 k; 3431 l1_idx = i * chunk_ba_num + j; 3432 } else if (hop_num == 1) { 3433 hem_idx = i * chunk_ba_num + j; 3434 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3435 hem_idx = i; 3436 } 3437 3438 if (table->type == HEM_TYPE_SCCC) 3439 obj = mhop.l0_idx; 3440 3441 if (check_whether_last_step(hop_num, step_idx)) { 3442 hem = table->hem[hem_idx]; 3443 for (hns_roce_hem_first(hem, &iter); 3444 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3445 bt_ba = hns_roce_hem_addr(&iter); 3446 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3447 step_idx); 3448 } 3449 } else { 3450 if (step_idx == 0) 3451 bt_ba = table->bt_l0_dma_addr[i]; 3452 else if (step_idx == 1 && hop_num == 2) 3453 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3454 3455 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3456 } 3457 3458 return ret; 3459 } 3460 3461 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3462 struct hns_roce_hem_table *table, int obj, 3463 int step_idx) 3464 { 3465 struct device *dev = hr_dev->dev; 3466 struct hns_roce_cmd_mailbox *mailbox; 3467 int ret; 3468 u16 op = 0xff; 3469 3470 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3471 return 0; 3472 3473 switch (table->type) { 3474 case HEM_TYPE_QPC: 3475 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3476 break; 3477 case HEM_TYPE_MTPT: 3478 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3479 break; 3480 case HEM_TYPE_CQC: 3481 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3482 break; 3483 case HEM_TYPE_SCCC: 3484 case HEM_TYPE_QPC_TIMER: 3485 case HEM_TYPE_CQC_TIMER: 3486 break; 3487 case HEM_TYPE_SRQC: 3488 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3489 break; 3490 default: 3491 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 3492 table->type); 3493 return 0; 3494 } 3495 3496 if (table->type == HEM_TYPE_SCCC || 3497 table->type == HEM_TYPE_QPC_TIMER || 3498 table->type == HEM_TYPE_CQC_TIMER) 3499 return 0; 3500 3501 op += step_idx; 3502 3503 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3504 if (IS_ERR(mailbox)) 3505 return PTR_ERR(mailbox); 3506 3507 /* configure the tag and op */ 3508 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3509 HNS_ROCE_CMD_TIMEOUT_MSECS); 3510 3511 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3512 return ret; 3513 } 3514 3515 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3516 struct hns_roce_v2_qp_context *context, 3517 struct hns_roce_qp *hr_qp) 3518 { 3519 struct hns_roce_cmd_mailbox *mailbox; 3520 int ret; 3521 3522 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3523 if (IS_ERR(mailbox)) 3524 return PTR_ERR(mailbox); 3525 3526 memcpy(mailbox->buf, context, sizeof(*context) * 2); 3527 3528 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 3529 HNS_ROCE_CMD_MODIFY_QPC, 3530 HNS_ROCE_CMD_TIMEOUT_MSECS); 3531 3532 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3533 3534 return ret; 3535 } 3536 3537 static void set_access_flags(struct hns_roce_qp *hr_qp, 3538 struct hns_roce_v2_qp_context *context, 3539 struct hns_roce_v2_qp_context *qpc_mask, 3540 const struct ib_qp_attr *attr, int attr_mask) 3541 { 3542 u8 dest_rd_atomic; 3543 u32 access_flags; 3544 3545 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 3546 attr->max_dest_rd_atomic : hr_qp->resp_depth; 3547 3548 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 3549 attr->qp_access_flags : hr_qp->atomic_rd_en; 3550 3551 if (!dest_rd_atomic) 3552 access_flags &= IB_ACCESS_REMOTE_WRITE; 3553 3554 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3555 !!(access_flags & IB_ACCESS_REMOTE_READ)); 3556 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 3557 3558 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3559 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3560 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 3561 3562 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3563 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3564 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 3565 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 3566 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3567 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0); 3568 } 3569 3570 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 3571 struct hns_roce_v2_qp_context *context, 3572 struct hns_roce_v2_qp_context *qpc_mask) 3573 { 3574 roce_set_field(context->byte_4_sqpn_tst, 3575 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S, 3576 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 3577 hr_qp->sge.sge_shift)); 3578 3579 roce_set_field(context->byte_20_smac_sgid_idx, 3580 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 3581 ilog2(hr_qp->sq.wqe_cnt)); 3582 3583 roce_set_field(context->byte_20_smac_sgid_idx, 3584 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 3585 ilog2(hr_qp->rq.wqe_cnt)); 3586 } 3587 3588 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 3589 const struct ib_qp_attr *attr, 3590 int attr_mask, 3591 struct hns_roce_v2_qp_context *context, 3592 struct hns_roce_v2_qp_context *qpc_mask) 3593 { 3594 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3595 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3596 3597 /* 3598 * In v2 engine, software pass context and context mask to hardware 3599 * when modifying qp. If software need modify some fields in context, 3600 * we should set all bits of the relevant fields in context mask to 3601 * 0 at the same time, else set them to 0x1. 3602 */ 3603 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3604 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3605 3606 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3607 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3608 3609 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3610 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3611 3612 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 3613 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 3614 3615 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 3616 3617 /* No VLAN need to set 0xFFF */ 3618 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 3619 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); 3620 3621 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 3622 roce_set_bit(context->byte_68_rq_db, 3623 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 3624 3625 roce_set_field(context->byte_68_rq_db, 3626 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 3627 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 3628 ((u32)hr_qp->rdb.dma) >> 1); 3629 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32); 3630 3631 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 3632 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 3633 3634 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3635 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3636 if (ibqp->srq) { 3637 roce_set_field(context->byte_76_srqn_op_en, 3638 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3639 to_hr_srq(ibqp->srq)->srqn); 3640 roce_set_bit(context->byte_76_srqn_op_en, 3641 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3642 } 3643 3644 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 3645 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 3646 3647 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); 3648 3649 hr_qp->access_flags = attr->qp_access_flags; 3650 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3651 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3652 } 3653 3654 static void modify_qp_init_to_init(struct ib_qp *ibqp, 3655 const struct ib_qp_attr *attr, int attr_mask, 3656 struct hns_roce_v2_qp_context *context, 3657 struct hns_roce_v2_qp_context *qpc_mask) 3658 { 3659 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3660 3661 /* 3662 * In v2 engine, software pass context and context mask to hardware 3663 * when modifying qp. If software need modify some fields in context, 3664 * we should set all bits of the relevant fields in context mask to 3665 * 0 at the same time, else set them to 0x1. 3666 */ 3667 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3668 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3669 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3670 V2_QPC_BYTE_4_TST_S, 0); 3671 3672 if (attr_mask & IB_QP_ACCESS_FLAGS) { 3673 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3674 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 3675 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3676 0); 3677 3678 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3679 !!(attr->qp_access_flags & 3680 IB_ACCESS_REMOTE_WRITE)); 3681 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3682 0); 3683 3684 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3685 !!(attr->qp_access_flags & 3686 IB_ACCESS_REMOTE_ATOMIC)); 3687 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3688 0); 3689 roce_set_bit(context->byte_76_srqn_op_en, 3690 V2_QPC_BYTE_76_EXT_ATE_S, 3691 !!(attr->qp_access_flags & 3692 IB_ACCESS_REMOTE_ATOMIC)); 3693 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3694 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3695 } else { 3696 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3697 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 3698 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3699 0); 3700 3701 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3702 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 3703 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3704 0); 3705 3706 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3707 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3708 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3709 0); 3710 roce_set_bit(context->byte_76_srqn_op_en, 3711 V2_QPC_BYTE_76_EXT_ATE_S, 3712 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3713 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3714 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3715 } 3716 3717 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3718 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3719 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3720 V2_QPC_BYTE_16_PD_S, 0); 3721 3722 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3723 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3724 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3725 V2_QPC_BYTE_80_RX_CQN_S, 0); 3726 3727 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3728 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3729 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3730 V2_QPC_BYTE_252_TX_CQN_S, 0); 3731 3732 if (ibqp->srq) { 3733 roce_set_bit(context->byte_76_srqn_op_en, 3734 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3735 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3736 V2_QPC_BYTE_76_SRQ_EN_S, 0); 3737 roce_set_field(context->byte_76_srqn_op_en, 3738 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3739 to_hr_srq(ibqp->srq)->srqn); 3740 roce_set_field(qpc_mask->byte_76_srqn_op_en, 3741 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 3742 } 3743 3744 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3745 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3746 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3747 V2_QPC_BYTE_4_SQPN_S, 0); 3748 3749 if (attr_mask & IB_QP_DEST_QPN) { 3750 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 3751 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 3752 roce_set_field(qpc_mask->byte_56_dqpn_err, 3753 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 3754 } 3755 } 3756 3757 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 3758 struct hns_roce_qp *hr_qp, 3759 struct hns_roce_v2_qp_context *context, 3760 struct hns_roce_v2_qp_context *qpc_mask) 3761 { 3762 u64 mtts[MTT_MIN_COUNT] = { 0 }; 3763 u64 wqe_sge_ba; 3764 int count; 3765 3766 /* Search qp buf's mtts */ 3767 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 3768 MTT_MIN_COUNT, &wqe_sge_ba); 3769 if (hr_qp->rq.wqe_cnt && count < 1) { 3770 ibdev_err(&hr_dev->ib_dev, 3771 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 3772 return -EINVAL; 3773 } 3774 3775 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 3776 qpc_mask->wqe_sge_ba = 0; 3777 3778 /* 3779 * In v2 engine, software pass context and context mask to hardware 3780 * when modifying qp. If software need modify some fields in context, 3781 * we should set all bits of the relevant fields in context mask to 3782 * 0 at the same time, else set them to 0x1. 3783 */ 3784 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3785 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3)); 3786 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3787 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 3788 3789 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3790 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 3791 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 3792 hr_qp->sq.wqe_cnt)); 3793 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3794 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 3795 3796 roce_set_field(context->byte_20_smac_sgid_idx, 3797 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3798 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 3799 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 3800 hr_qp->sge.sge_cnt)); 3801 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3802 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3803 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 3804 3805 roce_set_field(context->byte_20_smac_sgid_idx, 3806 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3807 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 3808 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 3809 hr_qp->rq.wqe_cnt)); 3810 3811 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3812 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3813 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 3814 3815 roce_set_field(context->byte_16_buf_ba_pg_sz, 3816 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3817 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 3818 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 3819 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3820 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3821 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 3822 3823 roce_set_field(context->byte_16_buf_ba_pg_sz, 3824 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3825 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 3826 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 3827 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3828 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3829 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 3830 3831 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 3832 qpc_mask->rq_cur_blk_addr = 0; 3833 3834 roce_set_field(context->byte_92_srq_info, 3835 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3836 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 3837 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3838 roce_set_field(qpc_mask->byte_92_srq_info, 3839 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3840 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 3841 3842 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 3843 qpc_mask->rq_nxt_blk_addr = 0; 3844 3845 roce_set_field(context->byte_104_rq_sge, 3846 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3847 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 3848 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3849 roce_set_field(qpc_mask->byte_104_rq_sge, 3850 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3851 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 3852 3853 roce_set_field(context->byte_84_rq_ci_pi, 3854 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3855 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 3856 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3857 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3858 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 3859 3860 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3861 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 3862 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 3863 3864 return 0; 3865 } 3866 3867 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 3868 struct hns_roce_qp *hr_qp, 3869 struct hns_roce_v2_qp_context *context, 3870 struct hns_roce_v2_qp_context *qpc_mask) 3871 { 3872 struct ib_device *ibdev = &hr_dev->ib_dev; 3873 u64 sge_cur_blk = 0; 3874 u64 sq_cur_blk = 0; 3875 int count; 3876 3877 /* search qp buf's mtts */ 3878 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 3879 if (count < 1) { 3880 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 3881 hr_qp->qpn); 3882 return -EINVAL; 3883 } 3884 if (hr_qp->sge.sge_cnt > 0) { 3885 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 3886 hr_qp->sge.offset, 3887 &sge_cur_blk, 1, NULL); 3888 if (count < 1) { 3889 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 3890 hr_qp->qpn); 3891 return -EINVAL; 3892 } 3893 } 3894 3895 /* 3896 * In v2 engine, software pass context and context mask to hardware 3897 * when modifying qp. If software need modify some fields in context, 3898 * we should set all bits of the relevant fields in context mask to 3899 * 0 at the same time, else set them to 0x1. 3900 */ 3901 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3902 roce_set_field(context->byte_168_irrl_idx, 3903 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3904 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 3905 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3906 qpc_mask->sq_cur_blk_addr = 0; 3907 roce_set_field(qpc_mask->byte_168_irrl_idx, 3908 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3909 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 3910 3911 context->sq_cur_sge_blk_addr = 3912 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)); 3913 roce_set_field(context->byte_184_irrl_idx, 3914 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3915 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 3916 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 3917 qpc_mask->sq_cur_sge_blk_addr = 0; 3918 roce_set_field(qpc_mask->byte_184_irrl_idx, 3919 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3920 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 3921 3922 context->rx_sq_cur_blk_addr = 3923 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3924 roce_set_field(context->byte_232_irrl_sge, 3925 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3926 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 3927 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3928 qpc_mask->rx_sq_cur_blk_addr = 0; 3929 roce_set_field(qpc_mask->byte_232_irrl_sge, 3930 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3931 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 3932 3933 return 0; 3934 } 3935 3936 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 3937 const struct ib_qp_attr *attr) 3938 { 3939 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 3940 return IB_MTU_4096; 3941 3942 return attr->path_mtu; 3943 } 3944 3945 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 3946 const struct ib_qp_attr *attr, int attr_mask, 3947 struct hns_roce_v2_qp_context *context, 3948 struct hns_roce_v2_qp_context *qpc_mask) 3949 { 3950 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 3951 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3952 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3953 struct ib_device *ibdev = &hr_dev->ib_dev; 3954 dma_addr_t trrl_ba; 3955 dma_addr_t irrl_ba; 3956 enum ib_mtu mtu; 3957 u8 port_num; 3958 u64 *mtts; 3959 u8 *dmac; 3960 u8 *smac; 3961 int port; 3962 int ret; 3963 3964 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 3965 if (ret) { 3966 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 3967 return ret; 3968 } 3969 3970 /* Search IRRL's mtts */ 3971 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 3972 hr_qp->qpn, &irrl_ba); 3973 if (!mtts) { 3974 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 3975 return -EINVAL; 3976 } 3977 3978 /* Search TRRL's mtts */ 3979 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 3980 hr_qp->qpn, &trrl_ba); 3981 if (!mtts) { 3982 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 3983 return -EINVAL; 3984 } 3985 3986 if (attr_mask & IB_QP_ALT_PATH) { 3987 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 3988 attr_mask); 3989 return -EINVAL; 3990 } 3991 3992 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3993 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4); 3994 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3995 V2_QPC_BYTE_132_TRRL_BA_S, 0); 3996 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 3997 qpc_mask->trrl_ba = 0; 3998 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 3999 V2_QPC_BYTE_140_TRRL_BA_S, 4000 (u32)(trrl_ba >> (32 + 16 + 4))); 4001 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4002 V2_QPC_BYTE_140_TRRL_BA_S, 0); 4003 4004 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4005 qpc_mask->irrl_ba = 0; 4006 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4007 V2_QPC_BYTE_208_IRRL_BA_S, 4008 irrl_ba >> (32 + 6)); 4009 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4010 V2_QPC_BYTE_208_IRRL_BA_S, 0); 4011 4012 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 4013 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 4014 4015 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4016 hr_qp->sq_signal_bits); 4017 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4018 0); 4019 4020 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4021 4022 smac = (u8 *)hr_dev->dev_addr[port]; 4023 dmac = (u8 *)attr->ah_attr.roce.dmac; 4024 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4025 if (ether_addr_equal_unaligned(dmac, smac) || 4026 hr_dev->loop_idc == 0x1) { 4027 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 4028 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 4029 } 4030 4031 if (attr_mask & IB_QP_DEST_QPN) { 4032 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 4033 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 4034 roce_set_field(qpc_mask->byte_56_dqpn_err, 4035 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 4036 } 4037 4038 /* Configure GID index */ 4039 port_num = rdma_ah_get_port_num(&attr->ah_attr); 4040 roce_set_field(context->byte_20_smac_sgid_idx, 4041 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4042 hns_get_gid_index(hr_dev, port_num - 1, 4043 grh->sgid_index)); 4044 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4045 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4046 4047 memcpy(&(context->dmac), dmac, sizeof(u32)); 4048 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4049 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 4050 qpc_mask->dmac = 0; 4051 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4052 V2_QPC_BYTE_52_DMAC_S, 0); 4053 4054 mtu = get_mtu(ibqp, attr); 4055 4056 if (attr_mask & IB_QP_PATH_MTU) { 4057 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4058 V2_QPC_BYTE_24_MTU_S, mtu); 4059 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4060 V2_QPC_BYTE_24_MTU_S, 0); 4061 } 4062 4063 #define MAX_LP_MSG_LEN 65536 4064 /* MTU*(2^LP_PKTN_INI) shouldn't be bigger than 64kb */ 4065 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4066 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4067 ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu))); 4068 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4069 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 4070 4071 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4072 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 4073 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 4074 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 4075 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4076 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 4077 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 4078 4079 context->rq_rnr_timer = 0; 4080 qpc_mask->rq_rnr_timer = 0; 4081 4082 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 4083 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 4084 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 4085 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 4086 4087 /* rocee send 2^lp_sgen_ini segs every time */ 4088 roce_set_field(context->byte_168_irrl_idx, 4089 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4090 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 4091 roce_set_field(qpc_mask->byte_168_irrl_idx, 4092 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4093 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 4094 4095 return 0; 4096 } 4097 4098 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4099 const struct ib_qp_attr *attr, int attr_mask, 4100 struct hns_roce_v2_qp_context *context, 4101 struct hns_roce_v2_qp_context *qpc_mask) 4102 { 4103 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4104 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4105 struct ib_device *ibdev = &hr_dev->ib_dev; 4106 int ret; 4107 4108 /* Not support alternate path and path migration */ 4109 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4110 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4111 return -EINVAL; 4112 } 4113 4114 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4115 if (ret) { 4116 ibdev_err(ibdev, "failed to config sq buf, ret %d\n", ret); 4117 return ret; 4118 } 4119 4120 /* 4121 * Set some fields in context to zero, Because the default values 4122 * of all fields in context are zero, we need not set them to 0 again. 4123 * but we should set the relevant fields of context mask to 0. 4124 */ 4125 roce_set_field(qpc_mask->byte_232_irrl_sge, 4126 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 4127 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 4128 4129 roce_set_field(qpc_mask->byte_240_irrl_tail, 4130 V2_QPC_BYTE_240_RX_ACK_MSN_M, 4131 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 4132 4133 roce_set_field(qpc_mask->byte_248_ack_psn, 4134 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 4135 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 4136 roce_set_bit(qpc_mask->byte_248_ack_psn, 4137 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 4138 roce_set_field(qpc_mask->byte_248_ack_psn, 4139 V2_QPC_BYTE_248_IRRL_PSN_M, 4140 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 4141 4142 roce_set_field(qpc_mask->byte_240_irrl_tail, 4143 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 4144 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 4145 4146 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4147 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 4148 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 4149 4150 roce_set_bit(qpc_mask->byte_248_ack_psn, 4151 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 4152 4153 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 4154 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 4155 4156 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4157 V2_QPC_BYTE_212_LSN_S, 0x100); 4158 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4159 V2_QPC_BYTE_212_LSN_S, 0); 4160 4161 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 4162 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 4163 4164 return 0; 4165 } 4166 4167 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4168 const struct ib_qp_attr *attr, 4169 int attr_mask, 4170 struct hns_roce_v2_qp_context *context, 4171 struct hns_roce_v2_qp_context *qpc_mask) 4172 { 4173 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4174 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4175 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4176 struct ib_device *ibdev = &hr_dev->ib_dev; 4177 const struct ib_gid_attr *gid_attr = NULL; 4178 int is_roce_protocol; 4179 u16 vlan_id = 0xffff; 4180 bool is_udp = false; 4181 u8 ib_port; 4182 u8 hr_port; 4183 int ret; 4184 4185 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4186 hr_port = ib_port - 1; 4187 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4188 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4189 4190 if (is_roce_protocol) { 4191 gid_attr = attr->ah_attr.grh.sgid_attr; 4192 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4193 if (ret) 4194 return ret; 4195 4196 if (gid_attr) 4197 is_udp = (gid_attr->gid_type == 4198 IB_GID_TYPE_ROCE_UDP_ENCAP); 4199 } 4200 4201 if (vlan_id < VLAN_N_VID) { 4202 roce_set_bit(context->byte_76_srqn_op_en, 4203 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1); 4204 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 4205 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0); 4206 roce_set_bit(context->byte_168_irrl_idx, 4207 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1); 4208 roce_set_bit(qpc_mask->byte_168_irrl_idx, 4209 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0); 4210 } 4211 4212 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4213 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id); 4214 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4215 V2_QPC_BYTE_24_VLAN_ID_S, 0); 4216 4217 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4218 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4219 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4220 return -EINVAL; 4221 } 4222 4223 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4224 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4225 return -EINVAL; 4226 } 4227 4228 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4229 V2_QPC_BYTE_52_UDPSPN_S, 4230 is_udp ? 0x12b7 : 0); 4231 4232 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4233 V2_QPC_BYTE_52_UDPSPN_S, 0); 4234 4235 roce_set_field(context->byte_20_smac_sgid_idx, 4236 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4237 grh->sgid_index); 4238 4239 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4240 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4241 4242 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4243 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 4244 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4245 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 4246 4247 if (is_udp) 4248 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4249 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2); 4250 else 4251 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4252 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 4253 4254 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4255 V2_QPC_BYTE_24_TC_S, 0); 4256 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4257 V2_QPC_BYTE_28_FL_S, grh->flow_label); 4258 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4259 V2_QPC_BYTE_28_FL_S, 0); 4260 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4261 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4262 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4263 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 4264 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4265 V2_QPC_BYTE_28_SL_S, 0); 4266 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4267 4268 return 0; 4269 } 4270 4271 static bool check_qp_state(enum ib_qp_state cur_state, 4272 enum ib_qp_state new_state) 4273 { 4274 static const bool sm[][IB_QPS_ERR + 1] = { 4275 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4276 [IB_QPS_INIT] = true }, 4277 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4278 [IB_QPS_INIT] = true, 4279 [IB_QPS_RTR] = true, 4280 [IB_QPS_ERR] = true }, 4281 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4282 [IB_QPS_RTS] = true, 4283 [IB_QPS_ERR] = true }, 4284 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4285 [IB_QPS_RTS] = true, 4286 [IB_QPS_ERR] = true }, 4287 [IB_QPS_SQD] = {}, 4288 [IB_QPS_SQE] = {}, 4289 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4290 }; 4291 4292 return sm[cur_state][new_state]; 4293 } 4294 4295 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4296 const struct ib_qp_attr *attr, 4297 int attr_mask, 4298 enum ib_qp_state cur_state, 4299 enum ib_qp_state new_state, 4300 struct hns_roce_v2_qp_context *context, 4301 struct hns_roce_v2_qp_context *qpc_mask) 4302 { 4303 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4304 int ret = 0; 4305 4306 if (!check_qp_state(cur_state, new_state)) { 4307 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4308 return -EINVAL; 4309 } 4310 4311 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4312 memset(qpc_mask, 0, sizeof(*qpc_mask)); 4313 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4314 qpc_mask); 4315 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4316 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4317 qpc_mask); 4318 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4319 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4320 qpc_mask); 4321 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4322 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4323 qpc_mask); 4324 } 4325 4326 return ret; 4327 } 4328 4329 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4330 const struct ib_qp_attr *attr, 4331 int attr_mask, 4332 struct hns_roce_v2_qp_context *context, 4333 struct hns_roce_v2_qp_context *qpc_mask) 4334 { 4335 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4336 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4337 int ret = 0; 4338 4339 if (attr_mask & IB_QP_AV) { 4340 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4341 qpc_mask); 4342 if (ret) 4343 return ret; 4344 } 4345 4346 if (attr_mask & IB_QP_TIMEOUT) { 4347 if (attr->timeout < 31) { 4348 roce_set_field(context->byte_28_at_fl, 4349 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4350 attr->timeout); 4351 roce_set_field(qpc_mask->byte_28_at_fl, 4352 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4353 0); 4354 } else { 4355 ibdev_warn(&hr_dev->ib_dev, 4356 "Local ACK timeout shall be 0 to 30.\n"); 4357 } 4358 } 4359 4360 if (attr_mask & IB_QP_RETRY_CNT) { 4361 roce_set_field(context->byte_212_lsn, 4362 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4363 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 4364 attr->retry_cnt); 4365 roce_set_field(qpc_mask->byte_212_lsn, 4366 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4367 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 4368 4369 roce_set_field(context->byte_212_lsn, 4370 V2_QPC_BYTE_212_RETRY_CNT_M, 4371 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 4372 roce_set_field(qpc_mask->byte_212_lsn, 4373 V2_QPC_BYTE_212_RETRY_CNT_M, 4374 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 4375 } 4376 4377 if (attr_mask & IB_QP_RNR_RETRY) { 4378 roce_set_field(context->byte_244_rnr_rxack, 4379 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4380 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 4381 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4382 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4383 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 4384 4385 roce_set_field(context->byte_244_rnr_rxack, 4386 V2_QPC_BYTE_244_RNR_CNT_M, 4387 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 4388 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4389 V2_QPC_BYTE_244_RNR_CNT_M, 4390 V2_QPC_BYTE_244_RNR_CNT_S, 0); 4391 } 4392 4393 /* RC&UC&UD required attr */ 4394 if (attr_mask & IB_QP_SQ_PSN) { 4395 roce_set_field(context->byte_172_sq_psn, 4396 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4397 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 4398 roce_set_field(qpc_mask->byte_172_sq_psn, 4399 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4400 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 4401 4402 roce_set_field(context->byte_196_sq_psn, 4403 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4404 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 4405 roce_set_field(qpc_mask->byte_196_sq_psn, 4406 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4407 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 4408 4409 roce_set_field(context->byte_220_retry_psn_msn, 4410 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4411 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 4412 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4413 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4414 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 4415 4416 roce_set_field(context->byte_224_retry_msg, 4417 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4418 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 4419 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S); 4420 roce_set_field(qpc_mask->byte_224_retry_msg, 4421 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4422 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 4423 4424 roce_set_field(context->byte_224_retry_msg, 4425 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4426 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 4427 attr->sq_psn); 4428 roce_set_field(qpc_mask->byte_224_retry_msg, 4429 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4430 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 4431 4432 roce_set_field(context->byte_244_rnr_rxack, 4433 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4434 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 4435 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4436 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4437 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 4438 } 4439 4440 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4441 attr->max_dest_rd_atomic) { 4442 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4443 V2_QPC_BYTE_140_RR_MAX_S, 4444 fls(attr->max_dest_rd_atomic - 1)); 4445 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4446 V2_QPC_BYTE_140_RR_MAX_S, 0); 4447 } 4448 4449 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4450 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 4451 V2_QPC_BYTE_208_SR_MAX_S, 4452 fls(attr->max_rd_atomic - 1)); 4453 roce_set_field(qpc_mask->byte_208_irrl, 4454 V2_QPC_BYTE_208_SR_MAX_M, 4455 V2_QPC_BYTE_208_SR_MAX_S, 0); 4456 } 4457 4458 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4459 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4460 4461 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4462 roce_set_field(context->byte_80_rnr_rx_cqn, 4463 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4464 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 4465 attr->min_rnr_timer); 4466 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 4467 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4468 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 4469 } 4470 4471 /* RC&UC required attr */ 4472 if (attr_mask & IB_QP_RQ_PSN) { 4473 roce_set_field(context->byte_108_rx_reqepsn, 4474 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4475 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 4476 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4477 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4478 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 4479 4480 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 4481 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 4482 roce_set_field(qpc_mask->byte_152_raq, 4483 V2_QPC_BYTE_152_RAQ_PSN_M, 4484 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 4485 } 4486 4487 if (attr_mask & IB_QP_QKEY) { 4488 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4489 qpc_mask->qkey_xrcd = 0; 4490 hr_qp->qkey = attr->qkey; 4491 } 4492 4493 return ret; 4494 } 4495 4496 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4497 const struct ib_qp_attr *attr, 4498 int attr_mask) 4499 { 4500 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4501 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4502 4503 if (attr_mask & IB_QP_ACCESS_FLAGS) 4504 hr_qp->atomic_rd_en = attr->qp_access_flags; 4505 4506 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4507 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4508 if (attr_mask & IB_QP_PORT) { 4509 hr_qp->port = attr->port_num - 1; 4510 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4511 } 4512 } 4513 4514 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4515 const struct ib_qp_attr *attr, 4516 int attr_mask, enum ib_qp_state cur_state, 4517 enum ib_qp_state new_state) 4518 { 4519 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4520 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4521 struct hns_roce_v2_qp_context ctx[2]; 4522 struct hns_roce_v2_qp_context *context = ctx; 4523 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4524 struct ib_device *ibdev = &hr_dev->ib_dev; 4525 unsigned long sq_flag = 0; 4526 unsigned long rq_flag = 0; 4527 int ret; 4528 4529 /* 4530 * In v2 engine, software pass context and context mask to hardware 4531 * when modifying qp. If software need modify some fields in context, 4532 * we should set all bits of the relevant fields in context mask to 4533 * 0 at the same time, else set them to 0x1. 4534 */ 4535 memset(context, 0, sizeof(*context)); 4536 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 4537 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4538 new_state, context, qpc_mask); 4539 if (ret) 4540 goto out; 4541 4542 /* When QP state is err, SQ and RQ WQE should be flushed */ 4543 if (new_state == IB_QPS_ERR) { 4544 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4545 hr_qp->state = IB_QPS_ERR; 4546 roce_set_field(context->byte_160_sq_ci_pi, 4547 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4548 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 4549 hr_qp->sq.head); 4550 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 4551 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4552 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 4553 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4554 4555 if (!ibqp->srq) { 4556 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4557 roce_set_field(context->byte_84_rq_ci_pi, 4558 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4559 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 4560 hr_qp->rq.head); 4561 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4562 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4563 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 4564 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4565 } 4566 } 4567 4568 /* Configure the optional fields */ 4569 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 4570 qpc_mask); 4571 if (ret) 4572 goto out; 4573 4574 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 4575 ibqp->srq ? 1 : 0); 4576 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4577 V2_QPC_BYTE_108_INV_CREDIT_S, 0); 4578 4579 /* Every status migrate must change state */ 4580 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4581 V2_QPC_BYTE_60_QP_ST_S, new_state); 4582 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4583 V2_QPC_BYTE_60_QP_ST_S, 0); 4584 4585 /* SW pass context to HW */ 4586 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp); 4587 if (ret) { 4588 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret); 4589 goto out; 4590 } 4591 4592 hr_qp->state = new_state; 4593 4594 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 4595 4596 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 4597 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 4598 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 4599 if (ibqp->send_cq != ibqp->recv_cq) 4600 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4601 hr_qp->qpn, NULL); 4602 4603 hr_qp->rq.head = 0; 4604 hr_qp->rq.tail = 0; 4605 hr_qp->sq.head = 0; 4606 hr_qp->sq.tail = 0; 4607 hr_qp->next_sge = 0; 4608 if (hr_qp->rq.wqe_cnt) 4609 *hr_qp->rdb.db_record = 0; 4610 } 4611 4612 out: 4613 return ret; 4614 } 4615 4616 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 4617 { 4618 static const enum ib_qp_state map[] = { 4619 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 4620 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 4621 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 4622 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 4623 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 4624 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 4625 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 4626 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 4627 }; 4628 4629 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 4630 } 4631 4632 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 4633 struct hns_roce_qp *hr_qp, 4634 struct hns_roce_v2_qp_context *hr_context) 4635 { 4636 struct hns_roce_cmd_mailbox *mailbox; 4637 int ret; 4638 4639 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4640 if (IS_ERR(mailbox)) 4641 return PTR_ERR(mailbox); 4642 4643 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 4644 HNS_ROCE_CMD_QUERY_QPC, 4645 HNS_ROCE_CMD_TIMEOUT_MSECS); 4646 if (ret) 4647 goto out; 4648 4649 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 4650 4651 out: 4652 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4653 return ret; 4654 } 4655 4656 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4657 int qp_attr_mask, 4658 struct ib_qp_init_attr *qp_init_attr) 4659 { 4660 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4661 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4662 struct hns_roce_v2_qp_context context = {}; 4663 struct ib_device *ibdev = &hr_dev->ib_dev; 4664 int tmp_qp_state; 4665 int state; 4666 int ret; 4667 4668 memset(qp_attr, 0, sizeof(*qp_attr)); 4669 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4670 4671 mutex_lock(&hr_qp->mutex); 4672 4673 if (hr_qp->state == IB_QPS_RESET) { 4674 qp_attr->qp_state = IB_QPS_RESET; 4675 ret = 0; 4676 goto done; 4677 } 4678 4679 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 4680 if (ret) { 4681 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret); 4682 ret = -EINVAL; 4683 goto out; 4684 } 4685 4686 state = roce_get_field(context.byte_60_qpst_tempid, 4687 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 4688 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 4689 if (tmp_qp_state == -1) { 4690 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 4691 ret = -EINVAL; 4692 goto out; 4693 } 4694 hr_qp->state = (u8)tmp_qp_state; 4695 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 4696 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc, 4697 V2_QPC_BYTE_24_MTU_M, 4698 V2_QPC_BYTE_24_MTU_S); 4699 qp_attr->path_mig_state = IB_MIG_ARMED; 4700 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 4701 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 4702 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 4703 4704 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn, 4705 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4706 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 4707 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn, 4708 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4709 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 4710 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err, 4711 V2_QPC_BYTE_56_DQPN_M, 4712 V2_QPC_BYTE_56_DQPN_S); 4713 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en, 4714 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) | 4715 ((roce_get_bit(context.byte_76_srqn_op_en, 4716 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) | 4717 ((roce_get_bit(context.byte_76_srqn_op_en, 4718 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); 4719 4720 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 4721 hr_qp->ibqp.qp_type == IB_QPT_UC) { 4722 struct ib_global_route *grh = 4723 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 4724 4725 rdma_ah_set_sl(&qp_attr->ah_attr, 4726 roce_get_field(context.byte_28_at_fl, 4727 V2_QPC_BYTE_28_SL_M, 4728 V2_QPC_BYTE_28_SL_S)); 4729 grh->flow_label = roce_get_field(context.byte_28_at_fl, 4730 V2_QPC_BYTE_28_FL_M, 4731 V2_QPC_BYTE_28_FL_S); 4732 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx, 4733 V2_QPC_BYTE_20_SGID_IDX_M, 4734 V2_QPC_BYTE_20_SGID_IDX_S); 4735 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc, 4736 V2_QPC_BYTE_24_HOP_LIMIT_M, 4737 V2_QPC_BYTE_24_HOP_LIMIT_S); 4738 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc, 4739 V2_QPC_BYTE_24_TC_M, 4740 V2_QPC_BYTE_24_TC_S); 4741 4742 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 4743 } 4744 4745 qp_attr->port_num = hr_qp->port + 1; 4746 qp_attr->sq_draining = 0; 4747 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl, 4748 V2_QPC_BYTE_208_SR_MAX_M, 4749 V2_QPC_BYTE_208_SR_MAX_S); 4750 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, 4751 V2_QPC_BYTE_140_RR_MAX_M, 4752 V2_QPC_BYTE_140_RR_MAX_S); 4753 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, 4754 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4755 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 4756 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl, 4757 V2_QPC_BYTE_28_AT_M, 4758 V2_QPC_BYTE_28_AT_S); 4759 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn, 4760 V2_QPC_BYTE_212_RETRY_CNT_M, 4761 V2_QPC_BYTE_212_RETRY_CNT_S); 4762 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer); 4763 4764 done: 4765 qp_attr->cur_qp_state = qp_attr->qp_state; 4766 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 4767 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 4768 4769 if (!ibqp->uobject) { 4770 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 4771 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 4772 } else { 4773 qp_attr->cap.max_send_wr = 0; 4774 qp_attr->cap.max_send_sge = 0; 4775 } 4776 4777 qp_init_attr->cap = qp_attr->cap; 4778 4779 out: 4780 mutex_unlock(&hr_qp->mutex); 4781 return ret; 4782 } 4783 4784 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 4785 struct hns_roce_qp *hr_qp, 4786 struct ib_udata *udata) 4787 { 4788 struct ib_device *ibdev = &hr_dev->ib_dev; 4789 struct hns_roce_cq *send_cq, *recv_cq; 4790 unsigned long flags; 4791 int ret = 0; 4792 4793 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 4794 /* Modify qp to reset before destroying qp */ 4795 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 4796 hr_qp->state, IB_QPS_RESET); 4797 if (ret) 4798 ibdev_err(ibdev, 4799 "failed to modify QP to RST, ret = %d\n", 4800 ret); 4801 } 4802 4803 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 4804 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 4805 4806 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 4807 hns_roce_lock_cqs(send_cq, recv_cq); 4808 4809 if (!udata) { 4810 if (recv_cq) 4811 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 4812 (hr_qp->ibqp.srq ? 4813 to_hr_srq(hr_qp->ibqp.srq) : 4814 NULL)); 4815 4816 if (send_cq && send_cq != recv_cq) 4817 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 4818 4819 } 4820 4821 hns_roce_qp_remove(hr_dev, hr_qp); 4822 4823 hns_roce_unlock_cqs(send_cq, recv_cq); 4824 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 4825 4826 return ret; 4827 } 4828 4829 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 4830 { 4831 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4832 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4833 int ret; 4834 4835 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 4836 if (ret) 4837 ibdev_err(&hr_dev->ib_dev, 4838 "failed to destroy QP 0x%06lx, ret = %d\n", 4839 hr_qp->qpn, ret); 4840 4841 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 4842 4843 return 0; 4844 } 4845 4846 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 4847 struct hns_roce_qp *hr_qp) 4848 { 4849 struct ib_device *ibdev = &hr_dev->ib_dev; 4850 struct hns_roce_sccc_clr_done *resp; 4851 struct hns_roce_sccc_clr *clr; 4852 struct hns_roce_cmq_desc desc; 4853 int ret, i; 4854 4855 mutex_lock(&hr_dev->qp_table.scc_mutex); 4856 4857 /* set scc ctx clear done flag */ 4858 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 4859 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4860 if (ret) { 4861 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret); 4862 goto out; 4863 } 4864 4865 /* clear scc context */ 4866 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 4867 clr = (struct hns_roce_sccc_clr *)desc.data; 4868 clr->qpn = cpu_to_le32(hr_qp->qpn); 4869 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4870 if (ret) { 4871 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret); 4872 goto out; 4873 } 4874 4875 /* query scc context clear is done or not */ 4876 resp = (struct hns_roce_sccc_clr_done *)desc.data; 4877 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 4878 hns_roce_cmq_setup_basic_desc(&desc, 4879 HNS_ROCE_OPC_QUERY_SCCC, true); 4880 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4881 if (ret) { 4882 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 4883 ret); 4884 goto out; 4885 } 4886 4887 if (resp->clr_done) 4888 goto out; 4889 4890 msleep(20); 4891 } 4892 4893 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 4894 ret = -ETIMEDOUT; 4895 4896 out: 4897 mutex_unlock(&hr_dev->qp_table.scc_mutex); 4898 return ret; 4899 } 4900 4901 static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev, 4902 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, 4903 u32 cqn, void *mb_buf, u64 *mtts_wqe, 4904 u64 *mtts_idx, dma_addr_t dma_handle_wqe, 4905 dma_addr_t dma_handle_idx) 4906 { 4907 struct hns_roce_srq_context *srq_context; 4908 4909 srq_context = mb_buf; 4910 memset(srq_context, 0, sizeof(*srq_context)); 4911 4912 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M, 4913 SRQC_BYTE_4_SRQ_ST_S, 1); 4914 4915 roce_set_field(srq_context->byte_4_srqn_srqst, 4916 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M, 4917 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S, 4918 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 4919 srq->wqe_cnt)); 4920 roce_set_field(srq_context->byte_4_srqn_srqst, 4921 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S, 4922 ilog2(srq->wqe_cnt)); 4923 4924 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M, 4925 SRQC_BYTE_4_SRQN_S, srq->srqn); 4926 4927 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M, 4928 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 4929 4930 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M, 4931 SRQC_BYTE_12_SRQ_XRCD_S, xrcd); 4932 4933 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3)); 4934 4935 roce_set_field(srq_context->byte_24_wqe_bt_ba, 4936 SRQC_BYTE_24_SRQ_WQE_BT_BA_M, 4937 SRQC_BYTE_24_SRQ_WQE_BT_BA_S, 4938 dma_handle_wqe >> 35); 4939 4940 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M, 4941 SRQC_BYTE_28_PD_S, pdn); 4942 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M, 4943 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 : 4944 fls(srq->max_gs - 1)); 4945 4946 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3); 4947 roce_set_field(srq_context->rsv_idx_bt_ba, 4948 SRQC_BYTE_36_SRQ_IDX_BT_BA_M, 4949 SRQC_BYTE_36_SRQ_IDX_BT_BA_S, 4950 dma_handle_idx >> 35); 4951 4952 srq_context->idx_cur_blk_addr = 4953 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0])); 4954 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4955 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M, 4956 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S, 4957 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 4958 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4959 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M, 4960 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S, 4961 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, 4962 srq->wqe_cnt)); 4963 4964 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4965 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M, 4966 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S, 4967 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift)); 4968 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4969 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M, 4970 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S, 4971 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift)); 4972 4973 srq_context->idx_nxt_blk_addr = 4974 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1])); 4975 roce_set_field(srq_context->rsv_idxnxtblkaddr, 4976 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M, 4977 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S, 4978 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 4979 roce_set_field(srq_context->byte_56_xrc_cqn, 4980 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S, 4981 cqn); 4982 roce_set_field(srq_context->byte_56_xrc_cqn, 4983 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M, 4984 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S, 4985 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 4986 roce_set_field(srq_context->byte_56_xrc_cqn, 4987 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M, 4988 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S, 4989 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 4990 4991 roce_set_bit(srq_context->db_record_addr_record_en, 4992 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0); 4993 } 4994 4995 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 4996 struct ib_srq_attr *srq_attr, 4997 enum ib_srq_attr_mask srq_attr_mask, 4998 struct ib_udata *udata) 4999 { 5000 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5001 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5002 struct hns_roce_srq_context *srq_context; 5003 struct hns_roce_srq_context *srqc_mask; 5004 struct hns_roce_cmd_mailbox *mailbox; 5005 int ret; 5006 5007 if (srq_attr_mask & IB_SRQ_LIMIT) { 5008 if (srq_attr->srq_limit >= srq->wqe_cnt) 5009 return -EINVAL; 5010 5011 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5012 if (IS_ERR(mailbox)) 5013 return PTR_ERR(mailbox); 5014 5015 srq_context = mailbox->buf; 5016 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5017 5018 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5019 5020 roce_set_field(srq_context->byte_8_limit_wl, 5021 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5022 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit); 5023 roce_set_field(srqc_mask->byte_8_limit_wl, 5024 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5025 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 5026 5027 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5028 HNS_ROCE_CMD_MODIFY_SRQC, 5029 HNS_ROCE_CMD_TIMEOUT_MSECS); 5030 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5031 if (ret) { 5032 ibdev_err(&hr_dev->ib_dev, 5033 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5034 ret); 5035 return ret; 5036 } 5037 } 5038 5039 return 0; 5040 } 5041 5042 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5043 { 5044 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5045 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5046 struct hns_roce_srq_context *srq_context; 5047 struct hns_roce_cmd_mailbox *mailbox; 5048 int limit_wl; 5049 int ret; 5050 5051 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5052 if (IS_ERR(mailbox)) 5053 return PTR_ERR(mailbox); 5054 5055 srq_context = mailbox->buf; 5056 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5057 HNS_ROCE_CMD_QUERY_SRQC, 5058 HNS_ROCE_CMD_TIMEOUT_MSECS); 5059 if (ret) { 5060 ibdev_err(&hr_dev->ib_dev, 5061 "failed to process cmd of querying SRQ, ret = %d.\n", 5062 ret); 5063 goto out; 5064 } 5065 5066 limit_wl = roce_get_field(srq_context->byte_8_limit_wl, 5067 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5068 SRQC_BYTE_8_SRQ_LIMIT_WL_S); 5069 5070 attr->srq_limit = limit_wl; 5071 attr->max_wr = srq->wqe_cnt - 1; 5072 attr->max_sge = srq->max_gs; 5073 5074 out: 5075 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5076 return ret; 5077 } 5078 5079 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5080 { 5081 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5082 struct hns_roce_v2_cq_context *cq_context; 5083 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5084 struct hns_roce_v2_cq_context *cqc_mask; 5085 struct hns_roce_cmd_mailbox *mailbox; 5086 int ret; 5087 5088 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5089 if (IS_ERR(mailbox)) 5090 return PTR_ERR(mailbox); 5091 5092 cq_context = mailbox->buf; 5093 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5094 5095 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5096 5097 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5098 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5099 cq_count); 5100 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5101 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5102 0); 5103 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5104 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5105 cq_period); 5106 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5107 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5108 0); 5109 5110 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5111 HNS_ROCE_CMD_MODIFY_CQC, 5112 HNS_ROCE_CMD_TIMEOUT_MSECS); 5113 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5114 if (ret) 5115 ibdev_err(&hr_dev->ib_dev, 5116 "failed to process cmd when modifying CQ, ret = %d\n", 5117 ret); 5118 5119 return ret; 5120 } 5121 5122 static void hns_roce_irq_work_handle(struct work_struct *work) 5123 { 5124 struct hns_roce_work *irq_work = 5125 container_of(work, struct hns_roce_work, work); 5126 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5127 u32 qpn = irq_work->qpn; 5128 u32 cqn = irq_work->cqn; 5129 5130 switch (irq_work->event_type) { 5131 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5132 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5133 break; 5134 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5135 ibdev_warn(ibdev, "Path migration failed.\n"); 5136 break; 5137 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5138 break; 5139 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5140 ibdev_warn(ibdev, "Send queue drained.\n"); 5141 break; 5142 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5143 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5144 qpn, irq_work->sub_type); 5145 break; 5146 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5147 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5148 qpn); 5149 break; 5150 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5151 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5152 qpn, irq_work->sub_type); 5153 break; 5154 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5155 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5156 break; 5157 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5158 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5159 break; 5160 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5161 ibdev_err(ibdev, "SRQ catas error.\n"); 5162 break; 5163 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5164 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn); 5165 break; 5166 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5167 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn); 5168 break; 5169 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5170 ibdev_warn(ibdev, "DB overflow.\n"); 5171 break; 5172 case HNS_ROCE_EVENT_TYPE_FLR: 5173 ibdev_warn(ibdev, "Function level reset.\n"); 5174 break; 5175 default: 5176 break; 5177 } 5178 5179 kfree(irq_work); 5180 } 5181 5182 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5183 struct hns_roce_eq *eq, 5184 u32 qpn, u32 cqn) 5185 { 5186 struct hns_roce_work *irq_work; 5187 5188 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5189 if (!irq_work) 5190 return; 5191 5192 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5193 irq_work->hr_dev = hr_dev; 5194 irq_work->qpn = qpn; 5195 irq_work->cqn = cqn; 5196 irq_work->event_type = eq->event_type; 5197 irq_work->sub_type = eq->sub_type; 5198 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5199 } 5200 5201 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 5202 { 5203 struct hns_roce_dev *hr_dev = eq->hr_dev; 5204 __le32 doorbell[2] = {}; 5205 5206 if (eq->type_flag == HNS_ROCE_AEQ) { 5207 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5208 HNS_ROCE_V2_EQ_DB_CMD_S, 5209 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5210 HNS_ROCE_EQ_DB_CMD_AEQ : 5211 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5212 } else { 5213 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 5214 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 5215 5216 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5217 HNS_ROCE_V2_EQ_DB_CMD_S, 5218 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5219 HNS_ROCE_EQ_DB_CMD_CEQ : 5220 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5221 } 5222 5223 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 5224 HNS_ROCE_V2_EQ_DB_PARA_S, 5225 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 5226 5227 hns_roce_write64(hr_dev, doorbell, eq->doorbell); 5228 } 5229 5230 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5231 { 5232 struct hns_roce_aeqe *aeqe; 5233 5234 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5235 (eq->cons_index & (eq->entries - 1)) * 5236 HNS_ROCE_AEQ_ENTRY_SIZE); 5237 5238 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5239 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5240 } 5241 5242 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5243 struct hns_roce_eq *eq) 5244 { 5245 struct device *dev = hr_dev->dev; 5246 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5247 int aeqe_found = 0; 5248 int event_type; 5249 int sub_type; 5250 u32 srqn; 5251 u32 qpn; 5252 u32 cqn; 5253 5254 while (aeqe) { 5255 /* Make sure we read AEQ entry after we have checked the 5256 * ownership bit 5257 */ 5258 dma_rmb(); 5259 5260 event_type = roce_get_field(aeqe->asyn, 5261 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5262 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5263 sub_type = roce_get_field(aeqe->asyn, 5264 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5265 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5266 qpn = roce_get_field(aeqe->event.qp_event.qp, 5267 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5268 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5269 cqn = roce_get_field(aeqe->event.cq_event.cq, 5270 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5271 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5272 srqn = roce_get_field(aeqe->event.srq_event.srq, 5273 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5274 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5275 5276 switch (event_type) { 5277 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5278 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5279 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5280 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5281 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5282 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5283 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5284 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5285 hns_roce_qp_event(hr_dev, qpn, event_type); 5286 break; 5287 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5288 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5289 hns_roce_srq_event(hr_dev, srqn, event_type); 5290 break; 5291 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5292 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5293 hns_roce_cq_event(hr_dev, cqn, event_type); 5294 break; 5295 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5296 break; 5297 case HNS_ROCE_EVENT_TYPE_MB: 5298 hns_roce_cmd_event(hr_dev, 5299 le16_to_cpu(aeqe->event.cmd.token), 5300 aeqe->event.cmd.status, 5301 le64_to_cpu(aeqe->event.cmd.out_param)); 5302 break; 5303 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 5304 break; 5305 case HNS_ROCE_EVENT_TYPE_FLR: 5306 break; 5307 default: 5308 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5309 event_type, eq->eqn, eq->cons_index); 5310 break; 5311 } 5312 5313 eq->event_type = event_type; 5314 eq->sub_type = sub_type; 5315 ++eq->cons_index; 5316 aeqe_found = 1; 5317 5318 if (eq->cons_index > (2 * eq->entries - 1)) 5319 eq->cons_index = 0; 5320 5321 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn); 5322 5323 aeqe = next_aeqe_sw_v2(eq); 5324 } 5325 5326 set_eq_cons_index_v2(eq); 5327 return aeqe_found; 5328 } 5329 5330 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5331 { 5332 struct hns_roce_ceqe *ceqe; 5333 5334 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5335 (eq->cons_index & (eq->entries - 1)) * 5336 HNS_ROCE_CEQ_ENTRY_SIZE); 5337 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5338 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5339 } 5340 5341 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5342 struct hns_roce_eq *eq) 5343 { 5344 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5345 int ceqe_found = 0; 5346 u32 cqn; 5347 5348 while (ceqe) { 5349 /* Make sure we read CEQ entry after we have checked the 5350 * ownership bit 5351 */ 5352 dma_rmb(); 5353 5354 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5355 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5356 5357 hns_roce_cq_completion(hr_dev, cqn); 5358 5359 ++eq->cons_index; 5360 ceqe_found = 1; 5361 5362 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1)) 5363 eq->cons_index = 0; 5364 5365 ceqe = next_ceqe_sw_v2(eq); 5366 } 5367 5368 set_eq_cons_index_v2(eq); 5369 5370 return ceqe_found; 5371 } 5372 5373 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5374 { 5375 struct hns_roce_eq *eq = eq_ptr; 5376 struct hns_roce_dev *hr_dev = eq->hr_dev; 5377 int int_work = 0; 5378 5379 if (eq->type_flag == HNS_ROCE_CEQ) 5380 /* Completion event interrupt */ 5381 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5382 else 5383 /* Asychronous event interrupt */ 5384 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5385 5386 return IRQ_RETVAL(int_work); 5387 } 5388 5389 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5390 { 5391 struct hns_roce_dev *hr_dev = dev_id; 5392 struct device *dev = hr_dev->dev; 5393 int int_work = 0; 5394 u32 int_st; 5395 u32 int_en; 5396 5397 /* Abnormal interrupt */ 5398 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5399 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5400 5401 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5402 struct pci_dev *pdev = hr_dev->pci_dev; 5403 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5404 const struct hnae3_ae_ops *ops = ae_dev->ops; 5405 5406 dev_err(dev, "AEQ overflow!\n"); 5407 5408 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5409 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5410 5411 /* Set reset level for reset_event() */ 5412 if (ops->set_default_reset_request) 5413 ops->set_default_reset_request(ae_dev, 5414 HNAE3_FUNC_RESET); 5415 if (ops->reset_event) 5416 ops->reset_event(pdev, NULL); 5417 5418 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5419 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5420 5421 int_work = 1; 5422 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 5423 dev_err(dev, "BUS ERR!\n"); 5424 5425 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S; 5426 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5427 5428 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5429 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5430 5431 int_work = 1; 5432 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 5433 dev_err(dev, "OTHER ERR!\n"); 5434 5435 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S; 5436 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5437 5438 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5439 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5440 5441 int_work = 1; 5442 } else 5443 dev_err(dev, "There is no abnormal irq found!\n"); 5444 5445 return IRQ_RETVAL(int_work); 5446 } 5447 5448 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5449 int eq_num, int enable_flag) 5450 { 5451 int i; 5452 5453 if (enable_flag == EQ_ENABLE) { 5454 for (i = 0; i < eq_num; i++) 5455 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5456 i * EQ_REG_OFFSET, 5457 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 5458 5459 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5460 HNS_ROCE_V2_VF_ABN_INT_EN_M); 5461 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5462 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 5463 } else { 5464 for (i = 0; i < eq_num; i++) 5465 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5466 i * EQ_REG_OFFSET, 5467 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 5468 5469 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5470 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 5471 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5472 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 5473 } 5474 } 5475 5476 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5477 { 5478 struct device *dev = hr_dev->dev; 5479 int ret; 5480 5481 if (eqn < hr_dev->caps.num_comp_vectors) 5482 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5483 0, HNS_ROCE_CMD_DESTROY_CEQC, 5484 HNS_ROCE_CMD_TIMEOUT_MSECS); 5485 else 5486 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5487 0, HNS_ROCE_CMD_DESTROY_AEQC, 5488 HNS_ROCE_CMD_TIMEOUT_MSECS); 5489 if (ret) 5490 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5491 } 5492 5493 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5494 { 5495 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5496 } 5497 5498 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5499 void *mb_buf) 5500 { 5501 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5502 struct hns_roce_eq_context *eqc; 5503 u64 bt_ba = 0; 5504 int count; 5505 5506 eqc = mb_buf; 5507 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5508 5509 /* init eqc */ 5510 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5511 eq->cons_index = 0; 5512 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5513 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5514 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5515 eq->shift = ilog2((unsigned int)eq->entries); 5516 5517 /* if not multi-hop, eqe buffer only use one trunk */ 5518 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5519 &bt_ba); 5520 if (count < 1) { 5521 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5522 return -ENOBUFS; 5523 } 5524 5525 /* set eqc state */ 5526 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, 5527 HNS_ROCE_V2_EQ_STATE_VALID); 5528 5529 /* set eqe hop num */ 5530 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, 5531 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 5532 5533 /* set eqc over_ignore */ 5534 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, 5535 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 5536 5537 /* set eqc coalesce */ 5538 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M, 5539 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 5540 5541 /* set eqc arm_state */ 5542 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, 5543 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 5544 5545 /* set eqn */ 5546 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, 5547 eq->eqn); 5548 5549 /* set eqe_cnt */ 5550 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, 5551 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); 5552 5553 /* set eqe_ba_pg_sz */ 5554 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M, 5555 HNS_ROCE_EQC_BA_PG_SZ_S, 5556 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5557 5558 /* set eqe_buf_pg_sz */ 5559 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M, 5560 HNS_ROCE_EQC_BUF_PG_SZ_S, 5561 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5562 5563 /* set eq_producer_idx */ 5564 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M, 5565 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX); 5566 5567 /* set eq_max_cnt */ 5568 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M, 5569 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 5570 5571 /* set eq_period */ 5572 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M, 5573 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 5574 5575 /* set eqe_report_timer */ 5576 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M, 5577 HNS_ROCE_EQC_REPORT_TIMER_S, 5578 HNS_ROCE_EQ_INIT_REPORT_TIMER); 5579 5580 /* set bt_ba [34:3] */ 5581 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M, 5582 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3); 5583 5584 /* set bt_ba [64:35] */ 5585 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M, 5586 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35); 5587 5588 /* set eq shift */ 5589 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S, 5590 eq->shift); 5591 5592 /* set eq MSI_IDX */ 5593 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M, 5594 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX); 5595 5596 /* set cur_eqe_ba [27:12] */ 5597 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M, 5598 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12); 5599 5600 /* set cur_eqe_ba [59:28] */ 5601 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M, 5602 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28); 5603 5604 /* set cur_eqe_ba [63:60] */ 5605 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M, 5606 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60); 5607 5608 /* set eq consumer idx */ 5609 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M, 5610 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX); 5611 5612 /* set nex_eqe_ba[43:12] */ 5613 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M, 5614 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12); 5615 5616 /* set nex_eqe_ba[63:44] */ 5617 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M, 5618 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44); 5619 5620 return 0; 5621 } 5622 5623 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5624 { 5625 struct hns_roce_buf_attr buf_attr = {}; 5626 int err; 5627 5628 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5629 eq->hop_num = 0; 5630 else 5631 eq->hop_num = hr_dev->caps.eqe_hop_num; 5632 5633 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT; 5634 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5635 buf_attr.region[0].hopnum = eq->hop_num; 5636 buf_attr.region_count = 1; 5637 buf_attr.fixed_page = true; 5638 5639 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5640 hr_dev->caps.eqe_ba_pg_sz + 5641 HNS_HW_PAGE_SHIFT, NULL, 0); 5642 if (err) 5643 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5644 5645 return err; 5646 } 5647 5648 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5649 struct hns_roce_eq *eq, 5650 unsigned int eq_cmd) 5651 { 5652 struct hns_roce_cmd_mailbox *mailbox; 5653 int ret; 5654 5655 /* Allocate mailbox memory */ 5656 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5657 if (IS_ERR_OR_NULL(mailbox)) 5658 return -ENOMEM; 5659 5660 ret = alloc_eq_buf(hr_dev, eq); 5661 if (ret) 5662 goto free_cmd_mbox; 5663 5664 ret = config_eqc(hr_dev, eq, mailbox->buf); 5665 if (ret) 5666 goto err_cmd_mbox; 5667 5668 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5669 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5670 if (ret) { 5671 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5672 goto err_cmd_mbox; 5673 } 5674 5675 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5676 5677 return 0; 5678 5679 err_cmd_mbox: 5680 free_eq_buf(hr_dev, eq); 5681 5682 free_cmd_mbox: 5683 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5684 5685 return ret; 5686 } 5687 5688 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5689 int comp_num, int aeq_num, int other_num) 5690 { 5691 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5692 int i, j; 5693 int ret; 5694 5695 for (i = 0; i < irq_num; i++) { 5696 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5697 GFP_KERNEL); 5698 if (!hr_dev->irq_names[i]) { 5699 ret = -ENOMEM; 5700 goto err_kzalloc_failed; 5701 } 5702 } 5703 5704 /* irq contains: abnormal + AEQ + CEQ */ 5705 for (j = 0; j < other_num; j++) 5706 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5707 "hns-abn-%d", j); 5708 5709 for (j = other_num; j < (other_num + aeq_num); j++) 5710 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5711 "hns-aeq-%d", j - other_num); 5712 5713 for (j = (other_num + aeq_num); j < irq_num; j++) 5714 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5715 "hns-ceq-%d", j - other_num - aeq_num); 5716 5717 for (j = 0; j < irq_num; j++) { 5718 if (j < other_num) 5719 ret = request_irq(hr_dev->irq[j], 5720 hns_roce_v2_msix_interrupt_abn, 5721 0, hr_dev->irq_names[j], hr_dev); 5722 5723 else if (j < (other_num + comp_num)) 5724 ret = request_irq(eq_table->eq[j - other_num].irq, 5725 hns_roce_v2_msix_interrupt_eq, 5726 0, hr_dev->irq_names[j + aeq_num], 5727 &eq_table->eq[j - other_num]); 5728 else 5729 ret = request_irq(eq_table->eq[j - other_num].irq, 5730 hns_roce_v2_msix_interrupt_eq, 5731 0, hr_dev->irq_names[j - comp_num], 5732 &eq_table->eq[j - other_num]); 5733 if (ret) { 5734 dev_err(hr_dev->dev, "Request irq error!\n"); 5735 goto err_request_failed; 5736 } 5737 } 5738 5739 return 0; 5740 5741 err_request_failed: 5742 for (j -= 1; j >= 0; j--) 5743 if (j < other_num) 5744 free_irq(hr_dev->irq[j], hr_dev); 5745 else 5746 free_irq(eq_table->eq[j - other_num].irq, 5747 &eq_table->eq[j - other_num]); 5748 5749 err_kzalloc_failed: 5750 for (i -= 1; i >= 0; i--) 5751 kfree(hr_dev->irq_names[i]); 5752 5753 return ret; 5754 } 5755 5756 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 5757 { 5758 int irq_num; 5759 int eq_num; 5760 int i; 5761 5762 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5763 irq_num = eq_num + hr_dev->caps.num_other_vectors; 5764 5765 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 5766 free_irq(hr_dev->irq[i], hr_dev); 5767 5768 for (i = 0; i < eq_num; i++) 5769 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 5770 5771 for (i = 0; i < irq_num; i++) 5772 kfree(hr_dev->irq_names[i]); 5773 } 5774 5775 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 5776 { 5777 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5778 struct device *dev = hr_dev->dev; 5779 struct hns_roce_eq *eq; 5780 unsigned int eq_cmd; 5781 int irq_num; 5782 int eq_num; 5783 int other_num; 5784 int comp_num; 5785 int aeq_num; 5786 int i; 5787 int ret; 5788 5789 other_num = hr_dev->caps.num_other_vectors; 5790 comp_num = hr_dev->caps.num_comp_vectors; 5791 aeq_num = hr_dev->caps.num_aeq_vectors; 5792 5793 eq_num = comp_num + aeq_num; 5794 irq_num = eq_num + other_num; 5795 5796 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 5797 if (!eq_table->eq) 5798 return -ENOMEM; 5799 5800 /* create eq */ 5801 for (i = 0; i < eq_num; i++) { 5802 eq = &eq_table->eq[i]; 5803 eq->hr_dev = hr_dev; 5804 eq->eqn = i; 5805 if (i < comp_num) { 5806 /* CEQ */ 5807 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 5808 eq->type_flag = HNS_ROCE_CEQ; 5809 eq->entries = hr_dev->caps.ceqe_depth; 5810 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 5811 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 5812 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 5813 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 5814 } else { 5815 /* AEQ */ 5816 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 5817 eq->type_flag = HNS_ROCE_AEQ; 5818 eq->entries = hr_dev->caps.aeqe_depth; 5819 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 5820 eq->irq = hr_dev->irq[i - comp_num + other_num]; 5821 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 5822 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 5823 } 5824 5825 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 5826 if (ret) { 5827 dev_err(dev, "eq create failed.\n"); 5828 goto err_create_eq_fail; 5829 } 5830 } 5831 5832 /* enable irq */ 5833 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 5834 5835 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, 5836 aeq_num, other_num); 5837 if (ret) { 5838 dev_err(dev, "Request irq failed.\n"); 5839 goto err_request_irq_fail; 5840 } 5841 5842 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 5843 if (!hr_dev->irq_workq) { 5844 dev_err(dev, "Create irq workqueue failed!\n"); 5845 ret = -ENOMEM; 5846 goto err_create_wq_fail; 5847 } 5848 5849 return 0; 5850 5851 err_create_wq_fail: 5852 __hns_roce_free_irq(hr_dev); 5853 5854 err_request_irq_fail: 5855 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5856 5857 err_create_eq_fail: 5858 for (i -= 1; i >= 0; i--) 5859 free_eq_buf(hr_dev, &eq_table->eq[i]); 5860 kfree(eq_table->eq); 5861 5862 return ret; 5863 } 5864 5865 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 5866 { 5867 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5868 int eq_num; 5869 int i; 5870 5871 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5872 5873 /* Disable irq */ 5874 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5875 5876 __hns_roce_free_irq(hr_dev); 5877 5878 for (i = 0; i < eq_num; i++) { 5879 hns_roce_v2_destroy_eqc(hr_dev, i); 5880 5881 free_eq_buf(hr_dev, &eq_table->eq[i]); 5882 } 5883 5884 kfree(eq_table->eq); 5885 5886 flush_workqueue(hr_dev->irq_workq); 5887 destroy_workqueue(hr_dev->irq_workq); 5888 } 5889 5890 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 5891 .query_cqc_info = hns_roce_v2_query_cqc_info, 5892 }; 5893 5894 static const struct ib_device_ops hns_roce_v2_dev_ops = { 5895 .destroy_qp = hns_roce_v2_destroy_qp, 5896 .modify_cq = hns_roce_v2_modify_cq, 5897 .poll_cq = hns_roce_v2_poll_cq, 5898 .post_recv = hns_roce_v2_post_recv, 5899 .post_send = hns_roce_v2_post_send, 5900 .query_qp = hns_roce_v2_query_qp, 5901 .req_notify_cq = hns_roce_v2_req_notify_cq, 5902 }; 5903 5904 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 5905 .modify_srq = hns_roce_v2_modify_srq, 5906 .post_srq_recv = hns_roce_v2_post_srq_recv, 5907 .query_srq = hns_roce_v2_query_srq, 5908 }; 5909 5910 static const struct hns_roce_hw hns_roce_hw_v2 = { 5911 .cmq_init = hns_roce_v2_cmq_init, 5912 .cmq_exit = hns_roce_v2_cmq_exit, 5913 .hw_profile = hns_roce_v2_profile, 5914 .hw_init = hns_roce_v2_init, 5915 .hw_exit = hns_roce_v2_exit, 5916 .post_mbox = hns_roce_v2_post_mbox, 5917 .chk_mbox = hns_roce_v2_chk_mbox, 5918 .rst_prc_mbox = hns_roce_v2_rst_process_cmd, 5919 .set_gid = hns_roce_v2_set_gid, 5920 .set_mac = hns_roce_v2_set_mac, 5921 .write_mtpt = hns_roce_v2_write_mtpt, 5922 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 5923 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 5924 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 5925 .write_cqc = hns_roce_v2_write_cqc, 5926 .set_hem = hns_roce_v2_set_hem, 5927 .clear_hem = hns_roce_v2_clear_hem, 5928 .modify_qp = hns_roce_v2_modify_qp, 5929 .query_qp = hns_roce_v2_query_qp, 5930 .destroy_qp = hns_roce_v2_destroy_qp, 5931 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 5932 .modify_cq = hns_roce_v2_modify_cq, 5933 .post_send = hns_roce_v2_post_send, 5934 .post_recv = hns_roce_v2_post_recv, 5935 .req_notify_cq = hns_roce_v2_req_notify_cq, 5936 .poll_cq = hns_roce_v2_poll_cq, 5937 .init_eq = hns_roce_v2_init_eq_table, 5938 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 5939 .write_srqc = hns_roce_v2_write_srqc, 5940 .modify_srq = hns_roce_v2_modify_srq, 5941 .query_srq = hns_roce_v2_query_srq, 5942 .post_srq_recv = hns_roce_v2_post_srq_recv, 5943 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 5944 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 5945 }; 5946 5947 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 5948 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 5949 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 5950 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 5951 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 5952 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 5953 /* required last entry */ 5954 {0, } 5955 }; 5956 5957 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 5958 5959 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 5960 struct hnae3_handle *handle) 5961 { 5962 struct hns_roce_v2_priv *priv = hr_dev->priv; 5963 int i; 5964 5965 hr_dev->pci_dev = handle->pdev; 5966 hr_dev->dev = &handle->pdev->dev; 5967 hr_dev->hw = &hns_roce_hw_v2; 5968 hr_dev->dfx = &hns_roce_dfx_hw_v2; 5969 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 5970 hr_dev->odb_offset = hr_dev->sdb_offset; 5971 5972 /* Get info from NIC driver. */ 5973 hr_dev->reg_base = handle->rinfo.roce_io_base; 5974 hr_dev->caps.num_ports = 1; 5975 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 5976 hr_dev->iboe.phy_port[0] = 0; 5977 5978 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 5979 hr_dev->iboe.netdevs[0]->dev_addr); 5980 5981 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 5982 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 5983 i + handle->rinfo.base_vector); 5984 5985 /* cmd issue mode: 0 is poll, 1 is event */ 5986 hr_dev->cmd_mod = 1; 5987 hr_dev->loop_idc = 0; 5988 5989 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 5990 priv->handle = handle; 5991 } 5992 5993 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 5994 { 5995 struct hns_roce_dev *hr_dev; 5996 int ret; 5997 5998 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 5999 if (!hr_dev) 6000 return -ENOMEM; 6001 6002 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6003 if (!hr_dev->priv) { 6004 ret = -ENOMEM; 6005 goto error_failed_kzalloc; 6006 } 6007 6008 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6009 6010 ret = hns_roce_init(hr_dev); 6011 if (ret) { 6012 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6013 goto error_failed_get_cfg; 6014 } 6015 6016 handle->priv = hr_dev; 6017 6018 return 0; 6019 6020 error_failed_get_cfg: 6021 kfree(hr_dev->priv); 6022 6023 error_failed_kzalloc: 6024 ib_dealloc_device(&hr_dev->ib_dev); 6025 6026 return ret; 6027 } 6028 6029 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6030 bool reset) 6031 { 6032 struct hns_roce_dev *hr_dev = handle->priv; 6033 6034 if (!hr_dev) 6035 return; 6036 6037 handle->priv = NULL; 6038 6039 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6040 hns_roce_handle_device_err(hr_dev); 6041 6042 hns_roce_exit(hr_dev); 6043 kfree(hr_dev->priv); 6044 ib_dealloc_device(&hr_dev->ib_dev); 6045 } 6046 6047 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6048 { 6049 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6050 const struct pci_device_id *id; 6051 struct device *dev = &handle->pdev->dev; 6052 int ret; 6053 6054 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6055 6056 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6057 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6058 goto reset_chk_err; 6059 } 6060 6061 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6062 if (!id) 6063 return 0; 6064 6065 ret = __hns_roce_hw_v2_init_instance(handle); 6066 if (ret) { 6067 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6068 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6069 if (ops->ae_dev_resetting(handle) || 6070 ops->get_hw_reset_stat(handle)) 6071 goto reset_chk_err; 6072 else 6073 return ret; 6074 } 6075 6076 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6077 6078 6079 return 0; 6080 6081 reset_chk_err: 6082 dev_err(dev, "Device is busy in resetting state.\n" 6083 "please retry later.\n"); 6084 6085 return -EBUSY; 6086 } 6087 6088 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6089 bool reset) 6090 { 6091 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6092 return; 6093 6094 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6095 6096 __hns_roce_hw_v2_uninit_instance(handle, reset); 6097 6098 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6099 } 6100 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6101 { 6102 struct hns_roce_dev *hr_dev; 6103 6104 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6105 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6106 return 0; 6107 } 6108 6109 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6110 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6111 6112 hr_dev = handle->priv; 6113 if (!hr_dev) 6114 return 0; 6115 6116 hr_dev->is_reset = true; 6117 hr_dev->active = false; 6118 hr_dev->dis_db = true; 6119 6120 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6121 6122 return 0; 6123 } 6124 6125 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6126 { 6127 struct device *dev = &handle->pdev->dev; 6128 int ret; 6129 6130 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6131 &handle->rinfo.state)) { 6132 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6133 return 0; 6134 } 6135 6136 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6137 6138 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6139 ret = __hns_roce_hw_v2_init_instance(handle); 6140 if (ret) { 6141 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6142 * callback function, RoCE Engine reinitialize. If RoCE reinit 6143 * failed, we should inform NIC driver. 6144 */ 6145 handle->priv = NULL; 6146 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6147 } else { 6148 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6149 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6150 } 6151 6152 return ret; 6153 } 6154 6155 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6156 { 6157 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6158 return 0; 6159 6160 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6161 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6162 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6163 __hns_roce_hw_v2_uninit_instance(handle, false); 6164 6165 return 0; 6166 } 6167 6168 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6169 enum hnae3_reset_notify_type type) 6170 { 6171 int ret = 0; 6172 6173 switch (type) { 6174 case HNAE3_DOWN_CLIENT: 6175 ret = hns_roce_hw_v2_reset_notify_down(handle); 6176 break; 6177 case HNAE3_INIT_CLIENT: 6178 ret = hns_roce_hw_v2_reset_notify_init(handle); 6179 break; 6180 case HNAE3_UNINIT_CLIENT: 6181 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6182 break; 6183 default: 6184 break; 6185 } 6186 6187 return ret; 6188 } 6189 6190 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6191 .init_instance = hns_roce_hw_v2_init_instance, 6192 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6193 .reset_notify = hns_roce_hw_v2_reset_notify, 6194 }; 6195 6196 static struct hnae3_client hns_roce_hw_v2_client = { 6197 .name = "hns_roce_hw_v2", 6198 .type = HNAE3_CLIENT_ROCE, 6199 .ops = &hns_roce_hw_v2_ops, 6200 }; 6201 6202 static int __init hns_roce_hw_v2_init(void) 6203 { 6204 return hnae3_register_client(&hns_roce_hw_v2_client); 6205 } 6206 6207 static void __exit hns_roce_hw_v2_exit(void) 6208 { 6209 hnae3_unregister_client(&hns_roce_hw_v2_client); 6210 } 6211 6212 module_init(hns_roce_hw_v2_init); 6213 module_exit(hns_roce_hw_v2_exit); 6214 6215 MODULE_LICENSE("Dual BSD/GPL"); 6216 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6217 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6218 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6219 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6220