1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 if (unlikely(hr_qp->state == IB_QPS_RESET || 376 hr_qp->state == IB_QPS_INIT || 377 hr_qp->state == IB_QPS_RTR)) 378 return -EINVAL; 379 else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 380 return -EIO; 381 382 return 0; 383 } 384 385 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 386 unsigned int *sge_len) 387 { 388 unsigned int valid_num = 0; 389 unsigned int len = 0; 390 int i; 391 392 for (i = 0; i < wr->num_sge; i++) { 393 if (likely(wr->sg_list[i].length)) { 394 len += wr->sg_list[i].length; 395 valid_num++; 396 } 397 } 398 399 *sge_len = len; 400 return valid_num; 401 } 402 403 static __le32 get_immtdata(const struct ib_send_wr *wr) 404 { 405 switch (wr->opcode) { 406 case IB_WR_SEND_WITH_IMM: 407 case IB_WR_RDMA_WRITE_WITH_IMM: 408 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 409 default: 410 return 0; 411 } 412 } 413 414 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 415 const struct ib_send_wr *wr) 416 { 417 u32 ib_op = wr->opcode; 418 419 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 420 return -EINVAL; 421 422 ud_sq_wqe->immtdata = get_immtdata(wr); 423 424 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 425 426 return 0; 427 } 428 429 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 430 struct hns_roce_ah *ah) 431 { 432 struct ib_device *ib_dev = ah->ibah.device; 433 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 434 435 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 436 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 437 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 439 440 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 441 return -EINVAL; 442 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 444 445 ud_sq_wqe->sgid_index = ah->av.gid_index; 446 447 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 448 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 449 450 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 451 return 0; 452 453 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 454 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 455 456 return 0; 457 } 458 459 static inline int set_ud_wqe(struct hns_roce_qp *qp, 460 const struct ib_send_wr *wr, 461 void *wqe, unsigned int *sge_idx, 462 unsigned int owner_bit) 463 { 464 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 465 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 466 unsigned int curr_idx = *sge_idx; 467 unsigned int valid_num_sge; 468 u32 msg_len = 0; 469 int ret; 470 471 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 472 473 ret = set_ud_opcode(ud_sq_wqe, wr); 474 if (WARN_ON(ret)) 475 return ret; 476 477 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 478 479 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 480 !!(wr->send_flags & IB_SEND_SIGNALED)); 481 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 482 !!(wr->send_flags & IB_SEND_SOLICITED)); 483 484 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 485 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 487 curr_idx & (qp->sge.sge_cnt - 1)); 488 489 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 490 qp->qkey : ud_wr(wr)->remote_qkey); 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 492 493 ret = fill_ud_av(ud_sq_wqe, ah); 494 if (ret) 495 return ret; 496 497 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 498 499 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 500 501 /* 502 * The pipeline can sequentially post all valid WQEs into WQ buffer, 503 * including new WQEs waiting for the doorbell to update the PI again. 504 * Therefore, the owner bit of WQE MUST be updated after all fields 505 * and extSGEs have been written into DDR instead of cache. 506 */ 507 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 508 dma_wmb(); 509 510 *sge_idx = curr_idx; 511 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 512 513 return 0; 514 } 515 516 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 517 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 518 const struct ib_send_wr *wr) 519 { 520 u32 ib_op = wr->opcode; 521 int ret = 0; 522 523 rc_sq_wqe->immtdata = get_immtdata(wr); 524 525 switch (ib_op) { 526 case IB_WR_RDMA_READ: 527 case IB_WR_RDMA_WRITE: 528 case IB_WR_RDMA_WRITE_WITH_IMM: 529 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 530 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 531 break; 532 case IB_WR_SEND: 533 case IB_WR_SEND_WITH_IMM: 534 break; 535 case IB_WR_ATOMIC_CMP_AND_SWP: 536 case IB_WR_ATOMIC_FETCH_AND_ADD: 537 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 538 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 539 break; 540 case IB_WR_REG_MR: 541 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 542 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 543 else 544 ret = -EOPNOTSUPP; 545 break; 546 case IB_WR_SEND_WITH_INV: 547 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 548 break; 549 default: 550 ret = -EINVAL; 551 } 552 553 if (unlikely(ret)) 554 return ret; 555 556 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 557 558 return ret; 559 } 560 561 static inline int set_rc_wqe(struct hns_roce_qp *qp, 562 const struct ib_send_wr *wr, 563 void *wqe, unsigned int *sge_idx, 564 unsigned int owner_bit) 565 { 566 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 567 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 568 unsigned int curr_idx = *sge_idx; 569 unsigned int valid_num_sge; 570 u32 msg_len = 0; 571 int ret; 572 573 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 574 575 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 576 577 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 578 if (WARN_ON(ret)) 579 return ret; 580 581 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SO, 582 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 583 584 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 585 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 586 587 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 588 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 589 590 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 591 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { 592 if (msg_len != ATOMIC_WR_LEN) 593 return -EINVAL; 594 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 595 } else if (wr->opcode != IB_WR_REG_MR) { 596 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 597 &curr_idx, valid_num_sge); 598 if (ret) 599 return ret; 600 } 601 602 /* 603 * The pipeline can sequentially post all valid WQEs into WQ buffer, 604 * including new WQEs waiting for the doorbell to update the PI again. 605 * Therefore, the owner bit of WQE MUST be updated after all fields 606 * and extSGEs have been written into DDR instead of cache. 607 */ 608 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 609 dma_wmb(); 610 611 *sge_idx = curr_idx; 612 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 613 614 return ret; 615 } 616 617 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 618 struct hns_roce_qp *qp) 619 { 620 if (unlikely(qp->state == IB_QPS_ERR)) { 621 flush_cqe(hr_dev, qp); 622 } else { 623 struct hns_roce_v2_db sq_db = {}; 624 625 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 626 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 627 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 628 hr_reg_write(&sq_db, DB_SL, qp->sl); 629 630 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 631 } 632 } 633 634 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 635 struct hns_roce_qp *qp) 636 { 637 if (unlikely(qp->state == IB_QPS_ERR)) { 638 flush_cqe(hr_dev, qp); 639 } else { 640 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 641 *qp->rdb.db_record = 642 qp->rq.head & V2_DB_PRODUCER_IDX_M; 643 } else { 644 struct hns_roce_v2_db rq_db = {}; 645 646 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 647 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 648 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 649 650 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 651 qp->rq.db_reg); 652 } 653 } 654 } 655 656 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 657 u64 __iomem *dest) 658 { 659 #define HNS_ROCE_WRITE_TIMES 8 660 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 661 struct hnae3_handle *handle = priv->handle; 662 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 663 int i; 664 665 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 666 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 667 writeq_relaxed(*(val + i), dest + i); 668 } 669 670 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 671 void *wqe) 672 { 673 #define HNS_ROCE_SL_SHIFT 2 674 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 675 676 /* All kinds of DirectWQE have the same header field layout */ 677 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 678 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 679 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 680 qp->sl >> HNS_ROCE_SL_SHIFT); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 682 683 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 684 } 685 686 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 687 const struct ib_send_wr *wr, 688 const struct ib_send_wr **bad_wr) 689 { 690 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 691 struct ib_device *ibdev = &hr_dev->ib_dev; 692 struct hns_roce_qp *qp = to_hr_qp(ibqp); 693 unsigned long flags = 0; 694 unsigned int owner_bit; 695 unsigned int sge_idx; 696 unsigned int wqe_idx; 697 void *wqe = NULL; 698 u32 nreq; 699 int ret; 700 701 spin_lock_irqsave(&qp->sq.lock, flags); 702 703 ret = check_send_valid(hr_dev, qp); 704 if (unlikely(ret)) { 705 *bad_wr = wr; 706 nreq = 0; 707 goto out; 708 } 709 710 sge_idx = qp->next_sge; 711 712 for (nreq = 0; wr; ++nreq, wr = wr->next) { 713 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 714 ret = -ENOMEM; 715 *bad_wr = wr; 716 goto out; 717 } 718 719 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 720 721 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 722 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 723 wr->num_sge, qp->sq.max_gs); 724 ret = -EINVAL; 725 *bad_wr = wr; 726 goto out; 727 } 728 729 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 730 qp->sq.wrid[wqe_idx] = wr->wr_id; 731 owner_bit = 732 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 733 734 /* Corresponding to the QP type, wqe process separately */ 735 if (ibqp->qp_type == IB_QPT_RC) 736 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 737 else 738 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 740 if (unlikely(ret)) { 741 *bad_wr = wr; 742 goto out; 743 } 744 } 745 746 out: 747 if (likely(nreq)) { 748 qp->sq.head += nreq; 749 qp->next_sge = sge_idx; 750 751 if (nreq == 1 && !ret && 752 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 753 write_dwqe(hr_dev, qp, wqe); 754 else 755 update_sq_db(hr_dev, qp); 756 } 757 758 spin_unlock_irqrestore(&qp->sq.lock, flags); 759 760 return ret; 761 } 762 763 static int check_recv_valid(struct hns_roce_dev *hr_dev, 764 struct hns_roce_qp *hr_qp) 765 { 766 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 767 return -EIO; 768 769 if (hr_qp->state == IB_QPS_RESET) 770 return -EINVAL; 771 772 return 0; 773 } 774 775 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 776 u32 max_sge, bool rsv) 777 { 778 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 779 u32 i, cnt; 780 781 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 782 /* Skip zero-length sge */ 783 if (!wr->sg_list[i].length) 784 continue; 785 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 786 cnt++; 787 } 788 789 /* Fill a reserved sge to make hw stop reading remaining segments */ 790 if (rsv) { 791 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 792 dseg[cnt].addr = 0; 793 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 794 } else { 795 /* Clear remaining segments to make ROCEE ignore sges */ 796 if (cnt < max_sge) 797 memset(dseg + cnt, 0, 798 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 799 } 800 } 801 802 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 803 u32 wqe_idx, u32 max_sge) 804 { 805 void *wqe = NULL; 806 807 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 808 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 809 } 810 811 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 812 const struct ib_recv_wr *wr, 813 const struct ib_recv_wr **bad_wr) 814 { 815 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 816 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 817 struct ib_device *ibdev = &hr_dev->ib_dev; 818 u32 wqe_idx, nreq, max_sge; 819 unsigned long flags; 820 int ret; 821 822 spin_lock_irqsave(&hr_qp->rq.lock, flags); 823 824 ret = check_recv_valid(hr_dev, hr_qp); 825 if (unlikely(ret)) { 826 *bad_wr = wr; 827 nreq = 0; 828 goto out; 829 } 830 831 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 832 for (nreq = 0; wr; ++nreq, wr = wr->next) { 833 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 834 hr_qp->ibqp.recv_cq))) { 835 ret = -ENOMEM; 836 *bad_wr = wr; 837 goto out; 838 } 839 840 if (unlikely(wr->num_sge > max_sge)) { 841 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 842 wr->num_sge, max_sge); 843 ret = -EINVAL; 844 *bad_wr = wr; 845 goto out; 846 } 847 848 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 849 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 850 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 851 } 852 853 out: 854 if (likely(nreq)) { 855 hr_qp->rq.head += nreq; 856 857 update_rq_db(hr_dev, hr_qp); 858 } 859 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 860 861 return ret; 862 } 863 864 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 865 { 866 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 867 } 868 869 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 870 { 871 return hns_roce_buf_offset(idx_que->mtr.kmem, 872 n << idx_que->entry_shift); 873 } 874 875 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 876 { 877 /* always called with interrupts disabled. */ 878 spin_lock(&srq->lock); 879 880 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 881 srq->idx_que.tail++; 882 883 spin_unlock(&srq->lock); 884 } 885 886 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 887 { 888 struct hns_roce_idx_que *idx_que = &srq->idx_que; 889 890 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 891 } 892 893 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 894 const struct ib_recv_wr *wr) 895 { 896 struct ib_device *ib_dev = srq->ibsrq.device; 897 898 if (unlikely(wr->num_sge > max_sge)) { 899 ibdev_err(ib_dev, 900 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 901 wr->num_sge, max_sge); 902 return -EINVAL; 903 } 904 905 if (unlikely(hns_roce_srqwq_overflow(srq))) { 906 ibdev_err(ib_dev, 907 "failed to check srqwq status, srqwq is full.\n"); 908 return -ENOMEM; 909 } 910 911 return 0; 912 } 913 914 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 915 { 916 struct hns_roce_idx_que *idx_que = &srq->idx_que; 917 u32 pos; 918 919 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 920 if (unlikely(pos == srq->wqe_cnt)) 921 return -ENOSPC; 922 923 bitmap_set(idx_que->bitmap, pos, 1); 924 *wqe_idx = pos; 925 return 0; 926 } 927 928 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 929 { 930 struct hns_roce_idx_que *idx_que = &srq->idx_que; 931 unsigned int head; 932 __le32 *buf; 933 934 head = idx_que->head & (srq->wqe_cnt - 1); 935 936 buf = get_idx_buf(idx_que, head); 937 *buf = cpu_to_le32(wqe_idx); 938 939 idx_que->head++; 940 } 941 942 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 943 { 944 hr_reg_write(db, DB_TAG, srq->srqn); 945 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 946 hr_reg_write(db, DB_PI, srq->idx_que.head); 947 } 948 949 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 950 const struct ib_recv_wr *wr, 951 const struct ib_recv_wr **bad_wr) 952 { 953 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 954 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 955 struct hns_roce_v2_db srq_db; 956 unsigned long flags; 957 int ret = 0; 958 u32 max_sge; 959 u32 wqe_idx; 960 void *wqe; 961 u32 nreq; 962 963 spin_lock_irqsave(&srq->lock, flags); 964 965 max_sge = srq->max_gs - srq->rsv_sge; 966 for (nreq = 0; wr; ++nreq, wr = wr->next) { 967 ret = check_post_srq_valid(srq, max_sge, wr); 968 if (ret) { 969 *bad_wr = wr; 970 break; 971 } 972 973 ret = get_srq_wqe_idx(srq, &wqe_idx); 974 if (unlikely(ret)) { 975 *bad_wr = wr; 976 break; 977 } 978 979 wqe = get_srq_wqe_buf(srq, wqe_idx); 980 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 981 fill_wqe_idx(srq, wqe_idx); 982 srq->wrid[wqe_idx] = wr->wr_id; 983 } 984 985 if (likely(nreq)) { 986 update_srq_db(&srq_db, srq); 987 988 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 989 } 990 991 spin_unlock_irqrestore(&srq->lock, flags); 992 993 return ret; 994 } 995 996 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 997 unsigned long instance_stage, 998 unsigned long reset_stage) 999 { 1000 /* When hardware reset has been completed once or more, we should stop 1001 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1002 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1003 * stage of soft reset process, we should exit with error, and then 1004 * HNAE3_INIT_CLIENT related process can rollback the operation like 1005 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1006 * process will exit with error to notify NIC driver to reschedule soft 1007 * reset process once again. 1008 */ 1009 hr_dev->is_reset = true; 1010 hr_dev->dis_db = true; 1011 1012 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1013 instance_stage == HNS_ROCE_STATE_INIT) 1014 return CMD_RST_PRC_EBUSY; 1015 1016 return CMD_RST_PRC_SUCCESS; 1017 } 1018 1019 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1020 unsigned long instance_stage, 1021 unsigned long reset_stage) 1022 { 1023 #define HW_RESET_TIMEOUT_US 1000000 1024 #define HW_RESET_SLEEP_US 1000 1025 1026 struct hns_roce_v2_priv *priv = hr_dev->priv; 1027 struct hnae3_handle *handle = priv->handle; 1028 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1029 unsigned long val; 1030 int ret; 1031 1032 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1033 * doorbell to hardware. If now in .init_instance() function, we should 1034 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1035 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1036 * related process can rollback the operation like notifing hardware to 1037 * free resources, HNAE3_INIT_CLIENT related process will exit with 1038 * error to notify NIC driver to reschedule soft reset process once 1039 * again. 1040 */ 1041 hr_dev->dis_db = true; 1042 1043 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1044 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1045 HW_RESET_TIMEOUT_US, false, handle); 1046 if (!ret) 1047 hr_dev->is_reset = true; 1048 1049 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1050 instance_stage == HNS_ROCE_STATE_INIT) 1051 return CMD_RST_PRC_EBUSY; 1052 1053 return CMD_RST_PRC_SUCCESS; 1054 } 1055 1056 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1057 { 1058 struct hns_roce_v2_priv *priv = hr_dev->priv; 1059 struct hnae3_handle *handle = priv->handle; 1060 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1061 1062 /* When software reset is detected at .init_instance() function, we 1063 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1064 * with error. 1065 */ 1066 hr_dev->dis_db = true; 1067 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1068 hr_dev->is_reset = true; 1069 1070 return CMD_RST_PRC_EBUSY; 1071 } 1072 1073 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1074 struct hnae3_handle *handle) 1075 { 1076 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1077 unsigned long instance_stage; /* the current instance stage */ 1078 unsigned long reset_stage; /* the current reset stage */ 1079 unsigned long reset_cnt; 1080 bool sw_resetting; 1081 bool hw_resetting; 1082 1083 /* Get information about reset from NIC driver or RoCE driver itself, 1084 * the meaning of the following variables from NIC driver are described 1085 * as below: 1086 * reset_cnt -- The count value of completed hardware reset. 1087 * hw_resetting -- Whether hardware device is resetting now. 1088 * sw_resetting -- Whether NIC's software reset process is running now. 1089 */ 1090 instance_stage = handle->rinfo.instance_state; 1091 reset_stage = handle->rinfo.reset_state; 1092 reset_cnt = ops->ae_dev_reset_cnt(handle); 1093 if (reset_cnt != hr_dev->reset_cnt) 1094 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1095 reset_stage); 1096 1097 hw_resetting = ops->get_cmdq_stat(handle); 1098 if (hw_resetting) 1099 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1100 reset_stage); 1101 1102 sw_resetting = ops->ae_dev_resetting(handle); 1103 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1104 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1105 1106 return CMD_RST_PRC_OTHERS; 1107 } 1108 1109 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1110 { 1111 struct hns_roce_v2_priv *priv = hr_dev->priv; 1112 struct hnae3_handle *handle = priv->handle; 1113 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1114 1115 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1116 return true; 1117 1118 if (ops->get_hw_reset_stat(handle)) 1119 return true; 1120 1121 if (ops->ae_dev_resetting(handle)) 1122 return true; 1123 1124 return false; 1125 } 1126 1127 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1128 { 1129 struct hns_roce_v2_priv *priv = hr_dev->priv; 1130 u32 status; 1131 1132 if (hr_dev->is_reset) 1133 status = CMD_RST_PRC_SUCCESS; 1134 else 1135 status = check_aedev_reset_status(hr_dev, priv->handle); 1136 1137 *busy = (status == CMD_RST_PRC_EBUSY); 1138 1139 return status == CMD_RST_PRC_OTHERS; 1140 } 1141 1142 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1143 struct hns_roce_v2_cmq_ring *ring) 1144 { 1145 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1146 1147 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1148 &ring->desc_dma_addr, GFP_KERNEL); 1149 if (!ring->desc) 1150 return -ENOMEM; 1151 1152 return 0; 1153 } 1154 1155 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1156 struct hns_roce_v2_cmq_ring *ring) 1157 { 1158 dma_free_coherent(hr_dev->dev, 1159 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1160 ring->desc, ring->desc_dma_addr); 1161 1162 ring->desc_dma_addr = 0; 1163 } 1164 1165 static int init_csq(struct hns_roce_dev *hr_dev, 1166 struct hns_roce_v2_cmq_ring *csq) 1167 { 1168 dma_addr_t dma; 1169 int ret; 1170 1171 csq->desc_num = CMD_CSQ_DESC_NUM; 1172 spin_lock_init(&csq->lock); 1173 csq->flag = TYPE_CSQ; 1174 csq->head = 0; 1175 1176 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1177 if (ret) 1178 return ret; 1179 1180 dma = csq->desc_dma_addr; 1181 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1182 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1183 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1184 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1185 1186 /* Make sure to write CI first and then PI */ 1187 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1188 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1189 1190 return 0; 1191 } 1192 1193 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1194 { 1195 struct hns_roce_v2_priv *priv = hr_dev->priv; 1196 int ret; 1197 1198 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1199 1200 ret = init_csq(hr_dev, &priv->cmq.csq); 1201 if (ret) 1202 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1203 1204 return ret; 1205 } 1206 1207 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1208 { 1209 struct hns_roce_v2_priv *priv = hr_dev->priv; 1210 1211 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1212 } 1213 1214 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1215 enum hns_roce_opcode_type opcode, 1216 bool is_read) 1217 { 1218 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1219 desc->opcode = cpu_to_le16(opcode); 1220 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1221 if (is_read) 1222 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1223 else 1224 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1225 } 1226 1227 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1228 { 1229 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1230 struct hns_roce_v2_priv *priv = hr_dev->priv; 1231 1232 return tail == priv->cmq.csq.head; 1233 } 1234 1235 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1236 { 1237 struct hns_roce_v2_priv *priv = hr_dev->priv; 1238 struct hnae3_handle *handle = priv->handle; 1239 1240 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1241 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1242 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1243 } 1244 1245 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1246 { 1247 struct hns_roce_cmd_errcode errcode_table[] = { 1248 {CMD_EXEC_SUCCESS, 0}, 1249 {CMD_NO_AUTH, -EPERM}, 1250 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1251 {CMD_CRQ_FULL, -EXFULL}, 1252 {CMD_NEXT_ERR, -ENOSR}, 1253 {CMD_NOT_EXEC, -ENOTBLK}, 1254 {CMD_PARA_ERR, -EINVAL}, 1255 {CMD_RESULT_ERR, -ERANGE}, 1256 {CMD_TIMEOUT, -ETIME}, 1257 {CMD_HILINK_ERR, -ENOLINK}, 1258 {CMD_INFO_ILLEGAL, -ENXIO}, 1259 {CMD_INVALID, -EBADR}, 1260 }; 1261 u16 i; 1262 1263 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1264 if (desc_ret == errcode_table[i].return_status) 1265 return errcode_table[i].errno; 1266 return -EIO; 1267 } 1268 1269 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1270 struct hns_roce_cmq_desc *desc, int num) 1271 { 1272 struct hns_roce_v2_priv *priv = hr_dev->priv; 1273 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1274 u32 timeout = 0; 1275 u16 desc_ret; 1276 u32 tail; 1277 int ret; 1278 int i; 1279 1280 spin_lock_bh(&csq->lock); 1281 1282 tail = csq->head; 1283 1284 for (i = 0; i < num; i++) { 1285 csq->desc[csq->head++] = desc[i]; 1286 if (csq->head == csq->desc_num) 1287 csq->head = 0; 1288 } 1289 1290 /* Write to hardware */ 1291 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1292 1293 do { 1294 if (hns_roce_cmq_csq_done(hr_dev)) 1295 break; 1296 udelay(1); 1297 } while (++timeout < priv->cmq.tx_timeout); 1298 1299 if (hns_roce_cmq_csq_done(hr_dev)) { 1300 ret = 0; 1301 for (i = 0; i < num; i++) { 1302 /* check the result of hardware write back */ 1303 desc[i] = csq->desc[tail++]; 1304 if (tail == csq->desc_num) 1305 tail = 0; 1306 1307 desc_ret = le16_to_cpu(desc[i].retval); 1308 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1309 continue; 1310 1311 dev_err_ratelimited(hr_dev->dev, 1312 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1313 desc->opcode, desc_ret); 1314 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1315 } 1316 } else { 1317 /* FW/HW reset or incorrect number of desc */ 1318 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1319 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1320 csq->head, tail); 1321 csq->head = tail; 1322 1323 update_cmdq_status(hr_dev); 1324 1325 ret = -EAGAIN; 1326 } 1327 1328 spin_unlock_bh(&csq->lock); 1329 1330 return ret; 1331 } 1332 1333 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1334 struct hns_roce_cmq_desc *desc, int num) 1335 { 1336 bool busy; 1337 int ret; 1338 1339 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1340 return -EIO; 1341 1342 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1343 return busy ? -EBUSY : 0; 1344 1345 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1346 if (ret) { 1347 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1348 return busy ? -EBUSY : 0; 1349 } 1350 1351 return ret; 1352 } 1353 1354 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1355 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1356 { 1357 struct hns_roce_cmd_mailbox *mbox; 1358 int ret; 1359 1360 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1361 if (IS_ERR(mbox)) 1362 return PTR_ERR(mbox); 1363 1364 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1365 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1366 return ret; 1367 } 1368 1369 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1370 { 1371 struct hns_roce_query_version *resp; 1372 struct hns_roce_cmq_desc desc; 1373 int ret; 1374 1375 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1376 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1377 if (ret) 1378 return ret; 1379 1380 resp = (struct hns_roce_query_version *)desc.data; 1381 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1382 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1383 1384 return 0; 1385 } 1386 1387 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1388 struct hnae3_handle *handle) 1389 { 1390 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1391 unsigned long end; 1392 1393 hr_dev->dis_db = true; 1394 1395 dev_warn(hr_dev->dev, 1396 "func clear is pending, device in resetting state.\n"); 1397 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1398 while (end) { 1399 if (!ops->get_hw_reset_stat(handle)) { 1400 hr_dev->is_reset = true; 1401 dev_info(hr_dev->dev, 1402 "func clear success after reset.\n"); 1403 return; 1404 } 1405 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1406 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1407 } 1408 1409 dev_warn(hr_dev->dev, "func clear failed.\n"); 1410 } 1411 1412 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1413 struct hnae3_handle *handle) 1414 { 1415 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1416 unsigned long end; 1417 1418 hr_dev->dis_db = true; 1419 1420 dev_warn(hr_dev->dev, 1421 "func clear is pending, device in resetting state.\n"); 1422 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1423 while (end) { 1424 if (ops->ae_dev_reset_cnt(handle) != 1425 hr_dev->reset_cnt) { 1426 hr_dev->is_reset = true; 1427 dev_info(hr_dev->dev, 1428 "func clear success after sw reset\n"); 1429 return; 1430 } 1431 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1432 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1433 } 1434 1435 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1436 } 1437 1438 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1439 int flag) 1440 { 1441 struct hns_roce_v2_priv *priv = hr_dev->priv; 1442 struct hnae3_handle *handle = priv->handle; 1443 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1444 1445 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1446 hr_dev->dis_db = true; 1447 hr_dev->is_reset = true; 1448 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1449 return; 1450 } 1451 1452 if (ops->get_hw_reset_stat(handle)) { 1453 func_clr_hw_resetting_state(hr_dev, handle); 1454 return; 1455 } 1456 1457 if (ops->ae_dev_resetting(handle) && 1458 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1459 func_clr_sw_resetting_state(hr_dev, handle); 1460 return; 1461 } 1462 1463 if (retval && !flag) 1464 dev_warn(hr_dev->dev, 1465 "func clear read failed, ret = %d.\n", retval); 1466 1467 dev_warn(hr_dev->dev, "func clear failed.\n"); 1468 } 1469 1470 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1471 { 1472 bool fclr_write_fail_flag = false; 1473 struct hns_roce_func_clear *resp; 1474 struct hns_roce_cmq_desc desc; 1475 unsigned long end; 1476 int ret = 0; 1477 1478 if (check_device_is_in_reset(hr_dev)) 1479 goto out; 1480 1481 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1482 resp = (struct hns_roce_func_clear *)desc.data; 1483 resp->rst_funcid_en = cpu_to_le32(vf_id); 1484 1485 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1486 if (ret) { 1487 fclr_write_fail_flag = true; 1488 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1489 ret); 1490 goto out; 1491 } 1492 1493 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1494 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1495 while (end) { 1496 if (check_device_is_in_reset(hr_dev)) 1497 goto out; 1498 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1499 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1500 1501 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1502 true); 1503 1504 resp->rst_funcid_en = cpu_to_le32(vf_id); 1505 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1506 if (ret) 1507 continue; 1508 1509 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1510 if (vf_id == 0) 1511 hr_dev->is_reset = true; 1512 return; 1513 } 1514 } 1515 1516 out: 1517 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1518 } 1519 1520 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1521 { 1522 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1523 struct hns_roce_cmq_desc desc[2]; 1524 struct hns_roce_cmq_req *req_a; 1525 1526 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1527 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1528 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1529 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1530 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1531 1532 return hns_roce_cmq_send(hr_dev, desc, 2); 1533 } 1534 1535 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1536 { 1537 int ret; 1538 int i; 1539 1540 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1541 return; 1542 1543 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1544 __hns_roce_function_clear(hr_dev, i); 1545 1546 if (i == 0) 1547 continue; 1548 1549 ret = hns_roce_free_vf_resource(hr_dev, i); 1550 if (ret) 1551 ibdev_err(&hr_dev->ib_dev, 1552 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1553 i, ret); 1554 } 1555 } 1556 1557 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1558 { 1559 struct hns_roce_cmq_desc desc; 1560 int ret; 1561 1562 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1563 false); 1564 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1565 if (ret) 1566 ibdev_err(&hr_dev->ib_dev, 1567 "failed to clear extended doorbell info, ret = %d.\n", 1568 ret); 1569 1570 return ret; 1571 } 1572 1573 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1574 { 1575 struct hns_roce_query_fw_info *resp; 1576 struct hns_roce_cmq_desc desc; 1577 int ret; 1578 1579 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1580 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1581 if (ret) 1582 return ret; 1583 1584 resp = (struct hns_roce_query_fw_info *)desc.data; 1585 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1586 1587 return 0; 1588 } 1589 1590 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1591 { 1592 struct hns_roce_cmq_desc desc; 1593 int ret; 1594 1595 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1596 hr_dev->func_num = 1; 1597 return 0; 1598 } 1599 1600 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1601 true); 1602 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1603 if (ret) { 1604 hr_dev->func_num = 1; 1605 return ret; 1606 } 1607 1608 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1609 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1610 1611 return 0; 1612 } 1613 1614 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1615 u64 *stats, u32 port, int *num_counters) 1616 { 1617 #define CNT_PER_DESC 3 1618 struct hns_roce_cmq_desc *desc; 1619 int bd_idx, cnt_idx; 1620 __le64 *cnt_data; 1621 int desc_num; 1622 int ret; 1623 int i; 1624 1625 if (port > hr_dev->caps.num_ports) 1626 return -EINVAL; 1627 1628 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1629 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1630 if (!desc) 1631 return -ENOMEM; 1632 1633 for (i = 0; i < desc_num; i++) { 1634 hns_roce_cmq_setup_basic_desc(&desc[i], 1635 HNS_ROCE_OPC_QUERY_COUNTER, true); 1636 if (i != desc_num - 1) 1637 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1638 } 1639 1640 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1641 if (ret) { 1642 ibdev_err(&hr_dev->ib_dev, 1643 "failed to get counter, ret = %d.\n", ret); 1644 goto err_out; 1645 } 1646 1647 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1648 bd_idx = i / CNT_PER_DESC; 1649 if (bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC && 1650 !(desc[bd_idx].flag & cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT))) 1651 break; 1652 1653 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1654 cnt_idx = i % CNT_PER_DESC; 1655 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1656 } 1657 *num_counters = i; 1658 1659 err_out: 1660 kfree(desc); 1661 return ret; 1662 } 1663 1664 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1665 { 1666 struct hns_roce_cmq_desc desc; 1667 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1668 u32 clock_cycles_of_1us; 1669 1670 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1671 false); 1672 1673 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1674 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1675 else 1676 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1677 1678 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1679 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1680 1681 return hns_roce_cmq_send(hr_dev, &desc, 1); 1682 } 1683 1684 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1685 { 1686 struct hns_roce_cmq_desc desc[2]; 1687 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1688 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1689 struct hns_roce_caps *caps = &hr_dev->caps; 1690 enum hns_roce_opcode_type opcode; 1691 u32 func_num; 1692 int ret; 1693 1694 if (is_vf) { 1695 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1696 func_num = 1; 1697 } else { 1698 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1699 func_num = hr_dev->func_num; 1700 } 1701 1702 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1703 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1704 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1705 1706 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1707 if (ret) 1708 return ret; 1709 1710 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1711 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1712 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1713 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1714 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1715 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1716 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1717 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1718 1719 if (is_vf) { 1720 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1721 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1722 func_num; 1723 } else { 1724 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1725 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1726 func_num; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1733 { 1734 struct hns_roce_cmq_desc desc; 1735 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1736 struct hns_roce_caps *caps = &hr_dev->caps; 1737 int ret; 1738 1739 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1740 true); 1741 1742 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1743 if (ret) 1744 return ret; 1745 1746 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1747 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1748 1749 return 0; 1750 } 1751 1752 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1753 { 1754 struct device *dev = hr_dev->dev; 1755 int ret; 1756 1757 ret = load_func_res_caps(hr_dev, false); 1758 if (ret) { 1759 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1760 return ret; 1761 } 1762 1763 ret = load_pf_timer_res_caps(hr_dev); 1764 if (ret) 1765 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1766 ret); 1767 1768 return ret; 1769 } 1770 1771 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1772 { 1773 struct device *dev = hr_dev->dev; 1774 int ret; 1775 1776 ret = load_func_res_caps(hr_dev, true); 1777 if (ret) 1778 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1779 1780 return ret; 1781 } 1782 1783 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1784 u32 vf_id) 1785 { 1786 struct hns_roce_vf_switch *swt; 1787 struct hns_roce_cmq_desc desc; 1788 int ret; 1789 1790 swt = (struct hns_roce_vf_switch *)desc.data; 1791 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1792 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1793 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1794 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1795 if (ret) 1796 return ret; 1797 1798 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1799 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1800 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1801 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1802 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1803 1804 return hns_roce_cmq_send(hr_dev, &desc, 1); 1805 } 1806 1807 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1808 { 1809 u32 vf_id; 1810 int ret; 1811 1812 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1813 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1814 if (ret) 1815 return ret; 1816 } 1817 return 0; 1818 } 1819 1820 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1821 { 1822 struct hns_roce_cmq_desc desc[2]; 1823 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1824 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1825 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1826 struct hns_roce_caps *caps = &hr_dev->caps; 1827 1828 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1829 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1830 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1831 1832 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1833 1834 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1835 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1836 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1837 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1838 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1839 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1840 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1841 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1842 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1843 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1844 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1845 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1846 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1847 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1848 1849 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1850 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1851 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1852 vf_id * caps->gmv_bt_num); 1853 } else { 1854 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1855 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1856 vf_id * caps->sgid_bt_num); 1857 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1858 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1859 vf_id * caps->smac_bt_num); 1860 } 1861 1862 return hns_roce_cmq_send(hr_dev, desc, 2); 1863 } 1864 1865 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1866 { 1867 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1868 u32 vf_id; 1869 int ret; 1870 1871 for (vf_id = 0; vf_id < func_num; vf_id++) { 1872 ret = config_vf_hem_resource(hr_dev, vf_id); 1873 if (ret) { 1874 dev_err(hr_dev->dev, 1875 "failed to config vf-%u hem res, ret = %d.\n", 1876 vf_id, ret); 1877 return ret; 1878 } 1879 } 1880 1881 return 0; 1882 } 1883 1884 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1885 { 1886 struct hns_roce_cmq_desc desc; 1887 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1888 struct hns_roce_caps *caps = &hr_dev->caps; 1889 1890 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1891 1892 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1893 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1894 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1895 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1896 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1897 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1898 1899 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1900 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1901 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1902 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1903 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1904 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1905 1906 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1907 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1908 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1909 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1910 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1911 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1912 1913 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1914 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1915 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1916 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1917 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1918 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1919 1920 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1921 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1922 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1923 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1924 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1925 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1926 1927 return hns_roce_cmq_send(hr_dev, &desc, 1); 1928 } 1929 1930 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1931 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1932 { 1933 u64 obj_per_chunk; 1934 u64 bt_chunk_size = PAGE_SIZE; 1935 u64 buf_chunk_size = PAGE_SIZE; 1936 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1937 1938 *buf_page_size = 0; 1939 *bt_page_size = 0; 1940 1941 switch (hop_num) { 1942 case 3: 1943 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1944 (bt_chunk_size / BA_BYTE_LEN) * 1945 (bt_chunk_size / BA_BYTE_LEN) * 1946 obj_per_chunk_default; 1947 break; 1948 case 2: 1949 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1950 (bt_chunk_size / BA_BYTE_LEN) * 1951 obj_per_chunk_default; 1952 break; 1953 case 1: 1954 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1955 obj_per_chunk_default; 1956 break; 1957 case HNS_ROCE_HOP_NUM_0: 1958 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1959 break; 1960 default: 1961 pr_err("table %u not support hop_num = %u!\n", hem_type, 1962 hop_num); 1963 return; 1964 } 1965 1966 if (hem_type >= HEM_TYPE_MTT) 1967 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1968 else 1969 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1970 } 1971 1972 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 1973 { 1974 struct hns_roce_caps *caps = &hr_dev->caps; 1975 1976 /* EQ */ 1977 caps->eqe_ba_pg_sz = 0; 1978 caps->eqe_buf_pg_sz = 0; 1979 1980 /* Link Table */ 1981 caps->llm_buf_pg_sz = 0; 1982 1983 /* MR */ 1984 caps->mpt_ba_pg_sz = 0; 1985 caps->mpt_buf_pg_sz = 0; 1986 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 1987 caps->pbl_buf_pg_sz = 0; 1988 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1989 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1990 HEM_TYPE_MTPT); 1991 1992 /* QP */ 1993 caps->qpc_ba_pg_sz = 0; 1994 caps->qpc_buf_pg_sz = 0; 1995 caps->qpc_timer_ba_pg_sz = 0; 1996 caps->qpc_timer_buf_pg_sz = 0; 1997 caps->sccc_ba_pg_sz = 0; 1998 caps->sccc_buf_pg_sz = 0; 1999 caps->mtt_ba_pg_sz = 0; 2000 caps->mtt_buf_pg_sz = 0; 2001 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2002 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2003 HEM_TYPE_QPC); 2004 2005 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2006 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2007 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2008 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2009 2010 /* CQ */ 2011 caps->cqc_ba_pg_sz = 0; 2012 caps->cqc_buf_pg_sz = 0; 2013 caps->cqc_timer_ba_pg_sz = 0; 2014 caps->cqc_timer_buf_pg_sz = 0; 2015 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2016 caps->cqe_buf_pg_sz = 0; 2017 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2018 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2019 HEM_TYPE_CQC); 2020 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2021 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2022 2023 /* SRQ */ 2024 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2025 caps->srqc_ba_pg_sz = 0; 2026 caps->srqc_buf_pg_sz = 0; 2027 caps->srqwqe_ba_pg_sz = 0; 2028 caps->srqwqe_buf_pg_sz = 0; 2029 caps->idx_ba_pg_sz = 0; 2030 caps->idx_buf_pg_sz = 0; 2031 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2032 caps->srqc_hop_num, caps->srqc_bt_num, 2033 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2034 HEM_TYPE_SRQC); 2035 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2036 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2037 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2038 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2039 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2040 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2041 } 2042 2043 /* GMV */ 2044 caps->gmv_ba_pg_sz = 0; 2045 caps->gmv_buf_pg_sz = 0; 2046 } 2047 2048 /* Apply all loaded caps before setting to hardware */ 2049 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2050 { 2051 struct hns_roce_caps *caps = &hr_dev->caps; 2052 struct hns_roce_v2_priv *priv = hr_dev->priv; 2053 2054 /* The following configurations don't need to be got from firmware. */ 2055 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2056 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2057 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2058 2059 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2060 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2061 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2062 2063 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2064 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2065 2066 if (!caps->num_comp_vectors) 2067 caps->num_comp_vectors = 2068 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2069 (u32)priv->handle->rinfo.num_vectors - 2070 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2071 2072 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2073 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2074 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2075 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2076 2077 /* The following configurations will be overwritten */ 2078 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2079 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2080 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2081 2082 /* The following configurations are not got from firmware */ 2083 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2084 2085 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2086 caps->gid_table_len[0] = caps->gmv_bt_num * 2087 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2088 2089 caps->gmv_entry_num = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 2090 caps->gmv_entry_sz); 2091 } else { 2092 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2093 2094 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2095 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2096 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2097 caps->gid_table_len[0] /= func_num; 2098 } 2099 2100 if (hr_dev->is_vf) { 2101 caps->default_aeq_arm_st = 0x3; 2102 caps->default_ceq_arm_st = 0x3; 2103 caps->default_ceq_max_cnt = 0x1; 2104 caps->default_ceq_period = 0x10; 2105 caps->default_aeq_max_cnt = 0x1; 2106 caps->default_aeq_period = 0x10; 2107 } 2108 2109 set_hem_page_size(hr_dev); 2110 } 2111 2112 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2113 { 2114 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2115 struct hns_roce_caps *caps = &hr_dev->caps; 2116 struct hns_roce_query_pf_caps_a *resp_a; 2117 struct hns_roce_query_pf_caps_b *resp_b; 2118 struct hns_roce_query_pf_caps_c *resp_c; 2119 struct hns_roce_query_pf_caps_d *resp_d; 2120 struct hns_roce_query_pf_caps_e *resp_e; 2121 enum hns_roce_opcode_type cmd; 2122 int ctx_hop_num; 2123 int pbl_hop_num; 2124 int ret; 2125 int i; 2126 2127 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2128 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2129 2130 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2131 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2132 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2133 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2134 else 2135 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2136 } 2137 2138 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2139 if (ret) 2140 return ret; 2141 2142 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2143 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2144 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2145 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2146 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2147 2148 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2149 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2150 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2151 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2152 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2153 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2154 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2155 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2156 caps->num_other_vectors = resp_a->num_other_vectors; 2157 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2158 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2159 2160 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2161 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2162 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2163 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2164 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2165 caps->idx_entry_sz = resp_b->idx_entry_sz; 2166 caps->sccc_sz = resp_b->sccc_sz; 2167 caps->max_mtu = resp_b->max_mtu; 2168 caps->min_cqes = resp_b->min_cqes; 2169 caps->min_wqes = resp_b->min_wqes; 2170 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2171 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2172 caps->phy_num_uars = resp_b->phy_num_uars; 2173 ctx_hop_num = resp_b->ctx_hop_num; 2174 pbl_hop_num = resp_b->pbl_hop_num; 2175 2176 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2177 2178 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2179 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2180 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2181 2182 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2183 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2184 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2185 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2186 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2187 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2188 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2189 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2190 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2191 2192 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2193 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2194 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2195 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2196 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2197 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2198 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2199 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2200 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2201 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2202 2203 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2204 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2205 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2206 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2207 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2208 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2209 2210 caps->qpc_hop_num = ctx_hop_num; 2211 caps->sccc_hop_num = ctx_hop_num; 2212 caps->srqc_hop_num = ctx_hop_num; 2213 caps->cqc_hop_num = ctx_hop_num; 2214 caps->mpt_hop_num = ctx_hop_num; 2215 caps->mtt_hop_num = pbl_hop_num; 2216 caps->cqe_hop_num = pbl_hop_num; 2217 caps->srqwqe_hop_num = pbl_hop_num; 2218 caps->idx_hop_num = pbl_hop_num; 2219 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2220 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2221 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2222 2223 if (!(caps->page_size_cap & PAGE_SIZE)) 2224 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2225 2226 if (!hr_dev->is_vf) { 2227 caps->cqe_sz = resp_a->cqe_sz; 2228 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2229 caps->default_aeq_arm_st = 2230 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2231 caps->default_ceq_arm_st = 2232 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2233 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2234 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2235 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2236 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2237 } 2238 2239 return 0; 2240 } 2241 2242 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2243 { 2244 struct hns_roce_cmq_desc desc; 2245 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2246 2247 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2248 false); 2249 2250 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2251 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2252 2253 return hns_roce_cmq_send(hr_dev, &desc, 1); 2254 } 2255 2256 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2257 { 2258 struct hns_roce_caps *caps = &hr_dev->caps; 2259 int ret; 2260 2261 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2262 return 0; 2263 2264 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2265 caps->qpc_sz); 2266 if (ret) { 2267 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2268 return ret; 2269 } 2270 2271 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2272 caps->sccc_sz); 2273 if (ret) 2274 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2275 2276 return ret; 2277 } 2278 2279 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2280 { 2281 struct device *dev = hr_dev->dev; 2282 int ret; 2283 2284 hr_dev->func_num = 1; 2285 2286 ret = hns_roce_query_caps(hr_dev); 2287 if (ret) { 2288 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2289 return ret; 2290 } 2291 2292 ret = hns_roce_query_vf_resource(hr_dev); 2293 if (ret) { 2294 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2295 return ret; 2296 } 2297 2298 apply_func_caps(hr_dev); 2299 2300 ret = hns_roce_v2_set_bt(hr_dev); 2301 if (ret) 2302 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2303 2304 return ret; 2305 } 2306 2307 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2308 { 2309 struct device *dev = hr_dev->dev; 2310 int ret; 2311 2312 ret = hns_roce_query_func_info(hr_dev); 2313 if (ret) { 2314 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2315 return ret; 2316 } 2317 2318 ret = hns_roce_config_global_param(hr_dev); 2319 if (ret) { 2320 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2321 return ret; 2322 } 2323 2324 ret = hns_roce_set_vf_switch_param(hr_dev); 2325 if (ret) { 2326 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2327 return ret; 2328 } 2329 2330 ret = hns_roce_query_caps(hr_dev); 2331 if (ret) { 2332 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2333 return ret; 2334 } 2335 2336 ret = hns_roce_query_pf_resource(hr_dev); 2337 if (ret) { 2338 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2339 return ret; 2340 } 2341 2342 apply_func_caps(hr_dev); 2343 2344 ret = hns_roce_alloc_vf_resource(hr_dev); 2345 if (ret) { 2346 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2347 return ret; 2348 } 2349 2350 ret = hns_roce_v2_set_bt(hr_dev); 2351 if (ret) { 2352 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2353 return ret; 2354 } 2355 2356 /* Configure the size of QPC, SCCC, etc. */ 2357 return hns_roce_config_entry_size(hr_dev); 2358 } 2359 2360 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2361 { 2362 struct device *dev = hr_dev->dev; 2363 int ret; 2364 2365 ret = hns_roce_cmq_query_hw_info(hr_dev); 2366 if (ret) { 2367 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2368 return ret; 2369 } 2370 2371 ret = hns_roce_query_fw_ver(hr_dev); 2372 if (ret) { 2373 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2374 return ret; 2375 } 2376 2377 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2378 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2379 2380 if (hr_dev->is_vf) 2381 return hns_roce_v2_vf_profile(hr_dev); 2382 else 2383 return hns_roce_v2_pf_profile(hr_dev); 2384 } 2385 2386 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2387 { 2388 u32 i, next_ptr, page_num; 2389 __le64 *entry = cfg_buf; 2390 dma_addr_t addr; 2391 u64 val; 2392 2393 page_num = data_buf->npages; 2394 for (i = 0; i < page_num; i++) { 2395 addr = hns_roce_buf_page(data_buf, i); 2396 if (i == (page_num - 1)) 2397 next_ptr = 0; 2398 else 2399 next_ptr = i + 1; 2400 2401 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2402 entry[i] = cpu_to_le64(val); 2403 } 2404 } 2405 2406 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2407 struct hns_roce_link_table *table) 2408 { 2409 struct hns_roce_cmq_desc desc[2]; 2410 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2411 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2412 struct hns_roce_buf *buf = table->buf; 2413 enum hns_roce_opcode_type opcode; 2414 dma_addr_t addr; 2415 2416 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2417 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2418 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2419 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2420 2421 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2422 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2423 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2424 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2425 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2426 2427 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2428 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2429 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2430 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2431 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2432 2433 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2434 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2435 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2436 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2437 2438 return hns_roce_cmq_send(hr_dev, desc, 2); 2439 } 2440 2441 static struct hns_roce_link_table * 2442 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2443 { 2444 u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num; 2445 struct hns_roce_v2_priv *priv = hr_dev->priv; 2446 struct hns_roce_link_table *link_tbl; 2447 u32 pg_shift, size, min_size; 2448 2449 link_tbl = &priv->ext_llm; 2450 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2451 size = hr_dev->caps.num_qps * hr_dev->func_num * 2452 HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2453 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift; 2454 2455 /* Alloc data table */ 2456 size = max(size, min_size); 2457 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2458 if (IS_ERR(link_tbl->buf)) 2459 return ERR_PTR(-ENOMEM); 2460 2461 /* Alloc config table */ 2462 size = link_tbl->buf->npages * sizeof(u64); 2463 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2464 &link_tbl->table.map, 2465 GFP_KERNEL); 2466 if (!link_tbl->table.buf) { 2467 hns_roce_buf_free(hr_dev, link_tbl->buf); 2468 return ERR_PTR(-ENOMEM); 2469 } 2470 2471 return link_tbl; 2472 } 2473 2474 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2475 struct hns_roce_link_table *tbl) 2476 { 2477 if (tbl->buf) { 2478 u32 size = tbl->buf->npages * sizeof(u64); 2479 2480 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2481 tbl->table.map); 2482 } 2483 2484 hns_roce_buf_free(hr_dev, tbl->buf); 2485 } 2486 2487 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2488 { 2489 struct hns_roce_link_table *link_tbl; 2490 int ret; 2491 2492 link_tbl = alloc_link_table_buf(hr_dev); 2493 if (IS_ERR(link_tbl)) 2494 return -ENOMEM; 2495 2496 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2497 ret = -EINVAL; 2498 goto err_alloc; 2499 } 2500 2501 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2502 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2503 if (ret) 2504 goto err_alloc; 2505 2506 return 0; 2507 2508 err_alloc: 2509 free_link_table_buf(hr_dev, link_tbl); 2510 return ret; 2511 } 2512 2513 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2514 { 2515 struct hns_roce_v2_priv *priv = hr_dev->priv; 2516 2517 free_link_table_buf(hr_dev, &priv->ext_llm); 2518 } 2519 2520 static void free_dip_list(struct hns_roce_dev *hr_dev) 2521 { 2522 struct hns_roce_dip *hr_dip; 2523 struct hns_roce_dip *tmp; 2524 unsigned long flags; 2525 2526 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2527 2528 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2529 list_del(&hr_dip->node); 2530 kfree(hr_dip); 2531 } 2532 2533 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2534 } 2535 2536 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2537 { 2538 struct hns_roce_v2_priv *priv = hr_dev->priv; 2539 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2540 struct ib_device *ibdev = &hr_dev->ib_dev; 2541 struct hns_roce_pd *hr_pd; 2542 struct ib_pd *pd; 2543 2544 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2545 if (ZERO_OR_NULL_PTR(hr_pd)) 2546 return NULL; 2547 pd = &hr_pd->ibpd; 2548 pd->device = ibdev; 2549 2550 if (hns_roce_alloc_pd(pd, NULL)) { 2551 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2552 kfree(hr_pd); 2553 return NULL; 2554 } 2555 free_mr->rsv_pd = to_hr_pd(pd); 2556 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2557 free_mr->rsv_pd->ibpd.uobject = NULL; 2558 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2559 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2560 2561 return pd; 2562 } 2563 2564 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2565 { 2566 struct hns_roce_v2_priv *priv = hr_dev->priv; 2567 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2568 struct ib_device *ibdev = &hr_dev->ib_dev; 2569 struct ib_cq_init_attr cq_init_attr = {}; 2570 struct hns_roce_cq *hr_cq; 2571 struct ib_cq *cq; 2572 2573 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2574 2575 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2576 if (ZERO_OR_NULL_PTR(hr_cq)) 2577 return NULL; 2578 2579 cq = &hr_cq->ib_cq; 2580 cq->device = ibdev; 2581 2582 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2583 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2584 kfree(hr_cq); 2585 return NULL; 2586 } 2587 free_mr->rsv_cq = to_hr_cq(cq); 2588 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2589 free_mr->rsv_cq->ib_cq.uobject = NULL; 2590 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2591 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2592 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2593 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2594 2595 return cq; 2596 } 2597 2598 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2599 struct ib_qp_init_attr *init_attr, int i) 2600 { 2601 struct hns_roce_v2_priv *priv = hr_dev->priv; 2602 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2603 struct ib_device *ibdev = &hr_dev->ib_dev; 2604 struct hns_roce_qp *hr_qp; 2605 struct ib_qp *qp; 2606 int ret; 2607 2608 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2609 if (ZERO_OR_NULL_PTR(hr_qp)) 2610 return -ENOMEM; 2611 2612 qp = &hr_qp->ibqp; 2613 qp->device = ibdev; 2614 2615 ret = hns_roce_create_qp(qp, init_attr, NULL); 2616 if (ret) { 2617 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2618 kfree(hr_qp); 2619 return ret; 2620 } 2621 2622 free_mr->rsv_qp[i] = hr_qp; 2623 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2624 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2625 2626 return 0; 2627 } 2628 2629 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2630 { 2631 struct hns_roce_v2_priv *priv = hr_dev->priv; 2632 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2633 struct ib_qp *qp; 2634 int i; 2635 2636 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2637 if (free_mr->rsv_qp[i]) { 2638 qp = &free_mr->rsv_qp[i]->ibqp; 2639 hns_roce_v2_destroy_qp(qp, NULL); 2640 kfree(free_mr->rsv_qp[i]); 2641 free_mr->rsv_qp[i] = NULL; 2642 } 2643 } 2644 2645 if (free_mr->rsv_cq) { 2646 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2647 kfree(free_mr->rsv_cq); 2648 free_mr->rsv_cq = NULL; 2649 } 2650 2651 if (free_mr->rsv_pd) { 2652 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2653 kfree(free_mr->rsv_pd); 2654 free_mr->rsv_pd = NULL; 2655 } 2656 } 2657 2658 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2659 { 2660 struct hns_roce_v2_priv *priv = hr_dev->priv; 2661 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2662 struct ib_qp_init_attr qp_init_attr = {}; 2663 struct ib_pd *pd; 2664 struct ib_cq *cq; 2665 int ret; 2666 int i; 2667 2668 pd = free_mr_init_pd(hr_dev); 2669 if (!pd) 2670 return -ENOMEM; 2671 2672 cq = free_mr_init_cq(hr_dev); 2673 if (!cq) { 2674 ret = -ENOMEM; 2675 goto create_failed_cq; 2676 } 2677 2678 qp_init_attr.qp_type = IB_QPT_RC; 2679 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2680 qp_init_attr.send_cq = cq; 2681 qp_init_attr.recv_cq = cq; 2682 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2683 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2684 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2685 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2686 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2687 2688 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2689 if (ret) 2690 goto create_failed_qp; 2691 } 2692 2693 return 0; 2694 2695 create_failed_qp: 2696 for (i--; i >= 0; i--) { 2697 hns_roce_v2_destroy_qp(&free_mr->rsv_qp[i]->ibqp, NULL); 2698 kfree(free_mr->rsv_qp[i]); 2699 } 2700 hns_roce_destroy_cq(cq, NULL); 2701 kfree(cq); 2702 2703 create_failed_cq: 2704 hns_roce_dealloc_pd(pd, NULL); 2705 kfree(pd); 2706 2707 return ret; 2708 } 2709 2710 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2711 struct ib_qp_attr *attr, int sl_num) 2712 { 2713 struct hns_roce_v2_priv *priv = hr_dev->priv; 2714 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2715 struct ib_device *ibdev = &hr_dev->ib_dev; 2716 struct hns_roce_qp *hr_qp; 2717 int loopback; 2718 int mask; 2719 int ret; 2720 2721 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2722 hr_qp->free_mr_en = 1; 2723 hr_qp->ibqp.device = ibdev; 2724 hr_qp->ibqp.qp_type = IB_QPT_RC; 2725 2726 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2727 attr->qp_state = IB_QPS_INIT; 2728 attr->port_num = 1; 2729 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2730 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2731 IB_QPS_INIT, NULL); 2732 if (ret) { 2733 ibdev_err_ratelimited(ibdev, "failed to modify qp to init, ret = %d.\n", 2734 ret); 2735 return ret; 2736 } 2737 2738 loopback = hr_dev->loop_idc; 2739 /* Set qpc lbi = 1 incidate loopback IO */ 2740 hr_dev->loop_idc = 1; 2741 2742 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2743 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2744 attr->qp_state = IB_QPS_RTR; 2745 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2746 attr->path_mtu = IB_MTU_256; 2747 attr->dest_qp_num = hr_qp->qpn; 2748 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2749 2750 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2751 2752 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2753 IB_QPS_RTR, NULL); 2754 hr_dev->loop_idc = loopback; 2755 if (ret) { 2756 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2757 ret); 2758 return ret; 2759 } 2760 2761 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2762 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2763 attr->qp_state = IB_QPS_RTS; 2764 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2765 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2766 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2767 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2768 IB_QPS_RTS, NULL); 2769 if (ret) 2770 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2771 ret); 2772 2773 return ret; 2774 } 2775 2776 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2777 { 2778 struct hns_roce_v2_priv *priv = hr_dev->priv; 2779 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2780 struct ib_qp_attr attr = {}; 2781 int ret; 2782 int i; 2783 2784 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2785 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2786 rdma_ah_set_port_num(&attr.ah_attr, 1); 2787 2788 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2789 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2790 if (ret) 2791 return ret; 2792 } 2793 2794 return 0; 2795 } 2796 2797 static int free_mr_init(struct hns_roce_dev *hr_dev) 2798 { 2799 struct hns_roce_v2_priv *priv = hr_dev->priv; 2800 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2801 int ret; 2802 2803 mutex_init(&free_mr->mutex); 2804 2805 ret = free_mr_alloc_res(hr_dev); 2806 if (ret) 2807 return ret; 2808 2809 ret = free_mr_modify_qp(hr_dev); 2810 if (ret) 2811 goto err_modify_qp; 2812 2813 return 0; 2814 2815 err_modify_qp: 2816 free_mr_exit(hr_dev); 2817 2818 return ret; 2819 } 2820 2821 static int get_hem_table(struct hns_roce_dev *hr_dev) 2822 { 2823 unsigned int qpc_count; 2824 unsigned int cqc_count; 2825 unsigned int gmv_count; 2826 int ret; 2827 int i; 2828 2829 /* Alloc memory for source address table buffer space chunk */ 2830 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2831 gmv_count++) { 2832 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2833 if (ret) 2834 goto err_gmv_failed; 2835 } 2836 2837 if (hr_dev->is_vf) 2838 return 0; 2839 2840 /* Alloc memory for QPC Timer buffer space chunk */ 2841 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2842 qpc_count++) { 2843 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2844 qpc_count); 2845 if (ret) { 2846 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2847 goto err_qpc_timer_failed; 2848 } 2849 } 2850 2851 /* Alloc memory for CQC Timer buffer space chunk */ 2852 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2853 cqc_count++) { 2854 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2855 cqc_count); 2856 if (ret) { 2857 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2858 goto err_cqc_timer_failed; 2859 } 2860 } 2861 2862 return 0; 2863 2864 err_cqc_timer_failed: 2865 for (i = 0; i < cqc_count; i++) 2866 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2867 2868 err_qpc_timer_failed: 2869 for (i = 0; i < qpc_count; i++) 2870 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2871 2872 err_gmv_failed: 2873 for (i = 0; i < gmv_count; i++) 2874 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2875 2876 return ret; 2877 } 2878 2879 static void put_hem_table(struct hns_roce_dev *hr_dev) 2880 { 2881 int i; 2882 2883 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2884 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2885 2886 if (hr_dev->is_vf) 2887 return; 2888 2889 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2890 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2891 2892 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2893 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2894 } 2895 2896 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2897 { 2898 int ret; 2899 2900 /* The hns ROCEE requires the extdb info to be cleared before using */ 2901 ret = hns_roce_clear_extdb_list_info(hr_dev); 2902 if (ret) 2903 return ret; 2904 2905 ret = get_hem_table(hr_dev); 2906 if (ret) 2907 return ret; 2908 2909 if (hr_dev->is_vf) 2910 return 0; 2911 2912 ret = hns_roce_init_link_table(hr_dev); 2913 if (ret) { 2914 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2915 goto err_llm_init_failed; 2916 } 2917 2918 return 0; 2919 2920 err_llm_init_failed: 2921 put_hem_table(hr_dev); 2922 2923 return ret; 2924 } 2925 2926 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2927 { 2928 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2929 free_mr_exit(hr_dev); 2930 2931 hns_roce_function_clear(hr_dev); 2932 2933 if (!hr_dev->is_vf) 2934 hns_roce_free_link_table(hr_dev); 2935 2936 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2937 free_dip_list(hr_dev); 2938 } 2939 2940 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2941 struct hns_roce_mbox_msg *mbox_msg) 2942 { 2943 struct hns_roce_cmq_desc desc; 2944 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2945 2946 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2947 2948 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2949 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2950 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2951 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2952 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2953 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2954 mbox_msg->token); 2955 2956 return hns_roce_cmq_send(hr_dev, &desc, 1); 2957 } 2958 2959 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2960 u8 *complete_status) 2961 { 2962 struct hns_roce_mbox_status *mb_st; 2963 struct hns_roce_cmq_desc desc; 2964 unsigned long end; 2965 int ret = -EBUSY; 2966 u32 status; 2967 bool busy; 2968 2969 mb_st = (struct hns_roce_mbox_status *)desc.data; 2970 end = msecs_to_jiffies(timeout) + jiffies; 2971 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2972 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2973 return -EIO; 2974 2975 status = 0; 2976 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2977 true); 2978 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2979 if (!ret) { 2980 status = le32_to_cpu(mb_st->mb_status_hw_run); 2981 /* No pending message exists in ROCEE mbox. */ 2982 if (!(status & MB_ST_HW_RUN_M)) 2983 break; 2984 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2985 break; 2986 } 2987 2988 if (time_after(jiffies, end)) { 2989 dev_err_ratelimited(hr_dev->dev, 2990 "failed to wait mbox status 0x%x\n", 2991 status); 2992 return -ETIMEDOUT; 2993 } 2994 2995 cond_resched(); 2996 ret = -EBUSY; 2997 } 2998 2999 if (!ret) { 3000 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3001 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3002 /* Ignore all errors if the mbox is unavailable. */ 3003 ret = 0; 3004 *complete_status = MB_ST_COMPLETE_M; 3005 } 3006 3007 return ret; 3008 } 3009 3010 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3011 struct hns_roce_mbox_msg *mbox_msg) 3012 { 3013 u8 status = 0; 3014 int ret; 3015 3016 /* Waiting for the mbox to be idle */ 3017 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3018 &status); 3019 if (unlikely(ret)) { 3020 dev_err_ratelimited(hr_dev->dev, 3021 "failed to check post mbox status = 0x%x, ret = %d.\n", 3022 status, ret); 3023 return ret; 3024 } 3025 3026 /* Post new message to mbox */ 3027 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3028 if (ret) 3029 dev_err_ratelimited(hr_dev->dev, 3030 "failed to post mailbox, ret = %d.\n", ret); 3031 3032 return ret; 3033 } 3034 3035 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3036 { 3037 u8 status = 0; 3038 int ret; 3039 3040 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3041 &status); 3042 if (!ret) { 3043 if (status != MB_ST_COMPLETE_SUCC) 3044 return -EBUSY; 3045 } else { 3046 dev_err_ratelimited(hr_dev->dev, 3047 "failed to check mbox status = 0x%x, ret = %d.\n", 3048 status, ret); 3049 } 3050 3051 return ret; 3052 } 3053 3054 static void copy_gid(void *dest, const union ib_gid *gid) 3055 { 3056 #define GID_SIZE 4 3057 const union ib_gid *src = gid; 3058 __le32 (*p)[GID_SIZE] = dest; 3059 int i; 3060 3061 if (!gid) 3062 src = &zgid; 3063 3064 for (i = 0; i < GID_SIZE; i++) 3065 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3066 } 3067 3068 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3069 int gid_index, const union ib_gid *gid, 3070 enum hns_roce_sgid_type sgid_type) 3071 { 3072 struct hns_roce_cmq_desc desc; 3073 struct hns_roce_cfg_sgid_tb *sgid_tb = 3074 (struct hns_roce_cfg_sgid_tb *)desc.data; 3075 3076 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3077 3078 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3079 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3080 3081 copy_gid(&sgid_tb->vf_sgid_l, gid); 3082 3083 return hns_roce_cmq_send(hr_dev, &desc, 1); 3084 } 3085 3086 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3087 int gid_index, const union ib_gid *gid, 3088 enum hns_roce_sgid_type sgid_type, 3089 const struct ib_gid_attr *attr) 3090 { 3091 struct hns_roce_cmq_desc desc[2]; 3092 struct hns_roce_cfg_gmv_tb_a *tb_a = 3093 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3094 struct hns_roce_cfg_gmv_tb_b *tb_b = 3095 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3096 3097 u16 vlan_id = VLAN_CFI_MASK; 3098 u8 mac[ETH_ALEN] = {}; 3099 int ret; 3100 3101 if (gid) { 3102 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3103 if (ret) 3104 return ret; 3105 } 3106 3107 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3108 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3109 3110 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3111 3112 copy_gid(&tb_a->vf_sgid_l, gid); 3113 3114 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3115 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3116 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3117 3118 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3119 3120 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3121 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3122 3123 return hns_roce_cmq_send(hr_dev, desc, 2); 3124 } 3125 3126 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3127 const union ib_gid *gid, 3128 const struct ib_gid_attr *attr) 3129 { 3130 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3131 int ret; 3132 3133 if (gid) { 3134 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3135 if (ipv6_addr_v4mapped((void *)gid)) 3136 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3137 else 3138 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3139 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3140 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3141 } 3142 } 3143 3144 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3145 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3146 else 3147 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3148 3149 if (ret) 3150 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3151 ret); 3152 3153 return ret; 3154 } 3155 3156 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3157 const u8 *addr) 3158 { 3159 struct hns_roce_cmq_desc desc; 3160 struct hns_roce_cfg_smac_tb *smac_tb = 3161 (struct hns_roce_cfg_smac_tb *)desc.data; 3162 u16 reg_smac_h; 3163 u32 reg_smac_l; 3164 3165 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3166 3167 reg_smac_l = *(u32 *)(&addr[0]); 3168 reg_smac_h = *(u16 *)(&addr[4]); 3169 3170 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3171 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3172 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3173 3174 return hns_roce_cmq_send(hr_dev, &desc, 1); 3175 } 3176 3177 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3178 struct hns_roce_v2_mpt_entry *mpt_entry, 3179 struct hns_roce_mr *mr) 3180 { 3181 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3182 struct ib_device *ibdev = &hr_dev->ib_dev; 3183 dma_addr_t pbl_ba; 3184 int i, count; 3185 3186 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3187 min_t(int, ARRAY_SIZE(pages), mr->npages), 3188 &pbl_ba); 3189 if (count < 1) { 3190 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3191 count); 3192 return -ENOBUFS; 3193 } 3194 3195 /* Aligned to the hardware address access unit */ 3196 for (i = 0; i < count; i++) 3197 pages[i] >>= 6; 3198 3199 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3200 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3201 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3202 3203 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3204 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3205 3206 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3207 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3208 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3209 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3210 3211 return 0; 3212 } 3213 3214 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3215 void *mb_buf, struct hns_roce_mr *mr) 3216 { 3217 struct hns_roce_v2_mpt_entry *mpt_entry; 3218 3219 mpt_entry = mb_buf; 3220 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3221 3222 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3223 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3224 3225 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3226 mr->access & IB_ACCESS_MW_BIND); 3227 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3228 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3229 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3230 mr->access & IB_ACCESS_REMOTE_READ); 3231 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3232 mr->access & IB_ACCESS_REMOTE_WRITE); 3233 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3234 mr->access & IB_ACCESS_LOCAL_WRITE); 3235 3236 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3237 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3238 mpt_entry->lkey = cpu_to_le32(mr->key); 3239 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3240 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3241 3242 if (mr->type != MR_TYPE_MR) 3243 hr_reg_enable(mpt_entry, MPT_PA); 3244 3245 if (mr->type == MR_TYPE_DMA) 3246 return 0; 3247 3248 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3249 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3250 3251 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3252 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3253 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3254 3255 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3256 } 3257 3258 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3259 struct hns_roce_mr *mr, int flags, 3260 void *mb_buf) 3261 { 3262 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3263 u32 mr_access_flags = mr->access; 3264 int ret = 0; 3265 3266 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3267 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3268 3269 if (flags & IB_MR_REREG_ACCESS) { 3270 hr_reg_write(mpt_entry, MPT_BIND_EN, 3271 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3272 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3273 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3274 hr_reg_write(mpt_entry, MPT_RR_EN, 3275 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3276 hr_reg_write(mpt_entry, MPT_RW_EN, 3277 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3278 hr_reg_write(mpt_entry, MPT_LW_EN, 3279 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3280 } 3281 3282 if (flags & IB_MR_REREG_TRANS) { 3283 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3284 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3285 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3286 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3287 3288 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3289 } 3290 3291 return ret; 3292 } 3293 3294 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3295 void *mb_buf, struct hns_roce_mr *mr) 3296 { 3297 struct ib_device *ibdev = &hr_dev->ib_dev; 3298 struct hns_roce_v2_mpt_entry *mpt_entry; 3299 dma_addr_t pbl_ba = 0; 3300 3301 mpt_entry = mb_buf; 3302 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3303 3304 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3305 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3306 return -ENOBUFS; 3307 } 3308 3309 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3310 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3311 3312 hr_reg_enable(mpt_entry, MPT_RA_EN); 3313 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3314 3315 hr_reg_enable(mpt_entry, MPT_FRE); 3316 hr_reg_clear(mpt_entry, MPT_MR_MW); 3317 hr_reg_enable(mpt_entry, MPT_BPD); 3318 hr_reg_clear(mpt_entry, MPT_PA); 3319 3320 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3321 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3322 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3323 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3324 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3325 3326 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3327 3328 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3329 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3330 3331 return 0; 3332 } 3333 3334 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3335 { 3336 struct hns_roce_v2_mpt_entry *mpt_entry; 3337 3338 mpt_entry = mb_buf; 3339 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3340 3341 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3342 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3343 3344 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3345 hr_reg_enable(mpt_entry, MPT_LW_EN); 3346 3347 hr_reg_enable(mpt_entry, MPT_MR_MW); 3348 hr_reg_enable(mpt_entry, MPT_BPD); 3349 hr_reg_clear(mpt_entry, MPT_PA); 3350 hr_reg_write(mpt_entry, MPT_BQP, 3351 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3352 3353 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3354 3355 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3356 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3357 mw->pbl_hop_num); 3358 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3359 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3360 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3361 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3362 3363 return 0; 3364 } 3365 3366 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3367 { 3368 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3369 struct ib_device *ibdev = &hr_dev->ib_dev; 3370 const struct ib_send_wr *bad_wr; 3371 struct ib_rdma_wr rdma_wr = {}; 3372 struct ib_send_wr *send_wr; 3373 int ret; 3374 3375 send_wr = &rdma_wr.wr; 3376 send_wr->opcode = IB_WR_RDMA_WRITE; 3377 3378 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3379 if (ret) { 3380 ibdev_err_ratelimited(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3381 ret); 3382 return ret; 3383 } 3384 3385 return 0; 3386 } 3387 3388 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3389 struct ib_wc *wc); 3390 3391 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3392 { 3393 struct hns_roce_v2_priv *priv = hr_dev->priv; 3394 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3395 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3396 struct ib_device *ibdev = &hr_dev->ib_dev; 3397 struct hns_roce_qp *hr_qp; 3398 unsigned long end; 3399 int cqe_cnt = 0; 3400 int npolled; 3401 int ret; 3402 int i; 3403 3404 /* 3405 * If the device initialization is not complete or in the uninstall 3406 * process, then there is no need to execute free mr. 3407 */ 3408 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3409 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3410 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3411 return; 3412 3413 mutex_lock(&free_mr->mutex); 3414 3415 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3416 hr_qp = free_mr->rsv_qp[i]; 3417 3418 ret = free_mr_post_send_lp_wqe(hr_qp); 3419 if (ret) { 3420 ibdev_err_ratelimited(ibdev, 3421 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3422 hr_qp->qpn, ret); 3423 break; 3424 } 3425 3426 cqe_cnt++; 3427 } 3428 3429 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3430 while (cqe_cnt) { 3431 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3432 if (npolled < 0) { 3433 ibdev_err_ratelimited(ibdev, 3434 "failed to poll cqe for free mr, remain %d cqe.\n", 3435 cqe_cnt); 3436 goto out; 3437 } 3438 3439 if (time_after(jiffies, end)) { 3440 ibdev_err_ratelimited(ibdev, 3441 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3442 cqe_cnt); 3443 goto out; 3444 } 3445 cqe_cnt -= npolled; 3446 } 3447 3448 out: 3449 mutex_unlock(&free_mr->mutex); 3450 } 3451 3452 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3453 { 3454 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3455 free_mr_send_cmd_to_hw(hr_dev); 3456 } 3457 3458 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3459 { 3460 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3461 } 3462 3463 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3464 { 3465 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3466 3467 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3468 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3469 NULL; 3470 } 3471 3472 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3473 struct hns_roce_cq *hr_cq) 3474 { 3475 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3476 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3477 } else { 3478 struct hns_roce_v2_db cq_db = {}; 3479 3480 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3481 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3482 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3483 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3484 3485 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3486 } 3487 } 3488 3489 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3490 struct hns_roce_srq *srq) 3491 { 3492 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3493 struct hns_roce_v2_cqe *cqe, *dest; 3494 u32 prod_index; 3495 int nfreed = 0; 3496 int wqe_index; 3497 u8 owner_bit; 3498 3499 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3500 ++prod_index) { 3501 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3502 break; 3503 } 3504 3505 /* 3506 * Now backwards through the CQ, removing CQ entries 3507 * that match our QP by overwriting them with next entries. 3508 */ 3509 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3510 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3511 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3512 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3513 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3514 hns_roce_free_srq_wqe(srq, wqe_index); 3515 } 3516 ++nfreed; 3517 } else if (nfreed) { 3518 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3519 hr_cq->ib_cq.cqe); 3520 owner_bit = hr_reg_read(dest, CQE_OWNER); 3521 memcpy(dest, cqe, hr_cq->cqe_size); 3522 hr_reg_write(dest, CQE_OWNER, owner_bit); 3523 } 3524 } 3525 3526 if (nfreed) { 3527 hr_cq->cons_index += nfreed; 3528 update_cq_db(hr_dev, hr_cq); 3529 } 3530 } 3531 3532 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3533 struct hns_roce_srq *srq) 3534 { 3535 spin_lock_irq(&hr_cq->lock); 3536 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3537 spin_unlock_irq(&hr_cq->lock); 3538 } 3539 3540 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3541 struct hns_roce_cq *hr_cq, void *mb_buf, 3542 u64 *mtts, dma_addr_t dma_handle) 3543 { 3544 struct hns_roce_v2_cq_context *cq_context; 3545 3546 cq_context = mb_buf; 3547 memset(cq_context, 0, sizeof(*cq_context)); 3548 3549 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3550 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3551 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3552 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3553 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3554 3555 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3556 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3557 3558 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3559 hr_reg_enable(cq_context, CQC_STASH); 3560 3561 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3562 to_hr_hw_page_addr(mtts[0])); 3563 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3564 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3565 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3566 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3567 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3568 to_hr_hw_page_addr(mtts[1])); 3569 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3570 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3571 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3572 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3573 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3574 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3575 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3576 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3577 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3578 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3579 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3580 ((u32)hr_cq->db.dma) >> 1); 3581 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3582 hr_cq->db.dma >> 32); 3583 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3584 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3585 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3586 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3587 } 3588 3589 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3590 enum ib_cq_notify_flags flags) 3591 { 3592 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3593 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3594 struct hns_roce_v2_db cq_db = {}; 3595 u32 notify_flag; 3596 3597 /* 3598 * flags = 0, then notify_flag : next 3599 * flags = 1, then notify flag : solocited 3600 */ 3601 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3602 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3603 3604 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3605 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3606 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3607 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3608 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3609 3610 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3611 3612 return 0; 3613 } 3614 3615 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3616 int num_entries, struct ib_wc *wc) 3617 { 3618 unsigned int left; 3619 int npolled = 0; 3620 3621 left = wq->head - wq->tail; 3622 if (left == 0) 3623 return 0; 3624 3625 left = min_t(unsigned int, (unsigned int)num_entries, left); 3626 while (npolled < left) { 3627 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3628 wc->status = IB_WC_WR_FLUSH_ERR; 3629 wc->vendor_err = 0; 3630 wc->qp = &hr_qp->ibqp; 3631 3632 wq->tail++; 3633 wc++; 3634 npolled++; 3635 } 3636 3637 return npolled; 3638 } 3639 3640 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3641 struct ib_wc *wc) 3642 { 3643 struct hns_roce_qp *hr_qp; 3644 int npolled = 0; 3645 3646 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3647 npolled += sw_comp(hr_qp, &hr_qp->sq, 3648 num_entries - npolled, wc + npolled); 3649 if (npolled >= num_entries) 3650 goto out; 3651 } 3652 3653 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3654 npolled += sw_comp(hr_qp, &hr_qp->rq, 3655 num_entries - npolled, wc + npolled); 3656 if (npolled >= num_entries) 3657 goto out; 3658 } 3659 3660 out: 3661 return npolled; 3662 } 3663 3664 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3665 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3666 struct ib_wc *wc) 3667 { 3668 static const struct { 3669 u32 cqe_status; 3670 enum ib_wc_status wc_status; 3671 } map[] = { 3672 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3673 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3674 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3675 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3676 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3677 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3678 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3679 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3680 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3681 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3682 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3683 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3684 IB_WC_RETRY_EXC_ERR }, 3685 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3686 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3687 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3688 }; 3689 3690 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3691 int i; 3692 3693 wc->status = IB_WC_GENERAL_ERR; 3694 for (i = 0; i < ARRAY_SIZE(map); i++) 3695 if (cqe_status == map[i].cqe_status) { 3696 wc->status = map[i].wc_status; 3697 break; 3698 } 3699 3700 if (likely(wc->status == IB_WC_SUCCESS || 3701 wc->status == IB_WC_WR_FLUSH_ERR)) 3702 return; 3703 3704 ibdev_err_ratelimited(&hr_dev->ib_dev, "error cqe status 0x%x:\n", 3705 cqe_status); 3706 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3707 cq->cqe_size, false); 3708 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3709 3710 /* 3711 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3712 * the standard protocol, the driver must ignore it and needn't to set 3713 * the QP to an error state. 3714 */ 3715 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3716 return; 3717 3718 flush_cqe(hr_dev, qp); 3719 } 3720 3721 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3722 struct hns_roce_qp **cur_qp) 3723 { 3724 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3725 struct hns_roce_qp *hr_qp = *cur_qp; 3726 u32 qpn; 3727 3728 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3729 3730 if (!hr_qp || qpn != hr_qp->qpn) { 3731 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3732 if (unlikely(!hr_qp)) { 3733 ibdev_err(&hr_dev->ib_dev, 3734 "CQ %06lx with entry for unknown QPN %06x\n", 3735 hr_cq->cqn, qpn); 3736 return -EINVAL; 3737 } 3738 *cur_qp = hr_qp; 3739 } 3740 3741 return 0; 3742 } 3743 3744 /* 3745 * mapped-value = 1 + real-value 3746 * The ib wc opcode's real value is start from 0, In order to distinguish 3747 * between initialized and uninitialized map values, we plus 1 to the actual 3748 * value when defining the mapping, so that the validity can be identified by 3749 * checking whether the mapped value is greater than 0. 3750 */ 3751 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3752 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3753 3754 static const u32 wc_send_op_map[] = { 3755 HR_WC_OP_MAP(SEND, SEND), 3756 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3757 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3758 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3759 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3760 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3761 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3762 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3763 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3764 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3765 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3766 HR_WC_OP_MAP(BIND_MW, REG_MR), 3767 }; 3768 3769 static int to_ib_wc_send_op(u32 hr_opcode) 3770 { 3771 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3772 return -EINVAL; 3773 3774 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3775 -EINVAL; 3776 } 3777 3778 static const u32 wc_recv_op_map[] = { 3779 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3780 HR_WC_OP_MAP(SEND, RECV), 3781 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3782 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3783 }; 3784 3785 static int to_ib_wc_recv_op(u32 hr_opcode) 3786 { 3787 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3788 return -EINVAL; 3789 3790 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3791 -EINVAL; 3792 } 3793 3794 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3795 { 3796 u32 hr_opcode; 3797 int ib_opcode; 3798 3799 wc->wc_flags = 0; 3800 3801 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3802 switch (hr_opcode) { 3803 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3804 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3805 break; 3806 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3807 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3808 wc->wc_flags |= IB_WC_WITH_IMM; 3809 break; 3810 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3811 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3812 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3813 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3814 wc->byte_len = 8; 3815 break; 3816 default: 3817 break; 3818 } 3819 3820 ib_opcode = to_ib_wc_send_op(hr_opcode); 3821 if (ib_opcode < 0) 3822 wc->status = IB_WC_GENERAL_ERR; 3823 else 3824 wc->opcode = ib_opcode; 3825 } 3826 3827 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3828 { 3829 u32 hr_opcode; 3830 int ib_opcode; 3831 3832 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3833 3834 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3835 switch (hr_opcode) { 3836 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3837 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3838 wc->wc_flags = IB_WC_WITH_IMM; 3839 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3840 break; 3841 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3842 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3843 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3844 break; 3845 default: 3846 wc->wc_flags = 0; 3847 } 3848 3849 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3850 if (ib_opcode < 0) 3851 wc->status = IB_WC_GENERAL_ERR; 3852 else 3853 wc->opcode = ib_opcode; 3854 3855 wc->sl = hr_reg_read(cqe, CQE_SL); 3856 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3857 wc->slid = 0; 3858 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3859 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3860 wc->pkey_index = 0; 3861 3862 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3863 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3864 wc->wc_flags |= IB_WC_WITH_VLAN; 3865 } else { 3866 wc->vlan_id = 0xffff; 3867 } 3868 3869 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3870 3871 return 0; 3872 } 3873 3874 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3875 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3876 { 3877 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3878 struct hns_roce_qp *qp = *cur_qp; 3879 struct hns_roce_srq *srq = NULL; 3880 struct hns_roce_v2_cqe *cqe; 3881 struct hns_roce_wq *wq; 3882 int is_send; 3883 u16 wqe_idx; 3884 int ret; 3885 3886 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3887 if (!cqe) 3888 return -EAGAIN; 3889 3890 ++hr_cq->cons_index; 3891 /* Memory barrier */ 3892 rmb(); 3893 3894 ret = get_cur_qp(hr_cq, cqe, &qp); 3895 if (ret) 3896 return ret; 3897 3898 wc->qp = &qp->ibqp; 3899 wc->vendor_err = 0; 3900 3901 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3902 3903 is_send = !hr_reg_read(cqe, CQE_S_R); 3904 if (is_send) { 3905 wq = &qp->sq; 3906 3907 /* If sg_signal_bit is set, tail pointer will be updated to 3908 * the WQE corresponding to the current CQE. 3909 */ 3910 if (qp->sq_signal_bits) 3911 wq->tail += (wqe_idx - (u16)wq->tail) & 3912 (wq->wqe_cnt - 1); 3913 3914 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3915 ++wq->tail; 3916 3917 fill_send_wc(wc, cqe); 3918 } else { 3919 if (qp->ibqp.srq) { 3920 srq = to_hr_srq(qp->ibqp.srq); 3921 wc->wr_id = srq->wrid[wqe_idx]; 3922 hns_roce_free_srq_wqe(srq, wqe_idx); 3923 } else { 3924 wq = &qp->rq; 3925 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3926 ++wq->tail; 3927 } 3928 3929 ret = fill_recv_wc(wc, cqe); 3930 } 3931 3932 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3933 if (unlikely(wc->status != IB_WC_SUCCESS)) 3934 return 0; 3935 3936 return ret; 3937 } 3938 3939 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3940 struct ib_wc *wc) 3941 { 3942 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3943 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3944 struct hns_roce_qp *cur_qp = NULL; 3945 unsigned long flags; 3946 int npolled; 3947 3948 spin_lock_irqsave(&hr_cq->lock, flags); 3949 3950 /* 3951 * When the device starts to reset, the state is RST_DOWN. At this time, 3952 * there may still be some valid CQEs in the hardware that are not 3953 * polled. Therefore, it is not allowed to switch to the software mode 3954 * immediately. When the state changes to UNINIT, CQE no longer exists 3955 * in the hardware, and then switch to software mode. 3956 */ 3957 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3958 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3959 goto out; 3960 } 3961 3962 for (npolled = 0; npolled < num_entries; ++npolled) { 3963 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3964 break; 3965 } 3966 3967 if (npolled) 3968 update_cq_db(hr_dev, hr_cq); 3969 3970 out: 3971 spin_unlock_irqrestore(&hr_cq->lock, flags); 3972 3973 return npolled; 3974 } 3975 3976 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3977 u32 step_idx, u8 *mbox_cmd) 3978 { 3979 u8 cmd; 3980 3981 switch (type) { 3982 case HEM_TYPE_QPC: 3983 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 3984 break; 3985 case HEM_TYPE_MTPT: 3986 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 3987 break; 3988 case HEM_TYPE_CQC: 3989 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 3990 break; 3991 case HEM_TYPE_SRQC: 3992 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3993 break; 3994 case HEM_TYPE_SCCC: 3995 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3996 break; 3997 case HEM_TYPE_QPC_TIMER: 3998 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3999 break; 4000 case HEM_TYPE_CQC_TIMER: 4001 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4002 break; 4003 default: 4004 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4005 return -EINVAL; 4006 } 4007 4008 *mbox_cmd = cmd + step_idx; 4009 4010 return 0; 4011 } 4012 4013 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4014 dma_addr_t base_addr) 4015 { 4016 struct hns_roce_cmq_desc desc; 4017 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4018 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4019 u64 addr = to_hr_hw_page_addr(base_addr); 4020 4021 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4022 4023 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4024 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4025 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4026 4027 return hns_roce_cmq_send(hr_dev, &desc, 1); 4028 } 4029 4030 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4031 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4032 { 4033 int ret; 4034 u8 cmd; 4035 4036 if (unlikely(hem_type == HEM_TYPE_GMV)) 4037 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4038 4039 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4040 return 0; 4041 4042 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4043 if (ret < 0) 4044 return ret; 4045 4046 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4047 } 4048 4049 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4050 struct hns_roce_hem_table *table, int obj, 4051 u32 step_idx) 4052 { 4053 struct hns_roce_hem_iter iter; 4054 struct hns_roce_hem_mhop mhop; 4055 struct hns_roce_hem *hem; 4056 unsigned long mhop_obj = obj; 4057 int i, j, k; 4058 int ret = 0; 4059 u64 hem_idx = 0; 4060 u64 l1_idx = 0; 4061 u64 bt_ba = 0; 4062 u32 chunk_ba_num; 4063 u32 hop_num; 4064 4065 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4066 return 0; 4067 4068 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4069 i = mhop.l0_idx; 4070 j = mhop.l1_idx; 4071 k = mhop.l2_idx; 4072 hop_num = mhop.hop_num; 4073 chunk_ba_num = mhop.bt_chunk_size / 8; 4074 4075 if (hop_num == 2) { 4076 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4077 k; 4078 l1_idx = i * chunk_ba_num + j; 4079 } else if (hop_num == 1) { 4080 hem_idx = i * chunk_ba_num + j; 4081 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4082 hem_idx = i; 4083 } 4084 4085 if (table->type == HEM_TYPE_SCCC) 4086 obj = mhop.l0_idx; 4087 4088 if (check_whether_last_step(hop_num, step_idx)) { 4089 hem = table->hem[hem_idx]; 4090 for (hns_roce_hem_first(hem, &iter); 4091 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4092 bt_ba = hns_roce_hem_addr(&iter); 4093 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4094 step_idx); 4095 } 4096 } else { 4097 if (step_idx == 0) 4098 bt_ba = table->bt_l0_dma_addr[i]; 4099 else if (step_idx == 1 && hop_num == 2) 4100 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4101 4102 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4103 } 4104 4105 return ret; 4106 } 4107 4108 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4109 struct hns_roce_hem_table *table, 4110 int tag, u32 step_idx) 4111 { 4112 struct hns_roce_cmd_mailbox *mailbox; 4113 struct device *dev = hr_dev->dev; 4114 u8 cmd = 0xff; 4115 int ret; 4116 4117 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4118 return 0; 4119 4120 switch (table->type) { 4121 case HEM_TYPE_QPC: 4122 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4123 break; 4124 case HEM_TYPE_MTPT: 4125 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4126 break; 4127 case HEM_TYPE_CQC: 4128 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4129 break; 4130 case HEM_TYPE_SRQC: 4131 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4132 break; 4133 case HEM_TYPE_SCCC: 4134 case HEM_TYPE_QPC_TIMER: 4135 case HEM_TYPE_CQC_TIMER: 4136 case HEM_TYPE_GMV: 4137 return 0; 4138 default: 4139 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4140 table->type); 4141 return 0; 4142 } 4143 4144 cmd += step_idx; 4145 4146 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4147 if (IS_ERR(mailbox)) 4148 return PTR_ERR(mailbox); 4149 4150 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4151 4152 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4153 return ret; 4154 } 4155 4156 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4157 struct hns_roce_v2_qp_context *context, 4158 struct hns_roce_v2_qp_context *qpc_mask, 4159 struct hns_roce_qp *hr_qp) 4160 { 4161 struct hns_roce_cmd_mailbox *mailbox; 4162 int qpc_size; 4163 int ret; 4164 4165 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4166 if (IS_ERR(mailbox)) 4167 return PTR_ERR(mailbox); 4168 4169 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4170 qpc_size = hr_dev->caps.qpc_sz; 4171 memcpy(mailbox->buf, context, qpc_size); 4172 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4173 4174 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4175 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4176 4177 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4178 4179 return ret; 4180 } 4181 4182 static void set_access_flags(struct hns_roce_qp *hr_qp, 4183 struct hns_roce_v2_qp_context *context, 4184 struct hns_roce_v2_qp_context *qpc_mask, 4185 const struct ib_qp_attr *attr, int attr_mask) 4186 { 4187 u8 dest_rd_atomic; 4188 u32 access_flags; 4189 4190 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4191 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4192 4193 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4194 attr->qp_access_flags : hr_qp->atomic_rd_en; 4195 4196 if (!dest_rd_atomic) 4197 access_flags &= IB_ACCESS_REMOTE_WRITE; 4198 4199 hr_reg_write_bool(context, QPC_RRE, 4200 access_flags & IB_ACCESS_REMOTE_READ); 4201 hr_reg_clear(qpc_mask, QPC_RRE); 4202 4203 hr_reg_write_bool(context, QPC_RWE, 4204 access_flags & IB_ACCESS_REMOTE_WRITE); 4205 hr_reg_clear(qpc_mask, QPC_RWE); 4206 4207 hr_reg_write_bool(context, QPC_ATE, 4208 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4209 hr_reg_clear(qpc_mask, QPC_ATE); 4210 hr_reg_write_bool(context, QPC_EXT_ATE, 4211 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4212 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4213 } 4214 4215 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4216 struct hns_roce_v2_qp_context *context, 4217 struct hns_roce_v2_qp_context *qpc_mask) 4218 { 4219 hr_reg_write(context, QPC_SGE_SHIFT, 4220 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4221 hr_qp->sge.sge_shift)); 4222 4223 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4224 4225 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4226 } 4227 4228 static inline int get_cqn(struct ib_cq *ib_cq) 4229 { 4230 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4231 } 4232 4233 static inline int get_pdn(struct ib_pd *ib_pd) 4234 { 4235 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4236 } 4237 4238 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4239 const struct ib_qp_attr *attr, 4240 struct hns_roce_v2_qp_context *context, 4241 struct hns_roce_v2_qp_context *qpc_mask) 4242 { 4243 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4244 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4245 4246 /* 4247 * In v2 engine, software pass context and context mask to hardware 4248 * when modifying qp. If software need modify some fields in context, 4249 * we should set all bits of the relevant fields in context mask to 4250 * 0 at the same time, else set them to 0x1. 4251 */ 4252 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4253 4254 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4255 4256 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4257 4258 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4259 4260 /* No VLAN need to set 0xFFF */ 4261 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4262 4263 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4264 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4265 4266 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4267 } 4268 4269 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4270 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4271 4272 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4273 hr_reg_enable(context, QPC_OWNER_MODE); 4274 4275 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4276 lower_32_bits(hr_qp->rdb.dma) >> 1); 4277 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4278 upper_32_bits(hr_qp->rdb.dma)); 4279 4280 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4281 4282 if (ibqp->srq) { 4283 hr_reg_enable(context, QPC_SRQ_EN); 4284 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4285 } 4286 4287 hr_reg_enable(context, QPC_FRE); 4288 4289 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4290 4291 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4292 return; 4293 4294 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4295 hr_reg_enable(&context->ext, QPCEX_STASH); 4296 } 4297 4298 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4299 const struct ib_qp_attr *attr, 4300 struct hns_roce_v2_qp_context *context, 4301 struct hns_roce_v2_qp_context *qpc_mask) 4302 { 4303 /* 4304 * In v2 engine, software pass context and context mask to hardware 4305 * when modifying qp. If software need modify some fields in context, 4306 * we should set all bits of the relevant fields in context mask to 4307 * 0 at the same time, else set them to 0x1. 4308 */ 4309 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4310 hr_reg_clear(qpc_mask, QPC_TST); 4311 4312 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4313 hr_reg_clear(qpc_mask, QPC_PD); 4314 4315 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4316 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4317 4318 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4319 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4320 4321 if (ibqp->srq) { 4322 hr_reg_enable(context, QPC_SRQ_EN); 4323 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4324 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4325 hr_reg_clear(qpc_mask, QPC_SRQN); 4326 } 4327 } 4328 4329 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4330 struct hns_roce_qp *hr_qp, 4331 struct hns_roce_v2_qp_context *context, 4332 struct hns_roce_v2_qp_context *qpc_mask) 4333 { 4334 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4335 u64 wqe_sge_ba; 4336 int count; 4337 4338 /* Search qp buf's mtts */ 4339 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4340 MTT_MIN_COUNT, &wqe_sge_ba); 4341 if (hr_qp->rq.wqe_cnt && count < 1) { 4342 ibdev_err(&hr_dev->ib_dev, 4343 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4344 return -EINVAL; 4345 } 4346 4347 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4348 qpc_mask->wqe_sge_ba = 0; 4349 4350 /* 4351 * In v2 engine, software pass context and context mask to hardware 4352 * when modifying qp. If software need modify some fields in context, 4353 * we should set all bits of the relevant fields in context mask to 4354 * 0 at the same time, else set them to 0x1. 4355 */ 4356 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4357 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4358 4359 hr_reg_write(context, QPC_SQ_HOP_NUM, 4360 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4361 hr_qp->sq.wqe_cnt)); 4362 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4363 4364 hr_reg_write(context, QPC_SGE_HOP_NUM, 4365 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4366 hr_qp->sge.sge_cnt)); 4367 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4368 4369 hr_reg_write(context, QPC_RQ_HOP_NUM, 4370 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4371 hr_qp->rq.wqe_cnt)); 4372 4373 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4374 4375 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4376 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4377 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4378 4379 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4380 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4381 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4382 4383 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4384 qpc_mask->rq_cur_blk_addr = 0; 4385 4386 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4387 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4388 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4389 4390 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4391 context->rq_nxt_blk_addr = 4392 cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4393 qpc_mask->rq_nxt_blk_addr = 0; 4394 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4395 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4396 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4397 } 4398 4399 return 0; 4400 } 4401 4402 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4403 struct hns_roce_qp *hr_qp, 4404 struct hns_roce_v2_qp_context *context, 4405 struct hns_roce_v2_qp_context *qpc_mask) 4406 { 4407 struct ib_device *ibdev = &hr_dev->ib_dev; 4408 u64 sge_cur_blk = 0; 4409 u64 sq_cur_blk = 0; 4410 int count; 4411 4412 /* search qp buf's mtts */ 4413 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4414 if (count < 1) { 4415 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4416 hr_qp->qpn); 4417 return -EINVAL; 4418 } 4419 if (hr_qp->sge.sge_cnt > 0) { 4420 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4421 hr_qp->sge.offset, 4422 &sge_cur_blk, 1, NULL); 4423 if (count < 1) { 4424 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4425 hr_qp->qpn); 4426 return -EINVAL; 4427 } 4428 } 4429 4430 /* 4431 * In v2 engine, software pass context and context mask to hardware 4432 * when modifying qp. If software need modify some fields in context, 4433 * we should set all bits of the relevant fields in context mask to 4434 * 0 at the same time, else set them to 0x1. 4435 */ 4436 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4437 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4438 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4439 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4440 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4441 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4442 4443 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4444 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4445 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4446 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4447 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4448 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4449 4450 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4451 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4452 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4453 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4454 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4455 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4456 4457 return 0; 4458 } 4459 4460 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4461 const struct ib_qp_attr *attr) 4462 { 4463 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4464 return IB_MTU_4096; 4465 4466 return attr->path_mtu; 4467 } 4468 4469 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4470 const struct ib_qp_attr *attr, int attr_mask, 4471 struct hns_roce_v2_qp_context *context, 4472 struct hns_roce_v2_qp_context *qpc_mask, 4473 struct ib_udata *udata) 4474 { 4475 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4476 struct hns_roce_ucontext, ibucontext); 4477 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4478 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4479 struct ib_device *ibdev = &hr_dev->ib_dev; 4480 dma_addr_t trrl_ba; 4481 dma_addr_t irrl_ba; 4482 enum ib_mtu ib_mtu; 4483 const u8 *smac; 4484 u8 lp_pktn_ini; 4485 u64 *mtts; 4486 u8 *dmac; 4487 u32 port; 4488 int mtu; 4489 int ret; 4490 4491 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4492 if (ret) { 4493 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4494 return ret; 4495 } 4496 4497 /* Search IRRL's mtts */ 4498 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4499 hr_qp->qpn, &irrl_ba); 4500 if (!mtts) { 4501 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4502 return -EINVAL; 4503 } 4504 4505 /* Search TRRL's mtts */ 4506 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4507 hr_qp->qpn, &trrl_ba); 4508 if (!mtts) { 4509 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4510 return -EINVAL; 4511 } 4512 4513 if (attr_mask & IB_QP_ALT_PATH) { 4514 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4515 attr_mask); 4516 return -EINVAL; 4517 } 4518 4519 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4520 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4521 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4522 qpc_mask->trrl_ba = 0; 4523 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4524 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4525 4526 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4527 qpc_mask->irrl_ba = 0; 4528 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4529 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4530 4531 hr_reg_enable(context, QPC_RMT_E2E); 4532 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4533 4534 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4535 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4536 4537 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4538 4539 smac = (const u8 *)hr_dev->dev_addr[port]; 4540 dmac = (u8 *)attr->ah_attr.roce.dmac; 4541 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4542 if (ether_addr_equal_unaligned(dmac, smac) || 4543 hr_dev->loop_idc == 0x1) { 4544 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4545 hr_reg_clear(qpc_mask, QPC_LBI); 4546 } 4547 4548 if (attr_mask & IB_QP_DEST_QPN) { 4549 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4550 hr_reg_clear(qpc_mask, QPC_DQPN); 4551 } 4552 4553 memcpy(&context->dmac, dmac, sizeof(u32)); 4554 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4555 qpc_mask->dmac = 0; 4556 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4557 4558 ib_mtu = get_mtu(ibqp, attr); 4559 hr_qp->path_mtu = ib_mtu; 4560 4561 mtu = ib_mtu_enum_to_int(ib_mtu); 4562 if (WARN_ON(mtu <= 0)) 4563 return -EINVAL; 4564 #define MIN_LP_MSG_LEN 1024 4565 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4566 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4567 4568 if (attr_mask & IB_QP_PATH_MTU) { 4569 hr_reg_write(context, QPC_MTU, ib_mtu); 4570 hr_reg_clear(qpc_mask, QPC_MTU); 4571 } 4572 4573 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4574 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4575 4576 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4577 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4578 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4579 4580 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4581 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4582 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4583 4584 context->rq_rnr_timer = 0; 4585 qpc_mask->rq_rnr_timer = 0; 4586 4587 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4588 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4589 4590 /* rocee send 2^lp_sgen_ini segs every time */ 4591 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4592 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4593 4594 if (udata && ibqp->qp_type == IB_QPT_RC && 4595 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4596 hr_reg_write_bool(context, QPC_RQIE, 4597 hr_dev->caps.flags & 4598 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4599 hr_reg_clear(qpc_mask, QPC_RQIE); 4600 } 4601 4602 if (udata && 4603 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4604 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4605 hr_reg_write_bool(context, QPC_CQEIE, 4606 hr_dev->caps.flags & 4607 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4608 hr_reg_clear(qpc_mask, QPC_CQEIE); 4609 4610 hr_reg_write(context, QPC_CQEIS, 0); 4611 hr_reg_clear(qpc_mask, QPC_CQEIS); 4612 } 4613 4614 return 0; 4615 } 4616 4617 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4618 const struct ib_qp_attr *attr, int attr_mask, 4619 struct hns_roce_v2_qp_context *context, 4620 struct hns_roce_v2_qp_context *qpc_mask) 4621 { 4622 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4623 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4624 struct ib_device *ibdev = &hr_dev->ib_dev; 4625 int ret; 4626 4627 /* Not support alternate path and path migration */ 4628 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4629 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4630 return -EINVAL; 4631 } 4632 4633 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4634 if (ret) { 4635 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4636 return ret; 4637 } 4638 4639 /* 4640 * Set some fields in context to zero, Because the default values 4641 * of all fields in context are zero, we need not set them to 0 again. 4642 * but we should set the relevant fields of context mask to 0. 4643 */ 4644 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4645 4646 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4647 4648 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4649 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4650 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4651 4652 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4653 4654 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4655 4656 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4657 4658 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4659 4660 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4661 4662 return 0; 4663 } 4664 4665 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4666 u32 *dip_idx) 4667 { 4668 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4669 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4670 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4671 u32 *head = &hr_dev->qp_table.idx_table.head; 4672 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4673 struct hns_roce_dip *hr_dip; 4674 unsigned long flags; 4675 int ret = 0; 4676 4677 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4678 4679 spare_idx[*tail] = ibqp->qp_num; 4680 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4681 4682 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4683 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4684 *dip_idx = hr_dip->dip_idx; 4685 goto out; 4686 } 4687 } 4688 4689 /* If no dgid is found, a new dip and a mapping between dgid and 4690 * dip_idx will be created. 4691 */ 4692 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4693 if (!hr_dip) { 4694 ret = -ENOMEM; 4695 goto out; 4696 } 4697 4698 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4699 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4700 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4701 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4702 4703 out: 4704 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4705 return ret; 4706 } 4707 4708 enum { 4709 CONG_DCQCN, 4710 CONG_WINDOW, 4711 }; 4712 4713 enum { 4714 UNSUPPORT_CONG_LEVEL, 4715 SUPPORT_CONG_LEVEL, 4716 }; 4717 4718 enum { 4719 CONG_LDCP, 4720 CONG_HC3, 4721 }; 4722 4723 enum { 4724 DIP_INVALID, 4725 DIP_VALID, 4726 }; 4727 4728 enum { 4729 WND_LIMIT, 4730 WND_UNLIMIT, 4731 }; 4732 4733 static int check_cong_type(struct ib_qp *ibqp, 4734 struct hns_roce_congestion_algorithm *cong_alg) 4735 { 4736 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4737 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4738 4739 if (ibqp->qp_type == IB_QPT_UD || ibqp->qp_type == IB_QPT_GSI) 4740 hr_qp->cong_type = CONG_TYPE_DCQCN; 4741 else 4742 hr_qp->cong_type = hr_dev->caps.cong_type; 4743 4744 /* different congestion types match different configurations */ 4745 switch (hr_qp->cong_type) { 4746 case CONG_TYPE_DCQCN: 4747 cong_alg->alg_sel = CONG_DCQCN; 4748 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4749 cong_alg->dip_vld = DIP_INVALID; 4750 cong_alg->wnd_mode_sel = WND_LIMIT; 4751 break; 4752 case CONG_TYPE_LDCP: 4753 cong_alg->alg_sel = CONG_WINDOW; 4754 cong_alg->alg_sub_sel = CONG_LDCP; 4755 cong_alg->dip_vld = DIP_INVALID; 4756 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4757 break; 4758 case CONG_TYPE_HC3: 4759 cong_alg->alg_sel = CONG_WINDOW; 4760 cong_alg->alg_sub_sel = CONG_HC3; 4761 cong_alg->dip_vld = DIP_INVALID; 4762 cong_alg->wnd_mode_sel = WND_LIMIT; 4763 break; 4764 case CONG_TYPE_DIP: 4765 cong_alg->alg_sel = CONG_DCQCN; 4766 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4767 cong_alg->dip_vld = DIP_VALID; 4768 cong_alg->wnd_mode_sel = WND_LIMIT; 4769 break; 4770 default: 4771 ibdev_warn(&hr_dev->ib_dev, 4772 "invalid type(%u) for congestion selection.\n", 4773 hr_qp->cong_type); 4774 hr_qp->cong_type = CONG_TYPE_DCQCN; 4775 cong_alg->alg_sel = CONG_DCQCN; 4776 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4777 cong_alg->dip_vld = DIP_INVALID; 4778 cong_alg->wnd_mode_sel = WND_LIMIT; 4779 break; 4780 } 4781 4782 return 0; 4783 } 4784 4785 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4786 struct hns_roce_v2_qp_context *context, 4787 struct hns_roce_v2_qp_context *qpc_mask) 4788 { 4789 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4790 struct hns_roce_congestion_algorithm cong_field; 4791 struct ib_device *ibdev = ibqp->device; 4792 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4793 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4794 u32 dip_idx = 0; 4795 int ret; 4796 4797 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4798 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4799 return 0; 4800 4801 ret = check_cong_type(ibqp, &cong_field); 4802 if (ret) 4803 return ret; 4804 4805 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4806 hr_qp->cong_type * HNS_ROCE_CONG_SIZE); 4807 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4808 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4809 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4810 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4811 cong_field.alg_sub_sel); 4812 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4813 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4814 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4815 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4816 cong_field.wnd_mode_sel); 4817 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4818 4819 /* if dip is disabled, there is no need to set dip idx */ 4820 if (cong_field.dip_vld == 0) 4821 return 0; 4822 4823 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4824 if (ret) { 4825 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4826 return ret; 4827 } 4828 4829 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4830 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4831 4832 return 0; 4833 } 4834 4835 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4836 const struct ib_qp_attr *attr, 4837 int attr_mask, 4838 struct hns_roce_v2_qp_context *context, 4839 struct hns_roce_v2_qp_context *qpc_mask) 4840 { 4841 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4842 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4843 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4844 struct ib_device *ibdev = &hr_dev->ib_dev; 4845 const struct ib_gid_attr *gid_attr = NULL; 4846 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4847 int is_roce_protocol; 4848 u16 vlan_id = 0xffff; 4849 bool is_udp = false; 4850 u32 max_sl; 4851 u8 ib_port; 4852 u8 hr_port; 4853 int ret; 4854 4855 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4856 if (unlikely(sl > max_sl)) { 4857 ibdev_err_ratelimited(ibdev, 4858 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n", 4859 sl, max_sl); 4860 return -EINVAL; 4861 } 4862 4863 /* 4864 * If free_mr_en of qp is set, it means that this qp comes from 4865 * free mr. This qp will perform the loopback operation. 4866 * In the loopback scenario, only sl needs to be set. 4867 */ 4868 if (hr_qp->free_mr_en) { 4869 hr_reg_write(context, QPC_SL, sl); 4870 hr_reg_clear(qpc_mask, QPC_SL); 4871 hr_qp->sl = sl; 4872 return 0; 4873 } 4874 4875 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4876 hr_port = ib_port - 1; 4877 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4878 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4879 4880 if (is_roce_protocol) { 4881 gid_attr = attr->ah_attr.grh.sgid_attr; 4882 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4883 if (ret) 4884 return ret; 4885 4886 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4887 } 4888 4889 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4890 if (vlan_id < VLAN_N_VID && 4891 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4892 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4893 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4894 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4895 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4896 } 4897 4898 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4899 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4900 4901 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4902 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4903 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4904 return -EINVAL; 4905 } 4906 4907 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4908 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4909 return -EINVAL; 4910 } 4911 4912 hr_reg_write(context, QPC_UDPSPN, 4913 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4914 attr->dest_qp_num) : 4915 0); 4916 4917 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4918 4919 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4920 4921 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4922 4923 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4924 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4925 4926 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4927 if (ret) 4928 return ret; 4929 4930 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4931 hr_reg_clear(qpc_mask, QPC_TC); 4932 4933 hr_reg_write(context, QPC_FL, grh->flow_label); 4934 hr_reg_clear(qpc_mask, QPC_FL); 4935 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4936 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4937 4938 hr_qp->sl = sl; 4939 hr_reg_write(context, QPC_SL, hr_qp->sl); 4940 hr_reg_clear(qpc_mask, QPC_SL); 4941 4942 return 0; 4943 } 4944 4945 static bool check_qp_state(enum ib_qp_state cur_state, 4946 enum ib_qp_state new_state) 4947 { 4948 static const bool sm[][IB_QPS_ERR + 1] = { 4949 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4950 [IB_QPS_INIT] = true }, 4951 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4952 [IB_QPS_INIT] = true, 4953 [IB_QPS_RTR] = true, 4954 [IB_QPS_ERR] = true }, 4955 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4956 [IB_QPS_RTS] = true, 4957 [IB_QPS_ERR] = true }, 4958 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4959 [IB_QPS_RTS] = true, 4960 [IB_QPS_ERR] = true }, 4961 [IB_QPS_SQD] = {}, 4962 [IB_QPS_SQE] = {}, 4963 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4964 [IB_QPS_ERR] = true } 4965 }; 4966 4967 return sm[cur_state][new_state]; 4968 } 4969 4970 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4971 const struct ib_qp_attr *attr, 4972 int attr_mask, 4973 enum ib_qp_state cur_state, 4974 enum ib_qp_state new_state, 4975 struct hns_roce_v2_qp_context *context, 4976 struct hns_roce_v2_qp_context *qpc_mask, 4977 struct ib_udata *udata) 4978 { 4979 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4980 int ret = 0; 4981 4982 if (!check_qp_state(cur_state, new_state)) 4983 return -EINVAL; 4984 4985 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4986 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4987 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4988 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4989 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4990 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4991 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4992 qpc_mask, udata); 4993 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4994 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4995 qpc_mask); 4996 } 4997 4998 return ret; 4999 } 5000 5001 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5002 { 5003 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5004 #define QP_ACK_TIMEOUT_MAX 31 5005 5006 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5007 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5008 ibdev_warn(&hr_dev->ib_dev, 5009 "local ACK timeout shall be 0 to 20.\n"); 5010 return false; 5011 } 5012 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5013 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5014 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5015 ibdev_warn(&hr_dev->ib_dev, 5016 "local ACK timeout shall be 0 to 31.\n"); 5017 return false; 5018 } 5019 } 5020 5021 return true; 5022 } 5023 5024 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5025 const struct ib_qp_attr *attr, 5026 int attr_mask, 5027 struct hns_roce_v2_qp_context *context, 5028 struct hns_roce_v2_qp_context *qpc_mask) 5029 { 5030 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5031 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5032 int ret = 0; 5033 u8 timeout; 5034 5035 if (attr_mask & IB_QP_AV) { 5036 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5037 qpc_mask); 5038 if (ret) 5039 return ret; 5040 } 5041 5042 if (attr_mask & IB_QP_TIMEOUT) { 5043 timeout = attr->timeout; 5044 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5045 hr_reg_write(context, QPC_AT, timeout); 5046 hr_reg_clear(qpc_mask, QPC_AT); 5047 } 5048 } 5049 5050 if (attr_mask & IB_QP_RETRY_CNT) { 5051 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5052 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5053 5054 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5055 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5056 } 5057 5058 if (attr_mask & IB_QP_RNR_RETRY) { 5059 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5060 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5061 5062 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5063 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5064 } 5065 5066 if (attr_mask & IB_QP_SQ_PSN) { 5067 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5068 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5069 5070 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5071 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5072 5073 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5074 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5075 5076 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5077 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5078 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5079 5080 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5081 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5082 5083 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5084 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5085 } 5086 5087 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5088 attr->max_dest_rd_atomic) { 5089 hr_reg_write(context, QPC_RR_MAX, 5090 fls(attr->max_dest_rd_atomic - 1)); 5091 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5092 } 5093 5094 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5095 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5096 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5097 } 5098 5099 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5100 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5101 5102 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5103 hr_reg_write(context, QPC_MIN_RNR_TIME, 5104 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5105 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5106 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5107 } 5108 5109 if (attr_mask & IB_QP_RQ_PSN) { 5110 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5111 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5112 5113 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5114 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5115 } 5116 5117 if (attr_mask & IB_QP_QKEY) { 5118 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5119 qpc_mask->qkey_xrcd = 0; 5120 hr_qp->qkey = attr->qkey; 5121 } 5122 5123 return ret; 5124 } 5125 5126 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5127 const struct ib_qp_attr *attr, 5128 int attr_mask) 5129 { 5130 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5131 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5132 5133 if (attr_mask & IB_QP_ACCESS_FLAGS) 5134 hr_qp->atomic_rd_en = attr->qp_access_flags; 5135 5136 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5137 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5138 if (attr_mask & IB_QP_PORT) { 5139 hr_qp->port = attr->port_num - 1; 5140 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5141 } 5142 } 5143 5144 static void clear_qp(struct hns_roce_qp *hr_qp) 5145 { 5146 struct ib_qp *ibqp = &hr_qp->ibqp; 5147 5148 if (ibqp->send_cq) 5149 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5150 hr_qp->qpn, NULL); 5151 5152 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5153 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5154 hr_qp->qpn, ibqp->srq ? 5155 to_hr_srq(ibqp->srq) : NULL); 5156 5157 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5158 *hr_qp->rdb.db_record = 0; 5159 5160 hr_qp->rq.head = 0; 5161 hr_qp->rq.tail = 0; 5162 hr_qp->sq.head = 0; 5163 hr_qp->sq.tail = 0; 5164 hr_qp->next_sge = 0; 5165 } 5166 5167 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5168 struct hns_roce_v2_qp_context *context, 5169 struct hns_roce_v2_qp_context *qpc_mask) 5170 { 5171 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5172 unsigned long sq_flag = 0; 5173 unsigned long rq_flag = 0; 5174 5175 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5176 return; 5177 5178 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5179 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5180 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5181 hr_qp->state = IB_QPS_ERR; 5182 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5183 5184 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5185 return; 5186 5187 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5188 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5189 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5190 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5191 } 5192 5193 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5194 const struct ib_qp_attr *attr, 5195 int attr_mask, enum ib_qp_state cur_state, 5196 enum ib_qp_state new_state, struct ib_udata *udata) 5197 { 5198 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5199 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5200 struct hns_roce_v2_qp_context ctx[2]; 5201 struct hns_roce_v2_qp_context *context = ctx; 5202 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5203 struct ib_device *ibdev = &hr_dev->ib_dev; 5204 int ret; 5205 5206 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5207 return -EOPNOTSUPP; 5208 5209 /* 5210 * In v2 engine, software pass context and context mask to hardware 5211 * when modifying qp. If software need modify some fields in context, 5212 * we should set all bits of the relevant fields in context mask to 5213 * 0 at the same time, else set them to 0x1. 5214 */ 5215 memset(context, 0, hr_dev->caps.qpc_sz); 5216 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5217 5218 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5219 new_state, context, qpc_mask, udata); 5220 if (ret) 5221 goto out; 5222 5223 /* When QP state is err, SQ and RQ WQE should be flushed */ 5224 if (new_state == IB_QPS_ERR) 5225 v2_set_flushed_fields(ibqp, context, qpc_mask); 5226 5227 /* Configure the optional fields */ 5228 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5229 qpc_mask); 5230 if (ret) 5231 goto out; 5232 5233 hr_reg_write_bool(context, QPC_INV_CREDIT, 5234 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5235 ibqp->srq); 5236 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5237 5238 /* Every status migrate must change state */ 5239 hr_reg_write(context, QPC_QP_ST, new_state); 5240 hr_reg_clear(qpc_mask, QPC_QP_ST); 5241 5242 /* SW pass context to HW */ 5243 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5244 if (ret) { 5245 ibdev_err_ratelimited(ibdev, "failed to modify QP, ret = %d.\n", ret); 5246 goto out; 5247 } 5248 5249 hr_qp->state = new_state; 5250 5251 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5252 5253 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5254 clear_qp(hr_qp); 5255 5256 out: 5257 return ret; 5258 } 5259 5260 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5261 { 5262 static const enum ib_qp_state map[] = { 5263 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5264 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5265 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5266 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5267 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5268 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5269 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5270 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5271 }; 5272 5273 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5274 } 5275 5276 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5277 void *buffer) 5278 { 5279 struct hns_roce_cmd_mailbox *mailbox; 5280 int ret; 5281 5282 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5283 if (IS_ERR(mailbox)) 5284 return PTR_ERR(mailbox); 5285 5286 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5287 qpn); 5288 if (ret) 5289 goto out; 5290 5291 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5292 5293 out: 5294 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5295 return ret; 5296 } 5297 5298 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5299 struct hns_roce_v2_qp_context *context) 5300 { 5301 u8 timeout; 5302 5303 timeout = (u8)hr_reg_read(context, QPC_AT); 5304 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5305 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5306 5307 return timeout; 5308 } 5309 5310 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5311 int qp_attr_mask, 5312 struct ib_qp_init_attr *qp_init_attr) 5313 { 5314 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5315 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5316 struct hns_roce_v2_qp_context context = {}; 5317 struct ib_device *ibdev = &hr_dev->ib_dev; 5318 int tmp_qp_state; 5319 int state; 5320 int ret; 5321 5322 memset(qp_attr, 0, sizeof(*qp_attr)); 5323 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5324 5325 mutex_lock(&hr_qp->mutex); 5326 5327 if (hr_qp->state == IB_QPS_RESET) { 5328 qp_attr->qp_state = IB_QPS_RESET; 5329 ret = 0; 5330 goto done; 5331 } 5332 5333 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5334 if (ret) { 5335 ibdev_err_ratelimited(ibdev, 5336 "failed to query QPC, ret = %d.\n", 5337 ret); 5338 ret = -EINVAL; 5339 goto out; 5340 } 5341 5342 state = hr_reg_read(&context, QPC_QP_ST); 5343 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5344 if (tmp_qp_state == -1) { 5345 ibdev_err_ratelimited(ibdev, "Illegal ib_qp_state\n"); 5346 ret = -EINVAL; 5347 goto out; 5348 } 5349 hr_qp->state = (u8)tmp_qp_state; 5350 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5351 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5352 qp_attr->path_mig_state = IB_MIG_ARMED; 5353 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5354 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5355 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5356 5357 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5358 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5359 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5360 qp_attr->qp_access_flags = 5361 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5362 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5363 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5364 5365 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5366 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5367 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5368 struct ib_global_route *grh = 5369 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5370 5371 rdma_ah_set_sl(&qp_attr->ah_attr, 5372 hr_reg_read(&context, QPC_SL)); 5373 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5374 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5375 grh->flow_label = hr_reg_read(&context, QPC_FL); 5376 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5377 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5378 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5379 5380 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5381 } 5382 5383 qp_attr->port_num = hr_qp->port + 1; 5384 qp_attr->sq_draining = 0; 5385 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5386 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5387 5388 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5389 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5390 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5391 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5392 5393 done: 5394 qp_attr->cur_qp_state = qp_attr->qp_state; 5395 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5396 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5397 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5398 5399 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5400 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5401 5402 qp_init_attr->qp_context = ibqp->qp_context; 5403 qp_init_attr->qp_type = ibqp->qp_type; 5404 qp_init_attr->recv_cq = ibqp->recv_cq; 5405 qp_init_attr->send_cq = ibqp->send_cq; 5406 qp_init_attr->srq = ibqp->srq; 5407 qp_init_attr->cap = qp_attr->cap; 5408 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5409 5410 out: 5411 mutex_unlock(&hr_qp->mutex); 5412 return ret; 5413 } 5414 5415 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5416 { 5417 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5418 hr_qp->ibqp.qp_type == IB_QPT_UD || 5419 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5420 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5421 hr_qp->state != IB_QPS_RESET); 5422 } 5423 5424 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5425 struct hns_roce_qp *hr_qp, 5426 struct ib_udata *udata) 5427 { 5428 struct ib_device *ibdev = &hr_dev->ib_dev; 5429 struct hns_roce_cq *send_cq, *recv_cq; 5430 unsigned long flags; 5431 int ret = 0; 5432 5433 if (modify_qp_is_ok(hr_qp)) { 5434 /* Modify qp to reset before destroying qp */ 5435 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5436 hr_qp->state, IB_QPS_RESET, udata); 5437 if (ret) 5438 ibdev_err_ratelimited(ibdev, 5439 "failed to modify QP to RST, ret = %d.\n", 5440 ret); 5441 } 5442 5443 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5444 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5445 5446 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5447 hns_roce_lock_cqs(send_cq, recv_cq); 5448 5449 if (!udata) { 5450 if (recv_cq) 5451 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5452 (hr_qp->ibqp.srq ? 5453 to_hr_srq(hr_qp->ibqp.srq) : 5454 NULL)); 5455 5456 if (send_cq && send_cq != recv_cq) 5457 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5458 } 5459 5460 hns_roce_qp_remove(hr_dev, hr_qp); 5461 5462 hns_roce_unlock_cqs(send_cq, recv_cq); 5463 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5464 5465 return ret; 5466 } 5467 5468 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5469 { 5470 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5471 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5472 int ret; 5473 5474 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5475 if (ret) 5476 ibdev_err_ratelimited(&hr_dev->ib_dev, 5477 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5478 hr_qp->qpn, ret); 5479 5480 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5481 5482 return 0; 5483 } 5484 5485 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5486 struct hns_roce_qp *hr_qp) 5487 { 5488 struct ib_device *ibdev = &hr_dev->ib_dev; 5489 struct hns_roce_sccc_clr_done *resp; 5490 struct hns_roce_sccc_clr *clr; 5491 struct hns_roce_cmq_desc desc; 5492 int ret, i; 5493 5494 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5495 return 0; 5496 5497 mutex_lock(&hr_dev->qp_table.scc_mutex); 5498 5499 /* set scc ctx clear done flag */ 5500 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5501 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5502 if (ret) { 5503 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5504 goto out; 5505 } 5506 5507 /* clear scc context */ 5508 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5509 clr = (struct hns_roce_sccc_clr *)desc.data; 5510 clr->qpn = cpu_to_le32(hr_qp->qpn); 5511 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5512 if (ret) { 5513 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5514 goto out; 5515 } 5516 5517 /* query scc context clear is done or not */ 5518 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5519 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5520 hns_roce_cmq_setup_basic_desc(&desc, 5521 HNS_ROCE_OPC_QUERY_SCCC, true); 5522 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5523 if (ret) { 5524 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5525 ret); 5526 goto out; 5527 } 5528 5529 if (resp->clr_done) 5530 goto out; 5531 5532 msleep(20); 5533 } 5534 5535 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5536 ret = -ETIMEDOUT; 5537 5538 out: 5539 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5540 return ret; 5541 } 5542 5543 #define DMA_IDX_SHIFT 3 5544 #define DMA_WQE_SHIFT 3 5545 5546 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5547 struct hns_roce_srq_context *ctx) 5548 { 5549 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5550 struct ib_device *ibdev = srq->ibsrq.device; 5551 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5552 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5553 dma_addr_t dma_handle_idx = 0; 5554 int ret; 5555 5556 /* Get physical address of idx que buf */ 5557 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5558 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5559 if (ret < 1) { 5560 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5561 ret); 5562 return -ENOBUFS; 5563 } 5564 5565 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5566 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5567 5568 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5569 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5570 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5571 5572 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5573 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5574 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5575 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5576 5577 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5578 to_hr_hw_page_addr(mtts_idx[0])); 5579 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5580 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5581 5582 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5583 to_hr_hw_page_addr(mtts_idx[1])); 5584 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5585 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5586 5587 return 0; 5588 } 5589 5590 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5591 { 5592 struct ib_device *ibdev = srq->ibsrq.device; 5593 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5594 struct hns_roce_srq_context *ctx = mb_buf; 5595 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5596 dma_addr_t dma_handle_wqe = 0; 5597 int ret; 5598 5599 memset(ctx, 0, sizeof(*ctx)); 5600 5601 /* Get the physical address of srq buf */ 5602 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5603 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5604 if (ret < 1) { 5605 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5606 ret); 5607 return -ENOBUFS; 5608 } 5609 5610 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5611 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5612 srq->ibsrq.srq_type == IB_SRQT_XRC); 5613 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5614 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5615 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5616 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5617 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5618 hr_reg_write(ctx, SRQC_RQWS, 5619 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5620 5621 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5622 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5623 srq->wqe_cnt)); 5624 5625 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5626 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5627 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5628 5629 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5630 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5631 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5632 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5633 5634 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5635 } 5636 5637 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5638 struct ib_srq_attr *srq_attr, 5639 enum ib_srq_attr_mask srq_attr_mask, 5640 struct ib_udata *udata) 5641 { 5642 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5643 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5644 struct hns_roce_srq_context *srq_context; 5645 struct hns_roce_srq_context *srqc_mask; 5646 struct hns_roce_cmd_mailbox *mailbox; 5647 int ret; 5648 5649 /* Resizing SRQs is not supported yet */ 5650 if (srq_attr_mask & IB_SRQ_MAX_WR) 5651 return -EOPNOTSUPP; 5652 5653 if (srq_attr_mask & IB_SRQ_LIMIT) { 5654 if (srq_attr->srq_limit > srq->wqe_cnt) 5655 return -EINVAL; 5656 5657 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5658 if (IS_ERR(mailbox)) 5659 return PTR_ERR(mailbox); 5660 5661 srq_context = mailbox->buf; 5662 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5663 5664 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5665 5666 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5667 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5668 5669 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5670 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5671 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5672 if (ret) { 5673 ibdev_err(&hr_dev->ib_dev, 5674 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5675 ret); 5676 return ret; 5677 } 5678 } 5679 5680 return 0; 5681 } 5682 5683 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5684 { 5685 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5686 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5687 struct hns_roce_srq_context *srq_context; 5688 struct hns_roce_cmd_mailbox *mailbox; 5689 int ret; 5690 5691 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5692 if (IS_ERR(mailbox)) 5693 return PTR_ERR(mailbox); 5694 5695 srq_context = mailbox->buf; 5696 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5697 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5698 if (ret) { 5699 ibdev_err(&hr_dev->ib_dev, 5700 "failed to process cmd of querying SRQ, ret = %d.\n", 5701 ret); 5702 goto out; 5703 } 5704 5705 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5706 attr->max_wr = srq->wqe_cnt; 5707 attr->max_sge = srq->max_gs - srq->rsv_sge; 5708 5709 out: 5710 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5711 return ret; 5712 } 5713 5714 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5715 { 5716 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5717 struct hns_roce_v2_cq_context *cq_context; 5718 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5719 struct hns_roce_v2_cq_context *cqc_mask; 5720 struct hns_roce_cmd_mailbox *mailbox; 5721 int ret; 5722 5723 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5724 if (IS_ERR(mailbox)) 5725 return PTR_ERR(mailbox); 5726 5727 cq_context = mailbox->buf; 5728 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5729 5730 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5731 5732 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5733 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5734 5735 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5736 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5737 dev_info(hr_dev->dev, 5738 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5739 cq_period); 5740 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5741 } 5742 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5743 } 5744 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5745 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5746 5747 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5748 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5749 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5750 if (ret) 5751 ibdev_err_ratelimited(&hr_dev->ib_dev, 5752 "failed to process cmd when modifying CQ, ret = %d.\n", 5753 ret); 5754 5755 return ret; 5756 } 5757 5758 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5759 void *buffer) 5760 { 5761 struct hns_roce_v2_cq_context *context; 5762 struct hns_roce_cmd_mailbox *mailbox; 5763 int ret; 5764 5765 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5766 if (IS_ERR(mailbox)) 5767 return PTR_ERR(mailbox); 5768 5769 context = mailbox->buf; 5770 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5771 HNS_ROCE_CMD_QUERY_CQC, cqn); 5772 if (ret) { 5773 ibdev_err_ratelimited(&hr_dev->ib_dev, 5774 "failed to process cmd when querying CQ, ret = %d.\n", 5775 ret); 5776 goto err_mailbox; 5777 } 5778 5779 memcpy(buffer, context, sizeof(*context)); 5780 5781 err_mailbox: 5782 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5783 5784 return ret; 5785 } 5786 5787 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5788 void *buffer) 5789 { 5790 struct hns_roce_v2_mpt_entry *context; 5791 struct hns_roce_cmd_mailbox *mailbox; 5792 int ret; 5793 5794 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5795 if (IS_ERR(mailbox)) 5796 return PTR_ERR(mailbox); 5797 5798 context = mailbox->buf; 5799 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5800 key_to_hw_index(key)); 5801 if (ret) { 5802 ibdev_err(&hr_dev->ib_dev, 5803 "failed to process cmd when querying MPT, ret = %d.\n", 5804 ret); 5805 goto err_mailbox; 5806 } 5807 5808 memcpy(buffer, context, sizeof(*context)); 5809 5810 err_mailbox: 5811 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5812 5813 return ret; 5814 } 5815 5816 static void dump_aeqe_log(struct hns_roce_work *irq_work) 5817 { 5818 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 5819 struct ib_device *ibdev = &hr_dev->ib_dev; 5820 5821 switch (irq_work->event_type) { 5822 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5823 ibdev_info(ibdev, "path migrated succeeded.\n"); 5824 break; 5825 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5826 ibdev_warn(ibdev, "path migration failed.\n"); 5827 break; 5828 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5829 break; 5830 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5831 ibdev_dbg(ibdev, "send queue drained.\n"); 5832 break; 5833 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5834 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5835 irq_work->queue_num, irq_work->sub_type); 5836 break; 5837 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5838 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5839 irq_work->queue_num); 5840 break; 5841 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5842 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5843 irq_work->queue_num, irq_work->sub_type); 5844 break; 5845 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5846 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5847 break; 5848 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5849 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 5850 break; 5851 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5852 ibdev_err(ibdev, "SRQ catas error.\n"); 5853 break; 5854 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5855 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5856 break; 5857 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5858 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5859 break; 5860 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5861 ibdev_warn(ibdev, "DB overflow.\n"); 5862 break; 5863 case HNS_ROCE_EVENT_TYPE_MB: 5864 break; 5865 case HNS_ROCE_EVENT_TYPE_FLR: 5866 ibdev_warn(ibdev, "function level reset.\n"); 5867 break; 5868 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5869 ibdev_err(ibdev, "xrc domain violation error.\n"); 5870 break; 5871 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5872 ibdev_err(ibdev, "invalid xrceth error.\n"); 5873 break; 5874 default: 5875 ibdev_info(ibdev, "Undefined event %d.\n", 5876 irq_work->event_type); 5877 break; 5878 } 5879 } 5880 5881 static void hns_roce_irq_work_handle(struct work_struct *work) 5882 { 5883 struct hns_roce_work *irq_work = 5884 container_of(work, struct hns_roce_work, work); 5885 struct hns_roce_dev *hr_dev = irq_work->hr_dev; 5886 int event_type = irq_work->event_type; 5887 u32 queue_num = irq_work->queue_num; 5888 5889 switch (event_type) { 5890 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5891 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5892 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5893 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5894 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5895 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5896 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5897 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5898 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5899 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5900 hns_roce_qp_event(hr_dev, queue_num, event_type); 5901 break; 5902 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5903 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5904 hns_roce_srq_event(hr_dev, queue_num, event_type); 5905 break; 5906 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5907 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5908 hns_roce_cq_event(hr_dev, queue_num, event_type); 5909 break; 5910 default: 5911 break; 5912 } 5913 5914 dump_aeqe_log(irq_work); 5915 5916 kfree(irq_work); 5917 } 5918 5919 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5920 struct hns_roce_eq *eq, u32 queue_num) 5921 { 5922 struct hns_roce_work *irq_work; 5923 5924 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5925 if (!irq_work) 5926 return; 5927 5928 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5929 irq_work->hr_dev = hr_dev; 5930 irq_work->event_type = eq->event_type; 5931 irq_work->sub_type = eq->sub_type; 5932 irq_work->queue_num = queue_num; 5933 queue_work(hr_dev->irq_workq, &irq_work->work); 5934 } 5935 5936 static void update_eq_db(struct hns_roce_eq *eq) 5937 { 5938 struct hns_roce_dev *hr_dev = eq->hr_dev; 5939 struct hns_roce_v2_db eq_db = {}; 5940 5941 if (eq->type_flag == HNS_ROCE_AEQ) { 5942 hr_reg_write(&eq_db, EQ_DB_CMD, 5943 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5944 HNS_ROCE_EQ_DB_CMD_AEQ : 5945 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5946 } else { 5947 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5948 5949 hr_reg_write(&eq_db, EQ_DB_CMD, 5950 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5951 HNS_ROCE_EQ_DB_CMD_CEQ : 5952 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5953 } 5954 5955 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5956 5957 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5958 } 5959 5960 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5961 { 5962 struct hns_roce_aeqe *aeqe; 5963 5964 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5965 (eq->cons_index & (eq->entries - 1)) * 5966 eq->eqe_size); 5967 5968 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5969 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5970 } 5971 5972 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5973 struct hns_roce_eq *eq) 5974 { 5975 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5976 irqreturn_t aeqe_found = IRQ_NONE; 5977 int num_aeqes = 0; 5978 int event_type; 5979 u32 queue_num; 5980 int sub_type; 5981 5982 while (aeqe && num_aeqes < HNS_AEQ_POLLING_BUDGET) { 5983 /* Make sure we read AEQ entry after we have checked the 5984 * ownership bit 5985 */ 5986 dma_rmb(); 5987 5988 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5989 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5990 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5991 5992 switch (event_type) { 5993 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5994 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5995 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5996 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5997 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5998 hns_roce_flush_cqe(hr_dev, queue_num); 5999 break; 6000 case HNS_ROCE_EVENT_TYPE_MB: 6001 hns_roce_cmd_event(hr_dev, 6002 le16_to_cpu(aeqe->event.cmd.token), 6003 aeqe->event.cmd.status, 6004 le64_to_cpu(aeqe->event.cmd.out_param)); 6005 break; 6006 default: 6007 break; 6008 } 6009 6010 eq->event_type = event_type; 6011 eq->sub_type = sub_type; 6012 ++eq->cons_index; 6013 aeqe_found = IRQ_HANDLED; 6014 6015 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6016 6017 aeqe = next_aeqe_sw_v2(eq); 6018 ++num_aeqes; 6019 } 6020 6021 update_eq_db(eq); 6022 6023 return IRQ_RETVAL(aeqe_found); 6024 } 6025 6026 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6027 { 6028 struct hns_roce_ceqe *ceqe; 6029 6030 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6031 (eq->cons_index & (eq->entries - 1)) * 6032 eq->eqe_size); 6033 6034 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6035 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6036 } 6037 6038 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6039 struct hns_roce_eq *eq) 6040 { 6041 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6042 irqreturn_t ceqe_found = IRQ_NONE; 6043 u32 cqn; 6044 6045 while (ceqe) { 6046 /* Make sure we read CEQ entry after we have checked the 6047 * ownership bit 6048 */ 6049 dma_rmb(); 6050 6051 cqn = hr_reg_read(ceqe, CEQE_CQN); 6052 6053 hns_roce_cq_completion(hr_dev, cqn); 6054 6055 ++eq->cons_index; 6056 ceqe_found = IRQ_HANDLED; 6057 6058 ceqe = next_ceqe_sw_v2(eq); 6059 } 6060 6061 update_eq_db(eq); 6062 6063 return IRQ_RETVAL(ceqe_found); 6064 } 6065 6066 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6067 { 6068 struct hns_roce_eq *eq = eq_ptr; 6069 struct hns_roce_dev *hr_dev = eq->hr_dev; 6070 irqreturn_t int_work; 6071 6072 if (eq->type_flag == HNS_ROCE_CEQ) 6073 /* Completion event interrupt */ 6074 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6075 else 6076 /* Asynchronous event interrupt */ 6077 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6078 6079 return IRQ_RETVAL(int_work); 6080 } 6081 6082 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6083 u32 int_st) 6084 { 6085 struct pci_dev *pdev = hr_dev->pci_dev; 6086 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6087 const struct hnae3_ae_ops *ops = ae_dev->ops; 6088 enum hnae3_reset_type reset_type; 6089 irqreturn_t int_work = IRQ_NONE; 6090 u32 int_en; 6091 6092 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6093 6094 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6095 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6096 6097 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6098 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6099 6100 reset_type = hr_dev->is_vf ? 6101 HNAE3_VF_FUNC_RESET : HNAE3_FUNC_RESET; 6102 6103 /* Set reset level for reset_event() */ 6104 if (ops->set_default_reset_request) 6105 ops->set_default_reset_request(ae_dev, reset_type); 6106 if (ops->reset_event) 6107 ops->reset_event(pdev, NULL); 6108 6109 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6110 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6111 6112 int_work = IRQ_HANDLED; 6113 } else { 6114 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6115 } 6116 6117 return IRQ_RETVAL(int_work); 6118 } 6119 6120 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6121 struct fmea_ram_ecc *ecc_info) 6122 { 6123 struct hns_roce_cmq_desc desc; 6124 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6125 int ret; 6126 6127 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6128 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6129 if (ret) 6130 return ret; 6131 6132 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6133 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6134 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6135 6136 return 0; 6137 } 6138 6139 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6140 { 6141 struct hns_roce_cmq_desc desc; 6142 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6143 u32 addr_upper; 6144 u32 addr_low; 6145 int ret; 6146 6147 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6148 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6149 6150 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6151 if (ret) { 6152 dev_err(hr_dev->dev, 6153 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6154 return ret; 6155 } 6156 6157 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6158 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6159 6160 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6161 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6162 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6163 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6164 6165 return hns_roce_cmq_send(hr_dev, &desc, 1); 6166 } 6167 6168 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6169 { 6170 if (res_type == ECC_RESOURCE_QPC_TIMER || 6171 res_type == ECC_RESOURCE_CQC_TIMER || 6172 res_type == ECC_RESOURCE_SCCC) 6173 return le64_to_cpu(*data); 6174 6175 return le64_to_cpu(*data) << HNS_HW_PAGE_SHIFT; 6176 } 6177 6178 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6179 u32 index) 6180 { 6181 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6182 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6183 struct hns_roce_cmd_mailbox *mailbox; 6184 u64 addr; 6185 int ret; 6186 6187 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6188 if (IS_ERR(mailbox)) 6189 return PTR_ERR(mailbox); 6190 6191 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6192 if (ret) { 6193 dev_err(hr_dev->dev, 6194 "failed to execute cmd to read fmea ram, ret = %d.\n", 6195 ret); 6196 goto out; 6197 } 6198 6199 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6200 6201 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6202 if (ret) 6203 dev_err(hr_dev->dev, 6204 "failed to execute cmd to write fmea ram, ret = %d.\n", 6205 ret); 6206 6207 out: 6208 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6209 return ret; 6210 } 6211 6212 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6213 struct fmea_ram_ecc *ecc_info) 6214 { 6215 u32 res_type = ecc_info->res_type; 6216 u32 index = ecc_info->index; 6217 int ret; 6218 6219 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6220 6221 if (res_type >= ECC_RESOURCE_COUNT) { 6222 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6223 res_type); 6224 return; 6225 } 6226 6227 if (res_type == ECC_RESOURCE_GMV) 6228 ret = fmea_recover_gmv(hr_dev, index); 6229 else 6230 ret = fmea_recover_others(hr_dev, res_type, index); 6231 if (ret) 6232 dev_err(hr_dev->dev, 6233 "failed to recover %s, index = %u, ret = %d.\n", 6234 fmea_ram_res[res_type].name, index, ret); 6235 } 6236 6237 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6238 { 6239 struct hns_roce_dev *hr_dev = 6240 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6241 struct fmea_ram_ecc ecc_info = {}; 6242 6243 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6244 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6245 return; 6246 } 6247 6248 if (!ecc_info.is_ecc_err) { 6249 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6250 return; 6251 } 6252 6253 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6254 } 6255 6256 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6257 { 6258 struct hns_roce_dev *hr_dev = dev_id; 6259 irqreturn_t int_work = IRQ_NONE; 6260 u32 int_st; 6261 6262 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6263 6264 if (int_st) { 6265 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6266 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6267 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6268 int_work = IRQ_HANDLED; 6269 } else { 6270 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6271 } 6272 6273 return IRQ_RETVAL(int_work); 6274 } 6275 6276 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6277 int eq_num, u32 enable_flag) 6278 { 6279 int i; 6280 6281 for (i = 0; i < eq_num; i++) 6282 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6283 i * EQ_REG_OFFSET, enable_flag); 6284 6285 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6286 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6287 } 6288 6289 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6290 { 6291 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6292 } 6293 6294 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, 6295 struct hns_roce_eq *eq) 6296 { 6297 struct device *dev = hr_dev->dev; 6298 int eqn = eq->eqn; 6299 int ret; 6300 u8 cmd; 6301 6302 if (eqn < hr_dev->caps.num_comp_vectors) 6303 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6304 else 6305 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6306 6307 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6308 if (ret) 6309 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 6310 6311 free_eq_buf(hr_dev, eq); 6312 } 6313 6314 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6315 { 6316 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6317 eq->cons_index = 0; 6318 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6319 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6320 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6321 eq->shift = ilog2((unsigned int)eq->entries); 6322 } 6323 6324 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6325 void *mb_buf) 6326 { 6327 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6328 struct hns_roce_eq_context *eqc; 6329 u64 bt_ba = 0; 6330 int count; 6331 6332 eqc = mb_buf; 6333 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6334 6335 init_eq_config(hr_dev, eq); 6336 6337 /* if not multi-hop, eqe buffer only use one trunk */ 6338 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6339 &bt_ba); 6340 if (count < 1) { 6341 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6342 return -ENOBUFS; 6343 } 6344 6345 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6346 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6347 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6348 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6349 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6350 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6351 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6352 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6353 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6354 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6355 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6356 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6357 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6358 6359 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6360 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6361 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6362 eq->eq_period); 6363 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6364 } 6365 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6366 } 6367 6368 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6369 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6370 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6371 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6372 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6373 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6374 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6375 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6376 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6377 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6378 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6379 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6380 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6381 6382 return 0; 6383 } 6384 6385 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6386 { 6387 struct hns_roce_buf_attr buf_attr = {}; 6388 int err; 6389 6390 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6391 eq->hop_num = 0; 6392 else 6393 eq->hop_num = hr_dev->caps.eqe_hop_num; 6394 6395 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6396 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6397 buf_attr.region[0].hopnum = eq->hop_num; 6398 buf_attr.region_count = 1; 6399 6400 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6401 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6402 0); 6403 if (err) 6404 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6405 6406 return err; 6407 } 6408 6409 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6410 struct hns_roce_eq *eq, u8 eq_cmd) 6411 { 6412 struct hns_roce_cmd_mailbox *mailbox; 6413 int ret; 6414 6415 /* Allocate mailbox memory */ 6416 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6417 if (IS_ERR(mailbox)) 6418 return PTR_ERR(mailbox); 6419 6420 ret = alloc_eq_buf(hr_dev, eq); 6421 if (ret) 6422 goto free_cmd_mbox; 6423 6424 ret = config_eqc(hr_dev, eq, mailbox->buf); 6425 if (ret) 6426 goto err_cmd_mbox; 6427 6428 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6429 if (ret) { 6430 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6431 goto err_cmd_mbox; 6432 } 6433 6434 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6435 6436 return 0; 6437 6438 err_cmd_mbox: 6439 free_eq_buf(hr_dev, eq); 6440 6441 free_cmd_mbox: 6442 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6443 6444 return ret; 6445 } 6446 6447 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6448 int comp_num, int aeq_num, int other_num) 6449 { 6450 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6451 int i, j; 6452 int ret; 6453 6454 for (i = 0; i < irq_num; i++) { 6455 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6456 GFP_KERNEL); 6457 if (!hr_dev->irq_names[i]) { 6458 ret = -ENOMEM; 6459 goto err_kzalloc_failed; 6460 } 6461 } 6462 6463 /* irq contains: abnormal + AEQ + CEQ */ 6464 for (j = 0; j < other_num; j++) 6465 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6466 "hns-abn-%d", j); 6467 6468 for (j = other_num; j < (other_num + aeq_num); j++) 6469 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6470 "hns-aeq-%d", j - other_num); 6471 6472 for (j = (other_num + aeq_num); j < irq_num; j++) 6473 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6474 "hns-ceq-%d", j - other_num - aeq_num); 6475 6476 for (j = 0; j < irq_num; j++) { 6477 if (j < other_num) 6478 ret = request_irq(hr_dev->irq[j], 6479 hns_roce_v2_msix_interrupt_abn, 6480 0, hr_dev->irq_names[j], hr_dev); 6481 6482 else if (j < (other_num + comp_num)) 6483 ret = request_irq(eq_table->eq[j - other_num].irq, 6484 hns_roce_v2_msix_interrupt_eq, 6485 0, hr_dev->irq_names[j + aeq_num], 6486 &eq_table->eq[j - other_num]); 6487 else 6488 ret = request_irq(eq_table->eq[j - other_num].irq, 6489 hns_roce_v2_msix_interrupt_eq, 6490 0, hr_dev->irq_names[j - comp_num], 6491 &eq_table->eq[j - other_num]); 6492 if (ret) { 6493 dev_err(hr_dev->dev, "request irq error!\n"); 6494 goto err_request_failed; 6495 } 6496 } 6497 6498 return 0; 6499 6500 err_request_failed: 6501 for (j -= 1; j >= 0; j--) 6502 if (j < other_num) 6503 free_irq(hr_dev->irq[j], hr_dev); 6504 else 6505 free_irq(eq_table->eq[j - other_num].irq, 6506 &eq_table->eq[j - other_num]); 6507 6508 err_kzalloc_failed: 6509 for (i -= 1; i >= 0; i--) 6510 kfree(hr_dev->irq_names[i]); 6511 6512 return ret; 6513 } 6514 6515 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6516 { 6517 int irq_num; 6518 int eq_num; 6519 int i; 6520 6521 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6522 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6523 6524 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6525 free_irq(hr_dev->irq[i], hr_dev); 6526 6527 for (i = 0; i < eq_num; i++) 6528 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6529 6530 for (i = 0; i < irq_num; i++) 6531 kfree(hr_dev->irq_names[i]); 6532 } 6533 6534 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6535 { 6536 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6537 struct device *dev = hr_dev->dev; 6538 struct hns_roce_eq *eq; 6539 int other_num; 6540 int comp_num; 6541 int aeq_num; 6542 int irq_num; 6543 int eq_num; 6544 u8 eq_cmd; 6545 int ret; 6546 int i; 6547 6548 if (hr_dev->caps.aeqe_depth < HNS_AEQ_POLLING_BUDGET) 6549 return -EINVAL; 6550 6551 other_num = hr_dev->caps.num_other_vectors; 6552 comp_num = hr_dev->caps.num_comp_vectors; 6553 aeq_num = hr_dev->caps.num_aeq_vectors; 6554 6555 eq_num = comp_num + aeq_num; 6556 irq_num = eq_num + other_num; 6557 6558 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6559 if (!eq_table->eq) 6560 return -ENOMEM; 6561 6562 /* create eq */ 6563 for (i = 0; i < eq_num; i++) { 6564 eq = &eq_table->eq[i]; 6565 eq->hr_dev = hr_dev; 6566 eq->eqn = i; 6567 if (i < comp_num) { 6568 /* CEQ */ 6569 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6570 eq->type_flag = HNS_ROCE_CEQ; 6571 eq->entries = hr_dev->caps.ceqe_depth; 6572 eq->eqe_size = hr_dev->caps.ceqe_size; 6573 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6574 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6575 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6576 } else { 6577 /* AEQ */ 6578 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6579 eq->type_flag = HNS_ROCE_AEQ; 6580 eq->entries = hr_dev->caps.aeqe_depth; 6581 eq->eqe_size = hr_dev->caps.aeqe_size; 6582 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6583 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6584 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6585 } 6586 6587 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6588 if (ret) { 6589 dev_err(dev, "failed to create eq.\n"); 6590 goto err_create_eq_fail; 6591 } 6592 } 6593 6594 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6595 6596 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6597 if (!hr_dev->irq_workq) { 6598 dev_err(dev, "failed to create irq workqueue.\n"); 6599 ret = -ENOMEM; 6600 goto err_create_eq_fail; 6601 } 6602 6603 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6604 other_num); 6605 if (ret) { 6606 dev_err(dev, "failed to request irq.\n"); 6607 goto err_request_irq_fail; 6608 } 6609 6610 /* enable irq */ 6611 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6612 6613 return 0; 6614 6615 err_request_irq_fail: 6616 destroy_workqueue(hr_dev->irq_workq); 6617 6618 err_create_eq_fail: 6619 for (i -= 1; i >= 0; i--) 6620 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6621 kfree(eq_table->eq); 6622 6623 return ret; 6624 } 6625 6626 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6627 { 6628 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6629 int eq_num; 6630 int i; 6631 6632 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6633 6634 /* Disable irq */ 6635 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6636 6637 __hns_roce_free_irq(hr_dev); 6638 destroy_workqueue(hr_dev->irq_workq); 6639 6640 for (i = 0; i < eq_num; i++) 6641 hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]); 6642 6643 kfree(eq_table->eq); 6644 } 6645 6646 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6647 .destroy_qp = hns_roce_v2_destroy_qp, 6648 .modify_cq = hns_roce_v2_modify_cq, 6649 .poll_cq = hns_roce_v2_poll_cq, 6650 .post_recv = hns_roce_v2_post_recv, 6651 .post_send = hns_roce_v2_post_send, 6652 .query_qp = hns_roce_v2_query_qp, 6653 .req_notify_cq = hns_roce_v2_req_notify_cq, 6654 }; 6655 6656 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6657 .modify_srq = hns_roce_v2_modify_srq, 6658 .post_srq_recv = hns_roce_v2_post_srq_recv, 6659 .query_srq = hns_roce_v2_query_srq, 6660 }; 6661 6662 static const struct hns_roce_hw hns_roce_hw_v2 = { 6663 .cmq_init = hns_roce_v2_cmq_init, 6664 .cmq_exit = hns_roce_v2_cmq_exit, 6665 .hw_profile = hns_roce_v2_profile, 6666 .hw_init = hns_roce_v2_init, 6667 .hw_exit = hns_roce_v2_exit, 6668 .post_mbox = v2_post_mbox, 6669 .poll_mbox_done = v2_poll_mbox_done, 6670 .chk_mbox_avail = v2_chk_mbox_is_avail, 6671 .set_gid = hns_roce_v2_set_gid, 6672 .set_mac = hns_roce_v2_set_mac, 6673 .write_mtpt = hns_roce_v2_write_mtpt, 6674 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6675 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6676 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6677 .write_cqc = hns_roce_v2_write_cqc, 6678 .set_hem = hns_roce_v2_set_hem, 6679 .clear_hem = hns_roce_v2_clear_hem, 6680 .modify_qp = hns_roce_v2_modify_qp, 6681 .dereg_mr = hns_roce_v2_dereg_mr, 6682 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6683 .init_eq = hns_roce_v2_init_eq_table, 6684 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6685 .write_srqc = hns_roce_v2_write_srqc, 6686 .query_cqc = hns_roce_v2_query_cqc, 6687 .query_qpc = hns_roce_v2_query_qpc, 6688 .query_mpt = hns_roce_v2_query_mpt, 6689 .query_hw_counter = hns_roce_hw_v2_query_counter, 6690 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6691 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6692 }; 6693 6694 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6695 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6696 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6697 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6698 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6699 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6700 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6701 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6702 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6703 /* required last entry */ 6704 {0, } 6705 }; 6706 6707 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6708 6709 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6710 struct hnae3_handle *handle) 6711 { 6712 struct hns_roce_v2_priv *priv = hr_dev->priv; 6713 const struct pci_device_id *id; 6714 int i; 6715 6716 hr_dev->pci_dev = handle->pdev; 6717 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6718 hr_dev->is_vf = id->driver_data; 6719 hr_dev->dev = &handle->pdev->dev; 6720 hr_dev->hw = &hns_roce_hw_v2; 6721 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6722 hr_dev->odb_offset = hr_dev->sdb_offset; 6723 6724 /* Get info from NIC driver. */ 6725 hr_dev->reg_base = handle->rinfo.roce_io_base; 6726 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6727 hr_dev->caps.num_ports = 1; 6728 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6729 hr_dev->iboe.phy_port[0] = 0; 6730 6731 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6732 hr_dev->iboe.netdevs[0]->dev_addr); 6733 6734 for (i = 0; i < handle->rinfo.num_vectors; i++) 6735 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6736 i + handle->rinfo.base_vector); 6737 6738 /* cmd issue mode: 0 is poll, 1 is event */ 6739 hr_dev->cmd_mod = 1; 6740 hr_dev->loop_idc = 0; 6741 6742 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6743 priv->handle = handle; 6744 } 6745 6746 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6747 { 6748 struct hns_roce_dev *hr_dev; 6749 int ret; 6750 6751 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6752 if (!hr_dev) 6753 return -ENOMEM; 6754 6755 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6756 if (!hr_dev->priv) { 6757 ret = -ENOMEM; 6758 goto error_failed_kzalloc; 6759 } 6760 6761 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6762 6763 ret = hns_roce_init(hr_dev); 6764 if (ret) { 6765 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6766 goto error_failed_roce_init; 6767 } 6768 6769 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6770 ret = free_mr_init(hr_dev); 6771 if (ret) { 6772 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6773 goto error_failed_free_mr_init; 6774 } 6775 } 6776 6777 handle->priv = hr_dev; 6778 6779 return 0; 6780 6781 error_failed_free_mr_init: 6782 hns_roce_exit(hr_dev); 6783 6784 error_failed_roce_init: 6785 kfree(hr_dev->priv); 6786 6787 error_failed_kzalloc: 6788 ib_dealloc_device(&hr_dev->ib_dev); 6789 6790 return ret; 6791 } 6792 6793 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6794 bool reset) 6795 { 6796 struct hns_roce_dev *hr_dev = handle->priv; 6797 6798 if (!hr_dev) 6799 return; 6800 6801 handle->priv = NULL; 6802 6803 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6804 hns_roce_handle_device_err(hr_dev); 6805 6806 hns_roce_exit(hr_dev); 6807 kfree(hr_dev->priv); 6808 ib_dealloc_device(&hr_dev->ib_dev); 6809 } 6810 6811 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6812 { 6813 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6814 const struct pci_device_id *id; 6815 struct device *dev = &handle->pdev->dev; 6816 int ret; 6817 6818 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6819 6820 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6821 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6822 goto reset_chk_err; 6823 } 6824 6825 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6826 if (!id) 6827 return 0; 6828 6829 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6830 return 0; 6831 6832 ret = __hns_roce_hw_v2_init_instance(handle); 6833 if (ret) { 6834 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6835 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6836 if (ops->ae_dev_resetting(handle) || 6837 ops->get_hw_reset_stat(handle)) 6838 goto reset_chk_err; 6839 else 6840 return ret; 6841 } 6842 6843 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6844 6845 return 0; 6846 6847 reset_chk_err: 6848 dev_err(dev, "Device is busy in resetting state.\n" 6849 "please retry later.\n"); 6850 6851 return -EBUSY; 6852 } 6853 6854 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6855 bool reset) 6856 { 6857 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6858 return; 6859 6860 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6861 6862 __hns_roce_hw_v2_uninit_instance(handle, reset); 6863 6864 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6865 } 6866 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6867 { 6868 struct hns_roce_dev *hr_dev; 6869 6870 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6871 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6872 return 0; 6873 } 6874 6875 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6876 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6877 6878 hr_dev = handle->priv; 6879 if (!hr_dev) 6880 return 0; 6881 6882 hr_dev->active = false; 6883 hr_dev->dis_db = true; 6884 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6885 6886 return 0; 6887 } 6888 6889 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6890 { 6891 struct device *dev = &handle->pdev->dev; 6892 int ret; 6893 6894 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6895 &handle->rinfo.state)) { 6896 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6897 return 0; 6898 } 6899 6900 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6901 6902 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6903 ret = __hns_roce_hw_v2_init_instance(handle); 6904 if (ret) { 6905 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6906 * callback function, RoCE Engine reinitialize. If RoCE reinit 6907 * failed, we should inform NIC driver. 6908 */ 6909 handle->priv = NULL; 6910 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6911 } else { 6912 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6913 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6914 } 6915 6916 return ret; 6917 } 6918 6919 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6920 { 6921 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6922 return 0; 6923 6924 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6925 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6926 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6927 __hns_roce_hw_v2_uninit_instance(handle, false); 6928 6929 return 0; 6930 } 6931 6932 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6933 enum hnae3_reset_notify_type type) 6934 { 6935 int ret = 0; 6936 6937 switch (type) { 6938 case HNAE3_DOWN_CLIENT: 6939 ret = hns_roce_hw_v2_reset_notify_down(handle); 6940 break; 6941 case HNAE3_INIT_CLIENT: 6942 ret = hns_roce_hw_v2_reset_notify_init(handle); 6943 break; 6944 case HNAE3_UNINIT_CLIENT: 6945 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6946 break; 6947 default: 6948 break; 6949 } 6950 6951 return ret; 6952 } 6953 6954 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6955 .init_instance = hns_roce_hw_v2_init_instance, 6956 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6957 .reset_notify = hns_roce_hw_v2_reset_notify, 6958 }; 6959 6960 static struct hnae3_client hns_roce_hw_v2_client = { 6961 .name = "hns_roce_hw_v2", 6962 .type = HNAE3_CLIENT_ROCE, 6963 .ops = &hns_roce_hw_v2_ops, 6964 }; 6965 6966 static int __init hns_roce_hw_v2_init(void) 6967 { 6968 return hnae3_register_client(&hns_roce_hw_v2_client); 6969 } 6970 6971 static void __exit hns_roce_hw_v2_exit(void) 6972 { 6973 hnae3_unregister_client(&hns_roce_hw_v2_client); 6974 } 6975 6976 module_init(hns_roce_hw_v2_init); 6977 module_exit(hns_roce_hw_v2_exit); 6978 6979 MODULE_LICENSE("Dual BSD/GPL"); 6980 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6981 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6982 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6983 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6984