1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 enum { 52 CMD_RST_PRC_OTHERS, 53 CMD_RST_PRC_SUCCESS, 54 CMD_RST_PRC_EBUSY, 55 }; 56 57 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 58 struct ib_sge *sg) 59 { 60 dseg->lkey = cpu_to_le32(sg->lkey); 61 dseg->addr = cpu_to_le64(sg->addr); 62 dseg->len = cpu_to_le32(sg->length); 63 } 64 65 /* 66 * mapped-value = 1 + real-value 67 * The hns wr opcode real value is start from 0, In order to distinguish between 68 * initialized and uninitialized map values, we plus 1 to the actual value when 69 * defining the mapping, so that the validity can be identified by checking the 70 * mapped value is greater than 0. 71 */ 72 #define HR_OPC_MAP(ib_key, hr_key) \ 73 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 74 75 static const u32 hns_roce_op_code[] = { 76 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 77 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 78 HR_OPC_MAP(SEND, SEND), 79 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 80 HR_OPC_MAP(RDMA_READ, RDMA_READ), 81 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 82 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 83 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 84 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 85 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 86 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 87 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 88 }; 89 90 static u32 to_hr_opcode(u32 ib_opcode) 91 { 92 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 93 return HNS_ROCE_V2_WQE_OP_MASK; 94 95 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 96 HNS_ROCE_V2_WQE_OP_MASK; 97 } 98 99 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 100 const struct ib_reg_wr *wr) 101 { 102 struct hns_roce_wqe_frmr_seg *fseg = 103 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 104 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 105 u64 pbl_ba; 106 107 /* use ib_access_flags */ 108 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 109 hr_reg_write_bool(fseg, FRMR_ATOMIC, 110 wr->access & IB_ACCESS_REMOTE_ATOMIC); 111 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 112 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 113 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 114 115 /* Data structure reuse may lead to confusion */ 116 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 117 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 118 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 119 120 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 121 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 122 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 123 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 124 125 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 126 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 127 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 128 hr_reg_clear(fseg, FRMR_BLK_MODE); 129 } 130 131 static void set_atomic_seg(const struct ib_send_wr *wr, 132 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 133 unsigned int valid_num_sge) 134 { 135 struct hns_roce_v2_wqe_data_seg *dseg = 136 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 137 struct hns_roce_wqe_atomic_seg *aseg = 138 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 139 140 set_data_seg_v2(dseg, wr->sg_list); 141 142 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 143 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 144 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 145 } else { 146 aseg->fetchadd_swap_data = 147 cpu_to_le64(atomic_wr(wr)->compare_add); 148 aseg->cmp_data = 0; 149 } 150 151 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 152 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 153 } 154 155 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 156 const struct ib_send_wr *wr, 157 unsigned int *sge_idx, u32 msg_len) 158 { 159 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 160 unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg); 161 unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len; 162 unsigned int left_len_in_pg; 163 unsigned int idx = *sge_idx; 164 unsigned int i = 0; 165 unsigned int len; 166 void *addr; 167 void *dseg; 168 169 if (msg_len > ext_sge_sz) { 170 ibdev_err(ibdev, 171 "no enough extended sge space for inline data.\n"); 172 return -EINVAL; 173 } 174 175 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 176 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 177 len = wr->sg_list[0].length; 178 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 179 180 /* When copying data to extended sge space, the left length in page may 181 * not long enough for current user's sge. So the data should be 182 * splited into several parts, one in the first page, and the others in 183 * the subsequent pages. 184 */ 185 while (1) { 186 if (len <= left_len_in_pg) { 187 memcpy(dseg, addr, len); 188 189 idx += len / dseg_len; 190 191 i++; 192 if (i >= wr->num_sge) 193 break; 194 195 left_len_in_pg -= len; 196 len = wr->sg_list[i].length; 197 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 198 dseg += len; 199 } else { 200 memcpy(dseg, addr, left_len_in_pg); 201 202 len -= left_len_in_pg; 203 addr += left_len_in_pg; 204 idx += left_len_in_pg / dseg_len; 205 dseg = hns_roce_get_extend_sge(qp, 206 idx & (qp->sge.sge_cnt - 1)); 207 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 208 } 209 } 210 211 *sge_idx = idx; 212 213 return 0; 214 } 215 216 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 217 unsigned int *sge_ind, unsigned int cnt) 218 { 219 struct hns_roce_v2_wqe_data_seg *dseg; 220 unsigned int idx = *sge_ind; 221 222 while (cnt > 0) { 223 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 224 if (likely(sge->length)) { 225 set_data_seg_v2(dseg, sge); 226 idx++; 227 cnt--; 228 } 229 sge++; 230 } 231 232 *sge_ind = idx; 233 } 234 235 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 236 { 237 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 238 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 239 240 if (len > qp->max_inline_data || len > mtu) { 241 ibdev_err(&hr_dev->ib_dev, 242 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 243 len, qp->max_inline_data, mtu); 244 return false; 245 } 246 247 return true; 248 } 249 250 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 251 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 252 unsigned int *sge_idx) 253 { 254 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 255 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 256 struct ib_device *ibdev = &hr_dev->ib_dev; 257 unsigned int curr_idx = *sge_idx; 258 void *dseg = rc_sq_wqe; 259 unsigned int i; 260 int ret; 261 262 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 263 ibdev_err(ibdev, "invalid inline parameters!\n"); 264 return -EINVAL; 265 } 266 267 if (!check_inl_data_len(qp, msg_len)) 268 return -EINVAL; 269 270 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 271 272 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 273 roce_set_bit(rc_sq_wqe->byte_20, 274 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0); 275 276 for (i = 0; i < wr->num_sge; i++) { 277 memcpy(dseg, ((void *)wr->sg_list[i].addr), 278 wr->sg_list[i].length); 279 dseg += wr->sg_list[i].length; 280 } 281 } else { 282 roce_set_bit(rc_sq_wqe->byte_20, 283 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1); 284 285 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 286 if (ret) 287 return ret; 288 289 roce_set_field(rc_sq_wqe->byte_16, 290 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 291 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, 292 curr_idx - *sge_idx); 293 } 294 295 *sge_idx = curr_idx; 296 297 return 0; 298 } 299 300 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 301 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 302 unsigned int *sge_ind, 303 unsigned int valid_num_sge) 304 { 305 struct hns_roce_v2_wqe_data_seg *dseg = 306 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 307 struct hns_roce_qp *qp = to_hr_qp(ibqp); 308 int j = 0; 309 int i; 310 311 roce_set_field(rc_sq_wqe->byte_20, 312 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 313 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 314 (*sge_ind) & (qp->sge.sge_cnt - 1)); 315 316 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 317 !!(wr->send_flags & IB_SEND_INLINE)); 318 if (wr->send_flags & IB_SEND_INLINE) 319 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 320 321 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 322 for (i = 0; i < wr->num_sge; i++) { 323 if (likely(wr->sg_list[i].length)) { 324 set_data_seg_v2(dseg, wr->sg_list + i); 325 dseg++; 326 } 327 } 328 } else { 329 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 330 if (likely(wr->sg_list[i].length)) { 331 set_data_seg_v2(dseg, wr->sg_list + i); 332 dseg++; 333 j++; 334 } 335 } 336 337 set_extend_sge(qp, wr->sg_list + i, sge_ind, 338 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 339 } 340 341 roce_set_field(rc_sq_wqe->byte_16, 342 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 343 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 344 345 return 0; 346 } 347 348 static int check_send_valid(struct hns_roce_dev *hr_dev, 349 struct hns_roce_qp *hr_qp) 350 { 351 struct ib_device *ibdev = &hr_dev->ib_dev; 352 struct ib_qp *ibqp = &hr_qp->ibqp; 353 354 if (unlikely(ibqp->qp_type != IB_QPT_RC && 355 ibqp->qp_type != IB_QPT_GSI && 356 ibqp->qp_type != IB_QPT_UD)) { 357 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 358 ibqp->qp_type); 359 return -EOPNOTSUPP; 360 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 361 hr_qp->state == IB_QPS_INIT || 362 hr_qp->state == IB_QPS_RTR)) { 363 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 364 hr_qp->state); 365 return -EINVAL; 366 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 367 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 368 hr_dev->state); 369 return -EIO; 370 } 371 372 return 0; 373 } 374 375 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 376 unsigned int *sge_len) 377 { 378 unsigned int valid_num = 0; 379 unsigned int len = 0; 380 int i; 381 382 for (i = 0; i < wr->num_sge; i++) { 383 if (likely(wr->sg_list[i].length)) { 384 len += wr->sg_list[i].length; 385 valid_num++; 386 } 387 } 388 389 *sge_len = len; 390 return valid_num; 391 } 392 393 static __le32 get_immtdata(const struct ib_send_wr *wr) 394 { 395 switch (wr->opcode) { 396 case IB_WR_SEND_WITH_IMM: 397 case IB_WR_RDMA_WRITE_WITH_IMM: 398 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 399 default: 400 return 0; 401 } 402 } 403 404 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 405 const struct ib_send_wr *wr) 406 { 407 u32 ib_op = wr->opcode; 408 409 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 410 return -EINVAL; 411 412 ud_sq_wqe->immtdata = get_immtdata(wr); 413 414 roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 415 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 416 417 return 0; 418 } 419 420 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 421 struct hns_roce_ah *ah) 422 { 423 struct ib_device *ib_dev = ah->ibah.device; 424 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 425 426 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 427 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport); 428 429 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 430 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 431 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 432 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 433 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 434 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 435 436 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 437 return -EINVAL; 438 439 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 440 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 441 442 ud_sq_wqe->sgid_index = ah->av.gid_index; 443 444 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 445 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 446 447 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 448 return 0; 449 450 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 451 ah->av.vlan_en); 452 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 453 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 454 455 return 0; 456 } 457 458 static inline int set_ud_wqe(struct hns_roce_qp *qp, 459 const struct ib_send_wr *wr, 460 void *wqe, unsigned int *sge_idx, 461 unsigned int owner_bit) 462 { 463 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 464 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 465 unsigned int curr_idx = *sge_idx; 466 unsigned int valid_num_sge; 467 u32 msg_len = 0; 468 int ret; 469 470 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 471 472 ret = set_ud_opcode(ud_sq_wqe, wr); 473 if (WARN_ON(ret)) 474 return ret; 475 476 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 477 478 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 479 !!(wr->send_flags & IB_SEND_SIGNALED)); 480 481 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 482 !!(wr->send_flags & IB_SEND_SOLICITED)); 483 484 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 485 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 486 487 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 488 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 489 490 roce_set_field(ud_sq_wqe->byte_20, 491 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 492 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 493 curr_idx & (qp->sge.sge_cnt - 1)); 494 495 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 496 qp->qkey : ud_wr(wr)->remote_qkey); 497 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 498 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 519 owner_bit); 520 521 return 0; 522 } 523 524 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 525 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 526 const struct ib_send_wr *wr) 527 { 528 u32 ib_op = wr->opcode; 529 int ret = 0; 530 531 rc_sq_wqe->immtdata = get_immtdata(wr); 532 533 switch (ib_op) { 534 case IB_WR_RDMA_READ: 535 case IB_WR_RDMA_WRITE: 536 case IB_WR_RDMA_WRITE_WITH_IMM: 537 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 538 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 539 break; 540 case IB_WR_SEND: 541 case IB_WR_SEND_WITH_IMM: 542 break; 543 case IB_WR_ATOMIC_CMP_AND_SWP: 544 case IB_WR_ATOMIC_FETCH_AND_ADD: 545 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 546 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 547 break; 548 case IB_WR_REG_MR: 549 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 550 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 551 else 552 ret = -EOPNOTSUPP; 553 break; 554 case IB_WR_LOCAL_INV: 555 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 556 fallthrough; 557 case IB_WR_SEND_WITH_INV: 558 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 559 break; 560 default: 561 ret = -EINVAL; 562 } 563 564 if (unlikely(ret)) 565 return ret; 566 567 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 568 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 569 570 return ret; 571 } 572 static inline int set_rc_wqe(struct hns_roce_qp *qp, 573 const struct ib_send_wr *wr, 574 void *wqe, unsigned int *sge_idx, 575 unsigned int owner_bit) 576 { 577 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 578 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 579 unsigned int curr_idx = *sge_idx; 580 unsigned int valid_num_sge; 581 u32 msg_len = 0; 582 int ret; 583 584 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 585 586 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 587 588 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 589 if (WARN_ON(ret)) 590 return ret; 591 592 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 593 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 594 595 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 596 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 597 598 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 599 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 600 601 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 602 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 603 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 604 else if (wr->opcode != IB_WR_REG_MR) 605 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 606 &curr_idx, valid_num_sge); 607 608 /* 609 * The pipeline can sequentially post all valid WQEs into WQ buffer, 610 * including new WQEs waiting for the doorbell to update the PI again. 611 * Therefore, the owner bit of WQE MUST be updated after all fields 612 * and extSGEs have been written into DDR instead of cache. 613 */ 614 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 615 dma_wmb(); 616 617 *sge_idx = curr_idx; 618 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 619 owner_bit); 620 621 return ret; 622 } 623 624 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 625 struct hns_roce_qp *qp) 626 { 627 if (unlikely(qp->state == IB_QPS_ERR)) { 628 flush_cqe(hr_dev, qp); 629 } else { 630 struct hns_roce_v2_db sq_db = {}; 631 632 hr_reg_write(&sq_db, DB_TAG, qp->doorbell_qpn); 633 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 634 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 635 hr_reg_write(&sq_db, DB_SL, qp->sl); 636 637 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 638 } 639 } 640 641 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 642 struct hns_roce_qp *qp) 643 { 644 if (unlikely(qp->state == IB_QPS_ERR)) { 645 flush_cqe(hr_dev, qp); 646 } else { 647 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 648 *qp->rdb.db_record = 649 qp->rq.head & V2_DB_PRODUCER_IDX_M; 650 } else { 651 struct hns_roce_v2_db rq_db = {}; 652 653 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 654 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 655 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 656 657 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 658 qp->rq.db_reg); 659 } 660 } 661 } 662 663 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 664 u64 __iomem *dest) 665 { 666 #define HNS_ROCE_WRITE_TIMES 8 667 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 668 struct hnae3_handle *handle = priv->handle; 669 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 670 int i; 671 672 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 673 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 674 writeq_relaxed(*(val + i), dest + i); 675 } 676 677 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 678 void *wqe) 679 { 680 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 681 682 /* All kinds of DirectWQE have the same header field layout */ 683 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); 684 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, 685 V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); 686 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, 687 V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); 688 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, 689 V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); 690 691 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 692 } 693 694 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 695 const struct ib_send_wr *wr, 696 const struct ib_send_wr **bad_wr) 697 { 698 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 699 struct ib_device *ibdev = &hr_dev->ib_dev; 700 struct hns_roce_qp *qp = to_hr_qp(ibqp); 701 unsigned long flags = 0; 702 unsigned int owner_bit; 703 unsigned int sge_idx; 704 unsigned int wqe_idx; 705 void *wqe = NULL; 706 u32 nreq; 707 int ret; 708 709 spin_lock_irqsave(&qp->sq.lock, flags); 710 711 ret = check_send_valid(hr_dev, qp); 712 if (unlikely(ret)) { 713 *bad_wr = wr; 714 nreq = 0; 715 goto out; 716 } 717 718 sge_idx = qp->next_sge; 719 720 for (nreq = 0; wr; ++nreq, wr = wr->next) { 721 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 722 ret = -ENOMEM; 723 *bad_wr = wr; 724 goto out; 725 } 726 727 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 728 729 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 730 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 731 wr->num_sge, qp->sq.max_gs); 732 ret = -EINVAL; 733 *bad_wr = wr; 734 goto out; 735 } 736 737 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 738 qp->sq.wrid[wqe_idx] = wr->wr_id; 739 owner_bit = 740 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 741 742 /* Corresponding to the QP type, wqe process separately */ 743 if (ibqp->qp_type == IB_QPT_RC) 744 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 745 else 746 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 747 748 if (unlikely(ret)) { 749 *bad_wr = wr; 750 goto out; 751 } 752 } 753 754 out: 755 if (likely(nreq)) { 756 qp->sq.head += nreq; 757 qp->next_sge = sge_idx; 758 759 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 760 write_dwqe(hr_dev, qp, wqe); 761 else 762 update_sq_db(hr_dev, qp); 763 } 764 765 spin_unlock_irqrestore(&qp->sq.lock, flags); 766 767 return ret; 768 } 769 770 static int check_recv_valid(struct hns_roce_dev *hr_dev, 771 struct hns_roce_qp *hr_qp) 772 { 773 struct ib_device *ibdev = &hr_dev->ib_dev; 774 struct ib_qp *ibqp = &hr_qp->ibqp; 775 776 if (unlikely(ibqp->qp_type != IB_QPT_RC && 777 ibqp->qp_type != IB_QPT_GSI && 778 ibqp->qp_type != IB_QPT_UD)) { 779 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 780 ibqp->qp_type); 781 return -EOPNOTSUPP; 782 } 783 784 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 785 return -EIO; 786 787 if (hr_qp->state == IB_QPS_RESET) 788 return -EINVAL; 789 790 return 0; 791 } 792 793 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 794 u32 max_sge, bool rsv) 795 { 796 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 797 u32 i, cnt; 798 799 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 800 /* Skip zero-length sge */ 801 if (!wr->sg_list[i].length) 802 continue; 803 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 804 cnt++; 805 } 806 807 /* Fill a reserved sge to make hw stop reading remaining segments */ 808 if (rsv) { 809 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 810 dseg[cnt].addr = 0; 811 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 812 } else { 813 /* Clear remaining segments to make ROCEE ignore sges */ 814 if (cnt < max_sge) 815 memset(dseg + cnt, 0, 816 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 817 } 818 } 819 820 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 821 u32 wqe_idx, u32 max_sge) 822 { 823 struct hns_roce_rinl_sge *sge_list; 824 void *wqe = NULL; 825 u32 i; 826 827 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 828 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 829 830 /* rq support inline data */ 831 if (hr_qp->rq_inl_buf.wqe_cnt) { 832 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 833 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 834 for (i = 0; i < wr->num_sge; i++) { 835 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 836 sge_list[i].len = wr->sg_list[i].length; 837 } 838 } 839 } 840 841 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 842 const struct ib_recv_wr *wr, 843 const struct ib_recv_wr **bad_wr) 844 { 845 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 846 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 847 struct ib_device *ibdev = &hr_dev->ib_dev; 848 u32 wqe_idx, nreq, max_sge; 849 unsigned long flags; 850 int ret; 851 852 spin_lock_irqsave(&hr_qp->rq.lock, flags); 853 854 ret = check_recv_valid(hr_dev, hr_qp); 855 if (unlikely(ret)) { 856 *bad_wr = wr; 857 nreq = 0; 858 goto out; 859 } 860 861 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 862 for (nreq = 0; wr; ++nreq, wr = wr->next) { 863 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 864 hr_qp->ibqp.recv_cq))) { 865 ret = -ENOMEM; 866 *bad_wr = wr; 867 goto out; 868 } 869 870 if (unlikely(wr->num_sge > max_sge)) { 871 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 872 wr->num_sge, max_sge); 873 ret = -EINVAL; 874 *bad_wr = wr; 875 goto out; 876 } 877 878 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 879 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 880 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 881 } 882 883 out: 884 if (likely(nreq)) { 885 hr_qp->rq.head += nreq; 886 887 update_rq_db(hr_dev, hr_qp); 888 } 889 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 890 891 return ret; 892 } 893 894 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 895 { 896 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 897 } 898 899 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 900 { 901 return hns_roce_buf_offset(idx_que->mtr.kmem, 902 n << idx_que->entry_shift); 903 } 904 905 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 906 { 907 /* always called with interrupts disabled. */ 908 spin_lock(&srq->lock); 909 910 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 911 srq->idx_que.tail++; 912 913 spin_unlock(&srq->lock); 914 } 915 916 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 917 { 918 struct hns_roce_idx_que *idx_que = &srq->idx_que; 919 920 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 921 } 922 923 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 924 const struct ib_recv_wr *wr) 925 { 926 struct ib_device *ib_dev = srq->ibsrq.device; 927 928 if (unlikely(wr->num_sge > max_sge)) { 929 ibdev_err(ib_dev, 930 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 931 wr->num_sge, max_sge); 932 return -EINVAL; 933 } 934 935 if (unlikely(hns_roce_srqwq_overflow(srq))) { 936 ibdev_err(ib_dev, 937 "failed to check srqwq status, srqwq is full.\n"); 938 return -ENOMEM; 939 } 940 941 return 0; 942 } 943 944 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 945 { 946 struct hns_roce_idx_que *idx_que = &srq->idx_que; 947 u32 pos; 948 949 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 950 if (unlikely(pos == srq->wqe_cnt)) 951 return -ENOSPC; 952 953 bitmap_set(idx_que->bitmap, pos, 1); 954 *wqe_idx = pos; 955 return 0; 956 } 957 958 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 959 { 960 struct hns_roce_idx_que *idx_que = &srq->idx_que; 961 unsigned int head; 962 __le32 *buf; 963 964 head = idx_que->head & (srq->wqe_cnt - 1); 965 966 buf = get_idx_buf(idx_que, head); 967 *buf = cpu_to_le32(wqe_idx); 968 969 idx_que->head++; 970 } 971 972 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 973 { 974 hr_reg_write(db, DB_TAG, srq->srqn); 975 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 976 hr_reg_write(db, DB_PI, srq->idx_que.head); 977 } 978 979 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 980 const struct ib_recv_wr *wr, 981 const struct ib_recv_wr **bad_wr) 982 { 983 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 984 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 985 struct hns_roce_v2_db srq_db; 986 unsigned long flags; 987 int ret = 0; 988 u32 max_sge; 989 u32 wqe_idx; 990 void *wqe; 991 u32 nreq; 992 993 spin_lock_irqsave(&srq->lock, flags); 994 995 max_sge = srq->max_gs - srq->rsv_sge; 996 for (nreq = 0; wr; ++nreq, wr = wr->next) { 997 ret = check_post_srq_valid(srq, max_sge, wr); 998 if (ret) { 999 *bad_wr = wr; 1000 break; 1001 } 1002 1003 ret = get_srq_wqe_idx(srq, &wqe_idx); 1004 if (unlikely(ret)) { 1005 *bad_wr = wr; 1006 break; 1007 } 1008 1009 wqe = get_srq_wqe_buf(srq, wqe_idx); 1010 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1011 fill_wqe_idx(srq, wqe_idx); 1012 srq->wrid[wqe_idx] = wr->wr_id; 1013 } 1014 1015 if (likely(nreq)) { 1016 update_srq_db(&srq_db, srq); 1017 1018 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1019 } 1020 1021 spin_unlock_irqrestore(&srq->lock, flags); 1022 1023 return ret; 1024 } 1025 1026 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1027 unsigned long instance_stage, 1028 unsigned long reset_stage) 1029 { 1030 /* When hardware reset has been completed once or more, we should stop 1031 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1032 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1033 * stage of soft reset process, we should exit with error, and then 1034 * HNAE3_INIT_CLIENT related process can rollback the operation like 1035 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1036 * process will exit with error to notify NIC driver to reschedule soft 1037 * reset process once again. 1038 */ 1039 hr_dev->is_reset = true; 1040 hr_dev->dis_db = true; 1041 1042 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1043 instance_stage == HNS_ROCE_STATE_INIT) 1044 return CMD_RST_PRC_EBUSY; 1045 1046 return CMD_RST_PRC_SUCCESS; 1047 } 1048 1049 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1050 unsigned long instance_stage, 1051 unsigned long reset_stage) 1052 { 1053 struct hns_roce_v2_priv *priv = hr_dev->priv; 1054 struct hnae3_handle *handle = priv->handle; 1055 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1056 1057 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1058 * doorbell to hardware. If now in .init_instance() function, we should 1059 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1060 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1061 * related process can rollback the operation like notifing hardware to 1062 * free resources, HNAE3_INIT_CLIENT related process will exit with 1063 * error to notify NIC driver to reschedule soft reset process once 1064 * again. 1065 */ 1066 hr_dev->dis_db = true; 1067 if (!ops->get_hw_reset_stat(handle)) 1068 hr_dev->is_reset = true; 1069 1070 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1071 instance_stage == HNS_ROCE_STATE_INIT) 1072 return CMD_RST_PRC_EBUSY; 1073 1074 return CMD_RST_PRC_SUCCESS; 1075 } 1076 1077 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1078 { 1079 struct hns_roce_v2_priv *priv = hr_dev->priv; 1080 struct hnae3_handle *handle = priv->handle; 1081 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1082 1083 /* When software reset is detected at .init_instance() function, we 1084 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1085 * with error. 1086 */ 1087 hr_dev->dis_db = true; 1088 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1089 hr_dev->is_reset = true; 1090 1091 return CMD_RST_PRC_EBUSY; 1092 } 1093 1094 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1095 struct hnae3_handle *handle) 1096 { 1097 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1098 unsigned long instance_stage; /* the current instance stage */ 1099 unsigned long reset_stage; /* the current reset stage */ 1100 unsigned long reset_cnt; 1101 bool sw_resetting; 1102 bool hw_resetting; 1103 1104 /* Get information about reset from NIC driver or RoCE driver itself, 1105 * the meaning of the following variables from NIC driver are described 1106 * as below: 1107 * reset_cnt -- The count value of completed hardware reset. 1108 * hw_resetting -- Whether hardware device is resetting now. 1109 * sw_resetting -- Whether NIC's software reset process is running now. 1110 */ 1111 instance_stage = handle->rinfo.instance_state; 1112 reset_stage = handle->rinfo.reset_state; 1113 reset_cnt = ops->ae_dev_reset_cnt(handle); 1114 if (reset_cnt != hr_dev->reset_cnt) 1115 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1116 reset_stage); 1117 1118 hw_resetting = ops->get_cmdq_stat(handle); 1119 if (hw_resetting) 1120 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1121 reset_stage); 1122 1123 sw_resetting = ops->ae_dev_resetting(handle); 1124 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1125 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1126 1127 return CMD_RST_PRC_OTHERS; 1128 } 1129 1130 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1131 { 1132 struct hns_roce_v2_priv *priv = hr_dev->priv; 1133 struct hnae3_handle *handle = priv->handle; 1134 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1135 1136 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1137 return true; 1138 1139 if (ops->get_hw_reset_stat(handle)) 1140 return true; 1141 1142 if (ops->ae_dev_resetting(handle)) 1143 return true; 1144 1145 return false; 1146 } 1147 1148 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1149 { 1150 struct hns_roce_v2_priv *priv = hr_dev->priv; 1151 u32 status; 1152 1153 if (hr_dev->is_reset) 1154 status = CMD_RST_PRC_SUCCESS; 1155 else 1156 status = check_aedev_reset_status(hr_dev, priv->handle); 1157 1158 *busy = (status == CMD_RST_PRC_EBUSY); 1159 1160 return status == CMD_RST_PRC_OTHERS; 1161 } 1162 1163 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1164 struct hns_roce_v2_cmq_ring *ring) 1165 { 1166 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1167 1168 ring->desc = kzalloc(size, GFP_KERNEL); 1169 if (!ring->desc) 1170 return -ENOMEM; 1171 1172 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 1173 DMA_BIDIRECTIONAL); 1174 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 1175 ring->desc_dma_addr = 0; 1176 kfree(ring->desc); 1177 ring->desc = NULL; 1178 1179 return -ENOMEM; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1186 struct hns_roce_v2_cmq_ring *ring) 1187 { 1188 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 1189 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1190 DMA_BIDIRECTIONAL); 1191 1192 ring->desc_dma_addr = 0; 1193 kfree(ring->desc); 1194 } 1195 1196 static int init_csq(struct hns_roce_dev *hr_dev, 1197 struct hns_roce_v2_cmq_ring *csq) 1198 { 1199 dma_addr_t dma; 1200 int ret; 1201 1202 csq->desc_num = CMD_CSQ_DESC_NUM; 1203 spin_lock_init(&csq->lock); 1204 csq->flag = TYPE_CSQ; 1205 csq->head = 0; 1206 1207 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1208 if (ret) 1209 return ret; 1210 1211 dma = csq->desc_dma_addr; 1212 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1213 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1214 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1215 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1216 1217 /* Make sure to write CI first and then PI */ 1218 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1219 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1220 1221 return 0; 1222 } 1223 1224 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1225 { 1226 struct hns_roce_v2_priv *priv = hr_dev->priv; 1227 int ret; 1228 1229 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1230 1231 ret = init_csq(hr_dev, &priv->cmq.csq); 1232 if (ret) 1233 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1234 1235 return ret; 1236 } 1237 1238 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1239 { 1240 struct hns_roce_v2_priv *priv = hr_dev->priv; 1241 1242 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1243 } 1244 1245 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1246 enum hns_roce_opcode_type opcode, 1247 bool is_read) 1248 { 1249 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1250 desc->opcode = cpu_to_le16(opcode); 1251 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1252 if (is_read) 1253 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1254 else 1255 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1256 } 1257 1258 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1259 { 1260 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1261 struct hns_roce_v2_priv *priv = hr_dev->priv; 1262 1263 return tail == priv->cmq.csq.head; 1264 } 1265 1266 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1267 struct hns_roce_cmq_desc *desc, int num) 1268 { 1269 struct hns_roce_v2_priv *priv = hr_dev->priv; 1270 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1271 u32 timeout = 0; 1272 u16 desc_ret; 1273 u32 tail; 1274 int ret; 1275 int i; 1276 1277 spin_lock_bh(&csq->lock); 1278 1279 tail = csq->head; 1280 1281 for (i = 0; i < num; i++) { 1282 csq->desc[csq->head++] = desc[i]; 1283 if (csq->head == csq->desc_num) 1284 csq->head = 0; 1285 } 1286 1287 /* Write to hardware */ 1288 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1289 1290 do { 1291 if (hns_roce_cmq_csq_done(hr_dev)) 1292 break; 1293 udelay(1); 1294 } while (++timeout < priv->cmq.tx_timeout); 1295 1296 if (hns_roce_cmq_csq_done(hr_dev)) { 1297 for (ret = 0, i = 0; i < num; i++) { 1298 /* check the result of hardware write back */ 1299 desc[i] = csq->desc[tail++]; 1300 if (tail == csq->desc_num) 1301 tail = 0; 1302 1303 desc_ret = le16_to_cpu(desc[i].retval); 1304 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1305 continue; 1306 1307 dev_err_ratelimited(hr_dev->dev, 1308 "Cmdq IO error, opcode = %x, return = %x\n", 1309 desc->opcode, desc_ret); 1310 ret = -EIO; 1311 } 1312 } else { 1313 /* FW/HW reset or incorrect number of desc */ 1314 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1315 dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n", 1316 csq->head, tail); 1317 csq->head = tail; 1318 1319 ret = -EAGAIN; 1320 } 1321 1322 spin_unlock_bh(&csq->lock); 1323 1324 return ret; 1325 } 1326 1327 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1328 struct hns_roce_cmq_desc *desc, int num) 1329 { 1330 bool busy; 1331 int ret; 1332 1333 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1334 return busy ? -EBUSY : 0; 1335 1336 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1337 if (ret) { 1338 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1339 return busy ? -EBUSY : 0; 1340 } 1341 1342 return ret; 1343 } 1344 1345 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 1346 dma_addr_t base_addr, u16 op) 1347 { 1348 struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1349 int ret; 1350 1351 if (IS_ERR(mbox)) 1352 return PTR_ERR(mbox); 1353 1354 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op, 1355 HNS_ROCE_CMD_TIMEOUT_MSECS); 1356 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1357 return ret; 1358 } 1359 1360 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1361 { 1362 struct hns_roce_query_version *resp; 1363 struct hns_roce_cmq_desc desc; 1364 int ret; 1365 1366 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1367 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1368 if (ret) 1369 return ret; 1370 1371 resp = (struct hns_roce_query_version *)desc.data; 1372 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1373 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1374 1375 return 0; 1376 } 1377 1378 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1379 struct hnae3_handle *handle) 1380 { 1381 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1382 unsigned long end; 1383 1384 hr_dev->dis_db = true; 1385 1386 dev_warn(hr_dev->dev, 1387 "Func clear is pending, device in resetting state.\n"); 1388 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1389 while (end) { 1390 if (!ops->get_hw_reset_stat(handle)) { 1391 hr_dev->is_reset = true; 1392 dev_info(hr_dev->dev, 1393 "Func clear success after reset.\n"); 1394 return; 1395 } 1396 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1397 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1398 } 1399 1400 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1401 } 1402 1403 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1404 struct hnae3_handle *handle) 1405 { 1406 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1407 unsigned long end; 1408 1409 hr_dev->dis_db = true; 1410 1411 dev_warn(hr_dev->dev, 1412 "Func clear is pending, device in resetting state.\n"); 1413 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1414 while (end) { 1415 if (ops->ae_dev_reset_cnt(handle) != 1416 hr_dev->reset_cnt) { 1417 hr_dev->is_reset = true; 1418 dev_info(hr_dev->dev, 1419 "Func clear success after sw reset\n"); 1420 return; 1421 } 1422 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1423 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1424 } 1425 1426 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1427 } 1428 1429 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1430 int flag) 1431 { 1432 struct hns_roce_v2_priv *priv = hr_dev->priv; 1433 struct hnae3_handle *handle = priv->handle; 1434 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1435 1436 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1437 hr_dev->dis_db = true; 1438 hr_dev->is_reset = true; 1439 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1440 return; 1441 } 1442 1443 if (ops->get_hw_reset_stat(handle)) { 1444 func_clr_hw_resetting_state(hr_dev, handle); 1445 return; 1446 } 1447 1448 if (ops->ae_dev_resetting(handle) && 1449 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1450 func_clr_sw_resetting_state(hr_dev, handle); 1451 return; 1452 } 1453 1454 if (retval && !flag) 1455 dev_warn(hr_dev->dev, 1456 "Func clear read failed, ret = %d.\n", retval); 1457 1458 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1459 } 1460 1461 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1462 { 1463 bool fclr_write_fail_flag = false; 1464 struct hns_roce_func_clear *resp; 1465 struct hns_roce_cmq_desc desc; 1466 unsigned long end; 1467 int ret = 0; 1468 1469 if (check_device_is_in_reset(hr_dev)) 1470 goto out; 1471 1472 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1473 resp = (struct hns_roce_func_clear *)desc.data; 1474 resp->rst_funcid_en = cpu_to_le32(vf_id); 1475 1476 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1477 if (ret) { 1478 fclr_write_fail_flag = true; 1479 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1480 ret); 1481 goto out; 1482 } 1483 1484 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1485 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1486 while (end) { 1487 if (check_device_is_in_reset(hr_dev)) 1488 goto out; 1489 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1490 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1491 1492 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1493 true); 1494 1495 resp->rst_funcid_en = cpu_to_le32(vf_id); 1496 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1497 if (ret) 1498 continue; 1499 1500 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1501 if (vf_id == 0) 1502 hr_dev->is_reset = true; 1503 return; 1504 } 1505 } 1506 1507 out: 1508 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1509 } 1510 1511 static void hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1512 { 1513 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1514 struct hns_roce_cmq_desc desc[2]; 1515 struct hns_roce_cmq_req *req_a; 1516 1517 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1518 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1519 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1520 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1521 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1522 hns_roce_cmq_send(hr_dev, desc, 2); 1523 } 1524 1525 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1526 { 1527 int i; 1528 1529 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1530 __hns_roce_function_clear(hr_dev, i); 1531 if (i != 0) 1532 hns_roce_free_vf_resource(hr_dev, i); 1533 } 1534 } 1535 1536 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1537 { 1538 struct hns_roce_cmq_desc desc; 1539 int ret; 1540 1541 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1542 false); 1543 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1544 if (ret) 1545 ibdev_err(&hr_dev->ib_dev, 1546 "failed to clear extended doorbell info, ret = %d.\n", 1547 ret); 1548 1549 return ret; 1550 } 1551 1552 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1553 { 1554 struct hns_roce_query_fw_info *resp; 1555 struct hns_roce_cmq_desc desc; 1556 int ret; 1557 1558 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1559 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1560 if (ret) 1561 return ret; 1562 1563 resp = (struct hns_roce_query_fw_info *)desc.data; 1564 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1565 1566 return 0; 1567 } 1568 1569 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1570 { 1571 struct hns_roce_cmq_desc desc; 1572 int ret; 1573 1574 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) { 1575 hr_dev->func_num = 1; 1576 return 0; 1577 } 1578 1579 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1580 true); 1581 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1582 if (ret) { 1583 hr_dev->func_num = 1; 1584 return ret; 1585 } 1586 1587 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1588 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1589 1590 return 0; 1591 } 1592 1593 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1594 { 1595 struct hns_roce_cmq_desc desc; 1596 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1597 1598 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1599 false); 1600 1601 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, 0x3e8); 1602 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1603 1604 return hns_roce_cmq_send(hr_dev, &desc, 1); 1605 } 1606 1607 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1608 { 1609 struct hns_roce_cmq_desc desc[2]; 1610 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1611 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1612 struct hns_roce_caps *caps = &hr_dev->caps; 1613 enum hns_roce_opcode_type opcode; 1614 u32 func_num; 1615 int ret; 1616 1617 if (is_vf) { 1618 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1619 func_num = 1; 1620 } else { 1621 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1622 func_num = hr_dev->func_num; 1623 } 1624 1625 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1626 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1627 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1628 1629 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1630 if (ret) 1631 return ret; 1632 1633 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1634 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1635 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1636 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1637 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1638 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1639 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1640 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1641 1642 if (is_vf) { 1643 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1644 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1645 func_num; 1646 } else { 1647 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1648 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1649 func_num; 1650 } 1651 1652 return 0; 1653 } 1654 1655 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1656 { 1657 struct hns_roce_cmq_desc desc; 1658 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1659 struct hns_roce_caps *caps = &hr_dev->caps; 1660 u32 func_num, qp_num; 1661 int ret; 1662 1663 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1664 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1665 if (ret) 1666 return ret; 1667 1668 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1669 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1670 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1671 1672 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1673 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1674 1675 return 0; 1676 } 1677 1678 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1679 { 1680 struct hns_roce_cmq_desc desc; 1681 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1682 struct hns_roce_caps *caps = &hr_dev->caps; 1683 int ret; 1684 1685 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1686 true); 1687 1688 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1689 if (ret) 1690 return ret; 1691 1692 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1693 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1694 1695 return 0; 1696 } 1697 1698 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1699 { 1700 struct device *dev = hr_dev->dev; 1701 int ret; 1702 1703 ret = load_func_res_caps(hr_dev, is_vf); 1704 if (ret) { 1705 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1706 is_vf ? "vf" : "pf"); 1707 return ret; 1708 } 1709 1710 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1711 ret = load_ext_cfg_caps(hr_dev, is_vf); 1712 if (ret) 1713 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1714 ret, is_vf ? "vf" : "pf"); 1715 } 1716 1717 return ret; 1718 } 1719 1720 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1721 { 1722 struct device *dev = hr_dev->dev; 1723 int ret; 1724 1725 ret = query_func_resource_caps(hr_dev, false); 1726 if (ret) 1727 return ret; 1728 1729 ret = load_pf_timer_res_caps(hr_dev); 1730 if (ret) 1731 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1732 ret); 1733 1734 return ret; 1735 } 1736 1737 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1738 { 1739 return query_func_resource_caps(hr_dev, true); 1740 } 1741 1742 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1743 u32 vf_id) 1744 { 1745 struct hns_roce_vf_switch *swt; 1746 struct hns_roce_cmq_desc desc; 1747 int ret; 1748 1749 swt = (struct hns_roce_vf_switch *)desc.data; 1750 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1751 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1752 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1753 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1754 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1755 if (ret) 1756 return ret; 1757 1758 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1759 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1760 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1761 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1762 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1763 1764 return hns_roce_cmq_send(hr_dev, &desc, 1); 1765 } 1766 1767 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1768 { 1769 u32 vf_id; 1770 int ret; 1771 1772 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1773 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1774 if (ret) 1775 return ret; 1776 } 1777 return 0; 1778 } 1779 1780 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1781 { 1782 struct hns_roce_cmq_desc desc[2]; 1783 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1784 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1785 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1786 struct hns_roce_caps *caps = &hr_dev->caps; 1787 1788 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1789 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1790 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1791 1792 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1793 1794 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1795 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1796 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1797 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1798 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1799 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1800 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1801 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1802 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1803 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1804 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1805 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1806 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1807 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1808 1809 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1810 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1811 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1812 vf_id * caps->gmv_bt_num); 1813 } else { 1814 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1815 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1816 vf_id * caps->sgid_bt_num); 1817 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1818 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1819 vf_id * caps->smac_bt_num); 1820 } 1821 1822 return hns_roce_cmq_send(hr_dev, desc, 2); 1823 } 1824 1825 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1826 { 1827 struct hns_roce_cmq_desc desc; 1828 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1829 struct hns_roce_caps *caps = &hr_dev->caps; 1830 1831 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1832 1833 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1834 1835 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1836 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1837 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1838 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1839 1840 return hns_roce_cmq_send(hr_dev, &desc, 1); 1841 } 1842 1843 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1844 { 1845 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1846 u32 vf_id; 1847 int ret; 1848 1849 for (vf_id = 0; vf_id < func_num; vf_id++) { 1850 ret = config_vf_hem_resource(hr_dev, vf_id); 1851 if (ret) { 1852 dev_err(hr_dev->dev, 1853 "failed to config vf-%u hem res, ret = %d.\n", 1854 vf_id, ret); 1855 return ret; 1856 } 1857 1858 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1859 ret = config_vf_ext_resource(hr_dev, vf_id); 1860 if (ret) { 1861 dev_err(hr_dev->dev, 1862 "failed to config vf-%u ext res, ret = %d.\n", 1863 vf_id, ret); 1864 return ret; 1865 } 1866 } 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1873 { 1874 struct hns_roce_cmq_desc desc; 1875 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1876 struct hns_roce_caps *caps = &hr_dev->caps; 1877 1878 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1879 1880 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1881 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1882 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1883 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1884 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1885 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1886 1887 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1888 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1889 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1890 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1891 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1892 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1893 1894 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1895 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1896 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1897 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1898 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1899 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1900 1901 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1902 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1903 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1904 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1905 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1906 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1907 1908 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1909 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1910 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1911 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1912 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1913 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1914 1915 return hns_roce_cmq_send(hr_dev, &desc, 1); 1916 } 1917 1918 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1919 static void set_default_caps(struct hns_roce_dev *hr_dev) 1920 { 1921 struct hns_roce_caps *caps = &hr_dev->caps; 1922 1923 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1924 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1925 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1926 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1927 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1928 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1929 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1930 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1931 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1932 1933 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1934 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1935 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1936 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1937 caps->num_comp_vectors = 0; 1938 1939 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1940 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1941 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1942 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1943 1944 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1945 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1946 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1947 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1948 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1949 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1950 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1951 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1952 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1953 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1954 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1955 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1956 caps->reserved_lkey = 0; 1957 caps->reserved_pds = 0; 1958 caps->reserved_mrws = 1; 1959 caps->reserved_uars = 0; 1960 caps->reserved_cqs = 0; 1961 caps->reserved_srqs = 0; 1962 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1963 1964 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1965 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1966 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1967 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1968 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1969 1970 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1971 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1972 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1973 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1974 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1975 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1976 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1977 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1978 1979 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1980 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1981 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 1982 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 1983 1984 caps->pkey_table_len[0] = 1; 1985 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1986 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1987 caps->local_ca_ack_delay = 0; 1988 caps->max_mtu = IB_MTU_4096; 1989 1990 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1991 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1992 1993 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1994 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1995 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; 1996 1997 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1998 1999 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2000 caps->flags |= HNS_ROCE_CAP_FLAG_STASH; 2001 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 2002 } else { 2003 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 2004 2005 /* The following configuration are only valid for HIP08 */ 2006 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2007 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 2008 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2009 } 2010 } 2011 2012 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2013 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2014 { 2015 u64 obj_per_chunk; 2016 u64 bt_chunk_size = PAGE_SIZE; 2017 u64 buf_chunk_size = PAGE_SIZE; 2018 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2019 2020 *buf_page_size = 0; 2021 *bt_page_size = 0; 2022 2023 switch (hop_num) { 2024 case 3: 2025 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2026 (bt_chunk_size / BA_BYTE_LEN) * 2027 (bt_chunk_size / BA_BYTE_LEN) * 2028 obj_per_chunk_default; 2029 break; 2030 case 2: 2031 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2032 (bt_chunk_size / BA_BYTE_LEN) * 2033 obj_per_chunk_default; 2034 break; 2035 case 1: 2036 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2037 obj_per_chunk_default; 2038 break; 2039 case HNS_ROCE_HOP_NUM_0: 2040 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2041 break; 2042 default: 2043 pr_err("table %u not support hop_num = %u!\n", hem_type, 2044 hop_num); 2045 return; 2046 } 2047 2048 if (hem_type >= HEM_TYPE_MTT) 2049 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2050 else 2051 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2052 } 2053 2054 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2055 { 2056 struct hns_roce_caps *caps = &hr_dev->caps; 2057 2058 /* EQ */ 2059 caps->eqe_ba_pg_sz = 0; 2060 caps->eqe_buf_pg_sz = 0; 2061 2062 /* Link Table */ 2063 caps->llm_buf_pg_sz = 0; 2064 2065 /* MR */ 2066 caps->mpt_ba_pg_sz = 0; 2067 caps->mpt_buf_pg_sz = 0; 2068 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2069 caps->pbl_buf_pg_sz = 0; 2070 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2071 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2072 HEM_TYPE_MTPT); 2073 2074 /* QP */ 2075 caps->qpc_ba_pg_sz = 0; 2076 caps->qpc_buf_pg_sz = 0; 2077 caps->qpc_timer_ba_pg_sz = 0; 2078 caps->qpc_timer_buf_pg_sz = 0; 2079 caps->sccc_ba_pg_sz = 0; 2080 caps->sccc_buf_pg_sz = 0; 2081 caps->mtt_ba_pg_sz = 0; 2082 caps->mtt_buf_pg_sz = 0; 2083 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2084 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2085 HEM_TYPE_QPC); 2086 2087 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2088 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2089 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2090 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2091 2092 /* CQ */ 2093 caps->cqc_ba_pg_sz = 0; 2094 caps->cqc_buf_pg_sz = 0; 2095 caps->cqc_timer_ba_pg_sz = 0; 2096 caps->cqc_timer_buf_pg_sz = 0; 2097 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2098 caps->cqe_buf_pg_sz = 0; 2099 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2100 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2101 HEM_TYPE_CQC); 2102 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2103 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2104 2105 /* SRQ */ 2106 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2107 caps->srqc_ba_pg_sz = 0; 2108 caps->srqc_buf_pg_sz = 0; 2109 caps->srqwqe_ba_pg_sz = 0; 2110 caps->srqwqe_buf_pg_sz = 0; 2111 caps->idx_ba_pg_sz = 0; 2112 caps->idx_buf_pg_sz = 0; 2113 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2114 caps->srqc_hop_num, caps->srqc_bt_num, 2115 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2116 HEM_TYPE_SRQC); 2117 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2118 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2119 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2120 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2121 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2122 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2123 } 2124 2125 /* GMV */ 2126 caps->gmv_ba_pg_sz = 0; 2127 caps->gmv_buf_pg_sz = 0; 2128 } 2129 2130 /* Apply all loaded caps before setting to hardware */ 2131 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2132 { 2133 struct hns_roce_caps *caps = &hr_dev->caps; 2134 struct hns_roce_v2_priv *priv = hr_dev->priv; 2135 2136 /* The following configurations don't need to be got from firmware. */ 2137 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2138 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2139 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2140 2141 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2142 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2143 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2144 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2145 2146 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2147 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2148 2149 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 2150 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2151 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2152 2153 if (!caps->num_comp_vectors) 2154 caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1, 2155 (u32)priv->handle->rinfo.num_vectors - 2); 2156 2157 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2158 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2159 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2160 2161 /* The following configurations will be overwritten */ 2162 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2163 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2164 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2165 2166 /* The following configurations are not got from firmware */ 2167 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2168 2169 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2170 caps->gid_table_len[0] = caps->gmv_bt_num * 2171 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2172 2173 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2174 caps->gmv_entry_sz); 2175 } else { 2176 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2177 2178 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2179 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2180 caps->gid_table_len[0] /= func_num; 2181 } 2182 2183 if (hr_dev->is_vf) { 2184 caps->default_aeq_arm_st = 0x3; 2185 caps->default_ceq_arm_st = 0x3; 2186 caps->default_ceq_max_cnt = 0x1; 2187 caps->default_ceq_period = 0x10; 2188 caps->default_aeq_max_cnt = 0x1; 2189 caps->default_aeq_period = 0x10; 2190 } 2191 2192 set_hem_page_size(hr_dev); 2193 } 2194 2195 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2196 { 2197 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2198 struct hns_roce_caps *caps = &hr_dev->caps; 2199 struct hns_roce_query_pf_caps_a *resp_a; 2200 struct hns_roce_query_pf_caps_b *resp_b; 2201 struct hns_roce_query_pf_caps_c *resp_c; 2202 struct hns_roce_query_pf_caps_d *resp_d; 2203 struct hns_roce_query_pf_caps_e *resp_e; 2204 int ctx_hop_num; 2205 int pbl_hop_num; 2206 int ret; 2207 int i; 2208 2209 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2210 hns_roce_cmq_setup_basic_desc(&desc[i], 2211 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2212 true); 2213 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2214 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2215 else 2216 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2217 } 2218 2219 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2220 if (ret) 2221 return ret; 2222 2223 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2224 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2225 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2226 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2227 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2228 2229 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2230 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2231 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2232 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2233 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2234 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 2235 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 2236 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 2237 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2238 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2239 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2240 caps->num_other_vectors = resp_a->num_other_vectors; 2241 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2242 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2243 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 2244 caps->cqe_sz = resp_a->cqe_sz; 2245 2246 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2247 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2248 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2249 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2250 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2251 caps->idx_entry_sz = resp_b->idx_entry_sz; 2252 caps->sccc_sz = resp_b->sccc_sz; 2253 caps->max_mtu = resp_b->max_mtu; 2254 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2255 caps->min_cqes = resp_b->min_cqes; 2256 caps->min_wqes = resp_b->min_wqes; 2257 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2258 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2259 caps->phy_num_uars = resp_b->phy_num_uars; 2260 ctx_hop_num = resp_b->ctx_hop_num; 2261 pbl_hop_num = resp_b->pbl_hop_num; 2262 2263 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 2264 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 2265 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 2266 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 2267 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 2268 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 2269 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2270 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2271 2272 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 2273 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 2274 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 2275 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 2276 V2_QUERY_PF_CAPS_C_MAX_GID_M, 2277 V2_QUERY_PF_CAPS_C_MAX_GID_S); 2278 2279 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 2280 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 2281 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 2282 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 2283 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 2284 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 2285 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 2286 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 2287 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 2288 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 2289 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 2290 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 2291 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2292 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2293 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 2294 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 2295 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 2296 caps->cong_type = roce_get_field(resp_d->wq_hop_num_max_srqs, 2297 V2_QUERY_PF_CAPS_D_CONG_TYPE_M, 2298 V2_QUERY_PF_CAPS_D_CONG_TYPE_S); 2299 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2300 2301 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 2302 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 2303 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 2304 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 2305 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 2306 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 2307 2308 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 2309 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 2310 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 2311 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2312 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 2313 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 2314 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2315 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 2316 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 2317 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 2318 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 2319 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 2320 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 2321 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 2322 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 2323 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 2324 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 2325 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 2326 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 2327 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 2328 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 2329 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2330 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 2331 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 2332 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2333 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 2334 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 2335 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 2336 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 2337 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 2338 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 2339 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 2340 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 2341 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 2342 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 2343 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 2344 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2345 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2346 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2347 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2348 2349 caps->qpc_hop_num = ctx_hop_num; 2350 caps->sccc_hop_num = ctx_hop_num; 2351 caps->srqc_hop_num = ctx_hop_num; 2352 caps->cqc_hop_num = ctx_hop_num; 2353 caps->mpt_hop_num = ctx_hop_num; 2354 caps->mtt_hop_num = pbl_hop_num; 2355 caps->cqe_hop_num = pbl_hop_num; 2356 caps->srqwqe_hop_num = pbl_hop_num; 2357 caps->idx_hop_num = pbl_hop_num; 2358 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2359 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 2360 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 2361 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2362 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 2363 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 2364 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2365 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 2366 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 2367 2368 return 0; 2369 } 2370 2371 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2372 { 2373 struct hns_roce_cmq_desc desc; 2374 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2375 2376 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2377 false); 2378 2379 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2380 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2381 2382 return hns_roce_cmq_send(hr_dev, &desc, 1); 2383 } 2384 2385 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2386 { 2387 struct hns_roce_caps *caps = &hr_dev->caps; 2388 int ret; 2389 2390 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 2391 return 0; 2392 2393 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2394 caps->qpc_sz); 2395 if (ret) { 2396 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2397 return ret; 2398 } 2399 2400 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2401 caps->sccc_sz); 2402 if (ret) 2403 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2404 2405 return ret; 2406 } 2407 2408 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2409 { 2410 struct device *dev = hr_dev->dev; 2411 int ret; 2412 2413 hr_dev->func_num = 1; 2414 2415 set_default_caps(hr_dev); 2416 2417 ret = hns_roce_query_vf_resource(hr_dev); 2418 if (ret) { 2419 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2420 return ret; 2421 } 2422 2423 apply_func_caps(hr_dev); 2424 2425 ret = hns_roce_v2_set_bt(hr_dev); 2426 if (ret) 2427 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2428 2429 return ret; 2430 } 2431 2432 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2433 { 2434 struct device *dev = hr_dev->dev; 2435 int ret; 2436 2437 ret = hns_roce_query_func_info(hr_dev); 2438 if (ret) { 2439 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2440 return ret; 2441 } 2442 2443 ret = hns_roce_config_global_param(hr_dev); 2444 if (ret) { 2445 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2446 return ret; 2447 } 2448 2449 ret = hns_roce_set_vf_switch_param(hr_dev); 2450 if (ret) { 2451 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2452 return ret; 2453 } 2454 2455 ret = hns_roce_query_pf_caps(hr_dev); 2456 if (ret) 2457 set_default_caps(hr_dev); 2458 2459 ret = hns_roce_query_pf_resource(hr_dev); 2460 if (ret) { 2461 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2462 return ret; 2463 } 2464 2465 apply_func_caps(hr_dev); 2466 2467 ret = hns_roce_alloc_vf_resource(hr_dev); 2468 if (ret) { 2469 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2470 return ret; 2471 } 2472 2473 ret = hns_roce_v2_set_bt(hr_dev); 2474 if (ret) { 2475 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2476 return ret; 2477 } 2478 2479 /* Configure the size of QPC, SCCC, etc. */ 2480 return hns_roce_config_entry_size(hr_dev); 2481 } 2482 2483 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2484 { 2485 struct device *dev = hr_dev->dev; 2486 int ret; 2487 2488 ret = hns_roce_cmq_query_hw_info(hr_dev); 2489 if (ret) { 2490 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2491 return ret; 2492 } 2493 2494 ret = hns_roce_query_fw_ver(hr_dev); 2495 if (ret) { 2496 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2497 return ret; 2498 } 2499 2500 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2501 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2502 2503 if (hr_dev->is_vf) 2504 return hns_roce_v2_vf_profile(hr_dev); 2505 else 2506 return hns_roce_v2_pf_profile(hr_dev); 2507 } 2508 2509 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2510 { 2511 u32 i, next_ptr, page_num; 2512 __le64 *entry = cfg_buf; 2513 dma_addr_t addr; 2514 u64 val; 2515 2516 page_num = data_buf->npages; 2517 for (i = 0; i < page_num; i++) { 2518 addr = hns_roce_buf_page(data_buf, i); 2519 if (i == (page_num - 1)) 2520 next_ptr = 0; 2521 else 2522 next_ptr = i + 1; 2523 2524 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2525 entry[i] = cpu_to_le64(val); 2526 } 2527 } 2528 2529 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2530 struct hns_roce_link_table *table) 2531 { 2532 struct hns_roce_cmq_desc desc[2]; 2533 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2534 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2535 struct hns_roce_buf *buf = table->buf; 2536 enum hns_roce_opcode_type opcode; 2537 dma_addr_t addr; 2538 2539 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2540 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2541 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2542 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2543 2544 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2545 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2546 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2547 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2548 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2549 2550 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2551 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2552 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2553 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2554 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2555 2556 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2557 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2558 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2559 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2560 2561 return hns_roce_cmq_send(hr_dev, desc, 2); 2562 } 2563 2564 static struct hns_roce_link_table * 2565 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2566 { 2567 struct hns_roce_v2_priv *priv = hr_dev->priv; 2568 struct hns_roce_link_table *link_tbl; 2569 u32 pg_shift, size, min_size; 2570 2571 link_tbl = &priv->ext_llm; 2572 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2573 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2574 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2575 2576 /* Alloc data table */ 2577 size = max(size, min_size); 2578 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2579 if (IS_ERR(link_tbl->buf)) 2580 return ERR_PTR(-ENOMEM); 2581 2582 /* Alloc config table */ 2583 size = link_tbl->buf->npages * sizeof(u64); 2584 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2585 &link_tbl->table.map, 2586 GFP_KERNEL); 2587 if (!link_tbl->table.buf) { 2588 hns_roce_buf_free(hr_dev, link_tbl->buf); 2589 return ERR_PTR(-ENOMEM); 2590 } 2591 2592 return link_tbl; 2593 } 2594 2595 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2596 struct hns_roce_link_table *tbl) 2597 { 2598 if (tbl->buf) { 2599 u32 size = tbl->buf->npages * sizeof(u64); 2600 2601 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2602 tbl->table.map); 2603 } 2604 2605 hns_roce_buf_free(hr_dev, tbl->buf); 2606 } 2607 2608 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2609 { 2610 struct hns_roce_link_table *link_tbl; 2611 int ret; 2612 2613 link_tbl = alloc_link_table_buf(hr_dev); 2614 if (IS_ERR(link_tbl)) 2615 return -ENOMEM; 2616 2617 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2618 ret = -EINVAL; 2619 goto err_alloc; 2620 } 2621 2622 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2623 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2624 if (ret) 2625 goto err_alloc; 2626 2627 return 0; 2628 2629 err_alloc: 2630 free_link_table_buf(hr_dev, link_tbl); 2631 return ret; 2632 } 2633 2634 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2635 { 2636 struct hns_roce_v2_priv *priv = hr_dev->priv; 2637 2638 free_link_table_buf(hr_dev, &priv->ext_llm); 2639 } 2640 2641 static void free_dip_list(struct hns_roce_dev *hr_dev) 2642 { 2643 struct hns_roce_dip *hr_dip; 2644 struct hns_roce_dip *tmp; 2645 unsigned long flags; 2646 2647 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2648 2649 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2650 list_del(&hr_dip->node); 2651 kfree(hr_dip); 2652 } 2653 2654 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2655 } 2656 2657 static int get_hem_table(struct hns_roce_dev *hr_dev) 2658 { 2659 unsigned int qpc_count; 2660 unsigned int cqc_count; 2661 unsigned int gmv_count; 2662 int ret; 2663 int i; 2664 2665 /* Alloc memory for source address table buffer space chunk */ 2666 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2667 gmv_count++) { 2668 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2669 if (ret) 2670 goto err_gmv_failed; 2671 } 2672 2673 if (hr_dev->is_vf) 2674 return 0; 2675 2676 /* Alloc memory for QPC Timer buffer space chunk */ 2677 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2678 qpc_count++) { 2679 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2680 qpc_count); 2681 if (ret) { 2682 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2683 goto err_qpc_timer_failed; 2684 } 2685 } 2686 2687 /* Alloc memory for CQC Timer buffer space chunk */ 2688 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2689 cqc_count++) { 2690 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2691 cqc_count); 2692 if (ret) { 2693 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2694 goto err_cqc_timer_failed; 2695 } 2696 } 2697 2698 return 0; 2699 2700 err_cqc_timer_failed: 2701 for (i = 0; i < cqc_count; i++) 2702 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2703 2704 err_qpc_timer_failed: 2705 for (i = 0; i < qpc_count; i++) 2706 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2707 2708 err_gmv_failed: 2709 for (i = 0; i < gmv_count; i++) 2710 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2711 2712 return ret; 2713 } 2714 2715 static void put_hem_table(struct hns_roce_dev *hr_dev) 2716 { 2717 int i; 2718 2719 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2720 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2721 2722 if (hr_dev->is_vf) 2723 return; 2724 2725 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2726 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2727 2728 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2729 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2730 } 2731 2732 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2733 { 2734 int ret; 2735 2736 /* The hns ROCEE requires the extdb info to be cleared before using */ 2737 ret = hns_roce_clear_extdb_list_info(hr_dev); 2738 if (ret) 2739 return ret; 2740 2741 ret = get_hem_table(hr_dev); 2742 if (ret) 2743 return ret; 2744 2745 if (hr_dev->is_vf) 2746 return 0; 2747 2748 ret = hns_roce_init_link_table(hr_dev); 2749 if (ret) { 2750 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2751 goto err_llm_init_failed; 2752 } 2753 2754 return 0; 2755 2756 err_llm_init_failed: 2757 put_hem_table(hr_dev); 2758 2759 return ret; 2760 } 2761 2762 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2763 { 2764 hns_roce_function_clear(hr_dev); 2765 2766 if (!hr_dev->is_vf) 2767 hns_roce_free_link_table(hr_dev); 2768 2769 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2770 free_dip_list(hr_dev); 2771 } 2772 2773 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2774 u64 out_param, u32 in_modifier, u8 op_modifier, 2775 u16 op, u16 token, int event) 2776 { 2777 struct hns_roce_cmq_desc desc; 2778 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2779 2780 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2781 2782 mb->in_param_l = cpu_to_le32(in_param); 2783 mb->in_param_h = cpu_to_le32(in_param >> 32); 2784 mb->out_param_l = cpu_to_le32(out_param); 2785 mb->out_param_h = cpu_to_le32(out_param >> 32); 2786 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2787 mb->token_event_en = cpu_to_le32(event << 16 | token); 2788 2789 return hns_roce_cmq_send(hr_dev, &desc, 1); 2790 } 2791 2792 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2793 u8 *complete_status) 2794 { 2795 struct hns_roce_mbox_status *mb_st; 2796 struct hns_roce_cmq_desc desc; 2797 unsigned long end; 2798 int ret = -EBUSY; 2799 u32 status; 2800 bool busy; 2801 2802 mb_st = (struct hns_roce_mbox_status *)desc.data; 2803 end = msecs_to_jiffies(timeout) + jiffies; 2804 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2805 status = 0; 2806 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2807 true); 2808 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2809 if (!ret) { 2810 status = le32_to_cpu(mb_st->mb_status_hw_run); 2811 /* No pending message exists in ROCEE mbox. */ 2812 if (!(status & MB_ST_HW_RUN_M)) 2813 break; 2814 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2815 break; 2816 } 2817 2818 if (time_after(jiffies, end)) { 2819 dev_err_ratelimited(hr_dev->dev, 2820 "failed to wait mbox status 0x%x\n", 2821 status); 2822 return -ETIMEDOUT; 2823 } 2824 2825 cond_resched(); 2826 ret = -EBUSY; 2827 } 2828 2829 if (!ret) { 2830 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2831 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2832 /* Ignore all errors if the mbox is unavailable. */ 2833 ret = 0; 2834 *complete_status = MB_ST_COMPLETE_M; 2835 } 2836 2837 return ret; 2838 } 2839 2840 static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2841 u64 out_param, u32 in_modifier, u8 op_modifier, 2842 u16 op, u16 token, int event) 2843 { 2844 u8 status = 0; 2845 int ret; 2846 2847 /* Waiting for the mbox to be idle */ 2848 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 2849 &status); 2850 if (unlikely(ret)) { 2851 dev_err_ratelimited(hr_dev->dev, 2852 "failed to check post mbox status = 0x%x, ret = %d.\n", 2853 status, ret); 2854 return ret; 2855 } 2856 2857 /* Post new message to mbox */ 2858 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2859 op_modifier, op, token, event); 2860 if (ret) 2861 dev_err_ratelimited(hr_dev->dev, 2862 "failed to post mailbox, ret = %d.\n", ret); 2863 2864 return ret; 2865 } 2866 2867 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout) 2868 { 2869 u8 status = 0; 2870 int ret; 2871 2872 ret = v2_wait_mbox_complete(hr_dev, timeout, &status); 2873 if (!ret) { 2874 if (status != MB_ST_COMPLETE_SUCC) 2875 return -EBUSY; 2876 } else { 2877 dev_err_ratelimited(hr_dev->dev, 2878 "failed to check mbox status = 0x%x, ret = %d.\n", 2879 status, ret); 2880 } 2881 2882 return ret; 2883 } 2884 2885 static void copy_gid(void *dest, const union ib_gid *gid) 2886 { 2887 #define GID_SIZE 4 2888 const union ib_gid *src = gid; 2889 __le32 (*p)[GID_SIZE] = dest; 2890 int i; 2891 2892 if (!gid) 2893 src = &zgid; 2894 2895 for (i = 0; i < GID_SIZE; i++) 2896 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 2897 } 2898 2899 static int config_sgid_table(struct hns_roce_dev *hr_dev, 2900 int gid_index, const union ib_gid *gid, 2901 enum hns_roce_sgid_type sgid_type) 2902 { 2903 struct hns_roce_cmq_desc desc; 2904 struct hns_roce_cfg_sgid_tb *sgid_tb = 2905 (struct hns_roce_cfg_sgid_tb *)desc.data; 2906 2907 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2908 2909 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2910 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2911 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2912 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2913 2914 copy_gid(&sgid_tb->vf_sgid_l, gid); 2915 2916 return hns_roce_cmq_send(hr_dev, &desc, 1); 2917 } 2918 2919 static int config_gmv_table(struct hns_roce_dev *hr_dev, 2920 int gid_index, const union ib_gid *gid, 2921 enum hns_roce_sgid_type sgid_type, 2922 const struct ib_gid_attr *attr) 2923 { 2924 struct hns_roce_cmq_desc desc[2]; 2925 struct hns_roce_cfg_gmv_tb_a *tb_a = 2926 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 2927 struct hns_roce_cfg_gmv_tb_b *tb_b = 2928 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 2929 2930 u16 vlan_id = VLAN_CFI_MASK; 2931 u8 mac[ETH_ALEN] = {}; 2932 int ret; 2933 2934 if (gid) { 2935 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 2936 if (ret) 2937 return ret; 2938 } 2939 2940 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2941 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2942 2943 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2944 2945 copy_gid(&tb_a->vf_sgid_l, gid); 2946 2947 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_SGID_TYPE_M, 2948 CFG_GMV_TB_VF_SGID_TYPE_S, sgid_type); 2949 roce_set_bit(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_EN_S, 2950 vlan_id < VLAN_CFI_MASK); 2951 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_ID_M, 2952 CFG_GMV_TB_VF_VLAN_ID_S, vlan_id); 2953 2954 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 2955 roce_set_field(tb_b->vf_smac_h, CFG_GMV_TB_SMAC_H_M, 2956 CFG_GMV_TB_SMAC_H_S, *(u16 *)&mac[4]); 2957 2958 roce_set_field(tb_b->table_idx_rsv, CFG_GMV_TB_SGID_IDX_M, 2959 CFG_GMV_TB_SGID_IDX_S, gid_index); 2960 2961 return hns_roce_cmq_send(hr_dev, desc, 2); 2962 } 2963 2964 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u32 port, 2965 int gid_index, const union ib_gid *gid, 2966 const struct ib_gid_attr *attr) 2967 { 2968 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2969 int ret; 2970 2971 if (gid) { 2972 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2973 if (ipv6_addr_v4mapped((void *)gid)) 2974 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2975 else 2976 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2977 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 2978 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2979 } 2980 } 2981 2982 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 2983 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 2984 else 2985 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2986 2987 if (ret) 2988 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 2989 ret); 2990 2991 return ret; 2992 } 2993 2994 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2995 u8 *addr) 2996 { 2997 struct hns_roce_cmq_desc desc; 2998 struct hns_roce_cfg_smac_tb *smac_tb = 2999 (struct hns_roce_cfg_smac_tb *)desc.data; 3000 u16 reg_smac_h; 3001 u32 reg_smac_l; 3002 3003 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3004 3005 reg_smac_l = *(u32 *)(&addr[0]); 3006 reg_smac_h = *(u16 *)(&addr[4]); 3007 3008 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 3009 CFG_SMAC_TB_IDX_S, phy_port); 3010 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 3011 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 3012 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3013 3014 return hns_roce_cmq_send(hr_dev, &desc, 1); 3015 } 3016 3017 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3018 struct hns_roce_v2_mpt_entry *mpt_entry, 3019 struct hns_roce_mr *mr) 3020 { 3021 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3022 struct ib_device *ibdev = &hr_dev->ib_dev; 3023 dma_addr_t pbl_ba; 3024 int i, count; 3025 3026 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3027 ARRAY_SIZE(pages), &pbl_ba); 3028 if (count < 1) { 3029 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3030 count); 3031 return -ENOBUFS; 3032 } 3033 3034 /* Aligned to the hardware address access unit */ 3035 for (i = 0; i < count; i++) 3036 pages[i] >>= 6; 3037 3038 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3039 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3040 roce_set_field(mpt_entry->byte_48_mode_ba, 3041 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 3042 upper_32_bits(pbl_ba >> 3)); 3043 3044 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3045 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 3046 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 3047 3048 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3049 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 3050 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 3051 roce_set_field(mpt_entry->byte_64_buf_pa1, 3052 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3053 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3054 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3055 3056 return 0; 3057 } 3058 3059 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3060 void *mb_buf, struct hns_roce_mr *mr, 3061 unsigned long mtpt_idx) 3062 { 3063 struct hns_roce_v2_mpt_entry *mpt_entry; 3064 int ret; 3065 3066 mpt_entry = mb_buf; 3067 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3068 3069 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3070 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3071 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3072 3073 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3074 mr->access & IB_ACCESS_MW_BIND); 3075 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3076 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3077 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3078 mr->access & IB_ACCESS_REMOTE_READ); 3079 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3080 mr->access & IB_ACCESS_REMOTE_WRITE); 3081 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3082 mr->access & IB_ACCESS_LOCAL_WRITE); 3083 3084 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3085 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3086 mpt_entry->lkey = cpu_to_le32(mr->key); 3087 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3088 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3089 3090 if (mr->type != MR_TYPE_MR) 3091 hr_reg_enable(mpt_entry, MPT_PA); 3092 3093 if (mr->type == MR_TYPE_DMA) 3094 return 0; 3095 3096 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3097 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3098 3099 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3100 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3101 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3102 3103 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3104 3105 return ret; 3106 } 3107 3108 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3109 struct hns_roce_mr *mr, int flags, 3110 void *mb_buf) 3111 { 3112 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3113 u32 mr_access_flags = mr->access; 3114 int ret = 0; 3115 3116 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3117 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 3118 3119 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3120 V2_MPT_BYTE_4_PD_S, mr->pd); 3121 3122 if (flags & IB_MR_REREG_ACCESS) { 3123 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3124 V2_MPT_BYTE_8_BIND_EN_S, 3125 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3126 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3127 V2_MPT_BYTE_8_ATOMIC_EN_S, 3128 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3129 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 3130 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3131 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 3132 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3133 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 3134 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3135 } 3136 3137 if (flags & IB_MR_REREG_TRANS) { 3138 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3139 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3140 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3141 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3142 3143 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3144 } 3145 3146 return ret; 3147 } 3148 3149 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3150 void *mb_buf, struct hns_roce_mr *mr) 3151 { 3152 struct ib_device *ibdev = &hr_dev->ib_dev; 3153 struct hns_roce_v2_mpt_entry *mpt_entry; 3154 dma_addr_t pbl_ba = 0; 3155 3156 mpt_entry = mb_buf; 3157 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3158 3159 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3160 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3161 return -ENOBUFS; 3162 } 3163 3164 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3165 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3166 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3167 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 3168 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3169 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3170 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3171 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3172 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3173 V2_MPT_BYTE_4_PD_S, mr->pd); 3174 3175 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 3176 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3177 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3178 3179 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 3180 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3181 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 3182 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3183 3184 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3185 3186 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3187 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 3188 V2_MPT_BYTE_48_PBL_BA_H_S, 3189 upper_32_bits(pbl_ba >> 3)); 3190 3191 roce_set_field(mpt_entry->byte_64_buf_pa1, 3192 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3193 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3194 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3195 3196 return 0; 3197 } 3198 3199 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3200 { 3201 struct hns_roce_v2_mpt_entry *mpt_entry; 3202 3203 mpt_entry = mb_buf; 3204 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3205 3206 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3207 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3208 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3209 V2_MPT_BYTE_4_PD_S, mw->pdn); 3210 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3211 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 3212 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3213 mw->pbl_hop_num); 3214 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3215 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3216 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3217 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3218 3219 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3220 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3221 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1); 3222 3223 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3224 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 3225 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3226 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 3227 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3228 3229 roce_set_field(mpt_entry->byte_64_buf_pa1, 3230 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3231 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3232 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3233 3234 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3235 3236 return 0; 3237 } 3238 3239 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3240 { 3241 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3242 } 3243 3244 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3245 { 3246 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3247 3248 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3249 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3250 NULL; 3251 } 3252 3253 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3254 struct hns_roce_cq *hr_cq) 3255 { 3256 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3257 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3258 } else { 3259 struct hns_roce_v2_db cq_db = {}; 3260 3261 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3262 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3263 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3264 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3265 3266 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3267 } 3268 } 3269 3270 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3271 struct hns_roce_srq *srq) 3272 { 3273 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3274 struct hns_roce_v2_cqe *cqe, *dest; 3275 u32 prod_index; 3276 int nfreed = 0; 3277 int wqe_index; 3278 u8 owner_bit; 3279 3280 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3281 ++prod_index) { 3282 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3283 break; 3284 } 3285 3286 /* 3287 * Now backwards through the CQ, removing CQ entries 3288 * that match our QP by overwriting them with next entries. 3289 */ 3290 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3291 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3292 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3293 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3294 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3295 hns_roce_free_srq_wqe(srq, wqe_index); 3296 } 3297 ++nfreed; 3298 } else if (nfreed) { 3299 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3300 hr_cq->ib_cq.cqe); 3301 owner_bit = hr_reg_read(dest, CQE_OWNER); 3302 memcpy(dest, cqe, sizeof(*cqe)); 3303 hr_reg_write(dest, CQE_OWNER, owner_bit); 3304 } 3305 } 3306 3307 if (nfreed) { 3308 hr_cq->cons_index += nfreed; 3309 update_cq_db(hr_dev, hr_cq); 3310 } 3311 } 3312 3313 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3314 struct hns_roce_srq *srq) 3315 { 3316 spin_lock_irq(&hr_cq->lock); 3317 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3318 spin_unlock_irq(&hr_cq->lock); 3319 } 3320 3321 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3322 struct hns_roce_cq *hr_cq, void *mb_buf, 3323 u64 *mtts, dma_addr_t dma_handle) 3324 { 3325 struct hns_roce_v2_cq_context *cq_context; 3326 3327 cq_context = mb_buf; 3328 memset(cq_context, 0, sizeof(*cq_context)); 3329 3330 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3331 hr_reg_write(cq_context, CQC_ARM_ST, REG_NXT_CEQE); 3332 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3333 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3334 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3335 3336 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3337 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3338 3339 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3340 hr_reg_enable(cq_context, CQC_STASH); 3341 3342 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3343 to_hr_hw_page_addr(mtts[0])); 3344 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3345 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3346 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3347 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3348 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3349 to_hr_hw_page_addr(mtts[1])); 3350 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3351 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3352 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3353 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3354 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3355 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3356 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3357 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3358 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3359 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3360 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3361 ((u32)hr_cq->db.dma) >> 1); 3362 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3363 hr_cq->db.dma >> 32); 3364 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3365 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3366 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3367 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3368 } 3369 3370 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3371 enum ib_cq_notify_flags flags) 3372 { 3373 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3374 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3375 struct hns_roce_v2_db cq_db = {}; 3376 u32 notify_flag; 3377 3378 /* 3379 * flags = 0, then notify_flag : next 3380 * flags = 1, then notify flag : solocited 3381 */ 3382 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3383 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3384 3385 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3386 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3387 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3388 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3389 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3390 3391 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3392 3393 return 0; 3394 } 3395 3396 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3397 struct hns_roce_qp *qp, 3398 struct ib_wc *wc) 3399 { 3400 struct hns_roce_rinl_sge *sge_list; 3401 u32 wr_num, wr_cnt, sge_num; 3402 u32 sge_cnt, data_len, size; 3403 void *wqe_buf; 3404 3405 wr_num = hr_reg_read(cqe, CQE_WQE_IDX); 3406 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1); 3407 3408 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3409 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3410 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt); 3411 data_len = wc->byte_len; 3412 3413 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3414 size = min(sge_list[sge_cnt].len, data_len); 3415 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3416 3417 data_len -= size; 3418 wqe_buf += size; 3419 } 3420 3421 if (unlikely(data_len)) { 3422 wc->status = IB_WC_LOC_LEN_ERR; 3423 return -EAGAIN; 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3430 int num_entries, struct ib_wc *wc) 3431 { 3432 unsigned int left; 3433 int npolled = 0; 3434 3435 left = wq->head - wq->tail; 3436 if (left == 0) 3437 return 0; 3438 3439 left = min_t(unsigned int, (unsigned int)num_entries, left); 3440 while (npolled < left) { 3441 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3442 wc->status = IB_WC_WR_FLUSH_ERR; 3443 wc->vendor_err = 0; 3444 wc->qp = &hr_qp->ibqp; 3445 3446 wq->tail++; 3447 wc++; 3448 npolled++; 3449 } 3450 3451 return npolled; 3452 } 3453 3454 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3455 struct ib_wc *wc) 3456 { 3457 struct hns_roce_qp *hr_qp; 3458 int npolled = 0; 3459 3460 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3461 npolled += sw_comp(hr_qp, &hr_qp->sq, 3462 num_entries - npolled, wc + npolled); 3463 if (npolled >= num_entries) 3464 goto out; 3465 } 3466 3467 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3468 npolled += sw_comp(hr_qp, &hr_qp->rq, 3469 num_entries - npolled, wc + npolled); 3470 if (npolled >= num_entries) 3471 goto out; 3472 } 3473 3474 out: 3475 return npolled; 3476 } 3477 3478 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3479 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3480 struct ib_wc *wc) 3481 { 3482 static const struct { 3483 u32 cqe_status; 3484 enum ib_wc_status wc_status; 3485 } map[] = { 3486 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3487 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3488 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3489 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3490 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3491 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3492 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3493 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3494 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3495 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3496 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3497 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3498 IB_WC_RETRY_EXC_ERR }, 3499 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3500 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3501 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3502 }; 3503 3504 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3505 int i; 3506 3507 wc->status = IB_WC_GENERAL_ERR; 3508 for (i = 0; i < ARRAY_SIZE(map); i++) 3509 if (cqe_status == map[i].cqe_status) { 3510 wc->status = map[i].wc_status; 3511 break; 3512 } 3513 3514 if (likely(wc->status == IB_WC_SUCCESS || 3515 wc->status == IB_WC_WR_FLUSH_ERR)) 3516 return; 3517 3518 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3519 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3520 cq->cqe_size, false); 3521 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3522 3523 /* 3524 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3525 * the standard protocol, the driver must ignore it and needn't to set 3526 * the QP to an error state. 3527 */ 3528 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3529 return; 3530 3531 flush_cqe(hr_dev, qp); 3532 } 3533 3534 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3535 struct hns_roce_qp **cur_qp) 3536 { 3537 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3538 struct hns_roce_qp *hr_qp = *cur_qp; 3539 u32 qpn; 3540 3541 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3542 3543 if (!hr_qp || qpn != hr_qp->qpn) { 3544 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3545 if (unlikely(!hr_qp)) { 3546 ibdev_err(&hr_dev->ib_dev, 3547 "CQ %06lx with entry for unknown QPN %06x\n", 3548 hr_cq->cqn, qpn); 3549 return -EINVAL; 3550 } 3551 *cur_qp = hr_qp; 3552 } 3553 3554 return 0; 3555 } 3556 3557 /* 3558 * mapped-value = 1 + real-value 3559 * The ib wc opcode's real value is start from 0, In order to distinguish 3560 * between initialized and uninitialized map values, we plus 1 to the actual 3561 * value when defining the mapping, so that the validity can be identified by 3562 * checking whether the mapped value is greater than 0. 3563 */ 3564 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3565 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3566 3567 static const u32 wc_send_op_map[] = { 3568 HR_WC_OP_MAP(SEND, SEND), 3569 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3570 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3571 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3572 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3573 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3574 HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV), 3575 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3576 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3577 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3578 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3579 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3580 HR_WC_OP_MAP(BIND_MW, REG_MR), 3581 }; 3582 3583 static int to_ib_wc_send_op(u32 hr_opcode) 3584 { 3585 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3586 return -EINVAL; 3587 3588 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3589 -EINVAL; 3590 } 3591 3592 static const u32 wc_recv_op_map[] = { 3593 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3594 HR_WC_OP_MAP(SEND, RECV), 3595 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3596 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3597 }; 3598 3599 static int to_ib_wc_recv_op(u32 hr_opcode) 3600 { 3601 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3602 return -EINVAL; 3603 3604 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3605 -EINVAL; 3606 } 3607 3608 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3609 { 3610 u32 hr_opcode; 3611 int ib_opcode; 3612 3613 wc->wc_flags = 0; 3614 3615 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3616 switch (hr_opcode) { 3617 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3618 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3619 break; 3620 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3621 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3622 wc->wc_flags |= IB_WC_WITH_IMM; 3623 break; 3624 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3625 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3626 break; 3627 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3628 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3629 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3630 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3631 wc->byte_len = 8; 3632 break; 3633 default: 3634 break; 3635 } 3636 3637 ib_opcode = to_ib_wc_send_op(hr_opcode); 3638 if (ib_opcode < 0) 3639 wc->status = IB_WC_GENERAL_ERR; 3640 else 3641 wc->opcode = ib_opcode; 3642 } 3643 3644 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode, 3645 struct hns_roce_v2_cqe *cqe) 3646 { 3647 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI && 3648 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND || 3649 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3650 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3651 hr_reg_read(cqe, CQE_RQ_INLINE); 3652 } 3653 3654 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3655 { 3656 struct hns_roce_qp *qp = to_hr_qp(wc->qp); 3657 u32 hr_opcode; 3658 int ib_opcode; 3659 int ret; 3660 3661 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3662 3663 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3664 switch (hr_opcode) { 3665 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3666 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3667 wc->wc_flags = IB_WC_WITH_IMM; 3668 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3669 break; 3670 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3671 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3672 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3673 break; 3674 default: 3675 wc->wc_flags = 0; 3676 } 3677 3678 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3679 if (ib_opcode < 0) 3680 wc->status = IB_WC_GENERAL_ERR; 3681 else 3682 wc->opcode = ib_opcode; 3683 3684 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) { 3685 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc); 3686 if (unlikely(ret)) 3687 return ret; 3688 } 3689 3690 wc->sl = hr_reg_read(cqe, CQE_SL); 3691 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3692 wc->slid = 0; 3693 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3694 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3695 wc->pkey_index = 0; 3696 3697 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3698 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3699 wc->wc_flags |= IB_WC_WITH_VLAN; 3700 } else { 3701 wc->vlan_id = 0xffff; 3702 } 3703 3704 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3705 3706 return 0; 3707 } 3708 3709 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3710 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3711 { 3712 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3713 struct hns_roce_qp *qp = *cur_qp; 3714 struct hns_roce_srq *srq = NULL; 3715 struct hns_roce_v2_cqe *cqe; 3716 struct hns_roce_wq *wq; 3717 int is_send; 3718 u16 wqe_idx; 3719 int ret; 3720 3721 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3722 if (!cqe) 3723 return -EAGAIN; 3724 3725 ++hr_cq->cons_index; 3726 /* Memory barrier */ 3727 rmb(); 3728 3729 ret = get_cur_qp(hr_cq, cqe, &qp); 3730 if (ret) 3731 return ret; 3732 3733 wc->qp = &qp->ibqp; 3734 wc->vendor_err = 0; 3735 3736 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3737 3738 is_send = !hr_reg_read(cqe, CQE_S_R); 3739 if (is_send) { 3740 wq = &qp->sq; 3741 3742 /* If sg_signal_bit is set, tail pointer will be updated to 3743 * the WQE corresponding to the current CQE. 3744 */ 3745 if (qp->sq_signal_bits) 3746 wq->tail += (wqe_idx - (u16)wq->tail) & 3747 (wq->wqe_cnt - 1); 3748 3749 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3750 ++wq->tail; 3751 3752 fill_send_wc(wc, cqe); 3753 } else { 3754 if (qp->ibqp.srq) { 3755 srq = to_hr_srq(qp->ibqp.srq); 3756 wc->wr_id = srq->wrid[wqe_idx]; 3757 hns_roce_free_srq_wqe(srq, wqe_idx); 3758 } else { 3759 wq = &qp->rq; 3760 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3761 ++wq->tail; 3762 } 3763 3764 ret = fill_recv_wc(wc, cqe); 3765 } 3766 3767 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3768 if (unlikely(wc->status != IB_WC_SUCCESS)) 3769 return 0; 3770 3771 return ret; 3772 } 3773 3774 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3775 struct ib_wc *wc) 3776 { 3777 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3778 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3779 struct hns_roce_qp *cur_qp = NULL; 3780 unsigned long flags; 3781 int npolled; 3782 3783 spin_lock_irqsave(&hr_cq->lock, flags); 3784 3785 /* 3786 * When the device starts to reset, the state is RST_DOWN. At this time, 3787 * there may still be some valid CQEs in the hardware that are not 3788 * polled. Therefore, it is not allowed to switch to the software mode 3789 * immediately. When the state changes to UNINIT, CQE no longer exists 3790 * in the hardware, and then switch to software mode. 3791 */ 3792 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3793 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3794 goto out; 3795 } 3796 3797 for (npolled = 0; npolled < num_entries; ++npolled) { 3798 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3799 break; 3800 } 3801 3802 if (npolled) 3803 update_cq_db(hr_dev, hr_cq); 3804 3805 out: 3806 spin_unlock_irqrestore(&hr_cq->lock, flags); 3807 3808 return npolled; 3809 } 3810 3811 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3812 int step_idx, u16 *mbox_op) 3813 { 3814 u16 op; 3815 3816 switch (type) { 3817 case HEM_TYPE_QPC: 3818 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3819 break; 3820 case HEM_TYPE_MTPT: 3821 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3822 break; 3823 case HEM_TYPE_CQC: 3824 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3825 break; 3826 case HEM_TYPE_SRQC: 3827 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3828 break; 3829 case HEM_TYPE_SCCC: 3830 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3831 break; 3832 case HEM_TYPE_QPC_TIMER: 3833 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3834 break; 3835 case HEM_TYPE_CQC_TIMER: 3836 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3837 break; 3838 default: 3839 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 3840 return -EINVAL; 3841 } 3842 3843 *mbox_op = op + step_idx; 3844 3845 return 0; 3846 } 3847 3848 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 3849 dma_addr_t base_addr) 3850 { 3851 struct hns_roce_cmq_desc desc; 3852 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 3853 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 3854 u64 addr = to_hr_hw_page_addr(base_addr); 3855 3856 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 3857 3858 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 3859 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 3860 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 3861 3862 return hns_roce_cmq_send(hr_dev, &desc, 1); 3863 } 3864 3865 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 3866 dma_addr_t base_addr, u32 hem_type, int step_idx) 3867 { 3868 int ret; 3869 u16 op; 3870 3871 if (unlikely(hem_type == HEM_TYPE_GMV)) 3872 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 3873 3874 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 3875 return 0; 3876 3877 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op); 3878 if (ret < 0) 3879 return ret; 3880 3881 return config_hem_ba_to_hw(hr_dev, obj, base_addr, op); 3882 } 3883 3884 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3885 struct hns_roce_hem_table *table, int obj, 3886 int step_idx) 3887 { 3888 struct hns_roce_hem_iter iter; 3889 struct hns_roce_hem_mhop mhop; 3890 struct hns_roce_hem *hem; 3891 unsigned long mhop_obj = obj; 3892 int i, j, k; 3893 int ret = 0; 3894 u64 hem_idx = 0; 3895 u64 l1_idx = 0; 3896 u64 bt_ba = 0; 3897 u32 chunk_ba_num; 3898 u32 hop_num; 3899 3900 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3901 return 0; 3902 3903 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3904 i = mhop.l0_idx; 3905 j = mhop.l1_idx; 3906 k = mhop.l2_idx; 3907 hop_num = mhop.hop_num; 3908 chunk_ba_num = mhop.bt_chunk_size / 8; 3909 3910 if (hop_num == 2) { 3911 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3912 k; 3913 l1_idx = i * chunk_ba_num + j; 3914 } else if (hop_num == 1) { 3915 hem_idx = i * chunk_ba_num + j; 3916 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3917 hem_idx = i; 3918 } 3919 3920 if (table->type == HEM_TYPE_SCCC) 3921 obj = mhop.l0_idx; 3922 3923 if (check_whether_last_step(hop_num, step_idx)) { 3924 hem = table->hem[hem_idx]; 3925 for (hns_roce_hem_first(hem, &iter); 3926 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3927 bt_ba = hns_roce_hem_addr(&iter); 3928 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3929 step_idx); 3930 } 3931 } else { 3932 if (step_idx == 0) 3933 bt_ba = table->bt_l0_dma_addr[i]; 3934 else if (step_idx == 1 && hop_num == 2) 3935 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3936 3937 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3938 } 3939 3940 return ret; 3941 } 3942 3943 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3944 struct hns_roce_hem_table *table, int obj, 3945 int step_idx) 3946 { 3947 struct device *dev = hr_dev->dev; 3948 struct hns_roce_cmd_mailbox *mailbox; 3949 int ret; 3950 u16 op = 0xff; 3951 3952 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3953 return 0; 3954 3955 switch (table->type) { 3956 case HEM_TYPE_QPC: 3957 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3958 break; 3959 case HEM_TYPE_MTPT: 3960 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3961 break; 3962 case HEM_TYPE_CQC: 3963 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3964 break; 3965 case HEM_TYPE_SRQC: 3966 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3967 break; 3968 case HEM_TYPE_SCCC: 3969 case HEM_TYPE_QPC_TIMER: 3970 case HEM_TYPE_CQC_TIMER: 3971 case HEM_TYPE_GMV: 3972 return 0; 3973 default: 3974 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 3975 table->type); 3976 return 0; 3977 } 3978 3979 op += step_idx; 3980 3981 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3982 if (IS_ERR(mailbox)) 3983 return PTR_ERR(mailbox); 3984 3985 /* configure the tag and op */ 3986 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3987 HNS_ROCE_CMD_TIMEOUT_MSECS); 3988 3989 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3990 return ret; 3991 } 3992 3993 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3994 struct hns_roce_v2_qp_context *context, 3995 struct hns_roce_v2_qp_context *qpc_mask, 3996 struct hns_roce_qp *hr_qp) 3997 { 3998 struct hns_roce_cmd_mailbox *mailbox; 3999 int qpc_size; 4000 int ret; 4001 4002 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4003 if (IS_ERR(mailbox)) 4004 return PTR_ERR(mailbox); 4005 4006 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4007 qpc_size = hr_dev->caps.qpc_sz; 4008 memcpy(mailbox->buf, context, qpc_size); 4009 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4010 4011 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 4012 HNS_ROCE_CMD_MODIFY_QPC, 4013 HNS_ROCE_CMD_TIMEOUT_MSECS); 4014 4015 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4016 4017 return ret; 4018 } 4019 4020 static void set_access_flags(struct hns_roce_qp *hr_qp, 4021 struct hns_roce_v2_qp_context *context, 4022 struct hns_roce_v2_qp_context *qpc_mask, 4023 const struct ib_qp_attr *attr, int attr_mask) 4024 { 4025 u8 dest_rd_atomic; 4026 u32 access_flags; 4027 4028 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4029 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4030 4031 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4032 attr->qp_access_flags : hr_qp->atomic_rd_en; 4033 4034 if (!dest_rd_atomic) 4035 access_flags &= IB_ACCESS_REMOTE_WRITE; 4036 4037 hr_reg_write_bool(context, QPC_RRE, 4038 access_flags & IB_ACCESS_REMOTE_READ); 4039 hr_reg_clear(qpc_mask, QPC_RRE); 4040 4041 hr_reg_write_bool(context, QPC_RWE, 4042 access_flags & IB_ACCESS_REMOTE_WRITE); 4043 hr_reg_clear(qpc_mask, QPC_RWE); 4044 4045 hr_reg_write_bool(context, QPC_ATE, 4046 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4047 hr_reg_clear(qpc_mask, QPC_ATE); 4048 hr_reg_write_bool(context, QPC_EXT_ATE, 4049 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4050 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4051 } 4052 4053 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4054 struct hns_roce_v2_qp_context *context, 4055 struct hns_roce_v2_qp_context *qpc_mask) 4056 { 4057 hr_reg_write(context, QPC_SGE_SHIFT, 4058 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4059 hr_qp->sge.sge_shift)); 4060 4061 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4062 4063 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4064 } 4065 4066 static inline int get_cqn(struct ib_cq *ib_cq) 4067 { 4068 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4069 } 4070 4071 static inline int get_pdn(struct ib_pd *ib_pd) 4072 { 4073 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4074 } 4075 4076 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4077 const struct ib_qp_attr *attr, 4078 int attr_mask, 4079 struct hns_roce_v2_qp_context *context, 4080 struct hns_roce_v2_qp_context *qpc_mask) 4081 { 4082 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4083 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4084 4085 /* 4086 * In v2 engine, software pass context and context mask to hardware 4087 * when modifying qp. If software need modify some fields in context, 4088 * we should set all bits of the relevant fields in context mask to 4089 * 0 at the same time, else set them to 0x1. 4090 */ 4091 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4092 4093 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4094 4095 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4096 4097 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4098 4099 /* No VLAN need to set 0xFFF */ 4100 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4101 4102 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4103 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4104 4105 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4106 } 4107 4108 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4109 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4110 4111 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4112 hr_reg_enable(context, QPC_OWNER_MODE); 4113 4114 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4115 lower_32_bits(hr_qp->rdb.dma) >> 1); 4116 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4117 upper_32_bits(hr_qp->rdb.dma)); 4118 4119 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI) 4120 hr_reg_write_bool(context, QPC_RQIE, 4121 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE); 4122 4123 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4124 4125 if (ibqp->srq) { 4126 hr_reg_enable(context, QPC_SRQ_EN); 4127 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4128 } 4129 4130 hr_reg_enable(context, QPC_FRE); 4131 4132 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4133 4134 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4135 return; 4136 4137 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4138 hr_reg_enable(&context->ext, QPCEX_STASH); 4139 } 4140 4141 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4142 const struct ib_qp_attr *attr, int attr_mask, 4143 struct hns_roce_v2_qp_context *context, 4144 struct hns_roce_v2_qp_context *qpc_mask) 4145 { 4146 /* 4147 * In v2 engine, software pass context and context mask to hardware 4148 * when modifying qp. If software need modify some fields in context, 4149 * we should set all bits of the relevant fields in context mask to 4150 * 0 at the same time, else set them to 0x1. 4151 */ 4152 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4153 hr_reg_clear(qpc_mask, QPC_TST); 4154 4155 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4156 hr_reg_clear(qpc_mask, QPC_PD); 4157 4158 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4159 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4160 4161 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4162 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4163 4164 if (ibqp->srq) { 4165 hr_reg_enable(context, QPC_SRQ_EN); 4166 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4167 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4168 hr_reg_clear(qpc_mask, QPC_SRQN); 4169 } 4170 } 4171 4172 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4173 struct hns_roce_qp *hr_qp, 4174 struct hns_roce_v2_qp_context *context, 4175 struct hns_roce_v2_qp_context *qpc_mask) 4176 { 4177 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4178 u64 wqe_sge_ba; 4179 int count; 4180 4181 /* Search qp buf's mtts */ 4182 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4183 MTT_MIN_COUNT, &wqe_sge_ba); 4184 if (hr_qp->rq.wqe_cnt && count < 1) { 4185 ibdev_err(&hr_dev->ib_dev, 4186 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4187 return -EINVAL; 4188 } 4189 4190 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4191 qpc_mask->wqe_sge_ba = 0; 4192 4193 /* 4194 * In v2 engine, software pass context and context mask to hardware 4195 * when modifying qp. If software need modify some fields in context, 4196 * we should set all bits of the relevant fields in context mask to 4197 * 0 at the same time, else set them to 0x1. 4198 */ 4199 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4200 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4201 4202 hr_reg_write(context, QPC_SQ_HOP_NUM, 4203 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4204 hr_qp->sq.wqe_cnt)); 4205 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4206 4207 hr_reg_write(context, QPC_SGE_HOP_NUM, 4208 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4209 hr_qp->sge.sge_cnt)); 4210 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4211 4212 hr_reg_write(context, QPC_RQ_HOP_NUM, 4213 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4214 hr_qp->rq.wqe_cnt)); 4215 4216 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4217 4218 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4219 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4220 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4221 4222 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4223 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4224 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4225 4226 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4227 qpc_mask->rq_cur_blk_addr = 0; 4228 4229 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4230 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4231 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4232 4233 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4234 qpc_mask->rq_nxt_blk_addr = 0; 4235 4236 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4237 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4238 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4239 4240 return 0; 4241 } 4242 4243 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4244 struct hns_roce_qp *hr_qp, 4245 struct hns_roce_v2_qp_context *context, 4246 struct hns_roce_v2_qp_context *qpc_mask) 4247 { 4248 struct ib_device *ibdev = &hr_dev->ib_dev; 4249 u64 sge_cur_blk = 0; 4250 u64 sq_cur_blk = 0; 4251 int count; 4252 4253 /* search qp buf's mtts */ 4254 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4255 if (count < 1) { 4256 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4257 hr_qp->qpn); 4258 return -EINVAL; 4259 } 4260 if (hr_qp->sge.sge_cnt > 0) { 4261 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4262 hr_qp->sge.offset, 4263 &sge_cur_blk, 1, NULL); 4264 if (count < 1) { 4265 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4266 hr_qp->qpn); 4267 return -EINVAL; 4268 } 4269 } 4270 4271 /* 4272 * In v2 engine, software pass context and context mask to hardware 4273 * when modifying qp. If software need modify some fields in context, 4274 * we should set all bits of the relevant fields in context mask to 4275 * 0 at the same time, else set them to 0x1. 4276 */ 4277 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4278 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4279 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4280 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4281 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4282 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4283 4284 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4285 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4286 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4287 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4288 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4289 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4290 4291 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4292 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4293 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4294 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4295 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4296 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4297 4298 return 0; 4299 } 4300 4301 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4302 const struct ib_qp_attr *attr) 4303 { 4304 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4305 return IB_MTU_4096; 4306 4307 return attr->path_mtu; 4308 } 4309 4310 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4311 const struct ib_qp_attr *attr, int attr_mask, 4312 struct hns_roce_v2_qp_context *context, 4313 struct hns_roce_v2_qp_context *qpc_mask) 4314 { 4315 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4316 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4317 struct ib_device *ibdev = &hr_dev->ib_dev; 4318 dma_addr_t trrl_ba; 4319 dma_addr_t irrl_ba; 4320 enum ib_mtu ib_mtu; 4321 u8 lp_pktn_ini; 4322 u64 *mtts; 4323 u8 *dmac; 4324 u8 *smac; 4325 u32 port; 4326 int mtu; 4327 int ret; 4328 4329 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4330 if (ret) { 4331 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4332 return ret; 4333 } 4334 4335 /* Search IRRL's mtts */ 4336 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4337 hr_qp->qpn, &irrl_ba); 4338 if (!mtts) { 4339 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4340 return -EINVAL; 4341 } 4342 4343 /* Search TRRL's mtts */ 4344 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4345 hr_qp->qpn, &trrl_ba); 4346 if (!mtts) { 4347 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4348 return -EINVAL; 4349 } 4350 4351 if (attr_mask & IB_QP_ALT_PATH) { 4352 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4353 attr_mask); 4354 return -EINVAL; 4355 } 4356 4357 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4358 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4359 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4360 qpc_mask->trrl_ba = 0; 4361 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4362 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4363 4364 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4365 qpc_mask->irrl_ba = 0; 4366 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4367 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4368 4369 hr_reg_enable(context, QPC_RMT_E2E); 4370 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4371 4372 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4373 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4374 4375 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4376 4377 smac = (u8 *)hr_dev->dev_addr[port]; 4378 dmac = (u8 *)attr->ah_attr.roce.dmac; 4379 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4380 if (ether_addr_equal_unaligned(dmac, smac) || 4381 hr_dev->loop_idc == 0x1) { 4382 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4383 hr_reg_clear(qpc_mask, QPC_LBI); 4384 } 4385 4386 if (attr_mask & IB_QP_DEST_QPN) { 4387 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4388 hr_reg_clear(qpc_mask, QPC_DQPN); 4389 } 4390 4391 memcpy(&(context->dmac), dmac, sizeof(u32)); 4392 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4393 qpc_mask->dmac = 0; 4394 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4395 4396 ib_mtu = get_mtu(ibqp, attr); 4397 hr_qp->path_mtu = ib_mtu; 4398 4399 mtu = ib_mtu_enum_to_int(ib_mtu); 4400 if (WARN_ON(mtu < 0)) 4401 return -EINVAL; 4402 4403 if (attr_mask & IB_QP_PATH_MTU) { 4404 hr_reg_write(context, QPC_MTU, ib_mtu); 4405 hr_reg_clear(qpc_mask, QPC_MTU); 4406 } 4407 4408 #define MAX_LP_MSG_LEN 65536 4409 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 64KB */ 4410 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4411 4412 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4413 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4414 4415 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4416 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4417 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4418 4419 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4420 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4421 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4422 4423 context->rq_rnr_timer = 0; 4424 qpc_mask->rq_rnr_timer = 0; 4425 4426 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4427 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4428 4429 /* rocee send 2^lp_sgen_ini segs every time */ 4430 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4431 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4432 4433 return 0; 4434 } 4435 4436 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4437 const struct ib_qp_attr *attr, int attr_mask, 4438 struct hns_roce_v2_qp_context *context, 4439 struct hns_roce_v2_qp_context *qpc_mask) 4440 { 4441 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4442 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4443 struct ib_device *ibdev = &hr_dev->ib_dev; 4444 int ret; 4445 4446 /* Not support alternate path and path migration */ 4447 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4448 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4449 return -EINVAL; 4450 } 4451 4452 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4453 if (ret) { 4454 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4455 return ret; 4456 } 4457 4458 /* 4459 * Set some fields in context to zero, Because the default values 4460 * of all fields in context are zero, we need not set them to 0 again. 4461 * but we should set the relevant fields of context mask to 0. 4462 */ 4463 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4464 4465 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4466 4467 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4468 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4469 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4470 4471 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4472 4473 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4474 4475 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4476 4477 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4478 4479 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4480 4481 return 0; 4482 } 4483 4484 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn) 4485 { 4486 if (!fl) 4487 fl = rdma_calc_flow_label(lqpn, rqpn); 4488 4489 return rdma_flow_label_to_udp_sport(fl); 4490 } 4491 4492 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4493 u32 *dip_idx) 4494 { 4495 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4496 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4497 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4498 u32 *head = &hr_dev->qp_table.idx_table.head; 4499 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4500 struct hns_roce_dip *hr_dip; 4501 unsigned long flags; 4502 int ret = 0; 4503 4504 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4505 4506 spare_idx[*tail] = ibqp->qp_num; 4507 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4508 4509 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4510 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4511 *dip_idx = hr_dip->dip_idx; 4512 goto out; 4513 } 4514 } 4515 4516 /* If no dgid is found, a new dip and a mapping between dgid and 4517 * dip_idx will be created. 4518 */ 4519 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4520 if (!hr_dip) { 4521 ret = -ENOMEM; 4522 goto out; 4523 } 4524 4525 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4526 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4527 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4528 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4529 4530 out: 4531 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4532 return ret; 4533 } 4534 4535 enum { 4536 CONG_DCQCN, 4537 CONG_WINDOW, 4538 }; 4539 4540 enum { 4541 UNSUPPORT_CONG_LEVEL, 4542 SUPPORT_CONG_LEVEL, 4543 }; 4544 4545 enum { 4546 CONG_LDCP, 4547 CONG_HC3, 4548 }; 4549 4550 enum { 4551 DIP_INVALID, 4552 DIP_VALID, 4553 }; 4554 4555 enum { 4556 WND_LIMIT, 4557 WND_UNLIMIT, 4558 }; 4559 4560 static int check_cong_type(struct ib_qp *ibqp, 4561 struct hns_roce_congestion_algorithm *cong_alg) 4562 { 4563 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4564 4565 /* different congestion types match different configurations */ 4566 switch (hr_dev->caps.cong_type) { 4567 case CONG_TYPE_DCQCN: 4568 cong_alg->alg_sel = CONG_DCQCN; 4569 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4570 cong_alg->dip_vld = DIP_INVALID; 4571 cong_alg->wnd_mode_sel = WND_LIMIT; 4572 break; 4573 case CONG_TYPE_LDCP: 4574 cong_alg->alg_sel = CONG_WINDOW; 4575 cong_alg->alg_sub_sel = CONG_LDCP; 4576 cong_alg->dip_vld = DIP_INVALID; 4577 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4578 break; 4579 case CONG_TYPE_HC3: 4580 cong_alg->alg_sel = CONG_WINDOW; 4581 cong_alg->alg_sub_sel = CONG_HC3; 4582 cong_alg->dip_vld = DIP_INVALID; 4583 cong_alg->wnd_mode_sel = WND_LIMIT; 4584 break; 4585 case CONG_TYPE_DIP: 4586 cong_alg->alg_sel = CONG_DCQCN; 4587 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4588 cong_alg->dip_vld = DIP_VALID; 4589 cong_alg->wnd_mode_sel = WND_LIMIT; 4590 break; 4591 default: 4592 ibdev_err(&hr_dev->ib_dev, 4593 "error type(%u) for congestion selection.\n", 4594 hr_dev->caps.cong_type); 4595 return -EINVAL; 4596 } 4597 4598 return 0; 4599 } 4600 4601 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4602 struct hns_roce_v2_qp_context *context, 4603 struct hns_roce_v2_qp_context *qpc_mask) 4604 { 4605 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4606 struct hns_roce_congestion_algorithm cong_field; 4607 struct ib_device *ibdev = ibqp->device; 4608 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4609 u32 dip_idx = 0; 4610 int ret; 4611 4612 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4613 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4614 return 0; 4615 4616 ret = check_cong_type(ibqp, &cong_field); 4617 if (ret) 4618 return ret; 4619 4620 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4621 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4622 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4623 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4624 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4625 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4626 cong_field.alg_sub_sel); 4627 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4628 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4629 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4630 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4631 cong_field.wnd_mode_sel); 4632 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4633 4634 /* if dip is disabled, there is no need to set dip idx */ 4635 if (cong_field.dip_vld == 0) 4636 return 0; 4637 4638 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4639 if (ret) { 4640 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4641 return ret; 4642 } 4643 4644 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4645 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4646 4647 return 0; 4648 } 4649 4650 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4651 const struct ib_qp_attr *attr, 4652 int attr_mask, 4653 struct hns_roce_v2_qp_context *context, 4654 struct hns_roce_v2_qp_context *qpc_mask) 4655 { 4656 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4657 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4658 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4659 struct ib_device *ibdev = &hr_dev->ib_dev; 4660 const struct ib_gid_attr *gid_attr = NULL; 4661 int is_roce_protocol; 4662 u16 vlan_id = 0xffff; 4663 bool is_udp = false; 4664 u8 ib_port; 4665 u8 hr_port; 4666 int ret; 4667 4668 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4669 hr_port = ib_port - 1; 4670 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4671 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4672 4673 if (is_roce_protocol) { 4674 gid_attr = attr->ah_attr.grh.sgid_attr; 4675 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4676 if (ret) 4677 return ret; 4678 4679 if (gid_attr) 4680 is_udp = (gid_attr->gid_type == 4681 IB_GID_TYPE_ROCE_UDP_ENCAP); 4682 } 4683 4684 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4685 if (vlan_id < VLAN_N_VID && 4686 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4687 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4688 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4689 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4690 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4691 } 4692 4693 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4694 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4695 4696 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4697 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4698 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4699 return -EINVAL; 4700 } 4701 4702 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4703 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4704 return -EINVAL; 4705 } 4706 4707 hr_reg_write(context, QPC_UDPSPN, 4708 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num, 4709 attr->dest_qp_num) : 0); 4710 4711 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4712 4713 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4714 4715 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4716 4717 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4718 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4719 4720 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4721 if (ret) 4722 return ret; 4723 4724 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4725 hr_reg_clear(qpc_mask, QPC_TC); 4726 4727 hr_reg_write(context, QPC_FL, grh->flow_label); 4728 hr_reg_clear(qpc_mask, QPC_FL); 4729 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4730 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4731 4732 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4733 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4734 ibdev_err(ibdev, 4735 "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n", 4736 hr_qp->sl, MAX_SERVICE_LEVEL); 4737 return -EINVAL; 4738 } 4739 4740 hr_reg_write(context, QPC_SL, hr_qp->sl); 4741 hr_reg_clear(qpc_mask, QPC_SL); 4742 4743 return 0; 4744 } 4745 4746 static bool check_qp_state(enum ib_qp_state cur_state, 4747 enum ib_qp_state new_state) 4748 { 4749 static const bool sm[][IB_QPS_ERR + 1] = { 4750 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4751 [IB_QPS_INIT] = true }, 4752 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4753 [IB_QPS_INIT] = true, 4754 [IB_QPS_RTR] = true, 4755 [IB_QPS_ERR] = true }, 4756 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4757 [IB_QPS_RTS] = true, 4758 [IB_QPS_ERR] = true }, 4759 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4760 [IB_QPS_RTS] = true, 4761 [IB_QPS_ERR] = true }, 4762 [IB_QPS_SQD] = {}, 4763 [IB_QPS_SQE] = {}, 4764 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4765 }; 4766 4767 return sm[cur_state][new_state]; 4768 } 4769 4770 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4771 const struct ib_qp_attr *attr, 4772 int attr_mask, 4773 enum ib_qp_state cur_state, 4774 enum ib_qp_state new_state, 4775 struct hns_roce_v2_qp_context *context, 4776 struct hns_roce_v2_qp_context *qpc_mask) 4777 { 4778 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4779 int ret = 0; 4780 4781 if (!check_qp_state(cur_state, new_state)) { 4782 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4783 return -EINVAL; 4784 } 4785 4786 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4787 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4788 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4789 qpc_mask); 4790 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4791 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4792 qpc_mask); 4793 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4794 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4795 qpc_mask); 4796 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4797 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4798 qpc_mask); 4799 } 4800 4801 return ret; 4802 } 4803 4804 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4805 const struct ib_qp_attr *attr, 4806 int attr_mask, 4807 struct hns_roce_v2_qp_context *context, 4808 struct hns_roce_v2_qp_context *qpc_mask) 4809 { 4810 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4811 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4812 int ret = 0; 4813 4814 if (attr_mask & IB_QP_AV) { 4815 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4816 qpc_mask); 4817 if (ret) 4818 return ret; 4819 } 4820 4821 if (attr_mask & IB_QP_TIMEOUT) { 4822 if (attr->timeout < 31) { 4823 hr_reg_write(context, QPC_AT, attr->timeout); 4824 hr_reg_clear(qpc_mask, QPC_AT); 4825 } else { 4826 ibdev_warn(&hr_dev->ib_dev, 4827 "Local ACK timeout shall be 0 to 30.\n"); 4828 } 4829 } 4830 4831 if (attr_mask & IB_QP_RETRY_CNT) { 4832 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 4833 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 4834 4835 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 4836 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 4837 } 4838 4839 if (attr_mask & IB_QP_RNR_RETRY) { 4840 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 4841 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 4842 4843 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 4844 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 4845 } 4846 4847 if (attr_mask & IB_QP_SQ_PSN) { 4848 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 4849 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 4850 4851 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 4852 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 4853 4854 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 4855 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 4856 4857 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 4858 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 4859 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 4860 4861 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 4862 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 4863 4864 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 4865 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 4866 } 4867 4868 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4869 attr->max_dest_rd_atomic) { 4870 hr_reg_write(context, QPC_RR_MAX, 4871 fls(attr->max_dest_rd_atomic - 1)); 4872 hr_reg_clear(qpc_mask, QPC_RR_MAX); 4873 } 4874 4875 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4876 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 4877 hr_reg_clear(qpc_mask, QPC_SR_MAX); 4878 } 4879 4880 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4881 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4882 4883 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4884 hr_reg_write(context, QPC_MIN_RNR_TIME, attr->min_rnr_timer); 4885 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 4886 } 4887 4888 if (attr_mask & IB_QP_RQ_PSN) { 4889 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 4890 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 4891 4892 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 4893 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 4894 } 4895 4896 if (attr_mask & IB_QP_QKEY) { 4897 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4898 qpc_mask->qkey_xrcd = 0; 4899 hr_qp->qkey = attr->qkey; 4900 } 4901 4902 return ret; 4903 } 4904 4905 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4906 const struct ib_qp_attr *attr, 4907 int attr_mask) 4908 { 4909 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4910 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4911 4912 if (attr_mask & IB_QP_ACCESS_FLAGS) 4913 hr_qp->atomic_rd_en = attr->qp_access_flags; 4914 4915 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4916 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4917 if (attr_mask & IB_QP_PORT) { 4918 hr_qp->port = attr->port_num - 1; 4919 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4920 } 4921 } 4922 4923 static void clear_qp(struct hns_roce_qp *hr_qp) 4924 { 4925 struct ib_qp *ibqp = &hr_qp->ibqp; 4926 4927 if (ibqp->send_cq) 4928 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4929 hr_qp->qpn, NULL); 4930 4931 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 4932 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 4933 hr_qp->qpn, ibqp->srq ? 4934 to_hr_srq(ibqp->srq) : NULL); 4935 4936 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4937 *hr_qp->rdb.db_record = 0; 4938 4939 hr_qp->rq.head = 0; 4940 hr_qp->rq.tail = 0; 4941 hr_qp->sq.head = 0; 4942 hr_qp->sq.tail = 0; 4943 hr_qp->next_sge = 0; 4944 } 4945 4946 static void v2_set_flushed_fields(struct ib_qp *ibqp, 4947 struct hns_roce_v2_qp_context *context, 4948 struct hns_roce_v2_qp_context *qpc_mask) 4949 { 4950 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4951 unsigned long sq_flag = 0; 4952 unsigned long rq_flag = 0; 4953 4954 if (ibqp->qp_type == IB_QPT_XRC_TGT) 4955 return; 4956 4957 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4958 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 4959 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 4960 hr_qp->state = IB_QPS_ERR; 4961 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4962 4963 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 4964 return; 4965 4966 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4967 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 4968 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 4969 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4970 } 4971 4972 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4973 const struct ib_qp_attr *attr, 4974 int attr_mask, enum ib_qp_state cur_state, 4975 enum ib_qp_state new_state) 4976 { 4977 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4978 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4979 struct hns_roce_v2_qp_context ctx[2]; 4980 struct hns_roce_v2_qp_context *context = ctx; 4981 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4982 struct ib_device *ibdev = &hr_dev->ib_dev; 4983 int ret; 4984 4985 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 4986 return -EOPNOTSUPP; 4987 4988 /* 4989 * In v2 engine, software pass context and context mask to hardware 4990 * when modifying qp. If software need modify some fields in context, 4991 * we should set all bits of the relevant fields in context mask to 4992 * 0 at the same time, else set them to 0x1. 4993 */ 4994 memset(context, 0, hr_dev->caps.qpc_sz); 4995 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 4996 4997 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4998 new_state, context, qpc_mask); 4999 if (ret) 5000 goto out; 5001 5002 /* When QP state is err, SQ and RQ WQE should be flushed */ 5003 if (new_state == IB_QPS_ERR) 5004 v2_set_flushed_fields(ibqp, context, qpc_mask); 5005 5006 /* Configure the optional fields */ 5007 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5008 qpc_mask); 5009 if (ret) 5010 goto out; 5011 5012 hr_reg_write_bool(context, QPC_INV_CREDIT, 5013 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5014 ibqp->srq); 5015 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5016 5017 /* Every status migrate must change state */ 5018 hr_reg_write(context, QPC_QP_ST, new_state); 5019 hr_reg_clear(qpc_mask, QPC_QP_ST); 5020 5021 /* SW pass context to HW */ 5022 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5023 if (ret) { 5024 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5025 goto out; 5026 } 5027 5028 hr_qp->state = new_state; 5029 5030 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5031 5032 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5033 clear_qp(hr_qp); 5034 5035 out: 5036 return ret; 5037 } 5038 5039 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5040 { 5041 static const enum ib_qp_state map[] = { 5042 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5043 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5044 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5045 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5046 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5047 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5048 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5049 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5050 }; 5051 5052 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5053 } 5054 5055 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 5056 struct hns_roce_qp *hr_qp, 5057 struct hns_roce_v2_qp_context *hr_context) 5058 { 5059 struct hns_roce_cmd_mailbox *mailbox; 5060 int ret; 5061 5062 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5063 if (IS_ERR(mailbox)) 5064 return PTR_ERR(mailbox); 5065 5066 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 5067 HNS_ROCE_CMD_QUERY_QPC, 5068 HNS_ROCE_CMD_TIMEOUT_MSECS); 5069 if (ret) 5070 goto out; 5071 5072 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz); 5073 5074 out: 5075 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5076 return ret; 5077 } 5078 5079 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5080 int qp_attr_mask, 5081 struct ib_qp_init_attr *qp_init_attr) 5082 { 5083 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5084 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5085 struct hns_roce_v2_qp_context context = {}; 5086 struct ib_device *ibdev = &hr_dev->ib_dev; 5087 int tmp_qp_state; 5088 int state; 5089 int ret; 5090 5091 memset(qp_attr, 0, sizeof(*qp_attr)); 5092 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5093 5094 mutex_lock(&hr_qp->mutex); 5095 5096 if (hr_qp->state == IB_QPS_RESET) { 5097 qp_attr->qp_state = IB_QPS_RESET; 5098 ret = 0; 5099 goto done; 5100 } 5101 5102 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 5103 if (ret) { 5104 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5105 ret = -EINVAL; 5106 goto out; 5107 } 5108 5109 state = hr_reg_read(&context, QPC_QP_ST); 5110 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5111 if (tmp_qp_state == -1) { 5112 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5113 ret = -EINVAL; 5114 goto out; 5115 } 5116 hr_qp->state = (u8)tmp_qp_state; 5117 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5118 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5119 qp_attr->path_mig_state = IB_MIG_ARMED; 5120 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5121 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5122 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5123 5124 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5125 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5126 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5127 qp_attr->qp_access_flags = 5128 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5129 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5130 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5131 5132 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5133 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5134 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5135 struct ib_global_route *grh = 5136 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5137 5138 rdma_ah_set_sl(&qp_attr->ah_attr, 5139 hr_reg_read(&context, QPC_SL)); 5140 grh->flow_label = hr_reg_read(&context, QPC_FL); 5141 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5142 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5143 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5144 5145 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5146 } 5147 5148 qp_attr->port_num = hr_qp->port + 1; 5149 qp_attr->sq_draining = 0; 5150 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5151 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5152 5153 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5154 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5155 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5156 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5157 5158 done: 5159 qp_attr->cur_qp_state = qp_attr->qp_state; 5160 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5161 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5162 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5163 5164 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5165 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5166 5167 qp_init_attr->qp_context = ibqp->qp_context; 5168 qp_init_attr->qp_type = ibqp->qp_type; 5169 qp_init_attr->recv_cq = ibqp->recv_cq; 5170 qp_init_attr->send_cq = ibqp->send_cq; 5171 qp_init_attr->srq = ibqp->srq; 5172 qp_init_attr->cap = qp_attr->cap; 5173 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5174 5175 out: 5176 mutex_unlock(&hr_qp->mutex); 5177 return ret; 5178 } 5179 5180 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5181 { 5182 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5183 hr_qp->ibqp.qp_type == IB_QPT_UD || 5184 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5185 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5186 hr_qp->state != IB_QPS_RESET); 5187 } 5188 5189 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5190 struct hns_roce_qp *hr_qp, 5191 struct ib_udata *udata) 5192 { 5193 struct ib_device *ibdev = &hr_dev->ib_dev; 5194 struct hns_roce_cq *send_cq, *recv_cq; 5195 unsigned long flags; 5196 int ret = 0; 5197 5198 if (modify_qp_is_ok(hr_qp)) { 5199 /* Modify qp to reset before destroying qp */ 5200 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5201 hr_qp->state, IB_QPS_RESET); 5202 if (ret) 5203 ibdev_err(ibdev, 5204 "failed to modify QP to RST, ret = %d.\n", 5205 ret); 5206 } 5207 5208 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5209 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5210 5211 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5212 hns_roce_lock_cqs(send_cq, recv_cq); 5213 5214 if (!udata) { 5215 if (recv_cq) 5216 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5217 (hr_qp->ibqp.srq ? 5218 to_hr_srq(hr_qp->ibqp.srq) : 5219 NULL)); 5220 5221 if (send_cq && send_cq != recv_cq) 5222 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5223 } 5224 5225 hns_roce_qp_remove(hr_dev, hr_qp); 5226 5227 hns_roce_unlock_cqs(send_cq, recv_cq); 5228 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5229 5230 return ret; 5231 } 5232 5233 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5234 { 5235 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5236 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5237 int ret; 5238 5239 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5240 if (ret) 5241 ibdev_err(&hr_dev->ib_dev, 5242 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5243 hr_qp->qpn, ret); 5244 5245 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5246 5247 return 0; 5248 } 5249 5250 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5251 struct hns_roce_qp *hr_qp) 5252 { 5253 struct ib_device *ibdev = &hr_dev->ib_dev; 5254 struct hns_roce_sccc_clr_done *resp; 5255 struct hns_roce_sccc_clr *clr; 5256 struct hns_roce_cmq_desc desc; 5257 int ret, i; 5258 5259 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5260 return 0; 5261 5262 mutex_lock(&hr_dev->qp_table.scc_mutex); 5263 5264 /* set scc ctx clear done flag */ 5265 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5266 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5267 if (ret) { 5268 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5269 goto out; 5270 } 5271 5272 /* clear scc context */ 5273 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5274 clr = (struct hns_roce_sccc_clr *)desc.data; 5275 clr->qpn = cpu_to_le32(hr_qp->qpn); 5276 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5277 if (ret) { 5278 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5279 goto out; 5280 } 5281 5282 /* query scc context clear is done or not */ 5283 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5284 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5285 hns_roce_cmq_setup_basic_desc(&desc, 5286 HNS_ROCE_OPC_QUERY_SCCC, true); 5287 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5288 if (ret) { 5289 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5290 ret); 5291 goto out; 5292 } 5293 5294 if (resp->clr_done) 5295 goto out; 5296 5297 msleep(20); 5298 } 5299 5300 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 5301 ret = -ETIMEDOUT; 5302 5303 out: 5304 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5305 return ret; 5306 } 5307 5308 #define DMA_IDX_SHIFT 3 5309 #define DMA_WQE_SHIFT 3 5310 5311 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5312 struct hns_roce_srq_context *ctx) 5313 { 5314 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5315 struct ib_device *ibdev = srq->ibsrq.device; 5316 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5317 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5318 dma_addr_t dma_handle_idx = 0; 5319 int ret; 5320 5321 /* Get physical address of idx que buf */ 5322 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5323 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5324 if (ret < 1) { 5325 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5326 ret); 5327 return -ENOBUFS; 5328 } 5329 5330 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5331 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5332 5333 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5334 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5335 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5336 5337 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5338 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5339 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5340 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5341 5342 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5343 to_hr_hw_page_addr(mtts_idx[0])); 5344 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5345 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5346 5347 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5348 to_hr_hw_page_addr(mtts_idx[1])); 5349 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5350 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5351 5352 return 0; 5353 } 5354 5355 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5356 { 5357 struct ib_device *ibdev = srq->ibsrq.device; 5358 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5359 struct hns_roce_srq_context *ctx = mb_buf; 5360 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5361 dma_addr_t dma_handle_wqe = 0; 5362 int ret; 5363 5364 memset(ctx, 0, sizeof(*ctx)); 5365 5366 /* Get the physical address of srq buf */ 5367 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5368 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5369 if (ret < 1) { 5370 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5371 ret); 5372 return -ENOBUFS; 5373 } 5374 5375 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5376 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5377 srq->ibsrq.srq_type == IB_SRQT_XRC); 5378 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5379 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5380 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5381 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5382 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5383 hr_reg_write(ctx, SRQC_RQWS, 5384 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5385 5386 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5387 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5388 srq->wqe_cnt)); 5389 5390 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5391 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5392 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5393 5394 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5395 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5396 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5397 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5398 5399 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5400 } 5401 5402 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5403 struct ib_srq_attr *srq_attr, 5404 enum ib_srq_attr_mask srq_attr_mask, 5405 struct ib_udata *udata) 5406 { 5407 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5408 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5409 struct hns_roce_srq_context *srq_context; 5410 struct hns_roce_srq_context *srqc_mask; 5411 struct hns_roce_cmd_mailbox *mailbox; 5412 int ret; 5413 5414 /* Resizing SRQs is not supported yet */ 5415 if (srq_attr_mask & IB_SRQ_MAX_WR) 5416 return -EINVAL; 5417 5418 if (srq_attr_mask & IB_SRQ_LIMIT) { 5419 if (srq_attr->srq_limit > srq->wqe_cnt) 5420 return -EINVAL; 5421 5422 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5423 if (IS_ERR(mailbox)) 5424 return PTR_ERR(mailbox); 5425 5426 srq_context = mailbox->buf; 5427 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5428 5429 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5430 5431 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5432 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5433 5434 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5435 HNS_ROCE_CMD_MODIFY_SRQC, 5436 HNS_ROCE_CMD_TIMEOUT_MSECS); 5437 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5438 if (ret) { 5439 ibdev_err(&hr_dev->ib_dev, 5440 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5441 ret); 5442 return ret; 5443 } 5444 } 5445 5446 return 0; 5447 } 5448 5449 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5450 { 5451 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5452 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5453 struct hns_roce_srq_context *srq_context; 5454 struct hns_roce_cmd_mailbox *mailbox; 5455 int ret; 5456 5457 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5458 if (IS_ERR(mailbox)) 5459 return PTR_ERR(mailbox); 5460 5461 srq_context = mailbox->buf; 5462 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5463 HNS_ROCE_CMD_QUERY_SRQC, 5464 HNS_ROCE_CMD_TIMEOUT_MSECS); 5465 if (ret) { 5466 ibdev_err(&hr_dev->ib_dev, 5467 "failed to process cmd of querying SRQ, ret = %d.\n", 5468 ret); 5469 goto out; 5470 } 5471 5472 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5473 attr->max_wr = srq->wqe_cnt; 5474 attr->max_sge = srq->max_gs - srq->rsv_sge; 5475 5476 out: 5477 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5478 return ret; 5479 } 5480 5481 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5482 { 5483 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5484 struct hns_roce_v2_cq_context *cq_context; 5485 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5486 struct hns_roce_v2_cq_context *cqc_mask; 5487 struct hns_roce_cmd_mailbox *mailbox; 5488 int ret; 5489 5490 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5491 if (IS_ERR(mailbox)) 5492 return PTR_ERR(mailbox); 5493 5494 cq_context = mailbox->buf; 5495 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5496 5497 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5498 5499 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5500 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5501 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5502 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5503 5504 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5505 HNS_ROCE_CMD_MODIFY_CQC, 5506 HNS_ROCE_CMD_TIMEOUT_MSECS); 5507 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5508 if (ret) 5509 ibdev_err(&hr_dev->ib_dev, 5510 "failed to process cmd when modifying CQ, ret = %d.\n", 5511 ret); 5512 5513 return ret; 5514 } 5515 5516 static void hns_roce_irq_work_handle(struct work_struct *work) 5517 { 5518 struct hns_roce_work *irq_work = 5519 container_of(work, struct hns_roce_work, work); 5520 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5521 5522 switch (irq_work->event_type) { 5523 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5524 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5525 break; 5526 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5527 ibdev_warn(ibdev, "Path migration failed.\n"); 5528 break; 5529 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5530 break; 5531 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5532 ibdev_warn(ibdev, "Send queue drained.\n"); 5533 break; 5534 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5535 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5536 irq_work->queue_num, irq_work->sub_type); 5537 break; 5538 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5539 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5540 irq_work->queue_num); 5541 break; 5542 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5543 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5544 irq_work->queue_num, irq_work->sub_type); 5545 break; 5546 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5547 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5548 break; 5549 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5550 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5551 break; 5552 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5553 ibdev_err(ibdev, "SRQ catas error.\n"); 5554 break; 5555 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5556 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5557 break; 5558 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5559 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5560 break; 5561 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5562 ibdev_warn(ibdev, "DB overflow.\n"); 5563 break; 5564 case HNS_ROCE_EVENT_TYPE_FLR: 5565 ibdev_warn(ibdev, "Function level reset.\n"); 5566 break; 5567 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5568 ibdev_err(ibdev, "xrc domain violation error.\n"); 5569 break; 5570 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5571 ibdev_err(ibdev, "invalid xrceth error.\n"); 5572 break; 5573 default: 5574 break; 5575 } 5576 5577 kfree(irq_work); 5578 } 5579 5580 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5581 struct hns_roce_eq *eq, u32 queue_num) 5582 { 5583 struct hns_roce_work *irq_work; 5584 5585 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5586 if (!irq_work) 5587 return; 5588 5589 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5590 irq_work->hr_dev = hr_dev; 5591 irq_work->event_type = eq->event_type; 5592 irq_work->sub_type = eq->sub_type; 5593 irq_work->queue_num = queue_num; 5594 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5595 } 5596 5597 static void update_eq_db(struct hns_roce_eq *eq) 5598 { 5599 struct hns_roce_dev *hr_dev = eq->hr_dev; 5600 struct hns_roce_v2_db eq_db = {}; 5601 5602 if (eq->type_flag == HNS_ROCE_AEQ) { 5603 hr_reg_write(&eq_db, EQ_DB_CMD, 5604 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5605 HNS_ROCE_EQ_DB_CMD_AEQ : 5606 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5607 } else { 5608 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5609 5610 hr_reg_write(&eq_db, EQ_DB_CMD, 5611 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5612 HNS_ROCE_EQ_DB_CMD_CEQ : 5613 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5614 } 5615 5616 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5617 5618 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5619 } 5620 5621 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5622 { 5623 struct hns_roce_aeqe *aeqe; 5624 5625 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5626 (eq->cons_index & (eq->entries - 1)) * 5627 eq->eqe_size); 5628 5629 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5630 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5631 } 5632 5633 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5634 struct hns_roce_eq *eq) 5635 { 5636 struct device *dev = hr_dev->dev; 5637 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5638 int aeqe_found = 0; 5639 int event_type; 5640 u32 queue_num; 5641 int sub_type; 5642 5643 while (aeqe) { 5644 /* Make sure we read AEQ entry after we have checked the 5645 * ownership bit 5646 */ 5647 dma_rmb(); 5648 5649 event_type = roce_get_field(aeqe->asyn, 5650 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5651 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5652 sub_type = roce_get_field(aeqe->asyn, 5653 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5654 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5655 queue_num = roce_get_field(aeqe->event.queue_event.num, 5656 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5657 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5658 5659 switch (event_type) { 5660 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5661 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5662 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5663 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5664 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5665 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5666 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5667 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5668 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5669 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5670 hns_roce_qp_event(hr_dev, queue_num, event_type); 5671 break; 5672 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5673 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5674 hns_roce_srq_event(hr_dev, queue_num, event_type); 5675 break; 5676 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5677 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5678 hns_roce_cq_event(hr_dev, queue_num, event_type); 5679 break; 5680 case HNS_ROCE_EVENT_TYPE_MB: 5681 hns_roce_cmd_event(hr_dev, 5682 le16_to_cpu(aeqe->event.cmd.token), 5683 aeqe->event.cmd.status, 5684 le64_to_cpu(aeqe->event.cmd.out_param)); 5685 break; 5686 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5687 case HNS_ROCE_EVENT_TYPE_FLR: 5688 break; 5689 default: 5690 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5691 event_type, eq->eqn, eq->cons_index); 5692 break; 5693 } 5694 5695 eq->event_type = event_type; 5696 eq->sub_type = sub_type; 5697 ++eq->cons_index; 5698 aeqe_found = 1; 5699 5700 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5701 5702 aeqe = next_aeqe_sw_v2(eq); 5703 } 5704 5705 update_eq_db(eq); 5706 return aeqe_found; 5707 } 5708 5709 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5710 { 5711 struct hns_roce_ceqe *ceqe; 5712 5713 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5714 (eq->cons_index & (eq->entries - 1)) * 5715 eq->eqe_size); 5716 5717 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5718 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5719 } 5720 5721 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5722 struct hns_roce_eq *eq) 5723 { 5724 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5725 int ceqe_found = 0; 5726 u32 cqn; 5727 5728 while (ceqe) { 5729 /* Make sure we read CEQ entry after we have checked the 5730 * ownership bit 5731 */ 5732 dma_rmb(); 5733 5734 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5735 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5736 5737 hns_roce_cq_completion(hr_dev, cqn); 5738 5739 ++eq->cons_index; 5740 ceqe_found = 1; 5741 5742 ceqe = next_ceqe_sw_v2(eq); 5743 } 5744 5745 update_eq_db(eq); 5746 5747 return ceqe_found; 5748 } 5749 5750 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5751 { 5752 struct hns_roce_eq *eq = eq_ptr; 5753 struct hns_roce_dev *hr_dev = eq->hr_dev; 5754 int int_work; 5755 5756 if (eq->type_flag == HNS_ROCE_CEQ) 5757 /* Completion event interrupt */ 5758 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5759 else 5760 /* Asychronous event interrupt */ 5761 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5762 5763 return IRQ_RETVAL(int_work); 5764 } 5765 5766 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5767 { 5768 struct hns_roce_dev *hr_dev = dev_id; 5769 struct device *dev = hr_dev->dev; 5770 int int_work = 0; 5771 u32 int_st; 5772 u32 int_en; 5773 5774 /* Abnormal interrupt */ 5775 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5776 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5777 5778 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5779 struct pci_dev *pdev = hr_dev->pci_dev; 5780 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5781 const struct hnae3_ae_ops *ops = ae_dev->ops; 5782 5783 dev_err(dev, "AEQ overflow!\n"); 5784 5785 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5786 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5787 5788 /* Set reset level for reset_event() */ 5789 if (ops->set_default_reset_request) 5790 ops->set_default_reset_request(ae_dev, 5791 HNAE3_FUNC_RESET); 5792 if (ops->reset_event) 5793 ops->reset_event(pdev, NULL); 5794 5795 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5796 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5797 5798 int_work = 1; 5799 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) { 5800 dev_err(dev, "RAS interrupt!\n"); 5801 5802 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S; 5803 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5804 5805 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5806 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5807 5808 int_work = 1; 5809 } else { 5810 dev_err(dev, "There is no abnormal irq found!\n"); 5811 } 5812 5813 return IRQ_RETVAL(int_work); 5814 } 5815 5816 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5817 int eq_num, u32 enable_flag) 5818 { 5819 int i; 5820 5821 for (i = 0; i < eq_num; i++) 5822 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5823 i * EQ_REG_OFFSET, enable_flag); 5824 5825 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 5826 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 5827 } 5828 5829 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5830 { 5831 struct device *dev = hr_dev->dev; 5832 int ret; 5833 5834 if (eqn < hr_dev->caps.num_comp_vectors) 5835 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5836 0, HNS_ROCE_CMD_DESTROY_CEQC, 5837 HNS_ROCE_CMD_TIMEOUT_MSECS); 5838 else 5839 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5840 0, HNS_ROCE_CMD_DESTROY_AEQC, 5841 HNS_ROCE_CMD_TIMEOUT_MSECS); 5842 if (ret) 5843 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5844 } 5845 5846 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5847 { 5848 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5849 } 5850 5851 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5852 { 5853 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5854 eq->cons_index = 0; 5855 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5856 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5857 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5858 eq->shift = ilog2((unsigned int)eq->entries); 5859 } 5860 5861 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5862 void *mb_buf) 5863 { 5864 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5865 struct hns_roce_eq_context *eqc; 5866 u64 bt_ba = 0; 5867 int count; 5868 5869 eqc = mb_buf; 5870 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5871 5872 init_eq_config(hr_dev, eq); 5873 5874 /* if not multi-hop, eqe buffer only use one trunk */ 5875 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5876 &bt_ba); 5877 if (count < 1) { 5878 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5879 return -ENOBUFS; 5880 } 5881 5882 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 5883 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 5884 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 5885 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 5886 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 5887 hr_reg_write(eqc, EQC_EQN, eq->eqn); 5888 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 5889 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 5890 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5891 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 5892 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5893 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 5894 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 5895 5896 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 5897 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 5898 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 5899 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 5900 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 5901 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 5902 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 5903 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 5904 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 5905 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 5906 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 5907 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 5908 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 5909 5910 return 0; 5911 } 5912 5913 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5914 { 5915 struct hns_roce_buf_attr buf_attr = {}; 5916 int err; 5917 5918 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5919 eq->hop_num = 0; 5920 else 5921 eq->hop_num = hr_dev->caps.eqe_hop_num; 5922 5923 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 5924 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5925 buf_attr.region[0].hopnum = eq->hop_num; 5926 buf_attr.region_count = 1; 5927 5928 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5929 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 5930 0); 5931 if (err) 5932 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5933 5934 return err; 5935 } 5936 5937 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5938 struct hns_roce_eq *eq, 5939 unsigned int eq_cmd) 5940 { 5941 struct hns_roce_cmd_mailbox *mailbox; 5942 int ret; 5943 5944 /* Allocate mailbox memory */ 5945 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5946 if (IS_ERR_OR_NULL(mailbox)) 5947 return -ENOMEM; 5948 5949 ret = alloc_eq_buf(hr_dev, eq); 5950 if (ret) 5951 goto free_cmd_mbox; 5952 5953 ret = config_eqc(hr_dev, eq, mailbox->buf); 5954 if (ret) 5955 goto err_cmd_mbox; 5956 5957 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5958 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5959 if (ret) { 5960 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5961 goto err_cmd_mbox; 5962 } 5963 5964 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5965 5966 return 0; 5967 5968 err_cmd_mbox: 5969 free_eq_buf(hr_dev, eq); 5970 5971 free_cmd_mbox: 5972 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5973 5974 return ret; 5975 } 5976 5977 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5978 int comp_num, int aeq_num, int other_num) 5979 { 5980 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5981 int i, j; 5982 int ret; 5983 5984 for (i = 0; i < irq_num; i++) { 5985 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5986 GFP_KERNEL); 5987 if (!hr_dev->irq_names[i]) { 5988 ret = -ENOMEM; 5989 goto err_kzalloc_failed; 5990 } 5991 } 5992 5993 /* irq contains: abnormal + AEQ + CEQ */ 5994 for (j = 0; j < other_num; j++) 5995 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5996 "hns-abn-%d", j); 5997 5998 for (j = other_num; j < (other_num + aeq_num); j++) 5999 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6000 "hns-aeq-%d", j - other_num); 6001 6002 for (j = (other_num + aeq_num); j < irq_num; j++) 6003 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6004 "hns-ceq-%d", j - other_num - aeq_num); 6005 6006 for (j = 0; j < irq_num; j++) { 6007 if (j < other_num) 6008 ret = request_irq(hr_dev->irq[j], 6009 hns_roce_v2_msix_interrupt_abn, 6010 0, hr_dev->irq_names[j], hr_dev); 6011 6012 else if (j < (other_num + comp_num)) 6013 ret = request_irq(eq_table->eq[j - other_num].irq, 6014 hns_roce_v2_msix_interrupt_eq, 6015 0, hr_dev->irq_names[j + aeq_num], 6016 &eq_table->eq[j - other_num]); 6017 else 6018 ret = request_irq(eq_table->eq[j - other_num].irq, 6019 hns_roce_v2_msix_interrupt_eq, 6020 0, hr_dev->irq_names[j - comp_num], 6021 &eq_table->eq[j - other_num]); 6022 if (ret) { 6023 dev_err(hr_dev->dev, "Request irq error!\n"); 6024 goto err_request_failed; 6025 } 6026 } 6027 6028 return 0; 6029 6030 err_request_failed: 6031 for (j -= 1; j >= 0; j--) 6032 if (j < other_num) 6033 free_irq(hr_dev->irq[j], hr_dev); 6034 else 6035 free_irq(eq_table->eq[j - other_num].irq, 6036 &eq_table->eq[j - other_num]); 6037 6038 err_kzalloc_failed: 6039 for (i -= 1; i >= 0; i--) 6040 kfree(hr_dev->irq_names[i]); 6041 6042 return ret; 6043 } 6044 6045 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6046 { 6047 int irq_num; 6048 int eq_num; 6049 int i; 6050 6051 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6052 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6053 6054 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6055 free_irq(hr_dev->irq[i], hr_dev); 6056 6057 for (i = 0; i < eq_num; i++) 6058 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6059 6060 for (i = 0; i < irq_num; i++) 6061 kfree(hr_dev->irq_names[i]); 6062 } 6063 6064 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6065 { 6066 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6067 struct device *dev = hr_dev->dev; 6068 struct hns_roce_eq *eq; 6069 unsigned int eq_cmd; 6070 int irq_num; 6071 int eq_num; 6072 int other_num; 6073 int comp_num; 6074 int aeq_num; 6075 int i; 6076 int ret; 6077 6078 other_num = hr_dev->caps.num_other_vectors; 6079 comp_num = hr_dev->caps.num_comp_vectors; 6080 aeq_num = hr_dev->caps.num_aeq_vectors; 6081 6082 eq_num = comp_num + aeq_num; 6083 irq_num = eq_num + other_num; 6084 6085 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6086 if (!eq_table->eq) 6087 return -ENOMEM; 6088 6089 /* create eq */ 6090 for (i = 0; i < eq_num; i++) { 6091 eq = &eq_table->eq[i]; 6092 eq->hr_dev = hr_dev; 6093 eq->eqn = i; 6094 if (i < comp_num) { 6095 /* CEQ */ 6096 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6097 eq->type_flag = HNS_ROCE_CEQ; 6098 eq->entries = hr_dev->caps.ceqe_depth; 6099 eq->eqe_size = hr_dev->caps.ceqe_size; 6100 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6101 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6102 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6103 } else { 6104 /* AEQ */ 6105 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6106 eq->type_flag = HNS_ROCE_AEQ; 6107 eq->entries = hr_dev->caps.aeqe_depth; 6108 eq->eqe_size = hr_dev->caps.aeqe_size; 6109 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6110 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6111 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6112 } 6113 6114 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6115 if (ret) { 6116 dev_err(dev, "failed to create eq.\n"); 6117 goto err_create_eq_fail; 6118 } 6119 } 6120 6121 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6122 if (!hr_dev->irq_workq) { 6123 dev_err(dev, "failed to create irq workqueue.\n"); 6124 ret = -ENOMEM; 6125 goto err_create_eq_fail; 6126 } 6127 6128 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6129 other_num); 6130 if (ret) { 6131 dev_err(dev, "failed to request irq.\n"); 6132 goto err_request_irq_fail; 6133 } 6134 6135 /* enable irq */ 6136 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6137 6138 return 0; 6139 6140 err_request_irq_fail: 6141 destroy_workqueue(hr_dev->irq_workq); 6142 6143 err_create_eq_fail: 6144 for (i -= 1; i >= 0; i--) 6145 free_eq_buf(hr_dev, &eq_table->eq[i]); 6146 kfree(eq_table->eq); 6147 6148 return ret; 6149 } 6150 6151 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6152 { 6153 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6154 int eq_num; 6155 int i; 6156 6157 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6158 6159 /* Disable irq */ 6160 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6161 6162 __hns_roce_free_irq(hr_dev); 6163 destroy_workqueue(hr_dev->irq_workq); 6164 6165 for (i = 0; i < eq_num; i++) { 6166 hns_roce_v2_destroy_eqc(hr_dev, i); 6167 6168 free_eq_buf(hr_dev, &eq_table->eq[i]); 6169 } 6170 6171 kfree(eq_table->eq); 6172 } 6173 6174 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 6175 .query_cqc_info = hns_roce_v2_query_cqc_info, 6176 }; 6177 6178 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6179 .destroy_qp = hns_roce_v2_destroy_qp, 6180 .modify_cq = hns_roce_v2_modify_cq, 6181 .poll_cq = hns_roce_v2_poll_cq, 6182 .post_recv = hns_roce_v2_post_recv, 6183 .post_send = hns_roce_v2_post_send, 6184 .query_qp = hns_roce_v2_query_qp, 6185 .req_notify_cq = hns_roce_v2_req_notify_cq, 6186 }; 6187 6188 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6189 .modify_srq = hns_roce_v2_modify_srq, 6190 .post_srq_recv = hns_roce_v2_post_srq_recv, 6191 .query_srq = hns_roce_v2_query_srq, 6192 }; 6193 6194 static const struct hns_roce_hw hns_roce_hw_v2 = { 6195 .cmq_init = hns_roce_v2_cmq_init, 6196 .cmq_exit = hns_roce_v2_cmq_exit, 6197 .hw_profile = hns_roce_v2_profile, 6198 .hw_init = hns_roce_v2_init, 6199 .hw_exit = hns_roce_v2_exit, 6200 .post_mbox = v2_post_mbox, 6201 .poll_mbox_done = v2_poll_mbox_done, 6202 .chk_mbox_avail = v2_chk_mbox_is_avail, 6203 .set_gid = hns_roce_v2_set_gid, 6204 .set_mac = hns_roce_v2_set_mac, 6205 .write_mtpt = hns_roce_v2_write_mtpt, 6206 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6207 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6208 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6209 .write_cqc = hns_roce_v2_write_cqc, 6210 .set_hem = hns_roce_v2_set_hem, 6211 .clear_hem = hns_roce_v2_clear_hem, 6212 .modify_qp = hns_roce_v2_modify_qp, 6213 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6214 .init_eq = hns_roce_v2_init_eq_table, 6215 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6216 .write_srqc = hns_roce_v2_write_srqc, 6217 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6218 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6219 }; 6220 6221 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6222 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6223 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6224 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6225 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6226 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6227 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6228 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6229 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6230 /* required last entry */ 6231 {0, } 6232 }; 6233 6234 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6235 6236 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6237 struct hnae3_handle *handle) 6238 { 6239 struct hns_roce_v2_priv *priv = hr_dev->priv; 6240 const struct pci_device_id *id; 6241 int i; 6242 6243 hr_dev->pci_dev = handle->pdev; 6244 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6245 hr_dev->is_vf = id->driver_data; 6246 hr_dev->dev = &handle->pdev->dev; 6247 hr_dev->hw = &hns_roce_hw_v2; 6248 hr_dev->dfx = &hns_roce_dfx_hw_v2; 6249 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6250 hr_dev->odb_offset = hr_dev->sdb_offset; 6251 6252 /* Get info from NIC driver. */ 6253 hr_dev->reg_base = handle->rinfo.roce_io_base; 6254 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6255 hr_dev->caps.num_ports = 1; 6256 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6257 hr_dev->iboe.phy_port[0] = 0; 6258 6259 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6260 hr_dev->iboe.netdevs[0]->dev_addr); 6261 6262 for (i = 0; i < handle->rinfo.num_vectors; i++) 6263 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6264 i + handle->rinfo.base_vector); 6265 6266 /* cmd issue mode: 0 is poll, 1 is event */ 6267 hr_dev->cmd_mod = 1; 6268 hr_dev->loop_idc = 0; 6269 6270 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6271 priv->handle = handle; 6272 } 6273 6274 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6275 { 6276 struct hns_roce_dev *hr_dev; 6277 int ret; 6278 6279 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6280 if (!hr_dev) 6281 return -ENOMEM; 6282 6283 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6284 if (!hr_dev->priv) { 6285 ret = -ENOMEM; 6286 goto error_failed_kzalloc; 6287 } 6288 6289 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6290 6291 ret = hns_roce_init(hr_dev); 6292 if (ret) { 6293 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6294 goto error_failed_get_cfg; 6295 } 6296 6297 handle->priv = hr_dev; 6298 6299 return 0; 6300 6301 error_failed_get_cfg: 6302 kfree(hr_dev->priv); 6303 6304 error_failed_kzalloc: 6305 ib_dealloc_device(&hr_dev->ib_dev); 6306 6307 return ret; 6308 } 6309 6310 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6311 bool reset) 6312 { 6313 struct hns_roce_dev *hr_dev = handle->priv; 6314 6315 if (!hr_dev) 6316 return; 6317 6318 handle->priv = NULL; 6319 6320 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6321 hns_roce_handle_device_err(hr_dev); 6322 6323 hns_roce_exit(hr_dev); 6324 kfree(hr_dev->priv); 6325 ib_dealloc_device(&hr_dev->ib_dev); 6326 } 6327 6328 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6329 { 6330 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6331 const struct pci_device_id *id; 6332 struct device *dev = &handle->pdev->dev; 6333 int ret; 6334 6335 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6336 6337 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6338 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6339 goto reset_chk_err; 6340 } 6341 6342 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6343 if (!id) 6344 return 0; 6345 6346 if (id->driver_data && handle->pdev->revision < PCI_REVISION_ID_HIP09) 6347 return 0; 6348 6349 ret = __hns_roce_hw_v2_init_instance(handle); 6350 if (ret) { 6351 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6352 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6353 if (ops->ae_dev_resetting(handle) || 6354 ops->get_hw_reset_stat(handle)) 6355 goto reset_chk_err; 6356 else 6357 return ret; 6358 } 6359 6360 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6361 6362 return 0; 6363 6364 reset_chk_err: 6365 dev_err(dev, "Device is busy in resetting state.\n" 6366 "please retry later.\n"); 6367 6368 return -EBUSY; 6369 } 6370 6371 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6372 bool reset) 6373 { 6374 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6375 return; 6376 6377 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6378 6379 __hns_roce_hw_v2_uninit_instance(handle, reset); 6380 6381 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6382 } 6383 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6384 { 6385 struct hns_roce_dev *hr_dev; 6386 6387 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6388 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6389 return 0; 6390 } 6391 6392 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6393 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6394 6395 hr_dev = handle->priv; 6396 if (!hr_dev) 6397 return 0; 6398 6399 hr_dev->is_reset = true; 6400 hr_dev->active = false; 6401 hr_dev->dis_db = true; 6402 6403 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6404 6405 return 0; 6406 } 6407 6408 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6409 { 6410 struct device *dev = &handle->pdev->dev; 6411 int ret; 6412 6413 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6414 &handle->rinfo.state)) { 6415 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6416 return 0; 6417 } 6418 6419 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6420 6421 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6422 ret = __hns_roce_hw_v2_init_instance(handle); 6423 if (ret) { 6424 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6425 * callback function, RoCE Engine reinitialize. If RoCE reinit 6426 * failed, we should inform NIC driver. 6427 */ 6428 handle->priv = NULL; 6429 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6430 } else { 6431 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6432 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6433 } 6434 6435 return ret; 6436 } 6437 6438 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6439 { 6440 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6441 return 0; 6442 6443 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6444 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6445 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6446 __hns_roce_hw_v2_uninit_instance(handle, false); 6447 6448 return 0; 6449 } 6450 6451 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6452 enum hnae3_reset_notify_type type) 6453 { 6454 int ret = 0; 6455 6456 switch (type) { 6457 case HNAE3_DOWN_CLIENT: 6458 ret = hns_roce_hw_v2_reset_notify_down(handle); 6459 break; 6460 case HNAE3_INIT_CLIENT: 6461 ret = hns_roce_hw_v2_reset_notify_init(handle); 6462 break; 6463 case HNAE3_UNINIT_CLIENT: 6464 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6465 break; 6466 default: 6467 break; 6468 } 6469 6470 return ret; 6471 } 6472 6473 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6474 .init_instance = hns_roce_hw_v2_init_instance, 6475 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6476 .reset_notify = hns_roce_hw_v2_reset_notify, 6477 }; 6478 6479 static struct hnae3_client hns_roce_hw_v2_client = { 6480 .name = "hns_roce_hw_v2", 6481 .type = HNAE3_CLIENT_ROCE, 6482 .ops = &hns_roce_hw_v2_ops, 6483 }; 6484 6485 static int __init hns_roce_hw_v2_init(void) 6486 { 6487 return hnae3_register_client(&hns_roce_hw_v2_client); 6488 } 6489 6490 static void __exit hns_roce_hw_v2_exit(void) 6491 { 6492 hnae3_unregister_client(&hns_roce_hw_v2_client); 6493 } 6494 6495 module_init(hns_roce_hw_v2_init); 6496 module_exit(hns_roce_hw_v2_exit); 6497 6498 MODULE_LICENSE("Dual BSD/GPL"); 6499 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6500 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6501 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6502 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6503