1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 52 struct ib_sge *sg) 53 { 54 dseg->lkey = cpu_to_le32(sg->lkey); 55 dseg->addr = cpu_to_le64(sg->addr); 56 dseg->len = cpu_to_le32(sg->length); 57 } 58 59 /* 60 * mapped-value = 1 + real-value 61 * The hns wr opcode real value is start from 0, In order to distinguish between 62 * initialized and uninitialized map values, we plus 1 to the actual value when 63 * defining the mapping, so that the validity can be identified by checking the 64 * mapped value is greater than 0. 65 */ 66 #define HR_OPC_MAP(ib_key, hr_key) \ 67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 68 69 static const u32 hns_roce_op_code[] = { 70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 72 HR_OPC_MAP(SEND, SEND), 73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 74 HR_OPC_MAP(RDMA_READ, RDMA_READ), 75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 81 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 82 }; 83 84 static u32 to_hr_opcode(u32 ib_opcode) 85 { 86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 87 return HNS_ROCE_V2_WQE_OP_MASK; 88 89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 90 HNS_ROCE_V2_WQE_OP_MASK; 91 } 92 93 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 94 const struct ib_reg_wr *wr) 95 { 96 struct hns_roce_wqe_frmr_seg *fseg = 97 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 98 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 99 u64 pbl_ba; 100 101 /* use ib_access_flags */ 102 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BIND_EN_S, 103 !!(wr->access & IB_ACCESS_MW_BIND)); 104 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_ATOMIC_S, 105 !!(wr->access & IB_ACCESS_REMOTE_ATOMIC)); 106 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RR_S, 107 !!(wr->access & IB_ACCESS_REMOTE_READ)); 108 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_RW_S, 109 !!(wr->access & IB_ACCESS_REMOTE_WRITE)); 110 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_LW_S, 111 !!(wr->access & IB_ACCESS_LOCAL_WRITE)); 112 113 /* Data structure reuse may lead to confusion */ 114 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 115 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 116 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 117 118 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 119 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 120 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 121 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 122 123 fseg->pbl_size = cpu_to_le32(mr->npages); 124 roce_set_field(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, 125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, 126 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 127 roce_set_bit(fseg->byte_40, V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); 128 } 129 130 static void set_atomic_seg(const struct ib_send_wr *wr, 131 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 132 unsigned int valid_num_sge) 133 { 134 struct hns_roce_v2_wqe_data_seg *dseg = 135 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 136 struct hns_roce_wqe_atomic_seg *aseg = 137 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 138 139 set_data_seg_v2(dseg, wr->sg_list); 140 141 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 142 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 143 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 144 } else { 145 aseg->fetchadd_swap_data = 146 cpu_to_le64(atomic_wr(wr)->compare_add); 147 aseg->cmp_data = 0; 148 } 149 150 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 151 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 152 } 153 154 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 155 const struct ib_send_wr *wr, 156 unsigned int *sge_idx, u32 msg_len) 157 { 158 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 159 unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg); 160 unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len; 161 unsigned int left_len_in_pg; 162 unsigned int idx = *sge_idx; 163 unsigned int i = 0; 164 unsigned int len; 165 void *addr; 166 void *dseg; 167 168 if (msg_len > ext_sge_sz) { 169 ibdev_err(ibdev, 170 "no enough extended sge space for inline data.\n"); 171 return -EINVAL; 172 } 173 174 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 175 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 176 len = wr->sg_list[0].length; 177 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 178 179 /* When copying data to extended sge space, the left length in page may 180 * not long enough for current user's sge. So the data should be 181 * splited into several parts, one in the first page, and the others in 182 * the subsequent pages. 183 */ 184 while (1) { 185 if (len <= left_len_in_pg) { 186 memcpy(dseg, addr, len); 187 188 idx += len / dseg_len; 189 190 i++; 191 if (i >= wr->num_sge) 192 break; 193 194 left_len_in_pg -= len; 195 len = wr->sg_list[i].length; 196 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 197 dseg += len; 198 } else { 199 memcpy(dseg, addr, left_len_in_pg); 200 201 len -= left_len_in_pg; 202 addr += left_len_in_pg; 203 idx += left_len_in_pg / dseg_len; 204 dseg = hns_roce_get_extend_sge(qp, 205 idx & (qp->sge.sge_cnt - 1)); 206 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 207 } 208 } 209 210 *sge_idx = idx; 211 212 return 0; 213 } 214 215 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 216 unsigned int *sge_ind, unsigned int cnt) 217 { 218 struct hns_roce_v2_wqe_data_seg *dseg; 219 unsigned int idx = *sge_ind; 220 221 while (cnt > 0) { 222 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 223 if (likely(sge->length)) { 224 set_data_seg_v2(dseg, sge); 225 idx++; 226 cnt--; 227 } 228 sge++; 229 } 230 231 *sge_ind = idx; 232 } 233 234 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 235 { 236 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 237 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 238 239 if (len > qp->max_inline_data || len > mtu) { 240 ibdev_err(&hr_dev->ib_dev, 241 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 242 len, qp->max_inline_data, mtu); 243 return false; 244 } 245 246 return true; 247 } 248 249 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 250 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 251 unsigned int *sge_idx) 252 { 253 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 254 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 255 struct ib_device *ibdev = &hr_dev->ib_dev; 256 unsigned int curr_idx = *sge_idx; 257 void *dseg = rc_sq_wqe; 258 unsigned int i; 259 int ret; 260 261 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 262 ibdev_err(ibdev, "invalid inline parameters!\n"); 263 return -EINVAL; 264 } 265 266 if (!check_inl_data_len(qp, msg_len)) 267 return -EINVAL; 268 269 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 270 271 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1); 272 273 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 274 roce_set_bit(rc_sq_wqe->byte_20, 275 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0); 276 277 for (i = 0; i < wr->num_sge; i++) { 278 memcpy(dseg, ((void *)wr->sg_list[i].addr), 279 wr->sg_list[i].length); 280 dseg += wr->sg_list[i].length; 281 } 282 } else { 283 roce_set_bit(rc_sq_wqe->byte_20, 284 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1); 285 286 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 287 if (ret) 288 return ret; 289 290 roce_set_field(rc_sq_wqe->byte_16, 291 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 292 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, 293 curr_idx - *sge_idx); 294 } 295 296 *sge_idx = curr_idx; 297 298 return 0; 299 } 300 301 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 302 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 303 unsigned int *sge_ind, 304 unsigned int valid_num_sge) 305 { 306 struct hns_roce_v2_wqe_data_seg *dseg = 307 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 308 struct hns_roce_qp *qp = to_hr_qp(ibqp); 309 int j = 0; 310 int i; 311 312 roce_set_field(rc_sq_wqe->byte_20, 313 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 314 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 315 (*sge_ind) & (qp->sge.sge_cnt - 1)); 316 317 if (wr->send_flags & IB_SEND_INLINE) 318 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 319 320 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 321 for (i = 0; i < wr->num_sge; i++) { 322 if (likely(wr->sg_list[i].length)) { 323 set_data_seg_v2(dseg, wr->sg_list + i); 324 dseg++; 325 } 326 } 327 } else { 328 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 329 if (likely(wr->sg_list[i].length)) { 330 set_data_seg_v2(dseg, wr->sg_list + i); 331 dseg++; 332 j++; 333 } 334 } 335 336 set_extend_sge(qp, wr->sg_list + i, sge_ind, 337 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 338 } 339 340 roce_set_field(rc_sq_wqe->byte_16, 341 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 342 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 343 344 return 0; 345 } 346 347 static int check_send_valid(struct hns_roce_dev *hr_dev, 348 struct hns_roce_qp *hr_qp) 349 { 350 struct ib_device *ibdev = &hr_dev->ib_dev; 351 struct ib_qp *ibqp = &hr_qp->ibqp; 352 353 if (unlikely(ibqp->qp_type != IB_QPT_RC && 354 ibqp->qp_type != IB_QPT_GSI && 355 ibqp->qp_type != IB_QPT_UD)) { 356 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 357 ibqp->qp_type); 358 return -EOPNOTSUPP; 359 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 360 hr_qp->state == IB_QPS_INIT || 361 hr_qp->state == IB_QPS_RTR)) { 362 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 363 hr_qp->state); 364 return -EINVAL; 365 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 366 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 367 hr_dev->state); 368 return -EIO; 369 } 370 371 return 0; 372 } 373 374 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 375 unsigned int *sge_len) 376 { 377 unsigned int valid_num = 0; 378 unsigned int len = 0; 379 int i; 380 381 for (i = 0; i < wr->num_sge; i++) { 382 if (likely(wr->sg_list[i].length)) { 383 len += wr->sg_list[i].length; 384 valid_num++; 385 } 386 } 387 388 *sge_len = len; 389 return valid_num; 390 } 391 392 static __le32 get_immtdata(const struct ib_send_wr *wr) 393 { 394 switch (wr->opcode) { 395 case IB_WR_SEND_WITH_IMM: 396 case IB_WR_RDMA_WRITE_WITH_IMM: 397 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 398 default: 399 return 0; 400 } 401 } 402 403 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 404 const struct ib_send_wr *wr) 405 { 406 u32 ib_op = wr->opcode; 407 408 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 409 return -EINVAL; 410 411 ud_sq_wqe->immtdata = get_immtdata(wr); 412 413 roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 414 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 415 416 return 0; 417 } 418 419 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 420 struct hns_roce_ah *ah) 421 { 422 struct ib_device *ib_dev = ah->ibah.device; 423 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 424 425 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 426 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport); 427 428 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 429 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 430 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 431 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 432 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 433 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 434 435 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 436 return -EINVAL; 437 438 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 439 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 440 441 ud_sq_wqe->sgid_index = ah->av.gid_index; 442 443 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 444 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 445 446 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 447 return 0; 448 449 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 450 ah->av.vlan_en); 451 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 452 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 453 454 return 0; 455 } 456 457 static inline int set_ud_wqe(struct hns_roce_qp *qp, 458 const struct ib_send_wr *wr, 459 void *wqe, unsigned int *sge_idx, 460 unsigned int owner_bit) 461 { 462 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 463 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 464 unsigned int curr_idx = *sge_idx; 465 unsigned int valid_num_sge; 466 u32 msg_len = 0; 467 int ret; 468 469 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 470 471 ret = set_ud_opcode(ud_sq_wqe, wr); 472 if (WARN_ON(ret)) 473 return ret; 474 475 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 476 477 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 478 !!(wr->send_flags & IB_SEND_SIGNALED)); 479 480 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 481 !!(wr->send_flags & IB_SEND_SOLICITED)); 482 483 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 484 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 485 486 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 487 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 488 489 roce_set_field(ud_sq_wqe->byte_20, 490 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 491 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 492 curr_idx & (qp->sge.sge_cnt - 1)); 493 494 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 495 qp->qkey : ud_wr(wr)->remote_qkey); 496 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 497 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 498 499 ret = fill_ud_av(ud_sq_wqe, ah); 500 if (ret) 501 return ret; 502 503 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 504 505 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 506 507 /* 508 * The pipeline can sequentially post all valid WQEs into WQ buffer, 509 * including new WQEs waiting for the doorbell to update the PI again. 510 * Therefore, the owner bit of WQE MUST be updated after all fields 511 * and extSGEs have been written into DDR instead of cache. 512 */ 513 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 514 dma_wmb(); 515 516 *sge_idx = curr_idx; 517 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 518 owner_bit); 519 520 return 0; 521 } 522 523 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 525 const struct ib_send_wr *wr) 526 { 527 u32 ib_op = wr->opcode; 528 int ret = 0; 529 530 rc_sq_wqe->immtdata = get_immtdata(wr); 531 532 switch (ib_op) { 533 case IB_WR_RDMA_READ: 534 case IB_WR_RDMA_WRITE: 535 case IB_WR_RDMA_WRITE_WITH_IMM: 536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 538 break; 539 case IB_WR_SEND: 540 case IB_WR_SEND_WITH_IMM: 541 break; 542 case IB_WR_ATOMIC_CMP_AND_SWP: 543 case IB_WR_ATOMIC_FETCH_AND_ADD: 544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 546 break; 547 case IB_WR_REG_MR: 548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 549 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 550 else 551 ret = -EOPNOTSUPP; 552 break; 553 case IB_WR_LOCAL_INV: 554 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 555 fallthrough; 556 case IB_WR_SEND_WITH_INV: 557 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 558 break; 559 default: 560 ret = -EINVAL; 561 } 562 563 if (unlikely(ret)) 564 return ret; 565 566 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 567 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 568 569 return ret; 570 } 571 static inline int set_rc_wqe(struct hns_roce_qp *qp, 572 const struct ib_send_wr *wr, 573 void *wqe, unsigned int *sge_idx, 574 unsigned int owner_bit) 575 { 576 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 577 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 578 unsigned int curr_idx = *sge_idx; 579 unsigned int valid_num_sge; 580 u32 msg_len = 0; 581 int ret; 582 583 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 584 585 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 586 587 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 588 if (WARN_ON(ret)) 589 return ret; 590 591 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 592 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 593 594 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 595 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 596 597 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 598 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 599 600 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 601 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 602 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 603 else if (wr->opcode != IB_WR_REG_MR) 604 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 605 &curr_idx, valid_num_sge); 606 607 /* 608 * The pipeline can sequentially post all valid WQEs into WQ buffer, 609 * including new WQEs waiting for the doorbell to update the PI again. 610 * Therefore, the owner bit of WQE MUST be updated after all fields 611 * and extSGEs have been written into DDR instead of cache. 612 */ 613 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 614 dma_wmb(); 615 616 *sge_idx = curr_idx; 617 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 618 owner_bit); 619 620 return ret; 621 } 622 623 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 624 struct hns_roce_qp *qp) 625 { 626 /* 627 * Hip08 hardware cannot flush the WQEs in SQ if the QP state 628 * gets into errored mode. Hence, as a workaround to this 629 * hardware limitation, driver needs to assist in flushing. But 630 * the flushing operation uses mailbox to convey the QP state to 631 * the hardware and which can sleep due to the mutex protection 632 * around the mailbox calls. Hence, use the deferred flush for 633 * now. 634 */ 635 if (qp->state == IB_QPS_ERR) { 636 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 637 init_flush_work(hr_dev, qp); 638 } else { 639 struct hns_roce_v2_db sq_db = {}; 640 641 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 642 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 643 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 644 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 645 /* indicates data on new BAR, 0 : SQ doorbell, 1 : DWQE */ 646 roce_set_bit(sq_db.byte_4, V2_DB_FLAG_S, 0); 647 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, 648 V2_DB_PARAMETER_IDX_S, qp->sq.head); 649 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 650 V2_DB_PARAMETER_SL_S, qp->sl); 651 652 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l); 653 } 654 } 655 656 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 657 u64 __iomem *dest) 658 { 659 #define HNS_ROCE_WRITE_TIMES 8 660 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 661 struct hnae3_handle *handle = priv->handle; 662 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 663 int i; 664 665 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 666 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 667 writeq_relaxed(*(val + i), dest + i); 668 } 669 670 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 671 void *wqe) 672 { 673 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 674 675 /* All kinds of DirectWQE have the same header field layout */ 676 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); 677 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, 678 V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); 679 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, 680 V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); 681 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, 682 V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); 683 684 hns_roce_write512(hr_dev, wqe, hr_dev->mem_base + 685 HNS_ROCE_DWQE_SIZE * qp->ibqp.qp_num); 686 } 687 688 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 689 const struct ib_send_wr *wr, 690 const struct ib_send_wr **bad_wr) 691 { 692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 693 struct ib_device *ibdev = &hr_dev->ib_dev; 694 struct hns_roce_qp *qp = to_hr_qp(ibqp); 695 unsigned long flags = 0; 696 unsigned int owner_bit; 697 unsigned int sge_idx; 698 unsigned int wqe_idx; 699 void *wqe = NULL; 700 u32 nreq; 701 int ret; 702 703 spin_lock_irqsave(&qp->sq.lock, flags); 704 705 ret = check_send_valid(hr_dev, qp); 706 if (unlikely(ret)) { 707 *bad_wr = wr; 708 nreq = 0; 709 goto out; 710 } 711 712 sge_idx = qp->next_sge; 713 714 for (nreq = 0; wr; ++nreq, wr = wr->next) { 715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 716 ret = -ENOMEM; 717 *bad_wr = wr; 718 goto out; 719 } 720 721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 722 723 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 725 wr->num_sge, qp->sq.max_gs); 726 ret = -EINVAL; 727 *bad_wr = wr; 728 goto out; 729 } 730 731 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 732 qp->sq.wrid[wqe_idx] = wr->wr_id; 733 owner_bit = 734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 735 736 /* Corresponding to the QP type, wqe process separately */ 737 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 738 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 else if (ibqp->qp_type == IB_QPT_RC) 740 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 742 if (unlikely(ret)) { 743 *bad_wr = wr; 744 goto out; 745 } 746 } 747 748 out: 749 if (likely(nreq)) { 750 qp->sq.head += nreq; 751 qp->next_sge = sge_idx; 752 753 if (nreq == 1 && qp->sq.head == qp->sq.tail + 1 && 754 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 755 write_dwqe(hr_dev, qp, wqe); 756 else 757 update_sq_db(hr_dev, qp); 758 } 759 760 spin_unlock_irqrestore(&qp->sq.lock, flags); 761 762 return ret; 763 } 764 765 static int check_recv_valid(struct hns_roce_dev *hr_dev, 766 struct hns_roce_qp *hr_qp) 767 { 768 struct ib_device *ibdev = &hr_dev->ib_dev; 769 struct ib_qp *ibqp = &hr_qp->ibqp; 770 771 if (unlikely(ibqp->qp_type != IB_QPT_RC && 772 ibqp->qp_type != IB_QPT_GSI && 773 ibqp->qp_type != IB_QPT_UD)) { 774 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 775 ibqp->qp_type); 776 return -EOPNOTSUPP; 777 } 778 779 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 780 return -EIO; 781 782 if (hr_qp->state == IB_QPS_RESET) 783 return -EINVAL; 784 785 return 0; 786 } 787 788 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 789 u32 max_sge, bool rsv) 790 { 791 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 792 u32 i, cnt; 793 794 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 795 /* Skip zero-length sge */ 796 if (!wr->sg_list[i].length) 797 continue; 798 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 799 cnt++; 800 } 801 802 /* Fill a reserved sge to make hw stop reading remaining segments */ 803 if (rsv) { 804 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 805 dseg[cnt].addr = 0; 806 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 807 } else { 808 /* Clear remaining segments to make ROCEE ignore sges */ 809 if (cnt < max_sge) 810 memset(dseg + cnt, 0, 811 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 812 } 813 } 814 815 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 816 u32 wqe_idx, u32 max_sge) 817 { 818 struct hns_roce_rinl_sge *sge_list; 819 void *wqe = NULL; 820 u32 i; 821 822 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 823 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 824 825 /* rq support inline data */ 826 if (hr_qp->rq_inl_buf.wqe_cnt) { 827 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 828 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 829 for (i = 0; i < wr->num_sge; i++) { 830 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 831 sge_list[i].len = wr->sg_list[i].length; 832 } 833 } 834 } 835 836 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 837 const struct ib_recv_wr *wr, 838 const struct ib_recv_wr **bad_wr) 839 { 840 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 841 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 842 struct ib_device *ibdev = &hr_dev->ib_dev; 843 u32 wqe_idx, nreq, max_sge; 844 unsigned long flags; 845 int ret; 846 847 spin_lock_irqsave(&hr_qp->rq.lock, flags); 848 849 ret = check_recv_valid(hr_dev, hr_qp); 850 if (unlikely(ret)) { 851 *bad_wr = wr; 852 nreq = 0; 853 goto out; 854 } 855 856 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 857 for (nreq = 0; wr; ++nreq, wr = wr->next) { 858 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 859 hr_qp->ibqp.recv_cq))) { 860 ret = -ENOMEM; 861 *bad_wr = wr; 862 goto out; 863 } 864 865 if (unlikely(wr->num_sge > max_sge)) { 866 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 867 wr->num_sge, max_sge); 868 ret = -EINVAL; 869 *bad_wr = wr; 870 goto out; 871 } 872 873 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 874 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 875 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 876 } 877 878 out: 879 if (likely(nreq)) { 880 hr_qp->rq.head += nreq; 881 882 /* 883 * Hip08 hardware cannot flush the WQEs in RQ if the QP state 884 * gets into errored mode. Hence, as a workaround to this 885 * hardware limitation, driver needs to assist in flushing. But 886 * the flushing operation uses mailbox to convey the QP state to 887 * the hardware and which can sleep due to the mutex protection 888 * around the mailbox calls. Hence, use the deferred flush for 889 * now. 890 */ 891 if (hr_qp->state == IB_QPS_ERR) { 892 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, 893 &hr_qp->flush_flag)) 894 init_flush_work(hr_dev, hr_qp); 895 } else { 896 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 897 } 898 } 899 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 900 901 return ret; 902 } 903 904 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 905 { 906 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 907 } 908 909 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 910 { 911 return hns_roce_buf_offset(idx_que->mtr.kmem, 912 n << idx_que->entry_shift); 913 } 914 915 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 916 { 917 /* always called with interrupts disabled. */ 918 spin_lock(&srq->lock); 919 920 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 921 srq->idx_que.tail++; 922 923 spin_unlock(&srq->lock); 924 } 925 926 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 927 { 928 struct hns_roce_idx_que *idx_que = &srq->idx_que; 929 930 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 931 } 932 933 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 934 const struct ib_recv_wr *wr) 935 { 936 struct ib_device *ib_dev = srq->ibsrq.device; 937 938 if (unlikely(wr->num_sge > max_sge)) { 939 ibdev_err(ib_dev, 940 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 941 wr->num_sge, max_sge); 942 return -EINVAL; 943 } 944 945 if (unlikely(hns_roce_srqwq_overflow(srq))) { 946 ibdev_err(ib_dev, 947 "failed to check srqwq status, srqwq is full.\n"); 948 return -ENOMEM; 949 } 950 951 return 0; 952 } 953 954 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 955 { 956 struct hns_roce_idx_que *idx_que = &srq->idx_que; 957 u32 pos; 958 959 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 960 if (unlikely(pos == srq->wqe_cnt)) 961 return -ENOSPC; 962 963 bitmap_set(idx_que->bitmap, pos, 1); 964 *wqe_idx = pos; 965 return 0; 966 } 967 968 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 969 { 970 struct hns_roce_idx_que *idx_que = &srq->idx_que; 971 unsigned int head; 972 __le32 *buf; 973 974 head = idx_que->head & (srq->wqe_cnt - 1); 975 976 buf = get_idx_buf(idx_que, head); 977 *buf = cpu_to_le32(wqe_idx); 978 979 idx_que->head++; 980 } 981 982 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 983 const struct ib_recv_wr *wr, 984 const struct ib_recv_wr **bad_wr) 985 { 986 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 987 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 988 struct hns_roce_v2_db srq_db; 989 unsigned long flags; 990 int ret = 0; 991 u32 max_sge; 992 u32 wqe_idx; 993 void *wqe; 994 u32 nreq; 995 996 spin_lock_irqsave(&srq->lock, flags); 997 998 max_sge = srq->max_gs - srq->rsv_sge; 999 for (nreq = 0; wr; ++nreq, wr = wr->next) { 1000 ret = check_post_srq_valid(srq, max_sge, wr); 1001 if (ret) { 1002 *bad_wr = wr; 1003 break; 1004 } 1005 1006 ret = get_srq_wqe_idx(srq, &wqe_idx); 1007 if (unlikely(ret)) { 1008 *bad_wr = wr; 1009 break; 1010 } 1011 1012 wqe = get_srq_wqe_buf(srq, wqe_idx); 1013 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1014 fill_wqe_idx(srq, wqe_idx); 1015 srq->wrid[wqe_idx] = wr->wr_id; 1016 } 1017 1018 if (likely(nreq)) { 1019 srq_db.byte_4 = 1020 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S | 1021 (srq->srqn & V2_DB_BYTE_4_TAG_M)); 1022 srq_db.parameter = 1023 cpu_to_le32(srq->idx_que.head & V2_DB_PARAMETER_IDX_M); 1024 1025 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l); 1026 } 1027 1028 spin_unlock_irqrestore(&srq->lock, flags); 1029 1030 return ret; 1031 } 1032 1033 static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1034 unsigned long instance_stage, 1035 unsigned long reset_stage) 1036 { 1037 /* When hardware reset has been completed once or more, we should stop 1038 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1039 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1040 * stage of soft reset process, we should exit with error, and then 1041 * HNAE3_INIT_CLIENT related process can rollback the operation like 1042 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1043 * process will exit with error to notify NIC driver to reschedule soft 1044 * reset process once again. 1045 */ 1046 hr_dev->is_reset = true; 1047 hr_dev->dis_db = true; 1048 1049 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1050 instance_stage == HNS_ROCE_STATE_INIT) 1051 return CMD_RST_PRC_EBUSY; 1052 1053 return CMD_RST_PRC_SUCCESS; 1054 } 1055 1056 static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1057 unsigned long instance_stage, 1058 unsigned long reset_stage) 1059 { 1060 struct hns_roce_v2_priv *priv = hr_dev->priv; 1061 struct hnae3_handle *handle = priv->handle; 1062 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1063 1064 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1065 * doorbell to hardware. If now in .init_instance() function, we should 1066 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1067 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1068 * related process can rollback the operation like notifing hardware to 1069 * free resources, HNAE3_INIT_CLIENT related process will exit with 1070 * error to notify NIC driver to reschedule soft reset process once 1071 * again. 1072 */ 1073 hr_dev->dis_db = true; 1074 if (!ops->get_hw_reset_stat(handle)) 1075 hr_dev->is_reset = true; 1076 1077 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1078 instance_stage == HNS_ROCE_STATE_INIT) 1079 return CMD_RST_PRC_EBUSY; 1080 1081 return CMD_RST_PRC_SUCCESS; 1082 } 1083 1084 static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1085 { 1086 struct hns_roce_v2_priv *priv = hr_dev->priv; 1087 struct hnae3_handle *handle = priv->handle; 1088 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1089 1090 /* When software reset is detected at .init_instance() function, we 1091 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1092 * with error. 1093 */ 1094 hr_dev->dis_db = true; 1095 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1096 hr_dev->is_reset = true; 1097 1098 return CMD_RST_PRC_EBUSY; 1099 } 1100 1101 static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev) 1102 { 1103 struct hns_roce_v2_priv *priv = hr_dev->priv; 1104 struct hnae3_handle *handle = priv->handle; 1105 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1106 unsigned long instance_stage; /* the current instance stage */ 1107 unsigned long reset_stage; /* the current reset stage */ 1108 unsigned long reset_cnt; 1109 bool sw_resetting; 1110 bool hw_resetting; 1111 1112 if (hr_dev->is_reset) 1113 return CMD_RST_PRC_SUCCESS; 1114 1115 /* Get information about reset from NIC driver or RoCE driver itself, 1116 * the meaning of the following variables from NIC driver are described 1117 * as below: 1118 * reset_cnt -- The count value of completed hardware reset. 1119 * hw_resetting -- Whether hardware device is resetting now. 1120 * sw_resetting -- Whether NIC's software reset process is running now. 1121 */ 1122 instance_stage = handle->rinfo.instance_state; 1123 reset_stage = handle->rinfo.reset_state; 1124 reset_cnt = ops->ae_dev_reset_cnt(handle); 1125 hw_resetting = ops->get_cmdq_stat(handle); 1126 sw_resetting = ops->ae_dev_resetting(handle); 1127 1128 if (reset_cnt != hr_dev->reset_cnt) 1129 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1130 reset_stage); 1131 else if (hw_resetting) 1132 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1133 reset_stage); 1134 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1135 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1136 1137 return 0; 1138 } 1139 1140 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1141 struct hns_roce_v2_cmq_ring *ring) 1142 { 1143 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1144 1145 ring->desc = kzalloc(size, GFP_KERNEL); 1146 if (!ring->desc) 1147 return -ENOMEM; 1148 1149 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 1150 DMA_BIDIRECTIONAL); 1151 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 1152 ring->desc_dma_addr = 0; 1153 kfree(ring->desc); 1154 ring->desc = NULL; 1155 return -ENOMEM; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_v2_cmq_ring *ring) 1163 { 1164 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 1165 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1166 DMA_BIDIRECTIONAL); 1167 1168 ring->desc_dma_addr = 0; 1169 kfree(ring->desc); 1170 } 1171 1172 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 1173 { 1174 struct hns_roce_v2_priv *priv = hr_dev->priv; 1175 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 1176 &priv->cmq.csq : &priv->cmq.crq; 1177 1178 ring->flag = ring_type; 1179 ring->head = 0; 1180 1181 return hns_roce_alloc_cmq_desc(hr_dev, ring); 1182 } 1183 1184 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 1185 { 1186 struct hns_roce_v2_priv *priv = hr_dev->priv; 1187 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 1188 &priv->cmq.csq : &priv->cmq.crq; 1189 dma_addr_t dma = ring->desc_dma_addr; 1190 1191 if (ring_type == TYPE_CSQ) { 1192 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 1193 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 1194 upper_32_bits(dma)); 1195 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1196 (u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1197 1198 /* Make sure to write tail first and then head */ 1199 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 1200 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 1201 } else { 1202 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 1203 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 1204 upper_32_bits(dma)); 1205 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 1206 (u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1207 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 1208 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 1209 } 1210 } 1211 1212 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1213 { 1214 struct hns_roce_v2_priv *priv = hr_dev->priv; 1215 int ret; 1216 1217 /* Setup the queue entries for command queue */ 1218 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; 1219 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; 1220 1221 /* Setup the lock for command queue */ 1222 spin_lock_init(&priv->cmq.csq.lock); 1223 spin_lock_init(&priv->cmq.crq.lock); 1224 1225 /* Setup Tx write back timeout */ 1226 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1227 1228 /* Init CSQ */ 1229 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 1230 if (ret) { 1231 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 1232 return ret; 1233 } 1234 1235 /* Init CRQ */ 1236 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 1237 if (ret) { 1238 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 1239 goto err_crq; 1240 } 1241 1242 /* Init CSQ REG */ 1243 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 1244 1245 /* Init CRQ REG */ 1246 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 1247 1248 return 0; 1249 1250 err_crq: 1251 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1252 1253 return ret; 1254 } 1255 1256 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1257 { 1258 struct hns_roce_v2_priv *priv = hr_dev->priv; 1259 1260 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1261 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 1262 } 1263 1264 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1265 enum hns_roce_opcode_type opcode, 1266 bool is_read) 1267 { 1268 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1269 desc->opcode = cpu_to_le16(opcode); 1270 desc->flag = 1271 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1272 if (is_read) 1273 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1274 else 1275 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1276 } 1277 1278 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1279 { 1280 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG); 1281 struct hns_roce_v2_priv *priv = hr_dev->priv; 1282 1283 return tail == priv->cmq.csq.head; 1284 } 1285 1286 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1287 struct hns_roce_cmq_desc *desc, int num) 1288 { 1289 struct hns_roce_v2_priv *priv = hr_dev->priv; 1290 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1291 u32 timeout = 0; 1292 u16 desc_ret; 1293 u32 tail; 1294 int ret; 1295 int i; 1296 1297 spin_lock_bh(&csq->lock); 1298 1299 tail = csq->head; 1300 1301 for (i = 0; i < num; i++) { 1302 csq->desc[csq->head++] = desc[i]; 1303 if (csq->head == csq->desc_num) 1304 csq->head = 0; 1305 } 1306 1307 /* Write to hardware */ 1308 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, csq->head); 1309 1310 /* If the command is sync, wait for the firmware to write back, 1311 * if multi descriptors to be sent, use the first one to check 1312 */ 1313 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 1314 do { 1315 if (hns_roce_cmq_csq_done(hr_dev)) 1316 break; 1317 udelay(1); 1318 } while (++timeout < priv->cmq.tx_timeout); 1319 } 1320 1321 if (hns_roce_cmq_csq_done(hr_dev)) { 1322 for (ret = 0, i = 0; i < num; i++) { 1323 /* check the result of hardware write back */ 1324 desc[i] = csq->desc[tail++]; 1325 if (tail == csq->desc_num) 1326 tail = 0; 1327 1328 desc_ret = le16_to_cpu(desc[i].retval); 1329 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1330 continue; 1331 1332 dev_err_ratelimited(hr_dev->dev, 1333 "Cmdq IO error, opcode = %x, return = %x\n", 1334 desc->opcode, desc_ret); 1335 ret = -EIO; 1336 } 1337 } else { 1338 /* FW/HW reset or incorrect number of desc */ 1339 tail = roce_read(hr_dev, ROCEE_TX_CMQ_TAIL_REG); 1340 dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n", 1341 csq->head, tail); 1342 csq->head = tail; 1343 1344 ret = -EAGAIN; 1345 } 1346 1347 spin_unlock_bh(&csq->lock); 1348 1349 return ret; 1350 } 1351 1352 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1353 struct hns_roce_cmq_desc *desc, int num) 1354 { 1355 int retval; 1356 int ret; 1357 1358 ret = hns_roce_v2_rst_process_cmd(hr_dev); 1359 if (ret == CMD_RST_PRC_SUCCESS) 1360 return 0; 1361 if (ret == CMD_RST_PRC_EBUSY) 1362 return -EBUSY; 1363 1364 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1365 if (ret) { 1366 retval = hns_roce_v2_rst_process_cmd(hr_dev); 1367 if (retval == CMD_RST_PRC_SUCCESS) 1368 return 0; 1369 else if (retval == CMD_RST_PRC_EBUSY) 1370 return -EBUSY; 1371 } 1372 1373 return ret; 1374 } 1375 1376 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1377 { 1378 struct hns_roce_query_version *resp; 1379 struct hns_roce_cmq_desc desc; 1380 int ret; 1381 1382 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1383 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1384 if (ret) 1385 return ret; 1386 1387 resp = (struct hns_roce_query_version *)desc.data; 1388 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1389 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1390 1391 return 0; 1392 } 1393 1394 static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev) 1395 { 1396 struct hns_roce_v2_priv *priv = hr_dev->priv; 1397 struct hnae3_handle *handle = priv->handle; 1398 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1399 unsigned long reset_cnt; 1400 bool sw_resetting; 1401 bool hw_resetting; 1402 1403 reset_cnt = ops->ae_dev_reset_cnt(handle); 1404 hw_resetting = ops->get_hw_reset_stat(handle); 1405 sw_resetting = ops->ae_dev_resetting(handle); 1406 1407 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting) 1408 return true; 1409 1410 return false; 1411 } 1412 1413 static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval, 1414 int flag) 1415 { 1416 struct hns_roce_v2_priv *priv = hr_dev->priv; 1417 struct hnae3_handle *handle = priv->handle; 1418 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1419 unsigned long instance_stage; 1420 unsigned long reset_cnt; 1421 unsigned long end; 1422 bool sw_resetting; 1423 bool hw_resetting; 1424 1425 instance_stage = handle->rinfo.instance_state; 1426 reset_cnt = ops->ae_dev_reset_cnt(handle); 1427 hw_resetting = ops->get_hw_reset_stat(handle); 1428 sw_resetting = ops->ae_dev_resetting(handle); 1429 1430 if (reset_cnt != hr_dev->reset_cnt) { 1431 hr_dev->dis_db = true; 1432 hr_dev->is_reset = true; 1433 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1434 } else if (hw_resetting) { 1435 hr_dev->dis_db = true; 1436 1437 dev_warn(hr_dev->dev, 1438 "Func clear is pending, device in resetting state.\n"); 1439 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1440 while (end) { 1441 if (!ops->get_hw_reset_stat(handle)) { 1442 hr_dev->is_reset = true; 1443 dev_info(hr_dev->dev, 1444 "Func clear success after reset.\n"); 1445 return; 1446 } 1447 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1448 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1449 } 1450 1451 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1452 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) { 1453 hr_dev->dis_db = true; 1454 1455 dev_warn(hr_dev->dev, 1456 "Func clear is pending, device in resetting state.\n"); 1457 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1458 while (end) { 1459 if (ops->ae_dev_reset_cnt(handle) != 1460 hr_dev->reset_cnt) { 1461 hr_dev->is_reset = true; 1462 dev_info(hr_dev->dev, 1463 "Func clear success after sw reset\n"); 1464 return; 1465 } 1466 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1467 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1468 } 1469 1470 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1471 } else { 1472 if (retval && !flag) 1473 dev_warn(hr_dev->dev, 1474 "Func clear read failed, ret = %d.\n", retval); 1475 1476 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1477 } 1478 } 1479 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1480 { 1481 bool fclr_write_fail_flag = false; 1482 struct hns_roce_func_clear *resp; 1483 struct hns_roce_cmq_desc desc; 1484 unsigned long end; 1485 int ret = 0; 1486 1487 if (hns_roce_func_clr_chk_rst(hr_dev)) 1488 goto out; 1489 1490 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1491 resp = (struct hns_roce_func_clear *)desc.data; 1492 1493 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1494 if (ret) { 1495 fclr_write_fail_flag = true; 1496 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1497 ret); 1498 goto out; 1499 } 1500 1501 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1502 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1503 while (end) { 1504 if (hns_roce_func_clr_chk_rst(hr_dev)) 1505 goto out; 1506 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1507 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1508 1509 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1510 true); 1511 1512 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1513 if (ret) 1514 continue; 1515 1516 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1517 hr_dev->is_reset = true; 1518 return; 1519 } 1520 } 1521 1522 out: 1523 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag); 1524 } 1525 1526 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1527 { 1528 struct hns_roce_query_fw_info *resp; 1529 struct hns_roce_cmq_desc desc; 1530 int ret; 1531 1532 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1533 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1534 if (ret) 1535 return ret; 1536 1537 resp = (struct hns_roce_query_fw_info *)desc.data; 1538 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1539 1540 return 0; 1541 } 1542 1543 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1544 { 1545 struct hns_roce_cfg_global_param *req; 1546 struct hns_roce_cmq_desc desc; 1547 1548 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1549 false); 1550 1551 req = (struct hns_roce_cfg_global_param *)desc.data; 1552 memset(req, 0, sizeof(*req)); 1553 roce_set_field(req->time_cfg_udp_port, 1554 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 1555 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 1556 roce_set_field(req->time_cfg_udp_port, 1557 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 1558 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 1559 ROCE_V2_UDP_DPORT); 1560 1561 return hns_roce_cmq_send(hr_dev, &desc, 1); 1562 } 1563 1564 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1565 { 1566 struct hns_roce_cmq_desc desc[2]; 1567 struct hns_roce_pf_res_a *req_a; 1568 struct hns_roce_pf_res_b *req_b; 1569 int ret; 1570 1571 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_QUERY_PF_RES, 1572 true); 1573 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1574 1575 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_QUERY_PF_RES, 1576 true); 1577 1578 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1579 if (ret) 1580 return ret; 1581 1582 req_a = (struct hns_roce_pf_res_a *)desc[0].data; 1583 req_b = (struct hns_roce_pf_res_b *)desc[1].data; 1584 1585 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, 1586 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 1587 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 1588 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, 1589 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 1590 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 1591 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, 1592 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 1593 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 1594 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, 1595 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 1596 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 1597 1598 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, 1599 PF_RES_DATA_3_PF_SL_NUM_M, 1600 PF_RES_DATA_3_PF_SL_NUM_S); 1601 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, 1602 PF_RES_DATA_4_PF_SCCC_BT_NUM_M, 1603 PF_RES_DATA_4_PF_SCCC_BT_NUM_S); 1604 1605 hr_dev->caps.gmv_bt_num = roce_get_field(req_b->gmv_idx_num, 1606 PF_RES_DATA_5_PF_GMV_BT_NUM_M, 1607 PF_RES_DATA_5_PF_GMV_BT_NUM_S); 1608 1609 return 0; 1610 } 1611 1612 static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev) 1613 { 1614 struct hns_roce_pf_timer_res_a *req_a; 1615 struct hns_roce_cmq_desc desc; 1616 int ret; 1617 1618 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1619 true); 1620 1621 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1622 if (ret) 1623 return ret; 1624 1625 req_a = (struct hns_roce_pf_timer_res_a *)desc.data; 1626 1627 hr_dev->caps.qpc_timer_bt_num = 1628 roce_get_field(req_a->qpc_timer_bt_idx_num, 1629 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M, 1630 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S); 1631 hr_dev->caps.cqc_timer_bt_num = 1632 roce_get_field(req_a->cqc_timer_bt_idx_num, 1633 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M, 1634 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S); 1635 1636 return 0; 1637 } 1638 1639 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) 1640 { 1641 struct hns_roce_cmq_desc desc; 1642 struct hns_roce_vf_switch *swt; 1643 int ret; 1644 1645 swt = (struct hns_roce_vf_switch *)desc.data; 1646 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1647 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1648 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1649 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1650 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1651 if (ret) 1652 return ret; 1653 1654 desc.flag = 1655 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1656 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1657 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1658 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1659 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1660 1661 return hns_roce_cmq_send(hr_dev, &desc, 1); 1662 } 1663 1664 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1665 { 1666 struct hns_roce_cmq_desc desc[2]; 1667 struct hns_roce_vf_res_a *req_a; 1668 struct hns_roce_vf_res_b *req_b; 1669 1670 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 1671 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 1672 1673 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_ALLOC_VF_RES, 1674 false); 1675 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1676 1677 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_ALLOC_VF_RES, 1678 false); 1679 1680 roce_set_field(req_a->vf_qpc_bt_idx_num, 1681 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 1682 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 1683 roce_set_field(req_a->vf_qpc_bt_idx_num, 1684 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 1685 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM); 1686 1687 roce_set_field(req_a->vf_srqc_bt_idx_num, 1688 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 1689 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 1690 roce_set_field(req_a->vf_srqc_bt_idx_num, 1691 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 1692 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 1693 HNS_ROCE_VF_SRQC_BT_NUM); 1694 1695 roce_set_field(req_a->vf_cqc_bt_idx_num, 1696 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 1697 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 1698 roce_set_field(req_a->vf_cqc_bt_idx_num, 1699 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 1700 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM); 1701 1702 roce_set_field(req_a->vf_mpt_bt_idx_num, 1703 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 1704 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 1705 roce_set_field(req_a->vf_mpt_bt_idx_num, 1706 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 1707 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM); 1708 1709 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M, 1710 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 1711 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M, 1712 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM); 1713 1714 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M, 1715 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 1716 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M, 1717 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM); 1718 1719 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M, 1720 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1721 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M, 1722 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM); 1723 1724 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M, 1725 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1726 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M, 1727 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM); 1728 1729 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M, 1730 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0); 1731 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M, 1732 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S, 1733 HNS_ROCE_VF_SCCC_BT_NUM); 1734 1735 return hns_roce_cmq_send(hr_dev, desc, 2); 1736 } 1737 1738 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1739 { 1740 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1741 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1742 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1743 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1744 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num; 1745 struct hns_roce_cfg_bt_attr *req; 1746 struct hns_roce_cmq_desc desc; 1747 1748 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1749 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1750 memset(req, 0, sizeof(*req)); 1751 1752 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1753 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1754 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1755 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1756 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1757 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1758 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1759 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1760 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1761 1762 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1763 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1764 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1765 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1766 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1767 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1768 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1769 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1770 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1771 1772 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1773 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1774 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1775 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1776 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1777 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1778 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1779 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1780 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1781 1782 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1783 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1784 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1785 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1786 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1787 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1788 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1789 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1790 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1791 1792 roce_set_field(req->vf_sccc_cfg, 1793 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M, 1794 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S, 1795 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1796 roce_set_field(req->vf_sccc_cfg, 1797 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M, 1798 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S, 1799 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1800 roce_set_field(req->vf_sccc_cfg, 1801 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M, 1802 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S, 1803 sccc_hop_num == 1804 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num); 1805 1806 return hns_roce_cmq_send(hr_dev, &desc, 1); 1807 } 1808 1809 static void set_default_caps(struct hns_roce_dev *hr_dev) 1810 { 1811 struct hns_roce_caps *caps = &hr_dev->caps; 1812 1813 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1814 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1815 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1816 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1817 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1818 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1819 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1820 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1821 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1822 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1823 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1824 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1825 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1826 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1827 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1828 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1829 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1830 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1831 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1832 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1833 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1834 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1835 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1836 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1837 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1838 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1839 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 1840 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1841 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1842 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1843 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1844 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1845 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1846 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1847 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 1848 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1849 caps->reserved_lkey = 0; 1850 caps->reserved_pds = 0; 1851 caps->reserved_mrws = 1; 1852 caps->reserved_uars = 0; 1853 caps->reserved_cqs = 0; 1854 caps->reserved_srqs = 0; 1855 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1856 1857 caps->qpc_ba_pg_sz = 0; 1858 caps->qpc_buf_pg_sz = 0; 1859 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1860 caps->srqc_ba_pg_sz = 0; 1861 caps->srqc_buf_pg_sz = 0; 1862 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1863 caps->cqc_ba_pg_sz = 0; 1864 caps->cqc_buf_pg_sz = 0; 1865 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1866 caps->mpt_ba_pg_sz = 0; 1867 caps->mpt_buf_pg_sz = 0; 1868 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1869 caps->mtt_ba_pg_sz = 0; 1870 caps->mtt_buf_pg_sz = 0; 1871 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1872 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1873 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1874 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1875 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 1876 caps->cqe_buf_pg_sz = 0; 1877 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1878 caps->srqwqe_ba_pg_sz = 0; 1879 caps->srqwqe_buf_pg_sz = 0; 1880 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1881 caps->idx_ba_pg_sz = 0; 1882 caps->idx_buf_pg_sz = 0; 1883 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1884 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1885 1886 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1887 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1888 HNS_ROCE_CAP_FLAG_RECORD_DB | 1889 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; 1890 1891 caps->pkey_table_len[0] = 1; 1892 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1893 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1894 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1895 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 1896 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 1897 caps->local_ca_ack_delay = 0; 1898 caps->max_mtu = IB_MTU_4096; 1899 1900 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1901 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1902 1903 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1904 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1905 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; 1906 1907 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1908 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1909 caps->qpc_timer_ba_pg_sz = 0; 1910 caps->qpc_timer_buf_pg_sz = 0; 1911 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1912 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1913 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1914 caps->cqc_timer_ba_pg_sz = 0; 1915 caps->cqc_timer_buf_pg_sz = 0; 1916 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1917 1918 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 1919 caps->sccc_ba_pg_sz = 0; 1920 caps->sccc_buf_pg_sz = 0; 1921 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1922 1923 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1924 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 1925 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 1926 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 1927 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 1928 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 1929 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 1930 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 1931 caps->gmv_entry_sz); 1932 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 1933 caps->gmv_ba_pg_sz = 0; 1934 caps->gmv_buf_pg_sz = 0; 1935 caps->gid_table_len[0] = caps->gmv_bt_num * (HNS_HW_PAGE_SIZE / 1936 caps->gmv_entry_sz); 1937 } 1938 } 1939 1940 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1941 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1942 { 1943 u64 obj_per_chunk; 1944 u64 bt_chunk_size = PAGE_SIZE; 1945 u64 buf_chunk_size = PAGE_SIZE; 1946 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1947 1948 *buf_page_size = 0; 1949 *bt_page_size = 0; 1950 1951 switch (hop_num) { 1952 case 3: 1953 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1954 (bt_chunk_size / BA_BYTE_LEN) * 1955 (bt_chunk_size / BA_BYTE_LEN) * 1956 obj_per_chunk_default; 1957 break; 1958 case 2: 1959 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1960 (bt_chunk_size / BA_BYTE_LEN) * 1961 obj_per_chunk_default; 1962 break; 1963 case 1: 1964 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1965 obj_per_chunk_default; 1966 break; 1967 case HNS_ROCE_HOP_NUM_0: 1968 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1969 break; 1970 default: 1971 pr_err("table %u not support hop_num = %u!\n", hem_type, 1972 hop_num); 1973 return; 1974 } 1975 1976 if (hem_type >= HEM_TYPE_MTT) 1977 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1978 else 1979 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1980 } 1981 1982 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 1983 { 1984 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 1985 struct hns_roce_caps *caps = &hr_dev->caps; 1986 struct hns_roce_query_pf_caps_a *resp_a; 1987 struct hns_roce_query_pf_caps_b *resp_b; 1988 struct hns_roce_query_pf_caps_c *resp_c; 1989 struct hns_roce_query_pf_caps_d *resp_d; 1990 struct hns_roce_query_pf_caps_e *resp_e; 1991 int ctx_hop_num; 1992 int pbl_hop_num; 1993 int ret; 1994 int i; 1995 1996 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 1997 hns_roce_cmq_setup_basic_desc(&desc[i], 1998 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 1999 true); 2000 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2001 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2002 else 2003 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2004 } 2005 2006 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2007 if (ret) 2008 return ret; 2009 2010 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2011 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2012 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2013 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2014 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2015 2016 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2017 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2018 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2019 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2020 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2021 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 2022 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 2023 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 2024 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2025 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2026 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2027 caps->num_other_vectors = resp_a->num_other_vectors; 2028 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2029 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2030 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 2031 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2032 2033 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2034 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2035 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2036 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2037 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2038 caps->idx_entry_sz = resp_b->idx_entry_sz; 2039 caps->sccc_sz = resp_b->sccc_sz; 2040 caps->max_mtu = resp_b->max_mtu; 2041 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2042 caps->min_cqes = resp_b->min_cqes; 2043 caps->min_wqes = resp_b->min_wqes; 2044 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2045 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2046 caps->phy_num_uars = resp_b->phy_num_uars; 2047 ctx_hop_num = resp_b->ctx_hop_num; 2048 pbl_hop_num = resp_b->pbl_hop_num; 2049 2050 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 2051 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 2052 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 2053 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 2054 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 2055 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 2056 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2057 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2058 2059 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 2060 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 2061 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 2062 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 2063 V2_QUERY_PF_CAPS_C_MAX_GID_M, 2064 V2_QUERY_PF_CAPS_C_MAX_GID_S); 2065 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 2066 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 2067 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 2068 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 2069 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 2070 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 2071 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 2072 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 2073 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 2074 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 2075 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 2076 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 2077 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2078 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2079 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 2080 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 2081 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 2082 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2083 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 2084 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 2085 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 2086 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 2087 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 2088 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 2089 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 2090 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 2091 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 2092 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2093 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 2094 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 2095 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2096 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 2097 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 2098 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 2099 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 2100 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 2101 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 2102 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 2103 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 2104 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 2105 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 2106 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 2107 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 2108 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 2109 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 2110 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2111 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 2112 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 2113 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2114 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 2115 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 2116 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 2117 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 2118 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 2119 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 2120 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 2121 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 2122 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 2123 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 2124 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 2125 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2126 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2127 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2128 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2129 2130 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2131 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2132 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2133 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 2134 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2135 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2136 caps->mtt_ba_pg_sz = 0; 2137 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 2138 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2139 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2140 2141 caps->qpc_hop_num = ctx_hop_num; 2142 caps->srqc_hop_num = ctx_hop_num; 2143 caps->cqc_hop_num = ctx_hop_num; 2144 caps->mpt_hop_num = ctx_hop_num; 2145 caps->mtt_hop_num = pbl_hop_num; 2146 caps->cqe_hop_num = pbl_hop_num; 2147 caps->srqwqe_hop_num = pbl_hop_num; 2148 caps->idx_hop_num = pbl_hop_num; 2149 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2150 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 2151 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 2152 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2153 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 2154 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 2155 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2156 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 2157 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 2158 2159 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2160 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2161 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2162 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2163 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2164 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2165 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2166 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2167 caps->gmv_entry_sz); 2168 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2169 caps->gmv_ba_pg_sz = 0; 2170 caps->gmv_buf_pg_sz = 0; 2171 caps->gid_table_len[0] = caps->gmv_bt_num * 2172 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2173 } 2174 2175 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2176 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2177 HEM_TYPE_QPC); 2178 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2179 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2180 HEM_TYPE_MTPT); 2181 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2182 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2183 HEM_TYPE_CQC); 2184 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num, 2185 caps->srqc_bt_num, &caps->srqc_buf_pg_sz, 2186 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC); 2187 2188 caps->sccc_hop_num = ctx_hop_num; 2189 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2190 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2191 2192 calc_pg_sz(caps->num_qps, caps->sccc_sz, 2193 caps->sccc_hop_num, caps->sccc_bt_num, 2194 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz, 2195 HEM_TYPE_SCCC); 2196 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, 2197 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, 2198 &caps->cqc_timer_buf_pg_sz, 2199 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); 2200 2201 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num, 2202 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2203 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2204 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2205 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2206 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num, 2207 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2208 2209 return 0; 2210 } 2211 2212 static int hns_roce_config_qpc_size(struct hns_roce_dev *hr_dev) 2213 { 2214 struct hns_roce_cmq_desc desc; 2215 struct hns_roce_cfg_entry_size *cfg_size = 2216 (struct hns_roce_cfg_entry_size *)desc.data; 2217 2218 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2219 false); 2220 2221 cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_QPC_SIZE); 2222 cfg_size->size = cpu_to_le32(hr_dev->caps.qpc_sz); 2223 2224 return hns_roce_cmq_send(hr_dev, &desc, 1); 2225 } 2226 2227 static int hns_roce_config_sccc_size(struct hns_roce_dev *hr_dev) 2228 { 2229 struct hns_roce_cmq_desc desc; 2230 struct hns_roce_cfg_entry_size *cfg_size = 2231 (struct hns_roce_cfg_entry_size *)desc.data; 2232 2233 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2234 false); 2235 2236 cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_SCCC_SIZE); 2237 cfg_size->size = cpu_to_le32(hr_dev->caps.sccc_sz); 2238 2239 return hns_roce_cmq_send(hr_dev, &desc, 1); 2240 } 2241 2242 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2243 { 2244 int ret; 2245 2246 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 2247 return 0; 2248 2249 ret = hns_roce_config_qpc_size(hr_dev); 2250 if (ret) { 2251 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2252 return ret; 2253 } 2254 2255 ret = hns_roce_config_sccc_size(hr_dev); 2256 if (ret) 2257 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2258 2259 return ret; 2260 } 2261 2262 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2263 { 2264 struct hns_roce_caps *caps = &hr_dev->caps; 2265 int ret; 2266 2267 ret = hns_roce_cmq_query_hw_info(hr_dev); 2268 if (ret) { 2269 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n", 2270 ret); 2271 return ret; 2272 } 2273 2274 ret = hns_roce_query_fw_ver(hr_dev); 2275 if (ret) { 2276 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 2277 ret); 2278 return ret; 2279 } 2280 2281 ret = hns_roce_config_global_param(hr_dev); 2282 if (ret) { 2283 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 2284 ret); 2285 return ret; 2286 } 2287 2288 /* Get pf resource owned by every pf */ 2289 ret = hns_roce_query_pf_resource(hr_dev); 2290 if (ret) { 2291 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 2292 ret); 2293 return ret; 2294 } 2295 2296 ret = hns_roce_query_pf_timer_resource(hr_dev); 2297 if (ret) { 2298 dev_err(hr_dev->dev, 2299 "failed to query pf timer resource, ret = %d.\n", ret); 2300 return ret; 2301 } 2302 2303 ret = hns_roce_set_vf_switch_param(hr_dev, 0); 2304 if (ret) { 2305 dev_err(hr_dev->dev, 2306 "failed to set function switch param, ret = %d.\n", 2307 ret); 2308 return ret; 2309 } 2310 2311 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2312 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2313 2314 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2315 caps->pbl_buf_pg_sz = 0; 2316 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2317 caps->eqe_ba_pg_sz = 0; 2318 caps->eqe_buf_pg_sz = 0; 2319 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2320 caps->tsq_buf_pg_sz = 0; 2321 2322 ret = hns_roce_query_pf_caps(hr_dev); 2323 if (ret) 2324 set_default_caps(hr_dev); 2325 2326 ret = hns_roce_alloc_vf_resource(hr_dev); 2327 if (ret) { 2328 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 2329 ret); 2330 return ret; 2331 } 2332 2333 ret = hns_roce_v2_set_bt(hr_dev); 2334 if (ret) { 2335 dev_err(hr_dev->dev, 2336 "Configure bt attribute fail, ret = %d.\n", ret); 2337 return ret; 2338 } 2339 2340 /* Configure the size of QPC, SCCC, etc. */ 2341 ret = hns_roce_config_entry_size(hr_dev); 2342 2343 return ret; 2344 } 2345 2346 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, 2347 enum hns_roce_link_table_type type) 2348 { 2349 struct hns_roce_cmq_desc desc[2]; 2350 struct hns_roce_cfg_llm_a *req_a = 2351 (struct hns_roce_cfg_llm_a *)desc[0].data; 2352 struct hns_roce_cfg_llm_b *req_b = 2353 (struct hns_roce_cfg_llm_b *)desc[1].data; 2354 struct hns_roce_v2_priv *priv = hr_dev->priv; 2355 struct hns_roce_link_table *link_tbl; 2356 struct hns_roce_link_table_entry *entry; 2357 enum hns_roce_opcode_type opcode; 2358 u32 page_num; 2359 2360 switch (type) { 2361 case TSQ_LINK_TABLE: 2362 link_tbl = &priv->tsq; 2363 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2364 break; 2365 case TPQ_LINK_TABLE: 2366 link_tbl = &priv->tpq; 2367 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; 2368 break; 2369 default: 2370 return -EINVAL; 2371 } 2372 2373 page_num = link_tbl->npages; 2374 entry = link_tbl->table.buf; 2375 2376 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2377 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2378 2379 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2380 2381 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff); 2382 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32); 2383 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M, 2384 CFG_LLM_QUE_DEPTH_S, link_tbl->npages); 2385 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M, 2386 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz); 2387 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M, 2388 CFG_LLM_INIT_EN_S, 1); 2389 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0); 2390 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr); 2391 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S, 2392 0); 2393 2394 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0); 2395 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M, 2396 CFG_LLM_TAIL_BA_H_S, 2397 entry[page_num - 1].blk_ba1_nxt_ptr & 2398 HNS_ROCE_LINK_TABLE_BA1_M); 2399 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S, 2400 (entry[page_num - 2].blk_ba1_nxt_ptr & 2401 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> 2402 HNS_ROCE_LINK_TABLE_NXT_PTR_S); 2403 2404 return hns_roce_cmq_send(hr_dev, desc, 2); 2405 } 2406 2407 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, 2408 enum hns_roce_link_table_type type) 2409 { 2410 struct hns_roce_v2_priv *priv = hr_dev->priv; 2411 struct hns_roce_link_table *link_tbl; 2412 struct hns_roce_link_table_entry *entry; 2413 struct device *dev = hr_dev->dev; 2414 u32 buf_chk_sz; 2415 dma_addr_t t; 2416 int func_num = 1; 2417 u32 pg_num_a; 2418 u32 pg_num_b; 2419 u32 pg_num; 2420 u32 size; 2421 int i; 2422 2423 switch (type) { 2424 case TSQ_LINK_TABLE: 2425 link_tbl = &priv->tsq; 2426 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); 2427 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; 2428 pg_num_b = hr_dev->caps.sl_num * 4 + 2; 2429 break; 2430 case TPQ_LINK_TABLE: 2431 link_tbl = &priv->tpq; 2432 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); 2433 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; 2434 pg_num_b = 2 * 4 * func_num + 2; 2435 break; 2436 default: 2437 return -EINVAL; 2438 } 2439 2440 pg_num = max(pg_num_a, pg_num_b); 2441 size = pg_num * sizeof(struct hns_roce_link_table_entry); 2442 2443 link_tbl->table.buf = dma_alloc_coherent(dev, size, 2444 &link_tbl->table.map, 2445 GFP_KERNEL); 2446 if (!link_tbl->table.buf) 2447 goto out; 2448 2449 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), 2450 GFP_KERNEL); 2451 if (!link_tbl->pg_list) 2452 goto err_kcalloc_failed; 2453 2454 entry = link_tbl->table.buf; 2455 for (i = 0; i < pg_num; ++i) { 2456 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, 2457 &t, GFP_KERNEL); 2458 if (!link_tbl->pg_list[i].buf) 2459 goto err_alloc_buf_failed; 2460 2461 link_tbl->pg_list[i].map = t; 2462 2463 entry[i].blk_ba0 = (u32)(t >> 12); 2464 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44); 2465 2466 if (i < (pg_num - 1)) 2467 entry[i].blk_ba1_nxt_ptr |= 2468 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S; 2469 } 2470 link_tbl->npages = pg_num; 2471 link_tbl->pg_sz = buf_chk_sz; 2472 2473 return hns_roce_config_link_table(hr_dev, type); 2474 2475 err_alloc_buf_failed: 2476 for (i -= 1; i >= 0; i--) 2477 dma_free_coherent(dev, buf_chk_sz, 2478 link_tbl->pg_list[i].buf, 2479 link_tbl->pg_list[i].map); 2480 kfree(link_tbl->pg_list); 2481 2482 err_kcalloc_failed: 2483 dma_free_coherent(dev, size, link_tbl->table.buf, 2484 link_tbl->table.map); 2485 2486 out: 2487 return -ENOMEM; 2488 } 2489 2490 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, 2491 struct hns_roce_link_table *link_tbl) 2492 { 2493 struct device *dev = hr_dev->dev; 2494 int size; 2495 int i; 2496 2497 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); 2498 2499 for (i = 0; i < link_tbl->npages; ++i) 2500 if (link_tbl->pg_list[i].buf) 2501 dma_free_coherent(dev, link_tbl->pg_sz, 2502 link_tbl->pg_list[i].buf, 2503 link_tbl->pg_list[i].map); 2504 kfree(link_tbl->pg_list); 2505 2506 dma_free_coherent(dev, size, link_tbl->table.buf, 2507 link_tbl->table.map); 2508 } 2509 2510 static int get_hem_table(struct hns_roce_dev *hr_dev) 2511 { 2512 unsigned int qpc_count; 2513 unsigned int cqc_count; 2514 unsigned int gmv_count; 2515 int ret; 2516 int i; 2517 2518 /* Alloc memory for QPC Timer buffer space chunk */ 2519 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2520 qpc_count++) { 2521 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2522 qpc_count); 2523 if (ret) { 2524 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2525 goto err_qpc_timer_failed; 2526 } 2527 } 2528 2529 /* Alloc memory for CQC Timer buffer space chunk */ 2530 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2531 cqc_count++) { 2532 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2533 cqc_count); 2534 if (ret) { 2535 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2536 goto err_cqc_timer_failed; 2537 } 2538 } 2539 2540 /* Alloc memory for GMV(GID/MAC/VLAN) table buffer space chunk */ 2541 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2542 gmv_count++) { 2543 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2544 if (ret) { 2545 dev_err(hr_dev->dev, 2546 "failed to get gmv table, ret = %d.\n", ret); 2547 goto err_gmv_failed; 2548 } 2549 } 2550 2551 return 0; 2552 2553 err_gmv_failed: 2554 for (i = 0; i < gmv_count; i++) 2555 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2556 2557 err_cqc_timer_failed: 2558 for (i = 0; i < cqc_count; i++) 2559 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2560 2561 err_qpc_timer_failed: 2562 for (i = 0; i < qpc_count; i++) 2563 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2564 2565 return ret; 2566 } 2567 2568 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2569 { 2570 struct hns_roce_v2_priv *priv = hr_dev->priv; 2571 int ret; 2572 2573 /* TSQ includes SQ doorbell and ack doorbell */ 2574 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); 2575 if (ret) { 2576 dev_err(hr_dev->dev, "failed to init TSQ, ret = %d.\n", ret); 2577 return ret; 2578 } 2579 2580 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); 2581 if (ret) { 2582 dev_err(hr_dev->dev, "failed to init TPQ, ret = %d.\n", ret); 2583 goto err_tpq_init_failed; 2584 } 2585 2586 ret = get_hem_table(hr_dev); 2587 if (ret) 2588 goto err_get_hem_table_failed; 2589 2590 return 0; 2591 2592 err_get_hem_table_failed: 2593 hns_roce_free_link_table(hr_dev, &priv->tpq); 2594 2595 err_tpq_init_failed: 2596 hns_roce_free_link_table(hr_dev, &priv->tsq); 2597 2598 return ret; 2599 } 2600 2601 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2602 { 2603 struct hns_roce_v2_priv *priv = hr_dev->priv; 2604 2605 hns_roce_function_clear(hr_dev); 2606 2607 hns_roce_free_link_table(hr_dev, &priv->tpq); 2608 hns_roce_free_link_table(hr_dev, &priv->tsq); 2609 } 2610 2611 static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev) 2612 { 2613 struct hns_roce_cmq_desc desc; 2614 struct hns_roce_mbox_status *mb_st = 2615 (struct hns_roce_mbox_status *)desc.data; 2616 int status; 2617 2618 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true); 2619 2620 status = hns_roce_cmq_send(hr_dev, &desc, 1); 2621 if (status) 2622 return status; 2623 2624 return le32_to_cpu(mb_st->mb_status_hw_run); 2625 } 2626 2627 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 2628 { 2629 u32 status = hns_roce_query_mbox_status(hr_dev); 2630 2631 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 2632 } 2633 2634 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 2635 { 2636 u32 status = hns_roce_query_mbox_status(hr_dev); 2637 2638 return status & HNS_ROCE_HW_MB_STATUS_MASK; 2639 } 2640 2641 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2642 u64 out_param, u32 in_modifier, u8 op_modifier, 2643 u16 op, u16 token, int event) 2644 { 2645 struct hns_roce_cmq_desc desc; 2646 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2647 2648 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2649 2650 mb->in_param_l = cpu_to_le32(in_param); 2651 mb->in_param_h = cpu_to_le32(in_param >> 32); 2652 mb->out_param_l = cpu_to_le32(out_param); 2653 mb->out_param_h = cpu_to_le32(out_param >> 32); 2654 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2655 mb->token_event_en = cpu_to_le32(event << 16 | token); 2656 2657 return hns_roce_cmq_send(hr_dev, &desc, 1); 2658 } 2659 2660 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2661 u64 out_param, u32 in_modifier, u8 op_modifier, 2662 u16 op, u16 token, int event) 2663 { 2664 struct device *dev = hr_dev->dev; 2665 unsigned long end; 2666 int ret; 2667 2668 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 2669 while (hns_roce_v2_cmd_pending(hr_dev)) { 2670 if (time_after(jiffies, end)) { 2671 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 2672 (int)end); 2673 return -EAGAIN; 2674 } 2675 cond_resched(); 2676 } 2677 2678 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2679 op_modifier, op, token, event); 2680 if (ret) 2681 dev_err(dev, "Post mailbox fail(%d)\n", ret); 2682 2683 return ret; 2684 } 2685 2686 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 2687 unsigned int timeout) 2688 { 2689 struct device *dev = hr_dev->dev; 2690 unsigned long end; 2691 u32 status; 2692 2693 end = msecs_to_jiffies(timeout) + jiffies; 2694 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 2695 cond_resched(); 2696 2697 if (hns_roce_v2_cmd_pending(hr_dev)) { 2698 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 2699 return -ETIMEDOUT; 2700 } 2701 2702 status = hns_roce_v2_cmd_complete(hr_dev); 2703 if (status != 0x1) { 2704 if (status == CMD_RST_PRC_EBUSY) 2705 return status; 2706 2707 dev_err(dev, "mailbox status 0x%x!\n", status); 2708 return -EBUSY; 2709 } 2710 2711 return 0; 2712 } 2713 2714 static void copy_gid(void *dest, const union ib_gid *gid) 2715 { 2716 #define GID_SIZE 4 2717 const union ib_gid *src = gid; 2718 __le32 (*p)[GID_SIZE] = dest; 2719 int i; 2720 2721 if (!gid) 2722 src = &zgid; 2723 2724 for (i = 0; i < GID_SIZE; i++) 2725 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 2726 } 2727 2728 static int config_sgid_table(struct hns_roce_dev *hr_dev, 2729 int gid_index, const union ib_gid *gid, 2730 enum hns_roce_sgid_type sgid_type) 2731 { 2732 struct hns_roce_cmq_desc desc; 2733 struct hns_roce_cfg_sgid_tb *sgid_tb = 2734 (struct hns_roce_cfg_sgid_tb *)desc.data; 2735 2736 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2737 2738 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2739 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2740 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2741 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2742 2743 copy_gid(&sgid_tb->vf_sgid_l, gid); 2744 2745 return hns_roce_cmq_send(hr_dev, &desc, 1); 2746 } 2747 2748 static int config_gmv_table(struct hns_roce_dev *hr_dev, 2749 int gid_index, const union ib_gid *gid, 2750 enum hns_roce_sgid_type sgid_type, 2751 const struct ib_gid_attr *attr) 2752 { 2753 struct hns_roce_cmq_desc desc[2]; 2754 struct hns_roce_cfg_gmv_tb_a *tb_a = 2755 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 2756 struct hns_roce_cfg_gmv_tb_b *tb_b = 2757 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 2758 2759 u16 vlan_id = VLAN_CFI_MASK; 2760 u8 mac[ETH_ALEN] = {}; 2761 int ret; 2762 2763 if (gid) { 2764 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 2765 if (ret) 2766 return ret; 2767 } 2768 2769 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2770 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2771 2772 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2773 2774 copy_gid(&tb_a->vf_sgid_l, gid); 2775 2776 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_SGID_TYPE_M, 2777 CFG_GMV_TB_VF_SGID_TYPE_S, sgid_type); 2778 roce_set_bit(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_EN_S, 2779 vlan_id < VLAN_CFI_MASK); 2780 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_ID_M, 2781 CFG_GMV_TB_VF_VLAN_ID_S, vlan_id); 2782 2783 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 2784 roce_set_field(tb_b->vf_smac_h, CFG_GMV_TB_SMAC_H_M, 2785 CFG_GMV_TB_SMAC_H_S, *(u16 *)&mac[4]); 2786 2787 roce_set_field(tb_b->table_idx_rsv, CFG_GMV_TB_SGID_IDX_M, 2788 CFG_GMV_TB_SGID_IDX_S, gid_index); 2789 2790 return hns_roce_cmq_send(hr_dev, desc, 2); 2791 } 2792 2793 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 2794 int gid_index, const union ib_gid *gid, 2795 const struct ib_gid_attr *attr) 2796 { 2797 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2798 int ret; 2799 2800 if (gid) { 2801 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2802 if (ipv6_addr_v4mapped((void *)gid)) 2803 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2804 else 2805 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2806 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 2807 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2808 } 2809 } 2810 2811 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 2812 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 2813 else 2814 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2815 2816 if (ret) 2817 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 2818 ret); 2819 2820 return ret; 2821 } 2822 2823 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2824 u8 *addr) 2825 { 2826 struct hns_roce_cmq_desc desc; 2827 struct hns_roce_cfg_smac_tb *smac_tb = 2828 (struct hns_roce_cfg_smac_tb *)desc.data; 2829 u16 reg_smac_h; 2830 u32 reg_smac_l; 2831 2832 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 2833 2834 reg_smac_l = *(u32 *)(&addr[0]); 2835 reg_smac_h = *(u16 *)(&addr[4]); 2836 2837 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 2838 CFG_SMAC_TB_IDX_S, phy_port); 2839 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 2840 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 2841 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 2842 2843 return hns_roce_cmq_send(hr_dev, &desc, 1); 2844 } 2845 2846 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 2847 struct hns_roce_v2_mpt_entry *mpt_entry, 2848 struct hns_roce_mr *mr) 2849 { 2850 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 2851 struct ib_device *ibdev = &hr_dev->ib_dev; 2852 dma_addr_t pbl_ba; 2853 int i, count; 2854 2855 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 2856 ARRAY_SIZE(pages), &pbl_ba); 2857 if (count < 1) { 2858 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 2859 count); 2860 return -ENOBUFS; 2861 } 2862 2863 /* Aligned to the hardware address access unit */ 2864 for (i = 0; i < count; i++) 2865 pages[i] >>= 6; 2866 2867 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2868 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 2869 roce_set_field(mpt_entry->byte_48_mode_ba, 2870 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 2871 upper_32_bits(pbl_ba >> 3)); 2872 2873 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 2874 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 2875 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 2876 2877 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 2878 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 2879 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 2880 roce_set_field(mpt_entry->byte_64_buf_pa1, 2881 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2882 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2883 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2884 2885 return 0; 2886 } 2887 2888 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 2889 void *mb_buf, struct hns_roce_mr *mr, 2890 unsigned long mtpt_idx) 2891 { 2892 struct hns_roce_v2_mpt_entry *mpt_entry; 2893 int ret; 2894 2895 mpt_entry = mb_buf; 2896 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2897 2898 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 2899 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 2900 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 2901 2902 hr_reg_write(mpt_entry, MPT_BIND_EN, 2903 !!(mr->access & IB_ACCESS_MW_BIND)); 2904 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 2905 !!(mr->access & IB_ACCESS_REMOTE_ATOMIC)); 2906 hr_reg_write(mpt_entry, MPT_RR_EN, 2907 !!(mr->access & IB_ACCESS_REMOTE_READ)); 2908 hr_reg_write(mpt_entry, MPT_RW_EN, 2909 !!(mr->access & IB_ACCESS_REMOTE_WRITE)); 2910 hr_reg_write(mpt_entry, MPT_LW_EN, 2911 !!((mr->access & IB_ACCESS_LOCAL_WRITE))); 2912 2913 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 2914 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 2915 mpt_entry->lkey = cpu_to_le32(mr->key); 2916 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 2917 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 2918 2919 if (mr->type != MR_TYPE_MR) 2920 hr_reg_enable(mpt_entry, MPT_PA); 2921 2922 if (mr->type == MR_TYPE_DMA) 2923 return 0; 2924 2925 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 2926 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 2927 2928 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 2929 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2930 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 2931 2932 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2933 2934 return ret; 2935 } 2936 2937 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 2938 struct hns_roce_mr *mr, int flags, 2939 void *mb_buf) 2940 { 2941 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 2942 u32 mr_access_flags = mr->access; 2943 int ret = 0; 2944 2945 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2946 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2947 2948 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2949 V2_MPT_BYTE_4_PD_S, mr->pd); 2950 2951 if (flags & IB_MR_REREG_ACCESS) { 2952 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2953 V2_MPT_BYTE_8_BIND_EN_S, 2954 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 2955 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2956 V2_MPT_BYTE_8_ATOMIC_EN_S, 2957 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2958 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2959 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 2960 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2961 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 2962 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2963 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 2964 } 2965 2966 if (flags & IB_MR_REREG_TRANS) { 2967 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 2968 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 2969 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 2970 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 2971 2972 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2973 } 2974 2975 return ret; 2976 } 2977 2978 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 2979 void *mb_buf, struct hns_roce_mr *mr) 2980 { 2981 struct ib_device *ibdev = &hr_dev->ib_dev; 2982 struct hns_roce_v2_mpt_entry *mpt_entry; 2983 dma_addr_t pbl_ba = 0; 2984 2985 mpt_entry = mb_buf; 2986 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2987 2988 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 2989 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 2990 return -ENOBUFS; 2991 } 2992 2993 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2994 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2995 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2996 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 2997 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2998 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2999 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3000 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3001 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3002 V2_MPT_BYTE_4_PD_S, mr->pd); 3003 3004 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 3005 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3006 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3007 3008 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 3009 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3010 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 3011 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3012 3013 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3014 3015 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3016 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 3017 V2_MPT_BYTE_48_PBL_BA_H_S, 3018 upper_32_bits(pbl_ba >> 3)); 3019 3020 roce_set_field(mpt_entry->byte_64_buf_pa1, 3021 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3022 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3023 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3024 3025 return 0; 3026 } 3027 3028 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3029 { 3030 struct hns_roce_v2_mpt_entry *mpt_entry; 3031 3032 mpt_entry = mb_buf; 3033 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3034 3035 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3036 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3037 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3038 V2_MPT_BYTE_4_PD_S, mw->pdn); 3039 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3040 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 3041 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3042 mw->pbl_hop_num); 3043 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3044 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3045 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3046 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3047 3048 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3049 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3050 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1); 3051 3052 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3053 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 3054 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3055 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 3056 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3057 3058 roce_set_field(mpt_entry->byte_64_buf_pa1, 3059 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3060 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3061 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3062 3063 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3064 3065 return 0; 3066 } 3067 3068 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3069 { 3070 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3071 } 3072 3073 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3074 { 3075 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3076 3077 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3078 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 3079 !!(n & hr_cq->cq_depth)) ? cqe : NULL; 3080 } 3081 3082 static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci) 3083 { 3084 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M; 3085 } 3086 3087 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3088 struct hns_roce_srq *srq) 3089 { 3090 struct hns_roce_v2_cqe *cqe, *dest; 3091 u32 prod_index; 3092 int nfreed = 0; 3093 int wqe_index; 3094 u8 owner_bit; 3095 3096 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3097 ++prod_index) { 3098 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3099 break; 3100 } 3101 3102 /* 3103 * Now backwards through the CQ, removing CQ entries 3104 * that match our QP by overwriting them with next entries. 3105 */ 3106 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3107 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3108 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 3109 V2_CQE_BYTE_16_LCL_QPN_S) & 3110 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 3111 if (srq && 3112 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) { 3113 wqe_index = roce_get_field(cqe->byte_4, 3114 V2_CQE_BYTE_4_WQE_INDX_M, 3115 V2_CQE_BYTE_4_WQE_INDX_S); 3116 hns_roce_free_srq_wqe(srq, wqe_index); 3117 } 3118 ++nfreed; 3119 } else if (nfreed) { 3120 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3121 hr_cq->ib_cq.cqe); 3122 owner_bit = roce_get_bit(dest->byte_4, 3123 V2_CQE_BYTE_4_OWNER_S); 3124 memcpy(dest, cqe, sizeof(*cqe)); 3125 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 3126 owner_bit); 3127 } 3128 } 3129 3130 if (nfreed) { 3131 hr_cq->cons_index += nfreed; 3132 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 3133 } 3134 } 3135 3136 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3137 struct hns_roce_srq *srq) 3138 { 3139 spin_lock_irq(&hr_cq->lock); 3140 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3141 spin_unlock_irq(&hr_cq->lock); 3142 } 3143 3144 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3145 struct hns_roce_cq *hr_cq, void *mb_buf, 3146 u64 *mtts, dma_addr_t dma_handle) 3147 { 3148 struct hns_roce_v2_cq_context *cq_context; 3149 3150 cq_context = mb_buf; 3151 memset(cq_context, 0, sizeof(*cq_context)); 3152 3153 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 3154 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 3155 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 3156 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 3157 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 3158 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); 3159 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 3160 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); 3161 3162 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 3163 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 3164 3165 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQE_SIZE_M, 3166 V2_CQC_BYTE_8_CQE_SIZE_S, hr_cq->cqe_size == 3167 HNS_ROCE_V3_CQE_SIZE ? 1 : 0); 3168 3169 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3170 hr_reg_enable(cq_context, CQC_STASH); 3171 3172 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 3173 3174 roce_set_field(cq_context->byte_16_hop_addr, 3175 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 3176 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 3177 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3178 roce_set_field(cq_context->byte_16_hop_addr, 3179 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 3180 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 3181 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3182 3183 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 3184 roce_set_field(cq_context->byte_24_pgsz_addr, 3185 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 3186 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 3187 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3188 roce_set_field(cq_context->byte_24_pgsz_addr, 3189 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 3190 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 3191 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3192 roce_set_field(cq_context->byte_24_pgsz_addr, 3193 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 3194 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 3195 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3196 3197 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); 3198 3199 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 3200 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 3201 3202 roce_set_bit(cq_context->byte_44_db_record, 3203 V2_CQC_BYTE_44_DB_RECORD_EN_S, 3204 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0); 3205 3206 roce_set_field(cq_context->byte_44_db_record, 3207 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 3208 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 3209 ((u32)hr_cq->db.dma) >> 1); 3210 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); 3211 3212 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3213 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 3214 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3215 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3216 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3217 V2_CQC_BYTE_56_CQ_PERIOD_M, 3218 V2_CQC_BYTE_56_CQ_PERIOD_S, 3219 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3220 } 3221 3222 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3223 enum ib_cq_notify_flags flags) 3224 { 3225 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3226 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3227 u32 notification_flag; 3228 __le32 doorbell[2]; 3229 3230 doorbell[0] = 0; 3231 doorbell[1] = 0; 3232 3233 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3234 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3235 /* 3236 * flags = 0; Notification Flag = 1, next 3237 * flags = 1; Notification Flag = 0, solocited 3238 */ 3239 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 3240 hr_cq->cqn); 3241 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 3242 HNS_ROCE_V2_CQ_DB_NTR); 3243 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 3244 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index); 3245 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 3246 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 3247 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 3248 notification_flag); 3249 3250 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l); 3251 3252 return 0; 3253 } 3254 3255 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3256 struct hns_roce_qp **cur_qp, 3257 struct ib_wc *wc) 3258 { 3259 struct hns_roce_rinl_sge *sge_list; 3260 u32 wr_num, wr_cnt, sge_num; 3261 u32 sge_cnt, data_len, size; 3262 void *wqe_buf; 3263 3264 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 3265 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 3266 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 3267 3268 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3269 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3270 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt); 3271 data_len = wc->byte_len; 3272 3273 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3274 size = min(sge_list[sge_cnt].len, data_len); 3275 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3276 3277 data_len -= size; 3278 wqe_buf += size; 3279 } 3280 3281 if (unlikely(data_len)) { 3282 wc->status = IB_WC_LOC_LEN_ERR; 3283 return -EAGAIN; 3284 } 3285 3286 return 0; 3287 } 3288 3289 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3290 int num_entries, struct ib_wc *wc) 3291 { 3292 unsigned int left; 3293 int npolled = 0; 3294 3295 left = wq->head - wq->tail; 3296 if (left == 0) 3297 return 0; 3298 3299 left = min_t(unsigned int, (unsigned int)num_entries, left); 3300 while (npolled < left) { 3301 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3302 wc->status = IB_WC_WR_FLUSH_ERR; 3303 wc->vendor_err = 0; 3304 wc->qp = &hr_qp->ibqp; 3305 3306 wq->tail++; 3307 wc++; 3308 npolled++; 3309 } 3310 3311 return npolled; 3312 } 3313 3314 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3315 struct ib_wc *wc) 3316 { 3317 struct hns_roce_qp *hr_qp; 3318 int npolled = 0; 3319 3320 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3321 npolled += sw_comp(hr_qp, &hr_qp->sq, 3322 num_entries - npolled, wc + npolled); 3323 if (npolled >= num_entries) 3324 goto out; 3325 } 3326 3327 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3328 npolled += sw_comp(hr_qp, &hr_qp->rq, 3329 num_entries - npolled, wc + npolled); 3330 if (npolled >= num_entries) 3331 goto out; 3332 } 3333 3334 out: 3335 return npolled; 3336 } 3337 3338 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3339 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3340 struct ib_wc *wc) 3341 { 3342 static const struct { 3343 u32 cqe_status; 3344 enum ib_wc_status wc_status; 3345 } map[] = { 3346 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3347 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3348 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3349 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3350 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3351 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3352 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3353 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3354 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3355 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3356 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3357 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3358 IB_WC_RETRY_EXC_ERR }, 3359 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3360 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3361 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3362 }; 3363 3364 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 3365 V2_CQE_BYTE_4_STATUS_S); 3366 int i; 3367 3368 wc->status = IB_WC_GENERAL_ERR; 3369 for (i = 0; i < ARRAY_SIZE(map); i++) 3370 if (cqe_status == map[i].cqe_status) { 3371 wc->status = map[i].wc_status; 3372 break; 3373 } 3374 3375 if (likely(wc->status == IB_WC_SUCCESS || 3376 wc->status == IB_WC_WR_FLUSH_ERR)) 3377 return; 3378 3379 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3380 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3381 cq->cqe_size, false); 3382 3383 /* 3384 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3385 * the standard protocol, the driver must ignore it and needn't to set 3386 * the QP to an error state. 3387 */ 3388 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3389 return; 3390 3391 /* 3392 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets 3393 * into errored mode. Hence, as a workaround to this hardware 3394 * limitation, driver needs to assist in flushing. But the flushing 3395 * operation uses mailbox to convey the QP state to the hardware and 3396 * which can sleep due to the mutex protection around the mailbox calls. 3397 * Hence, use the deferred flush for now. Once wc error detected, the 3398 * flushing operation is needed. 3399 */ 3400 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 3401 init_flush_work(hr_dev, qp); 3402 } 3403 3404 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3405 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3406 { 3407 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3408 struct hns_roce_srq *srq = NULL; 3409 struct hns_roce_v2_cqe *cqe; 3410 struct hns_roce_qp *hr_qp; 3411 struct hns_roce_wq *wq; 3412 int is_send; 3413 u16 wqe_ctr; 3414 u32 opcode; 3415 u32 qpn; 3416 int ret; 3417 3418 /* Find cqe according to consumer index */ 3419 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3420 if (!cqe) 3421 return -EAGAIN; 3422 3423 ++hr_cq->cons_index; 3424 /* Memory barrier */ 3425 rmb(); 3426 3427 /* 0->SQ, 1->RQ */ 3428 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 3429 3430 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 3431 V2_CQE_BYTE_16_LCL_QPN_S); 3432 3433 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 3434 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3435 if (unlikely(!hr_qp)) { 3436 ibdev_err(&hr_dev->ib_dev, 3437 "CQ %06lx with entry for unknown QPN %06x\n", 3438 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK); 3439 return -EINVAL; 3440 } 3441 *cur_qp = hr_qp; 3442 } 3443 3444 wc->qp = &(*cur_qp)->ibqp; 3445 wc->vendor_err = 0; 3446 3447 if (is_send) { 3448 wq = &(*cur_qp)->sq; 3449 if ((*cur_qp)->sq_signal_bits) { 3450 /* 3451 * If sg_signal_bit is 1, 3452 * firstly tail pointer updated to wqe 3453 * which current cqe correspond to 3454 */ 3455 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3456 V2_CQE_BYTE_4_WQE_INDX_M, 3457 V2_CQE_BYTE_4_WQE_INDX_S); 3458 wq->tail += (wqe_ctr - (u16)wq->tail) & 3459 (wq->wqe_cnt - 1); 3460 } 3461 3462 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3463 ++wq->tail; 3464 } else if ((*cur_qp)->ibqp.srq) { 3465 srq = to_hr_srq((*cur_qp)->ibqp.srq); 3466 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3467 V2_CQE_BYTE_4_WQE_INDX_M, 3468 V2_CQE_BYTE_4_WQE_INDX_S); 3469 wc->wr_id = srq->wrid[wqe_ctr]; 3470 hns_roce_free_srq_wqe(srq, wqe_ctr); 3471 } else { 3472 /* Update tail pointer, record wr_id */ 3473 wq = &(*cur_qp)->rq; 3474 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3475 ++wq->tail; 3476 } 3477 3478 get_cqe_status(hr_dev, *cur_qp, hr_cq, cqe, wc); 3479 if (unlikely(wc->status != IB_WC_SUCCESS)) 3480 return 0; 3481 3482 if (is_send) { 3483 wc->wc_flags = 0; 3484 /* SQ corresponding to CQE */ 3485 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3486 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 3487 case HNS_ROCE_V2_WQE_OP_SEND: 3488 wc->opcode = IB_WC_SEND; 3489 break; 3490 case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV: 3491 wc->opcode = IB_WC_SEND; 3492 break; 3493 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3494 wc->opcode = IB_WC_SEND; 3495 wc->wc_flags |= IB_WC_WITH_IMM; 3496 break; 3497 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3498 wc->opcode = IB_WC_RDMA_READ; 3499 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3500 break; 3501 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE: 3502 wc->opcode = IB_WC_RDMA_WRITE; 3503 break; 3504 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3505 wc->opcode = IB_WC_RDMA_WRITE; 3506 wc->wc_flags |= IB_WC_WITH_IMM; 3507 break; 3508 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3509 wc->opcode = IB_WC_LOCAL_INV; 3510 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3511 break; 3512 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3513 wc->opcode = IB_WC_COMP_SWAP; 3514 wc->byte_len = 8; 3515 break; 3516 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3517 wc->opcode = IB_WC_FETCH_ADD; 3518 wc->byte_len = 8; 3519 break; 3520 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3521 wc->opcode = IB_WC_MASKED_COMP_SWAP; 3522 wc->byte_len = 8; 3523 break; 3524 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3525 wc->opcode = IB_WC_MASKED_FETCH_ADD; 3526 wc->byte_len = 8; 3527 break; 3528 case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR: 3529 wc->opcode = IB_WC_REG_MR; 3530 break; 3531 case HNS_ROCE_V2_WQE_OP_BIND_MW: 3532 wc->opcode = IB_WC_REG_MR; 3533 break; 3534 default: 3535 wc->status = IB_WC_GENERAL_ERR; 3536 break; 3537 } 3538 } else { 3539 /* RQ correspond to CQE */ 3540 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3541 3542 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3543 V2_CQE_BYTE_4_OPCODE_S); 3544 switch (opcode & 0x1f) { 3545 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3546 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3547 wc->wc_flags = IB_WC_WITH_IMM; 3548 wc->ex.imm_data = 3549 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3550 break; 3551 case HNS_ROCE_V2_OPCODE_SEND: 3552 wc->opcode = IB_WC_RECV; 3553 wc->wc_flags = 0; 3554 break; 3555 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3556 wc->opcode = IB_WC_RECV; 3557 wc->wc_flags = IB_WC_WITH_IMM; 3558 wc->ex.imm_data = 3559 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3560 break; 3561 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3562 wc->opcode = IB_WC_RECV; 3563 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3564 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3565 break; 3566 default: 3567 wc->status = IB_WC_GENERAL_ERR; 3568 break; 3569 } 3570 3571 if ((wc->qp->qp_type == IB_QPT_RC || 3572 wc->qp->qp_type == IB_QPT_UC) && 3573 (opcode == HNS_ROCE_V2_OPCODE_SEND || 3574 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3575 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3576 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 3577 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 3578 if (unlikely(ret)) 3579 return -EAGAIN; 3580 } 3581 3582 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 3583 V2_CQE_BYTE_32_SL_S); 3584 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 3585 V2_CQE_BYTE_32_RMT_QPN_M, 3586 V2_CQE_BYTE_32_RMT_QPN_S); 3587 wc->slid = 0; 3588 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 3589 V2_CQE_BYTE_32_GRH_S) ? 3590 IB_WC_GRH : 0); 3591 wc->port_num = roce_get_field(cqe->byte_32, 3592 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 3593 wc->pkey_index = 0; 3594 3595 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) { 3596 wc->vlan_id = (u16)roce_get_field(cqe->byte_28, 3597 V2_CQE_BYTE_28_VID_M, 3598 V2_CQE_BYTE_28_VID_S); 3599 wc->wc_flags |= IB_WC_WITH_VLAN; 3600 } else { 3601 wc->vlan_id = 0xffff; 3602 } 3603 3604 wc->network_hdr_type = roce_get_field(cqe->byte_28, 3605 V2_CQE_BYTE_28_PORT_TYPE_M, 3606 V2_CQE_BYTE_28_PORT_TYPE_S); 3607 } 3608 3609 return 0; 3610 } 3611 3612 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3613 struct ib_wc *wc) 3614 { 3615 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3616 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3617 struct hns_roce_qp *cur_qp = NULL; 3618 unsigned long flags; 3619 int npolled; 3620 3621 spin_lock_irqsave(&hr_cq->lock, flags); 3622 3623 /* 3624 * When the device starts to reset, the state is RST_DOWN. At this time, 3625 * there may still be some valid CQEs in the hardware that are not 3626 * polled. Therefore, it is not allowed to switch to the software mode 3627 * immediately. When the state changes to UNINIT, CQE no longer exists 3628 * in the hardware, and then switch to software mode. 3629 */ 3630 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3631 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3632 goto out; 3633 } 3634 3635 for (npolled = 0; npolled < num_entries; ++npolled) { 3636 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3637 break; 3638 } 3639 3640 if (npolled) 3641 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 3642 3643 out: 3644 spin_unlock_irqrestore(&hr_cq->lock, flags); 3645 3646 return npolled; 3647 } 3648 3649 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3650 int step_idx) 3651 { 3652 int op; 3653 3654 if (type == HEM_TYPE_SCCC && step_idx) 3655 return -EINVAL; 3656 3657 switch (type) { 3658 case HEM_TYPE_QPC: 3659 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3660 break; 3661 case HEM_TYPE_MTPT: 3662 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3663 break; 3664 case HEM_TYPE_CQC: 3665 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3666 break; 3667 case HEM_TYPE_SRQC: 3668 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3669 break; 3670 case HEM_TYPE_SCCC: 3671 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3672 break; 3673 case HEM_TYPE_QPC_TIMER: 3674 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3675 break; 3676 case HEM_TYPE_CQC_TIMER: 3677 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3678 break; 3679 default: 3680 dev_warn(hr_dev->dev, 3681 "table %u not to be written by mailbox!\n", type); 3682 return -EINVAL; 3683 } 3684 3685 return op + step_idx; 3686 } 3687 3688 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba, 3689 u32 hem_type, int step_idx) 3690 { 3691 struct hns_roce_cmd_mailbox *mailbox; 3692 struct hns_roce_cmq_desc desc; 3693 struct hns_roce_cfg_gmv_bt *gmv_bt = 3694 (struct hns_roce_cfg_gmv_bt *)desc.data; 3695 int ret; 3696 int op; 3697 3698 if (hem_type == HEM_TYPE_GMV) { 3699 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, 3700 false); 3701 3702 gmv_bt->gmv_ba_l = cpu_to_le32(bt_ba >> HNS_HW_PAGE_SHIFT); 3703 gmv_bt->gmv_ba_h = cpu_to_le32(bt_ba >> (HNS_HW_PAGE_SHIFT + 3704 32)); 3705 gmv_bt->gmv_bt_idx = cpu_to_le32(obj / 3706 (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz)); 3707 3708 return hns_roce_cmq_send(hr_dev, &desc, 1); 3709 } 3710 3711 op = get_op_for_set_hem(hr_dev, hem_type, step_idx); 3712 if (op < 0) 3713 return 0; 3714 3715 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3716 if (IS_ERR(mailbox)) 3717 return PTR_ERR(mailbox); 3718 3719 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 3720 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 3721 3722 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3723 3724 return ret; 3725 } 3726 3727 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3728 struct hns_roce_hem_table *table, int obj, 3729 int step_idx) 3730 { 3731 struct hns_roce_hem_iter iter; 3732 struct hns_roce_hem_mhop mhop; 3733 struct hns_roce_hem *hem; 3734 unsigned long mhop_obj = obj; 3735 int i, j, k; 3736 int ret = 0; 3737 u64 hem_idx = 0; 3738 u64 l1_idx = 0; 3739 u64 bt_ba = 0; 3740 u32 chunk_ba_num; 3741 u32 hop_num; 3742 3743 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3744 return 0; 3745 3746 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3747 i = mhop.l0_idx; 3748 j = mhop.l1_idx; 3749 k = mhop.l2_idx; 3750 hop_num = mhop.hop_num; 3751 chunk_ba_num = mhop.bt_chunk_size / 8; 3752 3753 if (hop_num == 2) { 3754 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3755 k; 3756 l1_idx = i * chunk_ba_num + j; 3757 } else if (hop_num == 1) { 3758 hem_idx = i * chunk_ba_num + j; 3759 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3760 hem_idx = i; 3761 } 3762 3763 if (table->type == HEM_TYPE_SCCC) 3764 obj = mhop.l0_idx; 3765 3766 if (check_whether_last_step(hop_num, step_idx)) { 3767 hem = table->hem[hem_idx]; 3768 for (hns_roce_hem_first(hem, &iter); 3769 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3770 bt_ba = hns_roce_hem_addr(&iter); 3771 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3772 step_idx); 3773 } 3774 } else { 3775 if (step_idx == 0) 3776 bt_ba = table->bt_l0_dma_addr[i]; 3777 else if (step_idx == 1 && hop_num == 2) 3778 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3779 3780 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3781 } 3782 3783 return ret; 3784 } 3785 3786 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3787 struct hns_roce_hem_table *table, int obj, 3788 int step_idx) 3789 { 3790 struct device *dev = hr_dev->dev; 3791 struct hns_roce_cmd_mailbox *mailbox; 3792 int ret; 3793 u16 op = 0xff; 3794 3795 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3796 return 0; 3797 3798 switch (table->type) { 3799 case HEM_TYPE_QPC: 3800 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3801 break; 3802 case HEM_TYPE_MTPT: 3803 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3804 break; 3805 case HEM_TYPE_CQC: 3806 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3807 break; 3808 case HEM_TYPE_SRQC: 3809 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3810 break; 3811 case HEM_TYPE_SCCC: 3812 case HEM_TYPE_QPC_TIMER: 3813 case HEM_TYPE_CQC_TIMER: 3814 case HEM_TYPE_GMV: 3815 return 0; 3816 default: 3817 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 3818 table->type); 3819 return 0; 3820 } 3821 3822 op += step_idx; 3823 3824 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3825 if (IS_ERR(mailbox)) 3826 return PTR_ERR(mailbox); 3827 3828 /* configure the tag and op */ 3829 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3830 HNS_ROCE_CMD_TIMEOUT_MSECS); 3831 3832 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3833 return ret; 3834 } 3835 3836 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3837 struct hns_roce_v2_qp_context *context, 3838 struct hns_roce_v2_qp_context *qpc_mask, 3839 struct hns_roce_qp *hr_qp) 3840 { 3841 struct hns_roce_cmd_mailbox *mailbox; 3842 int qpc_size; 3843 int ret; 3844 3845 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3846 if (IS_ERR(mailbox)) 3847 return PTR_ERR(mailbox); 3848 3849 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 3850 qpc_size = hr_dev->caps.qpc_sz; 3851 memcpy(mailbox->buf, context, qpc_size); 3852 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 3853 3854 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 3855 HNS_ROCE_CMD_MODIFY_QPC, 3856 HNS_ROCE_CMD_TIMEOUT_MSECS); 3857 3858 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3859 3860 return ret; 3861 } 3862 3863 static void set_access_flags(struct hns_roce_qp *hr_qp, 3864 struct hns_roce_v2_qp_context *context, 3865 struct hns_roce_v2_qp_context *qpc_mask, 3866 const struct ib_qp_attr *attr, int attr_mask) 3867 { 3868 u8 dest_rd_atomic; 3869 u32 access_flags; 3870 3871 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 3872 attr->max_dest_rd_atomic : hr_qp->resp_depth; 3873 3874 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 3875 attr->qp_access_flags : hr_qp->atomic_rd_en; 3876 3877 if (!dest_rd_atomic) 3878 access_flags &= IB_ACCESS_REMOTE_WRITE; 3879 3880 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3881 !!(access_flags & IB_ACCESS_REMOTE_READ)); 3882 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 3883 3884 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3885 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3886 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 3887 3888 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3889 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3890 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 3891 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 3892 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3893 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0); 3894 } 3895 3896 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 3897 struct hns_roce_v2_qp_context *context, 3898 struct hns_roce_v2_qp_context *qpc_mask) 3899 { 3900 roce_set_field(context->byte_4_sqpn_tst, 3901 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S, 3902 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 3903 hr_qp->sge.sge_shift)); 3904 3905 roce_set_field(context->byte_20_smac_sgid_idx, 3906 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 3907 ilog2(hr_qp->sq.wqe_cnt)); 3908 3909 roce_set_field(context->byte_20_smac_sgid_idx, 3910 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 3911 ilog2(hr_qp->rq.wqe_cnt)); 3912 } 3913 3914 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 3915 const struct ib_qp_attr *attr, 3916 int attr_mask, 3917 struct hns_roce_v2_qp_context *context, 3918 struct hns_roce_v2_qp_context *qpc_mask) 3919 { 3920 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3921 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3922 3923 /* 3924 * In v2 engine, software pass context and context mask to hardware 3925 * when modifying qp. If software need modify some fields in context, 3926 * we should set all bits of the relevant fields in context mask to 3927 * 0 at the same time, else set them to 0x1. 3928 */ 3929 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3930 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3931 3932 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3933 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3934 3935 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3936 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3937 3938 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 3939 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 3940 3941 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 3942 3943 /* No VLAN need to set 0xFFF */ 3944 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 3945 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); 3946 3947 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 3948 roce_set_bit(context->byte_68_rq_db, 3949 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 3950 3951 roce_set_field(context->byte_68_rq_db, 3952 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 3953 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 3954 ((u32)hr_qp->rdb.dma) >> 1); 3955 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32); 3956 3957 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 3958 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 3959 3960 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3961 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3962 if (ibqp->srq) { 3963 roce_set_field(context->byte_76_srqn_op_en, 3964 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3965 to_hr_srq(ibqp->srq)->srqn); 3966 roce_set_bit(context->byte_76_srqn_op_en, 3967 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3968 } 3969 3970 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); 3971 3972 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3973 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3974 3975 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 3976 return; 3977 3978 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3979 hr_reg_enable(&context->ext, QPCEX_STASH); 3980 } 3981 3982 static void modify_qp_init_to_init(struct ib_qp *ibqp, 3983 const struct ib_qp_attr *attr, int attr_mask, 3984 struct hns_roce_v2_qp_context *context, 3985 struct hns_roce_v2_qp_context *qpc_mask) 3986 { 3987 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3988 3989 /* 3990 * In v2 engine, software pass context and context mask to hardware 3991 * when modifying qp. If software need modify some fields in context, 3992 * we should set all bits of the relevant fields in context mask to 3993 * 0 at the same time, else set them to 0x1. 3994 */ 3995 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3996 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3997 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3998 V2_QPC_BYTE_4_TST_S, 0); 3999 4000 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 4001 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 4002 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 4003 V2_QPC_BYTE_16_PD_S, 0); 4004 4005 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 4006 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 4007 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 4008 V2_QPC_BYTE_80_RX_CQN_S, 0); 4009 4010 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 4011 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 4012 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 4013 V2_QPC_BYTE_252_TX_CQN_S, 0); 4014 4015 if (ibqp->srq) { 4016 roce_set_bit(context->byte_76_srqn_op_en, 4017 V2_QPC_BYTE_76_SRQ_EN_S, 1); 4018 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 4019 V2_QPC_BYTE_76_SRQ_EN_S, 0); 4020 roce_set_field(context->byte_76_srqn_op_en, 4021 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 4022 to_hr_srq(ibqp->srq)->srqn); 4023 roce_set_field(qpc_mask->byte_76_srqn_op_en, 4024 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 4025 } 4026 4027 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 4028 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 4029 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 4030 V2_QPC_BYTE_4_SQPN_S, 0); 4031 4032 if (attr_mask & IB_QP_DEST_QPN) { 4033 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 4034 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 4035 roce_set_field(qpc_mask->byte_56_dqpn_err, 4036 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 4037 } 4038 } 4039 4040 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4041 struct hns_roce_qp *hr_qp, 4042 struct hns_roce_v2_qp_context *context, 4043 struct hns_roce_v2_qp_context *qpc_mask) 4044 { 4045 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4046 u64 wqe_sge_ba; 4047 int count; 4048 4049 /* Search qp buf's mtts */ 4050 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4051 MTT_MIN_COUNT, &wqe_sge_ba); 4052 if (hr_qp->rq.wqe_cnt && count < 1) { 4053 ibdev_err(&hr_dev->ib_dev, 4054 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4055 return -EINVAL; 4056 } 4057 4058 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4059 qpc_mask->wqe_sge_ba = 0; 4060 4061 /* 4062 * In v2 engine, software pass context and context mask to hardware 4063 * when modifying qp. If software need modify some fields in context, 4064 * we should set all bits of the relevant fields in context mask to 4065 * 0 at the same time, else set them to 0x1. 4066 */ 4067 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 4068 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3)); 4069 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 4070 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 4071 4072 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 4073 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 4074 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4075 hr_qp->sq.wqe_cnt)); 4076 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 4077 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 4078 4079 roce_set_field(context->byte_20_smac_sgid_idx, 4080 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 4081 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 4082 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4083 hr_qp->sge.sge_cnt)); 4084 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4085 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 4086 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 4087 4088 roce_set_field(context->byte_20_smac_sgid_idx, 4089 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 4090 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 4091 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4092 hr_qp->rq.wqe_cnt)); 4093 4094 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4095 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 4096 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 4097 4098 roce_set_field(context->byte_16_buf_ba_pg_sz, 4099 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 4100 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 4101 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4102 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 4103 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 4104 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 4105 4106 roce_set_field(context->byte_16_buf_ba_pg_sz, 4107 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 4108 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 4109 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4110 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 4111 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 4112 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 4113 4114 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4115 qpc_mask->rq_cur_blk_addr = 0; 4116 4117 roce_set_field(context->byte_92_srq_info, 4118 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 4119 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 4120 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4121 roce_set_field(qpc_mask->byte_92_srq_info, 4122 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 4123 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 4124 4125 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4126 qpc_mask->rq_nxt_blk_addr = 0; 4127 4128 roce_set_field(context->byte_104_rq_sge, 4129 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 4130 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 4131 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4132 roce_set_field(qpc_mask->byte_104_rq_sge, 4133 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 4134 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 4135 4136 roce_set_field(context->byte_84_rq_ci_pi, 4137 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4138 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 4139 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4140 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4141 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 4142 4143 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4144 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 4145 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 4146 4147 return 0; 4148 } 4149 4150 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4151 struct hns_roce_qp *hr_qp, 4152 struct hns_roce_v2_qp_context *context, 4153 struct hns_roce_v2_qp_context *qpc_mask) 4154 { 4155 struct ib_device *ibdev = &hr_dev->ib_dev; 4156 u64 sge_cur_blk = 0; 4157 u64 sq_cur_blk = 0; 4158 int count; 4159 4160 /* search qp buf's mtts */ 4161 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4162 if (count < 1) { 4163 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4164 hr_qp->qpn); 4165 return -EINVAL; 4166 } 4167 if (hr_qp->sge.sge_cnt > 0) { 4168 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4169 hr_qp->sge.offset, 4170 &sge_cur_blk, 1, NULL); 4171 if (count < 1) { 4172 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4173 hr_qp->qpn); 4174 return -EINVAL; 4175 } 4176 } 4177 4178 /* 4179 * In v2 engine, software pass context and context mask to hardware 4180 * when modifying qp. If software need modify some fields in context, 4181 * we should set all bits of the relevant fields in context mask to 4182 * 0 at the same time, else set them to 0x1. 4183 */ 4184 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 4185 roce_set_field(context->byte_168_irrl_idx, 4186 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 4187 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 4188 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4189 qpc_mask->sq_cur_blk_addr = 0; 4190 roce_set_field(qpc_mask->byte_168_irrl_idx, 4191 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 4192 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 4193 4194 context->sq_cur_sge_blk_addr = 4195 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)); 4196 roce_set_field(context->byte_184_irrl_idx, 4197 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 4198 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 4199 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4200 qpc_mask->sq_cur_sge_blk_addr = 0; 4201 roce_set_field(qpc_mask->byte_184_irrl_idx, 4202 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 4203 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 4204 4205 context->rx_sq_cur_blk_addr = 4206 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 4207 roce_set_field(context->byte_232_irrl_sge, 4208 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 4209 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 4210 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4211 qpc_mask->rx_sq_cur_blk_addr = 0; 4212 roce_set_field(qpc_mask->byte_232_irrl_sge, 4213 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 4214 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 4215 4216 return 0; 4217 } 4218 4219 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4220 const struct ib_qp_attr *attr) 4221 { 4222 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4223 return IB_MTU_4096; 4224 4225 return attr->path_mtu; 4226 } 4227 4228 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4229 const struct ib_qp_attr *attr, int attr_mask, 4230 struct hns_roce_v2_qp_context *context, 4231 struct hns_roce_v2_qp_context *qpc_mask) 4232 { 4233 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4234 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4235 struct ib_device *ibdev = &hr_dev->ib_dev; 4236 dma_addr_t trrl_ba; 4237 dma_addr_t irrl_ba; 4238 enum ib_mtu mtu; 4239 u8 lp_pktn_ini; 4240 u64 *mtts; 4241 u8 *dmac; 4242 u8 *smac; 4243 int port; 4244 int ret; 4245 4246 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4247 if (ret) { 4248 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4249 return ret; 4250 } 4251 4252 /* Search IRRL's mtts */ 4253 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4254 hr_qp->qpn, &irrl_ba); 4255 if (!mtts) { 4256 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4257 return -EINVAL; 4258 } 4259 4260 /* Search TRRL's mtts */ 4261 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4262 hr_qp->qpn, &trrl_ba); 4263 if (!mtts) { 4264 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4265 return -EINVAL; 4266 } 4267 4268 if (attr_mask & IB_QP_ALT_PATH) { 4269 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4270 attr_mask); 4271 return -EINVAL; 4272 } 4273 4274 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 4275 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4); 4276 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 4277 V2_QPC_BYTE_132_TRRL_BA_S, 0); 4278 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4279 qpc_mask->trrl_ba = 0; 4280 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4281 V2_QPC_BYTE_140_TRRL_BA_S, 4282 (u32)(trrl_ba >> (32 + 16 + 4))); 4283 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4284 V2_QPC_BYTE_140_TRRL_BA_S, 0); 4285 4286 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4287 qpc_mask->irrl_ba = 0; 4288 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4289 V2_QPC_BYTE_208_IRRL_BA_S, 4290 irrl_ba >> (32 + 6)); 4291 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4292 V2_QPC_BYTE_208_IRRL_BA_S, 0); 4293 4294 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 4295 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 4296 4297 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4298 hr_qp->sq_signal_bits); 4299 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4300 0); 4301 4302 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4303 4304 smac = (u8 *)hr_dev->dev_addr[port]; 4305 dmac = (u8 *)attr->ah_attr.roce.dmac; 4306 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4307 if (ether_addr_equal_unaligned(dmac, smac) || 4308 hr_dev->loop_idc == 0x1) { 4309 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 4310 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 4311 } 4312 4313 if (attr_mask & IB_QP_DEST_QPN) { 4314 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 4315 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 4316 roce_set_field(qpc_mask->byte_56_dqpn_err, 4317 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 4318 } 4319 4320 memcpy(&(context->dmac), dmac, sizeof(u32)); 4321 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4322 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 4323 qpc_mask->dmac = 0; 4324 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4325 V2_QPC_BYTE_52_DMAC_S, 0); 4326 4327 mtu = get_mtu(ibqp, attr); 4328 hr_qp->path_mtu = mtu; 4329 4330 if (attr_mask & IB_QP_PATH_MTU) { 4331 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4332 V2_QPC_BYTE_24_MTU_S, mtu); 4333 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4334 V2_QPC_BYTE_24_MTU_S, 0); 4335 } 4336 4337 #define MAX_LP_MSG_LEN 65536 4338 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 64KB */ 4339 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu)); 4340 4341 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4342 V2_QPC_BYTE_56_LP_PKTN_INI_S, lp_pktn_ini); 4343 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4344 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 4345 4346 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4347 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 4348 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, lp_pktn_ini); 4349 roce_set_field(qpc_mask->byte_172_sq_psn, 4350 V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 4351 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0); 4352 4353 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4354 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 4355 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 4356 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 4357 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4358 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 4359 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 4360 4361 context->rq_rnr_timer = 0; 4362 qpc_mask->rq_rnr_timer = 0; 4363 4364 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 4365 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 4366 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 4367 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 4368 4369 /* rocee send 2^lp_sgen_ini segs every time */ 4370 roce_set_field(context->byte_168_irrl_idx, 4371 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4372 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 4373 roce_set_field(qpc_mask->byte_168_irrl_idx, 4374 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4375 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 4376 4377 return 0; 4378 } 4379 4380 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4381 const struct ib_qp_attr *attr, int attr_mask, 4382 struct hns_roce_v2_qp_context *context, 4383 struct hns_roce_v2_qp_context *qpc_mask) 4384 { 4385 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4386 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4387 struct ib_device *ibdev = &hr_dev->ib_dev; 4388 int ret; 4389 4390 /* Not support alternate path and path migration */ 4391 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4392 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4393 return -EINVAL; 4394 } 4395 4396 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4397 if (ret) { 4398 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4399 return ret; 4400 } 4401 4402 /* 4403 * Set some fields in context to zero, Because the default values 4404 * of all fields in context are zero, we need not set them to 0 again. 4405 * but we should set the relevant fields of context mask to 0. 4406 */ 4407 roce_set_field(qpc_mask->byte_232_irrl_sge, 4408 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 4409 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 4410 4411 roce_set_field(qpc_mask->byte_240_irrl_tail, 4412 V2_QPC_BYTE_240_RX_ACK_MSN_M, 4413 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 4414 4415 roce_set_field(qpc_mask->byte_248_ack_psn, 4416 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 4417 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 4418 roce_set_bit(qpc_mask->byte_248_ack_psn, 4419 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 4420 roce_set_field(qpc_mask->byte_248_ack_psn, 4421 V2_QPC_BYTE_248_IRRL_PSN_M, 4422 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 4423 4424 roce_set_field(qpc_mask->byte_240_irrl_tail, 4425 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 4426 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 4427 4428 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4429 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 4430 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 4431 4432 roce_set_bit(qpc_mask->byte_248_ack_psn, 4433 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 4434 4435 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 4436 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 4437 4438 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4439 V2_QPC_BYTE_212_LSN_S, 0x100); 4440 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4441 V2_QPC_BYTE_212_LSN_S, 0); 4442 4443 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 4444 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 4445 4446 return 0; 4447 } 4448 4449 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn) 4450 { 4451 if (!fl) 4452 fl = rdma_calc_flow_label(lqpn, rqpn); 4453 4454 return rdma_flow_label_to_udp_sport(fl); 4455 } 4456 4457 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4458 const struct ib_qp_attr *attr, 4459 int attr_mask, 4460 struct hns_roce_v2_qp_context *context, 4461 struct hns_roce_v2_qp_context *qpc_mask) 4462 { 4463 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4464 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4465 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4466 struct ib_device *ibdev = &hr_dev->ib_dev; 4467 const struct ib_gid_attr *gid_attr = NULL; 4468 int is_roce_protocol; 4469 u16 vlan_id = 0xffff; 4470 bool is_udp = false; 4471 u8 ib_port; 4472 u8 hr_port; 4473 int ret; 4474 4475 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4476 hr_port = ib_port - 1; 4477 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4478 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4479 4480 if (is_roce_protocol) { 4481 gid_attr = attr->ah_attr.grh.sgid_attr; 4482 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4483 if (ret) 4484 return ret; 4485 4486 if (gid_attr) 4487 is_udp = (gid_attr->gid_type == 4488 IB_GID_TYPE_ROCE_UDP_ENCAP); 4489 } 4490 4491 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4492 if (vlan_id < VLAN_N_VID && 4493 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4494 roce_set_bit(context->byte_76_srqn_op_en, 4495 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1); 4496 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 4497 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0); 4498 roce_set_bit(context->byte_168_irrl_idx, 4499 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1); 4500 roce_set_bit(qpc_mask->byte_168_irrl_idx, 4501 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0); 4502 } 4503 4504 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4505 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id); 4506 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4507 V2_QPC_BYTE_24_VLAN_ID_S, 0); 4508 4509 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4510 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4511 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4512 return -EINVAL; 4513 } 4514 4515 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4516 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4517 return -EINVAL; 4518 } 4519 4520 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4521 V2_QPC_BYTE_52_UDPSPN_S, 4522 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num, 4523 attr->dest_qp_num) : 0); 4524 4525 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4526 V2_QPC_BYTE_52_UDPSPN_S, 0); 4527 4528 roce_set_field(context->byte_20_smac_sgid_idx, 4529 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4530 grh->sgid_index); 4531 4532 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4533 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4534 4535 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4536 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 4537 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4538 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 4539 4540 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4541 V2_QPC_BYTE_24_TC_S, get_tclass(&attr->ah_attr.grh)); 4542 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4543 V2_QPC_BYTE_24_TC_S, 0); 4544 4545 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4546 V2_QPC_BYTE_28_FL_S, grh->flow_label); 4547 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4548 V2_QPC_BYTE_28_FL_S, 0); 4549 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4550 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4551 4552 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4553 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4554 ibdev_err(ibdev, 4555 "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n", 4556 hr_qp->sl, MAX_SERVICE_LEVEL); 4557 return -EINVAL; 4558 } 4559 4560 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4561 V2_QPC_BYTE_28_SL_S, hr_qp->sl); 4562 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4563 V2_QPC_BYTE_28_SL_S, 0); 4564 4565 return 0; 4566 } 4567 4568 static bool check_qp_state(enum ib_qp_state cur_state, 4569 enum ib_qp_state new_state) 4570 { 4571 static const bool sm[][IB_QPS_ERR + 1] = { 4572 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4573 [IB_QPS_INIT] = true }, 4574 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4575 [IB_QPS_INIT] = true, 4576 [IB_QPS_RTR] = true, 4577 [IB_QPS_ERR] = true }, 4578 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4579 [IB_QPS_RTS] = true, 4580 [IB_QPS_ERR] = true }, 4581 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4582 [IB_QPS_RTS] = true, 4583 [IB_QPS_ERR] = true }, 4584 [IB_QPS_SQD] = {}, 4585 [IB_QPS_SQE] = {}, 4586 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4587 }; 4588 4589 return sm[cur_state][new_state]; 4590 } 4591 4592 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4593 const struct ib_qp_attr *attr, 4594 int attr_mask, 4595 enum ib_qp_state cur_state, 4596 enum ib_qp_state new_state, 4597 struct hns_roce_v2_qp_context *context, 4598 struct hns_roce_v2_qp_context *qpc_mask) 4599 { 4600 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4601 int ret = 0; 4602 4603 if (!check_qp_state(cur_state, new_state)) { 4604 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4605 return -EINVAL; 4606 } 4607 4608 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4609 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4610 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4611 qpc_mask); 4612 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4613 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4614 qpc_mask); 4615 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4616 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4617 qpc_mask); 4618 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4619 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4620 qpc_mask); 4621 } 4622 4623 return ret; 4624 } 4625 4626 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4627 const struct ib_qp_attr *attr, 4628 int attr_mask, 4629 struct hns_roce_v2_qp_context *context, 4630 struct hns_roce_v2_qp_context *qpc_mask) 4631 { 4632 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4633 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4634 int ret = 0; 4635 4636 if (attr_mask & IB_QP_AV) { 4637 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4638 qpc_mask); 4639 if (ret) 4640 return ret; 4641 } 4642 4643 if (attr_mask & IB_QP_TIMEOUT) { 4644 if (attr->timeout < 31) { 4645 roce_set_field(context->byte_28_at_fl, 4646 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4647 attr->timeout); 4648 roce_set_field(qpc_mask->byte_28_at_fl, 4649 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4650 0); 4651 } else { 4652 ibdev_warn(&hr_dev->ib_dev, 4653 "Local ACK timeout shall be 0 to 30.\n"); 4654 } 4655 } 4656 4657 if (attr_mask & IB_QP_RETRY_CNT) { 4658 roce_set_field(context->byte_212_lsn, 4659 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4660 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 4661 attr->retry_cnt); 4662 roce_set_field(qpc_mask->byte_212_lsn, 4663 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4664 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 4665 4666 roce_set_field(context->byte_212_lsn, 4667 V2_QPC_BYTE_212_RETRY_CNT_M, 4668 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 4669 roce_set_field(qpc_mask->byte_212_lsn, 4670 V2_QPC_BYTE_212_RETRY_CNT_M, 4671 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 4672 } 4673 4674 if (attr_mask & IB_QP_RNR_RETRY) { 4675 roce_set_field(context->byte_244_rnr_rxack, 4676 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4677 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 4678 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4679 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4680 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 4681 4682 roce_set_field(context->byte_244_rnr_rxack, 4683 V2_QPC_BYTE_244_RNR_CNT_M, 4684 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 4685 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4686 V2_QPC_BYTE_244_RNR_CNT_M, 4687 V2_QPC_BYTE_244_RNR_CNT_S, 0); 4688 } 4689 4690 /* RC&UC&UD required attr */ 4691 if (attr_mask & IB_QP_SQ_PSN) { 4692 roce_set_field(context->byte_172_sq_psn, 4693 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4694 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 4695 roce_set_field(qpc_mask->byte_172_sq_psn, 4696 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4697 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 4698 4699 roce_set_field(context->byte_196_sq_psn, 4700 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4701 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 4702 roce_set_field(qpc_mask->byte_196_sq_psn, 4703 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4704 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 4705 4706 roce_set_field(context->byte_220_retry_psn_msn, 4707 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4708 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 4709 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4710 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4711 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 4712 4713 roce_set_field(context->byte_224_retry_msg, 4714 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4715 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 4716 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S); 4717 roce_set_field(qpc_mask->byte_224_retry_msg, 4718 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4719 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 4720 4721 roce_set_field(context->byte_224_retry_msg, 4722 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4723 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 4724 attr->sq_psn); 4725 roce_set_field(qpc_mask->byte_224_retry_msg, 4726 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4727 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 4728 4729 roce_set_field(context->byte_244_rnr_rxack, 4730 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4731 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 4732 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4733 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4734 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 4735 } 4736 4737 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4738 attr->max_dest_rd_atomic) { 4739 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4740 V2_QPC_BYTE_140_RR_MAX_S, 4741 fls(attr->max_dest_rd_atomic - 1)); 4742 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4743 V2_QPC_BYTE_140_RR_MAX_S, 0); 4744 } 4745 4746 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4747 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 4748 V2_QPC_BYTE_208_SR_MAX_S, 4749 fls(attr->max_rd_atomic - 1)); 4750 roce_set_field(qpc_mask->byte_208_irrl, 4751 V2_QPC_BYTE_208_SR_MAX_M, 4752 V2_QPC_BYTE_208_SR_MAX_S, 0); 4753 } 4754 4755 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4756 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4757 4758 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4759 roce_set_field(context->byte_80_rnr_rx_cqn, 4760 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4761 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 4762 attr->min_rnr_timer); 4763 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 4764 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4765 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 4766 } 4767 4768 /* RC&UC required attr */ 4769 if (attr_mask & IB_QP_RQ_PSN) { 4770 roce_set_field(context->byte_108_rx_reqepsn, 4771 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4772 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 4773 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4774 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4775 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 4776 4777 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 4778 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 4779 roce_set_field(qpc_mask->byte_152_raq, 4780 V2_QPC_BYTE_152_RAQ_PSN_M, 4781 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 4782 } 4783 4784 if (attr_mask & IB_QP_QKEY) { 4785 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4786 qpc_mask->qkey_xrcd = 0; 4787 hr_qp->qkey = attr->qkey; 4788 } 4789 4790 return ret; 4791 } 4792 4793 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4794 const struct ib_qp_attr *attr, 4795 int attr_mask) 4796 { 4797 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4798 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4799 4800 if (attr_mask & IB_QP_ACCESS_FLAGS) 4801 hr_qp->atomic_rd_en = attr->qp_access_flags; 4802 4803 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4804 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4805 if (attr_mask & IB_QP_PORT) { 4806 hr_qp->port = attr->port_num - 1; 4807 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4808 } 4809 } 4810 4811 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4812 const struct ib_qp_attr *attr, 4813 int attr_mask, enum ib_qp_state cur_state, 4814 enum ib_qp_state new_state) 4815 { 4816 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4817 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4818 struct hns_roce_v2_qp_context ctx[2]; 4819 struct hns_roce_v2_qp_context *context = ctx; 4820 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4821 struct ib_device *ibdev = &hr_dev->ib_dev; 4822 unsigned long sq_flag = 0; 4823 unsigned long rq_flag = 0; 4824 int ret; 4825 4826 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 4827 return -EOPNOTSUPP; 4828 4829 /* 4830 * In v2 engine, software pass context and context mask to hardware 4831 * when modifying qp. If software need modify some fields in context, 4832 * we should set all bits of the relevant fields in context mask to 4833 * 0 at the same time, else set them to 0x1. 4834 */ 4835 memset(context, 0, hr_dev->caps.qpc_sz); 4836 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 4837 4838 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4839 new_state, context, qpc_mask); 4840 if (ret) 4841 goto out; 4842 4843 /* When QP state is err, SQ and RQ WQE should be flushed */ 4844 if (new_state == IB_QPS_ERR) { 4845 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4846 hr_qp->state = IB_QPS_ERR; 4847 roce_set_field(context->byte_160_sq_ci_pi, 4848 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4849 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 4850 hr_qp->sq.head); 4851 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 4852 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4853 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 4854 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4855 4856 if (!ibqp->srq) { 4857 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4858 roce_set_field(context->byte_84_rq_ci_pi, 4859 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4860 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 4861 hr_qp->rq.head); 4862 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4863 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4864 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 4865 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4866 } 4867 } 4868 4869 /* Configure the optional fields */ 4870 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 4871 qpc_mask); 4872 if (ret) 4873 goto out; 4874 4875 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 4876 ibqp->srq ? 1 : 0); 4877 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4878 V2_QPC_BYTE_108_INV_CREDIT_S, 0); 4879 4880 /* Every status migrate must change state */ 4881 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4882 V2_QPC_BYTE_60_QP_ST_S, new_state); 4883 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4884 V2_QPC_BYTE_60_QP_ST_S, 0); 4885 4886 /* SW pass context to HW */ 4887 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 4888 if (ret) { 4889 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 4890 goto out; 4891 } 4892 4893 hr_qp->state = new_state; 4894 4895 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 4896 4897 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 4898 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 4899 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 4900 if (ibqp->send_cq != ibqp->recv_cq) 4901 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4902 hr_qp->qpn, NULL); 4903 4904 hr_qp->rq.head = 0; 4905 hr_qp->rq.tail = 0; 4906 hr_qp->sq.head = 0; 4907 hr_qp->sq.tail = 0; 4908 hr_qp->next_sge = 0; 4909 if (hr_qp->rq.wqe_cnt) 4910 *hr_qp->rdb.db_record = 0; 4911 } 4912 4913 out: 4914 return ret; 4915 } 4916 4917 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 4918 { 4919 static const enum ib_qp_state map[] = { 4920 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 4921 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 4922 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 4923 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 4924 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 4925 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 4926 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 4927 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 4928 }; 4929 4930 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 4931 } 4932 4933 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 4934 struct hns_roce_qp *hr_qp, 4935 struct hns_roce_v2_qp_context *hr_context) 4936 { 4937 struct hns_roce_cmd_mailbox *mailbox; 4938 int ret; 4939 4940 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4941 if (IS_ERR(mailbox)) 4942 return PTR_ERR(mailbox); 4943 4944 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 4945 HNS_ROCE_CMD_QUERY_QPC, 4946 HNS_ROCE_CMD_TIMEOUT_MSECS); 4947 if (ret) 4948 goto out; 4949 4950 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz); 4951 4952 out: 4953 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4954 return ret; 4955 } 4956 4957 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4958 int qp_attr_mask, 4959 struct ib_qp_init_attr *qp_init_attr) 4960 { 4961 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4962 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4963 struct hns_roce_v2_qp_context context = {}; 4964 struct ib_device *ibdev = &hr_dev->ib_dev; 4965 int tmp_qp_state; 4966 int state; 4967 int ret; 4968 4969 memset(qp_attr, 0, sizeof(*qp_attr)); 4970 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4971 4972 mutex_lock(&hr_qp->mutex); 4973 4974 if (hr_qp->state == IB_QPS_RESET) { 4975 qp_attr->qp_state = IB_QPS_RESET; 4976 ret = 0; 4977 goto done; 4978 } 4979 4980 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 4981 if (ret) { 4982 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 4983 ret = -EINVAL; 4984 goto out; 4985 } 4986 4987 state = roce_get_field(context.byte_60_qpst_tempid, 4988 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 4989 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 4990 if (tmp_qp_state == -1) { 4991 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 4992 ret = -EINVAL; 4993 goto out; 4994 } 4995 hr_qp->state = (u8)tmp_qp_state; 4996 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 4997 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc, 4998 V2_QPC_BYTE_24_MTU_M, 4999 V2_QPC_BYTE_24_MTU_S); 5000 qp_attr->path_mig_state = IB_MIG_ARMED; 5001 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5002 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5003 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5004 5005 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn, 5006 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 5007 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 5008 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn, 5009 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 5010 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 5011 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err, 5012 V2_QPC_BYTE_56_DQPN_M, 5013 V2_QPC_BYTE_56_DQPN_S); 5014 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en, 5015 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) | 5016 ((roce_get_bit(context.byte_76_srqn_op_en, 5017 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) | 5018 ((roce_get_bit(context.byte_76_srqn_op_en, 5019 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); 5020 5021 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5022 hr_qp->ibqp.qp_type == IB_QPT_UC) { 5023 struct ib_global_route *grh = 5024 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5025 5026 rdma_ah_set_sl(&qp_attr->ah_attr, 5027 roce_get_field(context.byte_28_at_fl, 5028 V2_QPC_BYTE_28_SL_M, 5029 V2_QPC_BYTE_28_SL_S)); 5030 grh->flow_label = roce_get_field(context.byte_28_at_fl, 5031 V2_QPC_BYTE_28_FL_M, 5032 V2_QPC_BYTE_28_FL_S); 5033 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx, 5034 V2_QPC_BYTE_20_SGID_IDX_M, 5035 V2_QPC_BYTE_20_SGID_IDX_S); 5036 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc, 5037 V2_QPC_BYTE_24_HOP_LIMIT_M, 5038 V2_QPC_BYTE_24_HOP_LIMIT_S); 5039 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc, 5040 V2_QPC_BYTE_24_TC_M, 5041 V2_QPC_BYTE_24_TC_S); 5042 5043 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5044 } 5045 5046 qp_attr->port_num = hr_qp->port + 1; 5047 qp_attr->sq_draining = 0; 5048 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl, 5049 V2_QPC_BYTE_208_SR_MAX_M, 5050 V2_QPC_BYTE_208_SR_MAX_S); 5051 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, 5052 V2_QPC_BYTE_140_RR_MAX_M, 5053 V2_QPC_BYTE_140_RR_MAX_S); 5054 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, 5055 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 5056 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 5057 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl, 5058 V2_QPC_BYTE_28_AT_M, 5059 V2_QPC_BYTE_28_AT_S); 5060 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn, 5061 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 5062 V2_QPC_BYTE_212_RETRY_NUM_INIT_S); 5063 qp_attr->rnr_retry = roce_get_field(context.byte_244_rnr_rxack, 5064 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 5065 V2_QPC_BYTE_244_RNR_NUM_INIT_S); 5066 5067 done: 5068 qp_attr->cur_qp_state = qp_attr->qp_state; 5069 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5070 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5071 5072 if (!ibqp->uobject) { 5073 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5074 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5075 } else { 5076 qp_attr->cap.max_send_wr = 0; 5077 qp_attr->cap.max_send_sge = 0; 5078 } 5079 5080 qp_init_attr->cap = qp_attr->cap; 5081 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5082 5083 out: 5084 mutex_unlock(&hr_qp->mutex); 5085 return ret; 5086 } 5087 5088 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5089 struct hns_roce_qp *hr_qp, 5090 struct ib_udata *udata) 5091 { 5092 struct ib_device *ibdev = &hr_dev->ib_dev; 5093 struct hns_roce_cq *send_cq, *recv_cq; 5094 unsigned long flags; 5095 int ret = 0; 5096 5097 if ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5098 hr_qp->ibqp.qp_type == IB_QPT_UD) && 5099 hr_qp->state != IB_QPS_RESET) { 5100 /* Modify qp to reset before destroying qp */ 5101 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5102 hr_qp->state, IB_QPS_RESET); 5103 if (ret) 5104 ibdev_err(ibdev, 5105 "failed to modify QP to RST, ret = %d.\n", 5106 ret); 5107 } 5108 5109 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5110 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5111 5112 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5113 hns_roce_lock_cqs(send_cq, recv_cq); 5114 5115 if (!udata) { 5116 if (recv_cq) 5117 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5118 (hr_qp->ibqp.srq ? 5119 to_hr_srq(hr_qp->ibqp.srq) : 5120 NULL)); 5121 5122 if (send_cq && send_cq != recv_cq) 5123 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5124 5125 } 5126 5127 hns_roce_qp_remove(hr_dev, hr_qp); 5128 5129 hns_roce_unlock_cqs(send_cq, recv_cq); 5130 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5131 5132 return ret; 5133 } 5134 5135 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5136 { 5137 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5138 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5139 int ret; 5140 5141 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5142 if (ret) 5143 ibdev_err(&hr_dev->ib_dev, 5144 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5145 hr_qp->qpn, ret); 5146 5147 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5148 5149 return 0; 5150 } 5151 5152 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5153 struct hns_roce_qp *hr_qp) 5154 { 5155 struct ib_device *ibdev = &hr_dev->ib_dev; 5156 struct hns_roce_sccc_clr_done *resp; 5157 struct hns_roce_sccc_clr *clr; 5158 struct hns_roce_cmq_desc desc; 5159 int ret, i; 5160 5161 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5162 return 0; 5163 5164 mutex_lock(&hr_dev->qp_table.scc_mutex); 5165 5166 /* set scc ctx clear done flag */ 5167 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5168 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5169 if (ret) { 5170 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5171 goto out; 5172 } 5173 5174 /* clear scc context */ 5175 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5176 clr = (struct hns_roce_sccc_clr *)desc.data; 5177 clr->qpn = cpu_to_le32(hr_qp->qpn); 5178 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5179 if (ret) { 5180 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5181 goto out; 5182 } 5183 5184 /* query scc context clear is done or not */ 5185 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5186 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5187 hns_roce_cmq_setup_basic_desc(&desc, 5188 HNS_ROCE_OPC_QUERY_SCCC, true); 5189 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5190 if (ret) { 5191 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5192 ret); 5193 goto out; 5194 } 5195 5196 if (resp->clr_done) 5197 goto out; 5198 5199 msleep(20); 5200 } 5201 5202 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 5203 ret = -ETIMEDOUT; 5204 5205 out: 5206 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5207 return ret; 5208 } 5209 5210 #define DMA_IDX_SHIFT 3 5211 #define DMA_WQE_SHIFT 3 5212 5213 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5214 struct hns_roce_srq_context *ctx) 5215 { 5216 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5217 struct ib_device *ibdev = srq->ibsrq.device; 5218 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5219 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5220 dma_addr_t dma_handle_idx = 0; 5221 int ret; 5222 5223 /* Get physical address of idx que buf */ 5224 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5225 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5226 if (ret < 1) { 5227 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5228 ret); 5229 return -ENOBUFS; 5230 } 5231 5232 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5233 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5234 5235 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5236 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5237 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5238 5239 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5240 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5241 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5242 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5243 5244 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5245 to_hr_hw_page_addr(mtts_idx[0])); 5246 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5247 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5248 5249 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5250 to_hr_hw_page_addr(mtts_idx[1])); 5251 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5252 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5253 5254 return 0; 5255 } 5256 5257 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5258 { 5259 struct ib_device *ibdev = srq->ibsrq.device; 5260 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5261 struct hns_roce_srq_context *ctx = mb_buf; 5262 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5263 dma_addr_t dma_handle_wqe = 0; 5264 int ret; 5265 5266 memset(ctx, 0, sizeof(*ctx)); 5267 5268 /* Get the physical address of srq buf */ 5269 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5270 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5271 if (ret < 1) { 5272 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5273 ret); 5274 return -ENOBUFS; 5275 } 5276 5277 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5278 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5279 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5280 hr_reg_write(ctx, SRQC_XRCD, 0); 5281 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5282 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5283 hr_reg_write(ctx, SRQC_RQWS, 5284 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5285 5286 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5287 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5288 srq->wqe_cnt)); 5289 5290 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5291 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5292 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5293 5294 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5295 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5296 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5297 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5298 5299 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5300 } 5301 5302 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5303 struct ib_srq_attr *srq_attr, 5304 enum ib_srq_attr_mask srq_attr_mask, 5305 struct ib_udata *udata) 5306 { 5307 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5308 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5309 struct hns_roce_srq_context *srq_context; 5310 struct hns_roce_srq_context *srqc_mask; 5311 struct hns_roce_cmd_mailbox *mailbox; 5312 int ret; 5313 5314 /* Resizing SRQs is not supported yet */ 5315 if (srq_attr_mask & IB_SRQ_MAX_WR) 5316 return -EINVAL; 5317 5318 if (srq_attr_mask & IB_SRQ_LIMIT) { 5319 if (srq_attr->srq_limit > srq->wqe_cnt) 5320 return -EINVAL; 5321 5322 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5323 if (IS_ERR(mailbox)) 5324 return PTR_ERR(mailbox); 5325 5326 srq_context = mailbox->buf; 5327 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5328 5329 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5330 5331 roce_set_field(srq_context->byte_8_limit_wl, 5332 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5333 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit); 5334 roce_set_field(srqc_mask->byte_8_limit_wl, 5335 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5336 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 5337 5338 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5339 HNS_ROCE_CMD_MODIFY_SRQC, 5340 HNS_ROCE_CMD_TIMEOUT_MSECS); 5341 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5342 if (ret) { 5343 ibdev_err(&hr_dev->ib_dev, 5344 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5345 ret); 5346 return ret; 5347 } 5348 } 5349 5350 return 0; 5351 } 5352 5353 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5354 { 5355 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5356 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5357 struct hns_roce_srq_context *srq_context; 5358 struct hns_roce_cmd_mailbox *mailbox; 5359 int limit_wl; 5360 int ret; 5361 5362 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5363 if (IS_ERR(mailbox)) 5364 return PTR_ERR(mailbox); 5365 5366 srq_context = mailbox->buf; 5367 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5368 HNS_ROCE_CMD_QUERY_SRQC, 5369 HNS_ROCE_CMD_TIMEOUT_MSECS); 5370 if (ret) { 5371 ibdev_err(&hr_dev->ib_dev, 5372 "failed to process cmd of querying SRQ, ret = %d.\n", 5373 ret); 5374 goto out; 5375 } 5376 5377 limit_wl = roce_get_field(srq_context->byte_8_limit_wl, 5378 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5379 SRQC_BYTE_8_SRQ_LIMIT_WL_S); 5380 5381 attr->srq_limit = limit_wl; 5382 attr->max_wr = srq->wqe_cnt; 5383 attr->max_sge = srq->max_gs - srq->rsv_sge; 5384 5385 out: 5386 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5387 return ret; 5388 } 5389 5390 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5391 { 5392 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5393 struct hns_roce_v2_cq_context *cq_context; 5394 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5395 struct hns_roce_v2_cq_context *cqc_mask; 5396 struct hns_roce_cmd_mailbox *mailbox; 5397 int ret; 5398 5399 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5400 if (IS_ERR(mailbox)) 5401 return PTR_ERR(mailbox); 5402 5403 cq_context = mailbox->buf; 5404 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5405 5406 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5407 5408 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5409 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5410 cq_count); 5411 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5412 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5413 0); 5414 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5415 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5416 cq_period); 5417 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5418 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5419 0); 5420 5421 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5422 HNS_ROCE_CMD_MODIFY_CQC, 5423 HNS_ROCE_CMD_TIMEOUT_MSECS); 5424 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5425 if (ret) 5426 ibdev_err(&hr_dev->ib_dev, 5427 "failed to process cmd when modifying CQ, ret = %d.\n", 5428 ret); 5429 5430 return ret; 5431 } 5432 5433 static void hns_roce_irq_work_handle(struct work_struct *work) 5434 { 5435 struct hns_roce_work *irq_work = 5436 container_of(work, struct hns_roce_work, work); 5437 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5438 5439 switch (irq_work->event_type) { 5440 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5441 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5442 break; 5443 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5444 ibdev_warn(ibdev, "Path migration failed.\n"); 5445 break; 5446 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5447 break; 5448 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5449 ibdev_warn(ibdev, "Send queue drained.\n"); 5450 break; 5451 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5452 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5453 irq_work->queue_num, irq_work->sub_type); 5454 break; 5455 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5456 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5457 irq_work->queue_num); 5458 break; 5459 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5460 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5461 irq_work->queue_num, irq_work->sub_type); 5462 break; 5463 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5464 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5465 break; 5466 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5467 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5468 break; 5469 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5470 ibdev_err(ibdev, "SRQ catas error.\n"); 5471 break; 5472 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5473 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5474 break; 5475 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5476 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5477 break; 5478 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5479 ibdev_warn(ibdev, "DB overflow.\n"); 5480 break; 5481 case HNS_ROCE_EVENT_TYPE_FLR: 5482 ibdev_warn(ibdev, "Function level reset.\n"); 5483 break; 5484 default: 5485 break; 5486 } 5487 5488 kfree(irq_work); 5489 } 5490 5491 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5492 struct hns_roce_eq *eq, u32 queue_num) 5493 { 5494 struct hns_roce_work *irq_work; 5495 5496 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5497 if (!irq_work) 5498 return; 5499 5500 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5501 irq_work->hr_dev = hr_dev; 5502 irq_work->event_type = eq->event_type; 5503 irq_work->sub_type = eq->sub_type; 5504 irq_work->queue_num = queue_num; 5505 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5506 } 5507 5508 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 5509 { 5510 struct hns_roce_dev *hr_dev = eq->hr_dev; 5511 __le32 doorbell[2] = {}; 5512 5513 if (eq->type_flag == HNS_ROCE_AEQ) { 5514 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5515 HNS_ROCE_V2_EQ_DB_CMD_S, 5516 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5517 HNS_ROCE_EQ_DB_CMD_AEQ : 5518 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5519 } else { 5520 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 5521 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 5522 5523 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5524 HNS_ROCE_V2_EQ_DB_CMD_S, 5525 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5526 HNS_ROCE_EQ_DB_CMD_CEQ : 5527 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5528 } 5529 5530 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 5531 HNS_ROCE_V2_EQ_DB_PARA_S, 5532 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 5533 5534 hns_roce_write64(hr_dev, doorbell, eq->doorbell); 5535 } 5536 5537 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5538 { 5539 struct hns_roce_aeqe *aeqe; 5540 5541 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5542 (eq->cons_index & (eq->entries - 1)) * 5543 eq->eqe_size); 5544 5545 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5546 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5547 } 5548 5549 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5550 struct hns_roce_eq *eq) 5551 { 5552 struct device *dev = hr_dev->dev; 5553 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5554 int aeqe_found = 0; 5555 int event_type; 5556 u32 queue_num; 5557 int sub_type; 5558 5559 while (aeqe) { 5560 /* Make sure we read AEQ entry after we have checked the 5561 * ownership bit 5562 */ 5563 dma_rmb(); 5564 5565 event_type = roce_get_field(aeqe->asyn, 5566 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5567 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5568 sub_type = roce_get_field(aeqe->asyn, 5569 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5570 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5571 queue_num = roce_get_field(aeqe->event.queue_event.num, 5572 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5573 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5574 5575 switch (event_type) { 5576 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5577 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5578 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5579 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5580 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5581 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5582 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5583 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5584 hns_roce_qp_event(hr_dev, queue_num, event_type); 5585 break; 5586 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5587 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5588 hns_roce_srq_event(hr_dev, queue_num, event_type); 5589 break; 5590 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5591 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5592 hns_roce_cq_event(hr_dev, queue_num, event_type); 5593 break; 5594 case HNS_ROCE_EVENT_TYPE_MB: 5595 hns_roce_cmd_event(hr_dev, 5596 le16_to_cpu(aeqe->event.cmd.token), 5597 aeqe->event.cmd.status, 5598 le64_to_cpu(aeqe->event.cmd.out_param)); 5599 break; 5600 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5601 case HNS_ROCE_EVENT_TYPE_FLR: 5602 break; 5603 default: 5604 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5605 event_type, eq->eqn, eq->cons_index); 5606 break; 5607 } 5608 5609 eq->event_type = event_type; 5610 eq->sub_type = sub_type; 5611 ++eq->cons_index; 5612 aeqe_found = 1; 5613 5614 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5615 5616 aeqe = next_aeqe_sw_v2(eq); 5617 } 5618 5619 set_eq_cons_index_v2(eq); 5620 return aeqe_found; 5621 } 5622 5623 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5624 { 5625 struct hns_roce_ceqe *ceqe; 5626 5627 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5628 (eq->cons_index & (eq->entries - 1)) * 5629 eq->eqe_size); 5630 5631 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5632 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5633 } 5634 5635 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5636 struct hns_roce_eq *eq) 5637 { 5638 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5639 int ceqe_found = 0; 5640 u32 cqn; 5641 5642 while (ceqe) { 5643 /* Make sure we read CEQ entry after we have checked the 5644 * ownership bit 5645 */ 5646 dma_rmb(); 5647 5648 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5649 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5650 5651 hns_roce_cq_completion(hr_dev, cqn); 5652 5653 ++eq->cons_index; 5654 ceqe_found = 1; 5655 5656 ceqe = next_ceqe_sw_v2(eq); 5657 } 5658 5659 set_eq_cons_index_v2(eq); 5660 5661 return ceqe_found; 5662 } 5663 5664 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5665 { 5666 struct hns_roce_eq *eq = eq_ptr; 5667 struct hns_roce_dev *hr_dev = eq->hr_dev; 5668 int int_work; 5669 5670 if (eq->type_flag == HNS_ROCE_CEQ) 5671 /* Completion event interrupt */ 5672 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5673 else 5674 /* Asychronous event interrupt */ 5675 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5676 5677 return IRQ_RETVAL(int_work); 5678 } 5679 5680 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5681 { 5682 struct hns_roce_dev *hr_dev = dev_id; 5683 struct device *dev = hr_dev->dev; 5684 int int_work = 0; 5685 u32 int_st; 5686 u32 int_en; 5687 5688 /* Abnormal interrupt */ 5689 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5690 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5691 5692 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5693 struct pci_dev *pdev = hr_dev->pci_dev; 5694 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5695 const struct hnae3_ae_ops *ops = ae_dev->ops; 5696 5697 dev_err(dev, "AEQ overflow!\n"); 5698 5699 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5700 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5701 5702 /* Set reset level for reset_event() */ 5703 if (ops->set_default_reset_request) 5704 ops->set_default_reset_request(ae_dev, 5705 HNAE3_FUNC_RESET); 5706 if (ops->reset_event) 5707 ops->reset_event(pdev, NULL); 5708 5709 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5710 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5711 5712 int_work = 1; 5713 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 5714 dev_err(dev, "BUS ERR!\n"); 5715 5716 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S; 5717 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5718 5719 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5720 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5721 5722 int_work = 1; 5723 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 5724 dev_err(dev, "OTHER ERR!\n"); 5725 5726 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S; 5727 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5728 5729 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5730 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5731 5732 int_work = 1; 5733 } else 5734 dev_err(dev, "There is no abnormal irq found!\n"); 5735 5736 return IRQ_RETVAL(int_work); 5737 } 5738 5739 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5740 int eq_num, int enable_flag) 5741 { 5742 int i; 5743 5744 if (enable_flag == EQ_ENABLE) { 5745 for (i = 0; i < eq_num; i++) 5746 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5747 i * EQ_REG_OFFSET, 5748 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 5749 5750 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5751 HNS_ROCE_V2_VF_ABN_INT_EN_M); 5752 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5753 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 5754 } else { 5755 for (i = 0; i < eq_num; i++) 5756 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5757 i * EQ_REG_OFFSET, 5758 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 5759 5760 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5761 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 5762 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5763 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 5764 } 5765 } 5766 5767 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5768 { 5769 struct device *dev = hr_dev->dev; 5770 int ret; 5771 5772 if (eqn < hr_dev->caps.num_comp_vectors) 5773 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5774 0, HNS_ROCE_CMD_DESTROY_CEQC, 5775 HNS_ROCE_CMD_TIMEOUT_MSECS); 5776 else 5777 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5778 0, HNS_ROCE_CMD_DESTROY_AEQC, 5779 HNS_ROCE_CMD_TIMEOUT_MSECS); 5780 if (ret) 5781 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5782 } 5783 5784 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5785 { 5786 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5787 } 5788 5789 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5790 void *mb_buf) 5791 { 5792 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5793 struct hns_roce_eq_context *eqc; 5794 u64 bt_ba = 0; 5795 int count; 5796 5797 eqc = mb_buf; 5798 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5799 5800 /* init eqc */ 5801 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5802 eq->cons_index = 0; 5803 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5804 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5805 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5806 eq->shift = ilog2((unsigned int)eq->entries); 5807 5808 /* if not multi-hop, eqe buffer only use one trunk */ 5809 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5810 &bt_ba); 5811 if (count < 1) { 5812 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5813 return -ENOBUFS; 5814 } 5815 5816 /* set eqc state */ 5817 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, 5818 HNS_ROCE_V2_EQ_STATE_VALID); 5819 5820 /* set eqe hop num */ 5821 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, 5822 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 5823 5824 /* set eqc over_ignore */ 5825 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, 5826 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 5827 5828 /* set eqc coalesce */ 5829 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M, 5830 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 5831 5832 /* set eqc arm_state */ 5833 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, 5834 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 5835 5836 /* set eqn */ 5837 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, 5838 eq->eqn); 5839 5840 /* set eqe_cnt */ 5841 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, 5842 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); 5843 5844 /* set eqe_ba_pg_sz */ 5845 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M, 5846 HNS_ROCE_EQC_BA_PG_SZ_S, 5847 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5848 5849 /* set eqe_buf_pg_sz */ 5850 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M, 5851 HNS_ROCE_EQC_BUF_PG_SZ_S, 5852 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5853 5854 /* set eq_producer_idx */ 5855 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M, 5856 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX); 5857 5858 /* set eq_max_cnt */ 5859 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M, 5860 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 5861 5862 /* set eq_period */ 5863 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M, 5864 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 5865 5866 /* set eqe_report_timer */ 5867 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M, 5868 HNS_ROCE_EQC_REPORT_TIMER_S, 5869 HNS_ROCE_EQ_INIT_REPORT_TIMER); 5870 5871 /* set bt_ba [34:3] */ 5872 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M, 5873 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3); 5874 5875 /* set bt_ba [64:35] */ 5876 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M, 5877 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35); 5878 5879 /* set eq shift */ 5880 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S, 5881 eq->shift); 5882 5883 /* set eq MSI_IDX */ 5884 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M, 5885 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX); 5886 5887 /* set cur_eqe_ba [27:12] */ 5888 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M, 5889 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12); 5890 5891 /* set cur_eqe_ba [59:28] */ 5892 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M, 5893 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28); 5894 5895 /* set cur_eqe_ba [63:60] */ 5896 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M, 5897 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60); 5898 5899 /* set eq consumer idx */ 5900 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M, 5901 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX); 5902 5903 roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M, 5904 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12); 5905 5906 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M, 5907 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44); 5908 5909 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M, 5910 HNS_ROCE_EQC_EQE_SIZE_S, 5911 eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0); 5912 5913 return 0; 5914 } 5915 5916 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5917 { 5918 struct hns_roce_buf_attr buf_attr = {}; 5919 int err; 5920 5921 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5922 eq->hop_num = 0; 5923 else 5924 eq->hop_num = hr_dev->caps.eqe_hop_num; 5925 5926 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT; 5927 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5928 buf_attr.region[0].hopnum = eq->hop_num; 5929 buf_attr.region_count = 1; 5930 5931 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5932 hr_dev->caps.eqe_ba_pg_sz + 5933 HNS_HW_PAGE_SHIFT, NULL, 0); 5934 if (err) 5935 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5936 5937 return err; 5938 } 5939 5940 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5941 struct hns_roce_eq *eq, 5942 unsigned int eq_cmd) 5943 { 5944 struct hns_roce_cmd_mailbox *mailbox; 5945 int ret; 5946 5947 /* Allocate mailbox memory */ 5948 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5949 if (IS_ERR_OR_NULL(mailbox)) 5950 return -ENOMEM; 5951 5952 ret = alloc_eq_buf(hr_dev, eq); 5953 if (ret) 5954 goto free_cmd_mbox; 5955 5956 ret = config_eqc(hr_dev, eq, mailbox->buf); 5957 if (ret) 5958 goto err_cmd_mbox; 5959 5960 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5961 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5962 if (ret) { 5963 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5964 goto err_cmd_mbox; 5965 } 5966 5967 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5968 5969 return 0; 5970 5971 err_cmd_mbox: 5972 free_eq_buf(hr_dev, eq); 5973 5974 free_cmd_mbox: 5975 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5976 5977 return ret; 5978 } 5979 5980 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5981 int comp_num, int aeq_num, int other_num) 5982 { 5983 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5984 int i, j; 5985 int ret; 5986 5987 for (i = 0; i < irq_num; i++) { 5988 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5989 GFP_KERNEL); 5990 if (!hr_dev->irq_names[i]) { 5991 ret = -ENOMEM; 5992 goto err_kzalloc_failed; 5993 } 5994 } 5995 5996 /* irq contains: abnormal + AEQ + CEQ */ 5997 for (j = 0; j < other_num; j++) 5998 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5999 "hns-abn-%d", j); 6000 6001 for (j = other_num; j < (other_num + aeq_num); j++) 6002 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6003 "hns-aeq-%d", j - other_num); 6004 6005 for (j = (other_num + aeq_num); j < irq_num; j++) 6006 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6007 "hns-ceq-%d", j - other_num - aeq_num); 6008 6009 for (j = 0; j < irq_num; j++) { 6010 if (j < other_num) 6011 ret = request_irq(hr_dev->irq[j], 6012 hns_roce_v2_msix_interrupt_abn, 6013 0, hr_dev->irq_names[j], hr_dev); 6014 6015 else if (j < (other_num + comp_num)) 6016 ret = request_irq(eq_table->eq[j - other_num].irq, 6017 hns_roce_v2_msix_interrupt_eq, 6018 0, hr_dev->irq_names[j + aeq_num], 6019 &eq_table->eq[j - other_num]); 6020 else 6021 ret = request_irq(eq_table->eq[j - other_num].irq, 6022 hns_roce_v2_msix_interrupt_eq, 6023 0, hr_dev->irq_names[j - comp_num], 6024 &eq_table->eq[j - other_num]); 6025 if (ret) { 6026 dev_err(hr_dev->dev, "Request irq error!\n"); 6027 goto err_request_failed; 6028 } 6029 } 6030 6031 return 0; 6032 6033 err_request_failed: 6034 for (j -= 1; j >= 0; j--) 6035 if (j < other_num) 6036 free_irq(hr_dev->irq[j], hr_dev); 6037 else 6038 free_irq(eq_table->eq[j - other_num].irq, 6039 &eq_table->eq[j - other_num]); 6040 6041 err_kzalloc_failed: 6042 for (i -= 1; i >= 0; i--) 6043 kfree(hr_dev->irq_names[i]); 6044 6045 return ret; 6046 } 6047 6048 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6049 { 6050 int irq_num; 6051 int eq_num; 6052 int i; 6053 6054 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6055 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6056 6057 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6058 free_irq(hr_dev->irq[i], hr_dev); 6059 6060 for (i = 0; i < eq_num; i++) 6061 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6062 6063 for (i = 0; i < irq_num; i++) 6064 kfree(hr_dev->irq_names[i]); 6065 } 6066 6067 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6068 { 6069 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6070 struct device *dev = hr_dev->dev; 6071 struct hns_roce_eq *eq; 6072 unsigned int eq_cmd; 6073 int irq_num; 6074 int eq_num; 6075 int other_num; 6076 int comp_num; 6077 int aeq_num; 6078 int i; 6079 int ret; 6080 6081 other_num = hr_dev->caps.num_other_vectors; 6082 comp_num = hr_dev->caps.num_comp_vectors; 6083 aeq_num = hr_dev->caps.num_aeq_vectors; 6084 6085 eq_num = comp_num + aeq_num; 6086 irq_num = eq_num + other_num; 6087 6088 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6089 if (!eq_table->eq) 6090 return -ENOMEM; 6091 6092 /* create eq */ 6093 for (i = 0; i < eq_num; i++) { 6094 eq = &eq_table->eq[i]; 6095 eq->hr_dev = hr_dev; 6096 eq->eqn = i; 6097 if (i < comp_num) { 6098 /* CEQ */ 6099 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6100 eq->type_flag = HNS_ROCE_CEQ; 6101 eq->entries = hr_dev->caps.ceqe_depth; 6102 eq->eqe_size = hr_dev->caps.ceqe_size; 6103 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6104 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6105 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6106 } else { 6107 /* AEQ */ 6108 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6109 eq->type_flag = HNS_ROCE_AEQ; 6110 eq->entries = hr_dev->caps.aeqe_depth; 6111 eq->eqe_size = hr_dev->caps.aeqe_size; 6112 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6113 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6114 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6115 } 6116 6117 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6118 if (ret) { 6119 dev_err(dev, "eq create failed.\n"); 6120 goto err_create_eq_fail; 6121 } 6122 } 6123 6124 /* enable irq */ 6125 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6126 6127 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, 6128 aeq_num, other_num); 6129 if (ret) { 6130 dev_err(dev, "Request irq failed.\n"); 6131 goto err_request_irq_fail; 6132 } 6133 6134 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6135 if (!hr_dev->irq_workq) { 6136 dev_err(dev, "Create irq workqueue failed!\n"); 6137 ret = -ENOMEM; 6138 goto err_create_wq_fail; 6139 } 6140 6141 return 0; 6142 6143 err_create_wq_fail: 6144 __hns_roce_free_irq(hr_dev); 6145 6146 err_request_irq_fail: 6147 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6148 6149 err_create_eq_fail: 6150 for (i -= 1; i >= 0; i--) 6151 free_eq_buf(hr_dev, &eq_table->eq[i]); 6152 kfree(eq_table->eq); 6153 6154 return ret; 6155 } 6156 6157 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6158 { 6159 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6160 int eq_num; 6161 int i; 6162 6163 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6164 6165 /* Disable irq */ 6166 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6167 6168 __hns_roce_free_irq(hr_dev); 6169 6170 for (i = 0; i < eq_num; i++) { 6171 hns_roce_v2_destroy_eqc(hr_dev, i); 6172 6173 free_eq_buf(hr_dev, &eq_table->eq[i]); 6174 } 6175 6176 kfree(eq_table->eq); 6177 6178 flush_workqueue(hr_dev->irq_workq); 6179 destroy_workqueue(hr_dev->irq_workq); 6180 } 6181 6182 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 6183 .query_cqc_info = hns_roce_v2_query_cqc_info, 6184 }; 6185 6186 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6187 .destroy_qp = hns_roce_v2_destroy_qp, 6188 .modify_cq = hns_roce_v2_modify_cq, 6189 .poll_cq = hns_roce_v2_poll_cq, 6190 .post_recv = hns_roce_v2_post_recv, 6191 .post_send = hns_roce_v2_post_send, 6192 .query_qp = hns_roce_v2_query_qp, 6193 .req_notify_cq = hns_roce_v2_req_notify_cq, 6194 }; 6195 6196 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6197 .modify_srq = hns_roce_v2_modify_srq, 6198 .post_srq_recv = hns_roce_v2_post_srq_recv, 6199 .query_srq = hns_roce_v2_query_srq, 6200 }; 6201 6202 static const struct hns_roce_hw hns_roce_hw_v2 = { 6203 .cmq_init = hns_roce_v2_cmq_init, 6204 .cmq_exit = hns_roce_v2_cmq_exit, 6205 .hw_profile = hns_roce_v2_profile, 6206 .hw_init = hns_roce_v2_init, 6207 .hw_exit = hns_roce_v2_exit, 6208 .post_mbox = hns_roce_v2_post_mbox, 6209 .chk_mbox = hns_roce_v2_chk_mbox, 6210 .rst_prc_mbox = hns_roce_v2_rst_process_cmd, 6211 .set_gid = hns_roce_v2_set_gid, 6212 .set_mac = hns_roce_v2_set_mac, 6213 .write_mtpt = hns_roce_v2_write_mtpt, 6214 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6215 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6216 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6217 .write_cqc = hns_roce_v2_write_cqc, 6218 .set_hem = hns_roce_v2_set_hem, 6219 .clear_hem = hns_roce_v2_clear_hem, 6220 .modify_qp = hns_roce_v2_modify_qp, 6221 .query_qp = hns_roce_v2_query_qp, 6222 .destroy_qp = hns_roce_v2_destroy_qp, 6223 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6224 .modify_cq = hns_roce_v2_modify_cq, 6225 .post_send = hns_roce_v2_post_send, 6226 .post_recv = hns_roce_v2_post_recv, 6227 .req_notify_cq = hns_roce_v2_req_notify_cq, 6228 .poll_cq = hns_roce_v2_poll_cq, 6229 .init_eq = hns_roce_v2_init_eq_table, 6230 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6231 .write_srqc = hns_roce_v2_write_srqc, 6232 .modify_srq = hns_roce_v2_modify_srq, 6233 .query_srq = hns_roce_v2_query_srq, 6234 .post_srq_recv = hns_roce_v2_post_srq_recv, 6235 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6236 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6237 }; 6238 6239 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6240 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6241 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6242 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6243 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6244 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6245 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6246 /* required last entry */ 6247 {0, } 6248 }; 6249 6250 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6251 6252 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6253 struct hnae3_handle *handle) 6254 { 6255 struct hns_roce_v2_priv *priv = hr_dev->priv; 6256 int i; 6257 6258 hr_dev->pci_dev = handle->pdev; 6259 hr_dev->dev = &handle->pdev->dev; 6260 hr_dev->hw = &hns_roce_hw_v2; 6261 hr_dev->dfx = &hns_roce_dfx_hw_v2; 6262 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6263 hr_dev->odb_offset = hr_dev->sdb_offset; 6264 6265 /* Get info from NIC driver. */ 6266 hr_dev->reg_base = handle->rinfo.roce_io_base; 6267 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6268 hr_dev->caps.num_ports = 1; 6269 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6270 hr_dev->iboe.phy_port[0] = 0; 6271 6272 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6273 hr_dev->iboe.netdevs[0]->dev_addr); 6274 6275 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 6276 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6277 i + handle->rinfo.base_vector); 6278 6279 /* cmd issue mode: 0 is poll, 1 is event */ 6280 hr_dev->cmd_mod = 1; 6281 hr_dev->loop_idc = 0; 6282 6283 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6284 priv->handle = handle; 6285 } 6286 6287 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6288 { 6289 struct hns_roce_dev *hr_dev; 6290 int ret; 6291 6292 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6293 if (!hr_dev) 6294 return -ENOMEM; 6295 6296 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6297 if (!hr_dev->priv) { 6298 ret = -ENOMEM; 6299 goto error_failed_kzalloc; 6300 } 6301 6302 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6303 6304 ret = hns_roce_init(hr_dev); 6305 if (ret) { 6306 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6307 goto error_failed_get_cfg; 6308 } 6309 6310 handle->priv = hr_dev; 6311 6312 return 0; 6313 6314 error_failed_get_cfg: 6315 kfree(hr_dev->priv); 6316 6317 error_failed_kzalloc: 6318 ib_dealloc_device(&hr_dev->ib_dev); 6319 6320 return ret; 6321 } 6322 6323 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6324 bool reset) 6325 { 6326 struct hns_roce_dev *hr_dev = handle->priv; 6327 6328 if (!hr_dev) 6329 return; 6330 6331 handle->priv = NULL; 6332 6333 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6334 hns_roce_handle_device_err(hr_dev); 6335 6336 hns_roce_exit(hr_dev); 6337 kfree(hr_dev->priv); 6338 ib_dealloc_device(&hr_dev->ib_dev); 6339 } 6340 6341 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6342 { 6343 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6344 const struct pci_device_id *id; 6345 struct device *dev = &handle->pdev->dev; 6346 int ret; 6347 6348 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6349 6350 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6351 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6352 goto reset_chk_err; 6353 } 6354 6355 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6356 if (!id) 6357 return 0; 6358 6359 ret = __hns_roce_hw_v2_init_instance(handle); 6360 if (ret) { 6361 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6362 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6363 if (ops->ae_dev_resetting(handle) || 6364 ops->get_hw_reset_stat(handle)) 6365 goto reset_chk_err; 6366 else 6367 return ret; 6368 } 6369 6370 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6371 6372 6373 return 0; 6374 6375 reset_chk_err: 6376 dev_err(dev, "Device is busy in resetting state.\n" 6377 "please retry later.\n"); 6378 6379 return -EBUSY; 6380 } 6381 6382 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6383 bool reset) 6384 { 6385 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6386 return; 6387 6388 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6389 6390 __hns_roce_hw_v2_uninit_instance(handle, reset); 6391 6392 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6393 } 6394 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6395 { 6396 struct hns_roce_dev *hr_dev; 6397 6398 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6399 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6400 return 0; 6401 } 6402 6403 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6404 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6405 6406 hr_dev = handle->priv; 6407 if (!hr_dev) 6408 return 0; 6409 6410 hr_dev->is_reset = true; 6411 hr_dev->active = false; 6412 hr_dev->dis_db = true; 6413 6414 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6415 6416 return 0; 6417 } 6418 6419 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6420 { 6421 struct device *dev = &handle->pdev->dev; 6422 int ret; 6423 6424 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6425 &handle->rinfo.state)) { 6426 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6427 return 0; 6428 } 6429 6430 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6431 6432 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6433 ret = __hns_roce_hw_v2_init_instance(handle); 6434 if (ret) { 6435 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6436 * callback function, RoCE Engine reinitialize. If RoCE reinit 6437 * failed, we should inform NIC driver. 6438 */ 6439 handle->priv = NULL; 6440 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6441 } else { 6442 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6443 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6444 } 6445 6446 return ret; 6447 } 6448 6449 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6450 { 6451 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6452 return 0; 6453 6454 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6455 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6456 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6457 __hns_roce_hw_v2_uninit_instance(handle, false); 6458 6459 return 0; 6460 } 6461 6462 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6463 enum hnae3_reset_notify_type type) 6464 { 6465 int ret = 0; 6466 6467 switch (type) { 6468 case HNAE3_DOWN_CLIENT: 6469 ret = hns_roce_hw_v2_reset_notify_down(handle); 6470 break; 6471 case HNAE3_INIT_CLIENT: 6472 ret = hns_roce_hw_v2_reset_notify_init(handle); 6473 break; 6474 case HNAE3_UNINIT_CLIENT: 6475 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6476 break; 6477 default: 6478 break; 6479 } 6480 6481 return ret; 6482 } 6483 6484 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6485 .init_instance = hns_roce_hw_v2_init_instance, 6486 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6487 .reset_notify = hns_roce_hw_v2_reset_notify, 6488 }; 6489 6490 static struct hnae3_client hns_roce_hw_v2_client = { 6491 .name = "hns_roce_hw_v2", 6492 .type = HNAE3_CLIENT_ROCE, 6493 .ops = &hns_roce_hw_v2_ops, 6494 }; 6495 6496 static int __init hns_roce_hw_v2_init(void) 6497 { 6498 return hnae3_register_client(&hns_roce_hw_v2_client); 6499 } 6500 6501 static void __exit hns_roce_hw_v2_exit(void) 6502 { 6503 hnae3_unregister_client(&hns_roce_hw_v2_client); 6504 } 6505 6506 module_init(hns_roce_hw_v2_init); 6507 module_exit(hns_roce_hw_v2_exit); 6508 6509 MODULE_LICENSE("Dual BSD/GPL"); 6510 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6511 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6512 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6513 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6514