1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <net/addrconf.h> 38 #include <rdma/ib_umem.h> 39 40 #include "hnae3.h" 41 #include "hns_roce_common.h" 42 #include "hns_roce_device.h" 43 #include "hns_roce_cmd.h" 44 #include "hns_roce_hem.h" 45 #include "hns_roce_hw_v2.h" 46 47 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 48 struct ib_sge *sg) 49 { 50 dseg->lkey = cpu_to_le32(sg->lkey); 51 dseg->addr = cpu_to_le64(sg->addr); 52 dseg->len = cpu_to_le32(sg->length); 53 } 54 55 static int set_rwqe_data_seg(struct ib_qp *ibqp, struct ib_send_wr *wr, 56 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 57 void *wqe, unsigned int *sge_ind, 58 struct ib_send_wr **bad_wr) 59 { 60 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 61 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 62 struct hns_roce_qp *qp = to_hr_qp(ibqp); 63 int i; 64 65 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 66 if (le32_to_cpu(rc_sq_wqe->msg_len) > 67 hr_dev->caps.max_sq_inline) { 68 *bad_wr = wr; 69 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal", 70 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline); 71 return -EINVAL; 72 } 73 74 if (wr->opcode == IB_WR_RDMA_READ) { 75 dev_err(hr_dev->dev, "Not support inline data!\n"); 76 return -EINVAL; 77 } 78 79 for (i = 0; i < wr->num_sge; i++) { 80 memcpy(wqe, ((void *)wr->sg_list[i].addr), 81 wr->sg_list[i].length); 82 wqe += wr->sg_list[i].length; 83 } 84 85 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 86 1); 87 } else { 88 if (wr->num_sge <= 2) { 89 for (i = 0; i < wr->num_sge; i++) { 90 if (likely(wr->sg_list[i].length)) { 91 set_data_seg_v2(dseg, wr->sg_list + i); 92 dseg++; 93 } 94 } 95 } else { 96 roce_set_field(rc_sq_wqe->byte_20, 97 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 98 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 99 (*sge_ind) & (qp->sge.sge_cnt - 1)); 100 101 for (i = 0; i < 2; i++) { 102 if (likely(wr->sg_list[i].length)) { 103 set_data_seg_v2(dseg, wr->sg_list + i); 104 dseg++; 105 } 106 } 107 108 dseg = get_send_extend_sge(qp, 109 (*sge_ind) & (qp->sge.sge_cnt - 1)); 110 111 for (i = 0; i < wr->num_sge - 2; i++) { 112 if (likely(wr->sg_list[i + 2].length)) { 113 set_data_seg_v2(dseg, 114 wr->sg_list + 2 + i); 115 dseg++; 116 (*sge_ind)++; 117 } 118 } 119 } 120 121 roce_set_field(rc_sq_wqe->byte_16, 122 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 123 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge); 124 } 125 126 return 0; 127 } 128 129 static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 130 struct ib_send_wr **bad_wr) 131 { 132 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 133 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 134 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe; 135 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe; 136 struct hns_roce_qp *qp = to_hr_qp(ibqp); 137 struct hns_roce_v2_wqe_data_seg *dseg; 138 struct device *dev = hr_dev->dev; 139 struct hns_roce_v2_db sq_db; 140 unsigned int sge_ind = 0; 141 unsigned int owner_bit; 142 unsigned long flags; 143 unsigned int ind; 144 void *wqe = NULL; 145 bool loopback; 146 u32 tmp_len; 147 int ret = 0; 148 u8 *smac; 149 int nreq; 150 int i; 151 152 if (unlikely(ibqp->qp_type != IB_QPT_RC && 153 ibqp->qp_type != IB_QPT_GSI && 154 ibqp->qp_type != IB_QPT_UD)) { 155 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type); 156 *bad_wr = wr; 157 return -EOPNOTSUPP; 158 } 159 160 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT || 161 qp->state == IB_QPS_RTR)) { 162 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state); 163 *bad_wr = wr; 164 return -EINVAL; 165 } 166 167 spin_lock_irqsave(&qp->sq.lock, flags); 168 ind = qp->sq_next_wqe; 169 sge_ind = qp->next_sge; 170 171 for (nreq = 0; wr; ++nreq, wr = wr->next) { 172 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 173 ret = -ENOMEM; 174 *bad_wr = wr; 175 goto out; 176 } 177 178 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 179 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n", 180 wr->num_sge, qp->sq.max_gs); 181 ret = -EINVAL; 182 *bad_wr = wr; 183 goto out; 184 } 185 186 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 187 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = 188 wr->wr_id; 189 190 owner_bit = 191 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 192 tmp_len = 0; 193 194 /* Corresponding to the QP type, wqe process separately */ 195 if (ibqp->qp_type == IB_QPT_GSI) { 196 ud_sq_wqe = wqe; 197 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 198 199 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 200 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 201 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 202 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 203 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 204 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 205 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 206 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 207 roce_set_field(ud_sq_wqe->byte_48, 208 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 209 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, 210 ah->av.mac[4]); 211 roce_set_field(ud_sq_wqe->byte_48, 212 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 213 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, 214 ah->av.mac[5]); 215 216 /* MAC loopback */ 217 smac = (u8 *)hr_dev->dev_addr[qp->port]; 218 loopback = ether_addr_equal_unaligned(ah->av.mac, 219 smac) ? 1 : 0; 220 221 roce_set_bit(ud_sq_wqe->byte_40, 222 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 223 224 roce_set_field(ud_sq_wqe->byte_4, 225 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 226 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 227 HNS_ROCE_V2_WQE_OP_SEND); 228 229 for (i = 0; i < wr->num_sge; i++) 230 tmp_len += wr->sg_list[i].length; 231 232 ud_sq_wqe->msg_len = 233 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len); 234 235 switch (wr->opcode) { 236 case IB_WR_SEND_WITH_IMM: 237 case IB_WR_RDMA_WRITE_WITH_IMM: 238 ud_sq_wqe->immtdata = wr->ex.imm_data; 239 break; 240 default: 241 ud_sq_wqe->immtdata = 0; 242 break; 243 } 244 245 /* Set sig attr */ 246 roce_set_bit(ud_sq_wqe->byte_4, 247 V2_UD_SEND_WQE_BYTE_4_CQE_S, 248 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 249 250 /* Set se attr */ 251 roce_set_bit(ud_sq_wqe->byte_4, 252 V2_UD_SEND_WQE_BYTE_4_SE_S, 253 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 254 255 roce_set_bit(ud_sq_wqe->byte_4, 256 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 257 258 roce_set_field(ud_sq_wqe->byte_16, 259 V2_UD_SEND_WQE_BYTE_16_PD_M, 260 V2_UD_SEND_WQE_BYTE_16_PD_S, 261 to_hr_pd(ibqp->pd)->pdn); 262 263 roce_set_field(ud_sq_wqe->byte_16, 264 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 265 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, 266 wr->num_sge); 267 268 roce_set_field(ud_sq_wqe->byte_20, 269 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 270 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 271 sge_ind & (qp->sge.sge_cnt - 1)); 272 273 roce_set_field(ud_sq_wqe->byte_24, 274 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 275 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 276 ud_sq_wqe->qkey = 277 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 278 qp->qkey : ud_wr(wr)->remote_qkey); 279 roce_set_field(ud_sq_wqe->byte_32, 280 V2_UD_SEND_WQE_BYTE_32_DQPN_M, 281 V2_UD_SEND_WQE_BYTE_32_DQPN_S, 282 ud_wr(wr)->remote_qpn); 283 284 roce_set_field(ud_sq_wqe->byte_36, 285 V2_UD_SEND_WQE_BYTE_36_VLAN_M, 286 V2_UD_SEND_WQE_BYTE_36_VLAN_S, 287 le16_to_cpu(ah->av.vlan)); 288 roce_set_field(ud_sq_wqe->byte_36, 289 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 290 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, 291 ah->av.hop_limit); 292 roce_set_field(ud_sq_wqe->byte_36, 293 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 294 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 295 0); 296 roce_set_field(ud_sq_wqe->byte_36, 297 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 298 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 299 0); 300 roce_set_field(ud_sq_wqe->byte_40, 301 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 302 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, 0); 303 roce_set_field(ud_sq_wqe->byte_40, 304 V2_UD_SEND_WQE_BYTE_40_SL_M, 305 V2_UD_SEND_WQE_BYTE_40_SL_S, 306 le32_to_cpu(ah->av.sl_tclass_flowlabel) >> 307 HNS_ROCE_SL_SHIFT); 308 roce_set_field(ud_sq_wqe->byte_40, 309 V2_UD_SEND_WQE_BYTE_40_PORTN_M, 310 V2_UD_SEND_WQE_BYTE_40_PORTN_S, 311 qp->port); 312 313 roce_set_field(ud_sq_wqe->byte_48, 314 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 315 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, 316 hns_get_gid_index(hr_dev, qp->phy_port, 317 ah->av.gid_index)); 318 319 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], 320 GID_LEN_V2); 321 322 dseg = get_send_extend_sge(qp, 323 sge_ind & (qp->sge.sge_cnt - 1)); 324 for (i = 0; i < wr->num_sge; i++) { 325 set_data_seg_v2(dseg + i, wr->sg_list + i); 326 sge_ind++; 327 } 328 329 ind++; 330 } else if (ibqp->qp_type == IB_QPT_RC) { 331 rc_sq_wqe = wqe; 332 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 333 for (i = 0; i < wr->num_sge; i++) 334 tmp_len += wr->sg_list[i].length; 335 336 rc_sq_wqe->msg_len = 337 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len); 338 339 switch (wr->opcode) { 340 case IB_WR_SEND_WITH_IMM: 341 case IB_WR_RDMA_WRITE_WITH_IMM: 342 rc_sq_wqe->immtdata = wr->ex.imm_data; 343 break; 344 case IB_WR_SEND_WITH_INV: 345 rc_sq_wqe->inv_key = 346 cpu_to_le32(wr->ex.invalidate_rkey); 347 break; 348 default: 349 rc_sq_wqe->immtdata = 0; 350 break; 351 } 352 353 roce_set_bit(rc_sq_wqe->byte_4, 354 V2_RC_SEND_WQE_BYTE_4_FENCE_S, 355 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 356 357 roce_set_bit(rc_sq_wqe->byte_4, 358 V2_RC_SEND_WQE_BYTE_4_SE_S, 359 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 360 361 roce_set_bit(rc_sq_wqe->byte_4, 362 V2_RC_SEND_WQE_BYTE_4_CQE_S, 363 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 364 365 roce_set_bit(rc_sq_wqe->byte_4, 366 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 367 368 switch (wr->opcode) { 369 case IB_WR_RDMA_READ: 370 roce_set_field(rc_sq_wqe->byte_4, 371 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 372 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 373 HNS_ROCE_V2_WQE_OP_RDMA_READ); 374 rc_sq_wqe->rkey = 375 cpu_to_le32(rdma_wr(wr)->rkey); 376 rc_sq_wqe->va = 377 cpu_to_le64(rdma_wr(wr)->remote_addr); 378 break; 379 case IB_WR_RDMA_WRITE: 380 roce_set_field(rc_sq_wqe->byte_4, 381 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 382 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 383 HNS_ROCE_V2_WQE_OP_RDMA_WRITE); 384 rc_sq_wqe->rkey = 385 cpu_to_le32(rdma_wr(wr)->rkey); 386 rc_sq_wqe->va = 387 cpu_to_le64(rdma_wr(wr)->remote_addr); 388 break; 389 case IB_WR_RDMA_WRITE_WITH_IMM: 390 roce_set_field(rc_sq_wqe->byte_4, 391 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 392 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 393 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM); 394 rc_sq_wqe->rkey = 395 cpu_to_le32(rdma_wr(wr)->rkey); 396 rc_sq_wqe->va = 397 cpu_to_le64(rdma_wr(wr)->remote_addr); 398 break; 399 case IB_WR_SEND: 400 roce_set_field(rc_sq_wqe->byte_4, 401 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 402 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 403 HNS_ROCE_V2_WQE_OP_SEND); 404 break; 405 case IB_WR_SEND_WITH_INV: 406 roce_set_field(rc_sq_wqe->byte_4, 407 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 408 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 409 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV); 410 break; 411 case IB_WR_SEND_WITH_IMM: 412 roce_set_field(rc_sq_wqe->byte_4, 413 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 414 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 415 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM); 416 break; 417 case IB_WR_LOCAL_INV: 418 roce_set_field(rc_sq_wqe->byte_4, 419 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 420 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 421 HNS_ROCE_V2_WQE_OP_LOCAL_INV); 422 break; 423 case IB_WR_ATOMIC_CMP_AND_SWP: 424 roce_set_field(rc_sq_wqe->byte_4, 425 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 426 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 427 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP); 428 break; 429 case IB_WR_ATOMIC_FETCH_AND_ADD: 430 roce_set_field(rc_sq_wqe->byte_4, 431 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 432 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 433 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD); 434 break; 435 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 436 roce_set_field(rc_sq_wqe->byte_4, 437 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 438 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 439 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP); 440 break; 441 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 442 roce_set_field(rc_sq_wqe->byte_4, 443 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 444 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 445 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD); 446 break; 447 default: 448 roce_set_field(rc_sq_wqe->byte_4, 449 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 450 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 451 HNS_ROCE_V2_WQE_OP_MASK); 452 break; 453 } 454 455 wqe += sizeof(struct hns_roce_v2_rc_send_wqe); 456 dseg = wqe; 457 458 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe, 459 &sge_ind, bad_wr); 460 if (ret) 461 goto out; 462 ind++; 463 } else { 464 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type); 465 spin_unlock_irqrestore(&qp->sq.lock, flags); 466 *bad_wr = wr; 467 return -EOPNOTSUPP; 468 } 469 } 470 471 out: 472 if (likely(nreq)) { 473 qp->sq.head += nreq; 474 /* Memory barrier */ 475 wmb(); 476 477 sq_db.byte_4 = 0; 478 sq_db.parameter = 0; 479 480 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 481 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 482 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 483 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 484 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M, 485 V2_DB_PARAMETER_CONS_IDX_S, 486 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)); 487 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 488 V2_DB_PARAMETER_SL_S, qp->sl); 489 490 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l); 491 492 qp->sq_next_wqe = ind; 493 qp->next_sge = sge_ind; 494 } 495 496 spin_unlock_irqrestore(&qp->sq.lock, flags); 497 498 return ret; 499 } 500 501 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 502 struct ib_recv_wr **bad_wr) 503 { 504 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 505 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 506 struct hns_roce_v2_wqe_data_seg *dseg; 507 struct hns_roce_rinl_sge *sge_list; 508 struct device *dev = hr_dev->dev; 509 unsigned long flags; 510 void *wqe = NULL; 511 int ret = 0; 512 int nreq; 513 int ind; 514 int i; 515 516 spin_lock_irqsave(&hr_qp->rq.lock, flags); 517 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1); 518 519 if (hr_qp->state == IB_QPS_RESET) { 520 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 521 *bad_wr = wr; 522 return -EINVAL; 523 } 524 525 for (nreq = 0; wr; ++nreq, wr = wr->next) { 526 if (hns_roce_wq_overflow(&hr_qp->rq, nreq, 527 hr_qp->ibqp.recv_cq)) { 528 ret = -ENOMEM; 529 *bad_wr = wr; 530 goto out; 531 } 532 533 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { 534 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n", 535 wr->num_sge, hr_qp->rq.max_gs); 536 ret = -EINVAL; 537 *bad_wr = wr; 538 goto out; 539 } 540 541 wqe = get_recv_wqe(hr_qp, ind); 542 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 543 for (i = 0; i < wr->num_sge; i++) { 544 if (!wr->sg_list[i].length) 545 continue; 546 set_data_seg_v2(dseg, wr->sg_list + i); 547 dseg++; 548 } 549 550 if (i < hr_qp->rq.max_gs) { 551 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 552 dseg->addr = 0; 553 } 554 555 /* rq support inline data */ 556 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 557 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list; 558 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt = 559 (u32)wr->num_sge; 560 for (i = 0; i < wr->num_sge; i++) { 561 sge_list[i].addr = 562 (void *)(u64)wr->sg_list[i].addr; 563 sge_list[i].len = wr->sg_list[i].length; 564 } 565 } 566 567 hr_qp->rq.wrid[ind] = wr->wr_id; 568 569 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1); 570 } 571 572 out: 573 if (likely(nreq)) { 574 hr_qp->rq.head += nreq; 575 /* Memory barrier */ 576 wmb(); 577 578 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 579 } 580 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 581 582 return ret; 583 } 584 585 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 586 { 587 int ntu = ring->next_to_use; 588 int ntc = ring->next_to_clean; 589 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 590 591 return ring->desc_num - used - 1; 592 } 593 594 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 595 struct hns_roce_v2_cmq_ring *ring) 596 { 597 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 598 599 ring->desc = kzalloc(size, GFP_KERNEL); 600 if (!ring->desc) 601 return -ENOMEM; 602 603 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 604 DMA_BIDIRECTIONAL); 605 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 606 ring->desc_dma_addr = 0; 607 kfree(ring->desc); 608 ring->desc = NULL; 609 return -ENOMEM; 610 } 611 612 return 0; 613 } 614 615 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 616 struct hns_roce_v2_cmq_ring *ring) 617 { 618 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 619 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 620 DMA_BIDIRECTIONAL); 621 622 ring->desc_dma_addr = 0; 623 kfree(ring->desc); 624 } 625 626 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 627 { 628 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 629 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 630 &priv->cmq.csq : &priv->cmq.crq; 631 632 ring->flag = ring_type; 633 ring->next_to_clean = 0; 634 ring->next_to_use = 0; 635 636 return hns_roce_alloc_cmq_desc(hr_dev, ring); 637 } 638 639 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 640 { 641 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 642 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 643 &priv->cmq.csq : &priv->cmq.crq; 644 dma_addr_t dma = ring->desc_dma_addr; 645 646 if (ring_type == TYPE_CSQ) { 647 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 648 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 649 upper_32_bits(dma)); 650 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 651 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 652 HNS_ROCE_CMQ_ENABLE); 653 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 654 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 655 } else { 656 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 657 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 658 upper_32_bits(dma)); 659 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 660 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 661 HNS_ROCE_CMQ_ENABLE); 662 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 663 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 664 } 665 } 666 667 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 668 { 669 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 670 int ret; 671 672 /* Setup the queue entries for command queue */ 673 priv->cmq.csq.desc_num = 1024; 674 priv->cmq.crq.desc_num = 1024; 675 676 /* Setup the lock for command queue */ 677 spin_lock_init(&priv->cmq.csq.lock); 678 spin_lock_init(&priv->cmq.crq.lock); 679 680 /* Setup Tx write back timeout */ 681 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 682 683 /* Init CSQ */ 684 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 685 if (ret) { 686 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 687 return ret; 688 } 689 690 /* Init CRQ */ 691 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 692 if (ret) { 693 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 694 goto err_crq; 695 } 696 697 /* Init CSQ REG */ 698 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 699 700 /* Init CRQ REG */ 701 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 702 703 return 0; 704 705 err_crq: 706 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 707 708 return ret; 709 } 710 711 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 712 { 713 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 714 715 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 716 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 717 } 718 719 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 720 enum hns_roce_opcode_type opcode, 721 bool is_read) 722 { 723 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 724 desc->opcode = cpu_to_le16(opcode); 725 desc->flag = 726 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 727 if (is_read) 728 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 729 else 730 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 731 } 732 733 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 734 { 735 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 736 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 737 738 return head == priv->cmq.csq.next_to_use; 739 } 740 741 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 742 { 743 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 744 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 745 struct hns_roce_cmq_desc *desc; 746 u16 ntc = csq->next_to_clean; 747 u32 head; 748 int clean = 0; 749 750 desc = &csq->desc[ntc]; 751 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 752 while (head != ntc) { 753 memset(desc, 0, sizeof(*desc)); 754 ntc++; 755 if (ntc == csq->desc_num) 756 ntc = 0; 757 desc = &csq->desc[ntc]; 758 clean++; 759 } 760 csq->next_to_clean = ntc; 761 762 return clean; 763 } 764 765 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 766 struct hns_roce_cmq_desc *desc, int num) 767 { 768 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 769 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 770 struct hns_roce_cmq_desc *desc_to_use; 771 bool complete = false; 772 u32 timeout = 0; 773 int handle = 0; 774 u16 desc_ret; 775 int ret = 0; 776 int ntc; 777 778 spin_lock_bh(&csq->lock); 779 780 if (num > hns_roce_cmq_space(csq)) { 781 spin_unlock_bh(&csq->lock); 782 return -EBUSY; 783 } 784 785 /* 786 * Record the location of desc in the cmq for this time 787 * which will be use for hardware to write back 788 */ 789 ntc = csq->next_to_use; 790 791 while (handle < num) { 792 desc_to_use = &csq->desc[csq->next_to_use]; 793 *desc_to_use = desc[handle]; 794 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 795 csq->next_to_use++; 796 if (csq->next_to_use == csq->desc_num) 797 csq->next_to_use = 0; 798 handle++; 799 } 800 801 /* Write to hardware */ 802 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 803 804 /* 805 * If the command is sync, wait for the firmware to write back, 806 * if multi descriptors to be sent, use the first one to check 807 */ 808 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 809 do { 810 if (hns_roce_cmq_csq_done(hr_dev)) 811 break; 812 udelay(1); 813 timeout++; 814 } while (timeout < priv->cmq.tx_timeout); 815 } 816 817 if (hns_roce_cmq_csq_done(hr_dev)) { 818 complete = true; 819 handle = 0; 820 while (handle < num) { 821 /* get the result of hardware write back */ 822 desc_to_use = &csq->desc[ntc]; 823 desc[handle] = *desc_to_use; 824 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 825 desc_ret = desc[handle].retval; 826 if (desc_ret == CMD_EXEC_SUCCESS) 827 ret = 0; 828 else 829 ret = -EIO; 830 priv->cmq.last_status = desc_ret; 831 ntc++; 832 handle++; 833 if (ntc == csq->desc_num) 834 ntc = 0; 835 } 836 } 837 838 if (!complete) 839 ret = -EAGAIN; 840 841 /* clean the command send queue */ 842 handle = hns_roce_cmq_csq_clean(hr_dev); 843 if (handle != num) 844 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 845 handle, num); 846 847 spin_unlock_bh(&csq->lock); 848 849 return ret; 850 } 851 852 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 853 { 854 struct hns_roce_query_version *resp; 855 struct hns_roce_cmq_desc desc; 856 int ret; 857 858 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 859 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 860 if (ret) 861 return ret; 862 863 resp = (struct hns_roce_query_version *)desc.data; 864 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version); 865 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id); 866 867 return 0; 868 } 869 870 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 871 { 872 struct hns_roce_cfg_global_param *req; 873 struct hns_roce_cmq_desc desc; 874 875 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 876 false); 877 878 req = (struct hns_roce_cfg_global_param *)desc.data; 879 memset(req, 0, sizeof(*req)); 880 roce_set_field(req->time_cfg_udp_port, 881 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 882 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 883 roce_set_field(req->time_cfg_udp_port, 884 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 885 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 886 887 return hns_roce_cmq_send(hr_dev, &desc, 1); 888 } 889 890 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 891 { 892 struct hns_roce_cmq_desc desc[2]; 893 struct hns_roce_pf_res *res; 894 int ret; 895 int i; 896 897 for (i = 0; i < 2; i++) { 898 hns_roce_cmq_setup_basic_desc(&desc[i], 899 HNS_ROCE_OPC_QUERY_PF_RES, true); 900 901 if (i == 0) 902 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 903 else 904 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 905 } 906 907 ret = hns_roce_cmq_send(hr_dev, desc, 2); 908 if (ret) 909 return ret; 910 911 res = (struct hns_roce_pf_res *)desc[0].data; 912 913 hr_dev->caps.qpc_bt_num = roce_get_field(res->qpc_bt_idx_num, 914 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 915 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 916 hr_dev->caps.srqc_bt_num = roce_get_field(res->srqc_bt_idx_num, 917 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 918 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 919 hr_dev->caps.cqc_bt_num = roce_get_field(res->cqc_bt_idx_num, 920 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 921 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 922 hr_dev->caps.mpt_bt_num = roce_get_field(res->mpt_bt_idx_num, 923 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 924 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 925 926 return 0; 927 } 928 929 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 930 { 931 struct hns_roce_cmq_desc desc[2]; 932 struct hns_roce_vf_res_a *req_a; 933 struct hns_roce_vf_res_b *req_b; 934 int i; 935 936 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 937 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 938 memset(req_a, 0, sizeof(*req_a)); 939 memset(req_b, 0, sizeof(*req_b)); 940 for (i = 0; i < 2; i++) { 941 hns_roce_cmq_setup_basic_desc(&desc[i], 942 HNS_ROCE_OPC_ALLOC_VF_RES, false); 943 944 if (i == 0) 945 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 946 else 947 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 948 949 if (i == 0) { 950 roce_set_field(req_a->vf_qpc_bt_idx_num, 951 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 952 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 953 roce_set_field(req_a->vf_qpc_bt_idx_num, 954 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 955 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, 956 HNS_ROCE_VF_QPC_BT_NUM); 957 958 roce_set_field(req_a->vf_srqc_bt_idx_num, 959 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 960 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 961 roce_set_field(req_a->vf_srqc_bt_idx_num, 962 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 963 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 964 HNS_ROCE_VF_SRQC_BT_NUM); 965 966 roce_set_field(req_a->vf_cqc_bt_idx_num, 967 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 968 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 969 roce_set_field(req_a->vf_cqc_bt_idx_num, 970 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 971 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, 972 HNS_ROCE_VF_CQC_BT_NUM); 973 974 roce_set_field(req_a->vf_mpt_bt_idx_num, 975 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 976 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 977 roce_set_field(req_a->vf_mpt_bt_idx_num, 978 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 979 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, 980 HNS_ROCE_VF_MPT_BT_NUM); 981 982 roce_set_field(req_a->vf_eqc_bt_idx_num, 983 VF_RES_A_DATA_5_VF_EQC_IDX_M, 984 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 985 roce_set_field(req_a->vf_eqc_bt_idx_num, 986 VF_RES_A_DATA_5_VF_EQC_NUM_M, 987 VF_RES_A_DATA_5_VF_EQC_NUM_S, 988 HNS_ROCE_VF_EQC_NUM); 989 } else { 990 roce_set_field(req_b->vf_smac_idx_num, 991 VF_RES_B_DATA_1_VF_SMAC_IDX_M, 992 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 993 roce_set_field(req_b->vf_smac_idx_num, 994 VF_RES_B_DATA_1_VF_SMAC_NUM_M, 995 VF_RES_B_DATA_1_VF_SMAC_NUM_S, 996 HNS_ROCE_VF_SMAC_NUM); 997 998 roce_set_field(req_b->vf_sgid_idx_num, 999 VF_RES_B_DATA_2_VF_SGID_IDX_M, 1000 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1001 roce_set_field(req_b->vf_sgid_idx_num, 1002 VF_RES_B_DATA_2_VF_SGID_NUM_M, 1003 VF_RES_B_DATA_2_VF_SGID_NUM_S, 1004 HNS_ROCE_VF_SGID_NUM); 1005 1006 roce_set_field(req_b->vf_qid_idx_sl_num, 1007 VF_RES_B_DATA_3_VF_QID_IDX_M, 1008 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1009 roce_set_field(req_b->vf_qid_idx_sl_num, 1010 VF_RES_B_DATA_3_VF_SL_NUM_M, 1011 VF_RES_B_DATA_3_VF_SL_NUM_S, 1012 HNS_ROCE_VF_SL_NUM); 1013 } 1014 } 1015 1016 return hns_roce_cmq_send(hr_dev, desc, 2); 1017 } 1018 1019 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1020 { 1021 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1022 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1023 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1024 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1025 struct hns_roce_cfg_bt_attr *req; 1026 struct hns_roce_cmq_desc desc; 1027 1028 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1029 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1030 memset(req, 0, sizeof(*req)); 1031 1032 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1033 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1034 hr_dev->caps.qpc_ba_pg_sz); 1035 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1036 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1037 hr_dev->caps.qpc_buf_pg_sz); 1038 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1039 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1040 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1041 1042 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1043 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1044 hr_dev->caps.srqc_ba_pg_sz); 1045 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1046 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1047 hr_dev->caps.srqc_buf_pg_sz); 1048 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1049 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1050 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1051 1052 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1053 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1054 hr_dev->caps.cqc_ba_pg_sz); 1055 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1056 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1057 hr_dev->caps.cqc_buf_pg_sz); 1058 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1059 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1060 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1061 1062 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1063 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1064 hr_dev->caps.mpt_ba_pg_sz); 1065 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1066 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1067 hr_dev->caps.mpt_buf_pg_sz); 1068 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1069 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1070 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1071 1072 return hns_roce_cmq_send(hr_dev, &desc, 1); 1073 } 1074 1075 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 1076 { 1077 struct hns_roce_caps *caps = &hr_dev->caps; 1078 int ret; 1079 1080 ret = hns_roce_cmq_query_hw_info(hr_dev); 1081 if (ret) { 1082 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 1083 ret); 1084 return ret; 1085 } 1086 1087 ret = hns_roce_config_global_param(hr_dev); 1088 if (ret) { 1089 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 1090 ret); 1091 return ret; 1092 } 1093 1094 /* Get pf resource owned by every pf */ 1095 ret = hns_roce_query_pf_resource(hr_dev); 1096 if (ret) { 1097 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 1098 ret); 1099 return ret; 1100 } 1101 1102 ret = hns_roce_alloc_vf_resource(hr_dev); 1103 if (ret) { 1104 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 1105 ret); 1106 return ret; 1107 } 1108 1109 hr_dev->vendor_part_id = 0; 1110 hr_dev->sys_image_guid = 0; 1111 1112 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1113 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1114 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1115 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1116 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1117 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1118 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1119 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1120 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1121 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1122 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1123 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1124 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1125 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1126 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1127 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1128 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1129 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1130 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1131 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1132 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1133 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1134 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1135 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ; 1136 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1137 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1138 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1139 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1140 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1141 caps->reserved_lkey = 0; 1142 caps->reserved_pds = 0; 1143 caps->reserved_mrws = 1; 1144 caps->reserved_uars = 0; 1145 caps->reserved_cqs = 0; 1146 1147 caps->qpc_ba_pg_sz = 0; 1148 caps->qpc_buf_pg_sz = 0; 1149 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1150 caps->srqc_ba_pg_sz = 0; 1151 caps->srqc_buf_pg_sz = 0; 1152 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0; 1153 caps->cqc_ba_pg_sz = 0; 1154 caps->cqc_buf_pg_sz = 0; 1155 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1156 caps->mpt_ba_pg_sz = 0; 1157 caps->mpt_buf_pg_sz = 0; 1158 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1159 caps->pbl_ba_pg_sz = 0; 1160 caps->pbl_buf_pg_sz = 0; 1161 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 1162 caps->mtt_ba_pg_sz = 0; 1163 caps->mtt_buf_pg_sz = 0; 1164 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1165 caps->cqe_ba_pg_sz = 0; 1166 caps->cqe_buf_pg_sz = 0; 1167 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1168 caps->eqe_ba_pg_sz = 0; 1169 caps->eqe_buf_pg_sz = 0; 1170 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 1171 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1172 1173 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1174 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1175 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1176 HNS_ROCE_CAP_FLAG_RECORD_DB; 1177 caps->pkey_table_len[0] = 1; 1178 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1179 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1180 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1181 caps->local_ca_ack_delay = 0; 1182 caps->max_mtu = IB_MTU_4096; 1183 1184 ret = hns_roce_v2_set_bt(hr_dev); 1185 if (ret) 1186 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 1187 ret); 1188 1189 return ret; 1190 } 1191 1192 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 1193 { 1194 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1195 1196 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 1197 } 1198 1199 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 1200 { 1201 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1202 1203 return status & HNS_ROCE_HW_MB_STATUS_MASK; 1204 } 1205 1206 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 1207 u64 out_param, u32 in_modifier, u8 op_modifier, 1208 u16 op, u16 token, int event) 1209 { 1210 struct device *dev = hr_dev->dev; 1211 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + 1212 ROCEE_VF_MB_CFG0_REG); 1213 unsigned long end; 1214 u32 val0 = 0; 1215 u32 val1 = 0; 1216 1217 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 1218 while (hns_roce_v2_cmd_pending(hr_dev)) { 1219 if (time_after(jiffies, end)) { 1220 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 1221 (int)end); 1222 return -EAGAIN; 1223 } 1224 cond_resched(); 1225 } 1226 1227 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK, 1228 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier); 1229 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK, 1230 HNS_ROCE_VF_MB4_CMD_SHIFT, op); 1231 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK, 1232 HNS_ROCE_VF_MB5_EVENT_SHIFT, event); 1233 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK, 1234 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token); 1235 1236 writeq(in_param, hcr + 0); 1237 writeq(out_param, hcr + 2); 1238 1239 /* Memory barrier */ 1240 wmb(); 1241 1242 writel(val0, hcr + 4); 1243 writel(val1, hcr + 5); 1244 1245 mmiowb(); 1246 1247 return 0; 1248 } 1249 1250 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 1251 unsigned long timeout) 1252 { 1253 struct device *dev = hr_dev->dev; 1254 unsigned long end = 0; 1255 u32 status; 1256 1257 end = msecs_to_jiffies(timeout) + jiffies; 1258 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 1259 cond_resched(); 1260 1261 if (hns_roce_v2_cmd_pending(hr_dev)) { 1262 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 1263 return -ETIMEDOUT; 1264 } 1265 1266 status = hns_roce_v2_cmd_complete(hr_dev); 1267 if (status != 0x1) { 1268 dev_err(dev, "mailbox status 0x%x!\n", status); 1269 return -EBUSY; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 1276 int gid_index, union ib_gid *gid, 1277 const struct ib_gid_attr *attr) 1278 { 1279 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 1280 u32 *p; 1281 u32 val; 1282 1283 if (!gid || !attr) 1284 return -EINVAL; 1285 1286 if (attr->gid_type == IB_GID_TYPE_ROCE) 1287 sgid_type = GID_TYPE_FLAG_ROCE_V1; 1288 1289 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 1290 if (ipv6_addr_v4mapped((void *)gid)) 1291 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 1292 else 1293 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 1294 } 1295 1296 p = (u32 *)&gid->raw[0]; 1297 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG + 1298 0x20 * gid_index); 1299 1300 p = (u32 *)&gid->raw[4]; 1301 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG + 1302 0x20 * gid_index); 1303 1304 p = (u32 *)&gid->raw[8]; 1305 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG + 1306 0x20 * gid_index); 1307 1308 p = (u32 *)&gid->raw[0xc]; 1309 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG + 1310 0x20 * gid_index); 1311 1312 val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index); 1313 roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M, 1314 ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type); 1315 1316 roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val); 1317 1318 return 0; 1319 } 1320 1321 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 1322 u8 *addr) 1323 { 1324 u16 reg_smac_h; 1325 u32 reg_smac_l; 1326 u32 val; 1327 1328 reg_smac_l = *(u32 *)(&addr[0]); 1329 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG + 1330 0x08 * phy_port); 1331 val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port); 1332 1333 reg_smac_h = *(u16 *)(&addr[4]); 1334 roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M, 1335 ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h); 1336 roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val); 1337 1338 return 0; 1339 } 1340 1341 static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 1342 unsigned long mtpt_idx) 1343 { 1344 struct hns_roce_v2_mpt_entry *mpt_entry; 1345 struct scatterlist *sg; 1346 u64 page_addr; 1347 u64 *pages; 1348 int i, j; 1349 int len; 1350 int entry; 1351 1352 mpt_entry = mb_buf; 1353 memset(mpt_entry, 0, sizeof(*mpt_entry)); 1354 1355 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 1356 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 1357 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 1358 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 1359 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 1360 roce_set_field(mpt_entry->byte_4_pd_hop_st, 1361 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 1362 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz); 1363 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1364 V2_MPT_BYTE_4_PD_S, mr->pd); 1365 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st); 1366 1367 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 1368 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 1369 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0); 1370 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 1371 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 1372 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0); 1373 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1374 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1375 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1376 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1377 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1378 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1379 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en); 1380 1381 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 1382 mr->type == MR_TYPE_MR ? 0 : 1); 1383 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, 1384 1); 1385 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa); 1386 1387 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 1388 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 1389 mpt_entry->lkey = cpu_to_le32(mr->key); 1390 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 1391 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 1392 1393 if (mr->type == MR_TYPE_DMA) 1394 return 0; 1395 1396 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1397 1398 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1399 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 1400 V2_MPT_BYTE_48_PBL_BA_H_S, 1401 upper_32_bits(mr->pbl_ba >> 3)); 1402 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba); 1403 1404 pages = (u64 *)__get_free_page(GFP_KERNEL); 1405 if (!pages) 1406 return -ENOMEM; 1407 1408 i = 0; 1409 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { 1410 len = sg_dma_len(sg) >> PAGE_SHIFT; 1411 for (j = 0; j < len; ++j) { 1412 page_addr = sg_dma_address(sg) + 1413 (j << mr->umem->page_shift); 1414 pages[i] = page_addr >> 6; 1415 1416 /* Record the first 2 entry directly to MTPT table */ 1417 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) 1418 goto found; 1419 i++; 1420 } 1421 } 1422 1423 found: 1424 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 1425 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 1426 V2_MPT_BYTE_56_PA0_H_S, 1427 upper_32_bits(pages[0])); 1428 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h); 1429 1430 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 1431 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 1432 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 1433 1434 free_page((unsigned long)pages); 1435 1436 roce_set_field(mpt_entry->byte_64_buf_pa1, 1437 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 1438 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz); 1439 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1); 1440 1441 return 0; 1442 } 1443 1444 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 1445 struct hns_roce_mr *mr, int flags, 1446 u32 pdn, int mr_access_flags, u64 iova, 1447 u64 size, void *mb_buf) 1448 { 1449 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 1450 1451 if (flags & IB_MR_REREG_PD) { 1452 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1453 V2_MPT_BYTE_4_PD_S, pdn); 1454 mr->pd = pdn; 1455 } 1456 1457 if (flags & IB_MR_REREG_ACCESS) { 1458 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1459 V2_MPT_BYTE_8_BIND_EN_S, 1460 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 1461 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1462 V2_MPT_BYTE_8_ATOMIC_EN_S, 1463 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0)); 1464 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1465 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1466 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1467 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1468 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1469 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1470 } 1471 1472 if (flags & IB_MR_REREG_TRANS) { 1473 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 1474 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 1475 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 1476 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 1477 1478 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1479 mpt_entry->pbl_ba_l = 1480 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1481 roce_set_field(mpt_entry->byte_48_mode_ba, 1482 V2_MPT_BYTE_48_PBL_BA_H_M, 1483 V2_MPT_BYTE_48_PBL_BA_H_S, 1484 upper_32_bits(mr->pbl_ba >> 3)); 1485 mpt_entry->byte_48_mode_ba = 1486 cpu_to_le32(mpt_entry->byte_48_mode_ba); 1487 1488 mr->iova = iova; 1489 mr->size = size; 1490 } 1491 1492 return 0; 1493 } 1494 1495 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1496 { 1497 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf, 1498 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 1499 } 1500 1501 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1502 { 1503 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 1504 1505 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 1506 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 1507 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL; 1508 } 1509 1510 static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq) 1511 { 1512 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 1513 } 1514 1515 static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) 1516 { 1517 *hr_cq->set_ci_db = cons_index & 0xffffff; 1518 } 1519 1520 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1521 struct hns_roce_srq *srq) 1522 { 1523 struct hns_roce_v2_cqe *cqe, *dest; 1524 u32 prod_index; 1525 int nfreed = 0; 1526 u8 owner_bit; 1527 1528 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 1529 ++prod_index) { 1530 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe) 1531 break; 1532 } 1533 1534 /* 1535 * Now backwards through the CQ, removing CQ entries 1536 * that match our QP by overwriting them with next entries. 1537 */ 1538 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 1539 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 1540 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1541 V2_CQE_BYTE_16_LCL_QPN_S) & 1542 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 1543 /* In v1 engine, not support SRQ */ 1544 ++nfreed; 1545 } else if (nfreed) { 1546 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 1547 hr_cq->ib_cq.cqe); 1548 owner_bit = roce_get_bit(dest->byte_4, 1549 V2_CQE_BYTE_4_OWNER_S); 1550 memcpy(dest, cqe, sizeof(*cqe)); 1551 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 1552 owner_bit); 1553 } 1554 } 1555 1556 if (nfreed) { 1557 hr_cq->cons_index += nfreed; 1558 /* 1559 * Make sure update of buffer contents is done before 1560 * updating consumer index. 1561 */ 1562 wmb(); 1563 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1564 } 1565 } 1566 1567 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1568 struct hns_roce_srq *srq) 1569 { 1570 spin_lock_irq(&hr_cq->lock); 1571 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 1572 spin_unlock_irq(&hr_cq->lock); 1573 } 1574 1575 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 1576 struct hns_roce_cq *hr_cq, void *mb_buf, 1577 u64 *mtts, dma_addr_t dma_handle, int nent, 1578 u32 vector) 1579 { 1580 struct hns_roce_v2_cq_context *cq_context; 1581 1582 cq_context = mb_buf; 1583 memset(cq_context, 0, sizeof(*cq_context)); 1584 1585 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 1586 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 1587 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 1588 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 1589 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 1590 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent)); 1591 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 1592 V2_CQC_BYTE_4_CEQN_S, vector); 1593 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn); 1594 1595 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 1596 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 1597 1598 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 1599 cq_context->cqe_cur_blk_addr = 1600 cpu_to_le32(cq_context->cqe_cur_blk_addr); 1601 1602 roce_set_field(cq_context->byte_16_hop_addr, 1603 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 1604 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 1605 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT))); 1606 roce_set_field(cq_context->byte_16_hop_addr, 1607 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 1608 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 1609 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 1610 1611 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT); 1612 roce_set_field(cq_context->byte_24_pgsz_addr, 1613 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 1614 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 1615 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT))); 1616 roce_set_field(cq_context->byte_24_pgsz_addr, 1617 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 1618 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 1619 hr_dev->caps.cqe_ba_pg_sz); 1620 roce_set_field(cq_context->byte_24_pgsz_addr, 1621 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 1622 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 1623 hr_dev->caps.cqe_buf_pg_sz); 1624 1625 cq_context->cqe_ba = (u32)(dma_handle >> 3); 1626 1627 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 1628 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 1629 1630 if (hr_cq->db_en) 1631 roce_set_bit(cq_context->byte_44_db_record, 1632 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1); 1633 1634 roce_set_field(cq_context->byte_44_db_record, 1635 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 1636 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 1637 ((u32)hr_cq->db.dma) >> 1); 1638 cq_context->db_record_addr = hr_cq->db.dma >> 32; 1639 1640 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1641 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 1642 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 1643 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 1644 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1645 V2_CQC_BYTE_56_CQ_PERIOD_M, 1646 V2_CQC_BYTE_56_CQ_PERIOD_S, 1647 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 1648 } 1649 1650 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 1651 enum ib_cq_notify_flags flags) 1652 { 1653 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1654 u32 notification_flag; 1655 u32 doorbell[2]; 1656 1657 doorbell[0] = 0; 1658 doorbell[1] = 0; 1659 1660 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 1661 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 1662 /* 1663 * flags = 0; Notification Flag = 1, next 1664 * flags = 1; Notification Flag = 0, solocited 1665 */ 1666 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 1667 hr_cq->cqn); 1668 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 1669 HNS_ROCE_V2_CQ_DB_NTR); 1670 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 1671 V2_CQ_DB_PARAMETER_CONS_IDX_S, 1672 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); 1673 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 1674 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 1675 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 1676 notification_flag); 1677 1678 hns_roce_write64_k(doorbell, hr_cq->cq_db_l); 1679 1680 return 0; 1681 } 1682 1683 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 1684 struct hns_roce_qp **cur_qp, 1685 struct ib_wc *wc) 1686 { 1687 struct hns_roce_rinl_sge *sge_list; 1688 u32 wr_num, wr_cnt, sge_num; 1689 u32 sge_cnt, data_len, size; 1690 void *wqe_buf; 1691 1692 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 1693 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 1694 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 1695 1696 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 1697 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 1698 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt); 1699 data_len = wc->byte_len; 1700 1701 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 1702 size = min(sge_list[sge_cnt].len, data_len); 1703 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 1704 1705 data_len -= size; 1706 wqe_buf += size; 1707 } 1708 1709 if (data_len) { 1710 wc->status = IB_WC_LOC_LEN_ERR; 1711 return -EAGAIN; 1712 } 1713 1714 return 0; 1715 } 1716 1717 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 1718 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 1719 { 1720 struct hns_roce_dev *hr_dev; 1721 struct hns_roce_v2_cqe *cqe; 1722 struct hns_roce_qp *hr_qp; 1723 struct hns_roce_wq *wq; 1724 int is_send; 1725 u16 wqe_ctr; 1726 u32 opcode; 1727 u32 status; 1728 int qpn; 1729 int ret; 1730 1731 /* Find cqe according to consumer index */ 1732 cqe = next_cqe_sw_v2(hr_cq); 1733 if (!cqe) 1734 return -EAGAIN; 1735 1736 ++hr_cq->cons_index; 1737 /* Memory barrier */ 1738 rmb(); 1739 1740 /* 0->SQ, 1->RQ */ 1741 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 1742 1743 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1744 V2_CQE_BYTE_16_LCL_QPN_S); 1745 1746 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 1747 hr_dev = to_hr_dev(hr_cq->ib_cq.device); 1748 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 1749 if (unlikely(!hr_qp)) { 1750 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n", 1751 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK)); 1752 return -EINVAL; 1753 } 1754 *cur_qp = hr_qp; 1755 } 1756 1757 wc->qp = &(*cur_qp)->ibqp; 1758 wc->vendor_err = 0; 1759 1760 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 1761 V2_CQE_BYTE_4_STATUS_S); 1762 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) { 1763 case HNS_ROCE_CQE_V2_SUCCESS: 1764 wc->status = IB_WC_SUCCESS; 1765 break; 1766 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR: 1767 wc->status = IB_WC_LOC_LEN_ERR; 1768 break; 1769 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR: 1770 wc->status = IB_WC_LOC_QP_OP_ERR; 1771 break; 1772 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR: 1773 wc->status = IB_WC_LOC_PROT_ERR; 1774 break; 1775 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR: 1776 wc->status = IB_WC_WR_FLUSH_ERR; 1777 break; 1778 case HNS_ROCE_CQE_V2_MW_BIND_ERR: 1779 wc->status = IB_WC_MW_BIND_ERR; 1780 break; 1781 case HNS_ROCE_CQE_V2_BAD_RESP_ERR: 1782 wc->status = IB_WC_BAD_RESP_ERR; 1783 break; 1784 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR: 1785 wc->status = IB_WC_LOC_ACCESS_ERR; 1786 break; 1787 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR: 1788 wc->status = IB_WC_REM_INV_REQ_ERR; 1789 break; 1790 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR: 1791 wc->status = IB_WC_REM_ACCESS_ERR; 1792 break; 1793 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR: 1794 wc->status = IB_WC_REM_OP_ERR; 1795 break; 1796 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR: 1797 wc->status = IB_WC_RETRY_EXC_ERR; 1798 break; 1799 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR: 1800 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 1801 break; 1802 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR: 1803 wc->status = IB_WC_REM_ABORT_ERR; 1804 break; 1805 default: 1806 wc->status = IB_WC_GENERAL_ERR; 1807 break; 1808 } 1809 1810 /* CQE status error, directly return */ 1811 if (wc->status != IB_WC_SUCCESS) 1812 return 0; 1813 1814 if (is_send) { 1815 wc->wc_flags = 0; 1816 /* SQ corresponding to CQE */ 1817 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1818 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 1819 case HNS_ROCE_SQ_OPCODE_SEND: 1820 wc->opcode = IB_WC_SEND; 1821 break; 1822 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: 1823 wc->opcode = IB_WC_SEND; 1824 break; 1825 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: 1826 wc->opcode = IB_WC_SEND; 1827 wc->wc_flags |= IB_WC_WITH_IMM; 1828 break; 1829 case HNS_ROCE_SQ_OPCODE_RDMA_READ: 1830 wc->opcode = IB_WC_RDMA_READ; 1831 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1832 break; 1833 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: 1834 wc->opcode = IB_WC_RDMA_WRITE; 1835 break; 1836 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: 1837 wc->opcode = IB_WC_RDMA_WRITE; 1838 wc->wc_flags |= IB_WC_WITH_IMM; 1839 break; 1840 case HNS_ROCE_SQ_OPCODE_LOCAL_INV: 1841 wc->opcode = IB_WC_LOCAL_INV; 1842 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 1843 break; 1844 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: 1845 wc->opcode = IB_WC_COMP_SWAP; 1846 wc->byte_len = 8; 1847 break; 1848 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: 1849 wc->opcode = IB_WC_FETCH_ADD; 1850 wc->byte_len = 8; 1851 break; 1852 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: 1853 wc->opcode = IB_WC_MASKED_COMP_SWAP; 1854 wc->byte_len = 8; 1855 break; 1856 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: 1857 wc->opcode = IB_WC_MASKED_FETCH_ADD; 1858 wc->byte_len = 8; 1859 break; 1860 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: 1861 wc->opcode = IB_WC_REG_MR; 1862 break; 1863 case HNS_ROCE_SQ_OPCODE_BIND_MW: 1864 wc->opcode = IB_WC_REG_MR; 1865 break; 1866 default: 1867 wc->status = IB_WC_GENERAL_ERR; 1868 break; 1869 } 1870 1871 wq = &(*cur_qp)->sq; 1872 if ((*cur_qp)->sq_signal_bits) { 1873 /* 1874 * If sg_signal_bit is 1, 1875 * firstly tail pointer updated to wqe 1876 * which current cqe correspond to 1877 */ 1878 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 1879 V2_CQE_BYTE_4_WQE_INDX_M, 1880 V2_CQE_BYTE_4_WQE_INDX_S); 1881 wq->tail += (wqe_ctr - (u16)wq->tail) & 1882 (wq->wqe_cnt - 1); 1883 } 1884 1885 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1886 ++wq->tail; 1887 } else { 1888 /* RQ correspond to CQE */ 1889 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1890 1891 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1892 V2_CQE_BYTE_4_OPCODE_S); 1893 switch (opcode & 0x1f) { 1894 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 1895 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 1896 wc->wc_flags = IB_WC_WITH_IMM; 1897 wc->ex.imm_data = cqe->immtdata; 1898 break; 1899 case HNS_ROCE_V2_OPCODE_SEND: 1900 wc->opcode = IB_WC_RECV; 1901 wc->wc_flags = 0; 1902 break; 1903 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 1904 wc->opcode = IB_WC_RECV; 1905 wc->wc_flags = IB_WC_WITH_IMM; 1906 wc->ex.imm_data = cqe->immtdata; 1907 break; 1908 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 1909 wc->opcode = IB_WC_RECV; 1910 wc->wc_flags = IB_WC_WITH_INVALIDATE; 1911 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 1912 break; 1913 default: 1914 wc->status = IB_WC_GENERAL_ERR; 1915 break; 1916 } 1917 1918 if ((wc->qp->qp_type == IB_QPT_RC || 1919 wc->qp->qp_type == IB_QPT_UC) && 1920 (opcode == HNS_ROCE_V2_OPCODE_SEND || 1921 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 1922 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 1923 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 1924 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 1925 if (ret) 1926 return -EAGAIN; 1927 } 1928 1929 /* Update tail pointer, record wr_id */ 1930 wq = &(*cur_qp)->rq; 1931 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1932 ++wq->tail; 1933 1934 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 1935 V2_CQE_BYTE_32_SL_S); 1936 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 1937 V2_CQE_BYTE_32_RMT_QPN_M, 1938 V2_CQE_BYTE_32_RMT_QPN_S); 1939 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 1940 V2_CQE_BYTE_32_GRH_S) ? 1941 IB_WC_GRH : 0); 1942 wc->port_num = roce_get_field(cqe->byte_32, 1943 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 1944 wc->pkey_index = 0; 1945 memcpy(wc->smac, cqe->smac, 4); 1946 wc->smac[4] = roce_get_field(cqe->byte_28, 1947 V2_CQE_BYTE_28_SMAC_4_M, 1948 V2_CQE_BYTE_28_SMAC_4_S); 1949 wc->smac[5] = roce_get_field(cqe->byte_28, 1950 V2_CQE_BYTE_28_SMAC_5_M, 1951 V2_CQE_BYTE_28_SMAC_5_S); 1952 wc->vlan_id = 0xffff; 1953 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 1954 wc->network_hdr_type = roce_get_field(cqe->byte_28, 1955 V2_CQE_BYTE_28_PORT_TYPE_M, 1956 V2_CQE_BYTE_28_PORT_TYPE_S); 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 1963 struct ib_wc *wc) 1964 { 1965 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1966 struct hns_roce_qp *cur_qp = NULL; 1967 unsigned long flags; 1968 int npolled; 1969 1970 spin_lock_irqsave(&hr_cq->lock, flags); 1971 1972 for (npolled = 0; npolled < num_entries; ++npolled) { 1973 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 1974 break; 1975 } 1976 1977 if (npolled) { 1978 /* Memory barrier */ 1979 wmb(); 1980 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1981 } 1982 1983 spin_unlock_irqrestore(&hr_cq->lock, flags); 1984 1985 return npolled; 1986 } 1987 1988 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 1989 struct hns_roce_hem_table *table, int obj, 1990 int step_idx) 1991 { 1992 struct device *dev = hr_dev->dev; 1993 struct hns_roce_cmd_mailbox *mailbox; 1994 struct hns_roce_hem_iter iter; 1995 struct hns_roce_hem_mhop mhop; 1996 struct hns_roce_hem *hem; 1997 unsigned long mhop_obj = obj; 1998 int i, j, k; 1999 int ret = 0; 2000 u64 hem_idx = 0; 2001 u64 l1_idx = 0; 2002 u64 bt_ba = 0; 2003 u32 chunk_ba_num; 2004 u32 hop_num; 2005 u16 op = 0xff; 2006 2007 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2008 return 0; 2009 2010 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 2011 i = mhop.l0_idx; 2012 j = mhop.l1_idx; 2013 k = mhop.l2_idx; 2014 hop_num = mhop.hop_num; 2015 chunk_ba_num = mhop.bt_chunk_size / 8; 2016 2017 if (hop_num == 2) { 2018 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 2019 k; 2020 l1_idx = i * chunk_ba_num + j; 2021 } else if (hop_num == 1) { 2022 hem_idx = i * chunk_ba_num + j; 2023 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 2024 hem_idx = i; 2025 } 2026 2027 switch (table->type) { 2028 case HEM_TYPE_QPC: 2029 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 2030 break; 2031 case HEM_TYPE_MTPT: 2032 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 2033 break; 2034 case HEM_TYPE_CQC: 2035 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 2036 break; 2037 case HEM_TYPE_SRQC: 2038 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 2039 break; 2040 default: 2041 dev_warn(dev, "Table %d not to be written by mailbox!\n", 2042 table->type); 2043 return 0; 2044 } 2045 op += step_idx; 2046 2047 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2048 if (IS_ERR(mailbox)) 2049 return PTR_ERR(mailbox); 2050 2051 if (check_whether_last_step(hop_num, step_idx)) { 2052 hem = table->hem[hem_idx]; 2053 for (hns_roce_hem_first(hem, &iter); 2054 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 2055 bt_ba = hns_roce_hem_addr(&iter); 2056 2057 /* configure the ba, tag, and op */ 2058 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, 2059 obj, 0, op, 2060 HNS_ROCE_CMD_TIMEOUT_MSECS); 2061 } 2062 } else { 2063 if (step_idx == 0) 2064 bt_ba = table->bt_l0_dma_addr[i]; 2065 else if (step_idx == 1 && hop_num == 2) 2066 bt_ba = table->bt_l1_dma_addr[l1_idx]; 2067 2068 /* configure the ba, tag, and op */ 2069 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 2070 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 2071 } 2072 2073 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2074 return ret; 2075 } 2076 2077 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 2078 struct hns_roce_hem_table *table, int obj, 2079 int step_idx) 2080 { 2081 struct device *dev = hr_dev->dev; 2082 struct hns_roce_cmd_mailbox *mailbox; 2083 int ret = 0; 2084 u16 op = 0xff; 2085 2086 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2087 return 0; 2088 2089 switch (table->type) { 2090 case HEM_TYPE_QPC: 2091 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 2092 break; 2093 case HEM_TYPE_MTPT: 2094 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 2095 break; 2096 case HEM_TYPE_CQC: 2097 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 2098 break; 2099 case HEM_TYPE_SRQC: 2100 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 2101 break; 2102 default: 2103 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 2104 table->type); 2105 return 0; 2106 } 2107 op += step_idx; 2108 2109 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2110 if (IS_ERR(mailbox)) 2111 return PTR_ERR(mailbox); 2112 2113 /* configure the tag and op */ 2114 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 2115 HNS_ROCE_CMD_TIMEOUT_MSECS); 2116 2117 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2118 return ret; 2119 } 2120 2121 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 2122 struct hns_roce_mtt *mtt, 2123 enum ib_qp_state cur_state, 2124 enum ib_qp_state new_state, 2125 struct hns_roce_v2_qp_context *context, 2126 struct hns_roce_qp *hr_qp) 2127 { 2128 struct hns_roce_cmd_mailbox *mailbox; 2129 int ret; 2130 2131 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2132 if (IS_ERR(mailbox)) 2133 return PTR_ERR(mailbox); 2134 2135 memcpy(mailbox->buf, context, sizeof(*context) * 2); 2136 2137 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 2138 HNS_ROCE_CMD_MODIFY_QPC, 2139 HNS_ROCE_CMD_TIMEOUT_MSECS); 2140 2141 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2142 2143 return ret; 2144 } 2145 2146 static void set_access_flags(struct hns_roce_qp *hr_qp, 2147 struct hns_roce_v2_qp_context *context, 2148 struct hns_roce_v2_qp_context *qpc_mask, 2149 const struct ib_qp_attr *attr, int attr_mask) 2150 { 2151 u8 dest_rd_atomic; 2152 u32 access_flags; 2153 2154 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 2155 attr->max_dest_rd_atomic : hr_qp->resp_depth; 2156 2157 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 2158 attr->qp_access_flags : hr_qp->atomic_rd_en; 2159 2160 if (!dest_rd_atomic) 2161 access_flags &= IB_ACCESS_REMOTE_WRITE; 2162 2163 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2164 !!(access_flags & IB_ACCESS_REMOTE_READ)); 2165 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 2166 2167 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2168 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 2169 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 2170 2171 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2172 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2173 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 2174 } 2175 2176 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 2177 const struct ib_qp_attr *attr, 2178 int attr_mask, 2179 struct hns_roce_v2_qp_context *context, 2180 struct hns_roce_v2_qp_context *qpc_mask) 2181 { 2182 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2183 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2184 2185 /* 2186 * In v2 engine, software pass context and context mask to hardware 2187 * when modifying qp. If software need modify some fields in context, 2188 * we should set all bits of the relevant fields in context mask to 2189 * 0 at the same time, else set them to 0x1. 2190 */ 2191 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2192 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2193 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2194 V2_QPC_BYTE_4_TST_S, 0); 2195 2196 if (ibqp->qp_type == IB_QPT_GSI) 2197 roce_set_field(context->byte_4_sqpn_tst, 2198 V2_QPC_BYTE_4_SGE_SHIFT_M, 2199 V2_QPC_BYTE_4_SGE_SHIFT_S, 2200 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2201 else 2202 roce_set_field(context->byte_4_sqpn_tst, 2203 V2_QPC_BYTE_4_SGE_SHIFT_M, 2204 V2_QPC_BYTE_4_SGE_SHIFT_S, 2205 hr_qp->sq.max_gs > 2 ? 2206 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2207 2208 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2209 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2210 2211 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2212 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2213 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2214 V2_QPC_BYTE_4_SQPN_S, 0); 2215 2216 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2217 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2218 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2219 V2_QPC_BYTE_16_PD_S, 0); 2220 2221 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2222 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 2223 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2224 V2_QPC_BYTE_20_RQWS_S, 0); 2225 2226 roce_set_field(context->byte_20_smac_sgid_idx, 2227 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2228 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2229 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2230 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2231 2232 roce_set_field(context->byte_20_smac_sgid_idx, 2233 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2234 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2235 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2236 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2237 2238 /* No VLAN need to set 0xFFF */ 2239 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2240 V2_QPC_BYTE_24_VLAN_IDX_S, 0xfff); 2241 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2242 V2_QPC_BYTE_24_VLAN_IDX_S, 0); 2243 2244 /* 2245 * Set some fields in context to zero, Because the default values 2246 * of all fields in context are zero, we need not set them to 0 again. 2247 * but we should set the relevant fields of context mask to 0. 2248 */ 2249 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0); 2250 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0); 2251 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0); 2252 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0); 2253 2254 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M, 2255 V2_QPC_BYTE_60_MAPID_S, 0); 2256 2257 roce_set_bit(qpc_mask->byte_60_qpst_mapid, 2258 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0); 2259 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S, 2260 0); 2261 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S, 2262 0); 2263 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S, 2264 0); 2265 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S, 2266 0); 2267 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S, 2268 0); 2269 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0); 2270 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0); 2271 2272 if (attr_mask & IB_QP_QKEY) { 2273 context->qkey_xrcd = attr->qkey; 2274 qpc_mask->qkey_xrcd = 0; 2275 hr_qp->qkey = attr->qkey; 2276 } 2277 2278 if (hr_qp->rdb_en) { 2279 roce_set_bit(context->byte_68_rq_db, 2280 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 2281 roce_set_bit(qpc_mask->byte_68_rq_db, 2282 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0); 2283 } 2284 2285 roce_set_field(context->byte_68_rq_db, 2286 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2287 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 2288 ((u32)hr_qp->rdb.dma) >> 1); 2289 roce_set_field(qpc_mask->byte_68_rq_db, 2290 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2291 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0); 2292 context->rq_db_record_addr = hr_qp->rdb.dma >> 32; 2293 qpc_mask->rq_db_record_addr = 0; 2294 2295 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 2296 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 2297 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0); 2298 2299 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2300 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2301 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2302 V2_QPC_BYTE_80_RX_CQN_S, 0); 2303 if (ibqp->srq) { 2304 roce_set_field(context->byte_76_srqn_op_en, 2305 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2306 to_hr_srq(ibqp->srq)->srqn); 2307 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2308 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2309 roce_set_bit(context->byte_76_srqn_op_en, 2310 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2311 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2312 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2313 } 2314 2315 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2316 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2317 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2318 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2319 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2320 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2321 2322 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M, 2323 V2_QPC_BYTE_92_SRQ_INFO_S, 0); 2324 2325 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2326 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2327 2328 roce_set_field(qpc_mask->byte_104_rq_sge, 2329 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M, 2330 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0); 2331 2332 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2333 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2334 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2335 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2336 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2337 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2338 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0); 2339 2340 qpc_mask->rq_rnr_timer = 0; 2341 qpc_mask->rx_msg_len = 0; 2342 qpc_mask->rx_rkey_pkt_info = 0; 2343 qpc_mask->rx_va = 0; 2344 2345 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2346 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2347 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2348 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2349 2350 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0); 2351 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M, 2352 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0); 2353 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M, 2354 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0); 2355 2356 roce_set_field(qpc_mask->byte_144_raq, 2357 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M, 2358 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0); 2359 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S, 2360 0); 2361 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M, 2362 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0); 2363 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0); 2364 2365 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M, 2366 V2_QPC_BYTE_148_RQ_MSN_S, 0); 2367 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M, 2368 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0); 2369 2370 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2371 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2372 roce_set_field(qpc_mask->byte_152_raq, 2373 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M, 2374 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0); 2375 2376 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M, 2377 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0); 2378 2379 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2380 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 2381 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 2382 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2383 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M, 2384 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0); 2385 2386 roce_set_field(context->byte_168_irrl_idx, 2387 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2388 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2389 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2390 roce_set_field(qpc_mask->byte_168_irrl_idx, 2391 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2392 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2393 2394 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2395 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); 2396 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2397 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0); 2398 roce_set_field(qpc_mask->byte_168_irrl_idx, 2399 V2_QPC_BYTE_168_IRRL_IDX_LSB_M, 2400 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); 2401 2402 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2403 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 2404 roce_set_field(qpc_mask->byte_172_sq_psn, 2405 V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2406 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0); 2407 2408 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S, 2409 0); 2410 2411 roce_set_field(qpc_mask->byte_176_msg_pktn, 2412 V2_QPC_BYTE_176_MSG_USE_PKTN_M, 2413 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0); 2414 roce_set_field(qpc_mask->byte_176_msg_pktn, 2415 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M, 2416 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0); 2417 2418 roce_set_field(qpc_mask->byte_184_irrl_idx, 2419 V2_QPC_BYTE_184_IRRL_IDX_MSB_M, 2420 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0); 2421 2422 qpc_mask->cur_sge_offset = 0; 2423 2424 roce_set_field(qpc_mask->byte_192_ext_sge, 2425 V2_QPC_BYTE_192_CUR_SGE_IDX_M, 2426 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0); 2427 roce_set_field(qpc_mask->byte_192_ext_sge, 2428 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M, 2429 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0); 2430 2431 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 2432 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 2433 2434 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M, 2435 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0); 2436 roce_set_field(qpc_mask->byte_200_sq_max, 2437 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M, 2438 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0); 2439 2440 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0); 2441 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0); 2442 2443 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 2444 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 2445 2446 qpc_mask->sq_timer = 0; 2447 2448 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 2449 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 2450 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 2451 roce_set_field(qpc_mask->byte_232_irrl_sge, 2452 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2453 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2454 2455 qpc_mask->irrl_cur_sge_offset = 0; 2456 2457 roce_set_field(qpc_mask->byte_240_irrl_tail, 2458 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 2459 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 2460 roce_set_field(qpc_mask->byte_240_irrl_tail, 2461 V2_QPC_BYTE_240_IRRL_TAIL_RD_M, 2462 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0); 2463 roce_set_field(qpc_mask->byte_240_irrl_tail, 2464 V2_QPC_BYTE_240_RX_ACK_MSN_M, 2465 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 2466 2467 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M, 2468 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 2469 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S, 2470 0); 2471 roce_set_field(qpc_mask->byte_248_ack_psn, 2472 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 2473 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 2474 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 2475 0); 2476 roce_set_bit(qpc_mask->byte_248_ack_psn, 2477 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 2478 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S, 2479 0); 2480 2481 hr_qp->access_flags = attr->qp_access_flags; 2482 hr_qp->pkey_index = attr->pkey_index; 2483 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2484 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2485 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2486 V2_QPC_BYTE_252_TX_CQN_S, 0); 2487 2488 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M, 2489 V2_QPC_BYTE_252_ERR_TYPE_S, 0); 2490 2491 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2492 V2_QPC_BYTE_256_RQ_CQE_IDX_M, 2493 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0); 2494 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2495 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M, 2496 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0); 2497 } 2498 2499 static void modify_qp_init_to_init(struct ib_qp *ibqp, 2500 const struct ib_qp_attr *attr, int attr_mask, 2501 struct hns_roce_v2_qp_context *context, 2502 struct hns_roce_v2_qp_context *qpc_mask) 2503 { 2504 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2505 2506 /* 2507 * In v2 engine, software pass context and context mask to hardware 2508 * when modifying qp. If software need modify some fields in context, 2509 * we should set all bits of the relevant fields in context mask to 2510 * 0 at the same time, else set them to 0x1. 2511 */ 2512 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2513 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2514 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2515 V2_QPC_BYTE_4_TST_S, 0); 2516 2517 if (ibqp->qp_type == IB_QPT_GSI) 2518 roce_set_field(context->byte_4_sqpn_tst, 2519 V2_QPC_BYTE_4_SGE_SHIFT_M, 2520 V2_QPC_BYTE_4_SGE_SHIFT_S, 2521 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2522 else 2523 roce_set_field(context->byte_4_sqpn_tst, 2524 V2_QPC_BYTE_4_SGE_SHIFT_M, 2525 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ? 2526 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2527 2528 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2529 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2530 2531 if (attr_mask & IB_QP_ACCESS_FLAGS) { 2532 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2533 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 2534 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2535 0); 2536 2537 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2538 !!(attr->qp_access_flags & 2539 IB_ACCESS_REMOTE_WRITE)); 2540 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2541 0); 2542 2543 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2544 !!(attr->qp_access_flags & 2545 IB_ACCESS_REMOTE_ATOMIC)); 2546 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2547 0); 2548 } else { 2549 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2550 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 2551 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2552 0); 2553 2554 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2555 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 2556 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2557 0); 2558 2559 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2560 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2561 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2562 0); 2563 } 2564 2565 roce_set_field(context->byte_20_smac_sgid_idx, 2566 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2567 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2568 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2569 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2570 2571 roce_set_field(context->byte_20_smac_sgid_idx, 2572 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2573 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2574 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2575 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2576 2577 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2578 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2579 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2580 V2_QPC_BYTE_16_PD_S, 0); 2581 2582 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2583 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2584 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2585 V2_QPC_BYTE_80_RX_CQN_S, 0); 2586 2587 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2588 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2589 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2590 V2_QPC_BYTE_252_TX_CQN_S, 0); 2591 2592 if (ibqp->srq) { 2593 roce_set_bit(context->byte_76_srqn_op_en, 2594 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2595 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2596 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2597 roce_set_field(context->byte_76_srqn_op_en, 2598 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2599 to_hr_srq(ibqp->srq)->srqn); 2600 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2601 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2602 } 2603 2604 if (attr_mask & IB_QP_QKEY) { 2605 context->qkey_xrcd = attr->qkey; 2606 qpc_mask->qkey_xrcd = 0; 2607 } 2608 2609 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2610 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2611 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2612 V2_QPC_BYTE_4_SQPN_S, 0); 2613 2614 if (attr_mask & IB_QP_DEST_QPN) { 2615 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2616 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 2617 roce_set_field(qpc_mask->byte_56_dqpn_err, 2618 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 2619 } 2620 roce_set_field(context->byte_168_irrl_idx, 2621 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2622 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2623 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2624 roce_set_field(qpc_mask->byte_168_irrl_idx, 2625 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2626 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2627 } 2628 2629 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 2630 const struct ib_qp_attr *attr, int attr_mask, 2631 struct hns_roce_v2_qp_context *context, 2632 struct hns_roce_v2_qp_context *qpc_mask) 2633 { 2634 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 2635 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2636 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2637 struct device *dev = hr_dev->dev; 2638 dma_addr_t dma_handle_3; 2639 dma_addr_t dma_handle_2; 2640 dma_addr_t dma_handle; 2641 u32 page_size; 2642 u8 port_num; 2643 u64 *mtts_3; 2644 u64 *mtts_2; 2645 u64 *mtts; 2646 u8 *dmac; 2647 u8 *smac; 2648 int port; 2649 2650 /* Search qp buf's mtts */ 2651 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2652 hr_qp->mtt.first_seg, &dma_handle); 2653 if (!mtts) { 2654 dev_err(dev, "qp buf pa find failed\n"); 2655 return -EINVAL; 2656 } 2657 2658 /* Search IRRL's mtts */ 2659 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 2660 hr_qp->qpn, &dma_handle_2); 2661 if (!mtts_2) { 2662 dev_err(dev, "qp irrl_table find failed\n"); 2663 return -EINVAL; 2664 } 2665 2666 /* Search TRRL's mtts */ 2667 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 2668 hr_qp->qpn, &dma_handle_3); 2669 if (!mtts_3) { 2670 dev_err(dev, "qp trrl_table find failed\n"); 2671 return -EINVAL; 2672 } 2673 2674 if (attr_mask & IB_QP_ALT_PATH) { 2675 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask); 2676 return -EINVAL; 2677 } 2678 2679 dmac = (u8 *)attr->ah_attr.roce.dmac; 2680 context->wqe_sge_ba = (u32)(dma_handle >> 3); 2681 qpc_mask->wqe_sge_ba = 0; 2682 2683 /* 2684 * In v2 engine, software pass context and context mask to hardware 2685 * when modifying qp. If software need modify some fields in context, 2686 * we should set all bits of the relevant fields in context mask to 2687 * 0 at the same time, else set them to 0x1. 2688 */ 2689 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2690 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3)); 2691 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2692 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 2693 2694 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2695 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 2696 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2697 0 : hr_dev->caps.mtt_hop_num); 2698 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2699 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 2700 2701 roce_set_field(context->byte_20_smac_sgid_idx, 2702 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2703 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 2704 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2705 hr_dev->caps.mtt_hop_num : 0); 2706 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2707 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2708 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 2709 2710 roce_set_field(context->byte_20_smac_sgid_idx, 2711 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2712 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 2713 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2714 0 : hr_dev->caps.mtt_hop_num); 2715 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2716 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2717 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 2718 2719 roce_set_field(context->byte_16_buf_ba_pg_sz, 2720 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2721 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 2722 hr_dev->caps.mtt_ba_pg_sz); 2723 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2724 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2725 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 2726 2727 roce_set_field(context->byte_16_buf_ba_pg_sz, 2728 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2729 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 2730 hr_dev->caps.mtt_buf_pg_sz); 2731 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2732 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2733 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 2734 2735 roce_set_field(context->byte_80_rnr_rx_cqn, 2736 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2737 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer); 2738 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 2739 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2740 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 2741 2742 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2743 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size] 2744 >> PAGE_ADDR_SHIFT); 2745 qpc_mask->rq_cur_blk_addr = 0; 2746 2747 roce_set_field(context->byte_92_srq_info, 2748 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2749 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 2750 mtts[hr_qp->rq.offset / page_size] 2751 >> (32 + PAGE_ADDR_SHIFT)); 2752 roce_set_field(qpc_mask->byte_92_srq_info, 2753 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2754 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 2755 2756 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1] 2757 >> PAGE_ADDR_SHIFT); 2758 qpc_mask->rq_nxt_blk_addr = 0; 2759 2760 roce_set_field(context->byte_104_rq_sge, 2761 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2762 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 2763 mtts[hr_qp->rq.offset / page_size + 1] 2764 >> (32 + PAGE_ADDR_SHIFT)); 2765 roce_set_field(qpc_mask->byte_104_rq_sge, 2766 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2767 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 2768 2769 roce_set_field(context->byte_108_rx_reqepsn, 2770 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2771 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 2772 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2773 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2774 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 2775 2776 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2777 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4); 2778 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2779 V2_QPC_BYTE_132_TRRL_BA_S, 0); 2780 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4)); 2781 qpc_mask->trrl_ba = 0; 2782 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2783 V2_QPC_BYTE_140_TRRL_BA_S, 2784 (u32)(dma_handle_3 >> (32 + 16 + 4))); 2785 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2786 V2_QPC_BYTE_140_TRRL_BA_S, 0); 2787 2788 context->irrl_ba = (u32)(dma_handle_2 >> 6); 2789 qpc_mask->irrl_ba = 0; 2790 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2791 V2_QPC_BYTE_208_IRRL_BA_S, 2792 dma_handle_2 >> (32 + 6)); 2793 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2794 V2_QPC_BYTE_208_IRRL_BA_S, 0); 2795 2796 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 2797 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 2798 2799 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2800 hr_qp->sq_signal_bits); 2801 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2802 0); 2803 2804 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 2805 2806 smac = (u8 *)hr_dev->dev_addr[port]; 2807 /* when dmac equals smac or loop_idc is 1, it should loopback */ 2808 if (ether_addr_equal_unaligned(dmac, smac) || 2809 hr_dev->loop_idc == 0x1) { 2810 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 2811 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 2812 } 2813 2814 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 2815 attr->max_dest_rd_atomic) { 2816 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2817 V2_QPC_BYTE_140_RR_MAX_S, 2818 fls(attr->max_dest_rd_atomic - 1)); 2819 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2820 V2_QPC_BYTE_140_RR_MAX_S, 0); 2821 } 2822 2823 if (attr_mask & IB_QP_DEST_QPN) { 2824 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2825 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 2826 roce_set_field(qpc_mask->byte_56_dqpn_err, 2827 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 2828 } 2829 2830 /* Configure GID index */ 2831 port_num = rdma_ah_get_port_num(&attr->ah_attr); 2832 roce_set_field(context->byte_20_smac_sgid_idx, 2833 V2_QPC_BYTE_20_SGID_IDX_M, 2834 V2_QPC_BYTE_20_SGID_IDX_S, 2835 hns_get_gid_index(hr_dev, port_num - 1, 2836 grh->sgid_index)); 2837 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2838 V2_QPC_BYTE_20_SGID_IDX_M, 2839 V2_QPC_BYTE_20_SGID_IDX_S, 0); 2840 memcpy(&(context->dmac), dmac, 4); 2841 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2842 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 2843 qpc_mask->dmac = 0; 2844 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2845 V2_QPC_BYTE_52_DMAC_S, 0); 2846 2847 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2848 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4); 2849 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2850 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 2851 2852 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2853 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 2854 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2855 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 2856 2857 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2858 V2_QPC_BYTE_28_FL_S, grh->flow_label); 2859 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2860 V2_QPC_BYTE_28_FL_S, 0); 2861 2862 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2863 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 2864 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2865 V2_QPC_BYTE_24_TC_S, 0); 2866 2867 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 2868 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2869 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); 2870 else if (attr_mask & IB_QP_PATH_MTU) 2871 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2872 V2_QPC_BYTE_24_MTU_S, attr->path_mtu); 2873 2874 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2875 V2_QPC_BYTE_24_MTU_S, 0); 2876 2877 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 2878 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 2879 2880 roce_set_field(context->byte_84_rq_ci_pi, 2881 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2882 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 2883 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2884 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2885 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2886 2887 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2888 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2889 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2890 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2891 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2892 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2893 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2894 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2895 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2896 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2897 2898 context->rq_rnr_timer = 0; 2899 qpc_mask->rq_rnr_timer = 0; 2900 2901 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2902 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 2903 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2904 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2905 2906 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2907 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2908 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2909 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2910 2911 roce_set_field(context->byte_168_irrl_idx, 2912 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2913 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 2914 roce_set_field(qpc_mask->byte_168_irrl_idx, 2915 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2916 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 2917 2918 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2919 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 2920 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2921 V2_QPC_BYTE_28_SL_S, 0); 2922 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 2923 2924 return 0; 2925 } 2926 2927 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 2928 const struct ib_qp_attr *attr, int attr_mask, 2929 struct hns_roce_v2_qp_context *context, 2930 struct hns_roce_v2_qp_context *qpc_mask) 2931 { 2932 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2933 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2934 struct device *dev = hr_dev->dev; 2935 dma_addr_t dma_handle; 2936 u32 page_size; 2937 u64 *mtts; 2938 2939 /* Search qp buf's mtts */ 2940 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2941 hr_qp->mtt.first_seg, &dma_handle); 2942 if (!mtts) { 2943 dev_err(dev, "qp buf pa find failed\n"); 2944 return -EINVAL; 2945 } 2946 2947 /* Not support alternate path and path migration */ 2948 if ((attr_mask & IB_QP_ALT_PATH) || 2949 (attr_mask & IB_QP_PATH_MIG_STATE)) { 2950 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 2951 return -EINVAL; 2952 } 2953 2954 /* 2955 * In v2 engine, software pass context and context mask to hardware 2956 * when modifying qp. If software need modify some fields in context, 2957 * we should set all bits of the relevant fields in context mask to 2958 * 0 at the same time, else set them to 0x1. 2959 */ 2960 roce_set_field(context->byte_60_qpst_mapid, 2961 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2962 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt); 2963 roce_set_field(qpc_mask->byte_60_qpst_mapid, 2964 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2965 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0); 2966 2967 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2968 roce_set_field(context->byte_168_irrl_idx, 2969 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2970 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 2971 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2972 qpc_mask->sq_cur_blk_addr = 0; 2973 roce_set_field(qpc_mask->byte_168_irrl_idx, 2974 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2975 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 2976 2977 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2978 context->sq_cur_sge_blk_addr = 2979 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2980 ((u32)(mtts[hr_qp->sge.offset / page_size] 2981 >> PAGE_ADDR_SHIFT)) : 0; 2982 roce_set_field(context->byte_184_irrl_idx, 2983 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2984 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 2985 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2986 (mtts[hr_qp->sge.offset / page_size] >> 2987 (32 + PAGE_ADDR_SHIFT)) : 0); 2988 qpc_mask->sq_cur_sge_blk_addr = 0; 2989 roce_set_field(qpc_mask->byte_184_irrl_idx, 2990 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2991 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 2992 2993 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2994 roce_set_field(context->byte_232_irrl_sge, 2995 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 2996 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 2997 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2998 qpc_mask->rx_sq_cur_blk_addr = 0; 2999 roce_set_field(qpc_mask->byte_232_irrl_sge, 3000 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3001 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 3002 3003 /* 3004 * Set some fields in context to zero, Because the default values 3005 * of all fields in context are zero, we need not set them to 0 again. 3006 * but we should set the relevant fields of context mask to 0. 3007 */ 3008 roce_set_field(qpc_mask->byte_232_irrl_sge, 3009 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 3010 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 3011 3012 roce_set_field(qpc_mask->byte_240_irrl_tail, 3013 V2_QPC_BYTE_240_RX_ACK_MSN_M, 3014 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 3015 3016 roce_set_field(context->byte_244_rnr_rxack, 3017 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3018 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 3019 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3020 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3021 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 3022 3023 roce_set_field(qpc_mask->byte_248_ack_psn, 3024 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 3025 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 3026 roce_set_bit(qpc_mask->byte_248_ack_psn, 3027 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 3028 roce_set_field(qpc_mask->byte_248_ack_psn, 3029 V2_QPC_BYTE_248_IRRL_PSN_M, 3030 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 3031 3032 roce_set_field(qpc_mask->byte_240_irrl_tail, 3033 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 3034 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 3035 3036 roce_set_field(context->byte_220_retry_psn_msn, 3037 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3038 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 3039 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3040 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3041 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 3042 3043 roce_set_field(context->byte_224_retry_msg, 3044 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3045 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16); 3046 roce_set_field(qpc_mask->byte_224_retry_msg, 3047 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3048 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 3049 3050 roce_set_field(context->byte_224_retry_msg, 3051 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3052 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn); 3053 roce_set_field(qpc_mask->byte_224_retry_msg, 3054 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3055 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 3056 3057 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3058 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 3059 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 3060 3061 roce_set_bit(qpc_mask->byte_248_ack_psn, 3062 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 3063 3064 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 3065 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 3066 3067 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3068 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 3069 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3070 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 3071 3072 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3073 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt); 3074 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3075 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 3076 3077 roce_set_field(context->byte_244_rnr_rxack, 3078 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3079 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 3080 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3081 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3082 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 3083 3084 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3085 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 3086 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3087 V2_QPC_BYTE_244_RNR_CNT_S, 0); 3088 3089 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3090 V2_QPC_BYTE_212_LSN_S, 0x100); 3091 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3092 V2_QPC_BYTE_212_LSN_S, 0); 3093 3094 if (attr_mask & IB_QP_TIMEOUT) { 3095 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3096 V2_QPC_BYTE_28_AT_S, attr->timeout); 3097 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3098 V2_QPC_BYTE_28_AT_S, 0); 3099 } 3100 3101 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3102 V2_QPC_BYTE_28_SL_S, 3103 rdma_ah_get_sl(&attr->ah_attr)); 3104 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3105 V2_QPC_BYTE_28_SL_S, 0); 3106 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 3107 3108 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3109 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 3110 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3111 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 3112 3113 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 3114 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 3115 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3116 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 3117 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3118 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 3119 3120 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 3121 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 3122 V2_QPC_BYTE_208_SR_MAX_S, 3123 fls(attr->max_rd_atomic - 1)); 3124 roce_set_field(qpc_mask->byte_208_irrl, 3125 V2_QPC_BYTE_208_SR_MAX_M, 3126 V2_QPC_BYTE_208_SR_MAX_S, 0); 3127 } 3128 return 0; 3129 } 3130 3131 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 3132 const struct ib_qp_attr *attr, 3133 int attr_mask, enum ib_qp_state cur_state, 3134 enum ib_qp_state new_state) 3135 { 3136 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3137 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3138 struct hns_roce_v2_qp_context *context; 3139 struct hns_roce_v2_qp_context *qpc_mask; 3140 struct device *dev = hr_dev->dev; 3141 int ret = -EINVAL; 3142 3143 context = kzalloc(2 * sizeof(*context), GFP_KERNEL); 3144 if (!context) 3145 return -ENOMEM; 3146 3147 qpc_mask = context + 1; 3148 /* 3149 * In v2 engine, software pass context and context mask to hardware 3150 * when modifying qp. If software need modify some fields in context, 3151 * we should set all bits of the relevant fields in context mask to 3152 * 0 at the same time, else set them to 0x1. 3153 */ 3154 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 3155 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3156 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 3157 qpc_mask); 3158 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3159 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 3160 qpc_mask); 3161 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3162 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 3163 qpc_mask); 3164 if (ret) 3165 goto out; 3166 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3167 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 3168 qpc_mask); 3169 if (ret) 3170 goto out; 3171 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) || 3172 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) || 3173 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) || 3174 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) || 3175 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) || 3176 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) || 3177 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) || 3178 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) || 3179 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) || 3180 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) || 3181 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) || 3182 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) || 3183 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) || 3184 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) || 3185 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) { 3186 /* Nothing */ 3187 ; 3188 } else { 3189 dev_err(dev, "Illegal state for QP!\n"); 3190 goto out; 3191 } 3192 3193 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3194 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 3195 3196 /* Every status migrate must change state */ 3197 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3198 V2_QPC_BYTE_60_QP_ST_S, new_state); 3199 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3200 V2_QPC_BYTE_60_QP_ST_S, 0); 3201 3202 /* SW pass context to HW */ 3203 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state, 3204 context, hr_qp); 3205 if (ret) { 3206 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret); 3207 goto out; 3208 } 3209 3210 hr_qp->state = new_state; 3211 3212 if (attr_mask & IB_QP_ACCESS_FLAGS) 3213 hr_qp->atomic_rd_en = attr->qp_access_flags; 3214 3215 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3216 hr_qp->resp_depth = attr->max_dest_rd_atomic; 3217 if (attr_mask & IB_QP_PORT) { 3218 hr_qp->port = attr->port_num - 1; 3219 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 3220 } 3221 3222 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3223 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 3224 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 3225 if (ibqp->send_cq != ibqp->recv_cq) 3226 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 3227 hr_qp->qpn, NULL); 3228 3229 hr_qp->rq.head = 0; 3230 hr_qp->rq.tail = 0; 3231 hr_qp->sq.head = 0; 3232 hr_qp->sq.tail = 0; 3233 hr_qp->sq_next_wqe = 0; 3234 hr_qp->next_sge = 0; 3235 if (hr_qp->rq.wqe_cnt) 3236 *hr_qp->rdb.db_record = 0; 3237 } 3238 3239 out: 3240 kfree(context); 3241 return ret; 3242 } 3243 3244 static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state) 3245 { 3246 switch (state) { 3247 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET; 3248 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT; 3249 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR; 3250 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS; 3251 case HNS_ROCE_QP_ST_SQ_DRAINING: 3252 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD; 3253 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE; 3254 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR; 3255 default: return -1; 3256 } 3257 } 3258 3259 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 3260 struct hns_roce_qp *hr_qp, 3261 struct hns_roce_v2_qp_context *hr_context) 3262 { 3263 struct hns_roce_cmd_mailbox *mailbox; 3264 int ret; 3265 3266 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3267 if (IS_ERR(mailbox)) 3268 return PTR_ERR(mailbox); 3269 3270 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 3271 HNS_ROCE_CMD_QUERY_QPC, 3272 HNS_ROCE_CMD_TIMEOUT_MSECS); 3273 if (ret) { 3274 dev_err(hr_dev->dev, "QUERY QP cmd process error\n"); 3275 goto out; 3276 } 3277 3278 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 3279 3280 out: 3281 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3282 return ret; 3283 } 3284 3285 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3286 int qp_attr_mask, 3287 struct ib_qp_init_attr *qp_init_attr) 3288 { 3289 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3290 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3291 struct hns_roce_v2_qp_context *context; 3292 struct device *dev = hr_dev->dev; 3293 int tmp_qp_state; 3294 int state; 3295 int ret; 3296 3297 context = kzalloc(sizeof(*context), GFP_KERNEL); 3298 if (!context) 3299 return -ENOMEM; 3300 3301 memset(qp_attr, 0, sizeof(*qp_attr)); 3302 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 3303 3304 mutex_lock(&hr_qp->mutex); 3305 3306 if (hr_qp->state == IB_QPS_RESET) { 3307 qp_attr->qp_state = IB_QPS_RESET; 3308 ret = 0; 3309 goto done; 3310 } 3311 3312 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context); 3313 if (ret) { 3314 dev_err(dev, "query qpc error\n"); 3315 ret = -EINVAL; 3316 goto out; 3317 } 3318 3319 state = roce_get_field(context->byte_60_qpst_mapid, 3320 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 3321 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 3322 if (tmp_qp_state == -1) { 3323 dev_err(dev, "Illegal ib_qp_state\n"); 3324 ret = -EINVAL; 3325 goto out; 3326 } 3327 hr_qp->state = (u8)tmp_qp_state; 3328 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 3329 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc, 3330 V2_QPC_BYTE_24_MTU_M, 3331 V2_QPC_BYTE_24_MTU_S); 3332 qp_attr->path_mig_state = IB_MIG_ARMED; 3333 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3334 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 3335 qp_attr->qkey = V2_QKEY_VAL; 3336 3337 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn, 3338 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3339 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 3340 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn, 3341 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3342 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 3343 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err, 3344 V2_QPC_BYTE_56_DQPN_M, 3345 V2_QPC_BYTE_56_DQPN_S); 3346 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en, 3347 V2_QPC_BYTE_76_RRE_S)) << 2) | 3348 ((roce_get_bit(context->byte_76_srqn_op_en, 3349 V2_QPC_BYTE_76_RWE_S)) << 1) | 3350 ((roce_get_bit(context->byte_76_srqn_op_en, 3351 V2_QPC_BYTE_76_ATE_S)) << 3); 3352 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 3353 hr_qp->ibqp.qp_type == IB_QPT_UC) { 3354 struct ib_global_route *grh = 3355 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 3356 3357 rdma_ah_set_sl(&qp_attr->ah_attr, 3358 roce_get_field(context->byte_28_at_fl, 3359 V2_QPC_BYTE_28_SL_M, 3360 V2_QPC_BYTE_28_SL_S)); 3361 grh->flow_label = roce_get_field(context->byte_28_at_fl, 3362 V2_QPC_BYTE_28_FL_M, 3363 V2_QPC_BYTE_28_FL_S); 3364 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx, 3365 V2_QPC_BYTE_20_SGID_IDX_M, 3366 V2_QPC_BYTE_20_SGID_IDX_S); 3367 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc, 3368 V2_QPC_BYTE_24_HOP_LIMIT_M, 3369 V2_QPC_BYTE_24_HOP_LIMIT_S); 3370 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc, 3371 V2_QPC_BYTE_24_TC_M, 3372 V2_QPC_BYTE_24_TC_S); 3373 3374 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw)); 3375 } 3376 3377 qp_attr->port_num = hr_qp->port + 1; 3378 qp_attr->sq_draining = 0; 3379 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl, 3380 V2_QPC_BYTE_208_SR_MAX_M, 3381 V2_QPC_BYTE_208_SR_MAX_S); 3382 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq, 3383 V2_QPC_BYTE_140_RR_MAX_M, 3384 V2_QPC_BYTE_140_RR_MAX_S); 3385 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn, 3386 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3387 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 3388 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl, 3389 V2_QPC_BYTE_28_AT_M, 3390 V2_QPC_BYTE_28_AT_S); 3391 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn, 3392 V2_QPC_BYTE_212_RETRY_CNT_M, 3393 V2_QPC_BYTE_212_RETRY_CNT_S); 3394 qp_attr->rnr_retry = context->rq_rnr_timer; 3395 3396 done: 3397 qp_attr->cur_qp_state = qp_attr->qp_state; 3398 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 3399 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 3400 3401 if (!ibqp->uobject) { 3402 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 3403 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 3404 } else { 3405 qp_attr->cap.max_send_wr = 0; 3406 qp_attr->cap.max_send_sge = 0; 3407 } 3408 3409 qp_init_attr->cap = qp_attr->cap; 3410 3411 out: 3412 mutex_unlock(&hr_qp->mutex); 3413 kfree(context); 3414 return ret; 3415 } 3416 3417 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 3418 struct hns_roce_qp *hr_qp, 3419 int is_user) 3420 { 3421 struct hns_roce_cq *send_cq, *recv_cq; 3422 struct device *dev = hr_dev->dev; 3423 int ret; 3424 3425 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 3426 /* Modify qp to reset before destroying qp */ 3427 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 3428 hr_qp->state, IB_QPS_RESET); 3429 if (ret) { 3430 dev_err(dev, "modify QP %06lx to ERR failed.\n", 3431 hr_qp->qpn); 3432 return ret; 3433 } 3434 } 3435 3436 send_cq = to_hr_cq(hr_qp->ibqp.send_cq); 3437 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq); 3438 3439 hns_roce_lock_cqs(send_cq, recv_cq); 3440 3441 if (!is_user) { 3442 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ? 3443 to_hr_srq(hr_qp->ibqp.srq) : NULL); 3444 if (send_cq != recv_cq) 3445 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 3446 } 3447 3448 hns_roce_qp_remove(hr_dev, hr_qp); 3449 3450 hns_roce_unlock_cqs(send_cq, recv_cq); 3451 3452 hns_roce_qp_free(hr_dev, hr_qp); 3453 3454 /* Not special_QP, free their QPN */ 3455 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) || 3456 (hr_qp->ibqp.qp_type == IB_QPT_UC) || 3457 (hr_qp->ibqp.qp_type == IB_QPT_UD)) 3458 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1); 3459 3460 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 3461 3462 if (is_user) { 3463 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1)) 3464 hns_roce_db_unmap_user( 3465 to_hr_ucontext(hr_qp->ibqp.uobject->context), 3466 &hr_qp->rdb); 3467 ib_umem_release(hr_qp->umem); 3468 } else { 3469 kfree(hr_qp->sq.wrid); 3470 kfree(hr_qp->rq.wrid); 3471 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 3472 if (hr_qp->rq.wqe_cnt) 3473 hns_roce_free_db(hr_dev, &hr_qp->rdb); 3474 } 3475 3476 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 3477 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 3478 kfree(hr_qp->rq_inl_buf.wqe_list); 3479 } 3480 3481 return 0; 3482 } 3483 3484 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp) 3485 { 3486 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3487 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3488 int ret; 3489 3490 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject); 3491 if (ret) { 3492 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret); 3493 return ret; 3494 } 3495 3496 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 3497 kfree(hr_to_hr_sqp(hr_qp)); 3498 else 3499 kfree(hr_qp); 3500 3501 return 0; 3502 } 3503 3504 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 3505 { 3506 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 3507 struct hns_roce_v2_cq_context *cq_context; 3508 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 3509 struct hns_roce_v2_cq_context *cqc_mask; 3510 struct hns_roce_cmd_mailbox *mailbox; 3511 int ret; 3512 3513 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3514 if (IS_ERR(mailbox)) 3515 return PTR_ERR(mailbox); 3516 3517 cq_context = mailbox->buf; 3518 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 3519 3520 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 3521 3522 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3523 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3524 cq_count); 3525 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3526 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3527 0); 3528 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3529 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3530 cq_period); 3531 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3532 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3533 0); 3534 3535 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 3536 HNS_ROCE_CMD_MODIFY_CQC, 3537 HNS_ROCE_CMD_TIMEOUT_MSECS); 3538 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3539 if (ret) 3540 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n"); 3541 3542 return ret; 3543 } 3544 3545 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 3546 { 3547 u32 doorbell[2]; 3548 3549 doorbell[0] = 0; 3550 doorbell[1] = 0; 3551 3552 if (eq->type_flag == HNS_ROCE_AEQ) { 3553 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3554 HNS_ROCE_V2_EQ_DB_CMD_S, 3555 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3556 HNS_ROCE_EQ_DB_CMD_AEQ : 3557 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 3558 } else { 3559 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 3560 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 3561 3562 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3563 HNS_ROCE_V2_EQ_DB_CMD_S, 3564 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3565 HNS_ROCE_EQ_DB_CMD_CEQ : 3566 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 3567 } 3568 3569 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 3570 HNS_ROCE_V2_EQ_DB_PARA_S, 3571 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 3572 3573 hns_roce_write64_k(doorbell, eq->doorbell); 3574 } 3575 3576 static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev, 3577 struct hns_roce_aeqe *aeqe, 3578 u32 qpn) 3579 { 3580 struct device *dev = hr_dev->dev; 3581 int sub_type; 3582 3583 dev_warn(dev, "Local work queue catastrophic error.\n"); 3584 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3585 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3586 switch (sub_type) { 3587 case HNS_ROCE_LWQCE_QPC_ERROR: 3588 dev_warn(dev, "QP %d, QPC error.\n", qpn); 3589 break; 3590 case HNS_ROCE_LWQCE_MTU_ERROR: 3591 dev_warn(dev, "QP %d, MTU error.\n", qpn); 3592 break; 3593 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR: 3594 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn); 3595 break; 3596 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR: 3597 dev_warn(dev, "QP %d, WQE addr error.\n", qpn); 3598 break; 3599 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR: 3600 dev_warn(dev, "QP %d, WQE shift error.\n", qpn); 3601 break; 3602 default: 3603 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3604 break; 3605 } 3606 } 3607 3608 static void hns_roce_v2_local_wq_access_err_handle(struct hns_roce_dev *hr_dev, 3609 struct hns_roce_aeqe *aeqe, u32 qpn) 3610 { 3611 struct device *dev = hr_dev->dev; 3612 int sub_type; 3613 3614 dev_warn(dev, "Local access violation work queue error.\n"); 3615 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3616 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3617 switch (sub_type) { 3618 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION: 3619 dev_warn(dev, "QP %d, R_key violation.\n", qpn); 3620 break; 3621 case HNS_ROCE_LAVWQE_LENGTH_ERROR: 3622 dev_warn(dev, "QP %d, length error.\n", qpn); 3623 break; 3624 case HNS_ROCE_LAVWQE_VA_ERROR: 3625 dev_warn(dev, "QP %d, VA error.\n", qpn); 3626 break; 3627 case HNS_ROCE_LAVWQE_PD_ERROR: 3628 dev_err(dev, "QP %d, PD error.\n", qpn); 3629 break; 3630 case HNS_ROCE_LAVWQE_RW_ACC_ERROR: 3631 dev_warn(dev, "QP %d, rw acc error.\n", qpn); 3632 break; 3633 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR: 3634 dev_warn(dev, "QP %d, key state error.\n", qpn); 3635 break; 3636 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR: 3637 dev_warn(dev, "QP %d, MR operation error.\n", qpn); 3638 break; 3639 default: 3640 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3641 break; 3642 } 3643 } 3644 3645 static void hns_roce_v2_qp_err_handle(struct hns_roce_dev *hr_dev, 3646 struct hns_roce_aeqe *aeqe, 3647 int event_type) 3648 { 3649 struct device *dev = hr_dev->dev; 3650 u32 qpn; 3651 3652 qpn = roce_get_field(aeqe->event.qp_event.qp, 3653 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3654 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3655 3656 switch (event_type) { 3657 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3658 dev_warn(dev, "Communication established.\n"); 3659 break; 3660 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3661 dev_warn(dev, "Send queue drained.\n"); 3662 break; 3663 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3664 hns_roce_v2_wq_catas_err_handle(hr_dev, aeqe, qpn); 3665 break; 3666 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3667 dev_warn(dev, "Invalid request local work queue error.\n"); 3668 break; 3669 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3670 hns_roce_v2_local_wq_access_err_handle(hr_dev, aeqe, qpn); 3671 break; 3672 default: 3673 break; 3674 } 3675 3676 hns_roce_qp_event(hr_dev, qpn, event_type); 3677 } 3678 3679 static void hns_roce_v2_cq_err_handle(struct hns_roce_dev *hr_dev, 3680 struct hns_roce_aeqe *aeqe, 3681 int event_type) 3682 { 3683 struct device *dev = hr_dev->dev; 3684 u32 cqn; 3685 3686 cqn = roce_get_field(aeqe->event.cq_event.cq, 3687 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3688 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3689 3690 switch (event_type) { 3691 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3692 dev_warn(dev, "CQ 0x%x access err.\n", cqn); 3693 break; 3694 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3695 dev_warn(dev, "CQ 0x%x overflow\n", cqn); 3696 break; 3697 default: 3698 break; 3699 } 3700 3701 hns_roce_cq_event(hr_dev, cqn, event_type); 3702 } 3703 3704 static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry) 3705 { 3706 u32 buf_chk_sz; 3707 unsigned long off; 3708 3709 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3710 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3711 3712 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) + 3713 off % buf_chk_sz); 3714 } 3715 3716 static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry) 3717 { 3718 u32 buf_chk_sz; 3719 unsigned long off; 3720 3721 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3722 3723 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3724 3725 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3726 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) + 3727 off % buf_chk_sz); 3728 else 3729 return (struct hns_roce_aeqe *)((u8 *) 3730 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz); 3731 } 3732 3733 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 3734 { 3735 struct hns_roce_aeqe *aeqe; 3736 3737 if (!eq->hop_num) 3738 aeqe = get_aeqe_v2(eq, eq->cons_index); 3739 else 3740 aeqe = mhop_get_aeqe(eq, eq->cons_index); 3741 3742 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 3743 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 3744 } 3745 3746 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 3747 struct hns_roce_eq *eq) 3748 { 3749 struct device *dev = hr_dev->dev; 3750 struct hns_roce_aeqe *aeqe; 3751 int aeqe_found = 0; 3752 int event_type; 3753 3754 while ((aeqe = next_aeqe_sw_v2(eq))) { 3755 3756 /* Make sure we read AEQ entry after we have checked the 3757 * ownership bit 3758 */ 3759 dma_rmb(); 3760 3761 event_type = roce_get_field(aeqe->asyn, 3762 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 3763 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 3764 3765 switch (event_type) { 3766 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 3767 dev_warn(dev, "Path migrated succeeded.\n"); 3768 break; 3769 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 3770 dev_warn(dev, "Path migration failed.\n"); 3771 break; 3772 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3773 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3774 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3775 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3776 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3777 hns_roce_v2_qp_err_handle(hr_dev, aeqe, event_type); 3778 break; 3779 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 3780 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 3781 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 3782 dev_warn(dev, "SRQ not support.\n"); 3783 break; 3784 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3785 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3786 hns_roce_v2_cq_err_handle(hr_dev, aeqe, event_type); 3787 break; 3788 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 3789 dev_warn(dev, "DB overflow.\n"); 3790 break; 3791 case HNS_ROCE_EVENT_TYPE_MB: 3792 hns_roce_cmd_event(hr_dev, 3793 le16_to_cpu(aeqe->event.cmd.token), 3794 aeqe->event.cmd.status, 3795 le64_to_cpu(aeqe->event.cmd.out_param)); 3796 break; 3797 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 3798 dev_warn(dev, "CEQ overflow.\n"); 3799 break; 3800 case HNS_ROCE_EVENT_TYPE_FLR: 3801 dev_warn(dev, "Function level reset.\n"); 3802 break; 3803 default: 3804 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 3805 event_type, eq->eqn, eq->cons_index); 3806 break; 3807 }; 3808 3809 ++eq->cons_index; 3810 aeqe_found = 1; 3811 3812 if (eq->cons_index > (2 * eq->entries - 1)) { 3813 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3814 eq->cons_index = 0; 3815 } 3816 } 3817 3818 set_eq_cons_index_v2(eq); 3819 return aeqe_found; 3820 } 3821 3822 static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry) 3823 { 3824 u32 buf_chk_sz; 3825 unsigned long off; 3826 3827 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3828 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3829 3830 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) + 3831 off % buf_chk_sz); 3832 } 3833 3834 static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry) 3835 { 3836 u32 buf_chk_sz; 3837 unsigned long off; 3838 3839 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3840 3841 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3842 3843 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3844 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) + 3845 off % buf_chk_sz); 3846 else 3847 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off / 3848 buf_chk_sz]) + off % buf_chk_sz); 3849 } 3850 3851 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 3852 { 3853 struct hns_roce_ceqe *ceqe; 3854 3855 if (!eq->hop_num) 3856 ceqe = get_ceqe_v2(eq, eq->cons_index); 3857 else 3858 ceqe = mhop_get_ceqe(eq, eq->cons_index); 3859 3860 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 3861 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 3862 } 3863 3864 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 3865 struct hns_roce_eq *eq) 3866 { 3867 struct device *dev = hr_dev->dev; 3868 struct hns_roce_ceqe *ceqe; 3869 int ceqe_found = 0; 3870 u32 cqn; 3871 3872 while ((ceqe = next_ceqe_sw_v2(eq))) { 3873 3874 /* Make sure we read CEQ entry after we have checked the 3875 * ownership bit 3876 */ 3877 dma_rmb(); 3878 3879 cqn = roce_get_field(ceqe->comp, 3880 HNS_ROCE_V2_CEQE_COMP_CQN_M, 3881 HNS_ROCE_V2_CEQE_COMP_CQN_S); 3882 3883 hns_roce_cq_completion(hr_dev, cqn); 3884 3885 ++eq->cons_index; 3886 ceqe_found = 1; 3887 3888 if (eq->cons_index > (2 * eq->entries - 1)) { 3889 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3890 eq->cons_index = 0; 3891 } 3892 } 3893 3894 set_eq_cons_index_v2(eq); 3895 3896 return ceqe_found; 3897 } 3898 3899 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 3900 { 3901 struct hns_roce_eq *eq = eq_ptr; 3902 struct hns_roce_dev *hr_dev = eq->hr_dev; 3903 int int_work = 0; 3904 3905 if (eq->type_flag == HNS_ROCE_CEQ) 3906 /* Completion event interrupt */ 3907 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 3908 else 3909 /* Asychronous event interrupt */ 3910 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 3911 3912 return IRQ_RETVAL(int_work); 3913 } 3914 3915 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 3916 { 3917 struct hns_roce_dev *hr_dev = dev_id; 3918 struct device *dev = hr_dev->dev; 3919 int int_work = 0; 3920 u32 int_st; 3921 u32 int_en; 3922 3923 /* Abnormal interrupt */ 3924 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 3925 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 3926 3927 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 3928 dev_err(dev, "AEQ overflow!\n"); 3929 3930 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1); 3931 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3932 3933 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3934 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3935 3936 int_work = 1; 3937 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 3938 dev_err(dev, "BUS ERR!\n"); 3939 3940 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1); 3941 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3942 3943 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3944 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3945 3946 int_work = 1; 3947 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 3948 dev_err(dev, "OTHER ERR!\n"); 3949 3950 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1); 3951 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3952 3953 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3954 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3955 3956 int_work = 1; 3957 } else 3958 dev_err(dev, "There is no abnormal irq found!\n"); 3959 3960 return IRQ_RETVAL(int_work); 3961 } 3962 3963 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 3964 int eq_num, int enable_flag) 3965 { 3966 int i; 3967 3968 if (enable_flag == EQ_ENABLE) { 3969 for (i = 0; i < eq_num; i++) 3970 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3971 i * EQ_REG_OFFSET, 3972 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 3973 3974 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3975 HNS_ROCE_V2_VF_ABN_INT_EN_M); 3976 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3977 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 3978 } else { 3979 for (i = 0; i < eq_num; i++) 3980 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3981 i * EQ_REG_OFFSET, 3982 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 3983 3984 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3985 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 3986 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3987 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 3988 } 3989 } 3990 3991 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 3992 { 3993 struct device *dev = hr_dev->dev; 3994 int ret; 3995 3996 if (eqn < hr_dev->caps.num_comp_vectors) 3997 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 3998 0, HNS_ROCE_CMD_DESTROY_CEQC, 3999 HNS_ROCE_CMD_TIMEOUT_MSECS); 4000 else 4001 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 4002 0, HNS_ROCE_CMD_DESTROY_AEQC, 4003 HNS_ROCE_CMD_TIMEOUT_MSECS); 4004 if (ret) 4005 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 4006 } 4007 4008 static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev, 4009 struct hns_roce_eq *eq) 4010 { 4011 struct device *dev = hr_dev->dev; 4012 u64 idx; 4013 u64 size; 4014 u32 buf_chk_sz; 4015 u32 bt_chk_sz; 4016 u32 mhop_num; 4017 int eqe_alloc; 4018 int ba_num; 4019 int i = 0; 4020 int j = 0; 4021 4022 mhop_num = hr_dev->caps.eqe_hop_num; 4023 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4024 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4025 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) / 4026 buf_chk_sz; 4027 4028 /* hop_num = 0 */ 4029 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4030 dma_free_coherent(dev, (unsigned int)(eq->entries * 4031 eq->eqe_size), eq->bt_l0, eq->l0_dma); 4032 return; 4033 } 4034 4035 /* hop_num = 1 or hop = 2 */ 4036 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4037 if (mhop_num == 1) { 4038 for (i = 0; i < eq->l0_last_num; i++) { 4039 if (i == eq->l0_last_num - 1) { 4040 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4041 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4042 dma_free_coherent(dev, size, eq->buf[i], 4043 eq->buf_dma[i]); 4044 break; 4045 } 4046 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4047 eq->buf_dma[i]); 4048 } 4049 } else if (mhop_num == 2) { 4050 for (i = 0; i < eq->l0_last_num; i++) { 4051 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4052 eq->l1_dma[i]); 4053 4054 for (j = 0; j < bt_chk_sz / 8; j++) { 4055 idx = i * (bt_chk_sz / 8) + j; 4056 if ((i == eq->l0_last_num - 1) 4057 && j == eq->l1_last_num - 1) { 4058 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4059 * idx; 4060 size = (eq->entries - eqe_alloc) 4061 * eq->eqe_size; 4062 dma_free_coherent(dev, size, 4063 eq->buf[idx], 4064 eq->buf_dma[idx]); 4065 break; 4066 } 4067 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4068 eq->buf_dma[idx]); 4069 } 4070 } 4071 } 4072 kfree(eq->buf_dma); 4073 kfree(eq->buf); 4074 kfree(eq->l1_dma); 4075 kfree(eq->bt_l1); 4076 eq->buf_dma = NULL; 4077 eq->buf = NULL; 4078 eq->l1_dma = NULL; 4079 eq->bt_l1 = NULL; 4080 } 4081 4082 static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev, 4083 struct hns_roce_eq *eq) 4084 { 4085 u32 buf_chk_sz; 4086 4087 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4088 4089 if (hr_dev->caps.eqe_hop_num) { 4090 hns_roce_mhop_free_eq(hr_dev, eq); 4091 return; 4092 } 4093 4094 if (eq->buf_list) 4095 dma_free_coherent(hr_dev->dev, buf_chk_sz, 4096 eq->buf_list->buf, eq->buf_list->map); 4097 } 4098 4099 static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, 4100 struct hns_roce_eq *eq, 4101 void *mb_buf) 4102 { 4103 struct hns_roce_eq_context *eqc; 4104 4105 eqc = mb_buf; 4106 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 4107 4108 /* init eqc */ 4109 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 4110 eq->hop_num = hr_dev->caps.eqe_hop_num; 4111 eq->cons_index = 0; 4112 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 4113 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 4114 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 4115 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz; 4116 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz; 4117 eq->shift = ilog2((unsigned int)eq->entries); 4118 4119 if (!eq->hop_num) 4120 eq->eqe_ba = eq->buf_list->map; 4121 else 4122 eq->eqe_ba = eq->l0_dma; 4123 4124 /* set eqc state */ 4125 roce_set_field(eqc->byte_4, 4126 HNS_ROCE_EQC_EQ_ST_M, 4127 HNS_ROCE_EQC_EQ_ST_S, 4128 HNS_ROCE_V2_EQ_STATE_VALID); 4129 4130 /* set eqe hop num */ 4131 roce_set_field(eqc->byte_4, 4132 HNS_ROCE_EQC_HOP_NUM_M, 4133 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 4134 4135 /* set eqc over_ignore */ 4136 roce_set_field(eqc->byte_4, 4137 HNS_ROCE_EQC_OVER_IGNORE_M, 4138 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 4139 4140 /* set eqc coalesce */ 4141 roce_set_field(eqc->byte_4, 4142 HNS_ROCE_EQC_COALESCE_M, 4143 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 4144 4145 /* set eqc arm_state */ 4146 roce_set_field(eqc->byte_4, 4147 HNS_ROCE_EQC_ARM_ST_M, 4148 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 4149 4150 /* set eqn */ 4151 roce_set_field(eqc->byte_4, 4152 HNS_ROCE_EQC_EQN_M, 4153 HNS_ROCE_EQC_EQN_S, eq->eqn); 4154 4155 /* set eqe_cnt */ 4156 roce_set_field(eqc->byte_4, 4157 HNS_ROCE_EQC_EQE_CNT_M, 4158 HNS_ROCE_EQC_EQE_CNT_S, 4159 HNS_ROCE_EQ_INIT_EQE_CNT); 4160 4161 /* set eqe_ba_pg_sz */ 4162 roce_set_field(eqc->byte_8, 4163 HNS_ROCE_EQC_BA_PG_SZ_M, 4164 HNS_ROCE_EQC_BA_PG_SZ_S, eq->eqe_ba_pg_sz); 4165 4166 /* set eqe_buf_pg_sz */ 4167 roce_set_field(eqc->byte_8, 4168 HNS_ROCE_EQC_BUF_PG_SZ_M, 4169 HNS_ROCE_EQC_BUF_PG_SZ_S, eq->eqe_buf_pg_sz); 4170 4171 /* set eq_producer_idx */ 4172 roce_set_field(eqc->byte_8, 4173 HNS_ROCE_EQC_PROD_INDX_M, 4174 HNS_ROCE_EQC_PROD_INDX_S, 4175 HNS_ROCE_EQ_INIT_PROD_IDX); 4176 4177 /* set eq_max_cnt */ 4178 roce_set_field(eqc->byte_12, 4179 HNS_ROCE_EQC_MAX_CNT_M, 4180 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 4181 4182 /* set eq_period */ 4183 roce_set_field(eqc->byte_12, 4184 HNS_ROCE_EQC_PERIOD_M, 4185 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 4186 4187 /* set eqe_report_timer */ 4188 roce_set_field(eqc->eqe_report_timer, 4189 HNS_ROCE_EQC_REPORT_TIMER_M, 4190 HNS_ROCE_EQC_REPORT_TIMER_S, 4191 HNS_ROCE_EQ_INIT_REPORT_TIMER); 4192 4193 /* set eqe_ba [34:3] */ 4194 roce_set_field(eqc->eqe_ba0, 4195 HNS_ROCE_EQC_EQE_BA_L_M, 4196 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3); 4197 4198 /* set eqe_ba [64:35] */ 4199 roce_set_field(eqc->eqe_ba1, 4200 HNS_ROCE_EQC_EQE_BA_H_M, 4201 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35); 4202 4203 /* set eq shift */ 4204 roce_set_field(eqc->byte_28, 4205 HNS_ROCE_EQC_SHIFT_M, 4206 HNS_ROCE_EQC_SHIFT_S, eq->shift); 4207 4208 /* set eq MSI_IDX */ 4209 roce_set_field(eqc->byte_28, 4210 HNS_ROCE_EQC_MSI_INDX_M, 4211 HNS_ROCE_EQC_MSI_INDX_S, 4212 HNS_ROCE_EQ_INIT_MSI_IDX); 4213 4214 /* set cur_eqe_ba [27:12] */ 4215 roce_set_field(eqc->byte_28, 4216 HNS_ROCE_EQC_CUR_EQE_BA_L_M, 4217 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12); 4218 4219 /* set cur_eqe_ba [59:28] */ 4220 roce_set_field(eqc->byte_32, 4221 HNS_ROCE_EQC_CUR_EQE_BA_M_M, 4222 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28); 4223 4224 /* set cur_eqe_ba [63:60] */ 4225 roce_set_field(eqc->byte_36, 4226 HNS_ROCE_EQC_CUR_EQE_BA_H_M, 4227 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60); 4228 4229 /* set eq consumer idx */ 4230 roce_set_field(eqc->byte_36, 4231 HNS_ROCE_EQC_CONS_INDX_M, 4232 HNS_ROCE_EQC_CONS_INDX_S, 4233 HNS_ROCE_EQ_INIT_CONS_IDX); 4234 4235 /* set nex_eqe_ba[43:12] */ 4236 roce_set_field(eqc->nxt_eqe_ba0, 4237 HNS_ROCE_EQC_NXT_EQE_BA_L_M, 4238 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12); 4239 4240 /* set nex_eqe_ba[63:44] */ 4241 roce_set_field(eqc->nxt_eqe_ba1, 4242 HNS_ROCE_EQC_NXT_EQE_BA_H_M, 4243 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44); 4244 } 4245 4246 static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev, 4247 struct hns_roce_eq *eq) 4248 { 4249 struct device *dev = hr_dev->dev; 4250 int eq_alloc_done = 0; 4251 int eq_buf_cnt = 0; 4252 int eqe_alloc; 4253 u32 buf_chk_sz; 4254 u32 bt_chk_sz; 4255 u32 mhop_num; 4256 u64 size; 4257 u64 idx; 4258 int ba_num; 4259 int bt_num; 4260 int record_i; 4261 int record_j; 4262 int i = 0; 4263 int j = 0; 4264 4265 mhop_num = hr_dev->caps.eqe_hop_num; 4266 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4267 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4268 4269 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) 4270 / buf_chk_sz; 4271 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8); 4272 4273 /* hop_num = 0 */ 4274 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4275 if (eq->entries > buf_chk_sz / eq->eqe_size) { 4276 dev_err(dev, "eq entries %d is larger than buf_pg_sz!", 4277 eq->entries); 4278 return -EINVAL; 4279 } 4280 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size, 4281 &(eq->l0_dma), GFP_KERNEL); 4282 if (!eq->bt_l0) 4283 return -ENOMEM; 4284 4285 eq->cur_eqe_ba = eq->l0_dma; 4286 eq->nxt_eqe_ba = 0; 4287 4288 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size); 4289 4290 return 0; 4291 } 4292 4293 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL); 4294 if (!eq->buf_dma) 4295 return -ENOMEM; 4296 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL); 4297 if (!eq->buf) 4298 goto err_kcalloc_buf; 4299 4300 if (mhop_num == 2) { 4301 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL); 4302 if (!eq->l1_dma) 4303 goto err_kcalloc_l1_dma; 4304 4305 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL); 4306 if (!eq->bt_l1) 4307 goto err_kcalloc_bt_l1; 4308 } 4309 4310 /* alloc L0 BT */ 4311 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL); 4312 if (!eq->bt_l0) 4313 goto err_dma_alloc_l0; 4314 4315 if (mhop_num == 1) { 4316 if (ba_num > (bt_chk_sz / 8)) 4317 dev_err(dev, "ba_num %d is too large for 1 hop\n", 4318 ba_num); 4319 4320 /* alloc buf */ 4321 for (i = 0; i < bt_chk_sz / 8; i++) { 4322 if (eq_buf_cnt + 1 < ba_num) { 4323 size = buf_chk_sz; 4324 } else { 4325 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4326 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4327 } 4328 eq->buf[i] = dma_alloc_coherent(dev, size, 4329 &(eq->buf_dma[i]), 4330 GFP_KERNEL); 4331 if (!eq->buf[i]) 4332 goto err_dma_alloc_buf; 4333 4334 memset(eq->buf[i], 0, size); 4335 *(eq->bt_l0 + i) = eq->buf_dma[i]; 4336 4337 eq_buf_cnt++; 4338 if (eq_buf_cnt >= ba_num) 4339 break; 4340 } 4341 eq->cur_eqe_ba = eq->buf_dma[0]; 4342 eq->nxt_eqe_ba = eq->buf_dma[1]; 4343 4344 } else if (mhop_num == 2) { 4345 /* alloc L1 BT and buf */ 4346 for (i = 0; i < bt_chk_sz / 8; i++) { 4347 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz, 4348 &(eq->l1_dma[i]), 4349 GFP_KERNEL); 4350 if (!eq->bt_l1[i]) 4351 goto err_dma_alloc_l1; 4352 *(eq->bt_l0 + i) = eq->l1_dma[i]; 4353 4354 for (j = 0; j < bt_chk_sz / 8; j++) { 4355 idx = i * bt_chk_sz / 8 + j; 4356 if (eq_buf_cnt + 1 < ba_num) { 4357 size = buf_chk_sz; 4358 } else { 4359 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4360 * idx; 4361 size = (eq->entries - eqe_alloc) 4362 * eq->eqe_size; 4363 } 4364 eq->buf[idx] = dma_alloc_coherent(dev, size, 4365 &(eq->buf_dma[idx]), 4366 GFP_KERNEL); 4367 if (!eq->buf[idx]) 4368 goto err_dma_alloc_buf; 4369 4370 memset(eq->buf[idx], 0, size); 4371 *(eq->bt_l1[i] + j) = eq->buf_dma[idx]; 4372 4373 eq_buf_cnt++; 4374 if (eq_buf_cnt >= ba_num) { 4375 eq_alloc_done = 1; 4376 break; 4377 } 4378 } 4379 4380 if (eq_alloc_done) 4381 break; 4382 } 4383 eq->cur_eqe_ba = eq->buf_dma[0]; 4384 eq->nxt_eqe_ba = eq->buf_dma[1]; 4385 } 4386 4387 eq->l0_last_num = i + 1; 4388 if (mhop_num == 2) 4389 eq->l1_last_num = j + 1; 4390 4391 return 0; 4392 4393 err_dma_alloc_l1: 4394 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4395 eq->bt_l0 = NULL; 4396 eq->l0_dma = 0; 4397 for (i -= 1; i >= 0; i--) { 4398 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4399 eq->l1_dma[i]); 4400 4401 for (j = 0; j < bt_chk_sz / 8; j++) { 4402 idx = i * bt_chk_sz / 8 + j; 4403 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4404 eq->buf_dma[idx]); 4405 } 4406 } 4407 goto err_dma_alloc_l0; 4408 4409 err_dma_alloc_buf: 4410 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4411 eq->bt_l0 = NULL; 4412 eq->l0_dma = 0; 4413 4414 if (mhop_num == 1) 4415 for (i -= 1; i >= 0; i--) 4416 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4417 eq->buf_dma[i]); 4418 else if (mhop_num == 2) { 4419 record_i = i; 4420 record_j = j; 4421 for (; i >= 0; i--) { 4422 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4423 eq->l1_dma[i]); 4424 4425 for (j = 0; j < bt_chk_sz / 8; j++) { 4426 if (i == record_i && j >= record_j) 4427 break; 4428 4429 idx = i * bt_chk_sz / 8 + j; 4430 dma_free_coherent(dev, buf_chk_sz, 4431 eq->buf[idx], 4432 eq->buf_dma[idx]); 4433 } 4434 } 4435 } 4436 4437 err_dma_alloc_l0: 4438 kfree(eq->bt_l1); 4439 eq->bt_l1 = NULL; 4440 4441 err_kcalloc_bt_l1: 4442 kfree(eq->l1_dma); 4443 eq->l1_dma = NULL; 4444 4445 err_kcalloc_l1_dma: 4446 kfree(eq->buf); 4447 eq->buf = NULL; 4448 4449 err_kcalloc_buf: 4450 kfree(eq->buf_dma); 4451 eq->buf_dma = NULL; 4452 4453 return -ENOMEM; 4454 } 4455 4456 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 4457 struct hns_roce_eq *eq, 4458 unsigned int eq_cmd) 4459 { 4460 struct device *dev = hr_dev->dev; 4461 struct hns_roce_cmd_mailbox *mailbox; 4462 u32 buf_chk_sz = 0; 4463 int ret; 4464 4465 /* Allocate mailbox memory */ 4466 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4467 if (IS_ERR(mailbox)) 4468 return PTR_ERR(mailbox); 4469 4470 if (!hr_dev->caps.eqe_hop_num) { 4471 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4472 4473 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list), 4474 GFP_KERNEL); 4475 if (!eq->buf_list) { 4476 ret = -ENOMEM; 4477 goto free_cmd_mbox; 4478 } 4479 4480 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz, 4481 &(eq->buf_list->map), 4482 GFP_KERNEL); 4483 if (!eq->buf_list->buf) { 4484 ret = -ENOMEM; 4485 goto err_alloc_buf; 4486 } 4487 4488 memset(eq->buf_list->buf, 0, buf_chk_sz); 4489 } else { 4490 ret = hns_roce_mhop_alloc_eq(hr_dev, eq); 4491 if (ret) { 4492 ret = -ENOMEM; 4493 goto free_cmd_mbox; 4494 } 4495 } 4496 4497 hns_roce_config_eqc(hr_dev, eq, mailbox->buf); 4498 4499 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 4500 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 4501 if (ret) { 4502 dev_err(dev, "[mailbox cmd] create eqc failed.\n"); 4503 goto err_cmd_mbox; 4504 } 4505 4506 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4507 4508 return 0; 4509 4510 err_cmd_mbox: 4511 if (!hr_dev->caps.eqe_hop_num) 4512 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf, 4513 eq->buf_list->map); 4514 else { 4515 hns_roce_mhop_free_eq(hr_dev, eq); 4516 goto free_cmd_mbox; 4517 } 4518 4519 err_alloc_buf: 4520 kfree(eq->buf_list); 4521 4522 free_cmd_mbox: 4523 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4524 4525 return ret; 4526 } 4527 4528 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 4529 { 4530 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4531 struct device *dev = hr_dev->dev; 4532 struct hns_roce_eq *eq; 4533 unsigned int eq_cmd; 4534 int irq_num; 4535 int eq_num; 4536 int other_num; 4537 int comp_num; 4538 int aeq_num; 4539 int i, j, k; 4540 int ret; 4541 4542 other_num = hr_dev->caps.num_other_vectors; 4543 comp_num = hr_dev->caps.num_comp_vectors; 4544 aeq_num = hr_dev->caps.num_aeq_vectors; 4545 4546 eq_num = comp_num + aeq_num; 4547 irq_num = eq_num + other_num; 4548 4549 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 4550 if (!eq_table->eq) 4551 return -ENOMEM; 4552 4553 for (i = 0; i < irq_num; i++) { 4554 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 4555 GFP_KERNEL); 4556 if (!hr_dev->irq_names[i]) { 4557 ret = -ENOMEM; 4558 goto err_failed_kzalloc; 4559 } 4560 } 4561 4562 /* create eq */ 4563 for (j = 0; j < eq_num; j++) { 4564 eq = &eq_table->eq[j]; 4565 eq->hr_dev = hr_dev; 4566 eq->eqn = j; 4567 if (j < comp_num) { 4568 /* CEQ */ 4569 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 4570 eq->type_flag = HNS_ROCE_CEQ; 4571 eq->entries = hr_dev->caps.ceqe_depth; 4572 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 4573 eq->irq = hr_dev->irq[j + other_num + aeq_num]; 4574 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 4575 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 4576 } else { 4577 /* AEQ */ 4578 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 4579 eq->type_flag = HNS_ROCE_AEQ; 4580 eq->entries = hr_dev->caps.aeqe_depth; 4581 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 4582 eq->irq = hr_dev->irq[j - comp_num + other_num]; 4583 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 4584 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 4585 } 4586 4587 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 4588 if (ret) { 4589 dev_err(dev, "eq create failed.\n"); 4590 goto err_create_eq_fail; 4591 } 4592 } 4593 4594 /* enable irq */ 4595 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 4596 4597 /* irq contains: abnormal + AEQ + CEQ*/ 4598 for (k = 0; k < irq_num; k++) 4599 if (k < other_num) 4600 snprintf((char *)hr_dev->irq_names[k], 4601 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k); 4602 else if (k < (other_num + aeq_num)) 4603 snprintf((char *)hr_dev->irq_names[k], 4604 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d", 4605 k - other_num); 4606 else 4607 snprintf((char *)hr_dev->irq_names[k], 4608 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d", 4609 k - other_num - aeq_num); 4610 4611 for (k = 0; k < irq_num; k++) { 4612 if (k < other_num) 4613 ret = request_irq(hr_dev->irq[k], 4614 hns_roce_v2_msix_interrupt_abn, 4615 0, hr_dev->irq_names[k], hr_dev); 4616 4617 else if (k < (other_num + comp_num)) 4618 ret = request_irq(eq_table->eq[k - other_num].irq, 4619 hns_roce_v2_msix_interrupt_eq, 4620 0, hr_dev->irq_names[k + aeq_num], 4621 &eq_table->eq[k - other_num]); 4622 else 4623 ret = request_irq(eq_table->eq[k - other_num].irq, 4624 hns_roce_v2_msix_interrupt_eq, 4625 0, hr_dev->irq_names[k - comp_num], 4626 &eq_table->eq[k - other_num]); 4627 if (ret) { 4628 dev_err(dev, "Request irq error!\n"); 4629 goto err_request_irq_fail; 4630 } 4631 } 4632 4633 return 0; 4634 4635 err_request_irq_fail: 4636 for (k -= 1; k >= 0; k--) 4637 if (k < other_num) 4638 free_irq(hr_dev->irq[k], hr_dev); 4639 else 4640 free_irq(eq_table->eq[k - other_num].irq, 4641 &eq_table->eq[k - other_num]); 4642 4643 err_create_eq_fail: 4644 for (j -= 1; j >= 0; j--) 4645 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]); 4646 4647 err_failed_kzalloc: 4648 for (i -= 1; i >= 0; i--) 4649 kfree(hr_dev->irq_names[i]); 4650 kfree(eq_table->eq); 4651 4652 return ret; 4653 } 4654 4655 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 4656 { 4657 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4658 int irq_num; 4659 int eq_num; 4660 int i; 4661 4662 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 4663 irq_num = eq_num + hr_dev->caps.num_other_vectors; 4664 4665 /* Disable irq */ 4666 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 4667 4668 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 4669 free_irq(hr_dev->irq[i], hr_dev); 4670 4671 for (i = 0; i < eq_num; i++) { 4672 hns_roce_v2_destroy_eqc(hr_dev, i); 4673 4674 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]); 4675 4676 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]); 4677 } 4678 4679 for (i = 0; i < irq_num; i++) 4680 kfree(hr_dev->irq_names[i]); 4681 4682 kfree(eq_table->eq); 4683 } 4684 4685 static const struct hns_roce_hw hns_roce_hw_v2 = { 4686 .cmq_init = hns_roce_v2_cmq_init, 4687 .cmq_exit = hns_roce_v2_cmq_exit, 4688 .hw_profile = hns_roce_v2_profile, 4689 .post_mbox = hns_roce_v2_post_mbox, 4690 .chk_mbox = hns_roce_v2_chk_mbox, 4691 .set_gid = hns_roce_v2_set_gid, 4692 .set_mac = hns_roce_v2_set_mac, 4693 .write_mtpt = hns_roce_v2_write_mtpt, 4694 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 4695 .write_cqc = hns_roce_v2_write_cqc, 4696 .set_hem = hns_roce_v2_set_hem, 4697 .clear_hem = hns_roce_v2_clear_hem, 4698 .modify_qp = hns_roce_v2_modify_qp, 4699 .query_qp = hns_roce_v2_query_qp, 4700 .destroy_qp = hns_roce_v2_destroy_qp, 4701 .modify_cq = hns_roce_v2_modify_cq, 4702 .post_send = hns_roce_v2_post_send, 4703 .post_recv = hns_roce_v2_post_recv, 4704 .req_notify_cq = hns_roce_v2_req_notify_cq, 4705 .poll_cq = hns_roce_v2_poll_cq, 4706 .init_eq = hns_roce_v2_init_eq_table, 4707 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 4708 }; 4709 4710 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 4711 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 4712 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 4713 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 4714 /* required last entry */ 4715 {0, } 4716 }; 4717 4718 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 4719 4720 static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 4721 struct hnae3_handle *handle) 4722 { 4723 const struct pci_device_id *id; 4724 int i; 4725 4726 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 4727 if (!id) { 4728 dev_err(hr_dev->dev, "device is not compatible!\n"); 4729 return -ENXIO; 4730 } 4731 4732 hr_dev->hw = &hns_roce_hw_v2; 4733 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 4734 hr_dev->odb_offset = hr_dev->sdb_offset; 4735 4736 /* Get info from NIC driver. */ 4737 hr_dev->reg_base = handle->rinfo.roce_io_base; 4738 hr_dev->caps.num_ports = 1; 4739 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 4740 hr_dev->iboe.phy_port[0] = 0; 4741 4742 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 4743 hr_dev->iboe.netdevs[0]->dev_addr); 4744 4745 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 4746 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 4747 i + handle->rinfo.base_vector); 4748 4749 /* cmd issue mode: 0 is poll, 1 is event */ 4750 hr_dev->cmd_mod = 1; 4751 hr_dev->loop_idc = 0; 4752 4753 return 0; 4754 } 4755 4756 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 4757 { 4758 struct hns_roce_dev *hr_dev; 4759 int ret; 4760 4761 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev)); 4762 if (!hr_dev) 4763 return -ENOMEM; 4764 4765 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 4766 if (!hr_dev->priv) { 4767 ret = -ENOMEM; 4768 goto error_failed_kzalloc; 4769 } 4770 4771 hr_dev->pci_dev = handle->pdev; 4772 hr_dev->dev = &handle->pdev->dev; 4773 handle->priv = hr_dev; 4774 4775 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle); 4776 if (ret) { 4777 dev_err(hr_dev->dev, "Get Configuration failed!\n"); 4778 goto error_failed_get_cfg; 4779 } 4780 4781 ret = hns_roce_init(hr_dev); 4782 if (ret) { 4783 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 4784 goto error_failed_get_cfg; 4785 } 4786 4787 return 0; 4788 4789 error_failed_get_cfg: 4790 kfree(hr_dev->priv); 4791 4792 error_failed_kzalloc: 4793 ib_dealloc_device(&hr_dev->ib_dev); 4794 4795 return ret; 4796 } 4797 4798 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 4799 bool reset) 4800 { 4801 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 4802 4803 hns_roce_exit(hr_dev); 4804 kfree(hr_dev->priv); 4805 ib_dealloc_device(&hr_dev->ib_dev); 4806 } 4807 4808 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 4809 .init_instance = hns_roce_hw_v2_init_instance, 4810 .uninit_instance = hns_roce_hw_v2_uninit_instance, 4811 }; 4812 4813 static struct hnae3_client hns_roce_hw_v2_client = { 4814 .name = "hns_roce_hw_v2", 4815 .type = HNAE3_CLIENT_ROCE, 4816 .ops = &hns_roce_hw_v2_ops, 4817 }; 4818 4819 static int __init hns_roce_hw_v2_init(void) 4820 { 4821 return hnae3_register_client(&hns_roce_hw_v2_client); 4822 } 4823 4824 static void __exit hns_roce_hw_v2_exit(void) 4825 { 4826 hnae3_unregister_client(&hns_roce_hw_v2_client); 4827 } 4828 4829 module_init(hns_roce_hw_v2_init); 4830 module_exit(hns_roce_hw_v2_exit); 4831 4832 MODULE_LICENSE("Dual BSD/GPL"); 4833 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 4834 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 4835 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 4836 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 4837