1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 59 struct ib_sge *sg) 60 { 61 dseg->lkey = cpu_to_le32(sg->lkey); 62 dseg->addr = cpu_to_le64(sg->addr); 63 dseg->len = cpu_to_le32(sg->length); 64 } 65 66 /* 67 * mapped-value = 1 + real-value 68 * The hns wr opcode real value is start from 0, In order to distinguish between 69 * initialized and uninitialized map values, we plus 1 to the actual value when 70 * defining the mapping, so that the validity can be identified by checking the 71 * mapped value is greater than 0. 72 */ 73 #define HR_OPC_MAP(ib_key, hr_key) \ 74 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 75 76 static const u32 hns_roce_op_code[] = { 77 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 78 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 79 HR_OPC_MAP(SEND, SEND), 80 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 81 HR_OPC_MAP(RDMA_READ, RDMA_READ), 82 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 83 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 84 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 85 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 86 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 87 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 88 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 89 }; 90 91 static u32 to_hr_opcode(u32 ib_opcode) 92 { 93 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 94 return HNS_ROCE_V2_WQE_OP_MASK; 95 96 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 97 HNS_ROCE_V2_WQE_OP_MASK; 98 } 99 100 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 101 const struct ib_reg_wr *wr) 102 { 103 struct hns_roce_wqe_frmr_seg *fseg = 104 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 105 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 106 u64 pbl_ba; 107 108 /* use ib_access_flags */ 109 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 110 hr_reg_write_bool(fseg, FRMR_ATOMIC, 111 wr->access & IB_ACCESS_REMOTE_ATOMIC); 112 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 113 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 114 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 115 116 /* Data structure reuse may lead to confusion */ 117 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 118 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 119 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 120 121 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 122 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 123 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 124 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 125 126 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 127 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 128 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 129 hr_reg_clear(fseg, FRMR_BLK_MODE); 130 } 131 132 static void set_atomic_seg(const struct ib_send_wr *wr, 133 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 134 unsigned int valid_num_sge) 135 { 136 struct hns_roce_v2_wqe_data_seg *dseg = 137 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 138 struct hns_roce_wqe_atomic_seg *aseg = 139 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 140 141 set_data_seg_v2(dseg, wr->sg_list); 142 143 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 144 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 145 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 146 } else { 147 aseg->fetchadd_swap_data = 148 cpu_to_le64(atomic_wr(wr)->compare_add); 149 aseg->cmp_data = 0; 150 } 151 152 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 153 } 154 155 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 156 const struct ib_send_wr *wr, 157 unsigned int *sge_idx, u32 msg_len) 158 { 159 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 160 unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg); 161 unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len; 162 unsigned int left_len_in_pg; 163 unsigned int idx = *sge_idx; 164 unsigned int i = 0; 165 unsigned int len; 166 void *addr; 167 void *dseg; 168 169 if (msg_len > ext_sge_sz) { 170 ibdev_err(ibdev, 171 "no enough extended sge space for inline data.\n"); 172 return -EINVAL; 173 } 174 175 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 176 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 177 len = wr->sg_list[0].length; 178 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 179 180 /* When copying data to extended sge space, the left length in page may 181 * not long enough for current user's sge. So the data should be 182 * splited into several parts, one in the first page, and the others in 183 * the subsequent pages. 184 */ 185 while (1) { 186 if (len <= left_len_in_pg) { 187 memcpy(dseg, addr, len); 188 189 idx += len / dseg_len; 190 191 i++; 192 if (i >= wr->num_sge) 193 break; 194 195 left_len_in_pg -= len; 196 len = wr->sg_list[i].length; 197 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 198 dseg += len; 199 } else { 200 memcpy(dseg, addr, left_len_in_pg); 201 202 len -= left_len_in_pg; 203 addr += left_len_in_pg; 204 idx += left_len_in_pg / dseg_len; 205 dseg = hns_roce_get_extend_sge(qp, 206 idx & (qp->sge.sge_cnt - 1)); 207 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 208 } 209 } 210 211 *sge_idx = idx; 212 213 return 0; 214 } 215 216 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 217 unsigned int *sge_ind, unsigned int cnt) 218 { 219 struct hns_roce_v2_wqe_data_seg *dseg; 220 unsigned int idx = *sge_ind; 221 222 while (cnt > 0) { 223 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 224 if (likely(sge->length)) { 225 set_data_seg_v2(dseg, sge); 226 idx++; 227 cnt--; 228 } 229 sge++; 230 } 231 232 *sge_ind = idx; 233 } 234 235 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 236 { 237 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 238 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 239 240 if (len > qp->max_inline_data || len > mtu) { 241 ibdev_err(&hr_dev->ib_dev, 242 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 243 len, qp->max_inline_data, mtu); 244 return false; 245 } 246 247 return true; 248 } 249 250 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 251 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 252 unsigned int *sge_idx) 253 { 254 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 255 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 256 struct ib_device *ibdev = &hr_dev->ib_dev; 257 unsigned int curr_idx = *sge_idx; 258 void *dseg = rc_sq_wqe; 259 unsigned int i; 260 int ret; 261 262 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 263 ibdev_err(ibdev, "invalid inline parameters!\n"); 264 return -EINVAL; 265 } 266 267 if (!check_inl_data_len(qp, msg_len)) 268 return -EINVAL; 269 270 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 271 272 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 273 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 274 275 for (i = 0; i < wr->num_sge; i++) { 276 memcpy(dseg, ((void *)wr->sg_list[i].addr), 277 wr->sg_list[i].length); 278 dseg += wr->sg_list[i].length; 279 } 280 } else { 281 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 282 283 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 284 if (ret) 285 return ret; 286 287 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 288 } 289 290 *sge_idx = curr_idx; 291 292 return 0; 293 } 294 295 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 296 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 297 unsigned int *sge_ind, 298 unsigned int valid_num_sge) 299 { 300 struct hns_roce_v2_wqe_data_seg *dseg = 301 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 302 struct hns_roce_qp *qp = to_hr_qp(ibqp); 303 int j = 0; 304 int i; 305 306 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 307 (*sge_ind) & (qp->sge.sge_cnt - 1)); 308 309 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 310 !!(wr->send_flags & IB_SEND_INLINE)); 311 if (wr->send_flags & IB_SEND_INLINE) 312 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 313 314 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 315 for (i = 0; i < wr->num_sge; i++) { 316 if (likely(wr->sg_list[i].length)) { 317 set_data_seg_v2(dseg, wr->sg_list + i); 318 dseg++; 319 } 320 } 321 } else { 322 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 323 if (likely(wr->sg_list[i].length)) { 324 set_data_seg_v2(dseg, wr->sg_list + i); 325 dseg++; 326 j++; 327 } 328 } 329 330 set_extend_sge(qp, wr->sg_list + i, sge_ind, 331 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 332 } 333 334 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 335 336 return 0; 337 } 338 339 static int check_send_valid(struct hns_roce_dev *hr_dev, 340 struct hns_roce_qp *hr_qp) 341 { 342 struct ib_device *ibdev = &hr_dev->ib_dev; 343 struct ib_qp *ibqp = &hr_qp->ibqp; 344 345 if (unlikely(ibqp->qp_type != IB_QPT_RC && 346 ibqp->qp_type != IB_QPT_GSI && 347 ibqp->qp_type != IB_QPT_UD)) { 348 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 349 ibqp->qp_type); 350 return -EOPNOTSUPP; 351 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 352 hr_qp->state == IB_QPS_INIT || 353 hr_qp->state == IB_QPS_RTR)) { 354 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 355 hr_qp->state); 356 return -EINVAL; 357 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 358 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 359 hr_dev->state); 360 return -EIO; 361 } 362 363 return 0; 364 } 365 366 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 367 unsigned int *sge_len) 368 { 369 unsigned int valid_num = 0; 370 unsigned int len = 0; 371 int i; 372 373 for (i = 0; i < wr->num_sge; i++) { 374 if (likely(wr->sg_list[i].length)) { 375 len += wr->sg_list[i].length; 376 valid_num++; 377 } 378 } 379 380 *sge_len = len; 381 return valid_num; 382 } 383 384 static __le32 get_immtdata(const struct ib_send_wr *wr) 385 { 386 switch (wr->opcode) { 387 case IB_WR_SEND_WITH_IMM: 388 case IB_WR_RDMA_WRITE_WITH_IMM: 389 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 390 default: 391 return 0; 392 } 393 } 394 395 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 396 const struct ib_send_wr *wr) 397 { 398 u32 ib_op = wr->opcode; 399 400 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 401 return -EINVAL; 402 403 ud_sq_wqe->immtdata = get_immtdata(wr); 404 405 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 406 407 return 0; 408 } 409 410 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 411 struct hns_roce_ah *ah) 412 { 413 struct ib_device *ib_dev = ah->ibah.device; 414 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 415 416 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 417 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 418 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 419 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 420 421 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 422 return -EINVAL; 423 424 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 425 426 ud_sq_wqe->sgid_index = ah->av.gid_index; 427 428 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 429 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 430 431 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 432 return 0; 433 434 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 435 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 436 437 return 0; 438 } 439 440 static inline int set_ud_wqe(struct hns_roce_qp *qp, 441 const struct ib_send_wr *wr, 442 void *wqe, unsigned int *sge_idx, 443 unsigned int owner_bit) 444 { 445 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 446 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 447 unsigned int curr_idx = *sge_idx; 448 unsigned int valid_num_sge; 449 u32 msg_len = 0; 450 int ret; 451 452 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 453 454 ret = set_ud_opcode(ud_sq_wqe, wr); 455 if (WARN_ON(ret)) 456 return ret; 457 458 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 459 460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 461 !!(wr->send_flags & IB_SEND_SIGNALED)); 462 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 463 !!(wr->send_flags & IB_SEND_SOLICITED)); 464 465 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 466 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 467 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 468 curr_idx & (qp->sge.sge_cnt - 1)); 469 470 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 471 qp->qkey : ud_wr(wr)->remote_qkey); 472 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 473 474 ret = fill_ud_av(ud_sq_wqe, ah); 475 if (ret) 476 return ret; 477 478 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 479 480 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 481 482 /* 483 * The pipeline can sequentially post all valid WQEs into WQ buffer, 484 * including new WQEs waiting for the doorbell to update the PI again. 485 * Therefore, the owner bit of WQE MUST be updated after all fields 486 * and extSGEs have been written into DDR instead of cache. 487 */ 488 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 489 dma_wmb(); 490 491 *sge_idx = curr_idx; 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 493 494 return 0; 495 } 496 497 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 498 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 499 const struct ib_send_wr *wr) 500 { 501 u32 ib_op = wr->opcode; 502 int ret = 0; 503 504 rc_sq_wqe->immtdata = get_immtdata(wr); 505 506 switch (ib_op) { 507 case IB_WR_RDMA_READ: 508 case IB_WR_RDMA_WRITE: 509 case IB_WR_RDMA_WRITE_WITH_IMM: 510 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 511 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 512 break; 513 case IB_WR_SEND: 514 case IB_WR_SEND_WITH_IMM: 515 break; 516 case IB_WR_ATOMIC_CMP_AND_SWP: 517 case IB_WR_ATOMIC_FETCH_AND_ADD: 518 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 519 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 520 break; 521 case IB_WR_REG_MR: 522 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 523 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 524 else 525 ret = -EOPNOTSUPP; 526 break; 527 case IB_WR_LOCAL_INV: 528 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_SO); 529 fallthrough; 530 case IB_WR_SEND_WITH_INV: 531 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 532 break; 533 default: 534 ret = -EINVAL; 535 } 536 537 if (unlikely(ret)) 538 return ret; 539 540 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 541 542 return ret; 543 } 544 545 static inline int set_rc_wqe(struct hns_roce_qp *qp, 546 const struct ib_send_wr *wr, 547 void *wqe, unsigned int *sge_idx, 548 unsigned int owner_bit) 549 { 550 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 551 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 552 unsigned int curr_idx = *sge_idx; 553 unsigned int valid_num_sge; 554 u32 msg_len = 0; 555 int ret; 556 557 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 558 559 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 560 561 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 562 if (WARN_ON(ret)) 563 return ret; 564 565 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 566 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 567 568 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 569 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 570 571 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 572 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 573 574 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 575 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 576 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 577 else if (wr->opcode != IB_WR_REG_MR) 578 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 579 &curr_idx, valid_num_sge); 580 581 /* 582 * The pipeline can sequentially post all valid WQEs into WQ buffer, 583 * including new WQEs waiting for the doorbell to update the PI again. 584 * Therefore, the owner bit of WQE MUST be updated after all fields 585 * and extSGEs have been written into DDR instead of cache. 586 */ 587 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 588 dma_wmb(); 589 590 *sge_idx = curr_idx; 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 592 593 return ret; 594 } 595 596 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 597 struct hns_roce_qp *qp) 598 { 599 if (unlikely(qp->state == IB_QPS_ERR)) { 600 flush_cqe(hr_dev, qp); 601 } else { 602 struct hns_roce_v2_db sq_db = {}; 603 604 hr_reg_write(&sq_db, DB_TAG, qp->doorbell_qpn); 605 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 606 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 607 hr_reg_write(&sq_db, DB_SL, qp->sl); 608 609 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 610 } 611 } 612 613 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 614 struct hns_roce_qp *qp) 615 { 616 if (unlikely(qp->state == IB_QPS_ERR)) { 617 flush_cqe(hr_dev, qp); 618 } else { 619 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 620 *qp->rdb.db_record = 621 qp->rq.head & V2_DB_PRODUCER_IDX_M; 622 } else { 623 struct hns_roce_v2_db rq_db = {}; 624 625 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 626 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 627 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 628 629 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 630 qp->rq.db_reg); 631 } 632 } 633 } 634 635 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 636 u64 __iomem *dest) 637 { 638 #define HNS_ROCE_WRITE_TIMES 8 639 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 640 struct hnae3_handle *handle = priv->handle; 641 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 642 int i; 643 644 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 645 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 646 writeq_relaxed(*(val + i), dest + i); 647 } 648 649 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 650 void *wqe) 651 { 652 #define HNS_ROCE_SL_SHIFT 2 653 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 654 655 /* All kinds of DirectWQE have the same header field layout */ 656 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 657 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 658 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 659 qp->sl >> HNS_ROCE_SL_SHIFT); 660 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 661 662 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 663 } 664 665 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 666 const struct ib_send_wr *wr, 667 const struct ib_send_wr **bad_wr) 668 { 669 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 670 struct ib_device *ibdev = &hr_dev->ib_dev; 671 struct hns_roce_qp *qp = to_hr_qp(ibqp); 672 unsigned long flags = 0; 673 unsigned int owner_bit; 674 unsigned int sge_idx; 675 unsigned int wqe_idx; 676 void *wqe = NULL; 677 u32 nreq; 678 int ret; 679 680 spin_lock_irqsave(&qp->sq.lock, flags); 681 682 ret = check_send_valid(hr_dev, qp); 683 if (unlikely(ret)) { 684 *bad_wr = wr; 685 nreq = 0; 686 goto out; 687 } 688 689 sge_idx = qp->next_sge; 690 691 for (nreq = 0; wr; ++nreq, wr = wr->next) { 692 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 693 ret = -ENOMEM; 694 *bad_wr = wr; 695 goto out; 696 } 697 698 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 699 700 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 701 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 702 wr->num_sge, qp->sq.max_gs); 703 ret = -EINVAL; 704 *bad_wr = wr; 705 goto out; 706 } 707 708 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 709 qp->sq.wrid[wqe_idx] = wr->wr_id; 710 owner_bit = 711 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 712 713 /* Corresponding to the QP type, wqe process separately */ 714 if (ibqp->qp_type == IB_QPT_RC) 715 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 716 else 717 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 718 719 if (unlikely(ret)) { 720 *bad_wr = wr; 721 goto out; 722 } 723 } 724 725 out: 726 if (likely(nreq)) { 727 qp->sq.head += nreq; 728 qp->next_sge = sge_idx; 729 730 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 731 write_dwqe(hr_dev, qp, wqe); 732 else 733 update_sq_db(hr_dev, qp); 734 } 735 736 spin_unlock_irqrestore(&qp->sq.lock, flags); 737 738 return ret; 739 } 740 741 static int check_recv_valid(struct hns_roce_dev *hr_dev, 742 struct hns_roce_qp *hr_qp) 743 { 744 struct ib_device *ibdev = &hr_dev->ib_dev; 745 struct ib_qp *ibqp = &hr_qp->ibqp; 746 747 if (unlikely(ibqp->qp_type != IB_QPT_RC && 748 ibqp->qp_type != IB_QPT_GSI && 749 ibqp->qp_type != IB_QPT_UD)) { 750 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 751 ibqp->qp_type); 752 return -EOPNOTSUPP; 753 } 754 755 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 756 return -EIO; 757 758 if (hr_qp->state == IB_QPS_RESET) 759 return -EINVAL; 760 761 return 0; 762 } 763 764 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 765 u32 max_sge, bool rsv) 766 { 767 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 768 u32 i, cnt; 769 770 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 771 /* Skip zero-length sge */ 772 if (!wr->sg_list[i].length) 773 continue; 774 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 775 cnt++; 776 } 777 778 /* Fill a reserved sge to make hw stop reading remaining segments */ 779 if (rsv) { 780 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 781 dseg[cnt].addr = 0; 782 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 783 } else { 784 /* Clear remaining segments to make ROCEE ignore sges */ 785 if (cnt < max_sge) 786 memset(dseg + cnt, 0, 787 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 788 } 789 } 790 791 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 792 u32 wqe_idx, u32 max_sge) 793 { 794 struct hns_roce_rinl_sge *sge_list; 795 void *wqe = NULL; 796 u32 i; 797 798 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 799 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 800 801 /* rq support inline data */ 802 if (hr_qp->rq_inl_buf.wqe_cnt) { 803 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 804 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 805 for (i = 0; i < wr->num_sge; i++) { 806 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 807 sge_list[i].len = wr->sg_list[i].length; 808 } 809 } 810 } 811 812 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 813 const struct ib_recv_wr *wr, 814 const struct ib_recv_wr **bad_wr) 815 { 816 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 817 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 818 struct ib_device *ibdev = &hr_dev->ib_dev; 819 u32 wqe_idx, nreq, max_sge; 820 unsigned long flags; 821 int ret; 822 823 spin_lock_irqsave(&hr_qp->rq.lock, flags); 824 825 ret = check_recv_valid(hr_dev, hr_qp); 826 if (unlikely(ret)) { 827 *bad_wr = wr; 828 nreq = 0; 829 goto out; 830 } 831 832 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 833 for (nreq = 0; wr; ++nreq, wr = wr->next) { 834 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 835 hr_qp->ibqp.recv_cq))) { 836 ret = -ENOMEM; 837 *bad_wr = wr; 838 goto out; 839 } 840 841 if (unlikely(wr->num_sge > max_sge)) { 842 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 843 wr->num_sge, max_sge); 844 ret = -EINVAL; 845 *bad_wr = wr; 846 goto out; 847 } 848 849 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 850 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 851 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 852 } 853 854 out: 855 if (likely(nreq)) { 856 hr_qp->rq.head += nreq; 857 858 update_rq_db(hr_dev, hr_qp); 859 } 860 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 861 862 return ret; 863 } 864 865 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 866 { 867 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 868 } 869 870 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 871 { 872 return hns_roce_buf_offset(idx_que->mtr.kmem, 873 n << idx_que->entry_shift); 874 } 875 876 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 877 { 878 /* always called with interrupts disabled. */ 879 spin_lock(&srq->lock); 880 881 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 882 srq->idx_que.tail++; 883 884 spin_unlock(&srq->lock); 885 } 886 887 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 888 { 889 struct hns_roce_idx_que *idx_que = &srq->idx_que; 890 891 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 892 } 893 894 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 895 const struct ib_recv_wr *wr) 896 { 897 struct ib_device *ib_dev = srq->ibsrq.device; 898 899 if (unlikely(wr->num_sge > max_sge)) { 900 ibdev_err(ib_dev, 901 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 902 wr->num_sge, max_sge); 903 return -EINVAL; 904 } 905 906 if (unlikely(hns_roce_srqwq_overflow(srq))) { 907 ibdev_err(ib_dev, 908 "failed to check srqwq status, srqwq is full.\n"); 909 return -ENOMEM; 910 } 911 912 return 0; 913 } 914 915 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 916 { 917 struct hns_roce_idx_que *idx_que = &srq->idx_que; 918 u32 pos; 919 920 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 921 if (unlikely(pos == srq->wqe_cnt)) 922 return -ENOSPC; 923 924 bitmap_set(idx_que->bitmap, pos, 1); 925 *wqe_idx = pos; 926 return 0; 927 } 928 929 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 930 { 931 struct hns_roce_idx_que *idx_que = &srq->idx_que; 932 unsigned int head; 933 __le32 *buf; 934 935 head = idx_que->head & (srq->wqe_cnt - 1); 936 937 buf = get_idx_buf(idx_que, head); 938 *buf = cpu_to_le32(wqe_idx); 939 940 idx_que->head++; 941 } 942 943 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 944 { 945 hr_reg_write(db, DB_TAG, srq->srqn); 946 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 947 hr_reg_write(db, DB_PI, srq->idx_que.head); 948 } 949 950 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 951 const struct ib_recv_wr *wr, 952 const struct ib_recv_wr **bad_wr) 953 { 954 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 955 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 956 struct hns_roce_v2_db srq_db; 957 unsigned long flags; 958 int ret = 0; 959 u32 max_sge; 960 u32 wqe_idx; 961 void *wqe; 962 u32 nreq; 963 964 spin_lock_irqsave(&srq->lock, flags); 965 966 max_sge = srq->max_gs - srq->rsv_sge; 967 for (nreq = 0; wr; ++nreq, wr = wr->next) { 968 ret = check_post_srq_valid(srq, max_sge, wr); 969 if (ret) { 970 *bad_wr = wr; 971 break; 972 } 973 974 ret = get_srq_wqe_idx(srq, &wqe_idx); 975 if (unlikely(ret)) { 976 *bad_wr = wr; 977 break; 978 } 979 980 wqe = get_srq_wqe_buf(srq, wqe_idx); 981 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 982 fill_wqe_idx(srq, wqe_idx); 983 srq->wrid[wqe_idx] = wr->wr_id; 984 } 985 986 if (likely(nreq)) { 987 update_srq_db(&srq_db, srq); 988 989 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 990 } 991 992 spin_unlock_irqrestore(&srq->lock, flags); 993 994 return ret; 995 } 996 997 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 998 unsigned long instance_stage, 999 unsigned long reset_stage) 1000 { 1001 /* When hardware reset has been completed once or more, we should stop 1002 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1003 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1004 * stage of soft reset process, we should exit with error, and then 1005 * HNAE3_INIT_CLIENT related process can rollback the operation like 1006 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1007 * process will exit with error to notify NIC driver to reschedule soft 1008 * reset process once again. 1009 */ 1010 hr_dev->is_reset = true; 1011 hr_dev->dis_db = true; 1012 1013 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1014 instance_stage == HNS_ROCE_STATE_INIT) 1015 return CMD_RST_PRC_EBUSY; 1016 1017 return CMD_RST_PRC_SUCCESS; 1018 } 1019 1020 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1021 unsigned long instance_stage, 1022 unsigned long reset_stage) 1023 { 1024 #define HW_RESET_TIMEOUT_US 1000000 1025 #define HW_RESET_SLEEP_US 1000 1026 1027 struct hns_roce_v2_priv *priv = hr_dev->priv; 1028 struct hnae3_handle *handle = priv->handle; 1029 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1030 unsigned long val; 1031 int ret; 1032 1033 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1034 * doorbell to hardware. If now in .init_instance() function, we should 1035 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1036 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1037 * related process can rollback the operation like notifing hardware to 1038 * free resources, HNAE3_INIT_CLIENT related process will exit with 1039 * error to notify NIC driver to reschedule soft reset process once 1040 * again. 1041 */ 1042 hr_dev->dis_db = true; 1043 1044 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1045 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1046 HW_RESET_TIMEOUT_US, false, handle); 1047 if (!ret) 1048 hr_dev->is_reset = true; 1049 1050 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1051 instance_stage == HNS_ROCE_STATE_INIT) 1052 return CMD_RST_PRC_EBUSY; 1053 1054 return CMD_RST_PRC_SUCCESS; 1055 } 1056 1057 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1058 { 1059 struct hns_roce_v2_priv *priv = hr_dev->priv; 1060 struct hnae3_handle *handle = priv->handle; 1061 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1062 1063 /* When software reset is detected at .init_instance() function, we 1064 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1065 * with error. 1066 */ 1067 hr_dev->dis_db = true; 1068 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1069 hr_dev->is_reset = true; 1070 1071 return CMD_RST_PRC_EBUSY; 1072 } 1073 1074 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1075 struct hnae3_handle *handle) 1076 { 1077 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1078 unsigned long instance_stage; /* the current instance stage */ 1079 unsigned long reset_stage; /* the current reset stage */ 1080 unsigned long reset_cnt; 1081 bool sw_resetting; 1082 bool hw_resetting; 1083 1084 /* Get information about reset from NIC driver or RoCE driver itself, 1085 * the meaning of the following variables from NIC driver are described 1086 * as below: 1087 * reset_cnt -- The count value of completed hardware reset. 1088 * hw_resetting -- Whether hardware device is resetting now. 1089 * sw_resetting -- Whether NIC's software reset process is running now. 1090 */ 1091 instance_stage = handle->rinfo.instance_state; 1092 reset_stage = handle->rinfo.reset_state; 1093 reset_cnt = ops->ae_dev_reset_cnt(handle); 1094 if (reset_cnt != hr_dev->reset_cnt) 1095 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1096 reset_stage); 1097 1098 hw_resetting = ops->get_cmdq_stat(handle); 1099 if (hw_resetting) 1100 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1101 reset_stage); 1102 1103 sw_resetting = ops->ae_dev_resetting(handle); 1104 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1105 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1106 1107 return CMD_RST_PRC_OTHERS; 1108 } 1109 1110 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1111 { 1112 struct hns_roce_v2_priv *priv = hr_dev->priv; 1113 struct hnae3_handle *handle = priv->handle; 1114 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1115 1116 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1117 return true; 1118 1119 if (ops->get_hw_reset_stat(handle)) 1120 return true; 1121 1122 if (ops->ae_dev_resetting(handle)) 1123 return true; 1124 1125 return false; 1126 } 1127 1128 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1129 { 1130 struct hns_roce_v2_priv *priv = hr_dev->priv; 1131 u32 status; 1132 1133 if (hr_dev->is_reset) 1134 status = CMD_RST_PRC_SUCCESS; 1135 else 1136 status = check_aedev_reset_status(hr_dev, priv->handle); 1137 1138 *busy = (status == CMD_RST_PRC_EBUSY); 1139 1140 return status == CMD_RST_PRC_OTHERS; 1141 } 1142 1143 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1144 struct hns_roce_v2_cmq_ring *ring) 1145 { 1146 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1147 1148 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1149 &ring->desc_dma_addr, GFP_KERNEL); 1150 if (!ring->desc) 1151 return -ENOMEM; 1152 1153 return 0; 1154 } 1155 1156 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1157 struct hns_roce_v2_cmq_ring *ring) 1158 { 1159 dma_free_coherent(hr_dev->dev, 1160 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1161 ring->desc, ring->desc_dma_addr); 1162 1163 ring->desc_dma_addr = 0; 1164 } 1165 1166 static int init_csq(struct hns_roce_dev *hr_dev, 1167 struct hns_roce_v2_cmq_ring *csq) 1168 { 1169 dma_addr_t dma; 1170 int ret; 1171 1172 csq->desc_num = CMD_CSQ_DESC_NUM; 1173 spin_lock_init(&csq->lock); 1174 csq->flag = TYPE_CSQ; 1175 csq->head = 0; 1176 1177 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1178 if (ret) 1179 return ret; 1180 1181 dma = csq->desc_dma_addr; 1182 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1183 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1184 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1185 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1186 1187 /* Make sure to write CI first and then PI */ 1188 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1189 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1190 1191 return 0; 1192 } 1193 1194 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1195 { 1196 struct hns_roce_v2_priv *priv = hr_dev->priv; 1197 int ret; 1198 1199 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1200 1201 ret = init_csq(hr_dev, &priv->cmq.csq); 1202 if (ret) 1203 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1204 1205 return ret; 1206 } 1207 1208 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1209 { 1210 struct hns_roce_v2_priv *priv = hr_dev->priv; 1211 1212 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1213 } 1214 1215 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1216 enum hns_roce_opcode_type opcode, 1217 bool is_read) 1218 { 1219 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1220 desc->opcode = cpu_to_le16(opcode); 1221 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1222 if (is_read) 1223 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1224 else 1225 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1226 } 1227 1228 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1229 { 1230 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1231 struct hns_roce_v2_priv *priv = hr_dev->priv; 1232 1233 return tail == priv->cmq.csq.head; 1234 } 1235 1236 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1237 { 1238 struct hns_roce_v2_priv *priv = hr_dev->priv; 1239 struct hnae3_handle *handle = priv->handle; 1240 1241 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1242 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1243 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1244 } 1245 1246 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1247 struct hns_roce_cmq_desc *desc, int num) 1248 { 1249 struct hns_roce_v2_priv *priv = hr_dev->priv; 1250 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1251 u32 timeout = 0; 1252 u16 desc_ret; 1253 u32 tail; 1254 int ret; 1255 int i; 1256 1257 spin_lock_bh(&csq->lock); 1258 1259 tail = csq->head; 1260 1261 for (i = 0; i < num; i++) { 1262 csq->desc[csq->head++] = desc[i]; 1263 if (csq->head == csq->desc_num) 1264 csq->head = 0; 1265 } 1266 1267 /* Write to hardware */ 1268 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1269 1270 do { 1271 if (hns_roce_cmq_csq_done(hr_dev)) 1272 break; 1273 udelay(1); 1274 } while (++timeout < priv->cmq.tx_timeout); 1275 1276 if (hns_roce_cmq_csq_done(hr_dev)) { 1277 ret = 0; 1278 for (i = 0; i < num; i++) { 1279 /* check the result of hardware write back */ 1280 desc[i] = csq->desc[tail++]; 1281 if (tail == csq->desc_num) 1282 tail = 0; 1283 1284 desc_ret = le16_to_cpu(desc[i].retval); 1285 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1286 continue; 1287 1288 dev_err_ratelimited(hr_dev->dev, 1289 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1290 desc->opcode, desc_ret); 1291 ret = -EIO; 1292 } 1293 } else { 1294 /* FW/HW reset or incorrect number of desc */ 1295 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1296 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1297 csq->head, tail); 1298 csq->head = tail; 1299 1300 update_cmdq_status(hr_dev); 1301 1302 ret = -EAGAIN; 1303 } 1304 1305 spin_unlock_bh(&csq->lock); 1306 1307 return ret; 1308 } 1309 1310 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1311 struct hns_roce_cmq_desc *desc, int num) 1312 { 1313 bool busy; 1314 int ret; 1315 1316 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1317 return -EIO; 1318 1319 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1320 return busy ? -EBUSY : 0; 1321 1322 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1323 if (ret) { 1324 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1325 return busy ? -EBUSY : 0; 1326 } 1327 1328 return ret; 1329 } 1330 1331 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1332 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1333 { 1334 struct hns_roce_cmd_mailbox *mbox; 1335 int ret; 1336 1337 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1338 if (IS_ERR(mbox)) 1339 return PTR_ERR(mbox); 1340 1341 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1342 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1343 return ret; 1344 } 1345 1346 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1347 { 1348 struct hns_roce_query_version *resp; 1349 struct hns_roce_cmq_desc desc; 1350 int ret; 1351 1352 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1353 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1354 if (ret) 1355 return ret; 1356 1357 resp = (struct hns_roce_query_version *)desc.data; 1358 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1359 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1360 1361 return 0; 1362 } 1363 1364 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1365 struct hnae3_handle *handle) 1366 { 1367 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1368 unsigned long end; 1369 1370 hr_dev->dis_db = true; 1371 1372 dev_warn(hr_dev->dev, 1373 "Func clear is pending, device in resetting state.\n"); 1374 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1375 while (end) { 1376 if (!ops->get_hw_reset_stat(handle)) { 1377 hr_dev->is_reset = true; 1378 dev_info(hr_dev->dev, 1379 "Func clear success after reset.\n"); 1380 return; 1381 } 1382 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1383 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1384 } 1385 1386 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1387 } 1388 1389 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1390 struct hnae3_handle *handle) 1391 { 1392 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1393 unsigned long end; 1394 1395 hr_dev->dis_db = true; 1396 1397 dev_warn(hr_dev->dev, 1398 "Func clear is pending, device in resetting state.\n"); 1399 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1400 while (end) { 1401 if (ops->ae_dev_reset_cnt(handle) != 1402 hr_dev->reset_cnt) { 1403 hr_dev->is_reset = true; 1404 dev_info(hr_dev->dev, 1405 "Func clear success after sw reset\n"); 1406 return; 1407 } 1408 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1409 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1410 } 1411 1412 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1413 } 1414 1415 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1416 int flag) 1417 { 1418 struct hns_roce_v2_priv *priv = hr_dev->priv; 1419 struct hnae3_handle *handle = priv->handle; 1420 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1421 1422 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1423 hr_dev->dis_db = true; 1424 hr_dev->is_reset = true; 1425 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1426 return; 1427 } 1428 1429 if (ops->get_hw_reset_stat(handle)) { 1430 func_clr_hw_resetting_state(hr_dev, handle); 1431 return; 1432 } 1433 1434 if (ops->ae_dev_resetting(handle) && 1435 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1436 func_clr_sw_resetting_state(hr_dev, handle); 1437 return; 1438 } 1439 1440 if (retval && !flag) 1441 dev_warn(hr_dev->dev, 1442 "Func clear read failed, ret = %d.\n", retval); 1443 1444 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1445 } 1446 1447 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1448 { 1449 bool fclr_write_fail_flag = false; 1450 struct hns_roce_func_clear *resp; 1451 struct hns_roce_cmq_desc desc; 1452 unsigned long end; 1453 int ret = 0; 1454 1455 if (check_device_is_in_reset(hr_dev)) 1456 goto out; 1457 1458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1459 resp = (struct hns_roce_func_clear *)desc.data; 1460 resp->rst_funcid_en = cpu_to_le32(vf_id); 1461 1462 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1463 if (ret) { 1464 fclr_write_fail_flag = true; 1465 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1466 ret); 1467 goto out; 1468 } 1469 1470 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1471 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1472 while (end) { 1473 if (check_device_is_in_reset(hr_dev)) 1474 goto out; 1475 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1476 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1477 1478 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1479 true); 1480 1481 resp->rst_funcid_en = cpu_to_le32(vf_id); 1482 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1483 if (ret) 1484 continue; 1485 1486 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1487 if (vf_id == 0) 1488 hr_dev->is_reset = true; 1489 return; 1490 } 1491 } 1492 1493 out: 1494 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1495 } 1496 1497 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1498 { 1499 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1500 struct hns_roce_cmq_desc desc[2]; 1501 struct hns_roce_cmq_req *req_a; 1502 1503 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1504 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1505 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1506 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1507 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1508 1509 return hns_roce_cmq_send(hr_dev, desc, 2); 1510 } 1511 1512 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1513 { 1514 int ret; 1515 int i; 1516 1517 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1518 return; 1519 1520 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1521 __hns_roce_function_clear(hr_dev, i); 1522 1523 if (i == 0) 1524 continue; 1525 1526 ret = hns_roce_free_vf_resource(hr_dev, i); 1527 if (ret) 1528 ibdev_err(&hr_dev->ib_dev, 1529 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1530 i, ret); 1531 } 1532 } 1533 1534 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1535 { 1536 struct hns_roce_cmq_desc desc; 1537 int ret; 1538 1539 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1540 false); 1541 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1542 if (ret) 1543 ibdev_err(&hr_dev->ib_dev, 1544 "failed to clear extended doorbell info, ret = %d.\n", 1545 ret); 1546 1547 return ret; 1548 } 1549 1550 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1551 { 1552 struct hns_roce_query_fw_info *resp; 1553 struct hns_roce_cmq_desc desc; 1554 int ret; 1555 1556 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1557 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1558 if (ret) 1559 return ret; 1560 1561 resp = (struct hns_roce_query_fw_info *)desc.data; 1562 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1563 1564 return 0; 1565 } 1566 1567 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1568 { 1569 struct hns_roce_cmq_desc desc; 1570 int ret; 1571 1572 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1573 hr_dev->func_num = 1; 1574 return 0; 1575 } 1576 1577 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1578 true); 1579 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1580 if (ret) { 1581 hr_dev->func_num = 1; 1582 return ret; 1583 } 1584 1585 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1586 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1587 1588 return 0; 1589 } 1590 1591 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1592 { 1593 struct hns_roce_cmq_desc desc; 1594 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1595 u32 clock_cycles_of_1us; 1596 1597 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1598 false); 1599 1600 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1601 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1602 else 1603 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1604 1605 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1606 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1607 1608 return hns_roce_cmq_send(hr_dev, &desc, 1); 1609 } 1610 1611 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1612 { 1613 struct hns_roce_cmq_desc desc[2]; 1614 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1615 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1616 struct hns_roce_caps *caps = &hr_dev->caps; 1617 enum hns_roce_opcode_type opcode; 1618 u32 func_num; 1619 int ret; 1620 1621 if (is_vf) { 1622 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1623 func_num = 1; 1624 } else { 1625 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1626 func_num = hr_dev->func_num; 1627 } 1628 1629 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1630 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1631 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1632 1633 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1634 if (ret) 1635 return ret; 1636 1637 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1638 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1639 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1640 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1641 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1642 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1643 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1644 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1645 1646 if (is_vf) { 1647 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1648 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1649 func_num; 1650 } else { 1651 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1652 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1653 func_num; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1660 { 1661 struct hns_roce_cmq_desc desc; 1662 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1663 struct hns_roce_caps *caps = &hr_dev->caps; 1664 u32 func_num, qp_num; 1665 int ret; 1666 1667 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1668 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1669 if (ret) 1670 return ret; 1671 1672 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1673 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1674 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1675 1676 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1677 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1678 1679 return 0; 1680 } 1681 1682 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1683 { 1684 struct hns_roce_cmq_desc desc; 1685 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1686 struct hns_roce_caps *caps = &hr_dev->caps; 1687 int ret; 1688 1689 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1690 true); 1691 1692 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1693 if (ret) 1694 return ret; 1695 1696 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1697 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1698 1699 return 0; 1700 } 1701 1702 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1703 { 1704 struct device *dev = hr_dev->dev; 1705 int ret; 1706 1707 ret = load_func_res_caps(hr_dev, is_vf); 1708 if (ret) { 1709 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1710 is_vf ? "vf" : "pf"); 1711 return ret; 1712 } 1713 1714 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1715 ret = load_ext_cfg_caps(hr_dev, is_vf); 1716 if (ret) 1717 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1718 ret, is_vf ? "vf" : "pf"); 1719 } 1720 1721 return ret; 1722 } 1723 1724 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1725 { 1726 struct device *dev = hr_dev->dev; 1727 int ret; 1728 1729 ret = query_func_resource_caps(hr_dev, false); 1730 if (ret) 1731 return ret; 1732 1733 ret = load_pf_timer_res_caps(hr_dev); 1734 if (ret) 1735 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1736 ret); 1737 1738 return ret; 1739 } 1740 1741 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1742 { 1743 return query_func_resource_caps(hr_dev, true); 1744 } 1745 1746 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1747 u32 vf_id) 1748 { 1749 struct hns_roce_vf_switch *swt; 1750 struct hns_roce_cmq_desc desc; 1751 int ret; 1752 1753 swt = (struct hns_roce_vf_switch *)desc.data; 1754 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1755 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1756 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1757 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1758 if (ret) 1759 return ret; 1760 1761 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1762 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1763 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1764 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1765 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1766 1767 return hns_roce_cmq_send(hr_dev, &desc, 1); 1768 } 1769 1770 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1771 { 1772 u32 vf_id; 1773 int ret; 1774 1775 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1776 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1777 if (ret) 1778 return ret; 1779 } 1780 return 0; 1781 } 1782 1783 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1784 { 1785 struct hns_roce_cmq_desc desc[2]; 1786 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1787 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1788 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1789 struct hns_roce_caps *caps = &hr_dev->caps; 1790 1791 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1792 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1793 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1794 1795 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1796 1797 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1798 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1799 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1800 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1801 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1802 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1803 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1804 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1805 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1806 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1807 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1808 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1809 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1810 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1811 1812 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1813 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1814 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1815 vf_id * caps->gmv_bt_num); 1816 } else { 1817 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1818 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1819 vf_id * caps->sgid_bt_num); 1820 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1821 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1822 vf_id * caps->smac_bt_num); 1823 } 1824 1825 return hns_roce_cmq_send(hr_dev, desc, 2); 1826 } 1827 1828 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1829 { 1830 struct hns_roce_cmq_desc desc; 1831 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1832 struct hns_roce_caps *caps = &hr_dev->caps; 1833 1834 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1835 1836 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1837 1838 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1839 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1840 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1841 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1842 1843 return hns_roce_cmq_send(hr_dev, &desc, 1); 1844 } 1845 1846 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1847 { 1848 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1849 u32 vf_id; 1850 int ret; 1851 1852 for (vf_id = 0; vf_id < func_num; vf_id++) { 1853 ret = config_vf_hem_resource(hr_dev, vf_id); 1854 if (ret) { 1855 dev_err(hr_dev->dev, 1856 "failed to config vf-%u hem res, ret = %d.\n", 1857 vf_id, ret); 1858 return ret; 1859 } 1860 1861 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1862 ret = config_vf_ext_resource(hr_dev, vf_id); 1863 if (ret) { 1864 dev_err(hr_dev->dev, 1865 "failed to config vf-%u ext res, ret = %d.\n", 1866 vf_id, ret); 1867 return ret; 1868 } 1869 } 1870 } 1871 1872 return 0; 1873 } 1874 1875 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1876 { 1877 struct hns_roce_cmq_desc desc; 1878 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1879 struct hns_roce_caps *caps = &hr_dev->caps; 1880 1881 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1882 1883 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1884 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1885 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1886 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1887 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1888 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1889 1890 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1891 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1892 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1893 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1894 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1895 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1896 1897 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1898 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1899 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1900 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1901 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1902 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1903 1904 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1905 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1906 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1907 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1908 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1909 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1910 1911 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1912 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1913 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1914 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1915 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1916 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1917 1918 return hns_roce_cmq_send(hr_dev, &desc, 1); 1919 } 1920 1921 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1922 static void set_default_caps(struct hns_roce_dev *hr_dev) 1923 { 1924 struct hns_roce_caps *caps = &hr_dev->caps; 1925 1926 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1927 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1928 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1929 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1930 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1931 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1932 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1933 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1934 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1935 1936 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1937 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1938 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1939 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1940 caps->num_comp_vectors = 0; 1941 1942 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1943 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1944 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1945 caps->cqc_timer_bt_num = HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM; 1946 1947 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1948 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1949 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1950 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1951 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1952 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1953 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1954 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1955 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1956 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1957 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1958 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1959 caps->reserved_lkey = 0; 1960 caps->reserved_pds = 0; 1961 caps->reserved_mrws = 1; 1962 caps->reserved_uars = 0; 1963 caps->reserved_cqs = 0; 1964 caps->reserved_srqs = 0; 1965 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1966 1967 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1968 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1969 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1970 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1971 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1972 1973 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1974 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1975 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1976 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1977 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1978 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1979 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1980 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1981 1982 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1983 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1984 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 1985 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 1986 1987 caps->pkey_table_len[0] = 1; 1988 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1989 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1990 caps->local_ca_ack_delay = 0; 1991 caps->max_mtu = IB_MTU_4096; 1992 1993 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1994 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1995 1996 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1997 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1998 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; 1999 2000 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 2001 2002 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2003 caps->flags |= HNS_ROCE_CAP_FLAG_STASH | 2004 HNS_ROCE_CAP_FLAG_DIRECT_WQE; 2005 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 2006 } else { 2007 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 2008 2009 /* The following configuration are only valid for HIP08 */ 2010 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2011 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 2012 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2013 } 2014 } 2015 2016 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2017 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2018 { 2019 u64 obj_per_chunk; 2020 u64 bt_chunk_size = PAGE_SIZE; 2021 u64 buf_chunk_size = PAGE_SIZE; 2022 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2023 2024 *buf_page_size = 0; 2025 *bt_page_size = 0; 2026 2027 switch (hop_num) { 2028 case 3: 2029 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2030 (bt_chunk_size / BA_BYTE_LEN) * 2031 (bt_chunk_size / BA_BYTE_LEN) * 2032 obj_per_chunk_default; 2033 break; 2034 case 2: 2035 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2036 (bt_chunk_size / BA_BYTE_LEN) * 2037 obj_per_chunk_default; 2038 break; 2039 case 1: 2040 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2041 obj_per_chunk_default; 2042 break; 2043 case HNS_ROCE_HOP_NUM_0: 2044 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2045 break; 2046 default: 2047 pr_err("table %u not support hop_num = %u!\n", hem_type, 2048 hop_num); 2049 return; 2050 } 2051 2052 if (hem_type >= HEM_TYPE_MTT) 2053 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2054 else 2055 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2056 } 2057 2058 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2059 { 2060 struct hns_roce_caps *caps = &hr_dev->caps; 2061 2062 /* EQ */ 2063 caps->eqe_ba_pg_sz = 0; 2064 caps->eqe_buf_pg_sz = 0; 2065 2066 /* Link Table */ 2067 caps->llm_buf_pg_sz = 0; 2068 2069 /* MR */ 2070 caps->mpt_ba_pg_sz = 0; 2071 caps->mpt_buf_pg_sz = 0; 2072 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2073 caps->pbl_buf_pg_sz = 0; 2074 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2075 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2076 HEM_TYPE_MTPT); 2077 2078 /* QP */ 2079 caps->qpc_ba_pg_sz = 0; 2080 caps->qpc_buf_pg_sz = 0; 2081 caps->qpc_timer_ba_pg_sz = 0; 2082 caps->qpc_timer_buf_pg_sz = 0; 2083 caps->sccc_ba_pg_sz = 0; 2084 caps->sccc_buf_pg_sz = 0; 2085 caps->mtt_ba_pg_sz = 0; 2086 caps->mtt_buf_pg_sz = 0; 2087 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2088 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2089 HEM_TYPE_QPC); 2090 2091 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2092 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2093 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2094 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2095 2096 /* CQ */ 2097 caps->cqc_ba_pg_sz = 0; 2098 caps->cqc_buf_pg_sz = 0; 2099 caps->cqc_timer_ba_pg_sz = 0; 2100 caps->cqc_timer_buf_pg_sz = 0; 2101 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2102 caps->cqe_buf_pg_sz = 0; 2103 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2104 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2105 HEM_TYPE_CQC); 2106 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2107 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2108 2109 /* SRQ */ 2110 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2111 caps->srqc_ba_pg_sz = 0; 2112 caps->srqc_buf_pg_sz = 0; 2113 caps->srqwqe_ba_pg_sz = 0; 2114 caps->srqwqe_buf_pg_sz = 0; 2115 caps->idx_ba_pg_sz = 0; 2116 caps->idx_buf_pg_sz = 0; 2117 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2118 caps->srqc_hop_num, caps->srqc_bt_num, 2119 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2120 HEM_TYPE_SRQC); 2121 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2122 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2123 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2124 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2125 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2126 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2127 } 2128 2129 /* GMV */ 2130 caps->gmv_ba_pg_sz = 0; 2131 caps->gmv_buf_pg_sz = 0; 2132 } 2133 2134 /* Apply all loaded caps before setting to hardware */ 2135 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2136 { 2137 struct hns_roce_caps *caps = &hr_dev->caps; 2138 struct hns_roce_v2_priv *priv = hr_dev->priv; 2139 2140 /* The following configurations don't need to be got from firmware. */ 2141 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2142 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2143 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2144 2145 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2146 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2147 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2148 2149 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2150 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2151 2152 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 2153 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2154 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2155 2156 if (!caps->num_comp_vectors) 2157 caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1, 2158 (u32)priv->handle->rinfo.num_vectors - 2); 2159 2160 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2161 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2162 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2163 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2164 2165 /* The following configurations will be overwritten */ 2166 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2167 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2168 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2169 2170 /* The following configurations are not got from firmware */ 2171 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2172 2173 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2174 caps->gid_table_len[0] = caps->gmv_bt_num * 2175 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2176 2177 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2178 caps->gmv_entry_sz); 2179 } else { 2180 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2181 2182 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2183 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2184 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2185 caps->gid_table_len[0] /= func_num; 2186 } 2187 2188 if (hr_dev->is_vf) { 2189 caps->default_aeq_arm_st = 0x3; 2190 caps->default_ceq_arm_st = 0x3; 2191 caps->default_ceq_max_cnt = 0x1; 2192 caps->default_ceq_period = 0x10; 2193 caps->default_aeq_max_cnt = 0x1; 2194 caps->default_aeq_period = 0x10; 2195 } 2196 2197 set_hem_page_size(hr_dev); 2198 } 2199 2200 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2201 { 2202 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2203 struct hns_roce_caps *caps = &hr_dev->caps; 2204 struct hns_roce_query_pf_caps_a *resp_a; 2205 struct hns_roce_query_pf_caps_b *resp_b; 2206 struct hns_roce_query_pf_caps_c *resp_c; 2207 struct hns_roce_query_pf_caps_d *resp_d; 2208 struct hns_roce_query_pf_caps_e *resp_e; 2209 int ctx_hop_num; 2210 int pbl_hop_num; 2211 int ret; 2212 int i; 2213 2214 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2215 hns_roce_cmq_setup_basic_desc(&desc[i], 2216 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2217 true); 2218 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2219 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2220 else 2221 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2222 } 2223 2224 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2225 if (ret) 2226 return ret; 2227 2228 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2229 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2230 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2231 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2232 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2233 2234 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2235 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2236 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2237 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2238 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2239 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 2240 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 2241 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2242 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2243 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2244 caps->num_other_vectors = resp_a->num_other_vectors; 2245 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2246 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2247 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 2248 caps->cqe_sz = resp_a->cqe_sz; 2249 2250 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2251 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2252 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2253 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2254 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2255 caps->idx_entry_sz = resp_b->idx_entry_sz; 2256 caps->sccc_sz = resp_b->sccc_sz; 2257 caps->max_mtu = resp_b->max_mtu; 2258 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2259 caps->min_cqes = resp_b->min_cqes; 2260 caps->min_wqes = resp_b->min_wqes; 2261 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2262 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2263 caps->phy_num_uars = resp_b->phy_num_uars; 2264 ctx_hop_num = resp_b->ctx_hop_num; 2265 pbl_hop_num = resp_b->pbl_hop_num; 2266 2267 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2268 2269 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2270 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2271 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2272 2273 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2274 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2275 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2276 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2277 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2278 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2279 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2280 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2281 2282 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2283 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2284 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2285 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2286 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2287 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2288 caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2289 caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2290 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2291 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2292 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2293 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2294 2295 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2296 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2297 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2298 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2299 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2300 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2301 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2302 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2303 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2304 2305 caps->qpc_hop_num = ctx_hop_num; 2306 caps->sccc_hop_num = ctx_hop_num; 2307 caps->srqc_hop_num = ctx_hop_num; 2308 caps->cqc_hop_num = ctx_hop_num; 2309 caps->mpt_hop_num = ctx_hop_num; 2310 caps->mtt_hop_num = pbl_hop_num; 2311 caps->cqe_hop_num = pbl_hop_num; 2312 caps->srqwqe_hop_num = pbl_hop_num; 2313 caps->idx_hop_num = pbl_hop_num; 2314 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2315 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2316 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2317 2318 return 0; 2319 } 2320 2321 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2322 { 2323 struct hns_roce_cmq_desc desc; 2324 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2325 2326 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2327 false); 2328 2329 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2330 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2331 2332 return hns_roce_cmq_send(hr_dev, &desc, 1); 2333 } 2334 2335 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2336 { 2337 struct hns_roce_caps *caps = &hr_dev->caps; 2338 int ret; 2339 2340 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2341 return 0; 2342 2343 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2344 caps->qpc_sz); 2345 if (ret) { 2346 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2347 return ret; 2348 } 2349 2350 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2351 caps->sccc_sz); 2352 if (ret) 2353 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2354 2355 return ret; 2356 } 2357 2358 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2359 { 2360 struct device *dev = hr_dev->dev; 2361 int ret; 2362 2363 hr_dev->func_num = 1; 2364 2365 set_default_caps(hr_dev); 2366 2367 ret = hns_roce_query_vf_resource(hr_dev); 2368 if (ret) { 2369 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2370 return ret; 2371 } 2372 2373 apply_func_caps(hr_dev); 2374 2375 ret = hns_roce_v2_set_bt(hr_dev); 2376 if (ret) 2377 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2378 2379 return ret; 2380 } 2381 2382 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2383 { 2384 struct device *dev = hr_dev->dev; 2385 int ret; 2386 2387 ret = hns_roce_query_func_info(hr_dev); 2388 if (ret) { 2389 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2390 return ret; 2391 } 2392 2393 ret = hns_roce_config_global_param(hr_dev); 2394 if (ret) { 2395 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2396 return ret; 2397 } 2398 2399 ret = hns_roce_set_vf_switch_param(hr_dev); 2400 if (ret) { 2401 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2402 return ret; 2403 } 2404 2405 ret = hns_roce_query_pf_caps(hr_dev); 2406 if (ret) 2407 set_default_caps(hr_dev); 2408 2409 ret = hns_roce_query_pf_resource(hr_dev); 2410 if (ret) { 2411 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2412 return ret; 2413 } 2414 2415 apply_func_caps(hr_dev); 2416 2417 ret = hns_roce_alloc_vf_resource(hr_dev); 2418 if (ret) { 2419 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2420 return ret; 2421 } 2422 2423 ret = hns_roce_v2_set_bt(hr_dev); 2424 if (ret) { 2425 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2426 return ret; 2427 } 2428 2429 /* Configure the size of QPC, SCCC, etc. */ 2430 return hns_roce_config_entry_size(hr_dev); 2431 } 2432 2433 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2434 { 2435 struct device *dev = hr_dev->dev; 2436 int ret; 2437 2438 ret = hns_roce_cmq_query_hw_info(hr_dev); 2439 if (ret) { 2440 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2441 return ret; 2442 } 2443 2444 ret = hns_roce_query_fw_ver(hr_dev); 2445 if (ret) { 2446 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2447 return ret; 2448 } 2449 2450 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2451 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2452 2453 if (hr_dev->is_vf) 2454 return hns_roce_v2_vf_profile(hr_dev); 2455 else 2456 return hns_roce_v2_pf_profile(hr_dev); 2457 } 2458 2459 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2460 { 2461 u32 i, next_ptr, page_num; 2462 __le64 *entry = cfg_buf; 2463 dma_addr_t addr; 2464 u64 val; 2465 2466 page_num = data_buf->npages; 2467 for (i = 0; i < page_num; i++) { 2468 addr = hns_roce_buf_page(data_buf, i); 2469 if (i == (page_num - 1)) 2470 next_ptr = 0; 2471 else 2472 next_ptr = i + 1; 2473 2474 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2475 entry[i] = cpu_to_le64(val); 2476 } 2477 } 2478 2479 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2480 struct hns_roce_link_table *table) 2481 { 2482 struct hns_roce_cmq_desc desc[2]; 2483 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2484 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2485 struct hns_roce_buf *buf = table->buf; 2486 enum hns_roce_opcode_type opcode; 2487 dma_addr_t addr; 2488 2489 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2490 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2491 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2492 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2493 2494 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2495 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2496 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2497 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2498 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2499 2500 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2501 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2502 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2503 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2504 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2505 2506 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2507 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2508 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2509 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2510 2511 return hns_roce_cmq_send(hr_dev, desc, 2); 2512 } 2513 2514 static struct hns_roce_link_table * 2515 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2516 { 2517 struct hns_roce_v2_priv *priv = hr_dev->priv; 2518 struct hns_roce_link_table *link_tbl; 2519 u32 pg_shift, size, min_size; 2520 2521 link_tbl = &priv->ext_llm; 2522 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2523 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2524 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2525 2526 /* Alloc data table */ 2527 size = max(size, min_size); 2528 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2529 if (IS_ERR(link_tbl->buf)) 2530 return ERR_PTR(-ENOMEM); 2531 2532 /* Alloc config table */ 2533 size = link_tbl->buf->npages * sizeof(u64); 2534 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2535 &link_tbl->table.map, 2536 GFP_KERNEL); 2537 if (!link_tbl->table.buf) { 2538 hns_roce_buf_free(hr_dev, link_tbl->buf); 2539 return ERR_PTR(-ENOMEM); 2540 } 2541 2542 return link_tbl; 2543 } 2544 2545 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2546 struct hns_roce_link_table *tbl) 2547 { 2548 if (tbl->buf) { 2549 u32 size = tbl->buf->npages * sizeof(u64); 2550 2551 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2552 tbl->table.map); 2553 } 2554 2555 hns_roce_buf_free(hr_dev, tbl->buf); 2556 } 2557 2558 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2559 { 2560 struct hns_roce_link_table *link_tbl; 2561 int ret; 2562 2563 link_tbl = alloc_link_table_buf(hr_dev); 2564 if (IS_ERR(link_tbl)) 2565 return -ENOMEM; 2566 2567 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2568 ret = -EINVAL; 2569 goto err_alloc; 2570 } 2571 2572 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2573 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2574 if (ret) 2575 goto err_alloc; 2576 2577 return 0; 2578 2579 err_alloc: 2580 free_link_table_buf(hr_dev, link_tbl); 2581 return ret; 2582 } 2583 2584 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2585 { 2586 struct hns_roce_v2_priv *priv = hr_dev->priv; 2587 2588 free_link_table_buf(hr_dev, &priv->ext_llm); 2589 } 2590 2591 static void free_dip_list(struct hns_roce_dev *hr_dev) 2592 { 2593 struct hns_roce_dip *hr_dip; 2594 struct hns_roce_dip *tmp; 2595 unsigned long flags; 2596 2597 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2598 2599 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2600 list_del(&hr_dip->node); 2601 kfree(hr_dip); 2602 } 2603 2604 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2605 } 2606 2607 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2608 { 2609 struct hns_roce_v2_priv *priv = hr_dev->priv; 2610 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2611 int ret; 2612 int i; 2613 2614 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2615 if (free_mr->rsv_qp[i]) { 2616 ret = ib_destroy_qp(free_mr->rsv_qp[i]); 2617 if (ret) 2618 ibdev_err(&hr_dev->ib_dev, 2619 "failed to destroy qp in free mr.\n"); 2620 2621 free_mr->rsv_qp[i] = NULL; 2622 } 2623 } 2624 2625 if (free_mr->rsv_cq) { 2626 ib_destroy_cq(free_mr->rsv_cq); 2627 free_mr->rsv_cq = NULL; 2628 } 2629 2630 if (free_mr->rsv_pd) { 2631 ib_dealloc_pd(free_mr->rsv_pd); 2632 free_mr->rsv_pd = NULL; 2633 } 2634 } 2635 2636 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2637 { 2638 struct hns_roce_v2_priv *priv = hr_dev->priv; 2639 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2640 struct ib_device *ibdev = &hr_dev->ib_dev; 2641 struct ib_cq_init_attr cq_init_attr = {}; 2642 struct ib_qp_init_attr qp_init_attr = {}; 2643 struct ib_pd *pd; 2644 struct ib_cq *cq; 2645 struct ib_qp *qp; 2646 int ret; 2647 int i; 2648 2649 pd = ib_alloc_pd(ibdev, 0); 2650 if (IS_ERR(pd)) { 2651 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2652 return PTR_ERR(pd); 2653 } 2654 free_mr->rsv_pd = pd; 2655 2656 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2657 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_init_attr); 2658 if (IS_ERR(cq)) { 2659 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2660 ret = PTR_ERR(cq); 2661 goto create_failed; 2662 } 2663 free_mr->rsv_cq = cq; 2664 2665 qp_init_attr.qp_type = IB_QPT_RC; 2666 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2667 qp_init_attr.send_cq = free_mr->rsv_cq; 2668 qp_init_attr.recv_cq = free_mr->rsv_cq; 2669 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2670 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2671 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2672 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2673 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2674 2675 qp = ib_create_qp(free_mr->rsv_pd, &qp_init_attr); 2676 if (IS_ERR(qp)) { 2677 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2678 ret = PTR_ERR(qp); 2679 goto create_failed; 2680 } 2681 2682 free_mr->rsv_qp[i] = qp; 2683 } 2684 2685 return 0; 2686 2687 create_failed: 2688 free_mr_exit(hr_dev); 2689 2690 return ret; 2691 } 2692 2693 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2694 struct ib_qp_attr *attr, int sl_num) 2695 { 2696 struct hns_roce_v2_priv *priv = hr_dev->priv; 2697 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2698 struct ib_device *ibdev = &hr_dev->ib_dev; 2699 struct hns_roce_qp *hr_qp; 2700 int loopback; 2701 int mask; 2702 int ret; 2703 2704 hr_qp = to_hr_qp(free_mr->rsv_qp[sl_num]); 2705 hr_qp->free_mr_en = 1; 2706 2707 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2708 attr->qp_state = IB_QPS_INIT; 2709 attr->port_num = 1; 2710 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2711 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2712 if (ret) { 2713 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2714 ret); 2715 return ret; 2716 } 2717 2718 loopback = hr_dev->loop_idc; 2719 /* Set qpc lbi = 1 incidate loopback IO */ 2720 hr_dev->loop_idc = 1; 2721 2722 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2723 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2724 attr->qp_state = IB_QPS_RTR; 2725 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2726 attr->path_mtu = IB_MTU_256; 2727 attr->dest_qp_num = hr_qp->qpn; 2728 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2729 2730 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2731 2732 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2733 hr_dev->loop_idc = loopback; 2734 if (ret) { 2735 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2736 ret); 2737 return ret; 2738 } 2739 2740 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2741 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2742 attr->qp_state = IB_QPS_RTS; 2743 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2744 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2745 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2746 ret = ib_modify_qp(&hr_qp->ibqp, attr, mask); 2747 if (ret) 2748 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2749 ret); 2750 2751 return ret; 2752 } 2753 2754 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2755 { 2756 struct hns_roce_v2_priv *priv = hr_dev->priv; 2757 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2758 struct ib_qp_attr attr = {}; 2759 int ret; 2760 int i; 2761 2762 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2763 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2764 rdma_ah_set_port_num(&attr.ah_attr, 1); 2765 2766 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2767 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2768 if (ret) 2769 return ret; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int free_mr_init(struct hns_roce_dev *hr_dev) 2776 { 2777 int ret; 2778 2779 ret = free_mr_alloc_res(hr_dev); 2780 if (ret) 2781 return ret; 2782 2783 ret = free_mr_modify_qp(hr_dev); 2784 if (ret) 2785 goto err_modify_qp; 2786 2787 return 0; 2788 2789 err_modify_qp: 2790 free_mr_exit(hr_dev); 2791 2792 return ret; 2793 } 2794 2795 static int get_hem_table(struct hns_roce_dev *hr_dev) 2796 { 2797 unsigned int qpc_count; 2798 unsigned int cqc_count; 2799 unsigned int gmv_count; 2800 int ret; 2801 int i; 2802 2803 /* Alloc memory for source address table buffer space chunk */ 2804 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2805 gmv_count++) { 2806 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2807 if (ret) 2808 goto err_gmv_failed; 2809 } 2810 2811 if (hr_dev->is_vf) 2812 return 0; 2813 2814 /* Alloc memory for QPC Timer buffer space chunk */ 2815 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2816 qpc_count++) { 2817 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2818 qpc_count); 2819 if (ret) { 2820 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2821 goto err_qpc_timer_failed; 2822 } 2823 } 2824 2825 /* Alloc memory for CQC Timer buffer space chunk */ 2826 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2827 cqc_count++) { 2828 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2829 cqc_count); 2830 if (ret) { 2831 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2832 goto err_cqc_timer_failed; 2833 } 2834 } 2835 2836 return 0; 2837 2838 err_cqc_timer_failed: 2839 for (i = 0; i < cqc_count; i++) 2840 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2841 2842 err_qpc_timer_failed: 2843 for (i = 0; i < qpc_count; i++) 2844 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2845 2846 err_gmv_failed: 2847 for (i = 0; i < gmv_count; i++) 2848 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2849 2850 return ret; 2851 } 2852 2853 static void put_hem_table(struct hns_roce_dev *hr_dev) 2854 { 2855 int i; 2856 2857 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2858 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2859 2860 if (hr_dev->is_vf) 2861 return; 2862 2863 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2864 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2865 2866 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2867 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2868 } 2869 2870 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2871 { 2872 int ret; 2873 2874 /* The hns ROCEE requires the extdb info to be cleared before using */ 2875 ret = hns_roce_clear_extdb_list_info(hr_dev); 2876 if (ret) 2877 return ret; 2878 2879 ret = get_hem_table(hr_dev); 2880 if (ret) 2881 return ret; 2882 2883 if (hr_dev->is_vf) 2884 return 0; 2885 2886 ret = hns_roce_init_link_table(hr_dev); 2887 if (ret) { 2888 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2889 goto err_llm_init_failed; 2890 } 2891 2892 return 0; 2893 2894 err_llm_init_failed: 2895 put_hem_table(hr_dev); 2896 2897 return ret; 2898 } 2899 2900 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2901 { 2902 hns_roce_function_clear(hr_dev); 2903 2904 if (!hr_dev->is_vf) 2905 hns_roce_free_link_table(hr_dev); 2906 2907 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2908 free_dip_list(hr_dev); 2909 } 2910 2911 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2912 struct hns_roce_mbox_msg *mbox_msg) 2913 { 2914 struct hns_roce_cmq_desc desc; 2915 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2916 2917 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2918 2919 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2920 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2921 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2922 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2923 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2924 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2925 mbox_msg->token); 2926 2927 return hns_roce_cmq_send(hr_dev, &desc, 1); 2928 } 2929 2930 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2931 u8 *complete_status) 2932 { 2933 struct hns_roce_mbox_status *mb_st; 2934 struct hns_roce_cmq_desc desc; 2935 unsigned long end; 2936 int ret = -EBUSY; 2937 u32 status; 2938 bool busy; 2939 2940 mb_st = (struct hns_roce_mbox_status *)desc.data; 2941 end = msecs_to_jiffies(timeout) + jiffies; 2942 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2943 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2944 return -EIO; 2945 2946 status = 0; 2947 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2948 true); 2949 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2950 if (!ret) { 2951 status = le32_to_cpu(mb_st->mb_status_hw_run); 2952 /* No pending message exists in ROCEE mbox. */ 2953 if (!(status & MB_ST_HW_RUN_M)) 2954 break; 2955 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2956 break; 2957 } 2958 2959 if (time_after(jiffies, end)) { 2960 dev_err_ratelimited(hr_dev->dev, 2961 "failed to wait mbox status 0x%x\n", 2962 status); 2963 return -ETIMEDOUT; 2964 } 2965 2966 cond_resched(); 2967 ret = -EBUSY; 2968 } 2969 2970 if (!ret) { 2971 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2972 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2973 /* Ignore all errors if the mbox is unavailable. */ 2974 ret = 0; 2975 *complete_status = MB_ST_COMPLETE_M; 2976 } 2977 2978 return ret; 2979 } 2980 2981 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 2982 struct hns_roce_mbox_msg *mbox_msg) 2983 { 2984 u8 status = 0; 2985 int ret; 2986 2987 /* Waiting for the mbox to be idle */ 2988 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 2989 &status); 2990 if (unlikely(ret)) { 2991 dev_err_ratelimited(hr_dev->dev, 2992 "failed to check post mbox status = 0x%x, ret = %d.\n", 2993 status, ret); 2994 return ret; 2995 } 2996 2997 /* Post new message to mbox */ 2998 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 2999 if (ret) 3000 dev_err_ratelimited(hr_dev->dev, 3001 "failed to post mailbox, ret = %d.\n", ret); 3002 3003 return ret; 3004 } 3005 3006 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3007 { 3008 u8 status = 0; 3009 int ret; 3010 3011 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3012 &status); 3013 if (!ret) { 3014 if (status != MB_ST_COMPLETE_SUCC) 3015 return -EBUSY; 3016 } else { 3017 dev_err_ratelimited(hr_dev->dev, 3018 "failed to check mbox status = 0x%x, ret = %d.\n", 3019 status, ret); 3020 } 3021 3022 return ret; 3023 } 3024 3025 static void copy_gid(void *dest, const union ib_gid *gid) 3026 { 3027 #define GID_SIZE 4 3028 const union ib_gid *src = gid; 3029 __le32 (*p)[GID_SIZE] = dest; 3030 int i; 3031 3032 if (!gid) 3033 src = &zgid; 3034 3035 for (i = 0; i < GID_SIZE; i++) 3036 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3037 } 3038 3039 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3040 int gid_index, const union ib_gid *gid, 3041 enum hns_roce_sgid_type sgid_type) 3042 { 3043 struct hns_roce_cmq_desc desc; 3044 struct hns_roce_cfg_sgid_tb *sgid_tb = 3045 (struct hns_roce_cfg_sgid_tb *)desc.data; 3046 3047 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3048 3049 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3050 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3051 3052 copy_gid(&sgid_tb->vf_sgid_l, gid); 3053 3054 return hns_roce_cmq_send(hr_dev, &desc, 1); 3055 } 3056 3057 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3058 int gid_index, const union ib_gid *gid, 3059 enum hns_roce_sgid_type sgid_type, 3060 const struct ib_gid_attr *attr) 3061 { 3062 struct hns_roce_cmq_desc desc[2]; 3063 struct hns_roce_cfg_gmv_tb_a *tb_a = 3064 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3065 struct hns_roce_cfg_gmv_tb_b *tb_b = 3066 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3067 3068 u16 vlan_id = VLAN_CFI_MASK; 3069 u8 mac[ETH_ALEN] = {}; 3070 int ret; 3071 3072 if (gid) { 3073 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3074 if (ret) 3075 return ret; 3076 } 3077 3078 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3079 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3080 3081 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3082 3083 copy_gid(&tb_a->vf_sgid_l, gid); 3084 3085 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3086 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3087 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3088 3089 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3090 3091 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3092 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3093 3094 return hns_roce_cmq_send(hr_dev, desc, 2); 3095 } 3096 3097 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3098 const union ib_gid *gid, 3099 const struct ib_gid_attr *attr) 3100 { 3101 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3102 int ret; 3103 3104 if (gid) { 3105 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3106 if (ipv6_addr_v4mapped((void *)gid)) 3107 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3108 else 3109 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3110 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3111 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3112 } 3113 } 3114 3115 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3116 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3117 else 3118 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3119 3120 if (ret) 3121 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3122 ret); 3123 3124 return ret; 3125 } 3126 3127 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3128 const u8 *addr) 3129 { 3130 struct hns_roce_cmq_desc desc; 3131 struct hns_roce_cfg_smac_tb *smac_tb = 3132 (struct hns_roce_cfg_smac_tb *)desc.data; 3133 u16 reg_smac_h; 3134 u32 reg_smac_l; 3135 3136 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3137 3138 reg_smac_l = *(u32 *)(&addr[0]); 3139 reg_smac_h = *(u16 *)(&addr[4]); 3140 3141 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3142 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3143 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3144 3145 return hns_roce_cmq_send(hr_dev, &desc, 1); 3146 } 3147 3148 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3149 struct hns_roce_v2_mpt_entry *mpt_entry, 3150 struct hns_roce_mr *mr) 3151 { 3152 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3153 struct ib_device *ibdev = &hr_dev->ib_dev; 3154 dma_addr_t pbl_ba; 3155 int i, count; 3156 3157 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3158 ARRAY_SIZE(pages), &pbl_ba); 3159 if (count < 1) { 3160 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3161 count); 3162 return -ENOBUFS; 3163 } 3164 3165 /* Aligned to the hardware address access unit */ 3166 for (i = 0; i < count; i++) 3167 pages[i] >>= 6; 3168 3169 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3170 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3171 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3172 3173 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3174 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3175 3176 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3177 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3178 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3179 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3180 3181 return 0; 3182 } 3183 3184 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3185 void *mb_buf, struct hns_roce_mr *mr) 3186 { 3187 struct hns_roce_v2_mpt_entry *mpt_entry; 3188 3189 mpt_entry = mb_buf; 3190 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3191 3192 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3193 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3194 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3195 3196 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3197 mr->access & IB_ACCESS_MW_BIND); 3198 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3199 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3200 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3201 mr->access & IB_ACCESS_REMOTE_READ); 3202 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3203 mr->access & IB_ACCESS_REMOTE_WRITE); 3204 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3205 mr->access & IB_ACCESS_LOCAL_WRITE); 3206 3207 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3208 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3209 mpt_entry->lkey = cpu_to_le32(mr->key); 3210 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3211 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3212 3213 if (mr->type != MR_TYPE_MR) 3214 hr_reg_enable(mpt_entry, MPT_PA); 3215 3216 if (mr->type == MR_TYPE_DMA) 3217 return 0; 3218 3219 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3220 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3221 3222 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3223 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3224 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3225 3226 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3227 } 3228 3229 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3230 struct hns_roce_mr *mr, int flags, 3231 void *mb_buf) 3232 { 3233 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3234 u32 mr_access_flags = mr->access; 3235 int ret = 0; 3236 3237 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3238 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3239 3240 if (flags & IB_MR_REREG_ACCESS) { 3241 hr_reg_write(mpt_entry, MPT_BIND_EN, 3242 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3243 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3244 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3245 hr_reg_write(mpt_entry, MPT_RR_EN, 3246 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3247 hr_reg_write(mpt_entry, MPT_RW_EN, 3248 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3249 hr_reg_write(mpt_entry, MPT_LW_EN, 3250 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3251 } 3252 3253 if (flags & IB_MR_REREG_TRANS) { 3254 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3255 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3256 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3257 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3258 3259 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3260 } 3261 3262 return ret; 3263 } 3264 3265 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3266 void *mb_buf, struct hns_roce_mr *mr) 3267 { 3268 struct ib_device *ibdev = &hr_dev->ib_dev; 3269 struct hns_roce_v2_mpt_entry *mpt_entry; 3270 dma_addr_t pbl_ba = 0; 3271 3272 mpt_entry = mb_buf; 3273 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3274 3275 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3276 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3277 return -ENOBUFS; 3278 } 3279 3280 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3281 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3282 3283 hr_reg_enable(mpt_entry, MPT_RA_EN); 3284 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3285 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3286 3287 hr_reg_enable(mpt_entry, MPT_FRE); 3288 hr_reg_clear(mpt_entry, MPT_MR_MW); 3289 hr_reg_enable(mpt_entry, MPT_BPD); 3290 hr_reg_clear(mpt_entry, MPT_PA); 3291 3292 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3293 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3294 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3295 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3296 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3297 3298 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3299 3300 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3301 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3302 3303 return 0; 3304 } 3305 3306 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3307 { 3308 struct hns_roce_v2_mpt_entry *mpt_entry; 3309 3310 mpt_entry = mb_buf; 3311 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3312 3313 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3314 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3315 3316 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3317 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3318 hr_reg_enable(mpt_entry, MPT_LW_EN); 3319 3320 hr_reg_enable(mpt_entry, MPT_MR_MW); 3321 hr_reg_enable(mpt_entry, MPT_BPD); 3322 hr_reg_clear(mpt_entry, MPT_PA); 3323 hr_reg_write(mpt_entry, MPT_BQP, 3324 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3325 3326 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3327 3328 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3329 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3330 mw->pbl_hop_num); 3331 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3332 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3333 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3334 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3335 3336 return 0; 3337 } 3338 3339 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3340 { 3341 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3342 struct ib_device *ibdev = &hr_dev->ib_dev; 3343 const struct ib_send_wr *bad_wr; 3344 struct ib_rdma_wr rdma_wr = {}; 3345 struct ib_send_wr *send_wr; 3346 int ret; 3347 3348 send_wr = &rdma_wr.wr; 3349 send_wr->opcode = IB_WR_RDMA_WRITE; 3350 3351 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3352 if (ret) { 3353 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3354 ret); 3355 return ret; 3356 } 3357 3358 return 0; 3359 } 3360 3361 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3362 struct ib_wc *wc); 3363 3364 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3365 { 3366 struct hns_roce_v2_priv *priv = hr_dev->priv; 3367 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3368 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3369 struct ib_device *ibdev = &hr_dev->ib_dev; 3370 struct hns_roce_qp *hr_qp; 3371 unsigned long end; 3372 int cqe_cnt = 0; 3373 int npolled; 3374 int ret; 3375 int i; 3376 3377 /* 3378 * If the device initialization is not complete or in the uninstall 3379 * process, then there is no need to execute free mr. 3380 */ 3381 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3382 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3383 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3384 return; 3385 3386 mutex_lock(&free_mr->mutex); 3387 3388 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3389 hr_qp = to_hr_qp(free_mr->rsv_qp[i]); 3390 3391 ret = free_mr_post_send_lp_wqe(hr_qp); 3392 if (ret) { 3393 ibdev_err(ibdev, 3394 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3395 hr_qp->qpn, ret); 3396 break; 3397 } 3398 3399 cqe_cnt++; 3400 } 3401 3402 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3403 while (cqe_cnt) { 3404 npolled = hns_roce_v2_poll_cq(free_mr->rsv_cq, cqe_cnt, wc); 3405 if (npolled < 0) { 3406 ibdev_err(ibdev, 3407 "failed to poll cqe for free mr, remain %d cqe.\n", 3408 cqe_cnt); 3409 goto out; 3410 } 3411 3412 if (time_after(jiffies, end)) { 3413 ibdev_err(ibdev, 3414 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3415 cqe_cnt); 3416 goto out; 3417 } 3418 cqe_cnt -= npolled; 3419 } 3420 3421 out: 3422 mutex_unlock(&free_mr->mutex); 3423 } 3424 3425 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3426 { 3427 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3428 free_mr_send_cmd_to_hw(hr_dev); 3429 } 3430 3431 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3432 { 3433 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3434 } 3435 3436 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3437 { 3438 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3439 3440 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3441 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3442 NULL; 3443 } 3444 3445 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3446 struct hns_roce_cq *hr_cq) 3447 { 3448 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3449 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3450 } else { 3451 struct hns_roce_v2_db cq_db = {}; 3452 3453 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3454 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3455 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3456 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3457 3458 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3459 } 3460 } 3461 3462 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3463 struct hns_roce_srq *srq) 3464 { 3465 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3466 struct hns_roce_v2_cqe *cqe, *dest; 3467 u32 prod_index; 3468 int nfreed = 0; 3469 int wqe_index; 3470 u8 owner_bit; 3471 3472 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3473 ++prod_index) { 3474 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3475 break; 3476 } 3477 3478 /* 3479 * Now backwards through the CQ, removing CQ entries 3480 * that match our QP by overwriting them with next entries. 3481 */ 3482 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3483 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3484 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3485 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3486 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3487 hns_roce_free_srq_wqe(srq, wqe_index); 3488 } 3489 ++nfreed; 3490 } else if (nfreed) { 3491 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3492 hr_cq->ib_cq.cqe); 3493 owner_bit = hr_reg_read(dest, CQE_OWNER); 3494 memcpy(dest, cqe, hr_cq->cqe_size); 3495 hr_reg_write(dest, CQE_OWNER, owner_bit); 3496 } 3497 } 3498 3499 if (nfreed) { 3500 hr_cq->cons_index += nfreed; 3501 update_cq_db(hr_dev, hr_cq); 3502 } 3503 } 3504 3505 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3506 struct hns_roce_srq *srq) 3507 { 3508 spin_lock_irq(&hr_cq->lock); 3509 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3510 spin_unlock_irq(&hr_cq->lock); 3511 } 3512 3513 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3514 struct hns_roce_cq *hr_cq, void *mb_buf, 3515 u64 *mtts, dma_addr_t dma_handle) 3516 { 3517 struct hns_roce_v2_cq_context *cq_context; 3518 3519 cq_context = mb_buf; 3520 memset(cq_context, 0, sizeof(*cq_context)); 3521 3522 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3523 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3524 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3525 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3526 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3527 3528 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3529 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3530 3531 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3532 hr_reg_enable(cq_context, CQC_STASH); 3533 3534 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3535 to_hr_hw_page_addr(mtts[0])); 3536 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3537 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3538 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3539 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3540 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3541 to_hr_hw_page_addr(mtts[1])); 3542 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3543 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3544 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3545 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3546 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3547 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3548 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3549 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3550 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3551 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3552 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3553 ((u32)hr_cq->db.dma) >> 1); 3554 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3555 hr_cq->db.dma >> 32); 3556 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3557 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3558 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3559 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3560 } 3561 3562 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3563 enum ib_cq_notify_flags flags) 3564 { 3565 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3566 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3567 struct hns_roce_v2_db cq_db = {}; 3568 u32 notify_flag; 3569 3570 /* 3571 * flags = 0, then notify_flag : next 3572 * flags = 1, then notify flag : solocited 3573 */ 3574 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3575 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3576 3577 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3578 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3579 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3580 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3581 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3582 3583 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3584 3585 return 0; 3586 } 3587 3588 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3589 struct hns_roce_qp *qp, 3590 struct ib_wc *wc) 3591 { 3592 struct hns_roce_rinl_sge *sge_list; 3593 u32 wr_num, wr_cnt, sge_num; 3594 u32 sge_cnt, data_len, size; 3595 void *wqe_buf; 3596 3597 wr_num = hr_reg_read(cqe, CQE_WQE_IDX); 3598 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1); 3599 3600 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3601 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3602 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt); 3603 data_len = wc->byte_len; 3604 3605 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3606 size = min(sge_list[sge_cnt].len, data_len); 3607 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3608 3609 data_len -= size; 3610 wqe_buf += size; 3611 } 3612 3613 if (unlikely(data_len)) { 3614 wc->status = IB_WC_LOC_LEN_ERR; 3615 return -EAGAIN; 3616 } 3617 3618 return 0; 3619 } 3620 3621 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3622 int num_entries, struct ib_wc *wc) 3623 { 3624 unsigned int left; 3625 int npolled = 0; 3626 3627 left = wq->head - wq->tail; 3628 if (left == 0) 3629 return 0; 3630 3631 left = min_t(unsigned int, (unsigned int)num_entries, left); 3632 while (npolled < left) { 3633 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3634 wc->status = IB_WC_WR_FLUSH_ERR; 3635 wc->vendor_err = 0; 3636 wc->qp = &hr_qp->ibqp; 3637 3638 wq->tail++; 3639 wc++; 3640 npolled++; 3641 } 3642 3643 return npolled; 3644 } 3645 3646 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3647 struct ib_wc *wc) 3648 { 3649 struct hns_roce_qp *hr_qp; 3650 int npolled = 0; 3651 3652 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3653 npolled += sw_comp(hr_qp, &hr_qp->sq, 3654 num_entries - npolled, wc + npolled); 3655 if (npolled >= num_entries) 3656 goto out; 3657 } 3658 3659 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3660 npolled += sw_comp(hr_qp, &hr_qp->rq, 3661 num_entries - npolled, wc + npolled); 3662 if (npolled >= num_entries) 3663 goto out; 3664 } 3665 3666 out: 3667 return npolled; 3668 } 3669 3670 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3671 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3672 struct ib_wc *wc) 3673 { 3674 static const struct { 3675 u32 cqe_status; 3676 enum ib_wc_status wc_status; 3677 } map[] = { 3678 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3679 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3680 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3681 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3682 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3683 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3684 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3685 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3686 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3687 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3688 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3689 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3690 IB_WC_RETRY_EXC_ERR }, 3691 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3692 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3693 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3694 }; 3695 3696 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3697 int i; 3698 3699 wc->status = IB_WC_GENERAL_ERR; 3700 for (i = 0; i < ARRAY_SIZE(map); i++) 3701 if (cqe_status == map[i].cqe_status) { 3702 wc->status = map[i].wc_status; 3703 break; 3704 } 3705 3706 if (likely(wc->status == IB_WC_SUCCESS || 3707 wc->status == IB_WC_WR_FLUSH_ERR)) 3708 return; 3709 3710 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3711 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3712 cq->cqe_size, false); 3713 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3714 3715 /* 3716 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3717 * the standard protocol, the driver must ignore it and needn't to set 3718 * the QP to an error state. 3719 */ 3720 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3721 return; 3722 3723 flush_cqe(hr_dev, qp); 3724 } 3725 3726 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3727 struct hns_roce_qp **cur_qp) 3728 { 3729 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3730 struct hns_roce_qp *hr_qp = *cur_qp; 3731 u32 qpn; 3732 3733 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3734 3735 if (!hr_qp || qpn != hr_qp->qpn) { 3736 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3737 if (unlikely(!hr_qp)) { 3738 ibdev_err(&hr_dev->ib_dev, 3739 "CQ %06lx with entry for unknown QPN %06x\n", 3740 hr_cq->cqn, qpn); 3741 return -EINVAL; 3742 } 3743 *cur_qp = hr_qp; 3744 } 3745 3746 return 0; 3747 } 3748 3749 /* 3750 * mapped-value = 1 + real-value 3751 * The ib wc opcode's real value is start from 0, In order to distinguish 3752 * between initialized and uninitialized map values, we plus 1 to the actual 3753 * value when defining the mapping, so that the validity can be identified by 3754 * checking whether the mapped value is greater than 0. 3755 */ 3756 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3757 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3758 3759 static const u32 wc_send_op_map[] = { 3760 HR_WC_OP_MAP(SEND, SEND), 3761 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3762 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3763 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3764 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3765 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3766 HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV), 3767 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3768 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3769 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3770 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3771 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3772 HR_WC_OP_MAP(BIND_MW, REG_MR), 3773 }; 3774 3775 static int to_ib_wc_send_op(u32 hr_opcode) 3776 { 3777 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3778 return -EINVAL; 3779 3780 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3781 -EINVAL; 3782 } 3783 3784 static const u32 wc_recv_op_map[] = { 3785 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3786 HR_WC_OP_MAP(SEND, RECV), 3787 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3788 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3789 }; 3790 3791 static int to_ib_wc_recv_op(u32 hr_opcode) 3792 { 3793 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3794 return -EINVAL; 3795 3796 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3797 -EINVAL; 3798 } 3799 3800 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3801 { 3802 u32 hr_opcode; 3803 int ib_opcode; 3804 3805 wc->wc_flags = 0; 3806 3807 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3808 switch (hr_opcode) { 3809 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3810 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3811 break; 3812 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3813 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3814 wc->wc_flags |= IB_WC_WITH_IMM; 3815 break; 3816 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3817 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3818 break; 3819 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3820 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3821 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3822 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3823 wc->byte_len = 8; 3824 break; 3825 default: 3826 break; 3827 } 3828 3829 ib_opcode = to_ib_wc_send_op(hr_opcode); 3830 if (ib_opcode < 0) 3831 wc->status = IB_WC_GENERAL_ERR; 3832 else 3833 wc->opcode = ib_opcode; 3834 } 3835 3836 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode, 3837 struct hns_roce_v2_cqe *cqe) 3838 { 3839 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI && 3840 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND || 3841 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3842 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3843 hr_reg_read(cqe, CQE_RQ_INLINE); 3844 } 3845 3846 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3847 { 3848 struct hns_roce_qp *qp = to_hr_qp(wc->qp); 3849 u32 hr_opcode; 3850 int ib_opcode; 3851 int ret; 3852 3853 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3854 3855 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3856 switch (hr_opcode) { 3857 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3858 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3859 wc->wc_flags = IB_WC_WITH_IMM; 3860 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3861 break; 3862 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3863 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3864 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3865 break; 3866 default: 3867 wc->wc_flags = 0; 3868 } 3869 3870 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3871 if (ib_opcode < 0) 3872 wc->status = IB_WC_GENERAL_ERR; 3873 else 3874 wc->opcode = ib_opcode; 3875 3876 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) { 3877 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc); 3878 if (unlikely(ret)) 3879 return ret; 3880 } 3881 3882 wc->sl = hr_reg_read(cqe, CQE_SL); 3883 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3884 wc->slid = 0; 3885 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3886 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3887 wc->pkey_index = 0; 3888 3889 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3890 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3891 wc->wc_flags |= IB_WC_WITH_VLAN; 3892 } else { 3893 wc->vlan_id = 0xffff; 3894 } 3895 3896 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3897 3898 return 0; 3899 } 3900 3901 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3902 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3903 { 3904 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3905 struct hns_roce_qp *qp = *cur_qp; 3906 struct hns_roce_srq *srq = NULL; 3907 struct hns_roce_v2_cqe *cqe; 3908 struct hns_roce_wq *wq; 3909 int is_send; 3910 u16 wqe_idx; 3911 int ret; 3912 3913 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3914 if (!cqe) 3915 return -EAGAIN; 3916 3917 ++hr_cq->cons_index; 3918 /* Memory barrier */ 3919 rmb(); 3920 3921 ret = get_cur_qp(hr_cq, cqe, &qp); 3922 if (ret) 3923 return ret; 3924 3925 wc->qp = &qp->ibqp; 3926 wc->vendor_err = 0; 3927 3928 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3929 3930 is_send = !hr_reg_read(cqe, CQE_S_R); 3931 if (is_send) { 3932 wq = &qp->sq; 3933 3934 /* If sg_signal_bit is set, tail pointer will be updated to 3935 * the WQE corresponding to the current CQE. 3936 */ 3937 if (qp->sq_signal_bits) 3938 wq->tail += (wqe_idx - (u16)wq->tail) & 3939 (wq->wqe_cnt - 1); 3940 3941 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3942 ++wq->tail; 3943 3944 fill_send_wc(wc, cqe); 3945 } else { 3946 if (qp->ibqp.srq) { 3947 srq = to_hr_srq(qp->ibqp.srq); 3948 wc->wr_id = srq->wrid[wqe_idx]; 3949 hns_roce_free_srq_wqe(srq, wqe_idx); 3950 } else { 3951 wq = &qp->rq; 3952 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3953 ++wq->tail; 3954 } 3955 3956 ret = fill_recv_wc(wc, cqe); 3957 } 3958 3959 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3960 if (unlikely(wc->status != IB_WC_SUCCESS)) 3961 return 0; 3962 3963 return ret; 3964 } 3965 3966 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3967 struct ib_wc *wc) 3968 { 3969 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3970 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3971 struct hns_roce_qp *cur_qp = NULL; 3972 unsigned long flags; 3973 int npolled; 3974 3975 spin_lock_irqsave(&hr_cq->lock, flags); 3976 3977 /* 3978 * When the device starts to reset, the state is RST_DOWN. At this time, 3979 * there may still be some valid CQEs in the hardware that are not 3980 * polled. Therefore, it is not allowed to switch to the software mode 3981 * immediately. When the state changes to UNINIT, CQE no longer exists 3982 * in the hardware, and then switch to software mode. 3983 */ 3984 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3985 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3986 goto out; 3987 } 3988 3989 for (npolled = 0; npolled < num_entries; ++npolled) { 3990 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3991 break; 3992 } 3993 3994 if (npolled) 3995 update_cq_db(hr_dev, hr_cq); 3996 3997 out: 3998 spin_unlock_irqrestore(&hr_cq->lock, flags); 3999 4000 return npolled; 4001 } 4002 4003 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4004 u32 step_idx, u8 *mbox_cmd) 4005 { 4006 u8 cmd; 4007 4008 switch (type) { 4009 case HEM_TYPE_QPC: 4010 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4011 break; 4012 case HEM_TYPE_MTPT: 4013 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4014 break; 4015 case HEM_TYPE_CQC: 4016 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4017 break; 4018 case HEM_TYPE_SRQC: 4019 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4020 break; 4021 case HEM_TYPE_SCCC: 4022 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4023 break; 4024 case HEM_TYPE_QPC_TIMER: 4025 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4026 break; 4027 case HEM_TYPE_CQC_TIMER: 4028 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4029 break; 4030 default: 4031 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4032 return -EINVAL; 4033 } 4034 4035 *mbox_cmd = cmd + step_idx; 4036 4037 return 0; 4038 } 4039 4040 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4041 dma_addr_t base_addr) 4042 { 4043 struct hns_roce_cmq_desc desc; 4044 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4045 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4046 u64 addr = to_hr_hw_page_addr(base_addr); 4047 4048 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4049 4050 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4051 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4052 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4053 4054 return hns_roce_cmq_send(hr_dev, &desc, 1); 4055 } 4056 4057 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4058 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4059 { 4060 int ret; 4061 u8 cmd; 4062 4063 if (unlikely(hem_type == HEM_TYPE_GMV)) 4064 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4065 4066 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4067 return 0; 4068 4069 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4070 if (ret < 0) 4071 return ret; 4072 4073 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4074 } 4075 4076 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4077 struct hns_roce_hem_table *table, int obj, 4078 u32 step_idx) 4079 { 4080 struct hns_roce_hem_iter iter; 4081 struct hns_roce_hem_mhop mhop; 4082 struct hns_roce_hem *hem; 4083 unsigned long mhop_obj = obj; 4084 int i, j, k; 4085 int ret = 0; 4086 u64 hem_idx = 0; 4087 u64 l1_idx = 0; 4088 u64 bt_ba = 0; 4089 u32 chunk_ba_num; 4090 u32 hop_num; 4091 4092 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4093 return 0; 4094 4095 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4096 i = mhop.l0_idx; 4097 j = mhop.l1_idx; 4098 k = mhop.l2_idx; 4099 hop_num = mhop.hop_num; 4100 chunk_ba_num = mhop.bt_chunk_size / 8; 4101 4102 if (hop_num == 2) { 4103 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4104 k; 4105 l1_idx = i * chunk_ba_num + j; 4106 } else if (hop_num == 1) { 4107 hem_idx = i * chunk_ba_num + j; 4108 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4109 hem_idx = i; 4110 } 4111 4112 if (table->type == HEM_TYPE_SCCC) 4113 obj = mhop.l0_idx; 4114 4115 if (check_whether_last_step(hop_num, step_idx)) { 4116 hem = table->hem[hem_idx]; 4117 for (hns_roce_hem_first(hem, &iter); 4118 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4119 bt_ba = hns_roce_hem_addr(&iter); 4120 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4121 step_idx); 4122 } 4123 } else { 4124 if (step_idx == 0) 4125 bt_ba = table->bt_l0_dma_addr[i]; 4126 else if (step_idx == 1 && hop_num == 2) 4127 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4128 4129 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4130 } 4131 4132 return ret; 4133 } 4134 4135 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4136 struct hns_roce_hem_table *table, 4137 int tag, u32 step_idx) 4138 { 4139 struct hns_roce_cmd_mailbox *mailbox; 4140 struct device *dev = hr_dev->dev; 4141 u8 cmd = 0xff; 4142 int ret; 4143 4144 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4145 return 0; 4146 4147 switch (table->type) { 4148 case HEM_TYPE_QPC: 4149 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4150 break; 4151 case HEM_TYPE_MTPT: 4152 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4153 break; 4154 case HEM_TYPE_CQC: 4155 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4156 break; 4157 case HEM_TYPE_SRQC: 4158 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4159 break; 4160 case HEM_TYPE_SCCC: 4161 case HEM_TYPE_QPC_TIMER: 4162 case HEM_TYPE_CQC_TIMER: 4163 case HEM_TYPE_GMV: 4164 return 0; 4165 default: 4166 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4167 table->type); 4168 return 0; 4169 } 4170 4171 cmd += step_idx; 4172 4173 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4174 if (IS_ERR(mailbox)) 4175 return PTR_ERR(mailbox); 4176 4177 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4178 4179 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4180 return ret; 4181 } 4182 4183 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4184 struct hns_roce_v2_qp_context *context, 4185 struct hns_roce_v2_qp_context *qpc_mask, 4186 struct hns_roce_qp *hr_qp) 4187 { 4188 struct hns_roce_cmd_mailbox *mailbox; 4189 int qpc_size; 4190 int ret; 4191 4192 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4193 if (IS_ERR(mailbox)) 4194 return PTR_ERR(mailbox); 4195 4196 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4197 qpc_size = hr_dev->caps.qpc_sz; 4198 memcpy(mailbox->buf, context, qpc_size); 4199 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4200 4201 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4202 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4203 4204 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4205 4206 return ret; 4207 } 4208 4209 static void set_access_flags(struct hns_roce_qp *hr_qp, 4210 struct hns_roce_v2_qp_context *context, 4211 struct hns_roce_v2_qp_context *qpc_mask, 4212 const struct ib_qp_attr *attr, int attr_mask) 4213 { 4214 u8 dest_rd_atomic; 4215 u32 access_flags; 4216 4217 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4218 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4219 4220 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4221 attr->qp_access_flags : hr_qp->atomic_rd_en; 4222 4223 if (!dest_rd_atomic) 4224 access_flags &= IB_ACCESS_REMOTE_WRITE; 4225 4226 hr_reg_write_bool(context, QPC_RRE, 4227 access_flags & IB_ACCESS_REMOTE_READ); 4228 hr_reg_clear(qpc_mask, QPC_RRE); 4229 4230 hr_reg_write_bool(context, QPC_RWE, 4231 access_flags & IB_ACCESS_REMOTE_WRITE); 4232 hr_reg_clear(qpc_mask, QPC_RWE); 4233 4234 hr_reg_write_bool(context, QPC_ATE, 4235 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4236 hr_reg_clear(qpc_mask, QPC_ATE); 4237 hr_reg_write_bool(context, QPC_EXT_ATE, 4238 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4239 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4240 } 4241 4242 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4243 struct hns_roce_v2_qp_context *context, 4244 struct hns_roce_v2_qp_context *qpc_mask) 4245 { 4246 hr_reg_write(context, QPC_SGE_SHIFT, 4247 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4248 hr_qp->sge.sge_shift)); 4249 4250 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4251 4252 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4253 } 4254 4255 static inline int get_cqn(struct ib_cq *ib_cq) 4256 { 4257 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4258 } 4259 4260 static inline int get_pdn(struct ib_pd *ib_pd) 4261 { 4262 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4263 } 4264 4265 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4266 const struct ib_qp_attr *attr, 4267 int attr_mask, 4268 struct hns_roce_v2_qp_context *context, 4269 struct hns_roce_v2_qp_context *qpc_mask) 4270 { 4271 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4272 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4273 4274 /* 4275 * In v2 engine, software pass context and context mask to hardware 4276 * when modifying qp. If software need modify some fields in context, 4277 * we should set all bits of the relevant fields in context mask to 4278 * 0 at the same time, else set them to 0x1. 4279 */ 4280 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4281 4282 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4283 4284 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4285 4286 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4287 4288 /* No VLAN need to set 0xFFF */ 4289 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4290 4291 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4292 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4293 4294 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4295 } 4296 4297 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4298 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4299 4300 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4301 hr_reg_enable(context, QPC_OWNER_MODE); 4302 4303 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4304 lower_32_bits(hr_qp->rdb.dma) >> 1); 4305 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4306 upper_32_bits(hr_qp->rdb.dma)); 4307 4308 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI) 4309 hr_reg_write_bool(context, QPC_RQIE, 4310 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE); 4311 4312 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4313 4314 if (ibqp->srq) { 4315 hr_reg_enable(context, QPC_SRQ_EN); 4316 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4317 } 4318 4319 hr_reg_enable(context, QPC_FRE); 4320 4321 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4322 4323 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4324 return; 4325 4326 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4327 hr_reg_enable(&context->ext, QPCEX_STASH); 4328 } 4329 4330 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4331 const struct ib_qp_attr *attr, int attr_mask, 4332 struct hns_roce_v2_qp_context *context, 4333 struct hns_roce_v2_qp_context *qpc_mask) 4334 { 4335 /* 4336 * In v2 engine, software pass context and context mask to hardware 4337 * when modifying qp. If software need modify some fields in context, 4338 * we should set all bits of the relevant fields in context mask to 4339 * 0 at the same time, else set them to 0x1. 4340 */ 4341 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4342 hr_reg_clear(qpc_mask, QPC_TST); 4343 4344 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4345 hr_reg_clear(qpc_mask, QPC_PD); 4346 4347 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4348 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4349 4350 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4351 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4352 4353 if (ibqp->srq) { 4354 hr_reg_enable(context, QPC_SRQ_EN); 4355 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4356 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4357 hr_reg_clear(qpc_mask, QPC_SRQN); 4358 } 4359 } 4360 4361 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4362 struct hns_roce_qp *hr_qp, 4363 struct hns_roce_v2_qp_context *context, 4364 struct hns_roce_v2_qp_context *qpc_mask) 4365 { 4366 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4367 u64 wqe_sge_ba; 4368 int count; 4369 4370 /* Search qp buf's mtts */ 4371 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4372 MTT_MIN_COUNT, &wqe_sge_ba); 4373 if (hr_qp->rq.wqe_cnt && count < 1) { 4374 ibdev_err(&hr_dev->ib_dev, 4375 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4376 return -EINVAL; 4377 } 4378 4379 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4380 qpc_mask->wqe_sge_ba = 0; 4381 4382 /* 4383 * In v2 engine, software pass context and context mask to hardware 4384 * when modifying qp. If software need modify some fields in context, 4385 * we should set all bits of the relevant fields in context mask to 4386 * 0 at the same time, else set them to 0x1. 4387 */ 4388 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4389 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4390 4391 hr_reg_write(context, QPC_SQ_HOP_NUM, 4392 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4393 hr_qp->sq.wqe_cnt)); 4394 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4395 4396 hr_reg_write(context, QPC_SGE_HOP_NUM, 4397 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4398 hr_qp->sge.sge_cnt)); 4399 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4400 4401 hr_reg_write(context, QPC_RQ_HOP_NUM, 4402 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4403 hr_qp->rq.wqe_cnt)); 4404 4405 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4406 4407 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4408 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4409 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4410 4411 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4412 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4413 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4414 4415 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4416 qpc_mask->rq_cur_blk_addr = 0; 4417 4418 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4419 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4420 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4421 4422 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4423 qpc_mask->rq_nxt_blk_addr = 0; 4424 4425 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4426 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4427 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4428 4429 return 0; 4430 } 4431 4432 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4433 struct hns_roce_qp *hr_qp, 4434 struct hns_roce_v2_qp_context *context, 4435 struct hns_roce_v2_qp_context *qpc_mask) 4436 { 4437 struct ib_device *ibdev = &hr_dev->ib_dev; 4438 u64 sge_cur_blk = 0; 4439 u64 sq_cur_blk = 0; 4440 int count; 4441 4442 /* search qp buf's mtts */ 4443 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4444 if (count < 1) { 4445 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4446 hr_qp->qpn); 4447 return -EINVAL; 4448 } 4449 if (hr_qp->sge.sge_cnt > 0) { 4450 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4451 hr_qp->sge.offset, 4452 &sge_cur_blk, 1, NULL); 4453 if (count < 1) { 4454 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4455 hr_qp->qpn); 4456 return -EINVAL; 4457 } 4458 } 4459 4460 /* 4461 * In v2 engine, software pass context and context mask to hardware 4462 * when modifying qp. If software need modify some fields in context, 4463 * we should set all bits of the relevant fields in context mask to 4464 * 0 at the same time, else set them to 0x1. 4465 */ 4466 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4467 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4468 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4469 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4470 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4471 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4472 4473 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4474 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4475 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4476 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4477 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4478 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4479 4480 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4481 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4482 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4483 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4484 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4485 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4486 4487 return 0; 4488 } 4489 4490 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4491 const struct ib_qp_attr *attr) 4492 { 4493 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4494 return IB_MTU_4096; 4495 4496 return attr->path_mtu; 4497 } 4498 4499 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4500 const struct ib_qp_attr *attr, int attr_mask, 4501 struct hns_roce_v2_qp_context *context, 4502 struct hns_roce_v2_qp_context *qpc_mask) 4503 { 4504 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4505 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4506 struct ib_device *ibdev = &hr_dev->ib_dev; 4507 dma_addr_t trrl_ba; 4508 dma_addr_t irrl_ba; 4509 enum ib_mtu ib_mtu; 4510 const u8 *smac; 4511 u8 lp_pktn_ini; 4512 u64 *mtts; 4513 u8 *dmac; 4514 u32 port; 4515 int mtu; 4516 int ret; 4517 4518 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4519 if (ret) { 4520 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4521 return ret; 4522 } 4523 4524 /* Search IRRL's mtts */ 4525 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4526 hr_qp->qpn, &irrl_ba); 4527 if (!mtts) { 4528 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4529 return -EINVAL; 4530 } 4531 4532 /* Search TRRL's mtts */ 4533 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4534 hr_qp->qpn, &trrl_ba); 4535 if (!mtts) { 4536 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4537 return -EINVAL; 4538 } 4539 4540 if (attr_mask & IB_QP_ALT_PATH) { 4541 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4542 attr_mask); 4543 return -EINVAL; 4544 } 4545 4546 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4547 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4548 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4549 qpc_mask->trrl_ba = 0; 4550 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4551 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4552 4553 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4554 qpc_mask->irrl_ba = 0; 4555 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4556 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4557 4558 hr_reg_enable(context, QPC_RMT_E2E); 4559 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4560 4561 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4562 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4563 4564 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4565 4566 smac = (const u8 *)hr_dev->dev_addr[port]; 4567 dmac = (u8 *)attr->ah_attr.roce.dmac; 4568 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4569 if (ether_addr_equal_unaligned(dmac, smac) || 4570 hr_dev->loop_idc == 0x1) { 4571 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4572 hr_reg_clear(qpc_mask, QPC_LBI); 4573 } 4574 4575 if (attr_mask & IB_QP_DEST_QPN) { 4576 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4577 hr_reg_clear(qpc_mask, QPC_DQPN); 4578 } 4579 4580 memcpy(&(context->dmac), dmac, sizeof(u32)); 4581 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4582 qpc_mask->dmac = 0; 4583 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4584 4585 ib_mtu = get_mtu(ibqp, attr); 4586 hr_qp->path_mtu = ib_mtu; 4587 4588 mtu = ib_mtu_enum_to_int(ib_mtu); 4589 if (WARN_ON(mtu <= 0)) 4590 return -EINVAL; 4591 #define MAX_LP_MSG_LEN 16384 4592 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */ 4593 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4594 if (WARN_ON(lp_pktn_ini >= 0xF)) 4595 return -EINVAL; 4596 4597 if (attr_mask & IB_QP_PATH_MTU) { 4598 hr_reg_write(context, QPC_MTU, ib_mtu); 4599 hr_reg_clear(qpc_mask, QPC_MTU); 4600 } 4601 4602 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4603 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4604 4605 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4606 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4607 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4608 4609 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4610 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4611 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4612 4613 context->rq_rnr_timer = 0; 4614 qpc_mask->rq_rnr_timer = 0; 4615 4616 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4617 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4618 4619 /* rocee send 2^lp_sgen_ini segs every time */ 4620 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4621 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4622 4623 return 0; 4624 } 4625 4626 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4627 const struct ib_qp_attr *attr, int attr_mask, 4628 struct hns_roce_v2_qp_context *context, 4629 struct hns_roce_v2_qp_context *qpc_mask) 4630 { 4631 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4632 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4633 struct ib_device *ibdev = &hr_dev->ib_dev; 4634 int ret; 4635 4636 /* Not support alternate path and path migration */ 4637 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4638 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4639 return -EINVAL; 4640 } 4641 4642 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4643 if (ret) { 4644 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4645 return ret; 4646 } 4647 4648 /* 4649 * Set some fields in context to zero, Because the default values 4650 * of all fields in context are zero, we need not set them to 0 again. 4651 * but we should set the relevant fields of context mask to 0. 4652 */ 4653 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4654 4655 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4656 4657 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4658 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4659 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4660 4661 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4662 4663 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4664 4665 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4666 4667 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4668 4669 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4670 4671 return 0; 4672 } 4673 4674 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4675 u32 *dip_idx) 4676 { 4677 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4678 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4679 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4680 u32 *head = &hr_dev->qp_table.idx_table.head; 4681 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4682 struct hns_roce_dip *hr_dip; 4683 unsigned long flags; 4684 int ret = 0; 4685 4686 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4687 4688 spare_idx[*tail] = ibqp->qp_num; 4689 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4690 4691 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4692 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4693 *dip_idx = hr_dip->dip_idx; 4694 goto out; 4695 } 4696 } 4697 4698 /* If no dgid is found, a new dip and a mapping between dgid and 4699 * dip_idx will be created. 4700 */ 4701 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4702 if (!hr_dip) { 4703 ret = -ENOMEM; 4704 goto out; 4705 } 4706 4707 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4708 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4709 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4710 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4711 4712 out: 4713 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4714 return ret; 4715 } 4716 4717 enum { 4718 CONG_DCQCN, 4719 CONG_WINDOW, 4720 }; 4721 4722 enum { 4723 UNSUPPORT_CONG_LEVEL, 4724 SUPPORT_CONG_LEVEL, 4725 }; 4726 4727 enum { 4728 CONG_LDCP, 4729 CONG_HC3, 4730 }; 4731 4732 enum { 4733 DIP_INVALID, 4734 DIP_VALID, 4735 }; 4736 4737 enum { 4738 WND_LIMIT, 4739 WND_UNLIMIT, 4740 }; 4741 4742 static int check_cong_type(struct ib_qp *ibqp, 4743 struct hns_roce_congestion_algorithm *cong_alg) 4744 { 4745 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4746 4747 /* different congestion types match different configurations */ 4748 switch (hr_dev->caps.cong_type) { 4749 case CONG_TYPE_DCQCN: 4750 cong_alg->alg_sel = CONG_DCQCN; 4751 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4752 cong_alg->dip_vld = DIP_INVALID; 4753 cong_alg->wnd_mode_sel = WND_LIMIT; 4754 break; 4755 case CONG_TYPE_LDCP: 4756 cong_alg->alg_sel = CONG_WINDOW; 4757 cong_alg->alg_sub_sel = CONG_LDCP; 4758 cong_alg->dip_vld = DIP_INVALID; 4759 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4760 break; 4761 case CONG_TYPE_HC3: 4762 cong_alg->alg_sel = CONG_WINDOW; 4763 cong_alg->alg_sub_sel = CONG_HC3; 4764 cong_alg->dip_vld = DIP_INVALID; 4765 cong_alg->wnd_mode_sel = WND_LIMIT; 4766 break; 4767 case CONG_TYPE_DIP: 4768 cong_alg->alg_sel = CONG_DCQCN; 4769 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4770 cong_alg->dip_vld = DIP_VALID; 4771 cong_alg->wnd_mode_sel = WND_LIMIT; 4772 break; 4773 default: 4774 ibdev_err(&hr_dev->ib_dev, 4775 "error type(%u) for congestion selection.\n", 4776 hr_dev->caps.cong_type); 4777 return -EINVAL; 4778 } 4779 4780 return 0; 4781 } 4782 4783 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4784 struct hns_roce_v2_qp_context *context, 4785 struct hns_roce_v2_qp_context *qpc_mask) 4786 { 4787 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4788 struct hns_roce_congestion_algorithm cong_field; 4789 struct ib_device *ibdev = ibqp->device; 4790 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4791 u32 dip_idx = 0; 4792 int ret; 4793 4794 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4795 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4796 return 0; 4797 4798 ret = check_cong_type(ibqp, &cong_field); 4799 if (ret) 4800 return ret; 4801 4802 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4803 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4804 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4805 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4806 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4807 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4808 cong_field.alg_sub_sel); 4809 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4810 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4811 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4812 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4813 cong_field.wnd_mode_sel); 4814 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4815 4816 /* if dip is disabled, there is no need to set dip idx */ 4817 if (cong_field.dip_vld == 0) 4818 return 0; 4819 4820 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4821 if (ret) { 4822 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4823 return ret; 4824 } 4825 4826 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4827 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4828 4829 return 0; 4830 } 4831 4832 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4833 const struct ib_qp_attr *attr, 4834 int attr_mask, 4835 struct hns_roce_v2_qp_context *context, 4836 struct hns_roce_v2_qp_context *qpc_mask) 4837 { 4838 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4839 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4840 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4841 struct ib_device *ibdev = &hr_dev->ib_dev; 4842 const struct ib_gid_attr *gid_attr = NULL; 4843 int is_roce_protocol; 4844 u16 vlan_id = 0xffff; 4845 bool is_udp = false; 4846 u8 ib_port; 4847 u8 hr_port; 4848 int ret; 4849 4850 /* 4851 * If free_mr_en of qp is set, it means that this qp comes from 4852 * free mr. This qp will perform the loopback operation. 4853 * In the loopback scenario, only sl needs to be set. 4854 */ 4855 if (hr_qp->free_mr_en) { 4856 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4857 hr_reg_clear(qpc_mask, QPC_SL); 4858 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4859 return 0; 4860 } 4861 4862 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4863 hr_port = ib_port - 1; 4864 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4865 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4866 4867 if (is_roce_protocol) { 4868 gid_attr = attr->ah_attr.grh.sgid_attr; 4869 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4870 if (ret) 4871 return ret; 4872 4873 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4874 } 4875 4876 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4877 if (vlan_id < VLAN_N_VID && 4878 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4879 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4880 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4881 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4882 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4883 } 4884 4885 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4886 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4887 4888 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4889 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4890 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4891 return -EINVAL; 4892 } 4893 4894 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4895 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4896 return -EINVAL; 4897 } 4898 4899 hr_reg_write(context, QPC_UDPSPN, 4900 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4901 attr->dest_qp_num) : 4902 0); 4903 4904 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4905 4906 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4907 4908 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4909 4910 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4911 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4912 4913 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4914 if (ret) 4915 return ret; 4916 4917 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4918 hr_reg_clear(qpc_mask, QPC_TC); 4919 4920 hr_reg_write(context, QPC_FL, grh->flow_label); 4921 hr_reg_clear(qpc_mask, QPC_FL); 4922 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4923 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4924 4925 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4926 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4927 ibdev_err(ibdev, 4928 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 4929 hr_qp->sl, MAX_SERVICE_LEVEL); 4930 return -EINVAL; 4931 } 4932 4933 hr_reg_write(context, QPC_SL, hr_qp->sl); 4934 hr_reg_clear(qpc_mask, QPC_SL); 4935 4936 return 0; 4937 } 4938 4939 static bool check_qp_state(enum ib_qp_state cur_state, 4940 enum ib_qp_state new_state) 4941 { 4942 static const bool sm[][IB_QPS_ERR + 1] = { 4943 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4944 [IB_QPS_INIT] = true }, 4945 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4946 [IB_QPS_INIT] = true, 4947 [IB_QPS_RTR] = true, 4948 [IB_QPS_ERR] = true }, 4949 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4950 [IB_QPS_RTS] = true, 4951 [IB_QPS_ERR] = true }, 4952 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4953 [IB_QPS_RTS] = true, 4954 [IB_QPS_ERR] = true }, 4955 [IB_QPS_SQD] = {}, 4956 [IB_QPS_SQE] = {}, 4957 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4958 [IB_QPS_ERR] = true } 4959 }; 4960 4961 return sm[cur_state][new_state]; 4962 } 4963 4964 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4965 const struct ib_qp_attr *attr, 4966 int attr_mask, 4967 enum ib_qp_state cur_state, 4968 enum ib_qp_state new_state, 4969 struct hns_roce_v2_qp_context *context, 4970 struct hns_roce_v2_qp_context *qpc_mask) 4971 { 4972 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4973 int ret = 0; 4974 4975 if (!check_qp_state(cur_state, new_state)) { 4976 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4977 return -EINVAL; 4978 } 4979 4980 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4981 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4982 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4983 qpc_mask); 4984 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4985 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4986 qpc_mask); 4987 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4988 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4989 qpc_mask); 4990 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4991 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4992 qpc_mask); 4993 } 4994 4995 return ret; 4996 } 4997 4998 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 4999 { 5000 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5001 #define QP_ACK_TIMEOUT_OFFSET 10 5002 #define QP_ACK_TIMEOUT_MAX 31 5003 5004 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5005 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5006 ibdev_warn(&hr_dev->ib_dev, 5007 "Local ACK timeout shall be 0 to 20.\n"); 5008 return false; 5009 } 5010 *timeout += QP_ACK_TIMEOUT_OFFSET; 5011 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5012 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5013 ibdev_warn(&hr_dev->ib_dev, 5014 "Local ACK timeout shall be 0 to 31.\n"); 5015 return false; 5016 } 5017 } 5018 5019 return true; 5020 } 5021 5022 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5023 const struct ib_qp_attr *attr, 5024 int attr_mask, 5025 struct hns_roce_v2_qp_context *context, 5026 struct hns_roce_v2_qp_context *qpc_mask) 5027 { 5028 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5029 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5030 int ret = 0; 5031 u8 timeout; 5032 5033 if (attr_mask & IB_QP_AV) { 5034 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5035 qpc_mask); 5036 if (ret) 5037 return ret; 5038 } 5039 5040 if (attr_mask & IB_QP_TIMEOUT) { 5041 timeout = attr->timeout; 5042 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5043 hr_reg_write(context, QPC_AT, timeout); 5044 hr_reg_clear(qpc_mask, QPC_AT); 5045 } 5046 } 5047 5048 if (attr_mask & IB_QP_RETRY_CNT) { 5049 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5050 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5051 5052 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5053 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5054 } 5055 5056 if (attr_mask & IB_QP_RNR_RETRY) { 5057 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5058 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5059 5060 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5061 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5062 } 5063 5064 if (attr_mask & IB_QP_SQ_PSN) { 5065 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5066 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5067 5068 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5069 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5070 5071 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5072 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5073 5074 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5075 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5076 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5077 5078 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5079 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5080 5081 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5082 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5083 } 5084 5085 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5086 attr->max_dest_rd_atomic) { 5087 hr_reg_write(context, QPC_RR_MAX, 5088 fls(attr->max_dest_rd_atomic - 1)); 5089 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5090 } 5091 5092 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5093 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5094 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5095 } 5096 5097 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5098 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5099 5100 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5101 hr_reg_write(context, QPC_MIN_RNR_TIME, 5102 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5103 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5104 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5105 } 5106 5107 if (attr_mask & IB_QP_RQ_PSN) { 5108 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5109 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5110 5111 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5112 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5113 } 5114 5115 if (attr_mask & IB_QP_QKEY) { 5116 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5117 qpc_mask->qkey_xrcd = 0; 5118 hr_qp->qkey = attr->qkey; 5119 } 5120 5121 return ret; 5122 } 5123 5124 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5125 const struct ib_qp_attr *attr, 5126 int attr_mask) 5127 { 5128 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5129 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5130 5131 if (attr_mask & IB_QP_ACCESS_FLAGS) 5132 hr_qp->atomic_rd_en = attr->qp_access_flags; 5133 5134 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5135 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5136 if (attr_mask & IB_QP_PORT) { 5137 hr_qp->port = attr->port_num - 1; 5138 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5139 } 5140 } 5141 5142 static void clear_qp(struct hns_roce_qp *hr_qp) 5143 { 5144 struct ib_qp *ibqp = &hr_qp->ibqp; 5145 5146 if (ibqp->send_cq) 5147 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5148 hr_qp->qpn, NULL); 5149 5150 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5151 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5152 hr_qp->qpn, ibqp->srq ? 5153 to_hr_srq(ibqp->srq) : NULL); 5154 5155 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5156 *hr_qp->rdb.db_record = 0; 5157 5158 hr_qp->rq.head = 0; 5159 hr_qp->rq.tail = 0; 5160 hr_qp->sq.head = 0; 5161 hr_qp->sq.tail = 0; 5162 hr_qp->next_sge = 0; 5163 } 5164 5165 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5166 struct hns_roce_v2_qp_context *context, 5167 struct hns_roce_v2_qp_context *qpc_mask) 5168 { 5169 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5170 unsigned long sq_flag = 0; 5171 unsigned long rq_flag = 0; 5172 5173 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5174 return; 5175 5176 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5177 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5178 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5179 hr_qp->state = IB_QPS_ERR; 5180 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5181 5182 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5183 return; 5184 5185 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5186 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5187 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5188 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5189 } 5190 5191 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5192 const struct ib_qp_attr *attr, 5193 int attr_mask, enum ib_qp_state cur_state, 5194 enum ib_qp_state new_state) 5195 { 5196 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5197 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5198 struct hns_roce_v2_qp_context ctx[2]; 5199 struct hns_roce_v2_qp_context *context = ctx; 5200 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5201 struct ib_device *ibdev = &hr_dev->ib_dev; 5202 int ret; 5203 5204 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5205 return -EOPNOTSUPP; 5206 5207 /* 5208 * In v2 engine, software pass context and context mask to hardware 5209 * when modifying qp. If software need modify some fields in context, 5210 * we should set all bits of the relevant fields in context mask to 5211 * 0 at the same time, else set them to 0x1. 5212 */ 5213 memset(context, 0, hr_dev->caps.qpc_sz); 5214 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5215 5216 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5217 new_state, context, qpc_mask); 5218 if (ret) 5219 goto out; 5220 5221 /* When QP state is err, SQ and RQ WQE should be flushed */ 5222 if (new_state == IB_QPS_ERR) 5223 v2_set_flushed_fields(ibqp, context, qpc_mask); 5224 5225 /* Configure the optional fields */ 5226 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5227 qpc_mask); 5228 if (ret) 5229 goto out; 5230 5231 hr_reg_write_bool(context, QPC_INV_CREDIT, 5232 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5233 ibqp->srq); 5234 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5235 5236 /* Every status migrate must change state */ 5237 hr_reg_write(context, QPC_QP_ST, new_state); 5238 hr_reg_clear(qpc_mask, QPC_QP_ST); 5239 5240 /* SW pass context to HW */ 5241 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5242 if (ret) { 5243 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5244 goto out; 5245 } 5246 5247 hr_qp->state = new_state; 5248 5249 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5250 5251 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5252 clear_qp(hr_qp); 5253 5254 out: 5255 return ret; 5256 } 5257 5258 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5259 { 5260 static const enum ib_qp_state map[] = { 5261 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5262 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5263 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5264 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5265 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5266 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5267 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5268 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5269 }; 5270 5271 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5272 } 5273 5274 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 5275 struct hns_roce_qp *hr_qp, 5276 struct hns_roce_v2_qp_context *hr_context) 5277 { 5278 struct hns_roce_cmd_mailbox *mailbox; 5279 int ret; 5280 5281 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5282 if (IS_ERR(mailbox)) 5283 return PTR_ERR(mailbox); 5284 5285 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5286 hr_qp->qpn); 5287 if (ret) 5288 goto out; 5289 5290 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz); 5291 5292 out: 5293 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5294 return ret; 5295 } 5296 5297 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5298 int qp_attr_mask, 5299 struct ib_qp_init_attr *qp_init_attr) 5300 { 5301 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5302 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5303 struct hns_roce_v2_qp_context context = {}; 5304 struct ib_device *ibdev = &hr_dev->ib_dev; 5305 int tmp_qp_state; 5306 int state; 5307 int ret; 5308 5309 memset(qp_attr, 0, sizeof(*qp_attr)); 5310 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5311 5312 mutex_lock(&hr_qp->mutex); 5313 5314 if (hr_qp->state == IB_QPS_RESET) { 5315 qp_attr->qp_state = IB_QPS_RESET; 5316 ret = 0; 5317 goto done; 5318 } 5319 5320 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 5321 if (ret) { 5322 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5323 ret = -EINVAL; 5324 goto out; 5325 } 5326 5327 state = hr_reg_read(&context, QPC_QP_ST); 5328 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5329 if (tmp_qp_state == -1) { 5330 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5331 ret = -EINVAL; 5332 goto out; 5333 } 5334 hr_qp->state = (u8)tmp_qp_state; 5335 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5336 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5337 qp_attr->path_mig_state = IB_MIG_ARMED; 5338 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5339 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5340 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5341 5342 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5343 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5344 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5345 qp_attr->qp_access_flags = 5346 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5347 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5348 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5349 5350 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5351 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5352 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5353 struct ib_global_route *grh = 5354 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5355 5356 rdma_ah_set_sl(&qp_attr->ah_attr, 5357 hr_reg_read(&context, QPC_SL)); 5358 grh->flow_label = hr_reg_read(&context, QPC_FL); 5359 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5360 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5361 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5362 5363 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5364 } 5365 5366 qp_attr->port_num = hr_qp->port + 1; 5367 qp_attr->sq_draining = 0; 5368 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5369 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5370 5371 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5372 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5373 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5374 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5375 5376 done: 5377 qp_attr->cur_qp_state = qp_attr->qp_state; 5378 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5379 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5380 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5381 5382 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5383 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5384 5385 qp_init_attr->qp_context = ibqp->qp_context; 5386 qp_init_attr->qp_type = ibqp->qp_type; 5387 qp_init_attr->recv_cq = ibqp->recv_cq; 5388 qp_init_attr->send_cq = ibqp->send_cq; 5389 qp_init_attr->srq = ibqp->srq; 5390 qp_init_attr->cap = qp_attr->cap; 5391 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5392 5393 out: 5394 mutex_unlock(&hr_qp->mutex); 5395 return ret; 5396 } 5397 5398 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5399 { 5400 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5401 hr_qp->ibqp.qp_type == IB_QPT_UD || 5402 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5403 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5404 hr_qp->state != IB_QPS_RESET); 5405 } 5406 5407 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5408 struct hns_roce_qp *hr_qp, 5409 struct ib_udata *udata) 5410 { 5411 struct ib_device *ibdev = &hr_dev->ib_dev; 5412 struct hns_roce_cq *send_cq, *recv_cq; 5413 unsigned long flags; 5414 int ret = 0; 5415 5416 if (modify_qp_is_ok(hr_qp)) { 5417 /* Modify qp to reset before destroying qp */ 5418 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5419 hr_qp->state, IB_QPS_RESET); 5420 if (ret) 5421 ibdev_err(ibdev, 5422 "failed to modify QP to RST, ret = %d.\n", 5423 ret); 5424 } 5425 5426 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5427 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5428 5429 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5430 hns_roce_lock_cqs(send_cq, recv_cq); 5431 5432 if (!udata) { 5433 if (recv_cq) 5434 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5435 (hr_qp->ibqp.srq ? 5436 to_hr_srq(hr_qp->ibqp.srq) : 5437 NULL)); 5438 5439 if (send_cq && send_cq != recv_cq) 5440 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5441 } 5442 5443 hns_roce_qp_remove(hr_dev, hr_qp); 5444 5445 hns_roce_unlock_cqs(send_cq, recv_cq); 5446 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5447 5448 return ret; 5449 } 5450 5451 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5452 { 5453 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5454 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5455 int ret; 5456 5457 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5458 if (ret) 5459 ibdev_err(&hr_dev->ib_dev, 5460 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5461 hr_qp->qpn, ret); 5462 5463 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5464 5465 return 0; 5466 } 5467 5468 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5469 struct hns_roce_qp *hr_qp) 5470 { 5471 struct ib_device *ibdev = &hr_dev->ib_dev; 5472 struct hns_roce_sccc_clr_done *resp; 5473 struct hns_roce_sccc_clr *clr; 5474 struct hns_roce_cmq_desc desc; 5475 int ret, i; 5476 5477 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5478 return 0; 5479 5480 mutex_lock(&hr_dev->qp_table.scc_mutex); 5481 5482 /* set scc ctx clear done flag */ 5483 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5484 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5485 if (ret) { 5486 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5487 goto out; 5488 } 5489 5490 /* clear scc context */ 5491 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5492 clr = (struct hns_roce_sccc_clr *)desc.data; 5493 clr->qpn = cpu_to_le32(hr_qp->qpn); 5494 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5495 if (ret) { 5496 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5497 goto out; 5498 } 5499 5500 /* query scc context clear is done or not */ 5501 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5502 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5503 hns_roce_cmq_setup_basic_desc(&desc, 5504 HNS_ROCE_OPC_QUERY_SCCC, true); 5505 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5506 if (ret) { 5507 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5508 ret); 5509 goto out; 5510 } 5511 5512 if (resp->clr_done) 5513 goto out; 5514 5515 msleep(20); 5516 } 5517 5518 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 5519 ret = -ETIMEDOUT; 5520 5521 out: 5522 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5523 return ret; 5524 } 5525 5526 #define DMA_IDX_SHIFT 3 5527 #define DMA_WQE_SHIFT 3 5528 5529 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5530 struct hns_roce_srq_context *ctx) 5531 { 5532 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5533 struct ib_device *ibdev = srq->ibsrq.device; 5534 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5535 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5536 dma_addr_t dma_handle_idx = 0; 5537 int ret; 5538 5539 /* Get physical address of idx que buf */ 5540 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5541 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5542 if (ret < 1) { 5543 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5544 ret); 5545 return -ENOBUFS; 5546 } 5547 5548 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5549 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5550 5551 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5552 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5553 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5554 5555 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5556 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5557 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5558 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5559 5560 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5561 to_hr_hw_page_addr(mtts_idx[0])); 5562 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5563 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5564 5565 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5566 to_hr_hw_page_addr(mtts_idx[1])); 5567 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5568 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5569 5570 return 0; 5571 } 5572 5573 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5574 { 5575 struct ib_device *ibdev = srq->ibsrq.device; 5576 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5577 struct hns_roce_srq_context *ctx = mb_buf; 5578 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5579 dma_addr_t dma_handle_wqe = 0; 5580 int ret; 5581 5582 memset(ctx, 0, sizeof(*ctx)); 5583 5584 /* Get the physical address of srq buf */ 5585 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5586 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5587 if (ret < 1) { 5588 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5589 ret); 5590 return -ENOBUFS; 5591 } 5592 5593 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5594 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5595 srq->ibsrq.srq_type == IB_SRQT_XRC); 5596 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5597 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5598 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5599 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5600 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5601 hr_reg_write(ctx, SRQC_RQWS, 5602 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5603 5604 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5605 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5606 srq->wqe_cnt)); 5607 5608 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5609 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5610 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5611 5612 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5613 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5614 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5615 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5616 5617 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5618 } 5619 5620 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5621 struct ib_srq_attr *srq_attr, 5622 enum ib_srq_attr_mask srq_attr_mask, 5623 struct ib_udata *udata) 5624 { 5625 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5626 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5627 struct hns_roce_srq_context *srq_context; 5628 struct hns_roce_srq_context *srqc_mask; 5629 struct hns_roce_cmd_mailbox *mailbox; 5630 int ret; 5631 5632 /* Resizing SRQs is not supported yet */ 5633 if (srq_attr_mask & IB_SRQ_MAX_WR) 5634 return -EINVAL; 5635 5636 if (srq_attr_mask & IB_SRQ_LIMIT) { 5637 if (srq_attr->srq_limit > srq->wqe_cnt) 5638 return -EINVAL; 5639 5640 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5641 if (IS_ERR(mailbox)) 5642 return PTR_ERR(mailbox); 5643 5644 srq_context = mailbox->buf; 5645 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5646 5647 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5648 5649 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5650 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5651 5652 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5653 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5654 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5655 if (ret) { 5656 ibdev_err(&hr_dev->ib_dev, 5657 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5658 ret); 5659 return ret; 5660 } 5661 } 5662 5663 return 0; 5664 } 5665 5666 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5667 { 5668 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5669 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5670 struct hns_roce_srq_context *srq_context; 5671 struct hns_roce_cmd_mailbox *mailbox; 5672 int ret; 5673 5674 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5675 if (IS_ERR(mailbox)) 5676 return PTR_ERR(mailbox); 5677 5678 srq_context = mailbox->buf; 5679 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5680 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5681 if (ret) { 5682 ibdev_err(&hr_dev->ib_dev, 5683 "failed to process cmd of querying SRQ, ret = %d.\n", 5684 ret); 5685 goto out; 5686 } 5687 5688 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5689 attr->max_wr = srq->wqe_cnt; 5690 attr->max_sge = srq->max_gs - srq->rsv_sge; 5691 5692 out: 5693 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5694 return ret; 5695 } 5696 5697 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5698 { 5699 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5700 struct hns_roce_v2_cq_context *cq_context; 5701 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5702 struct hns_roce_v2_cq_context *cqc_mask; 5703 struct hns_roce_cmd_mailbox *mailbox; 5704 int ret; 5705 5706 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5707 if (IS_ERR(mailbox)) 5708 return PTR_ERR(mailbox); 5709 5710 cq_context = mailbox->buf; 5711 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5712 5713 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5714 5715 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5716 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5717 5718 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5719 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5720 dev_info(hr_dev->dev, 5721 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5722 cq_period); 5723 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5724 } 5725 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5726 } 5727 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5728 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5729 5730 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5731 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5732 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5733 if (ret) 5734 ibdev_err(&hr_dev->ib_dev, 5735 "failed to process cmd when modifying CQ, ret = %d.\n", 5736 ret); 5737 5738 return ret; 5739 } 5740 5741 static void hns_roce_irq_work_handle(struct work_struct *work) 5742 { 5743 struct hns_roce_work *irq_work = 5744 container_of(work, struct hns_roce_work, work); 5745 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5746 5747 switch (irq_work->event_type) { 5748 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5749 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5750 break; 5751 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5752 ibdev_warn(ibdev, "Path migration failed.\n"); 5753 break; 5754 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5755 break; 5756 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5757 ibdev_warn(ibdev, "Send queue drained.\n"); 5758 break; 5759 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5760 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5761 irq_work->queue_num, irq_work->sub_type); 5762 break; 5763 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5764 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5765 irq_work->queue_num); 5766 break; 5767 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5768 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5769 irq_work->queue_num, irq_work->sub_type); 5770 break; 5771 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5772 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5773 break; 5774 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5775 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5776 break; 5777 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5778 ibdev_err(ibdev, "SRQ catas error.\n"); 5779 break; 5780 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5781 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5782 break; 5783 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5784 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5785 break; 5786 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5787 ibdev_warn(ibdev, "DB overflow.\n"); 5788 break; 5789 case HNS_ROCE_EVENT_TYPE_FLR: 5790 ibdev_warn(ibdev, "Function level reset.\n"); 5791 break; 5792 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5793 ibdev_err(ibdev, "xrc domain violation error.\n"); 5794 break; 5795 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5796 ibdev_err(ibdev, "invalid xrceth error.\n"); 5797 break; 5798 default: 5799 break; 5800 } 5801 5802 kfree(irq_work); 5803 } 5804 5805 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5806 struct hns_roce_eq *eq, u32 queue_num) 5807 { 5808 struct hns_roce_work *irq_work; 5809 5810 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5811 if (!irq_work) 5812 return; 5813 5814 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5815 irq_work->hr_dev = hr_dev; 5816 irq_work->event_type = eq->event_type; 5817 irq_work->sub_type = eq->sub_type; 5818 irq_work->queue_num = queue_num; 5819 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5820 } 5821 5822 static void update_eq_db(struct hns_roce_eq *eq) 5823 { 5824 struct hns_roce_dev *hr_dev = eq->hr_dev; 5825 struct hns_roce_v2_db eq_db = {}; 5826 5827 if (eq->type_flag == HNS_ROCE_AEQ) { 5828 hr_reg_write(&eq_db, EQ_DB_CMD, 5829 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5830 HNS_ROCE_EQ_DB_CMD_AEQ : 5831 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5832 } else { 5833 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5834 5835 hr_reg_write(&eq_db, EQ_DB_CMD, 5836 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5837 HNS_ROCE_EQ_DB_CMD_CEQ : 5838 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5839 } 5840 5841 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5842 5843 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5844 } 5845 5846 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5847 { 5848 struct hns_roce_aeqe *aeqe; 5849 5850 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5851 (eq->cons_index & (eq->entries - 1)) * 5852 eq->eqe_size); 5853 5854 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5855 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5856 } 5857 5858 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5859 struct hns_roce_eq *eq) 5860 { 5861 struct device *dev = hr_dev->dev; 5862 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5863 int aeqe_found = 0; 5864 int event_type; 5865 u32 queue_num; 5866 int sub_type; 5867 5868 while (aeqe) { 5869 /* Make sure we read AEQ entry after we have checked the 5870 * ownership bit 5871 */ 5872 dma_rmb(); 5873 5874 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5875 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5876 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5877 5878 switch (event_type) { 5879 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5880 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5881 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5882 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5883 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5884 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5885 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5886 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5887 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5888 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5889 hns_roce_qp_event(hr_dev, queue_num, event_type); 5890 break; 5891 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5892 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5893 hns_roce_srq_event(hr_dev, queue_num, event_type); 5894 break; 5895 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5896 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5897 hns_roce_cq_event(hr_dev, queue_num, event_type); 5898 break; 5899 case HNS_ROCE_EVENT_TYPE_MB: 5900 hns_roce_cmd_event(hr_dev, 5901 le16_to_cpu(aeqe->event.cmd.token), 5902 aeqe->event.cmd.status, 5903 le64_to_cpu(aeqe->event.cmd.out_param)); 5904 break; 5905 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5906 case HNS_ROCE_EVENT_TYPE_FLR: 5907 break; 5908 default: 5909 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5910 event_type, eq->eqn, eq->cons_index); 5911 break; 5912 } 5913 5914 eq->event_type = event_type; 5915 eq->sub_type = sub_type; 5916 ++eq->cons_index; 5917 aeqe_found = 1; 5918 5919 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5920 5921 aeqe = next_aeqe_sw_v2(eq); 5922 } 5923 5924 update_eq_db(eq); 5925 return aeqe_found; 5926 } 5927 5928 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5929 { 5930 struct hns_roce_ceqe *ceqe; 5931 5932 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5933 (eq->cons_index & (eq->entries - 1)) * 5934 eq->eqe_size); 5935 5936 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 5937 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5938 } 5939 5940 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5941 struct hns_roce_eq *eq) 5942 { 5943 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5944 int ceqe_found = 0; 5945 u32 cqn; 5946 5947 while (ceqe) { 5948 /* Make sure we read CEQ entry after we have checked the 5949 * ownership bit 5950 */ 5951 dma_rmb(); 5952 5953 cqn = hr_reg_read(ceqe, CEQE_CQN); 5954 5955 hns_roce_cq_completion(hr_dev, cqn); 5956 5957 ++eq->cons_index; 5958 ceqe_found = 1; 5959 5960 ceqe = next_ceqe_sw_v2(eq); 5961 } 5962 5963 update_eq_db(eq); 5964 5965 return ceqe_found; 5966 } 5967 5968 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5969 { 5970 struct hns_roce_eq *eq = eq_ptr; 5971 struct hns_roce_dev *hr_dev = eq->hr_dev; 5972 int int_work; 5973 5974 if (eq->type_flag == HNS_ROCE_CEQ) 5975 /* Completion event interrupt */ 5976 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5977 else 5978 /* Asychronous event interrupt */ 5979 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5980 5981 return IRQ_RETVAL(int_work); 5982 } 5983 5984 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5985 { 5986 struct hns_roce_dev *hr_dev = dev_id; 5987 struct device *dev = hr_dev->dev; 5988 int int_work = 0; 5989 u32 int_st; 5990 u32 int_en; 5991 5992 /* Abnormal interrupt */ 5993 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5994 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5995 5996 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5997 struct pci_dev *pdev = hr_dev->pci_dev; 5998 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5999 const struct hnae3_ae_ops *ops = ae_dev->ops; 6000 6001 dev_err(dev, "AEQ overflow!\n"); 6002 6003 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 6004 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 6005 6006 /* Set reset level for reset_event() */ 6007 if (ops->set_default_reset_request) 6008 ops->set_default_reset_request(ae_dev, 6009 HNAE3_FUNC_RESET); 6010 if (ops->reset_event) 6011 ops->reset_event(pdev, NULL); 6012 6013 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6014 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6015 6016 int_work = 1; 6017 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) { 6018 dev_err(dev, "RAS interrupt!\n"); 6019 6020 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S; 6021 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 6022 6023 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6024 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6025 6026 int_work = 1; 6027 } else { 6028 dev_err(dev, "There is no abnormal irq found!\n"); 6029 } 6030 6031 return IRQ_RETVAL(int_work); 6032 } 6033 6034 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6035 int eq_num, u32 enable_flag) 6036 { 6037 int i; 6038 6039 for (i = 0; i < eq_num; i++) 6040 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6041 i * EQ_REG_OFFSET, enable_flag); 6042 6043 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6044 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6045 } 6046 6047 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6048 { 6049 struct device *dev = hr_dev->dev; 6050 int ret; 6051 u8 cmd; 6052 6053 if (eqn < hr_dev->caps.num_comp_vectors) 6054 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6055 else 6056 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6057 6058 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6059 if (ret) 6060 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6061 } 6062 6063 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6064 { 6065 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6066 } 6067 6068 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6069 { 6070 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6071 eq->cons_index = 0; 6072 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6073 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6074 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6075 eq->shift = ilog2((unsigned int)eq->entries); 6076 } 6077 6078 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6079 void *mb_buf) 6080 { 6081 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6082 struct hns_roce_eq_context *eqc; 6083 u64 bt_ba = 0; 6084 int count; 6085 6086 eqc = mb_buf; 6087 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6088 6089 init_eq_config(hr_dev, eq); 6090 6091 /* if not multi-hop, eqe buffer only use one trunk */ 6092 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6093 &bt_ba); 6094 if (count < 1) { 6095 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6096 return -ENOBUFS; 6097 } 6098 6099 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6100 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6101 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6102 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6103 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6104 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6105 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6106 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6107 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6108 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6109 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6110 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6111 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6112 6113 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6114 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6115 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6116 eq->eq_period); 6117 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6118 } 6119 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6120 } 6121 6122 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6123 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6124 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6125 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6126 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6127 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6128 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6129 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6130 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6131 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6132 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6133 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6134 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6135 6136 return 0; 6137 } 6138 6139 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6140 { 6141 struct hns_roce_buf_attr buf_attr = {}; 6142 int err; 6143 6144 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6145 eq->hop_num = 0; 6146 else 6147 eq->hop_num = hr_dev->caps.eqe_hop_num; 6148 6149 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6150 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6151 buf_attr.region[0].hopnum = eq->hop_num; 6152 buf_attr.region_count = 1; 6153 6154 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6155 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6156 0); 6157 if (err) 6158 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 6159 6160 return err; 6161 } 6162 6163 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6164 struct hns_roce_eq *eq, u8 eq_cmd) 6165 { 6166 struct hns_roce_cmd_mailbox *mailbox; 6167 int ret; 6168 6169 /* Allocate mailbox memory */ 6170 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6171 if (IS_ERR(mailbox)) 6172 return PTR_ERR(mailbox); 6173 6174 ret = alloc_eq_buf(hr_dev, eq); 6175 if (ret) 6176 goto free_cmd_mbox; 6177 6178 ret = config_eqc(hr_dev, eq, mailbox->buf); 6179 if (ret) 6180 goto err_cmd_mbox; 6181 6182 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6183 if (ret) { 6184 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6185 goto err_cmd_mbox; 6186 } 6187 6188 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6189 6190 return 0; 6191 6192 err_cmd_mbox: 6193 free_eq_buf(hr_dev, eq); 6194 6195 free_cmd_mbox: 6196 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6197 6198 return ret; 6199 } 6200 6201 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6202 int comp_num, int aeq_num, int other_num) 6203 { 6204 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6205 int i, j; 6206 int ret; 6207 6208 for (i = 0; i < irq_num; i++) { 6209 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6210 GFP_KERNEL); 6211 if (!hr_dev->irq_names[i]) { 6212 ret = -ENOMEM; 6213 goto err_kzalloc_failed; 6214 } 6215 } 6216 6217 /* irq contains: abnormal + AEQ + CEQ */ 6218 for (j = 0; j < other_num; j++) 6219 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6220 "hns-abn-%d", j); 6221 6222 for (j = other_num; j < (other_num + aeq_num); j++) 6223 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6224 "hns-aeq-%d", j - other_num); 6225 6226 for (j = (other_num + aeq_num); j < irq_num; j++) 6227 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6228 "hns-ceq-%d", j - other_num - aeq_num); 6229 6230 for (j = 0; j < irq_num; j++) { 6231 if (j < other_num) 6232 ret = request_irq(hr_dev->irq[j], 6233 hns_roce_v2_msix_interrupt_abn, 6234 0, hr_dev->irq_names[j], hr_dev); 6235 6236 else if (j < (other_num + comp_num)) 6237 ret = request_irq(eq_table->eq[j - other_num].irq, 6238 hns_roce_v2_msix_interrupt_eq, 6239 0, hr_dev->irq_names[j + aeq_num], 6240 &eq_table->eq[j - other_num]); 6241 else 6242 ret = request_irq(eq_table->eq[j - other_num].irq, 6243 hns_roce_v2_msix_interrupt_eq, 6244 0, hr_dev->irq_names[j - comp_num], 6245 &eq_table->eq[j - other_num]); 6246 if (ret) { 6247 dev_err(hr_dev->dev, "Request irq error!\n"); 6248 goto err_request_failed; 6249 } 6250 } 6251 6252 return 0; 6253 6254 err_request_failed: 6255 for (j -= 1; j >= 0; j--) 6256 if (j < other_num) 6257 free_irq(hr_dev->irq[j], hr_dev); 6258 else 6259 free_irq(eq_table->eq[j - other_num].irq, 6260 &eq_table->eq[j - other_num]); 6261 6262 err_kzalloc_failed: 6263 for (i -= 1; i >= 0; i--) 6264 kfree(hr_dev->irq_names[i]); 6265 6266 return ret; 6267 } 6268 6269 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6270 { 6271 int irq_num; 6272 int eq_num; 6273 int i; 6274 6275 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6276 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6277 6278 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6279 free_irq(hr_dev->irq[i], hr_dev); 6280 6281 for (i = 0; i < eq_num; i++) 6282 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6283 6284 for (i = 0; i < irq_num; i++) 6285 kfree(hr_dev->irq_names[i]); 6286 } 6287 6288 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6289 { 6290 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6291 struct device *dev = hr_dev->dev; 6292 struct hns_roce_eq *eq; 6293 int other_num; 6294 int comp_num; 6295 int aeq_num; 6296 int irq_num; 6297 int eq_num; 6298 u8 eq_cmd; 6299 int ret; 6300 int i; 6301 6302 other_num = hr_dev->caps.num_other_vectors; 6303 comp_num = hr_dev->caps.num_comp_vectors; 6304 aeq_num = hr_dev->caps.num_aeq_vectors; 6305 6306 eq_num = comp_num + aeq_num; 6307 irq_num = eq_num + other_num; 6308 6309 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6310 if (!eq_table->eq) 6311 return -ENOMEM; 6312 6313 /* create eq */ 6314 for (i = 0; i < eq_num; i++) { 6315 eq = &eq_table->eq[i]; 6316 eq->hr_dev = hr_dev; 6317 eq->eqn = i; 6318 if (i < comp_num) { 6319 /* CEQ */ 6320 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6321 eq->type_flag = HNS_ROCE_CEQ; 6322 eq->entries = hr_dev->caps.ceqe_depth; 6323 eq->eqe_size = hr_dev->caps.ceqe_size; 6324 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6325 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6326 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6327 } else { 6328 /* AEQ */ 6329 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6330 eq->type_flag = HNS_ROCE_AEQ; 6331 eq->entries = hr_dev->caps.aeqe_depth; 6332 eq->eqe_size = hr_dev->caps.aeqe_size; 6333 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6334 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6335 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6336 } 6337 6338 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6339 if (ret) { 6340 dev_err(dev, "failed to create eq.\n"); 6341 goto err_create_eq_fail; 6342 } 6343 } 6344 6345 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6346 if (!hr_dev->irq_workq) { 6347 dev_err(dev, "failed to create irq workqueue.\n"); 6348 ret = -ENOMEM; 6349 goto err_create_eq_fail; 6350 } 6351 6352 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6353 other_num); 6354 if (ret) { 6355 dev_err(dev, "failed to request irq.\n"); 6356 goto err_request_irq_fail; 6357 } 6358 6359 /* enable irq */ 6360 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6361 6362 return 0; 6363 6364 err_request_irq_fail: 6365 destroy_workqueue(hr_dev->irq_workq); 6366 6367 err_create_eq_fail: 6368 for (i -= 1; i >= 0; i--) 6369 free_eq_buf(hr_dev, &eq_table->eq[i]); 6370 kfree(eq_table->eq); 6371 6372 return ret; 6373 } 6374 6375 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6376 { 6377 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6378 int eq_num; 6379 int i; 6380 6381 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6382 6383 /* Disable irq */ 6384 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6385 6386 __hns_roce_free_irq(hr_dev); 6387 destroy_workqueue(hr_dev->irq_workq); 6388 6389 for (i = 0; i < eq_num; i++) { 6390 hns_roce_v2_destroy_eqc(hr_dev, i); 6391 6392 free_eq_buf(hr_dev, &eq_table->eq[i]); 6393 } 6394 6395 kfree(eq_table->eq); 6396 } 6397 6398 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 6399 .query_cqc_info = hns_roce_v2_query_cqc_info, 6400 }; 6401 6402 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6403 .destroy_qp = hns_roce_v2_destroy_qp, 6404 .modify_cq = hns_roce_v2_modify_cq, 6405 .poll_cq = hns_roce_v2_poll_cq, 6406 .post_recv = hns_roce_v2_post_recv, 6407 .post_send = hns_roce_v2_post_send, 6408 .query_qp = hns_roce_v2_query_qp, 6409 .req_notify_cq = hns_roce_v2_req_notify_cq, 6410 }; 6411 6412 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6413 .modify_srq = hns_roce_v2_modify_srq, 6414 .post_srq_recv = hns_roce_v2_post_srq_recv, 6415 .query_srq = hns_roce_v2_query_srq, 6416 }; 6417 6418 static const struct hns_roce_hw hns_roce_hw_v2 = { 6419 .cmq_init = hns_roce_v2_cmq_init, 6420 .cmq_exit = hns_roce_v2_cmq_exit, 6421 .hw_profile = hns_roce_v2_profile, 6422 .hw_init = hns_roce_v2_init, 6423 .hw_exit = hns_roce_v2_exit, 6424 .post_mbox = v2_post_mbox, 6425 .poll_mbox_done = v2_poll_mbox_done, 6426 .chk_mbox_avail = v2_chk_mbox_is_avail, 6427 .set_gid = hns_roce_v2_set_gid, 6428 .set_mac = hns_roce_v2_set_mac, 6429 .write_mtpt = hns_roce_v2_write_mtpt, 6430 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6431 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6432 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6433 .write_cqc = hns_roce_v2_write_cqc, 6434 .set_hem = hns_roce_v2_set_hem, 6435 .clear_hem = hns_roce_v2_clear_hem, 6436 .modify_qp = hns_roce_v2_modify_qp, 6437 .dereg_mr = hns_roce_v2_dereg_mr, 6438 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6439 .init_eq = hns_roce_v2_init_eq_table, 6440 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6441 .write_srqc = hns_roce_v2_write_srqc, 6442 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6443 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6444 }; 6445 6446 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6447 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6448 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6449 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6450 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6451 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6452 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6453 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6454 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6455 /* required last entry */ 6456 {0, } 6457 }; 6458 6459 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6460 6461 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6462 struct hnae3_handle *handle) 6463 { 6464 struct hns_roce_v2_priv *priv = hr_dev->priv; 6465 const struct pci_device_id *id; 6466 int i; 6467 6468 hr_dev->pci_dev = handle->pdev; 6469 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6470 hr_dev->is_vf = id->driver_data; 6471 hr_dev->dev = &handle->pdev->dev; 6472 hr_dev->hw = &hns_roce_hw_v2; 6473 hr_dev->dfx = &hns_roce_dfx_hw_v2; 6474 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6475 hr_dev->odb_offset = hr_dev->sdb_offset; 6476 6477 /* Get info from NIC driver. */ 6478 hr_dev->reg_base = handle->rinfo.roce_io_base; 6479 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6480 hr_dev->caps.num_ports = 1; 6481 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6482 hr_dev->iboe.phy_port[0] = 0; 6483 6484 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6485 hr_dev->iboe.netdevs[0]->dev_addr); 6486 6487 for (i = 0; i < handle->rinfo.num_vectors; i++) 6488 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6489 i + handle->rinfo.base_vector); 6490 6491 /* cmd issue mode: 0 is poll, 1 is event */ 6492 hr_dev->cmd_mod = 1; 6493 hr_dev->loop_idc = 0; 6494 6495 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6496 priv->handle = handle; 6497 } 6498 6499 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6500 { 6501 struct hns_roce_dev *hr_dev; 6502 int ret; 6503 6504 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6505 if (!hr_dev) 6506 return -ENOMEM; 6507 6508 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6509 if (!hr_dev->priv) { 6510 ret = -ENOMEM; 6511 goto error_failed_kzalloc; 6512 } 6513 6514 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6515 6516 ret = hns_roce_init(hr_dev); 6517 if (ret) { 6518 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6519 goto error_failed_cfg; 6520 } 6521 6522 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6523 ret = free_mr_init(hr_dev); 6524 if (ret) { 6525 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6526 goto error_failed_roce_init; 6527 } 6528 } 6529 6530 handle->priv = hr_dev; 6531 6532 return 0; 6533 6534 error_failed_roce_init: 6535 hns_roce_exit(hr_dev); 6536 6537 error_failed_cfg: 6538 kfree(hr_dev->priv); 6539 6540 error_failed_kzalloc: 6541 ib_dealloc_device(&hr_dev->ib_dev); 6542 6543 return ret; 6544 } 6545 6546 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6547 bool reset) 6548 { 6549 struct hns_roce_dev *hr_dev = handle->priv; 6550 6551 if (!hr_dev) 6552 return; 6553 6554 handle->priv = NULL; 6555 6556 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6557 hns_roce_handle_device_err(hr_dev); 6558 6559 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6560 free_mr_exit(hr_dev); 6561 6562 hns_roce_exit(hr_dev); 6563 kfree(hr_dev->priv); 6564 ib_dealloc_device(&hr_dev->ib_dev); 6565 } 6566 6567 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6568 { 6569 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6570 const struct pci_device_id *id; 6571 struct device *dev = &handle->pdev->dev; 6572 int ret; 6573 6574 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6575 6576 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6577 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6578 goto reset_chk_err; 6579 } 6580 6581 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6582 if (!id) 6583 return 0; 6584 6585 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6586 return 0; 6587 6588 ret = __hns_roce_hw_v2_init_instance(handle); 6589 if (ret) { 6590 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6591 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6592 if (ops->ae_dev_resetting(handle) || 6593 ops->get_hw_reset_stat(handle)) 6594 goto reset_chk_err; 6595 else 6596 return ret; 6597 } 6598 6599 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6600 6601 return 0; 6602 6603 reset_chk_err: 6604 dev_err(dev, "Device is busy in resetting state.\n" 6605 "please retry later.\n"); 6606 6607 return -EBUSY; 6608 } 6609 6610 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6611 bool reset) 6612 { 6613 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6614 return; 6615 6616 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6617 6618 __hns_roce_hw_v2_uninit_instance(handle, reset); 6619 6620 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6621 } 6622 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6623 { 6624 struct hns_roce_dev *hr_dev; 6625 6626 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6627 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6628 return 0; 6629 } 6630 6631 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6632 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6633 6634 hr_dev = handle->priv; 6635 if (!hr_dev) 6636 return 0; 6637 6638 hr_dev->active = false; 6639 hr_dev->dis_db = true; 6640 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6641 6642 return 0; 6643 } 6644 6645 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6646 { 6647 struct device *dev = &handle->pdev->dev; 6648 int ret; 6649 6650 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6651 &handle->rinfo.state)) { 6652 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6653 return 0; 6654 } 6655 6656 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6657 6658 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6659 ret = __hns_roce_hw_v2_init_instance(handle); 6660 if (ret) { 6661 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6662 * callback function, RoCE Engine reinitialize. If RoCE reinit 6663 * failed, we should inform NIC driver. 6664 */ 6665 handle->priv = NULL; 6666 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6667 } else { 6668 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6669 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6670 } 6671 6672 return ret; 6673 } 6674 6675 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6676 { 6677 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6678 return 0; 6679 6680 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6681 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6682 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6683 __hns_roce_hw_v2_uninit_instance(handle, false); 6684 6685 return 0; 6686 } 6687 6688 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6689 enum hnae3_reset_notify_type type) 6690 { 6691 int ret = 0; 6692 6693 switch (type) { 6694 case HNAE3_DOWN_CLIENT: 6695 ret = hns_roce_hw_v2_reset_notify_down(handle); 6696 break; 6697 case HNAE3_INIT_CLIENT: 6698 ret = hns_roce_hw_v2_reset_notify_init(handle); 6699 break; 6700 case HNAE3_UNINIT_CLIENT: 6701 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6702 break; 6703 default: 6704 break; 6705 } 6706 6707 return ret; 6708 } 6709 6710 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6711 .init_instance = hns_roce_hw_v2_init_instance, 6712 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6713 .reset_notify = hns_roce_hw_v2_reset_notify, 6714 }; 6715 6716 static struct hnae3_client hns_roce_hw_v2_client = { 6717 .name = "hns_roce_hw_v2", 6718 .type = HNAE3_CLIENT_ROCE, 6719 .ops = &hns_roce_hw_v2_ops, 6720 }; 6721 6722 static int __init hns_roce_hw_v2_init(void) 6723 { 6724 return hnae3_register_client(&hns_roce_hw_v2_client); 6725 } 6726 6727 static void __exit hns_roce_hw_v2_exit(void) 6728 { 6729 hnae3_unregister_client(&hns_roce_hw_v2_client); 6730 } 6731 6732 module_init(hns_roce_hw_v2_init); 6733 module_exit(hns_roce_hw_v2_exit); 6734 6735 MODULE_LICENSE("Dual BSD/GPL"); 6736 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6737 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6738 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6739 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6740