1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 52 struct ib_sge *sg) 53 { 54 dseg->lkey = cpu_to_le32(sg->lkey); 55 dseg->addr = cpu_to_le64(sg->addr); 56 dseg->len = cpu_to_le32(sg->length); 57 } 58 59 /* 60 * mapped-value = 1 + real-value 61 * The hns wr opcode real value is start from 0, In order to distinguish between 62 * initialized and uninitialized map values, we plus 1 to the actual value when 63 * defining the mapping, so that the validity can be identified by checking the 64 * mapped value is greater than 0. 65 */ 66 #define HR_OPC_MAP(ib_key, hr_key) \ 67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 68 69 static const u32 hns_roce_op_code[] = { 70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 72 HR_OPC_MAP(SEND, SEND), 73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 74 HR_OPC_MAP(RDMA_READ, RDMA_READ), 75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 81 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 82 }; 83 84 static u32 to_hr_opcode(u32 ib_opcode) 85 { 86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 87 return HNS_ROCE_V2_WQE_OP_MASK; 88 89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 90 HNS_ROCE_V2_WQE_OP_MASK; 91 } 92 93 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 94 void *wqe, const struct ib_reg_wr *wr) 95 { 96 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 97 struct hns_roce_wqe_frmr_seg *fseg = wqe; 98 u64 pbl_ba; 99 100 /* use ib_access_flags */ 101 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, 102 wr->access & IB_ACCESS_MW_BIND ? 1 : 0); 103 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, 104 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 105 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, 106 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); 107 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, 108 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 109 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, 110 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 111 112 /* Data structure reuse may lead to confusion */ 113 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 114 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 115 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 116 117 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 118 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 119 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 120 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 121 122 fseg->pbl_size = cpu_to_le32(mr->npages); 123 roce_set_field(fseg->mode_buf_pg_sz, 124 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, 125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, 126 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 127 roce_set_bit(fseg->mode_buf_pg_sz, 128 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); 129 } 130 131 static void set_atomic_seg(const struct ib_send_wr *wr, void *wqe, 132 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 133 unsigned int valid_num_sge) 134 { 135 struct hns_roce_wqe_atomic_seg *aseg; 136 137 set_data_seg_v2(wqe, wr->sg_list); 138 aseg = wqe + sizeof(struct hns_roce_v2_wqe_data_seg); 139 140 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 141 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 142 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 143 } else { 144 aseg->fetchadd_swap_data = 145 cpu_to_le64(atomic_wr(wr)->compare_add); 146 aseg->cmp_data = 0; 147 } 148 149 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 150 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 151 } 152 153 static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 154 unsigned int *sge_ind, unsigned int valid_num_sge) 155 { 156 struct hns_roce_v2_wqe_data_seg *dseg; 157 unsigned int cnt = valid_num_sge; 158 struct ib_sge *sge = wr->sg_list; 159 unsigned int idx = *sge_ind; 160 161 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 162 cnt -= HNS_ROCE_SGE_IN_WQE; 163 sge += HNS_ROCE_SGE_IN_WQE; 164 } 165 166 while (cnt > 0) { 167 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 168 set_data_seg_v2(dseg, sge); 169 idx++; 170 sge++; 171 cnt--; 172 } 173 174 *sge_ind = idx; 175 } 176 177 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 178 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 179 void *wqe, unsigned int *sge_ind, 180 unsigned int valid_num_sge) 181 { 182 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 183 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 184 struct ib_device *ibdev = &hr_dev->ib_dev; 185 struct hns_roce_qp *qp = to_hr_qp(ibqp); 186 int j = 0; 187 int i; 188 189 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) { 190 if (unlikely(le32_to_cpu(rc_sq_wqe->msg_len) > 191 hr_dev->caps.max_sq_inline)) { 192 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal", 193 rc_sq_wqe->msg_len, 194 hr_dev->caps.max_sq_inline); 195 return -EINVAL; 196 } 197 198 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 199 ibdev_err(ibdev, "Not support inline data!\n"); 200 return -EINVAL; 201 } 202 203 for (i = 0; i < wr->num_sge; i++) { 204 memcpy(wqe, ((void *)wr->sg_list[i].addr), 205 wr->sg_list[i].length); 206 wqe += wr->sg_list[i].length; 207 } 208 209 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 210 1); 211 } else { 212 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 213 for (i = 0; i < wr->num_sge; i++) { 214 if (likely(wr->sg_list[i].length)) { 215 set_data_seg_v2(dseg, wr->sg_list + i); 216 dseg++; 217 } 218 } 219 } else { 220 roce_set_field(rc_sq_wqe->byte_20, 221 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 222 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 223 (*sge_ind) & (qp->sge.sge_cnt - 1)); 224 225 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; 226 i++) { 227 if (likely(wr->sg_list[i].length)) { 228 set_data_seg_v2(dseg, wr->sg_list + i); 229 dseg++; 230 j++; 231 } 232 } 233 234 set_extend_sge(qp, wr, sge_ind, valid_num_sge); 235 } 236 237 roce_set_field(rc_sq_wqe->byte_16, 238 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 239 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 240 } 241 242 return 0; 243 } 244 245 static int check_send_valid(struct hns_roce_dev *hr_dev, 246 struct hns_roce_qp *hr_qp) 247 { 248 struct ib_device *ibdev = &hr_dev->ib_dev; 249 struct ib_qp *ibqp = &hr_qp->ibqp; 250 251 if (unlikely(ibqp->qp_type != IB_QPT_RC && 252 ibqp->qp_type != IB_QPT_GSI && 253 ibqp->qp_type != IB_QPT_UD)) { 254 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 255 ibqp->qp_type); 256 return -EOPNOTSUPP; 257 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 258 hr_qp->state == IB_QPS_INIT || 259 hr_qp->state == IB_QPS_RTR)) { 260 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n", 261 hr_qp->state); 262 return -EINVAL; 263 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 264 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 265 hr_dev->state); 266 return -EIO; 267 } 268 269 return 0; 270 } 271 272 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 273 unsigned int *sge_len) 274 { 275 unsigned int valid_num = 0; 276 unsigned int len = 0; 277 int i; 278 279 for (i = 0; i < wr->num_sge; i++) { 280 if (likely(wr->sg_list[i].length)) { 281 len += wr->sg_list[i].length; 282 valid_num++; 283 } 284 } 285 286 *sge_len = len; 287 return valid_num; 288 } 289 290 static inline int set_ud_wqe(struct hns_roce_qp *qp, 291 const struct ib_send_wr *wr, 292 void *wqe, unsigned int *sge_idx, 293 unsigned int owner_bit) 294 { 295 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 296 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 297 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 298 unsigned int curr_idx = *sge_idx; 299 int valid_num_sge; 300 u32 msg_len = 0; 301 bool loopback; 302 u8 *smac; 303 304 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 305 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 306 307 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 308 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 309 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 310 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 311 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 312 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 313 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 314 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 315 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 316 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]); 317 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 318 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]); 319 320 /* MAC loopback */ 321 smac = (u8 *)hr_dev->dev_addr[qp->port]; 322 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0; 323 324 roce_set_bit(ud_sq_wqe->byte_40, 325 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 326 327 roce_set_field(ud_sq_wqe->byte_4, 328 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 329 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 330 HNS_ROCE_V2_WQE_OP_SEND); 331 332 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 333 334 switch (wr->opcode) { 335 case IB_WR_SEND_WITH_IMM: 336 case IB_WR_RDMA_WRITE_WITH_IMM: 337 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 338 break; 339 default: 340 ud_sq_wqe->immtdata = 0; 341 break; 342 } 343 344 /* Set sig attr */ 345 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 346 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 347 348 /* Set se attr */ 349 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 350 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 351 352 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 353 owner_bit); 354 355 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 356 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 357 358 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 359 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 360 361 roce_set_field(ud_sq_wqe->byte_20, 362 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 363 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 364 curr_idx & (qp->sge.sge_cnt - 1)); 365 366 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 367 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 368 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 369 qp->qkey : ud_wr(wr)->remote_qkey); 370 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 371 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 372 373 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 374 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 375 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 376 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 377 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 378 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 379 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 380 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 381 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 382 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 383 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M, 384 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port); 385 386 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 387 ah->av.vlan_en ? 1 : 0); 388 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 389 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index); 390 391 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2); 392 393 set_extend_sge(qp, wr, &curr_idx, valid_num_sge); 394 395 *sge_idx = curr_idx; 396 397 return 0; 398 } 399 400 static inline int set_rc_wqe(struct hns_roce_qp *qp, 401 const struct ib_send_wr *wr, 402 void *wqe, unsigned int *sge_idx, 403 unsigned int owner_bit) 404 { 405 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 406 unsigned int curr_idx = *sge_idx; 407 unsigned int valid_num_sge; 408 u32 msg_len = 0; 409 int ret = 0; 410 411 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 412 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 413 414 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 415 416 switch (wr->opcode) { 417 case IB_WR_SEND_WITH_IMM: 418 case IB_WR_RDMA_WRITE_WITH_IMM: 419 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 420 break; 421 case IB_WR_SEND_WITH_INV: 422 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 423 break; 424 default: 425 rc_sq_wqe->immtdata = 0; 426 break; 427 } 428 429 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 430 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 431 432 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 433 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 434 435 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 436 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 437 438 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 439 owner_bit); 440 441 wqe += sizeof(struct hns_roce_v2_rc_send_wqe); 442 switch (wr->opcode) { 443 case IB_WR_RDMA_READ: 444 case IB_WR_RDMA_WRITE: 445 case IB_WR_RDMA_WRITE_WITH_IMM: 446 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 447 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 448 break; 449 case IB_WR_LOCAL_INV: 450 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 451 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 452 break; 453 case IB_WR_REG_MR: 454 set_frmr_seg(rc_sq_wqe, wqe, reg_wr(wr)); 455 break; 456 case IB_WR_ATOMIC_CMP_AND_SWP: 457 case IB_WR_ATOMIC_FETCH_AND_ADD: 458 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 459 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 460 break; 461 default: 462 break; 463 } 464 465 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 466 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 467 to_hr_opcode(wr->opcode)); 468 469 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 470 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 471 set_atomic_seg(wr, wqe, rc_sq_wqe, valid_num_sge); 472 else if (wr->opcode != IB_WR_REG_MR) 473 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 474 wqe, &curr_idx, valid_num_sge); 475 476 *sge_idx = curr_idx; 477 478 return ret; 479 } 480 481 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 482 struct hns_roce_qp *qp) 483 { 484 /* 485 * Hip08 hardware cannot flush the WQEs in SQ if the QP state 486 * gets into errored mode. Hence, as a workaround to this 487 * hardware limitation, driver needs to assist in flushing. But 488 * the flushing operation uses mailbox to convey the QP state to 489 * the hardware and which can sleep due to the mutex protection 490 * around the mailbox calls. Hence, use the deferred flush for 491 * now. 492 */ 493 if (qp->state == IB_QPS_ERR) { 494 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 495 init_flush_work(hr_dev, qp); 496 } else { 497 struct hns_roce_v2_db sq_db = {}; 498 499 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 500 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 501 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 502 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 503 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, 504 V2_DB_PARAMETER_IDX_S, qp->sq.head); 505 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 506 V2_DB_PARAMETER_SL_S, qp->sl); 507 508 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l); 509 } 510 } 511 512 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 513 const struct ib_send_wr *wr, 514 const struct ib_send_wr **bad_wr) 515 { 516 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 517 struct ib_device *ibdev = &hr_dev->ib_dev; 518 struct hns_roce_qp *qp = to_hr_qp(ibqp); 519 unsigned long flags = 0; 520 unsigned int owner_bit; 521 unsigned int sge_idx; 522 unsigned int wqe_idx; 523 void *wqe = NULL; 524 int nreq; 525 int ret; 526 527 spin_lock_irqsave(&qp->sq.lock, flags); 528 529 ret = check_send_valid(hr_dev, qp); 530 if (unlikely(ret)) { 531 *bad_wr = wr; 532 nreq = 0; 533 goto out; 534 } 535 536 sge_idx = qp->next_sge; 537 538 for (nreq = 0; wr; ++nreq, wr = wr->next) { 539 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 540 ret = -ENOMEM; 541 *bad_wr = wr; 542 goto out; 543 } 544 545 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 546 547 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 548 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n", 549 wr->num_sge, qp->sq.max_gs); 550 ret = -EINVAL; 551 *bad_wr = wr; 552 goto out; 553 } 554 555 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 556 qp->sq.wrid[wqe_idx] = wr->wr_id; 557 owner_bit = 558 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 559 560 /* Corresponding to the QP type, wqe process separately */ 561 if (ibqp->qp_type == IB_QPT_GSI) 562 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 563 else if (ibqp->qp_type == IB_QPT_RC) 564 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 565 566 if (unlikely(ret)) { 567 *bad_wr = wr; 568 goto out; 569 } 570 } 571 572 out: 573 if (likely(nreq)) { 574 qp->sq.head += nreq; 575 qp->next_sge = sge_idx; 576 /* Memory barrier */ 577 wmb(); 578 update_sq_db(hr_dev, qp); 579 } 580 581 spin_unlock_irqrestore(&qp->sq.lock, flags); 582 583 return ret; 584 } 585 586 static int check_recv_valid(struct hns_roce_dev *hr_dev, 587 struct hns_roce_qp *hr_qp) 588 { 589 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 590 return -EIO; 591 else if (hr_qp->state == IB_QPS_RESET) 592 return -EINVAL; 593 594 return 0; 595 } 596 597 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 598 const struct ib_recv_wr *wr, 599 const struct ib_recv_wr **bad_wr) 600 { 601 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 602 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 603 struct ib_device *ibdev = &hr_dev->ib_dev; 604 struct hns_roce_v2_wqe_data_seg *dseg; 605 struct hns_roce_rinl_sge *sge_list; 606 unsigned long flags; 607 void *wqe = NULL; 608 u32 wqe_idx; 609 int nreq; 610 int ret; 611 int i; 612 613 spin_lock_irqsave(&hr_qp->rq.lock, flags); 614 615 ret = check_recv_valid(hr_dev, hr_qp); 616 if (unlikely(ret)) { 617 *bad_wr = wr; 618 nreq = 0; 619 goto out; 620 } 621 622 for (nreq = 0; wr; ++nreq, wr = wr->next) { 623 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 624 hr_qp->ibqp.recv_cq))) { 625 ret = -ENOMEM; 626 *bad_wr = wr; 627 goto out; 628 } 629 630 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 631 632 if (unlikely(wr->num_sge >= hr_qp->rq.max_gs)) { 633 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n", 634 wr->num_sge, hr_qp->rq.max_gs); 635 ret = -EINVAL; 636 *bad_wr = wr; 637 goto out; 638 } 639 640 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 641 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 642 for (i = 0; i < wr->num_sge; i++) { 643 if (!wr->sg_list[i].length) 644 continue; 645 set_data_seg_v2(dseg, wr->sg_list + i); 646 dseg++; 647 } 648 649 if (wr->num_sge < hr_qp->rq.max_gs) { 650 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 651 dseg->addr = 0; 652 dseg->len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 653 } 654 655 /* rq support inline data */ 656 if (hr_qp->rq_inl_buf.wqe_cnt) { 657 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 658 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = 659 (u32)wr->num_sge; 660 for (i = 0; i < wr->num_sge; i++) { 661 sge_list[i].addr = 662 (void *)(u64)wr->sg_list[i].addr; 663 sge_list[i].len = wr->sg_list[i].length; 664 } 665 } 666 667 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 668 } 669 670 out: 671 if (likely(nreq)) { 672 hr_qp->rq.head += nreq; 673 /* Memory barrier */ 674 wmb(); 675 676 /* 677 * Hip08 hardware cannot flush the WQEs in RQ if the QP state 678 * gets into errored mode. Hence, as a workaround to this 679 * hardware limitation, driver needs to assist in flushing. But 680 * the flushing operation uses mailbox to convey the QP state to 681 * the hardware and which can sleep due to the mutex protection 682 * around the mailbox calls. Hence, use the deferred flush for 683 * now. 684 */ 685 if (hr_qp->state == IB_QPS_ERR) { 686 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, 687 &hr_qp->flush_flag)) 688 init_flush_work(hr_dev, hr_qp); 689 } else { 690 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 691 } 692 } 693 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 694 695 return ret; 696 } 697 698 static void *get_srq_wqe(struct hns_roce_srq *srq, int n) 699 { 700 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 701 } 702 703 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n) 704 { 705 return hns_roce_buf_offset(idx_que->mtr.kmem, 706 n << idx_que->entry_shift); 707 } 708 709 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index) 710 { 711 /* always called with interrupts disabled. */ 712 spin_lock(&srq->lock); 713 714 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 715 srq->tail++; 716 717 spin_unlock(&srq->lock); 718 } 719 720 static int find_empty_entry(struct hns_roce_idx_que *idx_que, 721 unsigned long size) 722 { 723 int wqe_idx; 724 725 if (unlikely(bitmap_full(idx_que->bitmap, size))) 726 return -ENOSPC; 727 728 wqe_idx = find_first_zero_bit(idx_que->bitmap, size); 729 730 bitmap_set(idx_que->bitmap, wqe_idx, 1); 731 732 return wqe_idx; 733 } 734 735 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 736 const struct ib_recv_wr *wr, 737 const struct ib_recv_wr **bad_wr) 738 { 739 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 740 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 741 struct hns_roce_v2_wqe_data_seg *dseg; 742 struct hns_roce_v2_db srq_db; 743 unsigned long flags; 744 __le32 *srq_idx; 745 int ret = 0; 746 int wqe_idx; 747 void *wqe; 748 int nreq; 749 int ind; 750 int i; 751 752 spin_lock_irqsave(&srq->lock, flags); 753 754 ind = srq->head & (srq->wqe_cnt - 1); 755 756 for (nreq = 0; wr; ++nreq, wr = wr->next) { 757 if (unlikely(wr->num_sge >= srq->max_gs)) { 758 ret = -EINVAL; 759 *bad_wr = wr; 760 break; 761 } 762 763 if (unlikely(srq->head == srq->tail)) { 764 ret = -ENOMEM; 765 *bad_wr = wr; 766 break; 767 } 768 769 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt); 770 if (unlikely(wqe_idx < 0)) { 771 ret = -ENOMEM; 772 *bad_wr = wr; 773 break; 774 } 775 776 wqe = get_srq_wqe(srq, wqe_idx); 777 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 778 779 for (i = 0; i < wr->num_sge; ++i) { 780 dseg[i].len = cpu_to_le32(wr->sg_list[i].length); 781 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey); 782 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr); 783 } 784 785 if (wr->num_sge < srq->max_gs) { 786 dseg[i].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 787 dseg[i].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 788 dseg[i].addr = 0; 789 } 790 791 srq_idx = get_idx_buf(&srq->idx_que, ind); 792 *srq_idx = cpu_to_le32(wqe_idx); 793 794 srq->wrid[wqe_idx] = wr->wr_id; 795 ind = (ind + 1) & (srq->wqe_cnt - 1); 796 } 797 798 if (likely(nreq)) { 799 srq->head += nreq; 800 801 /* 802 * Make sure that descriptors are written before 803 * doorbell record. 804 */ 805 wmb(); 806 807 srq_db.byte_4 = 808 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S | 809 (srq->srqn & V2_DB_BYTE_4_TAG_M)); 810 srq_db.parameter = 811 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M); 812 813 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l); 814 } 815 816 spin_unlock_irqrestore(&srq->lock, flags); 817 818 return ret; 819 } 820 821 static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 822 unsigned long instance_stage, 823 unsigned long reset_stage) 824 { 825 /* When hardware reset has been completed once or more, we should stop 826 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 827 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 828 * stage of soft reset process, we should exit with error, and then 829 * HNAE3_INIT_CLIENT related process can rollback the operation like 830 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 831 * process will exit with error to notify NIC driver to reschedule soft 832 * reset process once again. 833 */ 834 hr_dev->is_reset = true; 835 hr_dev->dis_db = true; 836 837 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 838 instance_stage == HNS_ROCE_STATE_INIT) 839 return CMD_RST_PRC_EBUSY; 840 841 return CMD_RST_PRC_SUCCESS; 842 } 843 844 static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 845 unsigned long instance_stage, 846 unsigned long reset_stage) 847 { 848 struct hns_roce_v2_priv *priv = hr_dev->priv; 849 struct hnae3_handle *handle = priv->handle; 850 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 851 852 /* When hardware reset is detected, we should stop sending mailbox&cmq& 853 * doorbell to hardware. If now in .init_instance() function, we should 854 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 855 * process, we should exit with error, and then HNAE3_INIT_CLIENT 856 * related process can rollback the operation like notifing hardware to 857 * free resources, HNAE3_INIT_CLIENT related process will exit with 858 * error to notify NIC driver to reschedule soft reset process once 859 * again. 860 */ 861 hr_dev->dis_db = true; 862 if (!ops->get_hw_reset_stat(handle)) 863 hr_dev->is_reset = true; 864 865 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 866 instance_stage == HNS_ROCE_STATE_INIT) 867 return CMD_RST_PRC_EBUSY; 868 869 return CMD_RST_PRC_SUCCESS; 870 } 871 872 static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 873 { 874 struct hns_roce_v2_priv *priv = hr_dev->priv; 875 struct hnae3_handle *handle = priv->handle; 876 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 877 878 /* When software reset is detected at .init_instance() function, we 879 * should stop sending mailbox&cmq&doorbell to hardware, and exit 880 * with error. 881 */ 882 hr_dev->dis_db = true; 883 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 884 hr_dev->is_reset = true; 885 886 return CMD_RST_PRC_EBUSY; 887 } 888 889 static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev) 890 { 891 struct hns_roce_v2_priv *priv = hr_dev->priv; 892 struct hnae3_handle *handle = priv->handle; 893 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 894 unsigned long instance_stage; /* the current instance stage */ 895 unsigned long reset_stage; /* the current reset stage */ 896 unsigned long reset_cnt; 897 bool sw_resetting; 898 bool hw_resetting; 899 900 if (hr_dev->is_reset) 901 return CMD_RST_PRC_SUCCESS; 902 903 /* Get information about reset from NIC driver or RoCE driver itself, 904 * the meaning of the following variables from NIC driver are described 905 * as below: 906 * reset_cnt -- The count value of completed hardware reset. 907 * hw_resetting -- Whether hardware device is resetting now. 908 * sw_resetting -- Whether NIC's software reset process is running now. 909 */ 910 instance_stage = handle->rinfo.instance_state; 911 reset_stage = handle->rinfo.reset_state; 912 reset_cnt = ops->ae_dev_reset_cnt(handle); 913 hw_resetting = ops->get_hw_reset_stat(handle); 914 sw_resetting = ops->ae_dev_resetting(handle); 915 916 if (reset_cnt != hr_dev->reset_cnt) 917 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 918 reset_stage); 919 else if (hw_resetting) 920 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 921 reset_stage); 922 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 923 return hns_roce_v2_cmd_sw_resetting(hr_dev); 924 925 return 0; 926 } 927 928 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 929 { 930 int ntu = ring->next_to_use; 931 int ntc = ring->next_to_clean; 932 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 933 934 return ring->desc_num - used - 1; 935 } 936 937 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 938 struct hns_roce_v2_cmq_ring *ring) 939 { 940 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 941 942 ring->desc = kzalloc(size, GFP_KERNEL); 943 if (!ring->desc) 944 return -ENOMEM; 945 946 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 947 DMA_BIDIRECTIONAL); 948 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 949 ring->desc_dma_addr = 0; 950 kfree(ring->desc); 951 ring->desc = NULL; 952 return -ENOMEM; 953 } 954 955 return 0; 956 } 957 958 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 959 struct hns_roce_v2_cmq_ring *ring) 960 { 961 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 962 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 963 DMA_BIDIRECTIONAL); 964 965 ring->desc_dma_addr = 0; 966 kfree(ring->desc); 967 } 968 969 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 970 { 971 struct hns_roce_v2_priv *priv = hr_dev->priv; 972 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 973 &priv->cmq.csq : &priv->cmq.crq; 974 975 ring->flag = ring_type; 976 ring->next_to_clean = 0; 977 ring->next_to_use = 0; 978 979 return hns_roce_alloc_cmq_desc(hr_dev, ring); 980 } 981 982 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 983 { 984 struct hns_roce_v2_priv *priv = hr_dev->priv; 985 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 986 &priv->cmq.csq : &priv->cmq.crq; 987 dma_addr_t dma = ring->desc_dma_addr; 988 989 if (ring_type == TYPE_CSQ) { 990 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 991 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 992 upper_32_bits(dma)); 993 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 994 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 995 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 996 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 997 } else { 998 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 999 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 1000 upper_32_bits(dma)); 1001 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 1002 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1003 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 1004 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 1005 } 1006 } 1007 1008 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1009 { 1010 struct hns_roce_v2_priv *priv = hr_dev->priv; 1011 int ret; 1012 1013 /* Setup the queue entries for command queue */ 1014 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; 1015 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; 1016 1017 /* Setup the lock for command queue */ 1018 spin_lock_init(&priv->cmq.csq.lock); 1019 spin_lock_init(&priv->cmq.crq.lock); 1020 1021 /* Setup Tx write back timeout */ 1022 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1023 1024 /* Init CSQ */ 1025 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 1026 if (ret) { 1027 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 1028 return ret; 1029 } 1030 1031 /* Init CRQ */ 1032 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 1033 if (ret) { 1034 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 1035 goto err_crq; 1036 } 1037 1038 /* Init CSQ REG */ 1039 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 1040 1041 /* Init CRQ REG */ 1042 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 1043 1044 return 0; 1045 1046 err_crq: 1047 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1048 1049 return ret; 1050 } 1051 1052 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1053 { 1054 struct hns_roce_v2_priv *priv = hr_dev->priv; 1055 1056 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1057 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 1058 } 1059 1060 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1061 enum hns_roce_opcode_type opcode, 1062 bool is_read) 1063 { 1064 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1065 desc->opcode = cpu_to_le16(opcode); 1066 desc->flag = 1067 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1068 if (is_read) 1069 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1070 else 1071 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1072 } 1073 1074 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1075 { 1076 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1077 struct hns_roce_v2_priv *priv = hr_dev->priv; 1078 1079 return head == priv->cmq.csq.next_to_use; 1080 } 1081 1082 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 1083 { 1084 struct hns_roce_v2_priv *priv = hr_dev->priv; 1085 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1086 struct hns_roce_cmq_desc *desc; 1087 u16 ntc = csq->next_to_clean; 1088 u32 head; 1089 int clean = 0; 1090 1091 desc = &csq->desc[ntc]; 1092 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1093 while (head != ntc) { 1094 memset(desc, 0, sizeof(*desc)); 1095 ntc++; 1096 if (ntc == csq->desc_num) 1097 ntc = 0; 1098 desc = &csq->desc[ntc]; 1099 clean++; 1100 } 1101 csq->next_to_clean = ntc; 1102 1103 return clean; 1104 } 1105 1106 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1107 struct hns_roce_cmq_desc *desc, int num) 1108 { 1109 struct hns_roce_v2_priv *priv = hr_dev->priv; 1110 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1111 struct hns_roce_cmq_desc *desc_to_use; 1112 bool complete = false; 1113 u32 timeout = 0; 1114 int handle = 0; 1115 u16 desc_ret; 1116 int ret = 0; 1117 int ntc; 1118 1119 spin_lock_bh(&csq->lock); 1120 1121 if (num > hns_roce_cmq_space(csq)) { 1122 spin_unlock_bh(&csq->lock); 1123 return -EBUSY; 1124 } 1125 1126 /* 1127 * Record the location of desc in the cmq for this time 1128 * which will be use for hardware to write back 1129 */ 1130 ntc = csq->next_to_use; 1131 1132 while (handle < num) { 1133 desc_to_use = &csq->desc[csq->next_to_use]; 1134 *desc_to_use = desc[handle]; 1135 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 1136 csq->next_to_use++; 1137 if (csq->next_to_use == csq->desc_num) 1138 csq->next_to_use = 0; 1139 handle++; 1140 } 1141 1142 /* Write to hardware */ 1143 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 1144 1145 /* 1146 * If the command is sync, wait for the firmware to write back, 1147 * if multi descriptors to be sent, use the first one to check 1148 */ 1149 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 1150 do { 1151 if (hns_roce_cmq_csq_done(hr_dev)) 1152 break; 1153 udelay(1); 1154 timeout++; 1155 } while (timeout < priv->cmq.tx_timeout); 1156 } 1157 1158 if (hns_roce_cmq_csq_done(hr_dev)) { 1159 complete = true; 1160 handle = 0; 1161 while (handle < num) { 1162 /* get the result of hardware write back */ 1163 desc_to_use = &csq->desc[ntc]; 1164 desc[handle] = *desc_to_use; 1165 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 1166 desc_ret = le16_to_cpu(desc[handle].retval); 1167 if (desc_ret == CMD_EXEC_SUCCESS) 1168 ret = 0; 1169 else 1170 ret = -EIO; 1171 priv->cmq.last_status = desc_ret; 1172 ntc++; 1173 handle++; 1174 if (ntc == csq->desc_num) 1175 ntc = 0; 1176 } 1177 } 1178 1179 if (!complete) 1180 ret = -EAGAIN; 1181 1182 /* clean the command send queue */ 1183 handle = hns_roce_cmq_csq_clean(hr_dev); 1184 if (handle != num) 1185 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 1186 handle, num); 1187 1188 spin_unlock_bh(&csq->lock); 1189 1190 return ret; 1191 } 1192 1193 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1194 struct hns_roce_cmq_desc *desc, int num) 1195 { 1196 int retval; 1197 int ret; 1198 1199 ret = hns_roce_v2_rst_process_cmd(hr_dev); 1200 if (ret == CMD_RST_PRC_SUCCESS) 1201 return 0; 1202 if (ret == CMD_RST_PRC_EBUSY) 1203 return -EBUSY; 1204 1205 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1206 if (ret) { 1207 retval = hns_roce_v2_rst_process_cmd(hr_dev); 1208 if (retval == CMD_RST_PRC_SUCCESS) 1209 return 0; 1210 else if (retval == CMD_RST_PRC_EBUSY) 1211 return -EBUSY; 1212 } 1213 1214 return ret; 1215 } 1216 1217 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1218 { 1219 struct hns_roce_query_version *resp; 1220 struct hns_roce_cmq_desc desc; 1221 int ret; 1222 1223 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1224 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1225 if (ret) 1226 return ret; 1227 1228 resp = (struct hns_roce_query_version *)desc.data; 1229 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1230 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1231 1232 return 0; 1233 } 1234 1235 static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev) 1236 { 1237 struct hns_roce_v2_priv *priv = hr_dev->priv; 1238 struct hnae3_handle *handle = priv->handle; 1239 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1240 unsigned long reset_cnt; 1241 bool sw_resetting; 1242 bool hw_resetting; 1243 1244 reset_cnt = ops->ae_dev_reset_cnt(handle); 1245 hw_resetting = ops->get_hw_reset_stat(handle); 1246 sw_resetting = ops->ae_dev_resetting(handle); 1247 1248 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting) 1249 return true; 1250 1251 return false; 1252 } 1253 1254 static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval, 1255 int flag) 1256 { 1257 struct hns_roce_v2_priv *priv = hr_dev->priv; 1258 struct hnae3_handle *handle = priv->handle; 1259 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1260 unsigned long instance_stage; 1261 unsigned long reset_cnt; 1262 unsigned long end; 1263 bool sw_resetting; 1264 bool hw_resetting; 1265 1266 instance_stage = handle->rinfo.instance_state; 1267 reset_cnt = ops->ae_dev_reset_cnt(handle); 1268 hw_resetting = ops->get_hw_reset_stat(handle); 1269 sw_resetting = ops->ae_dev_resetting(handle); 1270 1271 if (reset_cnt != hr_dev->reset_cnt) { 1272 hr_dev->dis_db = true; 1273 hr_dev->is_reset = true; 1274 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1275 } else if (hw_resetting) { 1276 hr_dev->dis_db = true; 1277 1278 dev_warn(hr_dev->dev, 1279 "Func clear is pending, device in resetting state.\n"); 1280 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1281 while (end) { 1282 if (!ops->get_hw_reset_stat(handle)) { 1283 hr_dev->is_reset = true; 1284 dev_info(hr_dev->dev, 1285 "Func clear success after reset.\n"); 1286 return; 1287 } 1288 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1289 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1290 } 1291 1292 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1293 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) { 1294 hr_dev->dis_db = true; 1295 1296 dev_warn(hr_dev->dev, 1297 "Func clear is pending, device in resetting state.\n"); 1298 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1299 while (end) { 1300 if (ops->ae_dev_reset_cnt(handle) != 1301 hr_dev->reset_cnt) { 1302 hr_dev->is_reset = true; 1303 dev_info(hr_dev->dev, 1304 "Func clear success after sw reset\n"); 1305 return; 1306 } 1307 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1308 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1309 } 1310 1311 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1312 } else { 1313 if (retval && !flag) 1314 dev_warn(hr_dev->dev, 1315 "Func clear read failed, ret = %d.\n", retval); 1316 1317 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1318 } 1319 } 1320 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1321 { 1322 bool fclr_write_fail_flag = false; 1323 struct hns_roce_func_clear *resp; 1324 struct hns_roce_cmq_desc desc; 1325 unsigned long end; 1326 int ret = 0; 1327 1328 if (hns_roce_func_clr_chk_rst(hr_dev)) 1329 goto out; 1330 1331 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1332 resp = (struct hns_roce_func_clear *)desc.data; 1333 1334 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1335 if (ret) { 1336 fclr_write_fail_flag = true; 1337 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1338 ret); 1339 goto out; 1340 } 1341 1342 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1343 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1344 while (end) { 1345 if (hns_roce_func_clr_chk_rst(hr_dev)) 1346 goto out; 1347 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1348 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1349 1350 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1351 true); 1352 1353 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1354 if (ret) 1355 continue; 1356 1357 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1358 hr_dev->is_reset = true; 1359 return; 1360 } 1361 } 1362 1363 out: 1364 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag); 1365 } 1366 1367 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1368 { 1369 struct hns_roce_query_fw_info *resp; 1370 struct hns_roce_cmq_desc desc; 1371 int ret; 1372 1373 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1374 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1375 if (ret) 1376 return ret; 1377 1378 resp = (struct hns_roce_query_fw_info *)desc.data; 1379 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1380 1381 return 0; 1382 } 1383 1384 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1385 { 1386 struct hns_roce_cfg_global_param *req; 1387 struct hns_roce_cmq_desc desc; 1388 1389 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1390 false); 1391 1392 req = (struct hns_roce_cfg_global_param *)desc.data; 1393 memset(req, 0, sizeof(*req)); 1394 roce_set_field(req->time_cfg_udp_port, 1395 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 1396 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 1397 roce_set_field(req->time_cfg_udp_port, 1398 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 1399 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 1400 1401 return hns_roce_cmq_send(hr_dev, &desc, 1); 1402 } 1403 1404 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1405 { 1406 struct hns_roce_cmq_desc desc[2]; 1407 struct hns_roce_pf_res_a *req_a; 1408 struct hns_roce_pf_res_b *req_b; 1409 int ret; 1410 int i; 1411 1412 for (i = 0; i < 2; i++) { 1413 hns_roce_cmq_setup_basic_desc(&desc[i], 1414 HNS_ROCE_OPC_QUERY_PF_RES, true); 1415 1416 if (i == 0) 1417 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1418 else 1419 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1420 } 1421 1422 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1423 if (ret) 1424 return ret; 1425 1426 req_a = (struct hns_roce_pf_res_a *)desc[0].data; 1427 req_b = (struct hns_roce_pf_res_b *)desc[1].data; 1428 1429 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, 1430 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 1431 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 1432 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, 1433 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 1434 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 1435 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, 1436 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 1437 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 1438 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, 1439 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 1440 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 1441 1442 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, 1443 PF_RES_DATA_3_PF_SL_NUM_M, 1444 PF_RES_DATA_3_PF_SL_NUM_S); 1445 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, 1446 PF_RES_DATA_4_PF_SCCC_BT_NUM_M, 1447 PF_RES_DATA_4_PF_SCCC_BT_NUM_S); 1448 1449 return 0; 1450 } 1451 1452 static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev) 1453 { 1454 struct hns_roce_pf_timer_res_a *req_a; 1455 struct hns_roce_cmq_desc desc; 1456 int ret; 1457 1458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1459 true); 1460 1461 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1462 if (ret) 1463 return ret; 1464 1465 req_a = (struct hns_roce_pf_timer_res_a *)desc.data; 1466 1467 hr_dev->caps.qpc_timer_bt_num = 1468 roce_get_field(req_a->qpc_timer_bt_idx_num, 1469 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M, 1470 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S); 1471 hr_dev->caps.cqc_timer_bt_num = 1472 roce_get_field(req_a->cqc_timer_bt_idx_num, 1473 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M, 1474 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S); 1475 1476 return 0; 1477 } 1478 1479 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) 1480 { 1481 struct hns_roce_cmq_desc desc; 1482 struct hns_roce_vf_switch *swt; 1483 int ret; 1484 1485 swt = (struct hns_roce_vf_switch *)desc.data; 1486 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1487 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1488 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1489 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1490 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1491 if (ret) 1492 return ret; 1493 1494 desc.flag = 1495 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1496 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1497 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1498 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1499 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1500 1501 return hns_roce_cmq_send(hr_dev, &desc, 1); 1502 } 1503 1504 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1505 { 1506 struct hns_roce_cmq_desc desc[2]; 1507 struct hns_roce_vf_res_a *req_a; 1508 struct hns_roce_vf_res_b *req_b; 1509 int i; 1510 1511 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 1512 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 1513 memset(req_a, 0, sizeof(*req_a)); 1514 memset(req_b, 0, sizeof(*req_b)); 1515 for (i = 0; i < 2; i++) { 1516 hns_roce_cmq_setup_basic_desc(&desc[i], 1517 HNS_ROCE_OPC_ALLOC_VF_RES, false); 1518 1519 if (i == 0) 1520 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1521 else 1522 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1523 } 1524 1525 roce_set_field(req_a->vf_qpc_bt_idx_num, 1526 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 1527 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 1528 roce_set_field(req_a->vf_qpc_bt_idx_num, 1529 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 1530 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM); 1531 1532 roce_set_field(req_a->vf_srqc_bt_idx_num, 1533 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 1534 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 1535 roce_set_field(req_a->vf_srqc_bt_idx_num, 1536 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 1537 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 1538 HNS_ROCE_VF_SRQC_BT_NUM); 1539 1540 roce_set_field(req_a->vf_cqc_bt_idx_num, 1541 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 1542 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 1543 roce_set_field(req_a->vf_cqc_bt_idx_num, 1544 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 1545 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM); 1546 1547 roce_set_field(req_a->vf_mpt_bt_idx_num, 1548 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 1549 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 1550 roce_set_field(req_a->vf_mpt_bt_idx_num, 1551 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 1552 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM); 1553 1554 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M, 1555 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 1556 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M, 1557 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM); 1558 1559 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M, 1560 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 1561 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M, 1562 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM); 1563 1564 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M, 1565 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1566 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M, 1567 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM); 1568 1569 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M, 1570 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1571 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M, 1572 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM); 1573 1574 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M, 1575 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0); 1576 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M, 1577 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S, 1578 HNS_ROCE_VF_SCCC_BT_NUM); 1579 1580 return hns_roce_cmq_send(hr_dev, desc, 2); 1581 } 1582 1583 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1584 { 1585 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1586 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1587 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1588 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1589 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num; 1590 struct hns_roce_cfg_bt_attr *req; 1591 struct hns_roce_cmq_desc desc; 1592 1593 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1594 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1595 memset(req, 0, sizeof(*req)); 1596 1597 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1598 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1599 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1600 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1601 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1602 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1603 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1604 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1605 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1606 1607 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1608 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1609 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1610 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1611 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1612 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1613 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1614 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1615 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1616 1617 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1618 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1619 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1620 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1621 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1622 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1623 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1624 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1625 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1626 1627 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1628 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1629 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1630 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1631 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1632 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1633 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1634 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1635 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1636 1637 roce_set_field(req->vf_sccc_cfg, 1638 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M, 1639 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S, 1640 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1641 roce_set_field(req->vf_sccc_cfg, 1642 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M, 1643 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S, 1644 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1645 roce_set_field(req->vf_sccc_cfg, 1646 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M, 1647 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S, 1648 sccc_hop_num == 1649 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num); 1650 1651 return hns_roce_cmq_send(hr_dev, &desc, 1); 1652 } 1653 1654 static void set_default_caps(struct hns_roce_dev *hr_dev) 1655 { 1656 struct hns_roce_caps *caps = &hr_dev->caps; 1657 1658 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1659 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1660 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1661 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1662 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1663 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1664 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1665 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1666 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1667 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1668 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1669 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1670 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1671 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1672 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1673 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1674 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1675 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1676 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1677 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1678 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1679 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1680 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1681 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1682 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1683 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1684 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1685 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1686 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1687 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1688 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1689 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1690 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1691 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1692 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1693 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1694 caps->reserved_lkey = 0; 1695 caps->reserved_pds = 0; 1696 caps->reserved_mrws = 1; 1697 caps->reserved_uars = 0; 1698 caps->reserved_cqs = 0; 1699 caps->reserved_srqs = 0; 1700 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1701 1702 caps->qpc_ba_pg_sz = 0; 1703 caps->qpc_buf_pg_sz = 0; 1704 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1705 caps->srqc_ba_pg_sz = 0; 1706 caps->srqc_buf_pg_sz = 0; 1707 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1708 caps->cqc_ba_pg_sz = 0; 1709 caps->cqc_buf_pg_sz = 0; 1710 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1711 caps->mpt_ba_pg_sz = 0; 1712 caps->mpt_buf_pg_sz = 0; 1713 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1714 caps->mtt_ba_pg_sz = 0; 1715 caps->mtt_buf_pg_sz = 0; 1716 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1717 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1718 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1719 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1720 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 1721 caps->cqe_buf_pg_sz = 0; 1722 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1723 caps->srqwqe_ba_pg_sz = 0; 1724 caps->srqwqe_buf_pg_sz = 0; 1725 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1726 caps->idx_ba_pg_sz = 0; 1727 caps->idx_buf_pg_sz = 0; 1728 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1729 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1730 1731 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1732 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1733 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1734 HNS_ROCE_CAP_FLAG_RECORD_DB | 1735 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; 1736 1737 caps->pkey_table_len[0] = 1; 1738 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1739 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1740 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1741 caps->local_ca_ack_delay = 0; 1742 caps->max_mtu = IB_MTU_4096; 1743 1744 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1745 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1746 1747 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { 1748 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1749 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1750 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; 1751 1752 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1753 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1754 caps->qpc_timer_ba_pg_sz = 0; 1755 caps->qpc_timer_buf_pg_sz = 0; 1756 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1757 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1758 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1759 caps->cqc_timer_ba_pg_sz = 0; 1760 caps->cqc_timer_buf_pg_sz = 0; 1761 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1762 1763 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ; 1764 caps->sccc_ba_pg_sz = 0; 1765 caps->sccc_buf_pg_sz = 0; 1766 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1767 } 1768 } 1769 1770 static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num, 1771 int *buf_page_size, int *bt_page_size, u32 hem_type) 1772 { 1773 u64 obj_per_chunk; 1774 int bt_chunk_size = 1 << PAGE_SHIFT; 1775 int buf_chunk_size = 1 << PAGE_SHIFT; 1776 int obj_per_chunk_default = buf_chunk_size / obj_size; 1777 1778 *buf_page_size = 0; 1779 *bt_page_size = 0; 1780 1781 switch (hop_num) { 1782 case 3: 1783 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1784 (bt_chunk_size / BA_BYTE_LEN) * 1785 (bt_chunk_size / BA_BYTE_LEN) * 1786 obj_per_chunk_default; 1787 break; 1788 case 2: 1789 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1790 (bt_chunk_size / BA_BYTE_LEN) * 1791 obj_per_chunk_default; 1792 break; 1793 case 1: 1794 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1795 obj_per_chunk_default; 1796 break; 1797 case HNS_ROCE_HOP_NUM_0: 1798 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1799 break; 1800 default: 1801 pr_err("Table %d not support hop_num = %d!\n", hem_type, 1802 hop_num); 1803 return; 1804 } 1805 1806 if (hem_type >= HEM_TYPE_MTT) 1807 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1808 else 1809 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1810 } 1811 1812 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 1813 { 1814 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 1815 struct hns_roce_caps *caps = &hr_dev->caps; 1816 struct hns_roce_query_pf_caps_a *resp_a; 1817 struct hns_roce_query_pf_caps_b *resp_b; 1818 struct hns_roce_query_pf_caps_c *resp_c; 1819 struct hns_roce_query_pf_caps_d *resp_d; 1820 struct hns_roce_query_pf_caps_e *resp_e; 1821 int ctx_hop_num; 1822 int pbl_hop_num; 1823 int ret; 1824 int i; 1825 1826 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 1827 hns_roce_cmq_setup_basic_desc(&desc[i], 1828 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 1829 true); 1830 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 1831 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1832 else 1833 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1834 } 1835 1836 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 1837 if (ret) 1838 return ret; 1839 1840 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 1841 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 1842 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 1843 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 1844 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 1845 1846 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 1847 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 1848 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 1849 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 1850 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 1851 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 1852 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 1853 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 1854 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 1855 caps->num_other_vectors = resp_a->num_other_vectors; 1856 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 1857 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 1858 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 1859 caps->cq_entry_sz = resp_a->cq_entry_sz; 1860 1861 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 1862 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 1863 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 1864 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 1865 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 1866 caps->idx_entry_sz = resp_b->idx_entry_sz; 1867 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz; 1868 caps->max_mtu = resp_b->max_mtu; 1869 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz); 1870 caps->min_cqes = resp_b->min_cqes; 1871 caps->min_wqes = resp_b->min_wqes; 1872 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 1873 caps->pkey_table_len[0] = resp_b->pkey_table_len; 1874 caps->phy_num_uars = resp_b->phy_num_uars; 1875 ctx_hop_num = resp_b->ctx_hop_num; 1876 pbl_hop_num = resp_b->pbl_hop_num; 1877 1878 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 1879 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 1880 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 1881 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 1882 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 1883 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 1884 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 1885 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 1886 1887 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 1888 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 1889 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 1890 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 1891 V2_QUERY_PF_CAPS_C_MAX_GID_M, 1892 V2_QUERY_PF_CAPS_C_MAX_GID_S); 1893 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 1894 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 1895 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 1896 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 1897 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 1898 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 1899 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 1900 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 1901 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 1902 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 1903 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 1904 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 1905 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 1906 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 1907 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 1908 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 1909 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 1910 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 1911 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 1912 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 1913 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 1914 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 1915 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 1916 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 1917 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 1918 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 1919 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 1920 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1921 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 1922 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 1923 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1924 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 1925 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 1926 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 1927 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 1928 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 1929 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 1930 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 1931 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 1932 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 1933 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 1934 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 1935 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 1936 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 1937 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 1938 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1939 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 1940 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 1941 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1942 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 1943 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 1944 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 1945 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 1946 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 1947 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 1948 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 1949 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 1950 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 1951 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 1952 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 1953 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 1954 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 1955 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 1956 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 1957 1958 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1959 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1960 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1961 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1962 caps->mtt_ba_pg_sz = 0; 1963 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1964 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1965 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1966 1967 caps->qpc_hop_num = ctx_hop_num; 1968 caps->srqc_hop_num = ctx_hop_num; 1969 caps->cqc_hop_num = ctx_hop_num; 1970 caps->mpt_hop_num = ctx_hop_num; 1971 caps->mtt_hop_num = pbl_hop_num; 1972 caps->cqe_hop_num = pbl_hop_num; 1973 caps->srqwqe_hop_num = pbl_hop_num; 1974 caps->idx_hop_num = pbl_hop_num; 1975 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1976 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 1977 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 1978 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1979 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 1980 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 1981 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1982 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 1983 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 1984 1985 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num, 1986 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 1987 HEM_TYPE_QPC); 1988 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1989 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1990 HEM_TYPE_MTPT); 1991 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 1992 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 1993 HEM_TYPE_CQC); 1994 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num, 1995 caps->srqc_bt_num, &caps->srqc_buf_pg_sz, 1996 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC); 1997 1998 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { 1999 caps->sccc_hop_num = ctx_hop_num; 2000 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2001 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2002 2003 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz, 2004 caps->sccc_hop_num, caps->sccc_bt_num, 2005 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz, 2006 HEM_TYPE_SCCC); 2007 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, 2008 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, 2009 &caps->cqc_timer_buf_pg_sz, 2010 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); 2011 } 2012 2013 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num, 2014 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2015 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2016 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2017 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2018 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num, 2019 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2020 2021 return 0; 2022 } 2023 2024 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2025 { 2026 struct hns_roce_caps *caps = &hr_dev->caps; 2027 int ret; 2028 2029 ret = hns_roce_cmq_query_hw_info(hr_dev); 2030 if (ret) { 2031 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n", 2032 ret); 2033 return ret; 2034 } 2035 2036 ret = hns_roce_query_fw_ver(hr_dev); 2037 if (ret) { 2038 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 2039 ret); 2040 return ret; 2041 } 2042 2043 ret = hns_roce_config_global_param(hr_dev); 2044 if (ret) { 2045 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 2046 ret); 2047 return ret; 2048 } 2049 2050 /* Get pf resource owned by every pf */ 2051 ret = hns_roce_query_pf_resource(hr_dev); 2052 if (ret) { 2053 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 2054 ret); 2055 return ret; 2056 } 2057 2058 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { 2059 ret = hns_roce_query_pf_timer_resource(hr_dev); 2060 if (ret) { 2061 dev_err(hr_dev->dev, 2062 "Query pf timer resource fail, ret = %d.\n", 2063 ret); 2064 return ret; 2065 } 2066 2067 ret = hns_roce_set_vf_switch_param(hr_dev, 0); 2068 if (ret) { 2069 dev_err(hr_dev->dev, 2070 "Set function switch param fail, ret = %d.\n", 2071 ret); 2072 return ret; 2073 } 2074 } 2075 2076 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2077 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2078 2079 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2080 caps->pbl_buf_pg_sz = 0; 2081 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2082 caps->eqe_ba_pg_sz = 0; 2083 caps->eqe_buf_pg_sz = 0; 2084 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2085 caps->tsq_buf_pg_sz = 0; 2086 2087 ret = hns_roce_query_pf_caps(hr_dev); 2088 if (ret) 2089 set_default_caps(hr_dev); 2090 2091 ret = hns_roce_alloc_vf_resource(hr_dev); 2092 if (ret) { 2093 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 2094 ret); 2095 return ret; 2096 } 2097 2098 ret = hns_roce_v2_set_bt(hr_dev); 2099 if (ret) 2100 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 2101 ret); 2102 2103 return ret; 2104 } 2105 2106 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, 2107 enum hns_roce_link_table_type type) 2108 { 2109 struct hns_roce_cmq_desc desc[2]; 2110 struct hns_roce_cfg_llm_a *req_a = 2111 (struct hns_roce_cfg_llm_a *)desc[0].data; 2112 struct hns_roce_cfg_llm_b *req_b = 2113 (struct hns_roce_cfg_llm_b *)desc[1].data; 2114 struct hns_roce_v2_priv *priv = hr_dev->priv; 2115 struct hns_roce_link_table *link_tbl; 2116 struct hns_roce_link_table_entry *entry; 2117 enum hns_roce_opcode_type opcode; 2118 u32 page_num; 2119 int i; 2120 2121 switch (type) { 2122 case TSQ_LINK_TABLE: 2123 link_tbl = &priv->tsq; 2124 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2125 break; 2126 case TPQ_LINK_TABLE: 2127 link_tbl = &priv->tpq; 2128 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; 2129 break; 2130 default: 2131 return -EINVAL; 2132 } 2133 2134 page_num = link_tbl->npages; 2135 entry = link_tbl->table.buf; 2136 2137 for (i = 0; i < 2; i++) { 2138 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false); 2139 2140 if (i == 0) 2141 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2142 else 2143 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2144 } 2145 2146 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff); 2147 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32); 2148 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M, 2149 CFG_LLM_QUE_DEPTH_S, link_tbl->npages); 2150 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M, 2151 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz); 2152 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M, 2153 CFG_LLM_INIT_EN_S, 1); 2154 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0); 2155 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr); 2156 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S, 2157 0); 2158 2159 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0); 2160 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M, 2161 CFG_LLM_TAIL_BA_H_S, 2162 entry[page_num - 1].blk_ba1_nxt_ptr & 2163 HNS_ROCE_LINK_TABLE_BA1_M); 2164 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S, 2165 (entry[page_num - 2].blk_ba1_nxt_ptr & 2166 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> 2167 HNS_ROCE_LINK_TABLE_NXT_PTR_S); 2168 2169 return hns_roce_cmq_send(hr_dev, desc, 2); 2170 } 2171 2172 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, 2173 enum hns_roce_link_table_type type) 2174 { 2175 struct hns_roce_v2_priv *priv = hr_dev->priv; 2176 struct hns_roce_link_table *link_tbl; 2177 struct hns_roce_link_table_entry *entry; 2178 struct device *dev = hr_dev->dev; 2179 u32 buf_chk_sz; 2180 dma_addr_t t; 2181 int func_num = 1; 2182 int pg_num_a; 2183 int pg_num_b; 2184 int pg_num; 2185 int size; 2186 int i; 2187 2188 switch (type) { 2189 case TSQ_LINK_TABLE: 2190 link_tbl = &priv->tsq; 2191 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); 2192 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; 2193 pg_num_b = hr_dev->caps.sl_num * 4 + 2; 2194 break; 2195 case TPQ_LINK_TABLE: 2196 link_tbl = &priv->tpq; 2197 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); 2198 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; 2199 pg_num_b = 2 * 4 * func_num + 2; 2200 break; 2201 default: 2202 return -EINVAL; 2203 } 2204 2205 pg_num = max(pg_num_a, pg_num_b); 2206 size = pg_num * sizeof(struct hns_roce_link_table_entry); 2207 2208 link_tbl->table.buf = dma_alloc_coherent(dev, size, 2209 &link_tbl->table.map, 2210 GFP_KERNEL); 2211 if (!link_tbl->table.buf) 2212 goto out; 2213 2214 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), 2215 GFP_KERNEL); 2216 if (!link_tbl->pg_list) 2217 goto err_kcalloc_failed; 2218 2219 entry = link_tbl->table.buf; 2220 for (i = 0; i < pg_num; ++i) { 2221 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, 2222 &t, GFP_KERNEL); 2223 if (!link_tbl->pg_list[i].buf) 2224 goto err_alloc_buf_failed; 2225 2226 link_tbl->pg_list[i].map = t; 2227 2228 entry[i].blk_ba0 = (u32)(t >> 12); 2229 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44); 2230 2231 if (i < (pg_num - 1)) 2232 entry[i].blk_ba1_nxt_ptr |= 2233 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S; 2234 2235 } 2236 link_tbl->npages = pg_num; 2237 link_tbl->pg_sz = buf_chk_sz; 2238 2239 return hns_roce_config_link_table(hr_dev, type); 2240 2241 err_alloc_buf_failed: 2242 for (i -= 1; i >= 0; i--) 2243 dma_free_coherent(dev, buf_chk_sz, 2244 link_tbl->pg_list[i].buf, 2245 link_tbl->pg_list[i].map); 2246 kfree(link_tbl->pg_list); 2247 2248 err_kcalloc_failed: 2249 dma_free_coherent(dev, size, link_tbl->table.buf, 2250 link_tbl->table.map); 2251 2252 out: 2253 return -ENOMEM; 2254 } 2255 2256 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, 2257 struct hns_roce_link_table *link_tbl) 2258 { 2259 struct device *dev = hr_dev->dev; 2260 int size; 2261 int i; 2262 2263 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); 2264 2265 for (i = 0; i < link_tbl->npages; ++i) 2266 if (link_tbl->pg_list[i].buf) 2267 dma_free_coherent(dev, link_tbl->pg_sz, 2268 link_tbl->pg_list[i].buf, 2269 link_tbl->pg_list[i].map); 2270 kfree(link_tbl->pg_list); 2271 2272 dma_free_coherent(dev, size, link_tbl->table.buf, 2273 link_tbl->table.map); 2274 } 2275 2276 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2277 { 2278 struct hns_roce_v2_priv *priv = hr_dev->priv; 2279 int qpc_count, cqc_count; 2280 int ret, i; 2281 2282 /* TSQ includes SQ doorbell and ack doorbell */ 2283 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); 2284 if (ret) { 2285 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret); 2286 return ret; 2287 } 2288 2289 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); 2290 if (ret) { 2291 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret); 2292 goto err_tpq_init_failed; 2293 } 2294 2295 /* Alloc memory for QPC Timer buffer space chunk */ 2296 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2297 qpc_count++) { 2298 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2299 qpc_count); 2300 if (ret) { 2301 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2302 goto err_qpc_timer_failed; 2303 } 2304 } 2305 2306 /* Alloc memory for CQC Timer buffer space chunk */ 2307 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2308 cqc_count++) { 2309 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2310 cqc_count); 2311 if (ret) { 2312 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2313 goto err_cqc_timer_failed; 2314 } 2315 } 2316 2317 return 0; 2318 2319 err_cqc_timer_failed: 2320 for (i = 0; i < cqc_count; i++) 2321 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2322 2323 err_qpc_timer_failed: 2324 for (i = 0; i < qpc_count; i++) 2325 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2326 2327 hns_roce_free_link_table(hr_dev, &priv->tpq); 2328 2329 err_tpq_init_failed: 2330 hns_roce_free_link_table(hr_dev, &priv->tsq); 2331 2332 return ret; 2333 } 2334 2335 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2336 { 2337 struct hns_roce_v2_priv *priv = hr_dev->priv; 2338 2339 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) 2340 hns_roce_function_clear(hr_dev); 2341 2342 hns_roce_free_link_table(hr_dev, &priv->tpq); 2343 hns_roce_free_link_table(hr_dev, &priv->tsq); 2344 } 2345 2346 static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev) 2347 { 2348 struct hns_roce_cmq_desc desc; 2349 struct hns_roce_mbox_status *mb_st = 2350 (struct hns_roce_mbox_status *)desc.data; 2351 enum hns_roce_cmd_return_status status; 2352 2353 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true); 2354 2355 status = hns_roce_cmq_send(hr_dev, &desc, 1); 2356 if (status) 2357 return status; 2358 2359 return le32_to_cpu(mb_st->mb_status_hw_run); 2360 } 2361 2362 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 2363 { 2364 u32 status = hns_roce_query_mbox_status(hr_dev); 2365 2366 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 2367 } 2368 2369 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 2370 { 2371 u32 status = hns_roce_query_mbox_status(hr_dev); 2372 2373 return status & HNS_ROCE_HW_MB_STATUS_MASK; 2374 } 2375 2376 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2377 u64 out_param, u32 in_modifier, u8 op_modifier, 2378 u16 op, u16 token, int event) 2379 { 2380 struct hns_roce_cmq_desc desc; 2381 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2382 2383 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2384 2385 mb->in_param_l = cpu_to_le32(in_param); 2386 mb->in_param_h = cpu_to_le32(in_param >> 32); 2387 mb->out_param_l = cpu_to_le32(out_param); 2388 mb->out_param_h = cpu_to_le32(out_param >> 32); 2389 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2390 mb->token_event_en = cpu_to_le32(event << 16 | token); 2391 2392 return hns_roce_cmq_send(hr_dev, &desc, 1); 2393 } 2394 2395 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2396 u64 out_param, u32 in_modifier, u8 op_modifier, 2397 u16 op, u16 token, int event) 2398 { 2399 struct device *dev = hr_dev->dev; 2400 unsigned long end; 2401 int ret; 2402 2403 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 2404 while (hns_roce_v2_cmd_pending(hr_dev)) { 2405 if (time_after(jiffies, end)) { 2406 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 2407 (int)end); 2408 return -EAGAIN; 2409 } 2410 cond_resched(); 2411 } 2412 2413 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2414 op_modifier, op, token, event); 2415 if (ret) 2416 dev_err(dev, "Post mailbox fail(%d)\n", ret); 2417 2418 return ret; 2419 } 2420 2421 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 2422 unsigned long timeout) 2423 { 2424 struct device *dev = hr_dev->dev; 2425 unsigned long end; 2426 u32 status; 2427 2428 end = msecs_to_jiffies(timeout) + jiffies; 2429 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 2430 cond_resched(); 2431 2432 if (hns_roce_v2_cmd_pending(hr_dev)) { 2433 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 2434 return -ETIMEDOUT; 2435 } 2436 2437 status = hns_roce_v2_cmd_complete(hr_dev); 2438 if (status != 0x1) { 2439 if (status == CMD_RST_PRC_EBUSY) 2440 return status; 2441 2442 dev_err(dev, "mailbox status 0x%x!\n", status); 2443 return -EBUSY; 2444 } 2445 2446 return 0; 2447 } 2448 2449 static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev, 2450 int gid_index, const union ib_gid *gid, 2451 enum hns_roce_sgid_type sgid_type) 2452 { 2453 struct hns_roce_cmq_desc desc; 2454 struct hns_roce_cfg_sgid_tb *sgid_tb = 2455 (struct hns_roce_cfg_sgid_tb *)desc.data; 2456 u32 *p; 2457 2458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2459 2460 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2461 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2462 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2463 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2464 2465 p = (u32 *)&gid->raw[0]; 2466 sgid_tb->vf_sgid_l = cpu_to_le32(*p); 2467 2468 p = (u32 *)&gid->raw[4]; 2469 sgid_tb->vf_sgid_ml = cpu_to_le32(*p); 2470 2471 p = (u32 *)&gid->raw[8]; 2472 sgid_tb->vf_sgid_mh = cpu_to_le32(*p); 2473 2474 p = (u32 *)&gid->raw[0xc]; 2475 sgid_tb->vf_sgid_h = cpu_to_le32(*p); 2476 2477 return hns_roce_cmq_send(hr_dev, &desc, 1); 2478 } 2479 2480 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 2481 int gid_index, const union ib_gid *gid, 2482 const struct ib_gid_attr *attr) 2483 { 2484 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2485 int ret; 2486 2487 if (!gid || !attr) 2488 return -EINVAL; 2489 2490 if (attr->gid_type == IB_GID_TYPE_ROCE) 2491 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2492 2493 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2494 if (ipv6_addr_v4mapped((void *)gid)) 2495 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2496 else 2497 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2498 } 2499 2500 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2501 if (ret) 2502 ibdev_err(&hr_dev->ib_dev, 2503 "failed to configure sgid table, ret = %d!\n", 2504 ret); 2505 2506 return ret; 2507 } 2508 2509 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2510 u8 *addr) 2511 { 2512 struct hns_roce_cmq_desc desc; 2513 struct hns_roce_cfg_smac_tb *smac_tb = 2514 (struct hns_roce_cfg_smac_tb *)desc.data; 2515 u16 reg_smac_h; 2516 u32 reg_smac_l; 2517 2518 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 2519 2520 reg_smac_l = *(u32 *)(&addr[0]); 2521 reg_smac_h = *(u16 *)(&addr[4]); 2522 2523 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 2524 CFG_SMAC_TB_IDX_S, phy_port); 2525 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 2526 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 2527 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 2528 2529 return hns_roce_cmq_send(hr_dev, &desc, 1); 2530 } 2531 2532 static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry, 2533 struct hns_roce_mr *mr) 2534 { 2535 struct hns_roce_dev *hr_dev = to_hr_dev(mr->ibmr.device); 2536 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 2537 struct ib_device *ibdev = &hr_dev->ib_dev; 2538 dma_addr_t pbl_ba; 2539 int i, count; 2540 2541 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 2542 ARRAY_SIZE(pages), &pbl_ba); 2543 if (count < 1) { 2544 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 2545 count); 2546 return -ENOBUFS; 2547 } 2548 2549 /* Aligned to the hardware address access unit */ 2550 for (i = 0; i < count; i++) 2551 pages[i] >>= 6; 2552 2553 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2554 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 2555 roce_set_field(mpt_entry->byte_48_mode_ba, 2556 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 2557 upper_32_bits(pbl_ba >> 3)); 2558 2559 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 2560 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 2561 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 2562 2563 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 2564 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 2565 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 2566 roce_set_field(mpt_entry->byte_64_buf_pa1, 2567 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2568 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2569 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2570 2571 return 0; 2572 } 2573 2574 static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 2575 unsigned long mtpt_idx) 2576 { 2577 struct hns_roce_v2_mpt_entry *mpt_entry; 2578 int ret; 2579 2580 mpt_entry = mb_buf; 2581 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2582 2583 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2584 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2585 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2586 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 2587 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 2588 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2589 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2590 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2591 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2592 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2593 V2_MPT_BYTE_4_PD_S, mr->pd); 2594 2595 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 2596 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0); 2597 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2598 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 2599 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 2600 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 2601 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2602 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2603 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 2604 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2605 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 2606 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2607 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 2608 2609 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 2610 mr->type == MR_TYPE_MR ? 0 : 1); 2611 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, 2612 1); 2613 2614 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 2615 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 2616 mpt_entry->lkey = cpu_to_le32(mr->key); 2617 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 2618 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 2619 2620 if (mr->type == MR_TYPE_DMA) 2621 return 0; 2622 2623 ret = set_mtpt_pbl(mpt_entry, mr); 2624 2625 return ret; 2626 } 2627 2628 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 2629 struct hns_roce_mr *mr, int flags, 2630 u32 pdn, int mr_access_flags, u64 iova, 2631 u64 size, void *mb_buf) 2632 { 2633 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 2634 int ret = 0; 2635 2636 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2637 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2638 2639 if (flags & IB_MR_REREG_PD) { 2640 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2641 V2_MPT_BYTE_4_PD_S, pdn); 2642 mr->pd = pdn; 2643 } 2644 2645 if (flags & IB_MR_REREG_ACCESS) { 2646 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2647 V2_MPT_BYTE_8_BIND_EN_S, 2648 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 2649 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2650 V2_MPT_BYTE_8_ATOMIC_EN_S, 2651 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2652 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2653 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 2654 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2655 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 2656 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2657 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 2658 } 2659 2660 if (flags & IB_MR_REREG_TRANS) { 2661 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 2662 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 2663 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 2664 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 2665 2666 mr->iova = iova; 2667 mr->size = size; 2668 2669 ret = set_mtpt_pbl(mpt_entry, mr); 2670 } 2671 2672 return ret; 2673 } 2674 2675 static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) 2676 { 2677 struct hns_roce_dev *hr_dev = to_hr_dev(mr->ibmr.device); 2678 struct ib_device *ibdev = &hr_dev->ib_dev; 2679 struct hns_roce_v2_mpt_entry *mpt_entry; 2680 dma_addr_t pbl_ba = 0; 2681 2682 mpt_entry = mb_buf; 2683 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2684 2685 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 2686 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 2687 return -ENOBUFS; 2688 } 2689 2690 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2691 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2692 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2693 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 2694 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2695 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2696 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2697 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2698 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2699 V2_MPT_BYTE_4_PD_S, mr->pd); 2700 2701 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 2702 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2703 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2704 2705 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 2706 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2707 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 2708 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2709 2710 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2711 2712 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 2713 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 2714 V2_MPT_BYTE_48_PBL_BA_H_S, 2715 upper_32_bits(pbl_ba >> 3)); 2716 2717 roce_set_field(mpt_entry->byte_64_buf_pa1, 2718 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2719 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2720 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2721 2722 return 0; 2723 } 2724 2725 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 2726 { 2727 struct hns_roce_v2_mpt_entry *mpt_entry; 2728 2729 mpt_entry = mb_buf; 2730 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2731 2732 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2733 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2734 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2735 V2_MPT_BYTE_4_PD_S, mw->pdn); 2736 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2737 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 2738 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 2739 mw->pbl_hop_num); 2740 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2741 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2742 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2743 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 2744 2745 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2746 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2747 2748 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2749 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 2750 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2751 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 2752 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 2753 2754 roce_set_field(mpt_entry->byte_64_buf_pa1, 2755 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2756 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2757 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 2758 2759 mpt_entry->lkey = cpu_to_le32(mw->rkey); 2760 2761 return 0; 2762 } 2763 2764 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2765 { 2766 return hns_roce_buf_offset(hr_cq->mtr.kmem, 2767 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 2768 } 2769 2770 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2771 { 2772 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 2773 2774 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 2775 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 2776 !!(n & hr_cq->cq_depth)) ? cqe : NULL; 2777 } 2778 2779 static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci) 2780 { 2781 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M; 2782 } 2783 2784 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2785 struct hns_roce_srq *srq) 2786 { 2787 struct hns_roce_v2_cqe *cqe, *dest; 2788 u32 prod_index; 2789 int nfreed = 0; 2790 int wqe_index; 2791 u8 owner_bit; 2792 2793 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 2794 ++prod_index) { 2795 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 2796 break; 2797 } 2798 2799 /* 2800 * Now backwards through the CQ, removing CQ entries 2801 * that match our QP by overwriting them with next entries. 2802 */ 2803 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 2804 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 2805 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 2806 V2_CQE_BYTE_16_LCL_QPN_S) & 2807 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 2808 if (srq && 2809 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) { 2810 wqe_index = roce_get_field(cqe->byte_4, 2811 V2_CQE_BYTE_4_WQE_INDX_M, 2812 V2_CQE_BYTE_4_WQE_INDX_S); 2813 hns_roce_free_srq_wqe(srq, wqe_index); 2814 } 2815 ++nfreed; 2816 } else if (nfreed) { 2817 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 2818 hr_cq->ib_cq.cqe); 2819 owner_bit = roce_get_bit(dest->byte_4, 2820 V2_CQE_BYTE_4_OWNER_S); 2821 memcpy(dest, cqe, sizeof(*cqe)); 2822 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 2823 owner_bit); 2824 } 2825 } 2826 2827 if (nfreed) { 2828 hr_cq->cons_index += nfreed; 2829 /* 2830 * Make sure update of buffer contents is done before 2831 * updating consumer index. 2832 */ 2833 wmb(); 2834 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 2835 } 2836 } 2837 2838 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2839 struct hns_roce_srq *srq) 2840 { 2841 spin_lock_irq(&hr_cq->lock); 2842 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 2843 spin_unlock_irq(&hr_cq->lock); 2844 } 2845 2846 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 2847 struct hns_roce_cq *hr_cq, void *mb_buf, 2848 u64 *mtts, dma_addr_t dma_handle) 2849 { 2850 struct hns_roce_v2_cq_context *cq_context; 2851 2852 cq_context = mb_buf; 2853 memset(cq_context, 0, sizeof(*cq_context)); 2854 2855 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 2856 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 2857 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 2858 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 2859 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 2860 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); 2861 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 2862 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); 2863 2864 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 2865 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 2866 2867 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 2868 2869 roce_set_field(cq_context->byte_16_hop_addr, 2870 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 2871 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 2872 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 2873 roce_set_field(cq_context->byte_16_hop_addr, 2874 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 2875 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 2876 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 2877 2878 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 2879 roce_set_field(cq_context->byte_24_pgsz_addr, 2880 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 2881 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 2882 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 2883 roce_set_field(cq_context->byte_24_pgsz_addr, 2884 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 2885 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 2886 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 2887 roce_set_field(cq_context->byte_24_pgsz_addr, 2888 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 2889 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 2890 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 2891 2892 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); 2893 2894 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 2895 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 2896 2897 roce_set_bit(cq_context->byte_44_db_record, 2898 V2_CQC_BYTE_44_DB_RECORD_EN_S, 2899 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0); 2900 2901 roce_set_field(cq_context->byte_44_db_record, 2902 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 2903 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 2904 ((u32)hr_cq->db.dma) >> 1); 2905 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); 2906 2907 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2908 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 2909 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 2910 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 2911 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2912 V2_CQC_BYTE_56_CQ_PERIOD_M, 2913 V2_CQC_BYTE_56_CQ_PERIOD_S, 2914 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 2915 } 2916 2917 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 2918 enum ib_cq_notify_flags flags) 2919 { 2920 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 2921 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 2922 u32 notification_flag; 2923 __le32 doorbell[2]; 2924 2925 doorbell[0] = 0; 2926 doorbell[1] = 0; 2927 2928 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 2929 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 2930 /* 2931 * flags = 0; Notification Flag = 1, next 2932 * flags = 1; Notification Flag = 0, solocited 2933 */ 2934 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 2935 hr_cq->cqn); 2936 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 2937 HNS_ROCE_V2_CQ_DB_NTR); 2938 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 2939 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index); 2940 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 2941 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 2942 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 2943 notification_flag); 2944 2945 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l); 2946 2947 return 0; 2948 } 2949 2950 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 2951 struct hns_roce_qp **cur_qp, 2952 struct ib_wc *wc) 2953 { 2954 struct hns_roce_rinl_sge *sge_list; 2955 u32 wr_num, wr_cnt, sge_num; 2956 u32 sge_cnt, data_len, size; 2957 void *wqe_buf; 2958 2959 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 2960 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 2961 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 2962 2963 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 2964 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 2965 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt); 2966 data_len = wc->byte_len; 2967 2968 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 2969 size = min(sge_list[sge_cnt].len, data_len); 2970 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 2971 2972 data_len -= size; 2973 wqe_buf += size; 2974 } 2975 2976 if (unlikely(data_len)) { 2977 wc->status = IB_WC_LOC_LEN_ERR; 2978 return -EAGAIN; 2979 } 2980 2981 return 0; 2982 } 2983 2984 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 2985 int num_entries, struct ib_wc *wc) 2986 { 2987 unsigned int left; 2988 int npolled = 0; 2989 2990 left = wq->head - wq->tail; 2991 if (left == 0) 2992 return 0; 2993 2994 left = min_t(unsigned int, (unsigned int)num_entries, left); 2995 while (npolled < left) { 2996 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 2997 wc->status = IB_WC_WR_FLUSH_ERR; 2998 wc->vendor_err = 0; 2999 wc->qp = &hr_qp->ibqp; 3000 3001 wq->tail++; 3002 wc++; 3003 npolled++; 3004 } 3005 3006 return npolled; 3007 } 3008 3009 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3010 struct ib_wc *wc) 3011 { 3012 struct hns_roce_qp *hr_qp; 3013 int npolled = 0; 3014 3015 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3016 npolled += sw_comp(hr_qp, &hr_qp->sq, 3017 num_entries - npolled, wc + npolled); 3018 if (npolled >= num_entries) 3019 goto out; 3020 } 3021 3022 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3023 npolled += sw_comp(hr_qp, &hr_qp->rq, 3024 num_entries - npolled, wc + npolled); 3025 if (npolled >= num_entries) 3026 goto out; 3027 } 3028 3029 out: 3030 return npolled; 3031 } 3032 3033 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3034 struct hns_roce_v2_cqe *cqe, struct ib_wc *wc) 3035 { 3036 static const struct { 3037 u32 cqe_status; 3038 enum ib_wc_status wc_status; 3039 } map[] = { 3040 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3041 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3042 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3043 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3044 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3045 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3046 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3047 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3048 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3049 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3050 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3051 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3052 IB_WC_RETRY_EXC_ERR }, 3053 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3054 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3055 }; 3056 3057 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 3058 V2_CQE_BYTE_4_STATUS_S); 3059 int i; 3060 3061 wc->status = IB_WC_GENERAL_ERR; 3062 for (i = 0; i < ARRAY_SIZE(map); i++) 3063 if (cqe_status == map[i].cqe_status) { 3064 wc->status = map[i].wc_status; 3065 break; 3066 } 3067 3068 if (likely(wc->status == IB_WC_SUCCESS || 3069 wc->status == IB_WC_WR_FLUSH_ERR)) 3070 return; 3071 3072 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3073 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3074 sizeof(*cqe), false); 3075 3076 /* 3077 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets 3078 * into errored mode. Hence, as a workaround to this hardware 3079 * limitation, driver needs to assist in flushing. But the flushing 3080 * operation uses mailbox to convey the QP state to the hardware and 3081 * which can sleep due to the mutex protection around the mailbox calls. 3082 * Hence, use the deferred flush for now. Once wc error detected, the 3083 * flushing operation is needed. 3084 */ 3085 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 3086 init_flush_work(hr_dev, qp); 3087 } 3088 3089 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3090 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3091 { 3092 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3093 struct hns_roce_srq *srq = NULL; 3094 struct hns_roce_v2_cqe *cqe; 3095 struct hns_roce_qp *hr_qp; 3096 struct hns_roce_wq *wq; 3097 int is_send; 3098 u16 wqe_ctr; 3099 u32 opcode; 3100 int qpn; 3101 int ret; 3102 3103 /* Find cqe according to consumer index */ 3104 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3105 if (!cqe) 3106 return -EAGAIN; 3107 3108 ++hr_cq->cons_index; 3109 /* Memory barrier */ 3110 rmb(); 3111 3112 /* 0->SQ, 1->RQ */ 3113 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 3114 3115 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 3116 V2_CQE_BYTE_16_LCL_QPN_S); 3117 3118 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 3119 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3120 if (unlikely(!hr_qp)) { 3121 ibdev_err(&hr_dev->ib_dev, 3122 "CQ %06lx with entry for unknown QPN %06x\n", 3123 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK); 3124 return -EINVAL; 3125 } 3126 *cur_qp = hr_qp; 3127 } 3128 3129 wc->qp = &(*cur_qp)->ibqp; 3130 wc->vendor_err = 0; 3131 3132 if (is_send) { 3133 wq = &(*cur_qp)->sq; 3134 if ((*cur_qp)->sq_signal_bits) { 3135 /* 3136 * If sg_signal_bit is 1, 3137 * firstly tail pointer updated to wqe 3138 * which current cqe correspond to 3139 */ 3140 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3141 V2_CQE_BYTE_4_WQE_INDX_M, 3142 V2_CQE_BYTE_4_WQE_INDX_S); 3143 wq->tail += (wqe_ctr - (u16)wq->tail) & 3144 (wq->wqe_cnt - 1); 3145 } 3146 3147 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3148 ++wq->tail; 3149 } else if ((*cur_qp)->ibqp.srq) { 3150 srq = to_hr_srq((*cur_qp)->ibqp.srq); 3151 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3152 V2_CQE_BYTE_4_WQE_INDX_M, 3153 V2_CQE_BYTE_4_WQE_INDX_S); 3154 wc->wr_id = srq->wrid[wqe_ctr]; 3155 hns_roce_free_srq_wqe(srq, wqe_ctr); 3156 } else { 3157 /* Update tail pointer, record wr_id */ 3158 wq = &(*cur_qp)->rq; 3159 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3160 ++wq->tail; 3161 } 3162 3163 get_cqe_status(hr_dev, *cur_qp, cqe, wc); 3164 if (unlikely(wc->status != IB_WC_SUCCESS)) 3165 return 0; 3166 3167 if (is_send) { 3168 wc->wc_flags = 0; 3169 /* SQ corresponding to CQE */ 3170 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3171 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 3172 case HNS_ROCE_SQ_OPCODE_SEND: 3173 wc->opcode = IB_WC_SEND; 3174 break; 3175 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: 3176 wc->opcode = IB_WC_SEND; 3177 break; 3178 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: 3179 wc->opcode = IB_WC_SEND; 3180 wc->wc_flags |= IB_WC_WITH_IMM; 3181 break; 3182 case HNS_ROCE_SQ_OPCODE_RDMA_READ: 3183 wc->opcode = IB_WC_RDMA_READ; 3184 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3185 break; 3186 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: 3187 wc->opcode = IB_WC_RDMA_WRITE; 3188 break; 3189 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: 3190 wc->opcode = IB_WC_RDMA_WRITE; 3191 wc->wc_flags |= IB_WC_WITH_IMM; 3192 break; 3193 case HNS_ROCE_SQ_OPCODE_LOCAL_INV: 3194 wc->opcode = IB_WC_LOCAL_INV; 3195 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3196 break; 3197 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: 3198 wc->opcode = IB_WC_COMP_SWAP; 3199 wc->byte_len = 8; 3200 break; 3201 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: 3202 wc->opcode = IB_WC_FETCH_ADD; 3203 wc->byte_len = 8; 3204 break; 3205 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: 3206 wc->opcode = IB_WC_MASKED_COMP_SWAP; 3207 wc->byte_len = 8; 3208 break; 3209 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: 3210 wc->opcode = IB_WC_MASKED_FETCH_ADD; 3211 wc->byte_len = 8; 3212 break; 3213 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: 3214 wc->opcode = IB_WC_REG_MR; 3215 break; 3216 case HNS_ROCE_SQ_OPCODE_BIND_MW: 3217 wc->opcode = IB_WC_REG_MR; 3218 break; 3219 default: 3220 wc->status = IB_WC_GENERAL_ERR; 3221 break; 3222 } 3223 } else { 3224 /* RQ correspond to CQE */ 3225 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3226 3227 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3228 V2_CQE_BYTE_4_OPCODE_S); 3229 switch (opcode & 0x1f) { 3230 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3231 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3232 wc->wc_flags = IB_WC_WITH_IMM; 3233 wc->ex.imm_data = 3234 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3235 break; 3236 case HNS_ROCE_V2_OPCODE_SEND: 3237 wc->opcode = IB_WC_RECV; 3238 wc->wc_flags = 0; 3239 break; 3240 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3241 wc->opcode = IB_WC_RECV; 3242 wc->wc_flags = IB_WC_WITH_IMM; 3243 wc->ex.imm_data = 3244 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3245 break; 3246 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3247 wc->opcode = IB_WC_RECV; 3248 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3249 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3250 break; 3251 default: 3252 wc->status = IB_WC_GENERAL_ERR; 3253 break; 3254 } 3255 3256 if ((wc->qp->qp_type == IB_QPT_RC || 3257 wc->qp->qp_type == IB_QPT_UC) && 3258 (opcode == HNS_ROCE_V2_OPCODE_SEND || 3259 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3260 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3261 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 3262 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 3263 if (unlikely(ret)) 3264 return -EAGAIN; 3265 } 3266 3267 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 3268 V2_CQE_BYTE_32_SL_S); 3269 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 3270 V2_CQE_BYTE_32_RMT_QPN_M, 3271 V2_CQE_BYTE_32_RMT_QPN_S); 3272 wc->slid = 0; 3273 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 3274 V2_CQE_BYTE_32_GRH_S) ? 3275 IB_WC_GRH : 0); 3276 wc->port_num = roce_get_field(cqe->byte_32, 3277 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 3278 wc->pkey_index = 0; 3279 3280 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) { 3281 wc->vlan_id = (u16)roce_get_field(cqe->byte_28, 3282 V2_CQE_BYTE_28_VID_M, 3283 V2_CQE_BYTE_28_VID_S); 3284 wc->wc_flags |= IB_WC_WITH_VLAN; 3285 } else { 3286 wc->vlan_id = 0xffff; 3287 } 3288 3289 wc->network_hdr_type = roce_get_field(cqe->byte_28, 3290 V2_CQE_BYTE_28_PORT_TYPE_M, 3291 V2_CQE_BYTE_28_PORT_TYPE_S); 3292 } 3293 3294 return 0; 3295 } 3296 3297 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3298 struct ib_wc *wc) 3299 { 3300 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3301 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3302 struct hns_roce_qp *cur_qp = NULL; 3303 unsigned long flags; 3304 int npolled; 3305 3306 spin_lock_irqsave(&hr_cq->lock, flags); 3307 3308 /* 3309 * When the device starts to reset, the state is RST_DOWN. At this time, 3310 * there may still be some valid CQEs in the hardware that are not 3311 * polled. Therefore, it is not allowed to switch to the software mode 3312 * immediately. When the state changes to UNINIT, CQE no longer exists 3313 * in the hardware, and then switch to software mode. 3314 */ 3315 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3316 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3317 goto out; 3318 } 3319 3320 for (npolled = 0; npolled < num_entries; ++npolled) { 3321 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3322 break; 3323 } 3324 3325 if (npolled) { 3326 /* Memory barrier */ 3327 wmb(); 3328 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 3329 } 3330 3331 out: 3332 spin_unlock_irqrestore(&hr_cq->lock, flags); 3333 3334 return npolled; 3335 } 3336 3337 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3338 int step_idx) 3339 { 3340 int op; 3341 3342 if (type == HEM_TYPE_SCCC && step_idx) 3343 return -EINVAL; 3344 3345 switch (type) { 3346 case HEM_TYPE_QPC: 3347 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3348 break; 3349 case HEM_TYPE_MTPT: 3350 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3351 break; 3352 case HEM_TYPE_CQC: 3353 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3354 break; 3355 case HEM_TYPE_SRQC: 3356 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3357 break; 3358 case HEM_TYPE_SCCC: 3359 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3360 break; 3361 case HEM_TYPE_QPC_TIMER: 3362 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3363 break; 3364 case HEM_TYPE_CQC_TIMER: 3365 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3366 break; 3367 default: 3368 dev_warn(hr_dev->dev, 3369 "Table %d not to be written by mailbox!\n", type); 3370 return -EINVAL; 3371 } 3372 3373 return op + step_idx; 3374 } 3375 3376 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3377 struct hns_roce_hem_table *table, int obj, 3378 int step_idx) 3379 { 3380 struct hns_roce_cmd_mailbox *mailbox; 3381 struct hns_roce_hem_iter iter; 3382 struct hns_roce_hem_mhop mhop; 3383 struct hns_roce_hem *hem; 3384 unsigned long mhop_obj = obj; 3385 int i, j, k; 3386 int ret = 0; 3387 u64 hem_idx = 0; 3388 u64 l1_idx = 0; 3389 u64 bt_ba = 0; 3390 u32 chunk_ba_num; 3391 u32 hop_num; 3392 int op; 3393 3394 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3395 return 0; 3396 3397 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3398 i = mhop.l0_idx; 3399 j = mhop.l1_idx; 3400 k = mhop.l2_idx; 3401 hop_num = mhop.hop_num; 3402 chunk_ba_num = mhop.bt_chunk_size / 8; 3403 3404 if (hop_num == 2) { 3405 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3406 k; 3407 l1_idx = i * chunk_ba_num + j; 3408 } else if (hop_num == 1) { 3409 hem_idx = i * chunk_ba_num + j; 3410 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3411 hem_idx = i; 3412 } 3413 3414 op = get_op_for_set_hem(hr_dev, table->type, step_idx); 3415 if (op == -EINVAL) 3416 return 0; 3417 3418 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3419 if (IS_ERR(mailbox)) 3420 return PTR_ERR(mailbox); 3421 3422 if (table->type == HEM_TYPE_SCCC) 3423 obj = mhop.l0_idx; 3424 3425 if (check_whether_last_step(hop_num, step_idx)) { 3426 hem = table->hem[hem_idx]; 3427 for (hns_roce_hem_first(hem, &iter); 3428 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3429 bt_ba = hns_roce_hem_addr(&iter); 3430 3431 /* configure the ba, tag, and op */ 3432 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, 3433 obj, 0, op, 3434 HNS_ROCE_CMD_TIMEOUT_MSECS); 3435 } 3436 } else { 3437 if (step_idx == 0) 3438 bt_ba = table->bt_l0_dma_addr[i]; 3439 else if (step_idx == 1 && hop_num == 2) 3440 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3441 3442 /* configure the ba, tag, and op */ 3443 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 3444 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 3445 } 3446 3447 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3448 return ret; 3449 } 3450 3451 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3452 struct hns_roce_hem_table *table, int obj, 3453 int step_idx) 3454 { 3455 struct device *dev = hr_dev->dev; 3456 struct hns_roce_cmd_mailbox *mailbox; 3457 int ret; 3458 u16 op = 0xff; 3459 3460 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3461 return 0; 3462 3463 switch (table->type) { 3464 case HEM_TYPE_QPC: 3465 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3466 break; 3467 case HEM_TYPE_MTPT: 3468 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3469 break; 3470 case HEM_TYPE_CQC: 3471 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3472 break; 3473 case HEM_TYPE_SCCC: 3474 case HEM_TYPE_QPC_TIMER: 3475 case HEM_TYPE_CQC_TIMER: 3476 break; 3477 case HEM_TYPE_SRQC: 3478 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3479 break; 3480 default: 3481 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 3482 table->type); 3483 return 0; 3484 } 3485 3486 if (table->type == HEM_TYPE_SCCC || 3487 table->type == HEM_TYPE_QPC_TIMER || 3488 table->type == HEM_TYPE_CQC_TIMER) 3489 return 0; 3490 3491 op += step_idx; 3492 3493 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3494 if (IS_ERR(mailbox)) 3495 return PTR_ERR(mailbox); 3496 3497 /* configure the tag and op */ 3498 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3499 HNS_ROCE_CMD_TIMEOUT_MSECS); 3500 3501 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3502 return ret; 3503 } 3504 3505 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3506 struct hns_roce_v2_qp_context *context, 3507 struct hns_roce_qp *hr_qp) 3508 { 3509 struct hns_roce_cmd_mailbox *mailbox; 3510 int ret; 3511 3512 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3513 if (IS_ERR(mailbox)) 3514 return PTR_ERR(mailbox); 3515 3516 memcpy(mailbox->buf, context, sizeof(*context) * 2); 3517 3518 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 3519 HNS_ROCE_CMD_MODIFY_QPC, 3520 HNS_ROCE_CMD_TIMEOUT_MSECS); 3521 3522 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3523 3524 return ret; 3525 } 3526 3527 static void set_access_flags(struct hns_roce_qp *hr_qp, 3528 struct hns_roce_v2_qp_context *context, 3529 struct hns_roce_v2_qp_context *qpc_mask, 3530 const struct ib_qp_attr *attr, int attr_mask) 3531 { 3532 u8 dest_rd_atomic; 3533 u32 access_flags; 3534 3535 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 3536 attr->max_dest_rd_atomic : hr_qp->resp_depth; 3537 3538 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 3539 attr->qp_access_flags : hr_qp->atomic_rd_en; 3540 3541 if (!dest_rd_atomic) 3542 access_flags &= IB_ACCESS_REMOTE_WRITE; 3543 3544 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3545 !!(access_flags & IB_ACCESS_REMOTE_READ)); 3546 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 3547 3548 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3549 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3550 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 3551 3552 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3553 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3554 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 3555 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 3556 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3557 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0); 3558 } 3559 3560 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 3561 struct hns_roce_v2_qp_context *context, 3562 struct hns_roce_v2_qp_context *qpc_mask) 3563 { 3564 roce_set_field(context->byte_4_sqpn_tst, 3565 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S, 3566 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 3567 hr_qp->sge.sge_shift)); 3568 3569 roce_set_field(context->byte_20_smac_sgid_idx, 3570 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 3571 ilog2(hr_qp->sq.wqe_cnt)); 3572 3573 roce_set_field(context->byte_20_smac_sgid_idx, 3574 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 3575 ilog2(hr_qp->rq.wqe_cnt)); 3576 } 3577 3578 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 3579 const struct ib_qp_attr *attr, 3580 int attr_mask, 3581 struct hns_roce_v2_qp_context *context, 3582 struct hns_roce_v2_qp_context *qpc_mask) 3583 { 3584 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3585 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3586 3587 /* 3588 * In v2 engine, software pass context and context mask to hardware 3589 * when modifying qp. If software need modify some fields in context, 3590 * we should set all bits of the relevant fields in context mask to 3591 * 0 at the same time, else set them to 0x1. 3592 */ 3593 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3594 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3595 3596 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3597 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3598 3599 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3600 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3601 3602 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 3603 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 3604 3605 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 3606 3607 /* No VLAN need to set 0xFFF */ 3608 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 3609 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); 3610 3611 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 3612 roce_set_bit(context->byte_68_rq_db, 3613 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 3614 3615 roce_set_field(context->byte_68_rq_db, 3616 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 3617 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 3618 ((u32)hr_qp->rdb.dma) >> 1); 3619 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32); 3620 3621 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 3622 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 3623 3624 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3625 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3626 if (ibqp->srq) { 3627 roce_set_field(context->byte_76_srqn_op_en, 3628 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3629 to_hr_srq(ibqp->srq)->srqn); 3630 roce_set_bit(context->byte_76_srqn_op_en, 3631 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3632 } 3633 3634 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 3635 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 3636 3637 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); 3638 3639 hr_qp->access_flags = attr->qp_access_flags; 3640 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3641 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3642 } 3643 3644 static void modify_qp_init_to_init(struct ib_qp *ibqp, 3645 const struct ib_qp_attr *attr, int attr_mask, 3646 struct hns_roce_v2_qp_context *context, 3647 struct hns_roce_v2_qp_context *qpc_mask) 3648 { 3649 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3650 3651 /* 3652 * In v2 engine, software pass context and context mask to hardware 3653 * when modifying qp. If software need modify some fields in context, 3654 * we should set all bits of the relevant fields in context mask to 3655 * 0 at the same time, else set them to 0x1. 3656 */ 3657 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3658 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3659 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3660 V2_QPC_BYTE_4_TST_S, 0); 3661 3662 if (attr_mask & IB_QP_ACCESS_FLAGS) { 3663 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3664 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 3665 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3666 0); 3667 3668 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3669 !!(attr->qp_access_flags & 3670 IB_ACCESS_REMOTE_WRITE)); 3671 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3672 0); 3673 3674 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3675 !!(attr->qp_access_flags & 3676 IB_ACCESS_REMOTE_ATOMIC)); 3677 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3678 0); 3679 roce_set_bit(context->byte_76_srqn_op_en, 3680 V2_QPC_BYTE_76_EXT_ATE_S, 3681 !!(attr->qp_access_flags & 3682 IB_ACCESS_REMOTE_ATOMIC)); 3683 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3684 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3685 } else { 3686 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3687 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 3688 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3689 0); 3690 3691 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3692 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 3693 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3694 0); 3695 3696 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3697 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3698 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3699 0); 3700 roce_set_bit(context->byte_76_srqn_op_en, 3701 V2_QPC_BYTE_76_EXT_ATE_S, 3702 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3703 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3704 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3705 } 3706 3707 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3708 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3709 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3710 V2_QPC_BYTE_16_PD_S, 0); 3711 3712 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3713 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3714 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3715 V2_QPC_BYTE_80_RX_CQN_S, 0); 3716 3717 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3718 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3719 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3720 V2_QPC_BYTE_252_TX_CQN_S, 0); 3721 3722 if (ibqp->srq) { 3723 roce_set_bit(context->byte_76_srqn_op_en, 3724 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3725 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3726 V2_QPC_BYTE_76_SRQ_EN_S, 0); 3727 roce_set_field(context->byte_76_srqn_op_en, 3728 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3729 to_hr_srq(ibqp->srq)->srqn); 3730 roce_set_field(qpc_mask->byte_76_srqn_op_en, 3731 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 3732 } 3733 3734 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3735 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3736 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3737 V2_QPC_BYTE_4_SQPN_S, 0); 3738 3739 if (attr_mask & IB_QP_DEST_QPN) { 3740 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 3741 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 3742 roce_set_field(qpc_mask->byte_56_dqpn_err, 3743 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 3744 } 3745 } 3746 3747 static bool check_wqe_rq_mtt_count(struct hns_roce_dev *hr_dev, 3748 struct hns_roce_qp *hr_qp, int mtt_cnt, 3749 u32 page_size) 3750 { 3751 struct ib_device *ibdev = &hr_dev->ib_dev; 3752 3753 if (hr_qp->rq.wqe_cnt < 1) 3754 return true; 3755 3756 if (mtt_cnt < 1) { 3757 ibdev_err(ibdev, "failed to find RQWQE buf ba of QP(0x%lx)\n", 3758 hr_qp->qpn); 3759 return false; 3760 } 3761 3762 if (mtt_cnt < MTT_MIN_COUNT && 3763 (hr_qp->rq.offset + page_size) < hr_qp->buff_size) { 3764 ibdev_err(ibdev, 3765 "failed to find next RQWQE buf ba of QP(0x%lx)\n", 3766 hr_qp->qpn); 3767 return false; 3768 } 3769 3770 return true; 3771 } 3772 3773 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 3774 struct hns_roce_qp *hr_qp, 3775 struct hns_roce_v2_qp_context *context, 3776 struct hns_roce_v2_qp_context *qpc_mask) 3777 { 3778 struct ib_qp *ibqp = &hr_qp->ibqp; 3779 u64 mtts[MTT_MIN_COUNT] = { 0 }; 3780 u64 wqe_sge_ba; 3781 u32 page_size; 3782 int count; 3783 3784 /* Search qp buf's mtts */ 3785 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift; 3786 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 3787 hr_qp->rq.offset / page_size, mtts, 3788 MTT_MIN_COUNT, &wqe_sge_ba); 3789 if (!ibqp->srq) 3790 if (!check_wqe_rq_mtt_count(hr_dev, hr_qp, count, page_size)) 3791 return -EINVAL; 3792 3793 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 3794 qpc_mask->wqe_sge_ba = 0; 3795 3796 /* 3797 * In v2 engine, software pass context and context mask to hardware 3798 * when modifying qp. If software need modify some fields in context, 3799 * we should set all bits of the relevant fields in context mask to 3800 * 0 at the same time, else set them to 0x1. 3801 */ 3802 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3803 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3)); 3804 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3805 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 3806 3807 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3808 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 3809 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 3810 hr_qp->sq.wqe_cnt)); 3811 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3812 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 3813 3814 roce_set_field(context->byte_20_smac_sgid_idx, 3815 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3816 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 3817 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 3818 hr_qp->sge.sge_cnt)); 3819 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3820 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3821 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 3822 3823 roce_set_field(context->byte_20_smac_sgid_idx, 3824 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3825 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 3826 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 3827 hr_qp->rq.wqe_cnt)); 3828 3829 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3830 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3831 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 3832 3833 roce_set_field(context->byte_16_buf_ba_pg_sz, 3834 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3835 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 3836 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 3837 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3838 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3839 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 3840 3841 roce_set_field(context->byte_16_buf_ba_pg_sz, 3842 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3843 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 3844 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 3845 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3846 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3847 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 3848 3849 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 3850 qpc_mask->rq_cur_blk_addr = 0; 3851 3852 roce_set_field(context->byte_92_srq_info, 3853 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3854 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 3855 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3856 roce_set_field(qpc_mask->byte_92_srq_info, 3857 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3858 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 3859 3860 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 3861 qpc_mask->rq_nxt_blk_addr = 0; 3862 3863 roce_set_field(context->byte_104_rq_sge, 3864 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3865 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 3866 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3867 roce_set_field(qpc_mask->byte_104_rq_sge, 3868 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3869 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 3870 3871 roce_set_field(context->byte_84_rq_ci_pi, 3872 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3873 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 3874 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3875 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3876 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 3877 3878 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3879 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 3880 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 3881 3882 return 0; 3883 } 3884 3885 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 3886 struct hns_roce_qp *hr_qp, 3887 struct hns_roce_v2_qp_context *context, 3888 struct hns_roce_v2_qp_context *qpc_mask) 3889 { 3890 struct ib_device *ibdev = &hr_dev->ib_dev; 3891 u64 sge_cur_blk = 0; 3892 u64 sq_cur_blk = 0; 3893 u32 page_size; 3894 int count; 3895 3896 /* search qp buf's mtts */ 3897 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 3898 if (count < 1) { 3899 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 3900 hr_qp->qpn); 3901 return -EINVAL; 3902 } 3903 if (hr_qp->sge.sge_cnt > 0) { 3904 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift; 3905 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 3906 hr_qp->sge.offset / page_size, 3907 &sge_cur_blk, 1, NULL); 3908 if (count < 1) { 3909 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 3910 hr_qp->qpn); 3911 return -EINVAL; 3912 } 3913 } 3914 3915 /* 3916 * In v2 engine, software pass context and context mask to hardware 3917 * when modifying qp. If software need modify some fields in context, 3918 * we should set all bits of the relevant fields in context mask to 3919 * 0 at the same time, else set them to 0x1. 3920 */ 3921 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3922 roce_set_field(context->byte_168_irrl_idx, 3923 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3924 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 3925 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3926 qpc_mask->sq_cur_blk_addr = 0; 3927 roce_set_field(qpc_mask->byte_168_irrl_idx, 3928 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3929 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 3930 3931 context->sq_cur_sge_blk_addr = 3932 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)); 3933 roce_set_field(context->byte_184_irrl_idx, 3934 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3935 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 3936 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 3937 qpc_mask->sq_cur_sge_blk_addr = 0; 3938 roce_set_field(qpc_mask->byte_184_irrl_idx, 3939 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3940 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 3941 3942 context->rx_sq_cur_blk_addr = 3943 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3944 roce_set_field(context->byte_232_irrl_sge, 3945 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3946 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 3947 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3948 qpc_mask->rx_sq_cur_blk_addr = 0; 3949 roce_set_field(qpc_mask->byte_232_irrl_sge, 3950 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3951 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 3952 3953 return 0; 3954 } 3955 3956 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 3957 const struct ib_qp_attr *attr, int attr_mask, 3958 struct hns_roce_v2_qp_context *context, 3959 struct hns_roce_v2_qp_context *qpc_mask) 3960 { 3961 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 3962 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3963 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3964 struct ib_device *ibdev = &hr_dev->ib_dev; 3965 dma_addr_t trrl_ba; 3966 dma_addr_t irrl_ba; 3967 u8 port_num; 3968 u64 *mtts; 3969 u8 *dmac; 3970 u8 *smac; 3971 int port; 3972 int ret; 3973 3974 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 3975 if (ret) { 3976 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 3977 return ret; 3978 } 3979 3980 /* Search IRRL's mtts */ 3981 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 3982 hr_qp->qpn, &irrl_ba); 3983 if (!mtts) { 3984 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 3985 return -EINVAL; 3986 } 3987 3988 /* Search TRRL's mtts */ 3989 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 3990 hr_qp->qpn, &trrl_ba); 3991 if (!mtts) { 3992 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 3993 return -EINVAL; 3994 } 3995 3996 if (attr_mask & IB_QP_ALT_PATH) { 3997 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 3998 attr_mask); 3999 return -EINVAL; 4000 } 4001 4002 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 4003 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4); 4004 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 4005 V2_QPC_BYTE_132_TRRL_BA_S, 0); 4006 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4007 qpc_mask->trrl_ba = 0; 4008 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4009 V2_QPC_BYTE_140_TRRL_BA_S, 4010 (u32)(trrl_ba >> (32 + 16 + 4))); 4011 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4012 V2_QPC_BYTE_140_TRRL_BA_S, 0); 4013 4014 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4015 qpc_mask->irrl_ba = 0; 4016 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4017 V2_QPC_BYTE_208_IRRL_BA_S, 4018 irrl_ba >> (32 + 6)); 4019 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4020 V2_QPC_BYTE_208_IRRL_BA_S, 0); 4021 4022 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 4023 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 4024 4025 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4026 hr_qp->sq_signal_bits); 4027 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4028 0); 4029 4030 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4031 4032 smac = (u8 *)hr_dev->dev_addr[port]; 4033 dmac = (u8 *)attr->ah_attr.roce.dmac; 4034 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4035 if (ether_addr_equal_unaligned(dmac, smac) || 4036 hr_dev->loop_idc == 0x1) { 4037 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 4038 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 4039 } 4040 4041 if (attr_mask & IB_QP_DEST_QPN) { 4042 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 4043 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 4044 roce_set_field(qpc_mask->byte_56_dqpn_err, 4045 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 4046 } 4047 4048 /* Configure GID index */ 4049 port_num = rdma_ah_get_port_num(&attr->ah_attr); 4050 roce_set_field(context->byte_20_smac_sgid_idx, 4051 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4052 hns_get_gid_index(hr_dev, port_num - 1, 4053 grh->sgid_index)); 4054 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4055 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4056 4057 memcpy(&(context->dmac), dmac, sizeof(u32)); 4058 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4059 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 4060 qpc_mask->dmac = 0; 4061 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4062 V2_QPC_BYTE_52_DMAC_S, 0); 4063 4064 /* mtu*(2^LP_PKTN_INI) should not bigger than 1 message length 64kb */ 4065 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4066 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4067 ilog2(hr_dev->caps.max_sq_inline / IB_MTU_4096)); 4068 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4069 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 4070 4071 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4072 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4073 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); 4074 else if (attr_mask & IB_QP_PATH_MTU) 4075 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4076 V2_QPC_BYTE_24_MTU_S, attr->path_mtu); 4077 4078 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4079 V2_QPC_BYTE_24_MTU_S, 0); 4080 4081 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4082 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 4083 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 4084 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 4085 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4086 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 4087 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 4088 4089 context->rq_rnr_timer = 0; 4090 qpc_mask->rq_rnr_timer = 0; 4091 4092 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 4093 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 4094 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 4095 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 4096 4097 /* rocee send 2^lp_sgen_ini segs every time */ 4098 roce_set_field(context->byte_168_irrl_idx, 4099 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4100 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 4101 roce_set_field(qpc_mask->byte_168_irrl_idx, 4102 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4103 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 4104 4105 return 0; 4106 } 4107 4108 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4109 const struct ib_qp_attr *attr, int attr_mask, 4110 struct hns_roce_v2_qp_context *context, 4111 struct hns_roce_v2_qp_context *qpc_mask) 4112 { 4113 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4114 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4115 struct ib_device *ibdev = &hr_dev->ib_dev; 4116 int ret; 4117 4118 /* Not support alternate path and path migration */ 4119 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4120 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4121 return -EINVAL; 4122 } 4123 4124 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4125 if (ret) { 4126 ibdev_err(ibdev, "failed to config sq buf, ret %d\n", ret); 4127 return ret; 4128 } 4129 4130 /* 4131 * Set some fields in context to zero, Because the default values 4132 * of all fields in context are zero, we need not set them to 0 again. 4133 * but we should set the relevant fields of context mask to 0. 4134 */ 4135 roce_set_field(qpc_mask->byte_232_irrl_sge, 4136 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 4137 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 4138 4139 roce_set_field(qpc_mask->byte_240_irrl_tail, 4140 V2_QPC_BYTE_240_RX_ACK_MSN_M, 4141 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 4142 4143 roce_set_field(qpc_mask->byte_248_ack_psn, 4144 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 4145 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 4146 roce_set_bit(qpc_mask->byte_248_ack_psn, 4147 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 4148 roce_set_field(qpc_mask->byte_248_ack_psn, 4149 V2_QPC_BYTE_248_IRRL_PSN_M, 4150 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 4151 4152 roce_set_field(qpc_mask->byte_240_irrl_tail, 4153 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 4154 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 4155 4156 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4157 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 4158 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 4159 4160 roce_set_bit(qpc_mask->byte_248_ack_psn, 4161 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 4162 4163 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 4164 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 4165 4166 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4167 V2_QPC_BYTE_212_LSN_S, 0x100); 4168 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4169 V2_QPC_BYTE_212_LSN_S, 0); 4170 4171 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 4172 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 4173 4174 return 0; 4175 } 4176 4177 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4178 const struct ib_qp_attr *attr, 4179 int attr_mask, 4180 struct hns_roce_v2_qp_context *context, 4181 struct hns_roce_v2_qp_context *qpc_mask) 4182 { 4183 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4184 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4185 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4186 struct ib_device *ibdev = &hr_dev->ib_dev; 4187 const struct ib_gid_attr *gid_attr = NULL; 4188 int is_roce_protocol; 4189 u16 vlan_id = 0xffff; 4190 bool is_udp = false; 4191 u8 ib_port; 4192 u8 hr_port; 4193 int ret; 4194 4195 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4196 hr_port = ib_port - 1; 4197 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4198 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4199 4200 if (is_roce_protocol) { 4201 gid_attr = attr->ah_attr.grh.sgid_attr; 4202 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4203 if (ret) 4204 return ret; 4205 4206 if (gid_attr) 4207 is_udp = (gid_attr->gid_type == 4208 IB_GID_TYPE_ROCE_UDP_ENCAP); 4209 } 4210 4211 if (vlan_id < VLAN_N_VID) { 4212 roce_set_bit(context->byte_76_srqn_op_en, 4213 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1); 4214 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 4215 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0); 4216 roce_set_bit(context->byte_168_irrl_idx, 4217 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1); 4218 roce_set_bit(qpc_mask->byte_168_irrl_idx, 4219 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0); 4220 } 4221 4222 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4223 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id); 4224 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4225 V2_QPC_BYTE_24_VLAN_ID_S, 0); 4226 4227 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4228 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4229 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4230 return -EINVAL; 4231 } 4232 4233 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4234 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4235 return -EINVAL; 4236 } 4237 4238 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4239 V2_QPC_BYTE_52_UDPSPN_S, 4240 is_udp ? 0x12b7 : 0); 4241 4242 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4243 V2_QPC_BYTE_52_UDPSPN_S, 0); 4244 4245 roce_set_field(context->byte_20_smac_sgid_idx, 4246 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4247 grh->sgid_index); 4248 4249 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4250 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4251 4252 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4253 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 4254 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4255 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 4256 4257 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp) 4258 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4259 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2); 4260 else 4261 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4262 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 4263 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4264 V2_QPC_BYTE_24_TC_S, 0); 4265 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4266 V2_QPC_BYTE_28_FL_S, grh->flow_label); 4267 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4268 V2_QPC_BYTE_28_FL_S, 0); 4269 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4270 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4271 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4272 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 4273 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4274 V2_QPC_BYTE_28_SL_S, 0); 4275 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4276 4277 return 0; 4278 } 4279 4280 static bool check_qp_state(enum ib_qp_state cur_state, 4281 enum ib_qp_state new_state) 4282 { 4283 static const bool sm[][IB_QPS_ERR + 1] = { 4284 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4285 [IB_QPS_INIT] = true }, 4286 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4287 [IB_QPS_INIT] = true, 4288 [IB_QPS_RTR] = true, 4289 [IB_QPS_ERR] = true }, 4290 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4291 [IB_QPS_RTS] = true, 4292 [IB_QPS_ERR] = true }, 4293 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }, 4294 [IB_QPS_SQD] = {}, 4295 [IB_QPS_SQE] = {}, 4296 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4297 }; 4298 4299 return sm[cur_state][new_state]; 4300 } 4301 4302 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4303 const struct ib_qp_attr *attr, 4304 int attr_mask, 4305 enum ib_qp_state cur_state, 4306 enum ib_qp_state new_state, 4307 struct hns_roce_v2_qp_context *context, 4308 struct hns_roce_v2_qp_context *qpc_mask) 4309 { 4310 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4311 int ret = 0; 4312 4313 if (!check_qp_state(cur_state, new_state)) { 4314 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4315 return -EINVAL; 4316 } 4317 4318 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4319 memset(qpc_mask, 0, sizeof(*qpc_mask)); 4320 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4321 qpc_mask); 4322 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4323 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4324 qpc_mask); 4325 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4326 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4327 qpc_mask); 4328 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4329 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4330 qpc_mask); 4331 } 4332 4333 return ret; 4334 } 4335 4336 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4337 const struct ib_qp_attr *attr, 4338 int attr_mask, 4339 struct hns_roce_v2_qp_context *context, 4340 struct hns_roce_v2_qp_context *qpc_mask) 4341 { 4342 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4343 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4344 int ret = 0; 4345 4346 if (attr_mask & IB_QP_AV) { 4347 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4348 qpc_mask); 4349 if (ret) 4350 return ret; 4351 } 4352 4353 if (attr_mask & IB_QP_TIMEOUT) { 4354 if (attr->timeout < 31) { 4355 roce_set_field(context->byte_28_at_fl, 4356 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4357 attr->timeout); 4358 roce_set_field(qpc_mask->byte_28_at_fl, 4359 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4360 0); 4361 } else { 4362 ibdev_warn(&hr_dev->ib_dev, 4363 "Local ACK timeout shall be 0 to 30.\n"); 4364 } 4365 } 4366 4367 if (attr_mask & IB_QP_RETRY_CNT) { 4368 roce_set_field(context->byte_212_lsn, 4369 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4370 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 4371 attr->retry_cnt); 4372 roce_set_field(qpc_mask->byte_212_lsn, 4373 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4374 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 4375 4376 roce_set_field(context->byte_212_lsn, 4377 V2_QPC_BYTE_212_RETRY_CNT_M, 4378 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 4379 roce_set_field(qpc_mask->byte_212_lsn, 4380 V2_QPC_BYTE_212_RETRY_CNT_M, 4381 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 4382 } 4383 4384 if (attr_mask & IB_QP_RNR_RETRY) { 4385 roce_set_field(context->byte_244_rnr_rxack, 4386 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4387 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 4388 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4389 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4390 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 4391 4392 roce_set_field(context->byte_244_rnr_rxack, 4393 V2_QPC_BYTE_244_RNR_CNT_M, 4394 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 4395 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4396 V2_QPC_BYTE_244_RNR_CNT_M, 4397 V2_QPC_BYTE_244_RNR_CNT_S, 0); 4398 } 4399 4400 /* RC&UC&UD required attr */ 4401 if (attr_mask & IB_QP_SQ_PSN) { 4402 roce_set_field(context->byte_172_sq_psn, 4403 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4404 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 4405 roce_set_field(qpc_mask->byte_172_sq_psn, 4406 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4407 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 4408 4409 roce_set_field(context->byte_196_sq_psn, 4410 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4411 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 4412 roce_set_field(qpc_mask->byte_196_sq_psn, 4413 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4414 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 4415 4416 roce_set_field(context->byte_220_retry_psn_msn, 4417 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4418 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 4419 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4420 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4421 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 4422 4423 roce_set_field(context->byte_224_retry_msg, 4424 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4425 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 4426 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S); 4427 roce_set_field(qpc_mask->byte_224_retry_msg, 4428 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4429 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 4430 4431 roce_set_field(context->byte_224_retry_msg, 4432 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4433 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 4434 attr->sq_psn); 4435 roce_set_field(qpc_mask->byte_224_retry_msg, 4436 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4437 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 4438 4439 roce_set_field(context->byte_244_rnr_rxack, 4440 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4441 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 4442 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4443 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4444 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 4445 } 4446 4447 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4448 attr->max_dest_rd_atomic) { 4449 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4450 V2_QPC_BYTE_140_RR_MAX_S, 4451 fls(attr->max_dest_rd_atomic - 1)); 4452 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4453 V2_QPC_BYTE_140_RR_MAX_S, 0); 4454 } 4455 4456 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4457 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 4458 V2_QPC_BYTE_208_SR_MAX_S, 4459 fls(attr->max_rd_atomic - 1)); 4460 roce_set_field(qpc_mask->byte_208_irrl, 4461 V2_QPC_BYTE_208_SR_MAX_M, 4462 V2_QPC_BYTE_208_SR_MAX_S, 0); 4463 } 4464 4465 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4466 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4467 4468 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4469 roce_set_field(context->byte_80_rnr_rx_cqn, 4470 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4471 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 4472 attr->min_rnr_timer); 4473 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 4474 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4475 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 4476 } 4477 4478 /* RC&UC required attr */ 4479 if (attr_mask & IB_QP_RQ_PSN) { 4480 roce_set_field(context->byte_108_rx_reqepsn, 4481 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4482 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 4483 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4484 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4485 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 4486 4487 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 4488 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 4489 roce_set_field(qpc_mask->byte_152_raq, 4490 V2_QPC_BYTE_152_RAQ_PSN_M, 4491 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 4492 } 4493 4494 if (attr_mask & IB_QP_QKEY) { 4495 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4496 qpc_mask->qkey_xrcd = 0; 4497 hr_qp->qkey = attr->qkey; 4498 } 4499 4500 return ret; 4501 } 4502 4503 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4504 const struct ib_qp_attr *attr, 4505 int attr_mask) 4506 { 4507 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4508 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4509 4510 if (attr_mask & IB_QP_ACCESS_FLAGS) 4511 hr_qp->atomic_rd_en = attr->qp_access_flags; 4512 4513 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4514 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4515 if (attr_mask & IB_QP_PORT) { 4516 hr_qp->port = attr->port_num - 1; 4517 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4518 } 4519 } 4520 4521 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4522 const struct ib_qp_attr *attr, 4523 int attr_mask, enum ib_qp_state cur_state, 4524 enum ib_qp_state new_state) 4525 { 4526 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4527 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4528 struct hns_roce_v2_qp_context ctx[2]; 4529 struct hns_roce_v2_qp_context *context = ctx; 4530 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4531 struct ib_device *ibdev = &hr_dev->ib_dev; 4532 unsigned long sq_flag = 0; 4533 unsigned long rq_flag = 0; 4534 int ret; 4535 4536 /* 4537 * In v2 engine, software pass context and context mask to hardware 4538 * when modifying qp. If software need modify some fields in context, 4539 * we should set all bits of the relevant fields in context mask to 4540 * 0 at the same time, else set them to 0x1. 4541 */ 4542 memset(context, 0, sizeof(*context)); 4543 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 4544 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4545 new_state, context, qpc_mask); 4546 if (ret) 4547 goto out; 4548 4549 /* When QP state is err, SQ and RQ WQE should be flushed */ 4550 if (new_state == IB_QPS_ERR) { 4551 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4552 hr_qp->state = IB_QPS_ERR; 4553 roce_set_field(context->byte_160_sq_ci_pi, 4554 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4555 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 4556 hr_qp->sq.head); 4557 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 4558 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4559 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 4560 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4561 4562 if (!ibqp->srq) { 4563 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4564 roce_set_field(context->byte_84_rq_ci_pi, 4565 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4566 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 4567 hr_qp->rq.head); 4568 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4569 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4570 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 4571 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4572 } 4573 } 4574 4575 /* Configure the optional fields */ 4576 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 4577 qpc_mask); 4578 if (ret) 4579 goto out; 4580 4581 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 4582 ibqp->srq ? 1 : 0); 4583 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4584 V2_QPC_BYTE_108_INV_CREDIT_S, 0); 4585 4586 /* Every status migrate must change state */ 4587 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4588 V2_QPC_BYTE_60_QP_ST_S, new_state); 4589 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4590 V2_QPC_BYTE_60_QP_ST_S, 0); 4591 4592 /* SW pass context to HW */ 4593 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp); 4594 if (ret) { 4595 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret); 4596 goto out; 4597 } 4598 4599 hr_qp->state = new_state; 4600 4601 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 4602 4603 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 4604 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 4605 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 4606 if (ibqp->send_cq != ibqp->recv_cq) 4607 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4608 hr_qp->qpn, NULL); 4609 4610 hr_qp->rq.head = 0; 4611 hr_qp->rq.tail = 0; 4612 hr_qp->sq.head = 0; 4613 hr_qp->sq.tail = 0; 4614 hr_qp->next_sge = 0; 4615 if (hr_qp->rq.wqe_cnt) 4616 *hr_qp->rdb.db_record = 0; 4617 } 4618 4619 out: 4620 return ret; 4621 } 4622 4623 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 4624 { 4625 static const enum ib_qp_state map[] = { 4626 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 4627 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 4628 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 4629 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 4630 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 4631 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 4632 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 4633 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 4634 }; 4635 4636 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 4637 } 4638 4639 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 4640 struct hns_roce_qp *hr_qp, 4641 struct hns_roce_v2_qp_context *hr_context) 4642 { 4643 struct hns_roce_cmd_mailbox *mailbox; 4644 int ret; 4645 4646 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4647 if (IS_ERR(mailbox)) 4648 return PTR_ERR(mailbox); 4649 4650 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 4651 HNS_ROCE_CMD_QUERY_QPC, 4652 HNS_ROCE_CMD_TIMEOUT_MSECS); 4653 if (ret) 4654 goto out; 4655 4656 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 4657 4658 out: 4659 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4660 return ret; 4661 } 4662 4663 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4664 int qp_attr_mask, 4665 struct ib_qp_init_attr *qp_init_attr) 4666 { 4667 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4668 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4669 struct hns_roce_v2_qp_context context = {}; 4670 struct ib_device *ibdev = &hr_dev->ib_dev; 4671 int tmp_qp_state; 4672 int state; 4673 int ret; 4674 4675 memset(qp_attr, 0, sizeof(*qp_attr)); 4676 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4677 4678 mutex_lock(&hr_qp->mutex); 4679 4680 if (hr_qp->state == IB_QPS_RESET) { 4681 qp_attr->qp_state = IB_QPS_RESET; 4682 ret = 0; 4683 goto done; 4684 } 4685 4686 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 4687 if (ret) { 4688 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret); 4689 ret = -EINVAL; 4690 goto out; 4691 } 4692 4693 state = roce_get_field(context.byte_60_qpst_tempid, 4694 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 4695 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 4696 if (tmp_qp_state == -1) { 4697 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 4698 ret = -EINVAL; 4699 goto out; 4700 } 4701 hr_qp->state = (u8)tmp_qp_state; 4702 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 4703 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc, 4704 V2_QPC_BYTE_24_MTU_M, 4705 V2_QPC_BYTE_24_MTU_S); 4706 qp_attr->path_mig_state = IB_MIG_ARMED; 4707 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 4708 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 4709 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 4710 4711 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn, 4712 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4713 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 4714 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn, 4715 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4716 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 4717 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err, 4718 V2_QPC_BYTE_56_DQPN_M, 4719 V2_QPC_BYTE_56_DQPN_S); 4720 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en, 4721 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) | 4722 ((roce_get_bit(context.byte_76_srqn_op_en, 4723 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) | 4724 ((roce_get_bit(context.byte_76_srqn_op_en, 4725 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); 4726 4727 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 4728 hr_qp->ibqp.qp_type == IB_QPT_UC) { 4729 struct ib_global_route *grh = 4730 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 4731 4732 rdma_ah_set_sl(&qp_attr->ah_attr, 4733 roce_get_field(context.byte_28_at_fl, 4734 V2_QPC_BYTE_28_SL_M, 4735 V2_QPC_BYTE_28_SL_S)); 4736 grh->flow_label = roce_get_field(context.byte_28_at_fl, 4737 V2_QPC_BYTE_28_FL_M, 4738 V2_QPC_BYTE_28_FL_S); 4739 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx, 4740 V2_QPC_BYTE_20_SGID_IDX_M, 4741 V2_QPC_BYTE_20_SGID_IDX_S); 4742 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc, 4743 V2_QPC_BYTE_24_HOP_LIMIT_M, 4744 V2_QPC_BYTE_24_HOP_LIMIT_S); 4745 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc, 4746 V2_QPC_BYTE_24_TC_M, 4747 V2_QPC_BYTE_24_TC_S); 4748 4749 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 4750 } 4751 4752 qp_attr->port_num = hr_qp->port + 1; 4753 qp_attr->sq_draining = 0; 4754 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl, 4755 V2_QPC_BYTE_208_SR_MAX_M, 4756 V2_QPC_BYTE_208_SR_MAX_S); 4757 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, 4758 V2_QPC_BYTE_140_RR_MAX_M, 4759 V2_QPC_BYTE_140_RR_MAX_S); 4760 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, 4761 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4762 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 4763 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl, 4764 V2_QPC_BYTE_28_AT_M, 4765 V2_QPC_BYTE_28_AT_S); 4766 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn, 4767 V2_QPC_BYTE_212_RETRY_CNT_M, 4768 V2_QPC_BYTE_212_RETRY_CNT_S); 4769 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer); 4770 4771 done: 4772 qp_attr->cur_qp_state = qp_attr->qp_state; 4773 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 4774 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 4775 4776 if (!ibqp->uobject) { 4777 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 4778 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 4779 } else { 4780 qp_attr->cap.max_send_wr = 0; 4781 qp_attr->cap.max_send_sge = 0; 4782 } 4783 4784 qp_init_attr->cap = qp_attr->cap; 4785 4786 out: 4787 mutex_unlock(&hr_qp->mutex); 4788 return ret; 4789 } 4790 4791 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 4792 struct hns_roce_qp *hr_qp, 4793 struct ib_udata *udata) 4794 { 4795 struct ib_device *ibdev = &hr_dev->ib_dev; 4796 struct hns_roce_cq *send_cq, *recv_cq; 4797 unsigned long flags; 4798 int ret = 0; 4799 4800 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 4801 /* Modify qp to reset before destroying qp */ 4802 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 4803 hr_qp->state, IB_QPS_RESET); 4804 if (ret) 4805 ibdev_err(ibdev, 4806 "failed to modify QP to RST, ret = %d\n", 4807 ret); 4808 } 4809 4810 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 4811 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 4812 4813 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 4814 hns_roce_lock_cqs(send_cq, recv_cq); 4815 4816 if (!udata) { 4817 if (recv_cq) 4818 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 4819 (hr_qp->ibqp.srq ? 4820 to_hr_srq(hr_qp->ibqp.srq) : 4821 NULL)); 4822 4823 if (send_cq && send_cq != recv_cq) 4824 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 4825 4826 } 4827 4828 hns_roce_qp_remove(hr_dev, hr_qp); 4829 4830 hns_roce_unlock_cqs(send_cq, recv_cq); 4831 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 4832 4833 return ret; 4834 } 4835 4836 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 4837 { 4838 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4839 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4840 int ret; 4841 4842 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 4843 if (ret) 4844 ibdev_err(&hr_dev->ib_dev, 4845 "failed to destroy QP 0x%06lx, ret = %d\n", 4846 hr_qp->qpn, ret); 4847 4848 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 4849 4850 return 0; 4851 } 4852 4853 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 4854 struct hns_roce_qp *hr_qp) 4855 { 4856 struct ib_device *ibdev = &hr_dev->ib_dev; 4857 struct hns_roce_sccc_clr_done *resp; 4858 struct hns_roce_sccc_clr *clr; 4859 struct hns_roce_cmq_desc desc; 4860 int ret, i; 4861 4862 mutex_lock(&hr_dev->qp_table.scc_mutex); 4863 4864 /* set scc ctx clear done flag */ 4865 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 4866 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4867 if (ret) { 4868 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret); 4869 goto out; 4870 } 4871 4872 /* clear scc context */ 4873 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 4874 clr = (struct hns_roce_sccc_clr *)desc.data; 4875 clr->qpn = cpu_to_le32(hr_qp->qpn); 4876 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4877 if (ret) { 4878 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret); 4879 goto out; 4880 } 4881 4882 /* query scc context clear is done or not */ 4883 resp = (struct hns_roce_sccc_clr_done *)desc.data; 4884 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 4885 hns_roce_cmq_setup_basic_desc(&desc, 4886 HNS_ROCE_OPC_QUERY_SCCC, true); 4887 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4888 if (ret) { 4889 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 4890 ret); 4891 goto out; 4892 } 4893 4894 if (resp->clr_done) 4895 goto out; 4896 4897 msleep(20); 4898 } 4899 4900 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 4901 ret = -ETIMEDOUT; 4902 4903 out: 4904 mutex_unlock(&hr_dev->qp_table.scc_mutex); 4905 return ret; 4906 } 4907 4908 static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev, 4909 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, 4910 u32 cqn, void *mb_buf, u64 *mtts_wqe, 4911 u64 *mtts_idx, dma_addr_t dma_handle_wqe, 4912 dma_addr_t dma_handle_idx) 4913 { 4914 struct hns_roce_srq_context *srq_context; 4915 4916 srq_context = mb_buf; 4917 memset(srq_context, 0, sizeof(*srq_context)); 4918 4919 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M, 4920 SRQC_BYTE_4_SRQ_ST_S, 1); 4921 4922 roce_set_field(srq_context->byte_4_srqn_srqst, 4923 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M, 4924 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S, 4925 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 4926 srq->wqe_cnt)); 4927 roce_set_field(srq_context->byte_4_srqn_srqst, 4928 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S, 4929 ilog2(srq->wqe_cnt)); 4930 4931 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M, 4932 SRQC_BYTE_4_SRQN_S, srq->srqn); 4933 4934 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M, 4935 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 4936 4937 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M, 4938 SRQC_BYTE_12_SRQ_XRCD_S, xrcd); 4939 4940 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3)); 4941 4942 roce_set_field(srq_context->byte_24_wqe_bt_ba, 4943 SRQC_BYTE_24_SRQ_WQE_BT_BA_M, 4944 SRQC_BYTE_24_SRQ_WQE_BT_BA_S, 4945 dma_handle_wqe >> 35); 4946 4947 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M, 4948 SRQC_BYTE_28_PD_S, pdn); 4949 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M, 4950 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 : 4951 fls(srq->max_gs - 1)); 4952 4953 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3); 4954 roce_set_field(srq_context->rsv_idx_bt_ba, 4955 SRQC_BYTE_36_SRQ_IDX_BT_BA_M, 4956 SRQC_BYTE_36_SRQ_IDX_BT_BA_S, 4957 dma_handle_idx >> 35); 4958 4959 srq_context->idx_cur_blk_addr = 4960 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0])); 4961 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4962 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M, 4963 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S, 4964 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 4965 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4966 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M, 4967 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S, 4968 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, 4969 srq->wqe_cnt)); 4970 4971 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4972 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M, 4973 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S, 4974 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift)); 4975 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4976 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M, 4977 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S, 4978 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift)); 4979 4980 srq_context->idx_nxt_blk_addr = 4981 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1])); 4982 roce_set_field(srq_context->rsv_idxnxtblkaddr, 4983 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M, 4984 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S, 4985 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 4986 roce_set_field(srq_context->byte_56_xrc_cqn, 4987 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S, 4988 cqn); 4989 roce_set_field(srq_context->byte_56_xrc_cqn, 4990 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M, 4991 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S, 4992 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 4993 roce_set_field(srq_context->byte_56_xrc_cqn, 4994 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M, 4995 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S, 4996 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 4997 4998 roce_set_bit(srq_context->db_record_addr_record_en, 4999 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0); 5000 } 5001 5002 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5003 struct ib_srq_attr *srq_attr, 5004 enum ib_srq_attr_mask srq_attr_mask, 5005 struct ib_udata *udata) 5006 { 5007 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5008 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5009 struct hns_roce_srq_context *srq_context; 5010 struct hns_roce_srq_context *srqc_mask; 5011 struct hns_roce_cmd_mailbox *mailbox; 5012 int ret; 5013 5014 if (srq_attr_mask & IB_SRQ_LIMIT) { 5015 if (srq_attr->srq_limit >= srq->wqe_cnt) 5016 return -EINVAL; 5017 5018 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5019 if (IS_ERR(mailbox)) 5020 return PTR_ERR(mailbox); 5021 5022 srq_context = mailbox->buf; 5023 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5024 5025 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5026 5027 roce_set_field(srq_context->byte_8_limit_wl, 5028 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5029 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit); 5030 roce_set_field(srqc_mask->byte_8_limit_wl, 5031 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5032 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 5033 5034 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5035 HNS_ROCE_CMD_MODIFY_SRQC, 5036 HNS_ROCE_CMD_TIMEOUT_MSECS); 5037 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5038 if (ret) { 5039 ibdev_err(&hr_dev->ib_dev, 5040 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5041 ret); 5042 return ret; 5043 } 5044 } 5045 5046 return 0; 5047 } 5048 5049 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5050 { 5051 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5052 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5053 struct hns_roce_srq_context *srq_context; 5054 struct hns_roce_cmd_mailbox *mailbox; 5055 int limit_wl; 5056 int ret; 5057 5058 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5059 if (IS_ERR(mailbox)) 5060 return PTR_ERR(mailbox); 5061 5062 srq_context = mailbox->buf; 5063 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5064 HNS_ROCE_CMD_QUERY_SRQC, 5065 HNS_ROCE_CMD_TIMEOUT_MSECS); 5066 if (ret) { 5067 ibdev_err(&hr_dev->ib_dev, 5068 "failed to process cmd of querying SRQ, ret = %d.\n", 5069 ret); 5070 goto out; 5071 } 5072 5073 limit_wl = roce_get_field(srq_context->byte_8_limit_wl, 5074 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5075 SRQC_BYTE_8_SRQ_LIMIT_WL_S); 5076 5077 attr->srq_limit = limit_wl; 5078 attr->max_wr = srq->wqe_cnt - 1; 5079 attr->max_sge = srq->max_gs - HNS_ROCE_RESERVED_SGE; 5080 5081 out: 5082 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5083 return ret; 5084 } 5085 5086 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5087 { 5088 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5089 struct hns_roce_v2_cq_context *cq_context; 5090 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5091 struct hns_roce_v2_cq_context *cqc_mask; 5092 struct hns_roce_cmd_mailbox *mailbox; 5093 int ret; 5094 5095 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5096 if (IS_ERR(mailbox)) 5097 return PTR_ERR(mailbox); 5098 5099 cq_context = mailbox->buf; 5100 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5101 5102 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5103 5104 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5105 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5106 cq_count); 5107 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5108 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5109 0); 5110 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5111 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5112 cq_period); 5113 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5114 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5115 0); 5116 5117 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5118 HNS_ROCE_CMD_MODIFY_CQC, 5119 HNS_ROCE_CMD_TIMEOUT_MSECS); 5120 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5121 if (ret) 5122 ibdev_err(&hr_dev->ib_dev, 5123 "failed to process cmd when modifying CQ, ret = %d\n", 5124 ret); 5125 5126 return ret; 5127 } 5128 5129 static void hns_roce_irq_work_handle(struct work_struct *work) 5130 { 5131 struct hns_roce_work *irq_work = 5132 container_of(work, struct hns_roce_work, work); 5133 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5134 u32 qpn = irq_work->qpn; 5135 u32 cqn = irq_work->cqn; 5136 5137 switch (irq_work->event_type) { 5138 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5139 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5140 break; 5141 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5142 ibdev_warn(ibdev, "Path migration failed.\n"); 5143 break; 5144 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5145 break; 5146 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5147 ibdev_warn(ibdev, "Send queue drained.\n"); 5148 break; 5149 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5150 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5151 qpn, irq_work->sub_type); 5152 break; 5153 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5154 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5155 qpn); 5156 break; 5157 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5158 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5159 qpn, irq_work->sub_type); 5160 break; 5161 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5162 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5163 break; 5164 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5165 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5166 break; 5167 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5168 ibdev_err(ibdev, "SRQ catas error.\n"); 5169 break; 5170 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5171 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn); 5172 break; 5173 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5174 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn); 5175 break; 5176 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5177 ibdev_warn(ibdev, "DB overflow.\n"); 5178 break; 5179 case HNS_ROCE_EVENT_TYPE_FLR: 5180 ibdev_warn(ibdev, "Function level reset.\n"); 5181 break; 5182 default: 5183 break; 5184 } 5185 5186 kfree(irq_work); 5187 } 5188 5189 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5190 struct hns_roce_eq *eq, 5191 u32 qpn, u32 cqn) 5192 { 5193 struct hns_roce_work *irq_work; 5194 5195 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5196 if (!irq_work) 5197 return; 5198 5199 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5200 irq_work->hr_dev = hr_dev; 5201 irq_work->qpn = qpn; 5202 irq_work->cqn = cqn; 5203 irq_work->event_type = eq->event_type; 5204 irq_work->sub_type = eq->sub_type; 5205 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5206 } 5207 5208 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 5209 { 5210 struct hns_roce_dev *hr_dev = eq->hr_dev; 5211 __le32 doorbell[2] = {}; 5212 5213 if (eq->type_flag == HNS_ROCE_AEQ) { 5214 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5215 HNS_ROCE_V2_EQ_DB_CMD_S, 5216 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5217 HNS_ROCE_EQ_DB_CMD_AEQ : 5218 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5219 } else { 5220 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 5221 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 5222 5223 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5224 HNS_ROCE_V2_EQ_DB_CMD_S, 5225 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5226 HNS_ROCE_EQ_DB_CMD_CEQ : 5227 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5228 } 5229 5230 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 5231 HNS_ROCE_V2_EQ_DB_PARA_S, 5232 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 5233 5234 hns_roce_write64(hr_dev, doorbell, eq->doorbell); 5235 } 5236 5237 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5238 { 5239 struct hns_roce_aeqe *aeqe; 5240 5241 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5242 (eq->cons_index & (eq->entries - 1)) * 5243 HNS_ROCE_AEQ_ENTRY_SIZE); 5244 5245 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5246 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5247 } 5248 5249 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5250 struct hns_roce_eq *eq) 5251 { 5252 struct device *dev = hr_dev->dev; 5253 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5254 int aeqe_found = 0; 5255 int event_type; 5256 int sub_type; 5257 u32 srqn; 5258 u32 qpn; 5259 u32 cqn; 5260 5261 while (aeqe) { 5262 /* Make sure we read AEQ entry after we have checked the 5263 * ownership bit 5264 */ 5265 dma_rmb(); 5266 5267 event_type = roce_get_field(aeqe->asyn, 5268 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5269 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5270 sub_type = roce_get_field(aeqe->asyn, 5271 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5272 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5273 qpn = roce_get_field(aeqe->event.qp_event.qp, 5274 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5275 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5276 cqn = roce_get_field(aeqe->event.cq_event.cq, 5277 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5278 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5279 srqn = roce_get_field(aeqe->event.srq_event.srq, 5280 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5281 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5282 5283 switch (event_type) { 5284 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5285 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5286 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5287 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5288 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5289 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5290 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5291 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5292 hns_roce_qp_event(hr_dev, qpn, event_type); 5293 break; 5294 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5295 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5296 hns_roce_srq_event(hr_dev, srqn, event_type); 5297 break; 5298 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5299 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5300 hns_roce_cq_event(hr_dev, cqn, event_type); 5301 break; 5302 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5303 break; 5304 case HNS_ROCE_EVENT_TYPE_MB: 5305 hns_roce_cmd_event(hr_dev, 5306 le16_to_cpu(aeqe->event.cmd.token), 5307 aeqe->event.cmd.status, 5308 le64_to_cpu(aeqe->event.cmd.out_param)); 5309 break; 5310 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 5311 break; 5312 case HNS_ROCE_EVENT_TYPE_FLR: 5313 break; 5314 default: 5315 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5316 event_type, eq->eqn, eq->cons_index); 5317 break; 5318 } 5319 5320 eq->event_type = event_type; 5321 eq->sub_type = sub_type; 5322 ++eq->cons_index; 5323 aeqe_found = 1; 5324 5325 if (eq->cons_index > (2 * eq->entries - 1)) 5326 eq->cons_index = 0; 5327 5328 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn); 5329 5330 aeqe = next_aeqe_sw_v2(eq); 5331 } 5332 5333 set_eq_cons_index_v2(eq); 5334 return aeqe_found; 5335 } 5336 5337 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5338 { 5339 struct hns_roce_ceqe *ceqe; 5340 5341 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5342 (eq->cons_index & (eq->entries - 1)) * 5343 HNS_ROCE_CEQ_ENTRY_SIZE); 5344 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5345 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5346 } 5347 5348 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5349 struct hns_roce_eq *eq) 5350 { 5351 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5352 int ceqe_found = 0; 5353 u32 cqn; 5354 5355 while (ceqe) { 5356 /* Make sure we read CEQ entry after we have checked the 5357 * ownership bit 5358 */ 5359 dma_rmb(); 5360 5361 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5362 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5363 5364 hns_roce_cq_completion(hr_dev, cqn); 5365 5366 ++eq->cons_index; 5367 ceqe_found = 1; 5368 5369 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1)) 5370 eq->cons_index = 0; 5371 5372 ceqe = next_ceqe_sw_v2(eq); 5373 } 5374 5375 set_eq_cons_index_v2(eq); 5376 5377 return ceqe_found; 5378 } 5379 5380 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5381 { 5382 struct hns_roce_eq *eq = eq_ptr; 5383 struct hns_roce_dev *hr_dev = eq->hr_dev; 5384 int int_work = 0; 5385 5386 if (eq->type_flag == HNS_ROCE_CEQ) 5387 /* Completion event interrupt */ 5388 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5389 else 5390 /* Asychronous event interrupt */ 5391 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5392 5393 return IRQ_RETVAL(int_work); 5394 } 5395 5396 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5397 { 5398 struct hns_roce_dev *hr_dev = dev_id; 5399 struct device *dev = hr_dev->dev; 5400 int int_work = 0; 5401 u32 int_st; 5402 u32 int_en; 5403 5404 /* Abnormal interrupt */ 5405 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5406 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5407 5408 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5409 struct pci_dev *pdev = hr_dev->pci_dev; 5410 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5411 const struct hnae3_ae_ops *ops = ae_dev->ops; 5412 5413 dev_err(dev, "AEQ overflow!\n"); 5414 5415 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5416 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5417 5418 /* Set reset level for reset_event() */ 5419 if (ops->set_default_reset_request) 5420 ops->set_default_reset_request(ae_dev, 5421 HNAE3_FUNC_RESET); 5422 if (ops->reset_event) 5423 ops->reset_event(pdev, NULL); 5424 5425 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5426 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5427 5428 int_work = 1; 5429 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 5430 dev_err(dev, "BUS ERR!\n"); 5431 5432 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S; 5433 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5434 5435 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5436 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5437 5438 int_work = 1; 5439 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 5440 dev_err(dev, "OTHER ERR!\n"); 5441 5442 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S; 5443 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5444 5445 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5446 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5447 5448 int_work = 1; 5449 } else 5450 dev_err(dev, "There is no abnormal irq found!\n"); 5451 5452 return IRQ_RETVAL(int_work); 5453 } 5454 5455 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5456 int eq_num, int enable_flag) 5457 { 5458 int i; 5459 5460 if (enable_flag == EQ_ENABLE) { 5461 for (i = 0; i < eq_num; i++) 5462 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5463 i * EQ_REG_OFFSET, 5464 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 5465 5466 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5467 HNS_ROCE_V2_VF_ABN_INT_EN_M); 5468 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5469 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 5470 } else { 5471 for (i = 0; i < eq_num; i++) 5472 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5473 i * EQ_REG_OFFSET, 5474 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 5475 5476 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5477 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 5478 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5479 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 5480 } 5481 } 5482 5483 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5484 { 5485 struct device *dev = hr_dev->dev; 5486 int ret; 5487 5488 if (eqn < hr_dev->caps.num_comp_vectors) 5489 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5490 0, HNS_ROCE_CMD_DESTROY_CEQC, 5491 HNS_ROCE_CMD_TIMEOUT_MSECS); 5492 else 5493 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5494 0, HNS_ROCE_CMD_DESTROY_AEQC, 5495 HNS_ROCE_CMD_TIMEOUT_MSECS); 5496 if (ret) 5497 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5498 } 5499 5500 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5501 { 5502 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5503 } 5504 5505 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5506 void *mb_buf) 5507 { 5508 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5509 struct hns_roce_eq_context *eqc; 5510 u64 bt_ba = 0; 5511 int count; 5512 5513 eqc = mb_buf; 5514 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5515 5516 /* init eqc */ 5517 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5518 eq->cons_index = 0; 5519 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5520 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5521 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5522 eq->shift = ilog2((unsigned int)eq->entries); 5523 5524 /* if not multi-hop, eqe buffer only use one trunk */ 5525 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5526 &bt_ba); 5527 if (count < 1) { 5528 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5529 return -ENOBUFS; 5530 } 5531 5532 /* set eqc state */ 5533 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, 5534 HNS_ROCE_V2_EQ_STATE_VALID); 5535 5536 /* set eqe hop num */ 5537 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, 5538 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 5539 5540 /* set eqc over_ignore */ 5541 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, 5542 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 5543 5544 /* set eqc coalesce */ 5545 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M, 5546 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 5547 5548 /* set eqc arm_state */ 5549 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, 5550 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 5551 5552 /* set eqn */ 5553 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, 5554 eq->eqn); 5555 5556 /* set eqe_cnt */ 5557 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, 5558 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); 5559 5560 /* set eqe_ba_pg_sz */ 5561 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M, 5562 HNS_ROCE_EQC_BA_PG_SZ_S, 5563 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5564 5565 /* set eqe_buf_pg_sz */ 5566 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M, 5567 HNS_ROCE_EQC_BUF_PG_SZ_S, 5568 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5569 5570 /* set eq_producer_idx */ 5571 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M, 5572 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX); 5573 5574 /* set eq_max_cnt */ 5575 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M, 5576 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 5577 5578 /* set eq_period */ 5579 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M, 5580 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 5581 5582 /* set eqe_report_timer */ 5583 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M, 5584 HNS_ROCE_EQC_REPORT_TIMER_S, 5585 HNS_ROCE_EQ_INIT_REPORT_TIMER); 5586 5587 /* set bt_ba [34:3] */ 5588 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M, 5589 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3); 5590 5591 /* set bt_ba [64:35] */ 5592 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M, 5593 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35); 5594 5595 /* set eq shift */ 5596 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S, 5597 eq->shift); 5598 5599 /* set eq MSI_IDX */ 5600 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M, 5601 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX); 5602 5603 /* set cur_eqe_ba [27:12] */ 5604 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M, 5605 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12); 5606 5607 /* set cur_eqe_ba [59:28] */ 5608 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M, 5609 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28); 5610 5611 /* set cur_eqe_ba [63:60] */ 5612 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M, 5613 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60); 5614 5615 /* set eq consumer idx */ 5616 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M, 5617 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX); 5618 5619 /* set nex_eqe_ba[43:12] */ 5620 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M, 5621 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12); 5622 5623 /* set nex_eqe_ba[63:44] */ 5624 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M, 5625 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44); 5626 5627 return 0; 5628 } 5629 5630 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5631 { 5632 struct hns_roce_buf_attr buf_attr = {}; 5633 int err; 5634 5635 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5636 eq->hop_num = 0; 5637 else 5638 eq->hop_num = hr_dev->caps.eqe_hop_num; 5639 5640 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT; 5641 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5642 buf_attr.region[0].hopnum = eq->hop_num; 5643 buf_attr.region_count = 1; 5644 buf_attr.fixed_page = true; 5645 5646 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5647 hr_dev->caps.eqe_ba_pg_sz + 5648 HNS_HW_PAGE_SHIFT, NULL, 0); 5649 if (err) 5650 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5651 5652 return err; 5653 } 5654 5655 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5656 struct hns_roce_eq *eq, 5657 unsigned int eq_cmd) 5658 { 5659 struct hns_roce_cmd_mailbox *mailbox; 5660 int ret; 5661 5662 /* Allocate mailbox memory */ 5663 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5664 if (IS_ERR_OR_NULL(mailbox)) 5665 return -ENOMEM; 5666 5667 ret = alloc_eq_buf(hr_dev, eq); 5668 if (ret) 5669 goto free_cmd_mbox; 5670 5671 ret = config_eqc(hr_dev, eq, mailbox->buf); 5672 if (ret) 5673 goto err_cmd_mbox; 5674 5675 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5676 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5677 if (ret) { 5678 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5679 goto err_cmd_mbox; 5680 } 5681 5682 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5683 5684 return 0; 5685 5686 err_cmd_mbox: 5687 free_eq_buf(hr_dev, eq); 5688 5689 free_cmd_mbox: 5690 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5691 5692 return ret; 5693 } 5694 5695 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5696 int comp_num, int aeq_num, int other_num) 5697 { 5698 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5699 int i, j; 5700 int ret; 5701 5702 for (i = 0; i < irq_num; i++) { 5703 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5704 GFP_KERNEL); 5705 if (!hr_dev->irq_names[i]) { 5706 ret = -ENOMEM; 5707 goto err_kzalloc_failed; 5708 } 5709 } 5710 5711 /* irq contains: abnormal + AEQ + CEQ */ 5712 for (j = 0; j < other_num; j++) 5713 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5714 "hns-abn-%d", j); 5715 5716 for (j = other_num; j < (other_num + aeq_num); j++) 5717 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5718 "hns-aeq-%d", j - other_num); 5719 5720 for (j = (other_num + aeq_num); j < irq_num; j++) 5721 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5722 "hns-ceq-%d", j - other_num - aeq_num); 5723 5724 for (j = 0; j < irq_num; j++) { 5725 if (j < other_num) 5726 ret = request_irq(hr_dev->irq[j], 5727 hns_roce_v2_msix_interrupt_abn, 5728 0, hr_dev->irq_names[j], hr_dev); 5729 5730 else if (j < (other_num + comp_num)) 5731 ret = request_irq(eq_table->eq[j - other_num].irq, 5732 hns_roce_v2_msix_interrupt_eq, 5733 0, hr_dev->irq_names[j + aeq_num], 5734 &eq_table->eq[j - other_num]); 5735 else 5736 ret = request_irq(eq_table->eq[j - other_num].irq, 5737 hns_roce_v2_msix_interrupt_eq, 5738 0, hr_dev->irq_names[j - comp_num], 5739 &eq_table->eq[j - other_num]); 5740 if (ret) { 5741 dev_err(hr_dev->dev, "Request irq error!\n"); 5742 goto err_request_failed; 5743 } 5744 } 5745 5746 return 0; 5747 5748 err_request_failed: 5749 for (j -= 1; j >= 0; j--) 5750 if (j < other_num) 5751 free_irq(hr_dev->irq[j], hr_dev); 5752 else 5753 free_irq(eq_table->eq[j - other_num].irq, 5754 &eq_table->eq[j - other_num]); 5755 5756 err_kzalloc_failed: 5757 for (i -= 1; i >= 0; i--) 5758 kfree(hr_dev->irq_names[i]); 5759 5760 return ret; 5761 } 5762 5763 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 5764 { 5765 int irq_num; 5766 int eq_num; 5767 int i; 5768 5769 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5770 irq_num = eq_num + hr_dev->caps.num_other_vectors; 5771 5772 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 5773 free_irq(hr_dev->irq[i], hr_dev); 5774 5775 for (i = 0; i < eq_num; i++) 5776 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 5777 5778 for (i = 0; i < irq_num; i++) 5779 kfree(hr_dev->irq_names[i]); 5780 } 5781 5782 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 5783 { 5784 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5785 struct device *dev = hr_dev->dev; 5786 struct hns_roce_eq *eq; 5787 unsigned int eq_cmd; 5788 int irq_num; 5789 int eq_num; 5790 int other_num; 5791 int comp_num; 5792 int aeq_num; 5793 int i; 5794 int ret; 5795 5796 other_num = hr_dev->caps.num_other_vectors; 5797 comp_num = hr_dev->caps.num_comp_vectors; 5798 aeq_num = hr_dev->caps.num_aeq_vectors; 5799 5800 eq_num = comp_num + aeq_num; 5801 irq_num = eq_num + other_num; 5802 5803 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 5804 if (!eq_table->eq) 5805 return -ENOMEM; 5806 5807 /* create eq */ 5808 for (i = 0; i < eq_num; i++) { 5809 eq = &eq_table->eq[i]; 5810 eq->hr_dev = hr_dev; 5811 eq->eqn = i; 5812 if (i < comp_num) { 5813 /* CEQ */ 5814 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 5815 eq->type_flag = HNS_ROCE_CEQ; 5816 eq->entries = hr_dev->caps.ceqe_depth; 5817 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 5818 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 5819 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 5820 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 5821 } else { 5822 /* AEQ */ 5823 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 5824 eq->type_flag = HNS_ROCE_AEQ; 5825 eq->entries = hr_dev->caps.aeqe_depth; 5826 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 5827 eq->irq = hr_dev->irq[i - comp_num + other_num]; 5828 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 5829 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 5830 } 5831 5832 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 5833 if (ret) { 5834 dev_err(dev, "eq create failed.\n"); 5835 goto err_create_eq_fail; 5836 } 5837 } 5838 5839 /* enable irq */ 5840 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 5841 5842 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, 5843 aeq_num, other_num); 5844 if (ret) { 5845 dev_err(dev, "Request irq failed.\n"); 5846 goto err_request_irq_fail; 5847 } 5848 5849 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 5850 if (!hr_dev->irq_workq) { 5851 dev_err(dev, "Create irq workqueue failed!\n"); 5852 ret = -ENOMEM; 5853 goto err_create_wq_fail; 5854 } 5855 5856 return 0; 5857 5858 err_create_wq_fail: 5859 __hns_roce_free_irq(hr_dev); 5860 5861 err_request_irq_fail: 5862 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5863 5864 err_create_eq_fail: 5865 for (i -= 1; i >= 0; i--) 5866 free_eq_buf(hr_dev, &eq_table->eq[i]); 5867 kfree(eq_table->eq); 5868 5869 return ret; 5870 } 5871 5872 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 5873 { 5874 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5875 int eq_num; 5876 int i; 5877 5878 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5879 5880 /* Disable irq */ 5881 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5882 5883 __hns_roce_free_irq(hr_dev); 5884 5885 for (i = 0; i < eq_num; i++) { 5886 hns_roce_v2_destroy_eqc(hr_dev, i); 5887 5888 free_eq_buf(hr_dev, &eq_table->eq[i]); 5889 } 5890 5891 kfree(eq_table->eq); 5892 5893 flush_workqueue(hr_dev->irq_workq); 5894 destroy_workqueue(hr_dev->irq_workq); 5895 } 5896 5897 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 5898 .query_cqc_info = hns_roce_v2_query_cqc_info, 5899 }; 5900 5901 static const struct ib_device_ops hns_roce_v2_dev_ops = { 5902 .destroy_qp = hns_roce_v2_destroy_qp, 5903 .modify_cq = hns_roce_v2_modify_cq, 5904 .poll_cq = hns_roce_v2_poll_cq, 5905 .post_recv = hns_roce_v2_post_recv, 5906 .post_send = hns_roce_v2_post_send, 5907 .query_qp = hns_roce_v2_query_qp, 5908 .req_notify_cq = hns_roce_v2_req_notify_cq, 5909 }; 5910 5911 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 5912 .modify_srq = hns_roce_v2_modify_srq, 5913 .post_srq_recv = hns_roce_v2_post_srq_recv, 5914 .query_srq = hns_roce_v2_query_srq, 5915 }; 5916 5917 static const struct hns_roce_hw hns_roce_hw_v2 = { 5918 .cmq_init = hns_roce_v2_cmq_init, 5919 .cmq_exit = hns_roce_v2_cmq_exit, 5920 .hw_profile = hns_roce_v2_profile, 5921 .hw_init = hns_roce_v2_init, 5922 .hw_exit = hns_roce_v2_exit, 5923 .post_mbox = hns_roce_v2_post_mbox, 5924 .chk_mbox = hns_roce_v2_chk_mbox, 5925 .rst_prc_mbox = hns_roce_v2_rst_process_cmd, 5926 .set_gid = hns_roce_v2_set_gid, 5927 .set_mac = hns_roce_v2_set_mac, 5928 .write_mtpt = hns_roce_v2_write_mtpt, 5929 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 5930 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 5931 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 5932 .write_cqc = hns_roce_v2_write_cqc, 5933 .set_hem = hns_roce_v2_set_hem, 5934 .clear_hem = hns_roce_v2_clear_hem, 5935 .modify_qp = hns_roce_v2_modify_qp, 5936 .query_qp = hns_roce_v2_query_qp, 5937 .destroy_qp = hns_roce_v2_destroy_qp, 5938 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 5939 .modify_cq = hns_roce_v2_modify_cq, 5940 .post_send = hns_roce_v2_post_send, 5941 .post_recv = hns_roce_v2_post_recv, 5942 .req_notify_cq = hns_roce_v2_req_notify_cq, 5943 .poll_cq = hns_roce_v2_poll_cq, 5944 .init_eq = hns_roce_v2_init_eq_table, 5945 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 5946 .write_srqc = hns_roce_v2_write_srqc, 5947 .modify_srq = hns_roce_v2_modify_srq, 5948 .query_srq = hns_roce_v2_query_srq, 5949 .post_srq_recv = hns_roce_v2_post_srq_recv, 5950 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 5951 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 5952 }; 5953 5954 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 5955 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 5956 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 5957 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 5958 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 5959 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 5960 /* required last entry */ 5961 {0, } 5962 }; 5963 5964 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 5965 5966 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 5967 struct hnae3_handle *handle) 5968 { 5969 struct hns_roce_v2_priv *priv = hr_dev->priv; 5970 int i; 5971 5972 hr_dev->pci_dev = handle->pdev; 5973 hr_dev->dev = &handle->pdev->dev; 5974 hr_dev->hw = &hns_roce_hw_v2; 5975 hr_dev->dfx = &hns_roce_dfx_hw_v2; 5976 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 5977 hr_dev->odb_offset = hr_dev->sdb_offset; 5978 5979 /* Get info from NIC driver. */ 5980 hr_dev->reg_base = handle->rinfo.roce_io_base; 5981 hr_dev->caps.num_ports = 1; 5982 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 5983 hr_dev->iboe.phy_port[0] = 0; 5984 5985 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 5986 hr_dev->iboe.netdevs[0]->dev_addr); 5987 5988 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 5989 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 5990 i + handle->rinfo.base_vector); 5991 5992 /* cmd issue mode: 0 is poll, 1 is event */ 5993 hr_dev->cmd_mod = 1; 5994 hr_dev->loop_idc = 0; 5995 5996 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 5997 priv->handle = handle; 5998 } 5999 6000 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6001 { 6002 struct hns_roce_dev *hr_dev; 6003 int ret; 6004 6005 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6006 if (!hr_dev) 6007 return -ENOMEM; 6008 6009 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6010 if (!hr_dev->priv) { 6011 ret = -ENOMEM; 6012 goto error_failed_kzalloc; 6013 } 6014 6015 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6016 6017 ret = hns_roce_init(hr_dev); 6018 if (ret) { 6019 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6020 goto error_failed_get_cfg; 6021 } 6022 6023 handle->priv = hr_dev; 6024 6025 return 0; 6026 6027 error_failed_get_cfg: 6028 kfree(hr_dev->priv); 6029 6030 error_failed_kzalloc: 6031 ib_dealloc_device(&hr_dev->ib_dev); 6032 6033 return ret; 6034 } 6035 6036 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6037 bool reset) 6038 { 6039 struct hns_roce_dev *hr_dev = handle->priv; 6040 6041 if (!hr_dev) 6042 return; 6043 6044 handle->priv = NULL; 6045 6046 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6047 hns_roce_handle_device_err(hr_dev); 6048 6049 hns_roce_exit(hr_dev); 6050 kfree(hr_dev->priv); 6051 ib_dealloc_device(&hr_dev->ib_dev); 6052 } 6053 6054 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6055 { 6056 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6057 const struct pci_device_id *id; 6058 struct device *dev = &handle->pdev->dev; 6059 int ret; 6060 6061 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6062 6063 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6064 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6065 goto reset_chk_err; 6066 } 6067 6068 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6069 if (!id) 6070 return 0; 6071 6072 ret = __hns_roce_hw_v2_init_instance(handle); 6073 if (ret) { 6074 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6075 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6076 if (ops->ae_dev_resetting(handle) || 6077 ops->get_hw_reset_stat(handle)) 6078 goto reset_chk_err; 6079 else 6080 return ret; 6081 } 6082 6083 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6084 6085 6086 return 0; 6087 6088 reset_chk_err: 6089 dev_err(dev, "Device is busy in resetting state.\n" 6090 "please retry later.\n"); 6091 6092 return -EBUSY; 6093 } 6094 6095 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6096 bool reset) 6097 { 6098 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6099 return; 6100 6101 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6102 6103 __hns_roce_hw_v2_uninit_instance(handle, reset); 6104 6105 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6106 } 6107 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6108 { 6109 struct hns_roce_dev *hr_dev; 6110 6111 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6112 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6113 return 0; 6114 } 6115 6116 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6117 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6118 6119 hr_dev = handle->priv; 6120 if (!hr_dev) 6121 return 0; 6122 6123 hr_dev->is_reset = true; 6124 hr_dev->active = false; 6125 hr_dev->dis_db = true; 6126 6127 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6128 6129 return 0; 6130 } 6131 6132 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6133 { 6134 struct device *dev = &handle->pdev->dev; 6135 int ret; 6136 6137 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6138 &handle->rinfo.state)) { 6139 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6140 return 0; 6141 } 6142 6143 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6144 6145 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6146 ret = __hns_roce_hw_v2_init_instance(handle); 6147 if (ret) { 6148 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6149 * callback function, RoCE Engine reinitialize. If RoCE reinit 6150 * failed, we should inform NIC driver. 6151 */ 6152 handle->priv = NULL; 6153 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6154 } else { 6155 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6156 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6157 } 6158 6159 return ret; 6160 } 6161 6162 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6163 { 6164 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6165 return 0; 6166 6167 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6168 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6169 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6170 __hns_roce_hw_v2_uninit_instance(handle, false); 6171 6172 return 0; 6173 } 6174 6175 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6176 enum hnae3_reset_notify_type type) 6177 { 6178 int ret = 0; 6179 6180 switch (type) { 6181 case HNAE3_DOWN_CLIENT: 6182 ret = hns_roce_hw_v2_reset_notify_down(handle); 6183 break; 6184 case HNAE3_INIT_CLIENT: 6185 ret = hns_roce_hw_v2_reset_notify_init(handle); 6186 break; 6187 case HNAE3_UNINIT_CLIENT: 6188 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6189 break; 6190 default: 6191 break; 6192 } 6193 6194 return ret; 6195 } 6196 6197 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6198 .init_instance = hns_roce_hw_v2_init_instance, 6199 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6200 .reset_notify = hns_roce_hw_v2_reset_notify, 6201 }; 6202 6203 static struct hnae3_client hns_roce_hw_v2_client = { 6204 .name = "hns_roce_hw_v2", 6205 .type = HNAE3_CLIENT_ROCE, 6206 .ops = &hns_roce_hw_v2_ops, 6207 }; 6208 6209 static int __init hns_roce_hw_v2_init(void) 6210 { 6211 return hnae3_register_client(&hns_roce_hw_v2_client); 6212 } 6213 6214 static void __exit hns_roce_hw_v2_exit(void) 6215 { 6216 hnae3_unregister_client(&hns_roce_hw_v2_client); 6217 } 6218 6219 module_init(hns_roce_hw_v2_init); 6220 module_exit(hns_roce_hw_v2_exit); 6221 6222 MODULE_LICENSE("Dual BSD/GPL"); 6223 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6224 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6225 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6226 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6227