1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <net/addrconf.h> 38 #include <rdma/ib_umem.h> 39 40 #include "hnae3.h" 41 #include "hns_roce_common.h" 42 #include "hns_roce_device.h" 43 #include "hns_roce_cmd.h" 44 #include "hns_roce_hem.h" 45 #include "hns_roce_hw_v2.h" 46 47 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 48 struct ib_sge *sg) 49 { 50 dseg->lkey = cpu_to_le32(sg->lkey); 51 dseg->addr = cpu_to_le64(sg->addr); 52 dseg->len = cpu_to_le32(sg->length); 53 } 54 55 static int set_rwqe_data_seg(struct ib_qp *ibqp, struct ib_send_wr *wr, 56 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 57 void *wqe, unsigned int *sge_ind, 58 struct ib_send_wr **bad_wr) 59 { 60 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 61 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 62 struct hns_roce_qp *qp = to_hr_qp(ibqp); 63 int i; 64 65 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) { 66 if (le32_to_cpu(rc_sq_wqe->msg_len) > 67 hr_dev->caps.max_sq_inline) { 68 *bad_wr = wr; 69 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal", 70 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline); 71 return -EINVAL; 72 } 73 74 if (wr->opcode == IB_WR_RDMA_READ) { 75 dev_err(hr_dev->dev, "Not support inline data!\n"); 76 return -EINVAL; 77 } 78 79 for (i = 0; i < wr->num_sge; i++) { 80 memcpy(wqe, ((void *)wr->sg_list[i].addr), 81 wr->sg_list[i].length); 82 wqe += wr->sg_list[i].length; 83 } 84 85 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 86 1); 87 } else { 88 if (wr->num_sge <= 2) { 89 for (i = 0; i < wr->num_sge; i++) { 90 if (likely(wr->sg_list[i].length)) { 91 set_data_seg_v2(dseg, wr->sg_list + i); 92 dseg++; 93 } 94 } 95 } else { 96 roce_set_field(rc_sq_wqe->byte_20, 97 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 98 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 99 (*sge_ind) & (qp->sge.sge_cnt - 1)); 100 101 for (i = 0; i < 2; i++) { 102 if (likely(wr->sg_list[i].length)) { 103 set_data_seg_v2(dseg, wr->sg_list + i); 104 dseg++; 105 } 106 } 107 108 dseg = get_send_extend_sge(qp, 109 (*sge_ind) & (qp->sge.sge_cnt - 1)); 110 111 for (i = 0; i < wr->num_sge - 2; i++) { 112 if (likely(wr->sg_list[i + 2].length)) { 113 set_data_seg_v2(dseg, 114 wr->sg_list + 2 + i); 115 dseg++; 116 (*sge_ind)++; 117 } 118 } 119 } 120 121 roce_set_field(rc_sq_wqe->byte_16, 122 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 123 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge); 124 } 125 126 return 0; 127 } 128 129 static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 130 struct ib_send_wr **bad_wr) 131 { 132 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 133 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 134 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe; 135 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe; 136 struct hns_roce_qp *qp = to_hr_qp(ibqp); 137 struct hns_roce_v2_wqe_data_seg *dseg; 138 struct device *dev = hr_dev->dev; 139 struct hns_roce_v2_db sq_db; 140 unsigned int sge_ind = 0; 141 unsigned int owner_bit; 142 unsigned long flags; 143 unsigned int ind; 144 void *wqe = NULL; 145 u32 tmp_len = 0; 146 bool loopback; 147 int ret = 0; 148 u8 *smac; 149 int nreq; 150 int i; 151 152 if (unlikely(ibqp->qp_type != IB_QPT_RC && 153 ibqp->qp_type != IB_QPT_GSI && 154 ibqp->qp_type != IB_QPT_UD)) { 155 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type); 156 *bad_wr = wr; 157 return -EOPNOTSUPP; 158 } 159 160 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT || 161 qp->state == IB_QPS_RTR)) { 162 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state); 163 *bad_wr = wr; 164 return -EINVAL; 165 } 166 167 spin_lock_irqsave(&qp->sq.lock, flags); 168 ind = qp->sq_next_wqe; 169 sge_ind = qp->next_sge; 170 171 for (nreq = 0; wr; ++nreq, wr = wr->next) { 172 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 173 ret = -ENOMEM; 174 *bad_wr = wr; 175 goto out; 176 } 177 178 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 179 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n", 180 wr->num_sge, qp->sq.max_gs); 181 ret = -EINVAL; 182 *bad_wr = wr; 183 goto out; 184 } 185 186 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 187 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = 188 wr->wr_id; 189 190 owner_bit = 191 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 192 193 /* Corresponding to the QP type, wqe process separately */ 194 if (ibqp->qp_type == IB_QPT_GSI) { 195 ud_sq_wqe = wqe; 196 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 197 198 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 199 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 200 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 201 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 202 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 203 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 204 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 205 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 206 roce_set_field(ud_sq_wqe->byte_48, 207 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 208 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, 209 ah->av.mac[4]); 210 roce_set_field(ud_sq_wqe->byte_48, 211 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 212 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, 213 ah->av.mac[5]); 214 215 /* MAC loopback */ 216 smac = (u8 *)hr_dev->dev_addr[qp->port]; 217 loopback = ether_addr_equal_unaligned(ah->av.mac, 218 smac) ? 1 : 0; 219 220 roce_set_bit(ud_sq_wqe->byte_40, 221 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 222 223 roce_set_field(ud_sq_wqe->byte_4, 224 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 225 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 226 HNS_ROCE_V2_WQE_OP_SEND); 227 228 for (i = 0; i < wr->num_sge; i++) 229 tmp_len += wr->sg_list[i].length; 230 231 ud_sq_wqe->msg_len = 232 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len); 233 234 switch (wr->opcode) { 235 case IB_WR_SEND_WITH_IMM: 236 case IB_WR_RDMA_WRITE_WITH_IMM: 237 ud_sq_wqe->immtdata = wr->ex.imm_data; 238 break; 239 default: 240 ud_sq_wqe->immtdata = 0; 241 break; 242 } 243 244 /* Set sig attr */ 245 roce_set_bit(ud_sq_wqe->byte_4, 246 V2_UD_SEND_WQE_BYTE_4_CQE_S, 247 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 248 249 /* Set se attr */ 250 roce_set_bit(ud_sq_wqe->byte_4, 251 V2_UD_SEND_WQE_BYTE_4_SE_S, 252 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 253 254 roce_set_bit(ud_sq_wqe->byte_4, 255 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 256 257 roce_set_field(ud_sq_wqe->byte_16, 258 V2_UD_SEND_WQE_BYTE_16_PD_M, 259 V2_UD_SEND_WQE_BYTE_16_PD_S, 260 to_hr_pd(ibqp->pd)->pdn); 261 262 roce_set_field(ud_sq_wqe->byte_16, 263 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 264 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, 265 wr->num_sge); 266 267 roce_set_field(ud_sq_wqe->byte_20, 268 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 269 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 270 sge_ind & (qp->sge.sge_cnt - 1)); 271 272 roce_set_field(ud_sq_wqe->byte_24, 273 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 274 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 275 ud_sq_wqe->qkey = 276 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 277 qp->qkey : ud_wr(wr)->remote_qkey); 278 roce_set_field(ud_sq_wqe->byte_32, 279 V2_UD_SEND_WQE_BYTE_32_DQPN_M, 280 V2_UD_SEND_WQE_BYTE_32_DQPN_S, 281 ud_wr(wr)->remote_qpn); 282 283 roce_set_field(ud_sq_wqe->byte_36, 284 V2_UD_SEND_WQE_BYTE_36_VLAN_M, 285 V2_UD_SEND_WQE_BYTE_36_VLAN_S, 286 le16_to_cpu(ah->av.vlan)); 287 roce_set_field(ud_sq_wqe->byte_36, 288 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 289 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, 290 ah->av.hop_limit); 291 roce_set_field(ud_sq_wqe->byte_36, 292 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 293 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 294 0); 295 roce_set_field(ud_sq_wqe->byte_36, 296 V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 297 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, 298 0); 299 roce_set_field(ud_sq_wqe->byte_40, 300 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 301 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, 0); 302 roce_set_field(ud_sq_wqe->byte_40, 303 V2_UD_SEND_WQE_BYTE_40_SL_M, 304 V2_UD_SEND_WQE_BYTE_40_SL_S, 305 le32_to_cpu(ah->av.sl_tclass_flowlabel) >> 306 HNS_ROCE_SL_SHIFT); 307 roce_set_field(ud_sq_wqe->byte_40, 308 V2_UD_SEND_WQE_BYTE_40_PORTN_M, 309 V2_UD_SEND_WQE_BYTE_40_PORTN_S, 310 qp->port); 311 312 roce_set_field(ud_sq_wqe->byte_48, 313 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 314 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, 315 hns_get_gid_index(hr_dev, qp->phy_port, 316 ah->av.gid_index)); 317 318 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], 319 GID_LEN_V2); 320 321 dseg = get_send_extend_sge(qp, 322 sge_ind & (qp->sge.sge_cnt - 1)); 323 for (i = 0; i < wr->num_sge; i++) { 324 set_data_seg_v2(dseg + i, wr->sg_list + i); 325 sge_ind++; 326 } 327 328 ind++; 329 } else if (ibqp->qp_type == IB_QPT_RC) { 330 rc_sq_wqe = wqe; 331 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 332 for (i = 0; i < wr->num_sge; i++) 333 tmp_len += wr->sg_list[i].length; 334 335 rc_sq_wqe->msg_len = 336 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len); 337 338 switch (wr->opcode) { 339 case IB_WR_SEND_WITH_IMM: 340 case IB_WR_RDMA_WRITE_WITH_IMM: 341 rc_sq_wqe->immtdata = wr->ex.imm_data; 342 break; 343 case IB_WR_SEND_WITH_INV: 344 rc_sq_wqe->inv_key = 345 cpu_to_le32(wr->ex.invalidate_rkey); 346 break; 347 default: 348 rc_sq_wqe->immtdata = 0; 349 break; 350 } 351 352 roce_set_bit(rc_sq_wqe->byte_4, 353 V2_RC_SEND_WQE_BYTE_4_FENCE_S, 354 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 355 356 roce_set_bit(rc_sq_wqe->byte_4, 357 V2_RC_SEND_WQE_BYTE_4_SE_S, 358 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 359 360 roce_set_bit(rc_sq_wqe->byte_4, 361 V2_RC_SEND_WQE_BYTE_4_CQE_S, 362 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 363 364 roce_set_bit(rc_sq_wqe->byte_4, 365 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit); 366 367 switch (wr->opcode) { 368 case IB_WR_RDMA_READ: 369 roce_set_field(rc_sq_wqe->byte_4, 370 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 371 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 372 HNS_ROCE_V2_WQE_OP_RDMA_READ); 373 rc_sq_wqe->rkey = 374 cpu_to_le32(rdma_wr(wr)->rkey); 375 rc_sq_wqe->va = 376 cpu_to_le64(rdma_wr(wr)->remote_addr); 377 break; 378 case IB_WR_RDMA_WRITE: 379 roce_set_field(rc_sq_wqe->byte_4, 380 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 381 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 382 HNS_ROCE_V2_WQE_OP_RDMA_WRITE); 383 rc_sq_wqe->rkey = 384 cpu_to_le32(rdma_wr(wr)->rkey); 385 rc_sq_wqe->va = 386 cpu_to_le64(rdma_wr(wr)->remote_addr); 387 break; 388 case IB_WR_RDMA_WRITE_WITH_IMM: 389 roce_set_field(rc_sq_wqe->byte_4, 390 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 391 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 392 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM); 393 rc_sq_wqe->rkey = 394 cpu_to_le32(rdma_wr(wr)->rkey); 395 rc_sq_wqe->va = 396 cpu_to_le64(rdma_wr(wr)->remote_addr); 397 break; 398 case IB_WR_SEND: 399 roce_set_field(rc_sq_wqe->byte_4, 400 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 401 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 402 HNS_ROCE_V2_WQE_OP_SEND); 403 break; 404 case IB_WR_SEND_WITH_INV: 405 roce_set_field(rc_sq_wqe->byte_4, 406 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 407 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 408 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV); 409 break; 410 case IB_WR_SEND_WITH_IMM: 411 roce_set_field(rc_sq_wqe->byte_4, 412 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 413 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 414 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM); 415 break; 416 case IB_WR_LOCAL_INV: 417 roce_set_field(rc_sq_wqe->byte_4, 418 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 419 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 420 HNS_ROCE_V2_WQE_OP_LOCAL_INV); 421 break; 422 case IB_WR_ATOMIC_CMP_AND_SWP: 423 roce_set_field(rc_sq_wqe->byte_4, 424 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 425 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 426 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP); 427 break; 428 case IB_WR_ATOMIC_FETCH_AND_ADD: 429 roce_set_field(rc_sq_wqe->byte_4, 430 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 431 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 432 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD); 433 break; 434 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 435 roce_set_field(rc_sq_wqe->byte_4, 436 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 437 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 438 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP); 439 break; 440 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 441 roce_set_field(rc_sq_wqe->byte_4, 442 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 443 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 444 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD); 445 break; 446 default: 447 roce_set_field(rc_sq_wqe->byte_4, 448 V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 449 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 450 HNS_ROCE_V2_WQE_OP_MASK); 451 break; 452 } 453 454 wqe += sizeof(struct hns_roce_v2_rc_send_wqe); 455 dseg = wqe; 456 457 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe, 458 &sge_ind, bad_wr); 459 if (ret) 460 goto out; 461 ind++; 462 } else { 463 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type); 464 spin_unlock_irqrestore(&qp->sq.lock, flags); 465 *bad_wr = wr; 466 return -EOPNOTSUPP; 467 } 468 } 469 470 out: 471 if (likely(nreq)) { 472 qp->sq.head += nreq; 473 /* Memory barrier */ 474 wmb(); 475 476 sq_db.byte_4 = 0; 477 sq_db.parameter = 0; 478 479 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 480 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 481 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 482 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 483 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M, 484 V2_DB_PARAMETER_CONS_IDX_S, 485 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)); 486 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 487 V2_DB_PARAMETER_SL_S, qp->sl); 488 489 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l); 490 491 qp->sq_next_wqe = ind; 492 qp->next_sge = sge_ind; 493 } 494 495 spin_unlock_irqrestore(&qp->sq.lock, flags); 496 497 return ret; 498 } 499 500 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 501 struct ib_recv_wr **bad_wr) 502 { 503 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 504 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 505 struct hns_roce_v2_wqe_data_seg *dseg; 506 struct hns_roce_rinl_sge *sge_list; 507 struct device *dev = hr_dev->dev; 508 unsigned long flags; 509 void *wqe = NULL; 510 int ret = 0; 511 int nreq; 512 int ind; 513 int i; 514 515 spin_lock_irqsave(&hr_qp->rq.lock, flags); 516 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1); 517 518 if (hr_qp->state == IB_QPS_RESET) { 519 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 520 *bad_wr = wr; 521 return -EINVAL; 522 } 523 524 for (nreq = 0; wr; ++nreq, wr = wr->next) { 525 if (hns_roce_wq_overflow(&hr_qp->rq, nreq, 526 hr_qp->ibqp.recv_cq)) { 527 ret = -ENOMEM; 528 *bad_wr = wr; 529 goto out; 530 } 531 532 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { 533 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n", 534 wr->num_sge, hr_qp->rq.max_gs); 535 ret = -EINVAL; 536 *bad_wr = wr; 537 goto out; 538 } 539 540 wqe = get_recv_wqe(hr_qp, ind); 541 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 542 for (i = 0; i < wr->num_sge; i++) { 543 if (!wr->sg_list[i].length) 544 continue; 545 set_data_seg_v2(dseg, wr->sg_list + i); 546 dseg++; 547 } 548 549 if (i < hr_qp->rq.max_gs) { 550 dseg[i].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 551 dseg[i].addr = 0; 552 } 553 554 /* rq support inline data */ 555 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list; 556 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt = (u32)wr->num_sge; 557 for (i = 0; i < wr->num_sge; i++) { 558 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 559 sge_list[i].len = wr->sg_list[i].length; 560 } 561 562 hr_qp->rq.wrid[ind] = wr->wr_id; 563 564 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1); 565 } 566 567 out: 568 if (likely(nreq)) { 569 hr_qp->rq.head += nreq; 570 /* Memory barrier */ 571 wmb(); 572 573 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 574 } 575 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 576 577 return ret; 578 } 579 580 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 581 { 582 int ntu = ring->next_to_use; 583 int ntc = ring->next_to_clean; 584 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 585 586 return ring->desc_num - used - 1; 587 } 588 589 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 590 struct hns_roce_v2_cmq_ring *ring) 591 { 592 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 593 594 ring->desc = kzalloc(size, GFP_KERNEL); 595 if (!ring->desc) 596 return -ENOMEM; 597 598 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 599 DMA_BIDIRECTIONAL); 600 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 601 ring->desc_dma_addr = 0; 602 kfree(ring->desc); 603 ring->desc = NULL; 604 return -ENOMEM; 605 } 606 607 return 0; 608 } 609 610 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 611 struct hns_roce_v2_cmq_ring *ring) 612 { 613 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 614 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 615 DMA_BIDIRECTIONAL); 616 kfree(ring->desc); 617 } 618 619 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 620 { 621 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 622 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 623 &priv->cmq.csq : &priv->cmq.crq; 624 625 ring->flag = ring_type; 626 ring->next_to_clean = 0; 627 ring->next_to_use = 0; 628 629 return hns_roce_alloc_cmq_desc(hr_dev, ring); 630 } 631 632 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 633 { 634 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 635 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 636 &priv->cmq.csq : &priv->cmq.crq; 637 dma_addr_t dma = ring->desc_dma_addr; 638 639 if (ring_type == TYPE_CSQ) { 640 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 641 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 642 upper_32_bits(dma)); 643 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 644 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 645 HNS_ROCE_CMQ_ENABLE); 646 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 647 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 648 } else { 649 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 650 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 651 upper_32_bits(dma)); 652 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 653 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) | 654 HNS_ROCE_CMQ_ENABLE); 655 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 656 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 657 } 658 } 659 660 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 661 { 662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 663 int ret; 664 665 /* Setup the queue entries for command queue */ 666 priv->cmq.csq.desc_num = 1024; 667 priv->cmq.crq.desc_num = 1024; 668 669 /* Setup the lock for command queue */ 670 spin_lock_init(&priv->cmq.csq.lock); 671 spin_lock_init(&priv->cmq.crq.lock); 672 673 /* Setup Tx write back timeout */ 674 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 675 676 /* Init CSQ */ 677 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 678 if (ret) { 679 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 680 return ret; 681 } 682 683 /* Init CRQ */ 684 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 685 if (ret) { 686 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 687 goto err_crq; 688 } 689 690 /* Init CSQ REG */ 691 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 692 693 /* Init CRQ REG */ 694 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 695 696 return 0; 697 698 err_crq: 699 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 700 701 return ret; 702 } 703 704 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 705 { 706 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 707 708 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 709 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 710 } 711 712 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 713 enum hns_roce_opcode_type opcode, 714 bool is_read) 715 { 716 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 717 desc->opcode = cpu_to_le16(opcode); 718 desc->flag = 719 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 720 if (is_read) 721 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 722 else 723 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 724 } 725 726 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 727 { 728 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 729 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 730 731 return head == priv->cmq.csq.next_to_use; 732 } 733 734 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 735 { 736 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 737 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 738 struct hns_roce_cmq_desc *desc; 739 u16 ntc = csq->next_to_clean; 740 u32 head; 741 int clean = 0; 742 743 desc = &csq->desc[ntc]; 744 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 745 while (head != ntc) { 746 memset(desc, 0, sizeof(*desc)); 747 ntc++; 748 if (ntc == csq->desc_num) 749 ntc = 0; 750 desc = &csq->desc[ntc]; 751 clean++; 752 } 753 csq->next_to_clean = ntc; 754 755 return clean; 756 } 757 758 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 759 struct hns_roce_cmq_desc *desc, int num) 760 { 761 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 762 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 763 struct hns_roce_cmq_desc *desc_to_use; 764 bool complete = false; 765 u32 timeout = 0; 766 int handle = 0; 767 u16 desc_ret; 768 int ret = 0; 769 int ntc; 770 771 spin_lock_bh(&csq->lock); 772 773 if (num > hns_roce_cmq_space(csq)) { 774 spin_unlock_bh(&csq->lock); 775 return -EBUSY; 776 } 777 778 /* 779 * Record the location of desc in the cmq for this time 780 * which will be use for hardware to write back 781 */ 782 ntc = csq->next_to_use; 783 784 while (handle < num) { 785 desc_to_use = &csq->desc[csq->next_to_use]; 786 *desc_to_use = desc[handle]; 787 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 788 csq->next_to_use++; 789 if (csq->next_to_use == csq->desc_num) 790 csq->next_to_use = 0; 791 handle++; 792 } 793 794 /* Write to hardware */ 795 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 796 797 /* 798 * If the command is sync, wait for the firmware to write back, 799 * if multi descriptors to be sent, use the first one to check 800 */ 801 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 802 do { 803 if (hns_roce_cmq_csq_done(hr_dev)) 804 break; 805 udelay(1); 806 timeout++; 807 } while (timeout < priv->cmq.tx_timeout); 808 } 809 810 if (hns_roce_cmq_csq_done(hr_dev)) { 811 complete = true; 812 handle = 0; 813 while (handle < num) { 814 /* get the result of hardware write back */ 815 desc_to_use = &csq->desc[ntc]; 816 desc[handle] = *desc_to_use; 817 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 818 desc_ret = desc[handle].retval; 819 if (desc_ret == CMD_EXEC_SUCCESS) 820 ret = 0; 821 else 822 ret = -EIO; 823 priv->cmq.last_status = desc_ret; 824 ntc++; 825 handle++; 826 if (ntc == csq->desc_num) 827 ntc = 0; 828 } 829 } 830 831 if (!complete) 832 ret = -EAGAIN; 833 834 /* clean the command send queue */ 835 handle = hns_roce_cmq_csq_clean(hr_dev); 836 if (handle != num) 837 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 838 handle, num); 839 840 spin_unlock_bh(&csq->lock); 841 842 return ret; 843 } 844 845 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 846 { 847 struct hns_roce_query_version *resp; 848 struct hns_roce_cmq_desc desc; 849 int ret; 850 851 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 852 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 853 if (ret) 854 return ret; 855 856 resp = (struct hns_roce_query_version *)desc.data; 857 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version); 858 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id); 859 860 return 0; 861 } 862 863 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 864 { 865 struct hns_roce_cfg_global_param *req; 866 struct hns_roce_cmq_desc desc; 867 868 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 869 false); 870 871 req = (struct hns_roce_cfg_global_param *)desc.data; 872 memset(req, 0, sizeof(*req)); 873 roce_set_field(req->time_cfg_udp_port, 874 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 875 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 876 roce_set_field(req->time_cfg_udp_port, 877 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 878 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 879 880 return hns_roce_cmq_send(hr_dev, &desc, 1); 881 } 882 883 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 884 { 885 struct hns_roce_cmq_desc desc[2]; 886 struct hns_roce_pf_res *res; 887 int ret; 888 int i; 889 890 for (i = 0; i < 2; i++) { 891 hns_roce_cmq_setup_basic_desc(&desc[i], 892 HNS_ROCE_OPC_QUERY_PF_RES, true); 893 894 if (i == 0) 895 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 896 else 897 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 898 } 899 900 ret = hns_roce_cmq_send(hr_dev, desc, 2); 901 if (ret) 902 return ret; 903 904 res = (struct hns_roce_pf_res *)desc[0].data; 905 906 hr_dev->caps.qpc_bt_num = roce_get_field(res->qpc_bt_idx_num, 907 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 908 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 909 hr_dev->caps.srqc_bt_num = roce_get_field(res->srqc_bt_idx_num, 910 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 911 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 912 hr_dev->caps.cqc_bt_num = roce_get_field(res->cqc_bt_idx_num, 913 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 914 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 915 hr_dev->caps.mpt_bt_num = roce_get_field(res->mpt_bt_idx_num, 916 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 917 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 918 919 return 0; 920 } 921 922 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 923 { 924 struct hns_roce_cmq_desc desc[2]; 925 struct hns_roce_vf_res_a *req_a; 926 struct hns_roce_vf_res_b *req_b; 927 int i; 928 929 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 930 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 931 memset(req_a, 0, sizeof(*req_a)); 932 memset(req_b, 0, sizeof(*req_b)); 933 for (i = 0; i < 2; i++) { 934 hns_roce_cmq_setup_basic_desc(&desc[i], 935 HNS_ROCE_OPC_ALLOC_VF_RES, false); 936 937 if (i == 0) 938 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 939 else 940 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 941 942 if (i == 0) { 943 roce_set_field(req_a->vf_qpc_bt_idx_num, 944 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 945 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 946 roce_set_field(req_a->vf_qpc_bt_idx_num, 947 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 948 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, 949 HNS_ROCE_VF_QPC_BT_NUM); 950 951 roce_set_field(req_a->vf_srqc_bt_idx_num, 952 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 953 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 954 roce_set_field(req_a->vf_srqc_bt_idx_num, 955 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 956 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 957 HNS_ROCE_VF_SRQC_BT_NUM); 958 959 roce_set_field(req_a->vf_cqc_bt_idx_num, 960 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 961 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 962 roce_set_field(req_a->vf_cqc_bt_idx_num, 963 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 964 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, 965 HNS_ROCE_VF_CQC_BT_NUM); 966 967 roce_set_field(req_a->vf_mpt_bt_idx_num, 968 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 969 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 970 roce_set_field(req_a->vf_mpt_bt_idx_num, 971 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 972 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, 973 HNS_ROCE_VF_MPT_BT_NUM); 974 975 roce_set_field(req_a->vf_eqc_bt_idx_num, 976 VF_RES_A_DATA_5_VF_EQC_IDX_M, 977 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 978 roce_set_field(req_a->vf_eqc_bt_idx_num, 979 VF_RES_A_DATA_5_VF_EQC_NUM_M, 980 VF_RES_A_DATA_5_VF_EQC_NUM_S, 981 HNS_ROCE_VF_EQC_NUM); 982 } else { 983 roce_set_field(req_b->vf_smac_idx_num, 984 VF_RES_B_DATA_1_VF_SMAC_IDX_M, 985 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 986 roce_set_field(req_b->vf_smac_idx_num, 987 VF_RES_B_DATA_1_VF_SMAC_NUM_M, 988 VF_RES_B_DATA_1_VF_SMAC_NUM_S, 989 HNS_ROCE_VF_SMAC_NUM); 990 991 roce_set_field(req_b->vf_sgid_idx_num, 992 VF_RES_B_DATA_2_VF_SGID_IDX_M, 993 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 994 roce_set_field(req_b->vf_sgid_idx_num, 995 VF_RES_B_DATA_2_VF_SGID_NUM_M, 996 VF_RES_B_DATA_2_VF_SGID_NUM_S, 997 HNS_ROCE_VF_SGID_NUM); 998 999 roce_set_field(req_b->vf_qid_idx_sl_num, 1000 VF_RES_B_DATA_3_VF_QID_IDX_M, 1001 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1002 roce_set_field(req_b->vf_qid_idx_sl_num, 1003 VF_RES_B_DATA_3_VF_SL_NUM_M, 1004 VF_RES_B_DATA_3_VF_SL_NUM_S, 1005 HNS_ROCE_VF_SL_NUM); 1006 } 1007 } 1008 1009 return hns_roce_cmq_send(hr_dev, desc, 2); 1010 } 1011 1012 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1013 { 1014 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1015 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1016 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1017 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1018 struct hns_roce_cfg_bt_attr *req; 1019 struct hns_roce_cmq_desc desc; 1020 1021 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1022 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1023 memset(req, 0, sizeof(*req)); 1024 1025 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1026 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1027 hr_dev->caps.qpc_ba_pg_sz); 1028 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1029 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1030 hr_dev->caps.qpc_buf_pg_sz); 1031 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1032 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1033 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1034 1035 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1036 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1037 hr_dev->caps.srqc_ba_pg_sz); 1038 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1039 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1040 hr_dev->caps.srqc_buf_pg_sz); 1041 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1042 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1043 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1044 1045 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1046 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1047 hr_dev->caps.cqc_ba_pg_sz); 1048 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1049 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1050 hr_dev->caps.cqc_buf_pg_sz); 1051 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1052 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1053 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1054 1055 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1056 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1057 hr_dev->caps.mpt_ba_pg_sz); 1058 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1059 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1060 hr_dev->caps.mpt_buf_pg_sz); 1061 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1062 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1063 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1064 1065 return hns_roce_cmq_send(hr_dev, &desc, 1); 1066 } 1067 1068 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 1069 { 1070 struct hns_roce_caps *caps = &hr_dev->caps; 1071 int ret; 1072 1073 ret = hns_roce_cmq_query_hw_info(hr_dev); 1074 if (ret) { 1075 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 1076 ret); 1077 return ret; 1078 } 1079 1080 ret = hns_roce_config_global_param(hr_dev); 1081 if (ret) { 1082 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 1083 ret); 1084 } 1085 1086 /* Get pf resource owned by every pf */ 1087 ret = hns_roce_query_pf_resource(hr_dev); 1088 if (ret) { 1089 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 1090 ret); 1091 return ret; 1092 } 1093 1094 ret = hns_roce_alloc_vf_resource(hr_dev); 1095 if (ret) { 1096 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 1097 ret); 1098 return ret; 1099 } 1100 1101 hr_dev->vendor_part_id = 0; 1102 hr_dev->sys_image_guid = 0; 1103 1104 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1105 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1106 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1107 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1108 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1109 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1110 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1111 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1112 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1113 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1114 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1115 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1116 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1117 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1118 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1119 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1120 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1121 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1122 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1123 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1124 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1125 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1126 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1127 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ; 1128 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1129 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1130 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1131 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1132 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1133 caps->reserved_lkey = 0; 1134 caps->reserved_pds = 0; 1135 caps->reserved_mrws = 1; 1136 caps->reserved_uars = 0; 1137 caps->reserved_cqs = 0; 1138 1139 caps->qpc_ba_pg_sz = 0; 1140 caps->qpc_buf_pg_sz = 0; 1141 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1142 caps->srqc_ba_pg_sz = 0; 1143 caps->srqc_buf_pg_sz = 0; 1144 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0; 1145 caps->cqc_ba_pg_sz = 0; 1146 caps->cqc_buf_pg_sz = 0; 1147 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1148 caps->mpt_ba_pg_sz = 0; 1149 caps->mpt_buf_pg_sz = 0; 1150 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1151 caps->pbl_ba_pg_sz = 0; 1152 caps->pbl_buf_pg_sz = 0; 1153 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 1154 caps->mtt_ba_pg_sz = 0; 1155 caps->mtt_buf_pg_sz = 0; 1156 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1157 caps->cqe_ba_pg_sz = 0; 1158 caps->cqe_buf_pg_sz = 0; 1159 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1160 caps->eqe_ba_pg_sz = 0; 1161 caps->eqe_buf_pg_sz = 0; 1162 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 1163 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1164 1165 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1166 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1167 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1168 HNS_ROCE_CAP_FLAG_RECORD_DB; 1169 caps->pkey_table_len[0] = 1; 1170 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1171 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1172 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1173 caps->local_ca_ack_delay = 0; 1174 caps->max_mtu = IB_MTU_4096; 1175 1176 ret = hns_roce_v2_set_bt(hr_dev); 1177 if (ret) 1178 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 1179 ret); 1180 1181 return ret; 1182 } 1183 1184 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 1185 { 1186 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1187 1188 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 1189 } 1190 1191 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 1192 { 1193 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG); 1194 1195 return status & HNS_ROCE_HW_MB_STATUS_MASK; 1196 } 1197 1198 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 1199 u64 out_param, u32 in_modifier, u8 op_modifier, 1200 u16 op, u16 token, int event) 1201 { 1202 struct device *dev = hr_dev->dev; 1203 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + 1204 ROCEE_VF_MB_CFG0_REG); 1205 unsigned long end; 1206 u32 val0 = 0; 1207 u32 val1 = 0; 1208 1209 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 1210 while (hns_roce_v2_cmd_pending(hr_dev)) { 1211 if (time_after(jiffies, end)) { 1212 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 1213 (int)end); 1214 return -EAGAIN; 1215 } 1216 cond_resched(); 1217 } 1218 1219 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK, 1220 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier); 1221 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK, 1222 HNS_ROCE_VF_MB4_CMD_SHIFT, op); 1223 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK, 1224 HNS_ROCE_VF_MB5_EVENT_SHIFT, event); 1225 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK, 1226 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token); 1227 1228 writeq(in_param, hcr + 0); 1229 writeq(out_param, hcr + 2); 1230 1231 /* Memory barrier */ 1232 wmb(); 1233 1234 writel(val0, hcr + 4); 1235 writel(val1, hcr + 5); 1236 1237 mmiowb(); 1238 1239 return 0; 1240 } 1241 1242 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 1243 unsigned long timeout) 1244 { 1245 struct device *dev = hr_dev->dev; 1246 unsigned long end = 0; 1247 u32 status; 1248 1249 end = msecs_to_jiffies(timeout) + jiffies; 1250 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 1251 cond_resched(); 1252 1253 if (hns_roce_v2_cmd_pending(hr_dev)) { 1254 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 1255 return -ETIMEDOUT; 1256 } 1257 1258 status = hns_roce_v2_cmd_complete(hr_dev); 1259 if (status != 0x1) { 1260 dev_err(dev, "mailbox status 0x%x!\n", status); 1261 return -EBUSY; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 1268 int gid_index, union ib_gid *gid, 1269 const struct ib_gid_attr *attr) 1270 { 1271 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 1272 u32 *p; 1273 u32 val; 1274 1275 if (!gid || !attr) 1276 return -EINVAL; 1277 1278 if (attr->gid_type == IB_GID_TYPE_ROCE) 1279 sgid_type = GID_TYPE_FLAG_ROCE_V1; 1280 1281 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 1282 if (ipv6_addr_v4mapped((void *)gid)) 1283 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 1284 else 1285 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 1286 } 1287 1288 p = (u32 *)&gid->raw[0]; 1289 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG + 1290 0x20 * gid_index); 1291 1292 p = (u32 *)&gid->raw[4]; 1293 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG + 1294 0x20 * gid_index); 1295 1296 p = (u32 *)&gid->raw[8]; 1297 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG + 1298 0x20 * gid_index); 1299 1300 p = (u32 *)&gid->raw[0xc]; 1301 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG + 1302 0x20 * gid_index); 1303 1304 val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index); 1305 roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M, 1306 ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type); 1307 1308 roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val); 1309 1310 return 0; 1311 } 1312 1313 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 1314 u8 *addr) 1315 { 1316 u16 reg_smac_h; 1317 u32 reg_smac_l; 1318 u32 val; 1319 1320 reg_smac_l = *(u32 *)(&addr[0]); 1321 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG + 1322 0x08 * phy_port); 1323 val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port); 1324 1325 reg_smac_h = *(u16 *)(&addr[4]); 1326 roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M, 1327 ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h); 1328 roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val); 1329 1330 return 0; 1331 } 1332 1333 static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, 1334 unsigned long mtpt_idx) 1335 { 1336 struct hns_roce_v2_mpt_entry *mpt_entry; 1337 struct scatterlist *sg; 1338 u64 page_addr; 1339 u64 *pages; 1340 int i, j; 1341 int len; 1342 int entry; 1343 1344 mpt_entry = mb_buf; 1345 memset(mpt_entry, 0, sizeof(*mpt_entry)); 1346 1347 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 1348 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 1349 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 1350 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 1351 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 1352 roce_set_field(mpt_entry->byte_4_pd_hop_st, 1353 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 1354 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz); 1355 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1356 V2_MPT_BYTE_4_PD_S, mr->pd); 1357 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st); 1358 1359 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 1360 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 1361 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0); 1362 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 1363 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 1364 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0); 1365 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1366 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1367 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1368 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1369 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1370 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1371 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en); 1372 1373 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 1374 mr->type == MR_TYPE_MR ? 0 : 1); 1375 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa); 1376 1377 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 1378 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 1379 mpt_entry->lkey = cpu_to_le32(mr->key); 1380 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 1381 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 1382 1383 if (mr->type == MR_TYPE_DMA) 1384 return 0; 1385 1386 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1387 1388 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1389 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 1390 V2_MPT_BYTE_48_PBL_BA_H_S, 1391 upper_32_bits(mr->pbl_ba >> 3)); 1392 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba); 1393 1394 pages = (u64 *)__get_free_page(GFP_KERNEL); 1395 if (!pages) 1396 return -ENOMEM; 1397 1398 i = 0; 1399 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) { 1400 len = sg_dma_len(sg) >> PAGE_SHIFT; 1401 for (j = 0; j < len; ++j) { 1402 page_addr = sg_dma_address(sg) + 1403 (j << mr->umem->page_shift); 1404 pages[i] = page_addr >> 6; 1405 1406 /* Record the first 2 entry directly to MTPT table */ 1407 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) 1408 goto found; 1409 i++; 1410 } 1411 } 1412 1413 found: 1414 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 1415 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 1416 V2_MPT_BYTE_56_PA0_H_S, 1417 upper_32_bits(pages[0])); 1418 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h); 1419 1420 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 1421 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 1422 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 1423 1424 free_page((unsigned long)pages); 1425 1426 roce_set_field(mpt_entry->byte_64_buf_pa1, 1427 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 1428 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz); 1429 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1); 1430 1431 return 0; 1432 } 1433 1434 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 1435 struct hns_roce_mr *mr, int flags, 1436 u32 pdn, int mr_access_flags, u64 iova, 1437 u64 size, void *mb_buf) 1438 { 1439 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 1440 1441 if (flags & IB_MR_REREG_PD) { 1442 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 1443 V2_MPT_BYTE_4_PD_S, pdn); 1444 mr->pd = pdn; 1445 } 1446 1447 if (flags & IB_MR_REREG_ACCESS) { 1448 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1449 V2_MPT_BYTE_8_BIND_EN_S, 1450 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 1451 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 1452 V2_MPT_BYTE_8_ATOMIC_EN_S, 1453 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0)); 1454 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 1455 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0)); 1456 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 1457 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 1458 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1459 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 1460 } 1461 1462 if (flags & IB_MR_REREG_TRANS) { 1463 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 1464 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 1465 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 1466 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 1467 1468 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); 1469 mpt_entry->pbl_ba_l = 1470 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); 1471 roce_set_field(mpt_entry->byte_48_mode_ba, 1472 V2_MPT_BYTE_48_PBL_BA_H_M, 1473 V2_MPT_BYTE_48_PBL_BA_H_S, 1474 upper_32_bits(mr->pbl_ba >> 3)); 1475 mpt_entry->byte_48_mode_ba = 1476 cpu_to_le32(mpt_entry->byte_48_mode_ba); 1477 1478 mr->iova = iova; 1479 mr->size = size; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1486 { 1487 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf, 1488 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 1489 } 1490 1491 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 1492 { 1493 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 1494 1495 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 1496 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 1497 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL; 1498 } 1499 1500 static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq) 1501 { 1502 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 1503 } 1504 1505 static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) 1506 { 1507 *hr_cq->set_ci_db = cons_index & 0xffffff; 1508 } 1509 1510 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1511 struct hns_roce_srq *srq) 1512 { 1513 struct hns_roce_v2_cqe *cqe, *dest; 1514 u32 prod_index; 1515 int nfreed = 0; 1516 u8 owner_bit; 1517 1518 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 1519 ++prod_index) { 1520 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe) 1521 break; 1522 } 1523 1524 /* 1525 * Now backwards through the CQ, removing CQ entries 1526 * that match our QP by overwriting them with next entries. 1527 */ 1528 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 1529 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 1530 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1531 V2_CQE_BYTE_16_LCL_QPN_S) & 1532 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 1533 /* In v1 engine, not support SRQ */ 1534 ++nfreed; 1535 } else if (nfreed) { 1536 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 1537 hr_cq->ib_cq.cqe); 1538 owner_bit = roce_get_bit(dest->byte_4, 1539 V2_CQE_BYTE_4_OWNER_S); 1540 memcpy(dest, cqe, sizeof(*cqe)); 1541 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 1542 owner_bit); 1543 } 1544 } 1545 1546 if (nfreed) { 1547 hr_cq->cons_index += nfreed; 1548 /* 1549 * Make sure update of buffer contents is done before 1550 * updating consumer index. 1551 */ 1552 wmb(); 1553 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1554 } 1555 } 1556 1557 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 1558 struct hns_roce_srq *srq) 1559 { 1560 spin_lock_irq(&hr_cq->lock); 1561 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 1562 spin_unlock_irq(&hr_cq->lock); 1563 } 1564 1565 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 1566 struct hns_roce_cq *hr_cq, void *mb_buf, 1567 u64 *mtts, dma_addr_t dma_handle, int nent, 1568 u32 vector) 1569 { 1570 struct hns_roce_v2_cq_context *cq_context; 1571 1572 cq_context = mb_buf; 1573 memset(cq_context, 0, sizeof(*cq_context)); 1574 1575 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 1576 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 1577 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 1578 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 1579 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 1580 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent)); 1581 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 1582 V2_CQC_BYTE_4_CEQN_S, vector); 1583 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn); 1584 1585 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 1586 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 1587 1588 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 1589 cq_context->cqe_cur_blk_addr = 1590 cpu_to_le32(cq_context->cqe_cur_blk_addr); 1591 1592 roce_set_field(cq_context->byte_16_hop_addr, 1593 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 1594 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 1595 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT))); 1596 roce_set_field(cq_context->byte_16_hop_addr, 1597 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 1598 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 1599 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 1600 1601 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT); 1602 roce_set_field(cq_context->byte_24_pgsz_addr, 1603 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 1604 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 1605 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT))); 1606 roce_set_field(cq_context->byte_24_pgsz_addr, 1607 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 1608 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 1609 hr_dev->caps.cqe_ba_pg_sz); 1610 roce_set_field(cq_context->byte_24_pgsz_addr, 1611 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 1612 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 1613 hr_dev->caps.cqe_buf_pg_sz); 1614 1615 cq_context->cqe_ba = (u32)(dma_handle >> 3); 1616 1617 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 1618 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 1619 1620 if (hr_cq->db_en) 1621 roce_set_bit(cq_context->byte_44_db_record, 1622 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1); 1623 1624 roce_set_field(cq_context->byte_44_db_record, 1625 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 1626 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 1627 ((u32)hr_cq->db.dma) >> 1); 1628 cq_context->db_record_addr = hr_cq->db.dma >> 32; 1629 1630 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1631 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 1632 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 1633 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 1634 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 1635 V2_CQC_BYTE_56_CQ_PERIOD_M, 1636 V2_CQC_BYTE_56_CQ_PERIOD_S, 1637 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 1638 } 1639 1640 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 1641 enum ib_cq_notify_flags flags) 1642 { 1643 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1644 u32 notification_flag; 1645 u32 doorbell[2]; 1646 1647 doorbell[0] = 0; 1648 doorbell[1] = 0; 1649 1650 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 1651 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 1652 /* 1653 * flags = 0; Notification Flag = 1, next 1654 * flags = 1; Notification Flag = 0, solocited 1655 */ 1656 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 1657 hr_cq->cqn); 1658 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 1659 HNS_ROCE_V2_CQ_DB_NTR); 1660 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 1661 V2_CQ_DB_PARAMETER_CONS_IDX_S, 1662 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); 1663 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 1664 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 1665 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 1666 notification_flag); 1667 1668 hns_roce_write64_k(doorbell, hr_cq->cq_db_l); 1669 1670 return 0; 1671 } 1672 1673 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 1674 struct hns_roce_qp **cur_qp, 1675 struct ib_wc *wc) 1676 { 1677 struct hns_roce_rinl_sge *sge_list; 1678 u32 wr_num, wr_cnt, sge_num; 1679 u32 sge_cnt, data_len, size; 1680 void *wqe_buf; 1681 1682 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 1683 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 1684 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 1685 1686 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 1687 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 1688 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt); 1689 data_len = wc->byte_len; 1690 1691 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 1692 size = min(sge_list[sge_cnt].len, data_len); 1693 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 1694 1695 data_len -= size; 1696 wqe_buf += size; 1697 } 1698 1699 if (data_len) { 1700 wc->status = IB_WC_LOC_LEN_ERR; 1701 return -EAGAIN; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 1708 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 1709 { 1710 struct hns_roce_dev *hr_dev; 1711 struct hns_roce_v2_cqe *cqe; 1712 struct hns_roce_qp *hr_qp; 1713 struct hns_roce_wq *wq; 1714 int is_send; 1715 u16 wqe_ctr; 1716 u32 opcode; 1717 u32 status; 1718 int qpn; 1719 int ret; 1720 1721 /* Find cqe according to consumer index */ 1722 cqe = next_cqe_sw_v2(hr_cq); 1723 if (!cqe) 1724 return -EAGAIN; 1725 1726 ++hr_cq->cons_index; 1727 /* Memory barrier */ 1728 rmb(); 1729 1730 /* 0->SQ, 1->RQ */ 1731 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 1732 1733 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 1734 V2_CQE_BYTE_16_LCL_QPN_S); 1735 1736 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 1737 hr_dev = to_hr_dev(hr_cq->ib_cq.device); 1738 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 1739 if (unlikely(!hr_qp)) { 1740 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n", 1741 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK)); 1742 return -EINVAL; 1743 } 1744 *cur_qp = hr_qp; 1745 } 1746 1747 wc->qp = &(*cur_qp)->ibqp; 1748 wc->vendor_err = 0; 1749 1750 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 1751 V2_CQE_BYTE_4_STATUS_S); 1752 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) { 1753 case HNS_ROCE_CQE_V2_SUCCESS: 1754 wc->status = IB_WC_SUCCESS; 1755 break; 1756 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR: 1757 wc->status = IB_WC_LOC_LEN_ERR; 1758 break; 1759 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR: 1760 wc->status = IB_WC_LOC_QP_OP_ERR; 1761 break; 1762 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR: 1763 wc->status = IB_WC_LOC_PROT_ERR; 1764 break; 1765 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR: 1766 wc->status = IB_WC_WR_FLUSH_ERR; 1767 break; 1768 case HNS_ROCE_CQE_V2_MW_BIND_ERR: 1769 wc->status = IB_WC_MW_BIND_ERR; 1770 break; 1771 case HNS_ROCE_CQE_V2_BAD_RESP_ERR: 1772 wc->status = IB_WC_BAD_RESP_ERR; 1773 break; 1774 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR: 1775 wc->status = IB_WC_LOC_ACCESS_ERR; 1776 break; 1777 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR: 1778 wc->status = IB_WC_REM_INV_REQ_ERR; 1779 break; 1780 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR: 1781 wc->status = IB_WC_REM_ACCESS_ERR; 1782 break; 1783 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR: 1784 wc->status = IB_WC_REM_OP_ERR; 1785 break; 1786 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR: 1787 wc->status = IB_WC_RETRY_EXC_ERR; 1788 break; 1789 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR: 1790 wc->status = IB_WC_RNR_RETRY_EXC_ERR; 1791 break; 1792 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR: 1793 wc->status = IB_WC_REM_ABORT_ERR; 1794 break; 1795 default: 1796 wc->status = IB_WC_GENERAL_ERR; 1797 break; 1798 } 1799 1800 /* CQE status error, directly return */ 1801 if (wc->status != IB_WC_SUCCESS) 1802 return 0; 1803 1804 if (is_send) { 1805 wc->wc_flags = 0; 1806 /* SQ corresponding to CQE */ 1807 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1808 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 1809 case HNS_ROCE_SQ_OPCODE_SEND: 1810 wc->opcode = IB_WC_SEND; 1811 break; 1812 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: 1813 wc->opcode = IB_WC_SEND; 1814 break; 1815 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: 1816 wc->opcode = IB_WC_SEND; 1817 wc->wc_flags |= IB_WC_WITH_IMM; 1818 break; 1819 case HNS_ROCE_SQ_OPCODE_RDMA_READ: 1820 wc->opcode = IB_WC_RDMA_READ; 1821 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1822 break; 1823 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: 1824 wc->opcode = IB_WC_RDMA_WRITE; 1825 break; 1826 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: 1827 wc->opcode = IB_WC_RDMA_WRITE; 1828 wc->wc_flags |= IB_WC_WITH_IMM; 1829 break; 1830 case HNS_ROCE_SQ_OPCODE_LOCAL_INV: 1831 wc->opcode = IB_WC_LOCAL_INV; 1832 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 1833 break; 1834 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: 1835 wc->opcode = IB_WC_COMP_SWAP; 1836 wc->byte_len = 8; 1837 break; 1838 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: 1839 wc->opcode = IB_WC_FETCH_ADD; 1840 wc->byte_len = 8; 1841 break; 1842 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: 1843 wc->opcode = IB_WC_MASKED_COMP_SWAP; 1844 wc->byte_len = 8; 1845 break; 1846 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: 1847 wc->opcode = IB_WC_MASKED_FETCH_ADD; 1848 wc->byte_len = 8; 1849 break; 1850 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: 1851 wc->opcode = IB_WC_REG_MR; 1852 break; 1853 case HNS_ROCE_SQ_OPCODE_BIND_MW: 1854 wc->opcode = IB_WC_REG_MR; 1855 break; 1856 default: 1857 wc->status = IB_WC_GENERAL_ERR; 1858 break; 1859 } 1860 1861 wq = &(*cur_qp)->sq; 1862 if ((*cur_qp)->sq_signal_bits) { 1863 /* 1864 * If sg_signal_bit is 1, 1865 * firstly tail pointer updated to wqe 1866 * which current cqe correspond to 1867 */ 1868 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 1869 V2_CQE_BYTE_4_WQE_INDX_M, 1870 V2_CQE_BYTE_4_WQE_INDX_S); 1871 wq->tail += (wqe_ctr - (u16)wq->tail) & 1872 (wq->wqe_cnt - 1); 1873 } 1874 1875 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1876 ++wq->tail; 1877 } else { 1878 /* RQ correspond to CQE */ 1879 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 1880 1881 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 1882 V2_CQE_BYTE_4_OPCODE_S); 1883 switch (opcode & 0x1f) { 1884 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 1885 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 1886 wc->wc_flags = IB_WC_WITH_IMM; 1887 wc->ex.imm_data = cqe->immtdata; 1888 break; 1889 case HNS_ROCE_V2_OPCODE_SEND: 1890 wc->opcode = IB_WC_RECV; 1891 wc->wc_flags = 0; 1892 break; 1893 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 1894 wc->opcode = IB_WC_RECV; 1895 wc->wc_flags = IB_WC_WITH_IMM; 1896 wc->ex.imm_data = cqe->immtdata; 1897 break; 1898 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 1899 wc->opcode = IB_WC_RECV; 1900 wc->wc_flags = IB_WC_WITH_INVALIDATE; 1901 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 1902 break; 1903 default: 1904 wc->status = IB_WC_GENERAL_ERR; 1905 break; 1906 } 1907 1908 if ((wc->qp->qp_type == IB_QPT_RC || 1909 wc->qp->qp_type == IB_QPT_UC) && 1910 (opcode == HNS_ROCE_V2_OPCODE_SEND || 1911 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 1912 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 1913 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 1914 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 1915 if (ret) 1916 return -EAGAIN; 1917 } 1918 1919 /* Update tail pointer, record wr_id */ 1920 wq = &(*cur_qp)->rq; 1921 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 1922 ++wq->tail; 1923 1924 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 1925 V2_CQE_BYTE_32_SL_S); 1926 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 1927 V2_CQE_BYTE_32_RMT_QPN_M, 1928 V2_CQE_BYTE_32_RMT_QPN_S); 1929 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 1930 V2_CQE_BYTE_32_GRH_S) ? 1931 IB_WC_GRH : 0); 1932 wc->port_num = roce_get_field(cqe->byte_32, 1933 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 1934 wc->pkey_index = 0; 1935 memcpy(wc->smac, cqe->smac, 4); 1936 wc->smac[4] = roce_get_field(cqe->byte_28, 1937 V2_CQE_BYTE_28_SMAC_4_M, 1938 V2_CQE_BYTE_28_SMAC_4_S); 1939 wc->smac[5] = roce_get_field(cqe->byte_28, 1940 V2_CQE_BYTE_28_SMAC_5_M, 1941 V2_CQE_BYTE_28_SMAC_5_S); 1942 wc->vlan_id = 0xffff; 1943 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC); 1944 wc->network_hdr_type = roce_get_field(cqe->byte_28, 1945 V2_CQE_BYTE_28_PORT_TYPE_M, 1946 V2_CQE_BYTE_28_PORT_TYPE_S); 1947 } 1948 1949 return 0; 1950 } 1951 1952 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 1953 struct ib_wc *wc) 1954 { 1955 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 1956 struct hns_roce_qp *cur_qp = NULL; 1957 unsigned long flags; 1958 int npolled; 1959 1960 spin_lock_irqsave(&hr_cq->lock, flags); 1961 1962 for (npolled = 0; npolled < num_entries; ++npolled) { 1963 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 1964 break; 1965 } 1966 1967 if (npolled) { 1968 /* Memory barrier */ 1969 wmb(); 1970 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 1971 } 1972 1973 spin_unlock_irqrestore(&hr_cq->lock, flags); 1974 1975 return npolled; 1976 } 1977 1978 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 1979 struct hns_roce_hem_table *table, int obj, 1980 int step_idx) 1981 { 1982 struct device *dev = hr_dev->dev; 1983 struct hns_roce_cmd_mailbox *mailbox; 1984 struct hns_roce_hem_iter iter; 1985 struct hns_roce_hem_mhop mhop; 1986 struct hns_roce_hem *hem; 1987 unsigned long mhop_obj = obj; 1988 int i, j, k; 1989 int ret = 0; 1990 u64 hem_idx = 0; 1991 u64 l1_idx = 0; 1992 u64 bt_ba = 0; 1993 u32 chunk_ba_num; 1994 u32 hop_num; 1995 u16 op = 0xff; 1996 1997 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 1998 return 0; 1999 2000 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 2001 i = mhop.l0_idx; 2002 j = mhop.l1_idx; 2003 k = mhop.l2_idx; 2004 hop_num = mhop.hop_num; 2005 chunk_ba_num = mhop.bt_chunk_size / 8; 2006 2007 if (hop_num == 2) { 2008 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 2009 k; 2010 l1_idx = i * chunk_ba_num + j; 2011 } else if (hop_num == 1) { 2012 hem_idx = i * chunk_ba_num + j; 2013 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 2014 hem_idx = i; 2015 } 2016 2017 switch (table->type) { 2018 case HEM_TYPE_QPC: 2019 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 2020 break; 2021 case HEM_TYPE_MTPT: 2022 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 2023 break; 2024 case HEM_TYPE_CQC: 2025 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 2026 break; 2027 case HEM_TYPE_SRQC: 2028 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 2029 break; 2030 default: 2031 dev_warn(dev, "Table %d not to be written by mailbox!\n", 2032 table->type); 2033 return 0; 2034 } 2035 op += step_idx; 2036 2037 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2038 if (IS_ERR(mailbox)) 2039 return PTR_ERR(mailbox); 2040 2041 if (check_whether_last_step(hop_num, step_idx)) { 2042 hem = table->hem[hem_idx]; 2043 for (hns_roce_hem_first(hem, &iter); 2044 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 2045 bt_ba = hns_roce_hem_addr(&iter); 2046 2047 /* configure the ba, tag, and op */ 2048 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, 2049 obj, 0, op, 2050 HNS_ROCE_CMD_TIMEOUT_MSECS); 2051 } 2052 } else { 2053 if (step_idx == 0) 2054 bt_ba = table->bt_l0_dma_addr[i]; 2055 else if (step_idx == 1 && hop_num == 2) 2056 bt_ba = table->bt_l1_dma_addr[l1_idx]; 2057 2058 /* configure the ba, tag, and op */ 2059 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 2060 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 2061 } 2062 2063 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2064 return ret; 2065 } 2066 2067 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 2068 struct hns_roce_hem_table *table, int obj, 2069 int step_idx) 2070 { 2071 struct device *dev = hr_dev->dev; 2072 struct hns_roce_cmd_mailbox *mailbox; 2073 int ret = 0; 2074 u16 op = 0xff; 2075 2076 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 2077 return 0; 2078 2079 switch (table->type) { 2080 case HEM_TYPE_QPC: 2081 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 2082 break; 2083 case HEM_TYPE_MTPT: 2084 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 2085 break; 2086 case HEM_TYPE_CQC: 2087 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 2088 break; 2089 case HEM_TYPE_SRQC: 2090 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 2091 break; 2092 default: 2093 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 2094 table->type); 2095 return 0; 2096 } 2097 op += step_idx; 2098 2099 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2100 if (IS_ERR(mailbox)) 2101 return PTR_ERR(mailbox); 2102 2103 /* configure the tag and op */ 2104 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 2105 HNS_ROCE_CMD_TIMEOUT_MSECS); 2106 2107 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2108 return ret; 2109 } 2110 2111 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 2112 struct hns_roce_mtt *mtt, 2113 enum ib_qp_state cur_state, 2114 enum ib_qp_state new_state, 2115 struct hns_roce_v2_qp_context *context, 2116 struct hns_roce_qp *hr_qp) 2117 { 2118 struct hns_roce_cmd_mailbox *mailbox; 2119 int ret; 2120 2121 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2122 if (IS_ERR(mailbox)) 2123 return PTR_ERR(mailbox); 2124 2125 memcpy(mailbox->buf, context, sizeof(*context) * 2); 2126 2127 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 2128 HNS_ROCE_CMD_MODIFY_QPC, 2129 HNS_ROCE_CMD_TIMEOUT_MSECS); 2130 2131 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2132 2133 return ret; 2134 } 2135 2136 static void set_access_flags(struct hns_roce_qp *hr_qp, 2137 struct hns_roce_v2_qp_context *context, 2138 struct hns_roce_v2_qp_context *qpc_mask, 2139 const struct ib_qp_attr *attr, int attr_mask) 2140 { 2141 u8 dest_rd_atomic; 2142 u32 access_flags; 2143 2144 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 2145 attr->max_dest_rd_atomic : hr_qp->resp_depth; 2146 2147 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 2148 attr->qp_access_flags : hr_qp->atomic_rd_en; 2149 2150 if (!dest_rd_atomic) 2151 access_flags &= IB_ACCESS_REMOTE_WRITE; 2152 2153 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2154 !!(access_flags & IB_ACCESS_REMOTE_READ)); 2155 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 2156 2157 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2158 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 2159 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 2160 2161 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2162 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2163 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 2164 } 2165 2166 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 2167 const struct ib_qp_attr *attr, 2168 int attr_mask, 2169 struct hns_roce_v2_qp_context *context, 2170 struct hns_roce_v2_qp_context *qpc_mask) 2171 { 2172 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2173 2174 /* 2175 * In v2 engine, software pass context and context mask to hardware 2176 * when modifying qp. If software need modify some fields in context, 2177 * we should set all bits of the relevant fields in context mask to 2178 * 0 at the same time, else set them to 0x1. 2179 */ 2180 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2181 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2182 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2183 V2_QPC_BYTE_4_TST_S, 0); 2184 2185 if (ibqp->qp_type == IB_QPT_GSI) 2186 roce_set_field(context->byte_4_sqpn_tst, 2187 V2_QPC_BYTE_4_SGE_SHIFT_M, 2188 V2_QPC_BYTE_4_SGE_SHIFT_S, 2189 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2190 else 2191 roce_set_field(context->byte_4_sqpn_tst, 2192 V2_QPC_BYTE_4_SGE_SHIFT_M, 2193 V2_QPC_BYTE_4_SGE_SHIFT_S, 2194 hr_qp->sq.max_gs > 2 ? 2195 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2196 2197 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2198 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2199 2200 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2201 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2202 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2203 V2_QPC_BYTE_4_SQPN_S, 0); 2204 2205 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2206 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2207 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2208 V2_QPC_BYTE_16_PD_S, 0); 2209 2210 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2211 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 2212 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 2213 V2_QPC_BYTE_20_RQWS_S, 0); 2214 2215 roce_set_field(context->byte_20_smac_sgid_idx, 2216 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2217 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2218 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2219 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2220 2221 roce_set_field(context->byte_20_smac_sgid_idx, 2222 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2223 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2224 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2225 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2226 2227 /* No VLAN need to set 0xFFF */ 2228 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2229 V2_QPC_BYTE_24_VLAN_IDX_S, 0xfff); 2230 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M, 2231 V2_QPC_BYTE_24_VLAN_IDX_S, 0); 2232 2233 /* 2234 * Set some fields in context to zero, Because the default values 2235 * of all fields in context are zero, we need not set them to 0 again. 2236 * but we should set the relevant fields of context mask to 0. 2237 */ 2238 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0); 2239 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0); 2240 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0); 2241 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0); 2242 2243 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M, 2244 V2_QPC_BYTE_60_MAPID_S, 0); 2245 2246 roce_set_bit(qpc_mask->byte_60_qpst_mapid, 2247 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0); 2248 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S, 2249 0); 2250 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S, 2251 0); 2252 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S, 2253 0); 2254 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S, 2255 0); 2256 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S, 2257 0); 2258 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0); 2259 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0); 2260 2261 if (attr_mask & IB_QP_QKEY) { 2262 context->qkey_xrcd = attr->qkey; 2263 qpc_mask->qkey_xrcd = 0; 2264 hr_qp->qkey = attr->qkey; 2265 } 2266 2267 if (hr_qp->rdb_en) { 2268 roce_set_bit(context->byte_68_rq_db, 2269 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 2270 roce_set_bit(qpc_mask->byte_68_rq_db, 2271 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0); 2272 } 2273 2274 roce_set_field(context->byte_68_rq_db, 2275 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2276 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 2277 ((u32)hr_qp->rdb.dma) >> 1); 2278 roce_set_field(qpc_mask->byte_68_rq_db, 2279 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 2280 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0); 2281 context->rq_db_record_addr = hr_qp->rdb.dma >> 32; 2282 qpc_mask->rq_db_record_addr = 0; 2283 2284 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 1); 2285 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0); 2286 2287 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2288 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2289 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2290 V2_QPC_BYTE_80_RX_CQN_S, 0); 2291 if (ibqp->srq) { 2292 roce_set_field(context->byte_76_srqn_op_en, 2293 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2294 to_hr_srq(ibqp->srq)->srqn); 2295 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2296 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2297 roce_set_bit(context->byte_76_srqn_op_en, 2298 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2299 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2300 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2301 } 2302 2303 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2304 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2305 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2306 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2307 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2308 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2309 2310 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M, 2311 V2_QPC_BYTE_92_SRQ_INFO_S, 0); 2312 2313 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2314 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2315 2316 roce_set_field(qpc_mask->byte_104_rq_sge, 2317 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M, 2318 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0); 2319 2320 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2321 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2322 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2323 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2324 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2325 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2326 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0); 2327 2328 qpc_mask->rq_rnr_timer = 0; 2329 qpc_mask->rx_msg_len = 0; 2330 qpc_mask->rx_rkey_pkt_info = 0; 2331 qpc_mask->rx_va = 0; 2332 2333 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2334 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2335 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2336 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2337 2338 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0); 2339 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M, 2340 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0); 2341 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M, 2342 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0); 2343 2344 roce_set_field(qpc_mask->byte_144_raq, 2345 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M, 2346 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0); 2347 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S, 2348 0); 2349 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M, 2350 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0); 2351 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0); 2352 2353 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M, 2354 V2_QPC_BYTE_148_RQ_MSN_S, 0); 2355 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M, 2356 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0); 2357 2358 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2359 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2360 roce_set_field(qpc_mask->byte_152_raq, 2361 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M, 2362 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0); 2363 2364 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M, 2365 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0); 2366 2367 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2368 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 2369 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 2370 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 2371 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M, 2372 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0); 2373 2374 roce_set_field(context->byte_168_irrl_idx, 2375 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2376 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2377 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2378 roce_set_field(qpc_mask->byte_168_irrl_idx, 2379 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2380 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2381 2382 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2383 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0); 2384 roce_set_bit(qpc_mask->byte_168_irrl_idx, 2385 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0); 2386 roce_set_field(qpc_mask->byte_168_irrl_idx, 2387 V2_QPC_BYTE_168_IRRL_IDX_LSB_M, 2388 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0); 2389 2390 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2391 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 2392 roce_set_field(qpc_mask->byte_172_sq_psn, 2393 V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 2394 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0); 2395 2396 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S, 2397 0); 2398 2399 roce_set_field(qpc_mask->byte_176_msg_pktn, 2400 V2_QPC_BYTE_176_MSG_USE_PKTN_M, 2401 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0); 2402 roce_set_field(qpc_mask->byte_176_msg_pktn, 2403 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M, 2404 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0); 2405 2406 roce_set_field(qpc_mask->byte_184_irrl_idx, 2407 V2_QPC_BYTE_184_IRRL_IDX_MSB_M, 2408 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0); 2409 2410 qpc_mask->cur_sge_offset = 0; 2411 2412 roce_set_field(qpc_mask->byte_192_ext_sge, 2413 V2_QPC_BYTE_192_CUR_SGE_IDX_M, 2414 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0); 2415 roce_set_field(qpc_mask->byte_192_ext_sge, 2416 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M, 2417 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0); 2418 2419 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 2420 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 2421 2422 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M, 2423 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0); 2424 roce_set_field(qpc_mask->byte_200_sq_max, 2425 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M, 2426 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0); 2427 2428 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0); 2429 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0); 2430 2431 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 2432 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 2433 2434 qpc_mask->sq_timer = 0; 2435 2436 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 2437 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 2438 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 2439 roce_set_field(qpc_mask->byte_232_irrl_sge, 2440 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2441 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2442 2443 qpc_mask->irrl_cur_sge_offset = 0; 2444 2445 roce_set_field(qpc_mask->byte_240_irrl_tail, 2446 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 2447 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 2448 roce_set_field(qpc_mask->byte_240_irrl_tail, 2449 V2_QPC_BYTE_240_IRRL_TAIL_RD_M, 2450 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0); 2451 roce_set_field(qpc_mask->byte_240_irrl_tail, 2452 V2_QPC_BYTE_240_RX_ACK_MSN_M, 2453 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 2454 2455 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M, 2456 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 2457 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S, 2458 0); 2459 roce_set_field(qpc_mask->byte_248_ack_psn, 2460 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 2461 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 2462 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 2463 0); 2464 roce_set_bit(qpc_mask->byte_248_ack_psn, 2465 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 2466 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S, 2467 0); 2468 2469 hr_qp->access_flags = attr->qp_access_flags; 2470 hr_qp->pkey_index = attr->pkey_index; 2471 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2472 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2473 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2474 V2_QPC_BYTE_252_TX_CQN_S, 0); 2475 2476 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M, 2477 V2_QPC_BYTE_252_ERR_TYPE_S, 0); 2478 2479 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2480 V2_QPC_BYTE_256_RQ_CQE_IDX_M, 2481 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0); 2482 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe, 2483 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M, 2484 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0); 2485 } 2486 2487 static void modify_qp_init_to_init(struct ib_qp *ibqp, 2488 const struct ib_qp_attr *attr, int attr_mask, 2489 struct hns_roce_v2_qp_context *context, 2490 struct hns_roce_v2_qp_context *qpc_mask) 2491 { 2492 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2493 2494 /* 2495 * In v2 engine, software pass context and context mask to hardware 2496 * when modifying qp. If software need modify some fields in context, 2497 * we should set all bits of the relevant fields in context mask to 2498 * 0 at the same time, else set them to 0x1. 2499 */ 2500 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2501 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 2502 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 2503 V2_QPC_BYTE_4_TST_S, 0); 2504 2505 if (ibqp->qp_type == IB_QPT_GSI) 2506 roce_set_field(context->byte_4_sqpn_tst, 2507 V2_QPC_BYTE_4_SGE_SHIFT_M, 2508 V2_QPC_BYTE_4_SGE_SHIFT_S, 2509 ilog2((unsigned int)hr_qp->sge.sge_cnt)); 2510 else 2511 roce_set_field(context->byte_4_sqpn_tst, 2512 V2_QPC_BYTE_4_SGE_SHIFT_M, 2513 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ? 2514 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); 2515 2516 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M, 2517 V2_QPC_BYTE_4_SGE_SHIFT_S, 0); 2518 2519 if (attr_mask & IB_QP_ACCESS_FLAGS) { 2520 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2521 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 2522 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2523 0); 2524 2525 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2526 !!(attr->qp_access_flags & 2527 IB_ACCESS_REMOTE_WRITE)); 2528 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2529 0); 2530 2531 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2532 !!(attr->qp_access_flags & 2533 IB_ACCESS_REMOTE_ATOMIC)); 2534 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2535 0); 2536 } else { 2537 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2538 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 2539 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 2540 0); 2541 2542 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2543 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 2544 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 2545 0); 2546 2547 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2548 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 2549 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 2550 0); 2551 } 2552 2553 roce_set_field(context->byte_20_smac_sgid_idx, 2554 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 2555 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2556 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2557 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0); 2558 2559 roce_set_field(context->byte_20_smac_sgid_idx, 2560 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 2561 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 2562 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2563 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0); 2564 2565 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2566 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 2567 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 2568 V2_QPC_BYTE_16_PD_S, 0); 2569 2570 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2571 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 2572 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 2573 V2_QPC_BYTE_80_RX_CQN_S, 0); 2574 2575 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2576 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 2577 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 2578 V2_QPC_BYTE_252_TX_CQN_S, 0); 2579 2580 if (ibqp->srq) { 2581 roce_set_bit(context->byte_76_srqn_op_en, 2582 V2_QPC_BYTE_76_SRQ_EN_S, 1); 2583 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 2584 V2_QPC_BYTE_76_SRQ_EN_S, 0); 2585 roce_set_field(context->byte_76_srqn_op_en, 2586 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 2587 to_hr_srq(ibqp->srq)->srqn); 2588 roce_set_field(qpc_mask->byte_76_srqn_op_en, 2589 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 2590 } 2591 2592 if (attr_mask & IB_QP_QKEY) { 2593 context->qkey_xrcd = attr->qkey; 2594 qpc_mask->qkey_xrcd = 0; 2595 } 2596 2597 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2598 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 2599 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 2600 V2_QPC_BYTE_4_SQPN_S, 0); 2601 2602 if (attr_mask & IB_QP_DEST_QPN) { 2603 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2604 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 2605 roce_set_field(qpc_mask->byte_56_dqpn_err, 2606 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 2607 } 2608 roce_set_field(context->byte_168_irrl_idx, 2609 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2610 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 2611 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 2612 roce_set_field(qpc_mask->byte_168_irrl_idx, 2613 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M, 2614 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0); 2615 } 2616 2617 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 2618 const struct ib_qp_attr *attr, int attr_mask, 2619 struct hns_roce_v2_qp_context *context, 2620 struct hns_roce_v2_qp_context *qpc_mask) 2621 { 2622 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 2623 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2624 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2625 struct device *dev = hr_dev->dev; 2626 dma_addr_t dma_handle_3; 2627 dma_addr_t dma_handle_2; 2628 dma_addr_t dma_handle; 2629 u32 page_size; 2630 u8 port_num; 2631 u64 *mtts_3; 2632 u64 *mtts_2; 2633 u64 *mtts; 2634 u8 *dmac; 2635 u8 *smac; 2636 int port; 2637 2638 /* Search qp buf's mtts */ 2639 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2640 hr_qp->mtt.first_seg, &dma_handle); 2641 if (!mtts) { 2642 dev_err(dev, "qp buf pa find failed\n"); 2643 return -EINVAL; 2644 } 2645 2646 /* Search IRRL's mtts */ 2647 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 2648 hr_qp->qpn, &dma_handle_2); 2649 if (!mtts_2) { 2650 dev_err(dev, "qp irrl_table find failed\n"); 2651 return -EINVAL; 2652 } 2653 2654 /* Search TRRL's mtts */ 2655 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 2656 hr_qp->qpn, &dma_handle_3); 2657 if (!mtts_3) { 2658 dev_err(dev, "qp trrl_table find failed\n"); 2659 return -EINVAL; 2660 } 2661 2662 if (attr_mask & IB_QP_ALT_PATH) { 2663 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask); 2664 return -EINVAL; 2665 } 2666 2667 dmac = (u8 *)attr->ah_attr.roce.dmac; 2668 context->wqe_sge_ba = (u32)(dma_handle >> 3); 2669 qpc_mask->wqe_sge_ba = 0; 2670 2671 /* 2672 * In v2 engine, software pass context and context mask to hardware 2673 * when modifying qp. If software need modify some fields in context, 2674 * we should set all bits of the relevant fields in context mask to 2675 * 0 at the same time, else set them to 0x1. 2676 */ 2677 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2678 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3)); 2679 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 2680 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 2681 2682 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2683 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 2684 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2685 0 : hr_dev->caps.mtt_hop_num); 2686 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 2687 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 2688 2689 roce_set_field(context->byte_20_smac_sgid_idx, 2690 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2691 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 2692 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2693 hr_dev->caps.mtt_hop_num : 0); 2694 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2695 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 2696 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 2697 2698 roce_set_field(context->byte_20_smac_sgid_idx, 2699 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2700 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 2701 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ? 2702 0 : hr_dev->caps.mtt_hop_num); 2703 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2704 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 2705 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 2706 2707 roce_set_field(context->byte_16_buf_ba_pg_sz, 2708 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2709 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 2710 hr_dev->caps.mtt_ba_pg_sz); 2711 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2712 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 2713 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 2714 2715 roce_set_field(context->byte_16_buf_ba_pg_sz, 2716 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2717 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 2718 hr_dev->caps.mtt_buf_pg_sz); 2719 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 2720 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 2721 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 2722 2723 roce_set_field(context->byte_80_rnr_rx_cqn, 2724 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2725 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer); 2726 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 2727 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 2728 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 2729 2730 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2731 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size] 2732 >> PAGE_ADDR_SHIFT); 2733 qpc_mask->rq_cur_blk_addr = 0; 2734 2735 roce_set_field(context->byte_92_srq_info, 2736 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2737 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 2738 mtts[hr_qp->rq.offset / page_size] 2739 >> (32 + PAGE_ADDR_SHIFT)); 2740 roce_set_field(qpc_mask->byte_92_srq_info, 2741 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 2742 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 2743 2744 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1] 2745 >> PAGE_ADDR_SHIFT); 2746 qpc_mask->rq_nxt_blk_addr = 0; 2747 2748 roce_set_field(context->byte_104_rq_sge, 2749 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2750 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 2751 mtts[hr_qp->rq.offset / page_size + 1] 2752 >> (32 + PAGE_ADDR_SHIFT)); 2753 roce_set_field(qpc_mask->byte_104_rq_sge, 2754 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 2755 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 2756 2757 roce_set_field(context->byte_108_rx_reqepsn, 2758 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2759 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 2760 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2761 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 2762 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 2763 2764 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2765 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4); 2766 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 2767 V2_QPC_BYTE_132_TRRL_BA_S, 0); 2768 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4)); 2769 qpc_mask->trrl_ba = 0; 2770 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2771 V2_QPC_BYTE_140_TRRL_BA_S, 2772 (u32)(dma_handle_3 >> (32 + 16 + 4))); 2773 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 2774 V2_QPC_BYTE_140_TRRL_BA_S, 0); 2775 2776 context->irrl_ba = (u32)(dma_handle_2 >> 6); 2777 qpc_mask->irrl_ba = 0; 2778 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2779 V2_QPC_BYTE_208_IRRL_BA_S, 2780 dma_handle_2 >> (32 + 6)); 2781 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 2782 V2_QPC_BYTE_208_IRRL_BA_S, 0); 2783 2784 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 2785 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 2786 2787 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2788 hr_qp->sq_signal_bits); 2789 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 2790 0); 2791 2792 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 2793 2794 smac = (u8 *)hr_dev->dev_addr[port]; 2795 /* when dmac equals smac or loop_idc is 1, it should loopback */ 2796 if (ether_addr_equal_unaligned(dmac, smac) || 2797 hr_dev->loop_idc == 0x1) { 2798 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 2799 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 2800 } 2801 2802 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 2803 attr->max_dest_rd_atomic) { 2804 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2805 V2_QPC_BYTE_140_RR_MAX_S, 2806 fls(attr->max_dest_rd_atomic - 1)); 2807 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 2808 V2_QPC_BYTE_140_RR_MAX_S, 0); 2809 } 2810 2811 if (attr_mask & IB_QP_DEST_QPN) { 2812 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 2813 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 2814 roce_set_field(qpc_mask->byte_56_dqpn_err, 2815 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 2816 } 2817 2818 /* Configure GID index */ 2819 port_num = rdma_ah_get_port_num(&attr->ah_attr); 2820 roce_set_field(context->byte_20_smac_sgid_idx, 2821 V2_QPC_BYTE_20_SGID_IDX_M, 2822 V2_QPC_BYTE_20_SGID_IDX_S, 2823 hns_get_gid_index(hr_dev, port_num - 1, 2824 grh->sgid_index)); 2825 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 2826 V2_QPC_BYTE_20_SGID_IDX_M, 2827 V2_QPC_BYTE_20_SGID_IDX_S, 0); 2828 memcpy(&(context->dmac), dmac, 4); 2829 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2830 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 2831 qpc_mask->dmac = 0; 2832 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 2833 V2_QPC_BYTE_52_DMAC_S, 0); 2834 2835 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2836 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4); 2837 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 2838 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 2839 2840 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2841 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 2842 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 2843 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 2844 2845 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2846 V2_QPC_BYTE_28_FL_S, grh->flow_label); 2847 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 2848 V2_QPC_BYTE_28_FL_S, 0); 2849 2850 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2851 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 2852 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 2853 V2_QPC_BYTE_24_TC_S, 0); 2854 2855 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 2856 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2857 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); 2858 else if (attr_mask & IB_QP_PATH_MTU) 2859 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2860 V2_QPC_BYTE_24_MTU_S, attr->path_mtu); 2861 2862 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 2863 V2_QPC_BYTE_24_MTU_S, 0); 2864 2865 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 2866 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 2867 2868 roce_set_field(context->byte_84_rq_ci_pi, 2869 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2870 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 2871 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2872 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 2873 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 2874 2875 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 2876 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 2877 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 2878 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 2879 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 2880 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 2881 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 2882 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 2883 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 2884 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 2885 2886 context->rq_rnr_timer = 0; 2887 qpc_mask->rq_rnr_timer = 0; 2888 2889 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2890 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 2891 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 2892 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 2893 2894 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 2895 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 2896 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 2897 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 2898 2899 roce_set_field(context->byte_168_irrl_idx, 2900 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2901 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 2902 roce_set_field(qpc_mask->byte_168_irrl_idx, 2903 V2_QPC_BYTE_168_LP_SGEN_INI_M, 2904 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 2905 2906 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2907 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 2908 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 2909 V2_QPC_BYTE_28_SL_S, 0); 2910 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 2911 2912 return 0; 2913 } 2914 2915 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 2916 const struct ib_qp_attr *attr, int attr_mask, 2917 struct hns_roce_v2_qp_context *context, 2918 struct hns_roce_v2_qp_context *qpc_mask) 2919 { 2920 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 2921 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 2922 struct device *dev = hr_dev->dev; 2923 dma_addr_t dma_handle; 2924 u32 page_size; 2925 u64 *mtts; 2926 2927 /* Search qp buf's mtts */ 2928 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 2929 hr_qp->mtt.first_seg, &dma_handle); 2930 if (!mtts) { 2931 dev_err(dev, "qp buf pa find failed\n"); 2932 return -EINVAL; 2933 } 2934 2935 /* Not support alternate path and path migration */ 2936 if ((attr_mask & IB_QP_ALT_PATH) || 2937 (attr_mask & IB_QP_PATH_MIG_STATE)) { 2938 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 2939 return -EINVAL; 2940 } 2941 2942 /* 2943 * In v2 engine, software pass context and context mask to hardware 2944 * when modifying qp. If software need modify some fields in context, 2945 * we should set all bits of the relevant fields in context mask to 2946 * 0 at the same time, else set them to 0x1. 2947 */ 2948 roce_set_field(context->byte_60_qpst_mapid, 2949 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2950 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt); 2951 roce_set_field(qpc_mask->byte_60_qpst_mapid, 2952 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M, 2953 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0); 2954 2955 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2956 roce_set_field(context->byte_168_irrl_idx, 2957 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2958 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 2959 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2960 qpc_mask->sq_cur_blk_addr = 0; 2961 roce_set_field(qpc_mask->byte_168_irrl_idx, 2962 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 2963 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 2964 2965 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT); 2966 context->sq_cur_sge_blk_addr = 2967 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2968 ((u32)(mtts[hr_qp->sge.offset / page_size] 2969 >> PAGE_ADDR_SHIFT)) : 0; 2970 roce_set_field(context->byte_184_irrl_idx, 2971 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2972 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 2973 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ? 2974 (mtts[hr_qp->sge.offset / page_size] >> 2975 (32 + PAGE_ADDR_SHIFT)) : 0); 2976 qpc_mask->sq_cur_sge_blk_addr = 0; 2977 roce_set_field(qpc_mask->byte_184_irrl_idx, 2978 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 2979 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 2980 2981 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT); 2982 roce_set_field(context->byte_232_irrl_sge, 2983 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 2984 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 2985 mtts[0] >> (32 + PAGE_ADDR_SHIFT)); 2986 qpc_mask->rx_sq_cur_blk_addr = 0; 2987 roce_set_field(qpc_mask->byte_232_irrl_sge, 2988 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 2989 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 2990 2991 /* 2992 * Set some fields in context to zero, Because the default values 2993 * of all fields in context are zero, we need not set them to 0 again. 2994 * but we should set the relevant fields of context mask to 0. 2995 */ 2996 roce_set_field(qpc_mask->byte_232_irrl_sge, 2997 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 2998 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 2999 3000 roce_set_field(qpc_mask->byte_240_irrl_tail, 3001 V2_QPC_BYTE_240_RX_ACK_MSN_M, 3002 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 3003 3004 roce_set_field(context->byte_244_rnr_rxack, 3005 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3006 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 3007 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3008 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 3009 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 3010 3011 roce_set_field(qpc_mask->byte_248_ack_psn, 3012 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 3013 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 3014 roce_set_bit(qpc_mask->byte_248_ack_psn, 3015 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 3016 roce_set_field(qpc_mask->byte_248_ack_psn, 3017 V2_QPC_BYTE_248_IRRL_PSN_M, 3018 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 3019 3020 roce_set_field(qpc_mask->byte_240_irrl_tail, 3021 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 3022 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 3023 3024 roce_set_field(context->byte_220_retry_psn_msn, 3025 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3026 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 3027 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3028 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 3029 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 3030 3031 roce_set_field(context->byte_224_retry_msg, 3032 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3033 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16); 3034 roce_set_field(qpc_mask->byte_224_retry_msg, 3035 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 3036 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 3037 3038 roce_set_field(context->byte_224_retry_msg, 3039 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3040 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn); 3041 roce_set_field(qpc_mask->byte_224_retry_msg, 3042 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 3043 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 3044 3045 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 3046 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 3047 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 3048 3049 roce_set_bit(qpc_mask->byte_248_ack_psn, 3050 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 3051 3052 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 3053 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 3054 3055 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3056 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 3057 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M, 3058 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 3059 3060 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3061 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt); 3062 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 3063 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 3064 3065 roce_set_field(context->byte_244_rnr_rxack, 3066 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3067 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 3068 roce_set_field(qpc_mask->byte_244_rnr_rxack, 3069 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 3070 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 3071 3072 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3073 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 3074 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M, 3075 V2_QPC_BYTE_244_RNR_CNT_S, 0); 3076 3077 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3078 V2_QPC_BYTE_212_LSN_S, 0x100); 3079 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 3080 V2_QPC_BYTE_212_LSN_S, 0); 3081 3082 if (attr_mask & IB_QP_TIMEOUT) { 3083 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3084 V2_QPC_BYTE_28_AT_S, attr->timeout); 3085 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M, 3086 V2_QPC_BYTE_28_AT_S, 0); 3087 } 3088 3089 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3090 V2_QPC_BYTE_28_SL_S, 3091 rdma_ah_get_sl(&attr->ah_attr)); 3092 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 3093 V2_QPC_BYTE_28_SL_S, 0); 3094 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 3095 3096 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3097 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 3098 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3099 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 3100 3101 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 3102 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 3103 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3104 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 3105 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M, 3106 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 3107 3108 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 3109 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 3110 V2_QPC_BYTE_208_SR_MAX_S, 3111 fls(attr->max_rd_atomic - 1)); 3112 roce_set_field(qpc_mask->byte_208_irrl, 3113 V2_QPC_BYTE_208_SR_MAX_M, 3114 V2_QPC_BYTE_208_SR_MAX_S, 0); 3115 } 3116 return 0; 3117 } 3118 3119 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 3120 const struct ib_qp_attr *attr, 3121 int attr_mask, enum ib_qp_state cur_state, 3122 enum ib_qp_state new_state) 3123 { 3124 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3125 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3126 struct hns_roce_v2_qp_context *context; 3127 struct hns_roce_v2_qp_context *qpc_mask; 3128 struct device *dev = hr_dev->dev; 3129 int ret = -EINVAL; 3130 3131 context = kzalloc(2 * sizeof(*context), GFP_KERNEL); 3132 if (!context) 3133 return -ENOMEM; 3134 3135 qpc_mask = context + 1; 3136 /* 3137 * In v2 engine, software pass context and context mask to hardware 3138 * when modifying qp. If software need modify some fields in context, 3139 * we should set all bits of the relevant fields in context mask to 3140 * 0 at the same time, else set them to 0x1. 3141 */ 3142 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 3143 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 3144 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 3145 qpc_mask); 3146 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3147 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 3148 qpc_mask); 3149 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 3150 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 3151 qpc_mask); 3152 if (ret) 3153 goto out; 3154 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 3155 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 3156 qpc_mask); 3157 if (ret) 3158 goto out; 3159 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) || 3160 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) || 3161 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) || 3162 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) || 3163 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) || 3164 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) || 3165 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) || 3166 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) || 3167 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) || 3168 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) || 3169 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) || 3170 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) || 3171 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) || 3172 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) || 3173 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) { 3174 /* Nothing */ 3175 ; 3176 } else { 3177 dev_err(dev, "Illegal state for QP!\n"); 3178 goto out; 3179 } 3180 3181 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 3182 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 3183 3184 /* Every status migrate must change state */ 3185 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3186 V2_QPC_BYTE_60_QP_ST_S, new_state); 3187 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M, 3188 V2_QPC_BYTE_60_QP_ST_S, 0); 3189 3190 /* SW pass context to HW */ 3191 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state, 3192 context, hr_qp); 3193 if (ret) { 3194 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret); 3195 goto out; 3196 } 3197 3198 hr_qp->state = new_state; 3199 3200 if (attr_mask & IB_QP_ACCESS_FLAGS) 3201 hr_qp->atomic_rd_en = attr->qp_access_flags; 3202 3203 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 3204 hr_qp->resp_depth = attr->max_dest_rd_atomic; 3205 if (attr_mask & IB_QP_PORT) { 3206 hr_qp->port = attr->port_num - 1; 3207 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 3208 } 3209 3210 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 3211 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 3212 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 3213 if (ibqp->send_cq != ibqp->recv_cq) 3214 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 3215 hr_qp->qpn, NULL); 3216 3217 hr_qp->rq.head = 0; 3218 hr_qp->rq.tail = 0; 3219 hr_qp->sq.head = 0; 3220 hr_qp->sq.tail = 0; 3221 hr_qp->sq_next_wqe = 0; 3222 hr_qp->next_sge = 0; 3223 if (hr_qp->rq.wqe_cnt) 3224 *hr_qp->rdb.db_record = 0; 3225 } 3226 3227 out: 3228 kfree(context); 3229 return ret; 3230 } 3231 3232 static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state) 3233 { 3234 switch (state) { 3235 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET; 3236 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT; 3237 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR; 3238 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS; 3239 case HNS_ROCE_QP_ST_SQ_DRAINING: 3240 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD; 3241 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE; 3242 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR; 3243 default: return -1; 3244 } 3245 } 3246 3247 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 3248 struct hns_roce_qp *hr_qp, 3249 struct hns_roce_v2_qp_context *hr_context) 3250 { 3251 struct hns_roce_cmd_mailbox *mailbox; 3252 int ret; 3253 3254 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3255 if (IS_ERR(mailbox)) 3256 return PTR_ERR(mailbox); 3257 3258 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 3259 HNS_ROCE_CMD_QUERY_QPC, 3260 HNS_ROCE_CMD_TIMEOUT_MSECS); 3261 if (ret) { 3262 dev_err(hr_dev->dev, "QUERY QP cmd process error\n"); 3263 goto out; 3264 } 3265 3266 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 3267 3268 out: 3269 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3270 return ret; 3271 } 3272 3273 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3274 int qp_attr_mask, 3275 struct ib_qp_init_attr *qp_init_attr) 3276 { 3277 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3278 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3279 struct hns_roce_v2_qp_context *context; 3280 struct device *dev = hr_dev->dev; 3281 int tmp_qp_state; 3282 int state; 3283 int ret; 3284 3285 context = kzalloc(sizeof(*context), GFP_KERNEL); 3286 if (!context) 3287 return -ENOMEM; 3288 3289 memset(qp_attr, 0, sizeof(*qp_attr)); 3290 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 3291 3292 mutex_lock(&hr_qp->mutex); 3293 3294 if (hr_qp->state == IB_QPS_RESET) { 3295 qp_attr->qp_state = IB_QPS_RESET; 3296 ret = 0; 3297 goto done; 3298 } 3299 3300 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context); 3301 if (ret) { 3302 dev_err(dev, "query qpc error\n"); 3303 ret = -EINVAL; 3304 goto out; 3305 } 3306 3307 state = roce_get_field(context->byte_60_qpst_mapid, 3308 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 3309 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 3310 if (tmp_qp_state == -1) { 3311 dev_err(dev, "Illegal ib_qp_state\n"); 3312 ret = -EINVAL; 3313 goto out; 3314 } 3315 hr_qp->state = (u8)tmp_qp_state; 3316 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 3317 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc, 3318 V2_QPC_BYTE_24_MTU_M, 3319 V2_QPC_BYTE_24_MTU_S); 3320 qp_attr->path_mig_state = IB_MIG_ARMED; 3321 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 3322 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 3323 qp_attr->qkey = V2_QKEY_VAL; 3324 3325 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn, 3326 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 3327 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 3328 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn, 3329 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 3330 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 3331 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err, 3332 V2_QPC_BYTE_56_DQPN_M, 3333 V2_QPC_BYTE_56_DQPN_S); 3334 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en, 3335 V2_QPC_BYTE_76_RRE_S)) << 2) | 3336 ((roce_get_bit(context->byte_76_srqn_op_en, 3337 V2_QPC_BYTE_76_RWE_S)) << 1) | 3338 ((roce_get_bit(context->byte_76_srqn_op_en, 3339 V2_QPC_BYTE_76_ATE_S)) << 3); 3340 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 3341 hr_qp->ibqp.qp_type == IB_QPT_UC) { 3342 struct ib_global_route *grh = 3343 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 3344 3345 rdma_ah_set_sl(&qp_attr->ah_attr, 3346 roce_get_field(context->byte_28_at_fl, 3347 V2_QPC_BYTE_28_SL_M, 3348 V2_QPC_BYTE_28_SL_S)); 3349 grh->flow_label = roce_get_field(context->byte_28_at_fl, 3350 V2_QPC_BYTE_28_FL_M, 3351 V2_QPC_BYTE_28_FL_S); 3352 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx, 3353 V2_QPC_BYTE_20_SGID_IDX_M, 3354 V2_QPC_BYTE_20_SGID_IDX_S); 3355 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc, 3356 V2_QPC_BYTE_24_HOP_LIMIT_M, 3357 V2_QPC_BYTE_24_HOP_LIMIT_S); 3358 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc, 3359 V2_QPC_BYTE_24_TC_M, 3360 V2_QPC_BYTE_24_TC_S); 3361 3362 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw)); 3363 } 3364 3365 qp_attr->port_num = hr_qp->port + 1; 3366 qp_attr->sq_draining = 0; 3367 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl, 3368 V2_QPC_BYTE_208_SR_MAX_M, 3369 V2_QPC_BYTE_208_SR_MAX_S); 3370 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq, 3371 V2_QPC_BYTE_140_RR_MAX_M, 3372 V2_QPC_BYTE_140_RR_MAX_S); 3373 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn, 3374 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 3375 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 3376 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl, 3377 V2_QPC_BYTE_28_AT_M, 3378 V2_QPC_BYTE_28_AT_S); 3379 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn, 3380 V2_QPC_BYTE_212_RETRY_CNT_M, 3381 V2_QPC_BYTE_212_RETRY_CNT_S); 3382 qp_attr->rnr_retry = context->rq_rnr_timer; 3383 3384 done: 3385 qp_attr->cur_qp_state = qp_attr->qp_state; 3386 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 3387 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 3388 3389 if (!ibqp->uobject) { 3390 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 3391 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 3392 } else { 3393 qp_attr->cap.max_send_wr = 0; 3394 qp_attr->cap.max_send_sge = 0; 3395 } 3396 3397 qp_init_attr->cap = qp_attr->cap; 3398 3399 out: 3400 mutex_unlock(&hr_qp->mutex); 3401 kfree(context); 3402 return ret; 3403 } 3404 3405 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 3406 struct hns_roce_qp *hr_qp, 3407 int is_user) 3408 { 3409 struct hns_roce_cq *send_cq, *recv_cq; 3410 struct device *dev = hr_dev->dev; 3411 int ret; 3412 3413 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 3414 /* Modify qp to reset before destroying qp */ 3415 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 3416 hr_qp->state, IB_QPS_RESET); 3417 if (ret) { 3418 dev_err(dev, "modify QP %06lx to ERR failed.\n", 3419 hr_qp->qpn); 3420 return ret; 3421 } 3422 } 3423 3424 send_cq = to_hr_cq(hr_qp->ibqp.send_cq); 3425 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq); 3426 3427 hns_roce_lock_cqs(send_cq, recv_cq); 3428 3429 if (!is_user) { 3430 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ? 3431 to_hr_srq(hr_qp->ibqp.srq) : NULL); 3432 if (send_cq != recv_cq) 3433 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 3434 } 3435 3436 hns_roce_qp_remove(hr_dev, hr_qp); 3437 3438 hns_roce_unlock_cqs(send_cq, recv_cq); 3439 3440 hns_roce_qp_free(hr_dev, hr_qp); 3441 3442 /* Not special_QP, free their QPN */ 3443 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) || 3444 (hr_qp->ibqp.qp_type == IB_QPT_UC) || 3445 (hr_qp->ibqp.qp_type == IB_QPT_UD)) 3446 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1); 3447 3448 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 3449 3450 if (is_user) { 3451 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1)) 3452 hns_roce_db_unmap_user( 3453 to_hr_ucontext(hr_qp->ibqp.uobject->context), 3454 &hr_qp->rdb); 3455 ib_umem_release(hr_qp->umem); 3456 } else { 3457 kfree(hr_qp->sq.wrid); 3458 kfree(hr_qp->rq.wrid); 3459 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 3460 if (hr_qp->rq.wqe_cnt) 3461 hns_roce_free_db(hr_dev, &hr_qp->rdb); 3462 } 3463 3464 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 3465 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list); 3466 kfree(hr_qp->rq_inl_buf.wqe_list); 3467 } 3468 3469 return 0; 3470 } 3471 3472 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp) 3473 { 3474 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3475 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3476 int ret; 3477 3478 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject); 3479 if (ret) { 3480 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret); 3481 return ret; 3482 } 3483 3484 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 3485 kfree(hr_to_hr_sqp(hr_qp)); 3486 else 3487 kfree(hr_qp); 3488 3489 return 0; 3490 } 3491 3492 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 3493 { 3494 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 3495 struct hns_roce_v2_cq_context *cq_context; 3496 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 3497 struct hns_roce_v2_cq_context *cqc_mask; 3498 struct hns_roce_cmd_mailbox *mailbox; 3499 int ret; 3500 3501 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3502 if (IS_ERR(mailbox)) 3503 return PTR_ERR(mailbox); 3504 3505 cq_context = mailbox->buf; 3506 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 3507 3508 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 3509 3510 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3511 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3512 cq_count); 3513 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3514 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 3515 0); 3516 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 3517 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3518 cq_period); 3519 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 3520 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 3521 0); 3522 3523 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 3524 HNS_ROCE_CMD_MODIFY_CQC, 3525 HNS_ROCE_CMD_TIMEOUT_MSECS); 3526 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3527 if (ret) 3528 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n"); 3529 3530 return ret; 3531 } 3532 3533 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 3534 { 3535 u32 doorbell[2]; 3536 3537 doorbell[0] = 0; 3538 doorbell[1] = 0; 3539 3540 if (eq->type_flag == HNS_ROCE_AEQ) { 3541 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3542 HNS_ROCE_V2_EQ_DB_CMD_S, 3543 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3544 HNS_ROCE_EQ_DB_CMD_AEQ : 3545 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 3546 } else { 3547 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 3548 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 3549 3550 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 3551 HNS_ROCE_V2_EQ_DB_CMD_S, 3552 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 3553 HNS_ROCE_EQ_DB_CMD_CEQ : 3554 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 3555 } 3556 3557 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 3558 HNS_ROCE_V2_EQ_DB_PARA_S, 3559 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 3560 3561 hns_roce_write64_k(doorbell, eq->doorbell); 3562 } 3563 3564 static void hns_roce_v2_wq_catas_err_handle(struct hns_roce_dev *hr_dev, 3565 struct hns_roce_aeqe *aeqe, 3566 u32 qpn) 3567 { 3568 struct device *dev = hr_dev->dev; 3569 int sub_type; 3570 3571 dev_warn(dev, "Local work queue catastrophic error.\n"); 3572 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3573 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3574 switch (sub_type) { 3575 case HNS_ROCE_LWQCE_QPC_ERROR: 3576 dev_warn(dev, "QP %d, QPC error.\n", qpn); 3577 break; 3578 case HNS_ROCE_LWQCE_MTU_ERROR: 3579 dev_warn(dev, "QP %d, MTU error.\n", qpn); 3580 break; 3581 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR: 3582 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn); 3583 break; 3584 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR: 3585 dev_warn(dev, "QP %d, WQE addr error.\n", qpn); 3586 break; 3587 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR: 3588 dev_warn(dev, "QP %d, WQE shift error.\n", qpn); 3589 break; 3590 default: 3591 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3592 break; 3593 } 3594 } 3595 3596 static void hns_roce_v2_local_wq_access_err_handle(struct hns_roce_dev *hr_dev, 3597 struct hns_roce_aeqe *aeqe, u32 qpn) 3598 { 3599 struct device *dev = hr_dev->dev; 3600 int sub_type; 3601 3602 dev_warn(dev, "Local access violation work queue error.\n"); 3603 sub_type = roce_get_field(aeqe->asyn, HNS_ROCE_V2_AEQE_SUB_TYPE_M, 3604 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 3605 switch (sub_type) { 3606 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION: 3607 dev_warn(dev, "QP %d, R_key violation.\n", qpn); 3608 break; 3609 case HNS_ROCE_LAVWQE_LENGTH_ERROR: 3610 dev_warn(dev, "QP %d, length error.\n", qpn); 3611 break; 3612 case HNS_ROCE_LAVWQE_VA_ERROR: 3613 dev_warn(dev, "QP %d, VA error.\n", qpn); 3614 break; 3615 case HNS_ROCE_LAVWQE_PD_ERROR: 3616 dev_err(dev, "QP %d, PD error.\n", qpn); 3617 break; 3618 case HNS_ROCE_LAVWQE_RW_ACC_ERROR: 3619 dev_warn(dev, "QP %d, rw acc error.\n", qpn); 3620 break; 3621 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR: 3622 dev_warn(dev, "QP %d, key state error.\n", qpn); 3623 break; 3624 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR: 3625 dev_warn(dev, "QP %d, MR operation error.\n", qpn); 3626 break; 3627 default: 3628 dev_err(dev, "Unhandled sub_event type %d.\n", sub_type); 3629 break; 3630 } 3631 } 3632 3633 static void hns_roce_v2_qp_err_handle(struct hns_roce_dev *hr_dev, 3634 struct hns_roce_aeqe *aeqe, 3635 int event_type) 3636 { 3637 struct device *dev = hr_dev->dev; 3638 u32 qpn; 3639 3640 qpn = roce_get_field(aeqe->event.qp_event.qp, 3641 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3642 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3643 3644 switch (event_type) { 3645 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3646 dev_warn(dev, "Communication established.\n"); 3647 break; 3648 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3649 dev_warn(dev, "Send queue drained.\n"); 3650 break; 3651 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3652 hns_roce_v2_wq_catas_err_handle(hr_dev, aeqe, qpn); 3653 break; 3654 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3655 dev_warn(dev, "Invalid request local work queue error.\n"); 3656 break; 3657 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3658 hns_roce_v2_local_wq_access_err_handle(hr_dev, aeqe, qpn); 3659 break; 3660 default: 3661 break; 3662 } 3663 3664 hns_roce_qp_event(hr_dev, qpn, event_type); 3665 } 3666 3667 static void hns_roce_v2_cq_err_handle(struct hns_roce_dev *hr_dev, 3668 struct hns_roce_aeqe *aeqe, 3669 int event_type) 3670 { 3671 struct device *dev = hr_dev->dev; 3672 u32 cqn; 3673 3674 cqn = roce_get_field(aeqe->event.cq_event.cq, 3675 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 3676 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 3677 3678 switch (event_type) { 3679 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3680 dev_warn(dev, "CQ 0x%x access err.\n", cqn); 3681 break; 3682 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3683 dev_warn(dev, "CQ 0x%x overflow\n", cqn); 3684 break; 3685 default: 3686 break; 3687 } 3688 3689 hns_roce_cq_event(hr_dev, cqn, event_type); 3690 } 3691 3692 static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry) 3693 { 3694 u32 buf_chk_sz; 3695 unsigned long off; 3696 3697 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3698 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3699 3700 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) + 3701 off % buf_chk_sz); 3702 } 3703 3704 static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry) 3705 { 3706 u32 buf_chk_sz; 3707 unsigned long off; 3708 3709 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3710 3711 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE; 3712 3713 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3714 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) + 3715 off % buf_chk_sz); 3716 else 3717 return (struct hns_roce_aeqe *)((u8 *) 3718 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz); 3719 } 3720 3721 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 3722 { 3723 struct hns_roce_aeqe *aeqe; 3724 3725 if (!eq->hop_num) 3726 aeqe = get_aeqe_v2(eq, eq->cons_index); 3727 else 3728 aeqe = mhop_get_aeqe(eq, eq->cons_index); 3729 3730 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 3731 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 3732 } 3733 3734 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 3735 struct hns_roce_eq *eq) 3736 { 3737 struct device *dev = hr_dev->dev; 3738 struct hns_roce_aeqe *aeqe; 3739 int aeqe_found = 0; 3740 int event_type; 3741 3742 while ((aeqe = next_aeqe_sw_v2(eq))) { 3743 3744 /* Make sure we read AEQ entry after we have checked the 3745 * ownership bit 3746 */ 3747 dma_rmb(); 3748 3749 event_type = roce_get_field(aeqe->asyn, 3750 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 3751 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 3752 3753 switch (event_type) { 3754 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 3755 dev_warn(dev, "Path migrated succeeded.\n"); 3756 break; 3757 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 3758 dev_warn(dev, "Path migration failed.\n"); 3759 break; 3760 case HNS_ROCE_EVENT_TYPE_COMM_EST: 3761 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 3762 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 3763 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 3764 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 3765 hns_roce_v2_qp_err_handle(hr_dev, aeqe, event_type); 3766 break; 3767 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 3768 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 3769 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 3770 dev_warn(dev, "SRQ not support.\n"); 3771 break; 3772 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 3773 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 3774 hns_roce_v2_cq_err_handle(hr_dev, aeqe, event_type); 3775 break; 3776 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 3777 dev_warn(dev, "DB overflow.\n"); 3778 break; 3779 case HNS_ROCE_EVENT_TYPE_MB: 3780 hns_roce_cmd_event(hr_dev, 3781 le16_to_cpu(aeqe->event.cmd.token), 3782 aeqe->event.cmd.status, 3783 le64_to_cpu(aeqe->event.cmd.out_param)); 3784 break; 3785 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 3786 dev_warn(dev, "CEQ overflow.\n"); 3787 break; 3788 case HNS_ROCE_EVENT_TYPE_FLR: 3789 dev_warn(dev, "Function level reset.\n"); 3790 break; 3791 default: 3792 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 3793 event_type, eq->eqn, eq->cons_index); 3794 break; 3795 }; 3796 3797 ++eq->cons_index; 3798 aeqe_found = 1; 3799 3800 if (eq->cons_index > (2 * eq->entries - 1)) { 3801 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3802 eq->cons_index = 0; 3803 } 3804 } 3805 3806 set_eq_cons_index_v2(eq); 3807 return aeqe_found; 3808 } 3809 3810 static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry) 3811 { 3812 u32 buf_chk_sz; 3813 unsigned long off; 3814 3815 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3816 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3817 3818 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) + 3819 off % buf_chk_sz); 3820 } 3821 3822 static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry) 3823 { 3824 u32 buf_chk_sz; 3825 unsigned long off; 3826 3827 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 3828 3829 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE; 3830 3831 if (eq->hop_num == HNS_ROCE_HOP_NUM_0) 3832 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) + 3833 off % buf_chk_sz); 3834 else 3835 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off / 3836 buf_chk_sz]) + off % buf_chk_sz); 3837 } 3838 3839 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 3840 { 3841 struct hns_roce_ceqe *ceqe; 3842 3843 if (!eq->hop_num) 3844 ceqe = get_ceqe_v2(eq, eq->cons_index); 3845 else 3846 ceqe = mhop_get_ceqe(eq, eq->cons_index); 3847 3848 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 3849 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 3850 } 3851 3852 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 3853 struct hns_roce_eq *eq) 3854 { 3855 struct device *dev = hr_dev->dev; 3856 struct hns_roce_ceqe *ceqe; 3857 int ceqe_found = 0; 3858 u32 cqn; 3859 3860 while ((ceqe = next_ceqe_sw_v2(eq))) { 3861 3862 /* Make sure we read CEQ entry after we have checked the 3863 * ownership bit 3864 */ 3865 dma_rmb(); 3866 3867 cqn = roce_get_field(ceqe->comp, 3868 HNS_ROCE_V2_CEQE_COMP_CQN_M, 3869 HNS_ROCE_V2_CEQE_COMP_CQN_S); 3870 3871 hns_roce_cq_completion(hr_dev, cqn); 3872 3873 ++eq->cons_index; 3874 ceqe_found = 1; 3875 3876 if (eq->cons_index > (2 * eq->entries - 1)) { 3877 dev_warn(dev, "cons_index overflow, set back to 0.\n"); 3878 eq->cons_index = 0; 3879 } 3880 } 3881 3882 set_eq_cons_index_v2(eq); 3883 3884 return ceqe_found; 3885 } 3886 3887 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 3888 { 3889 struct hns_roce_eq *eq = eq_ptr; 3890 struct hns_roce_dev *hr_dev = eq->hr_dev; 3891 int int_work = 0; 3892 3893 if (eq->type_flag == HNS_ROCE_CEQ) 3894 /* Completion event interrupt */ 3895 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 3896 else 3897 /* Asychronous event interrupt */ 3898 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 3899 3900 return IRQ_RETVAL(int_work); 3901 } 3902 3903 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 3904 { 3905 struct hns_roce_dev *hr_dev = dev_id; 3906 struct device *dev = hr_dev->dev; 3907 int int_work = 0; 3908 u32 int_st; 3909 u32 int_en; 3910 3911 /* Abnormal interrupt */ 3912 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 3913 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 3914 3915 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 3916 dev_err(dev, "AEQ overflow!\n"); 3917 3918 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1); 3919 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3920 3921 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3922 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3923 3924 int_work = 1; 3925 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 3926 dev_err(dev, "BUS ERR!\n"); 3927 3928 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1); 3929 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3930 3931 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3932 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3933 3934 int_work = 1; 3935 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 3936 dev_err(dev, "OTHER ERR!\n"); 3937 3938 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1); 3939 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 3940 3941 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1); 3942 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 3943 3944 int_work = 1; 3945 } else 3946 dev_err(dev, "There is no abnormal irq found!\n"); 3947 3948 return IRQ_RETVAL(int_work); 3949 } 3950 3951 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 3952 int eq_num, int enable_flag) 3953 { 3954 int i; 3955 3956 if (enable_flag == EQ_ENABLE) { 3957 for (i = 0; i < eq_num; i++) 3958 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3959 i * EQ_REG_OFFSET, 3960 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 3961 3962 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3963 HNS_ROCE_V2_VF_ABN_INT_EN_M); 3964 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3965 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 3966 } else { 3967 for (i = 0; i < eq_num; i++) 3968 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 3969 i * EQ_REG_OFFSET, 3970 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 3971 3972 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 3973 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 3974 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 3975 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 3976 } 3977 } 3978 3979 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 3980 { 3981 struct device *dev = hr_dev->dev; 3982 int ret; 3983 3984 if (eqn < hr_dev->caps.num_comp_vectors) 3985 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 3986 0, HNS_ROCE_CMD_DESTROY_CEQC, 3987 HNS_ROCE_CMD_TIMEOUT_MSECS); 3988 else 3989 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 3990 0, HNS_ROCE_CMD_DESTROY_AEQC, 3991 HNS_ROCE_CMD_TIMEOUT_MSECS); 3992 if (ret) 3993 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 3994 } 3995 3996 static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev, 3997 struct hns_roce_eq *eq) 3998 { 3999 struct device *dev = hr_dev->dev; 4000 u64 idx; 4001 u64 size; 4002 u32 buf_chk_sz; 4003 u32 bt_chk_sz; 4004 u32 mhop_num; 4005 int eqe_alloc; 4006 int ba_num; 4007 int i = 0; 4008 int j = 0; 4009 4010 mhop_num = hr_dev->caps.eqe_hop_num; 4011 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4012 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4013 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) / 4014 buf_chk_sz; 4015 4016 /* hop_num = 0 */ 4017 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4018 dma_free_coherent(dev, (unsigned int)(eq->entries * 4019 eq->eqe_size), eq->bt_l0, eq->l0_dma); 4020 return; 4021 } 4022 4023 /* hop_num = 1 or hop = 2 */ 4024 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4025 if (mhop_num == 1) { 4026 for (i = 0; i < eq->l0_last_num; i++) { 4027 if (i == eq->l0_last_num - 1) { 4028 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4029 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4030 dma_free_coherent(dev, size, eq->buf[i], 4031 eq->buf_dma[i]); 4032 break; 4033 } 4034 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4035 eq->buf_dma[i]); 4036 } 4037 } else if (mhop_num == 2) { 4038 for (i = 0; i < eq->l0_last_num; i++) { 4039 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4040 eq->l1_dma[i]); 4041 4042 for (j = 0; j < bt_chk_sz / 8; j++) { 4043 idx = i * (bt_chk_sz / 8) + j; 4044 if ((i == eq->l0_last_num - 1) 4045 && j == eq->l1_last_num - 1) { 4046 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4047 * idx; 4048 size = (eq->entries - eqe_alloc) 4049 * eq->eqe_size; 4050 dma_free_coherent(dev, size, 4051 eq->buf[idx], 4052 eq->buf_dma[idx]); 4053 break; 4054 } 4055 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4056 eq->buf_dma[idx]); 4057 } 4058 } 4059 } 4060 kfree(eq->buf_dma); 4061 kfree(eq->buf); 4062 kfree(eq->l1_dma); 4063 kfree(eq->bt_l1); 4064 eq->buf_dma = NULL; 4065 eq->buf = NULL; 4066 eq->l1_dma = NULL; 4067 eq->bt_l1 = NULL; 4068 } 4069 4070 static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev, 4071 struct hns_roce_eq *eq) 4072 { 4073 u32 buf_chk_sz; 4074 4075 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT); 4076 4077 if (hr_dev->caps.eqe_hop_num) { 4078 hns_roce_mhop_free_eq(hr_dev, eq); 4079 return; 4080 } 4081 4082 if (eq->buf_list) 4083 dma_free_coherent(hr_dev->dev, buf_chk_sz, 4084 eq->buf_list->buf, eq->buf_list->map); 4085 } 4086 4087 static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev, 4088 struct hns_roce_eq *eq, 4089 void *mb_buf) 4090 { 4091 struct hns_roce_eq_context *eqc; 4092 4093 eqc = mb_buf; 4094 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 4095 4096 /* init eqc */ 4097 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 4098 eq->hop_num = hr_dev->caps.eqe_hop_num; 4099 eq->cons_index = 0; 4100 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 4101 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 4102 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 4103 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz; 4104 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz; 4105 eq->shift = ilog2((unsigned int)eq->entries); 4106 4107 if (!eq->hop_num) 4108 eq->eqe_ba = eq->buf_list->map; 4109 else 4110 eq->eqe_ba = eq->l0_dma; 4111 4112 /* set eqc state */ 4113 roce_set_field(eqc->byte_4, 4114 HNS_ROCE_EQC_EQ_ST_M, 4115 HNS_ROCE_EQC_EQ_ST_S, 4116 HNS_ROCE_V2_EQ_STATE_VALID); 4117 4118 /* set eqe hop num */ 4119 roce_set_field(eqc->byte_4, 4120 HNS_ROCE_EQC_HOP_NUM_M, 4121 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 4122 4123 /* set eqc over_ignore */ 4124 roce_set_field(eqc->byte_4, 4125 HNS_ROCE_EQC_OVER_IGNORE_M, 4126 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 4127 4128 /* set eqc coalesce */ 4129 roce_set_field(eqc->byte_4, 4130 HNS_ROCE_EQC_COALESCE_M, 4131 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 4132 4133 /* set eqc arm_state */ 4134 roce_set_field(eqc->byte_4, 4135 HNS_ROCE_EQC_ARM_ST_M, 4136 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 4137 4138 /* set eqn */ 4139 roce_set_field(eqc->byte_4, 4140 HNS_ROCE_EQC_EQN_M, 4141 HNS_ROCE_EQC_EQN_S, eq->eqn); 4142 4143 /* set eqe_cnt */ 4144 roce_set_field(eqc->byte_4, 4145 HNS_ROCE_EQC_EQE_CNT_M, 4146 HNS_ROCE_EQC_EQE_CNT_S, 4147 HNS_ROCE_EQ_INIT_EQE_CNT); 4148 4149 /* set eqe_ba_pg_sz */ 4150 roce_set_field(eqc->byte_8, 4151 HNS_ROCE_EQC_BA_PG_SZ_M, 4152 HNS_ROCE_EQC_BA_PG_SZ_S, eq->eqe_ba_pg_sz); 4153 4154 /* set eqe_buf_pg_sz */ 4155 roce_set_field(eqc->byte_8, 4156 HNS_ROCE_EQC_BUF_PG_SZ_M, 4157 HNS_ROCE_EQC_BUF_PG_SZ_S, eq->eqe_buf_pg_sz); 4158 4159 /* set eq_producer_idx */ 4160 roce_set_field(eqc->byte_8, 4161 HNS_ROCE_EQC_PROD_INDX_M, 4162 HNS_ROCE_EQC_PROD_INDX_S, 4163 HNS_ROCE_EQ_INIT_PROD_IDX); 4164 4165 /* set eq_max_cnt */ 4166 roce_set_field(eqc->byte_12, 4167 HNS_ROCE_EQC_MAX_CNT_M, 4168 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 4169 4170 /* set eq_period */ 4171 roce_set_field(eqc->byte_12, 4172 HNS_ROCE_EQC_PERIOD_M, 4173 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 4174 4175 /* set eqe_report_timer */ 4176 roce_set_field(eqc->eqe_report_timer, 4177 HNS_ROCE_EQC_REPORT_TIMER_M, 4178 HNS_ROCE_EQC_REPORT_TIMER_S, 4179 HNS_ROCE_EQ_INIT_REPORT_TIMER); 4180 4181 /* set eqe_ba [34:3] */ 4182 roce_set_field(eqc->eqe_ba0, 4183 HNS_ROCE_EQC_EQE_BA_L_M, 4184 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3); 4185 4186 /* set eqe_ba [64:35] */ 4187 roce_set_field(eqc->eqe_ba1, 4188 HNS_ROCE_EQC_EQE_BA_H_M, 4189 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35); 4190 4191 /* set eq shift */ 4192 roce_set_field(eqc->byte_28, 4193 HNS_ROCE_EQC_SHIFT_M, 4194 HNS_ROCE_EQC_SHIFT_S, eq->shift); 4195 4196 /* set eq MSI_IDX */ 4197 roce_set_field(eqc->byte_28, 4198 HNS_ROCE_EQC_MSI_INDX_M, 4199 HNS_ROCE_EQC_MSI_INDX_S, 4200 HNS_ROCE_EQ_INIT_MSI_IDX); 4201 4202 /* set cur_eqe_ba [27:12] */ 4203 roce_set_field(eqc->byte_28, 4204 HNS_ROCE_EQC_CUR_EQE_BA_L_M, 4205 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12); 4206 4207 /* set cur_eqe_ba [59:28] */ 4208 roce_set_field(eqc->byte_32, 4209 HNS_ROCE_EQC_CUR_EQE_BA_M_M, 4210 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28); 4211 4212 /* set cur_eqe_ba [63:60] */ 4213 roce_set_field(eqc->byte_36, 4214 HNS_ROCE_EQC_CUR_EQE_BA_H_M, 4215 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60); 4216 4217 /* set eq consumer idx */ 4218 roce_set_field(eqc->byte_36, 4219 HNS_ROCE_EQC_CONS_INDX_M, 4220 HNS_ROCE_EQC_CONS_INDX_S, 4221 HNS_ROCE_EQ_INIT_CONS_IDX); 4222 4223 /* set nex_eqe_ba[43:12] */ 4224 roce_set_field(eqc->nxt_eqe_ba0, 4225 HNS_ROCE_EQC_NXT_EQE_BA_L_M, 4226 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12); 4227 4228 /* set nex_eqe_ba[63:44] */ 4229 roce_set_field(eqc->nxt_eqe_ba1, 4230 HNS_ROCE_EQC_NXT_EQE_BA_H_M, 4231 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44); 4232 } 4233 4234 static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev, 4235 struct hns_roce_eq *eq) 4236 { 4237 struct device *dev = hr_dev->dev; 4238 int eq_alloc_done = 0; 4239 int eq_buf_cnt = 0; 4240 int eqe_alloc; 4241 u32 buf_chk_sz; 4242 u32 bt_chk_sz; 4243 u32 mhop_num; 4244 u64 size; 4245 u64 idx; 4246 int ba_num; 4247 int bt_num; 4248 int record_i; 4249 int record_j; 4250 int i = 0; 4251 int j = 0; 4252 4253 mhop_num = hr_dev->caps.eqe_hop_num; 4254 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4255 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT); 4256 4257 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1) 4258 / buf_chk_sz; 4259 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8); 4260 4261 /* hop_num = 0 */ 4262 if (mhop_num == HNS_ROCE_HOP_NUM_0) { 4263 if (eq->entries > buf_chk_sz / eq->eqe_size) { 4264 dev_err(dev, "eq entries %d is larger than buf_pg_sz!", 4265 eq->entries); 4266 return -EINVAL; 4267 } 4268 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size, 4269 &(eq->l0_dma), GFP_KERNEL); 4270 if (!eq->bt_l0) 4271 return -ENOMEM; 4272 4273 eq->cur_eqe_ba = eq->l0_dma; 4274 eq->nxt_eqe_ba = 0; 4275 4276 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size); 4277 4278 return 0; 4279 } 4280 4281 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL); 4282 if (!eq->buf_dma) 4283 return -ENOMEM; 4284 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL); 4285 if (!eq->buf) 4286 goto err_kcalloc_buf; 4287 4288 if (mhop_num == 2) { 4289 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL); 4290 if (!eq->l1_dma) 4291 goto err_kcalloc_l1_dma; 4292 4293 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL); 4294 if (!eq->bt_l1) 4295 goto err_kcalloc_bt_l1; 4296 } 4297 4298 /* alloc L0 BT */ 4299 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL); 4300 if (!eq->bt_l0) 4301 goto err_dma_alloc_l0; 4302 4303 if (mhop_num == 1) { 4304 if (ba_num > (bt_chk_sz / 8)) 4305 dev_err(dev, "ba_num %d is too large for 1 hop\n", 4306 ba_num); 4307 4308 /* alloc buf */ 4309 for (i = 0; i < bt_chk_sz / 8; i++) { 4310 if (eq_buf_cnt + 1 < ba_num) { 4311 size = buf_chk_sz; 4312 } else { 4313 eqe_alloc = i * (buf_chk_sz / eq->eqe_size); 4314 size = (eq->entries - eqe_alloc) * eq->eqe_size; 4315 } 4316 eq->buf[i] = dma_alloc_coherent(dev, size, 4317 &(eq->buf_dma[i]), 4318 GFP_KERNEL); 4319 if (!eq->buf[i]) 4320 goto err_dma_alloc_buf; 4321 4322 memset(eq->buf[i], 0, size); 4323 *(eq->bt_l0 + i) = eq->buf_dma[i]; 4324 4325 eq_buf_cnt++; 4326 if (eq_buf_cnt >= ba_num) 4327 break; 4328 } 4329 eq->cur_eqe_ba = eq->buf_dma[0]; 4330 eq->nxt_eqe_ba = eq->buf_dma[1]; 4331 4332 } else if (mhop_num == 2) { 4333 /* alloc L1 BT and buf */ 4334 for (i = 0; i < bt_chk_sz / 8; i++) { 4335 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz, 4336 &(eq->l1_dma[i]), 4337 GFP_KERNEL); 4338 if (!eq->bt_l1[i]) 4339 goto err_dma_alloc_l1; 4340 *(eq->bt_l0 + i) = eq->l1_dma[i]; 4341 4342 for (j = 0; j < bt_chk_sz / 8; j++) { 4343 idx = i * bt_chk_sz / 8 + j; 4344 if (eq_buf_cnt + 1 < ba_num) { 4345 size = buf_chk_sz; 4346 } else { 4347 eqe_alloc = (buf_chk_sz / eq->eqe_size) 4348 * idx; 4349 size = (eq->entries - eqe_alloc) 4350 * eq->eqe_size; 4351 } 4352 eq->buf[idx] = dma_alloc_coherent(dev, size, 4353 &(eq->buf_dma[idx]), 4354 GFP_KERNEL); 4355 if (!eq->buf[idx]) 4356 goto err_dma_alloc_buf; 4357 4358 memset(eq->buf[idx], 0, size); 4359 *(eq->bt_l1[i] + j) = eq->buf_dma[idx]; 4360 4361 eq_buf_cnt++; 4362 if (eq_buf_cnt >= ba_num) { 4363 eq_alloc_done = 1; 4364 break; 4365 } 4366 } 4367 4368 if (eq_alloc_done) 4369 break; 4370 } 4371 eq->cur_eqe_ba = eq->buf_dma[0]; 4372 eq->nxt_eqe_ba = eq->buf_dma[1]; 4373 } 4374 4375 eq->l0_last_num = i + 1; 4376 if (mhop_num == 2) 4377 eq->l1_last_num = j + 1; 4378 4379 return 0; 4380 4381 err_dma_alloc_l1: 4382 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4383 eq->bt_l0 = NULL; 4384 eq->l0_dma = 0; 4385 for (i -= 1; i >= 0; i--) { 4386 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4387 eq->l1_dma[i]); 4388 4389 for (j = 0; j < bt_chk_sz / 8; j++) { 4390 idx = i * bt_chk_sz / 8 + j; 4391 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx], 4392 eq->buf_dma[idx]); 4393 } 4394 } 4395 goto err_dma_alloc_l0; 4396 4397 err_dma_alloc_buf: 4398 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma); 4399 eq->bt_l0 = NULL; 4400 eq->l0_dma = 0; 4401 4402 if (mhop_num == 1) 4403 for (i -= 1; i >= 0; i--) 4404 dma_free_coherent(dev, buf_chk_sz, eq->buf[i], 4405 eq->buf_dma[i]); 4406 else if (mhop_num == 2) { 4407 record_i = i; 4408 record_j = j; 4409 for (; i >= 0; i--) { 4410 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i], 4411 eq->l1_dma[i]); 4412 4413 for (j = 0; j < bt_chk_sz / 8; j++) { 4414 if (i == record_i && j >= record_j) 4415 break; 4416 4417 idx = i * bt_chk_sz / 8 + j; 4418 dma_free_coherent(dev, buf_chk_sz, 4419 eq->buf[idx], 4420 eq->buf_dma[idx]); 4421 } 4422 } 4423 } 4424 4425 err_dma_alloc_l0: 4426 kfree(eq->bt_l1); 4427 eq->bt_l1 = NULL; 4428 4429 err_kcalloc_bt_l1: 4430 kfree(eq->l1_dma); 4431 eq->l1_dma = NULL; 4432 4433 err_kcalloc_l1_dma: 4434 kfree(eq->buf); 4435 eq->buf = NULL; 4436 4437 err_kcalloc_buf: 4438 kfree(eq->buf_dma); 4439 eq->buf_dma = NULL; 4440 4441 return -ENOMEM; 4442 } 4443 4444 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 4445 struct hns_roce_eq *eq, 4446 unsigned int eq_cmd) 4447 { 4448 struct device *dev = hr_dev->dev; 4449 struct hns_roce_cmd_mailbox *mailbox; 4450 u32 buf_chk_sz = 0; 4451 int ret; 4452 4453 /* Allocate mailbox memory */ 4454 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4455 if (IS_ERR(mailbox)) 4456 return PTR_ERR(mailbox); 4457 4458 if (!hr_dev->caps.eqe_hop_num) { 4459 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT); 4460 4461 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list), 4462 GFP_KERNEL); 4463 if (!eq->buf_list) { 4464 ret = -ENOMEM; 4465 goto free_cmd_mbox; 4466 } 4467 4468 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz, 4469 &(eq->buf_list->map), 4470 GFP_KERNEL); 4471 if (!eq->buf_list->buf) { 4472 ret = -ENOMEM; 4473 goto err_alloc_buf; 4474 } 4475 4476 memset(eq->buf_list->buf, 0, buf_chk_sz); 4477 } else { 4478 ret = hns_roce_mhop_alloc_eq(hr_dev, eq); 4479 if (ret) { 4480 ret = -ENOMEM; 4481 goto free_cmd_mbox; 4482 } 4483 } 4484 4485 hns_roce_config_eqc(hr_dev, eq, mailbox->buf); 4486 4487 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 4488 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 4489 if (ret) { 4490 dev_err(dev, "[mailbox cmd] create eqc failed.\n"); 4491 goto err_cmd_mbox; 4492 } 4493 4494 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4495 4496 return 0; 4497 4498 err_cmd_mbox: 4499 if (!hr_dev->caps.eqe_hop_num) 4500 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf, 4501 eq->buf_list->map); 4502 else { 4503 hns_roce_mhop_free_eq(hr_dev, eq); 4504 goto free_cmd_mbox; 4505 } 4506 4507 err_alloc_buf: 4508 kfree(eq->buf_list); 4509 4510 free_cmd_mbox: 4511 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4512 4513 return ret; 4514 } 4515 4516 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 4517 { 4518 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4519 struct device *dev = hr_dev->dev; 4520 struct hns_roce_eq *eq; 4521 unsigned int eq_cmd; 4522 int irq_num; 4523 int eq_num; 4524 int other_num; 4525 int comp_num; 4526 int aeq_num; 4527 int i, j, k; 4528 int ret; 4529 4530 other_num = hr_dev->caps.num_other_vectors; 4531 comp_num = hr_dev->caps.num_comp_vectors; 4532 aeq_num = hr_dev->caps.num_aeq_vectors; 4533 4534 eq_num = comp_num + aeq_num; 4535 irq_num = eq_num + other_num; 4536 4537 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 4538 if (!eq_table->eq) 4539 return -ENOMEM; 4540 4541 for (i = 0; i < irq_num; i++) { 4542 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 4543 GFP_KERNEL); 4544 if (!hr_dev->irq_names[i]) { 4545 ret = -ENOMEM; 4546 goto err_failed_kzalloc; 4547 } 4548 } 4549 4550 /* create eq */ 4551 for (j = 0; j < eq_num; j++) { 4552 eq = &eq_table->eq[j]; 4553 eq->hr_dev = hr_dev; 4554 eq->eqn = j; 4555 if (j < comp_num) { 4556 /* CEQ */ 4557 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 4558 eq->type_flag = HNS_ROCE_CEQ; 4559 eq->entries = hr_dev->caps.ceqe_depth; 4560 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 4561 eq->irq = hr_dev->irq[j + other_num + aeq_num]; 4562 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 4563 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 4564 } else { 4565 /* AEQ */ 4566 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 4567 eq->type_flag = HNS_ROCE_AEQ; 4568 eq->entries = hr_dev->caps.aeqe_depth; 4569 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 4570 eq->irq = hr_dev->irq[j - comp_num + other_num]; 4571 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 4572 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 4573 } 4574 4575 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 4576 if (ret) { 4577 dev_err(dev, "eq create failed.\n"); 4578 goto err_create_eq_fail; 4579 } 4580 } 4581 4582 /* enable irq */ 4583 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 4584 4585 /* irq contains: abnormal + AEQ + CEQ*/ 4586 for (k = 0; k < irq_num; k++) 4587 if (k < other_num) 4588 snprintf((char *)hr_dev->irq_names[k], 4589 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k); 4590 else if (k < (other_num + aeq_num)) 4591 snprintf((char *)hr_dev->irq_names[k], 4592 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d", 4593 k - other_num); 4594 else 4595 snprintf((char *)hr_dev->irq_names[k], 4596 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d", 4597 k - other_num - aeq_num); 4598 4599 for (k = 0; k < irq_num; k++) { 4600 if (k < other_num) 4601 ret = request_irq(hr_dev->irq[k], 4602 hns_roce_v2_msix_interrupt_abn, 4603 0, hr_dev->irq_names[k], hr_dev); 4604 4605 else if (k < (other_num + comp_num)) 4606 ret = request_irq(eq_table->eq[k - other_num].irq, 4607 hns_roce_v2_msix_interrupt_eq, 4608 0, hr_dev->irq_names[k + aeq_num], 4609 &eq_table->eq[k - other_num]); 4610 else 4611 ret = request_irq(eq_table->eq[k - other_num].irq, 4612 hns_roce_v2_msix_interrupt_eq, 4613 0, hr_dev->irq_names[k - comp_num], 4614 &eq_table->eq[k - other_num]); 4615 if (ret) { 4616 dev_err(dev, "Request irq error!\n"); 4617 goto err_request_irq_fail; 4618 } 4619 } 4620 4621 return 0; 4622 4623 err_request_irq_fail: 4624 for (k -= 1; k >= 0; k--) 4625 if (k < other_num) 4626 free_irq(hr_dev->irq[k], hr_dev); 4627 else 4628 free_irq(eq_table->eq[k - other_num].irq, 4629 &eq_table->eq[k - other_num]); 4630 4631 err_create_eq_fail: 4632 for (j -= 1; j >= 0; j--) 4633 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]); 4634 4635 err_failed_kzalloc: 4636 for (i -= 1; i >= 0; i--) 4637 kfree(hr_dev->irq_names[i]); 4638 kfree(eq_table->eq); 4639 4640 return ret; 4641 } 4642 4643 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 4644 { 4645 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 4646 int irq_num; 4647 int eq_num; 4648 int i; 4649 4650 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 4651 irq_num = eq_num + hr_dev->caps.num_other_vectors; 4652 4653 /* Disable irq */ 4654 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 4655 4656 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 4657 free_irq(hr_dev->irq[i], hr_dev); 4658 4659 for (i = 0; i < eq_num; i++) { 4660 hns_roce_v2_destroy_eqc(hr_dev, i); 4661 4662 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]); 4663 4664 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]); 4665 } 4666 4667 for (i = 0; i < irq_num; i++) 4668 kfree(hr_dev->irq_names[i]); 4669 4670 kfree(eq_table->eq); 4671 } 4672 4673 static const struct hns_roce_hw hns_roce_hw_v2 = { 4674 .cmq_init = hns_roce_v2_cmq_init, 4675 .cmq_exit = hns_roce_v2_cmq_exit, 4676 .hw_profile = hns_roce_v2_profile, 4677 .post_mbox = hns_roce_v2_post_mbox, 4678 .chk_mbox = hns_roce_v2_chk_mbox, 4679 .set_gid = hns_roce_v2_set_gid, 4680 .set_mac = hns_roce_v2_set_mac, 4681 .write_mtpt = hns_roce_v2_write_mtpt, 4682 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 4683 .write_cqc = hns_roce_v2_write_cqc, 4684 .set_hem = hns_roce_v2_set_hem, 4685 .clear_hem = hns_roce_v2_clear_hem, 4686 .modify_qp = hns_roce_v2_modify_qp, 4687 .query_qp = hns_roce_v2_query_qp, 4688 .destroy_qp = hns_roce_v2_destroy_qp, 4689 .modify_cq = hns_roce_v2_modify_cq, 4690 .post_send = hns_roce_v2_post_send, 4691 .post_recv = hns_roce_v2_post_recv, 4692 .req_notify_cq = hns_roce_v2_req_notify_cq, 4693 .poll_cq = hns_roce_v2_poll_cq, 4694 .init_eq = hns_roce_v2_init_eq_table, 4695 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 4696 }; 4697 4698 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 4699 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 4700 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 4701 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 4702 /* required last entry */ 4703 {0, } 4704 }; 4705 4706 static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 4707 struct hnae3_handle *handle) 4708 { 4709 const struct pci_device_id *id; 4710 int i; 4711 4712 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 4713 if (!id) { 4714 dev_err(hr_dev->dev, "device is not compatible!\n"); 4715 return -ENXIO; 4716 } 4717 4718 hr_dev->hw = &hns_roce_hw_v2; 4719 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 4720 hr_dev->odb_offset = hr_dev->sdb_offset; 4721 4722 /* Get info from NIC driver. */ 4723 hr_dev->reg_base = handle->rinfo.roce_io_base; 4724 hr_dev->caps.num_ports = 1; 4725 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 4726 hr_dev->iboe.phy_port[0] = 0; 4727 4728 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 4729 hr_dev->iboe.netdevs[0]->dev_addr); 4730 4731 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 4732 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 4733 i + handle->rinfo.base_vector); 4734 4735 /* cmd issue mode: 0 is poll, 1 is event */ 4736 hr_dev->cmd_mod = 1; 4737 hr_dev->loop_idc = 0; 4738 4739 return 0; 4740 } 4741 4742 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 4743 { 4744 struct hns_roce_dev *hr_dev; 4745 int ret; 4746 4747 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev)); 4748 if (!hr_dev) 4749 return -ENOMEM; 4750 4751 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 4752 if (!hr_dev->priv) { 4753 ret = -ENOMEM; 4754 goto error_failed_kzalloc; 4755 } 4756 4757 hr_dev->pci_dev = handle->pdev; 4758 hr_dev->dev = &handle->pdev->dev; 4759 handle->priv = hr_dev; 4760 4761 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle); 4762 if (ret) { 4763 dev_err(hr_dev->dev, "Get Configuration failed!\n"); 4764 goto error_failed_get_cfg; 4765 } 4766 4767 ret = hns_roce_init(hr_dev); 4768 if (ret) { 4769 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 4770 goto error_failed_get_cfg; 4771 } 4772 4773 return 0; 4774 4775 error_failed_get_cfg: 4776 kfree(hr_dev->priv); 4777 4778 error_failed_kzalloc: 4779 ib_dealloc_device(&hr_dev->ib_dev); 4780 4781 return ret; 4782 } 4783 4784 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 4785 bool reset) 4786 { 4787 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 4788 4789 hns_roce_exit(hr_dev); 4790 kfree(hr_dev->priv); 4791 ib_dealloc_device(&hr_dev->ib_dev); 4792 } 4793 4794 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 4795 .init_instance = hns_roce_hw_v2_init_instance, 4796 .uninit_instance = hns_roce_hw_v2_uninit_instance, 4797 }; 4798 4799 static struct hnae3_client hns_roce_hw_v2_client = { 4800 .name = "hns_roce_hw_v2", 4801 .type = HNAE3_CLIENT_ROCE, 4802 .ops = &hns_roce_hw_v2_ops, 4803 }; 4804 4805 static int __init hns_roce_hw_v2_init(void) 4806 { 4807 return hnae3_register_client(&hns_roce_hw_v2_client); 4808 } 4809 4810 static void __exit hns_roce_hw_v2_exit(void) 4811 { 4812 hnae3_unregister_client(&hns_roce_hw_v2_client); 4813 } 4814 4815 module_init(hns_roce_hw_v2_init); 4816 module_exit(hns_roce_hw_v2_exit); 4817 4818 MODULE_LICENSE("Dual BSD/GPL"); 4819 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 4820 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 4821 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 4822 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 4823