1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 struct ib_qp *ibqp = &hr_qp->ibqp; 377 378 if (unlikely(ibqp->qp_type != IB_QPT_RC && 379 ibqp->qp_type != IB_QPT_GSI && 380 ibqp->qp_type != IB_QPT_UD)) { 381 ibdev_err(ibdev, "not supported QP(0x%x)type!\n", 382 ibqp->qp_type); 383 return -EOPNOTSUPP; 384 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 385 hr_qp->state == IB_QPS_INIT || 386 hr_qp->state == IB_QPS_RTR)) { 387 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 388 hr_qp->state); 389 return -EINVAL; 390 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 391 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 392 hr_dev->state); 393 return -EIO; 394 } 395 396 return 0; 397 } 398 399 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 400 unsigned int *sge_len) 401 { 402 unsigned int valid_num = 0; 403 unsigned int len = 0; 404 int i; 405 406 for (i = 0; i < wr->num_sge; i++) { 407 if (likely(wr->sg_list[i].length)) { 408 len += wr->sg_list[i].length; 409 valid_num++; 410 } 411 } 412 413 *sge_len = len; 414 return valid_num; 415 } 416 417 static __le32 get_immtdata(const struct ib_send_wr *wr) 418 { 419 switch (wr->opcode) { 420 case IB_WR_SEND_WITH_IMM: 421 case IB_WR_RDMA_WRITE_WITH_IMM: 422 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 423 default: 424 return 0; 425 } 426 } 427 428 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 429 const struct ib_send_wr *wr) 430 { 431 u32 ib_op = wr->opcode; 432 433 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 434 return -EINVAL; 435 436 ud_sq_wqe->immtdata = get_immtdata(wr); 437 438 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 439 440 return 0; 441 } 442 443 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 444 struct hns_roce_ah *ah) 445 { 446 struct ib_device *ib_dev = ah->ibah.device; 447 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 448 449 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 451 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 452 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 453 454 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 455 return -EINVAL; 456 457 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 458 459 ud_sq_wqe->sgid_index = ah->av.gid_index; 460 461 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 462 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 463 464 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 465 return 0; 466 467 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 468 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 469 470 return 0; 471 } 472 473 static inline int set_ud_wqe(struct hns_roce_qp *qp, 474 const struct ib_send_wr *wr, 475 void *wqe, unsigned int *sge_idx, 476 unsigned int owner_bit) 477 { 478 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 479 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 480 unsigned int curr_idx = *sge_idx; 481 unsigned int valid_num_sge; 482 u32 msg_len = 0; 483 int ret; 484 485 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 486 487 ret = set_ud_opcode(ud_sq_wqe, wr); 488 if (WARN_ON(ret)) 489 return ret; 490 491 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 492 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 494 !!(wr->send_flags & IB_SEND_SIGNALED)); 495 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 496 !!(wr->send_flags & IB_SEND_SOLICITED)); 497 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 499 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 500 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 501 curr_idx & (qp->sge.sge_cnt - 1)); 502 503 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 504 qp->qkey : ud_wr(wr)->remote_qkey); 505 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 506 507 ret = fill_ud_av(ud_sq_wqe, ah); 508 if (ret) 509 return ret; 510 511 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 512 513 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 514 515 /* 516 * The pipeline can sequentially post all valid WQEs into WQ buffer, 517 * including new WQEs waiting for the doorbell to update the PI again. 518 * Therefore, the owner bit of WQE MUST be updated after all fields 519 * and extSGEs have been written into DDR instead of cache. 520 */ 521 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 522 dma_wmb(); 523 524 *sge_idx = curr_idx; 525 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 526 527 return 0; 528 } 529 530 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 531 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 532 const struct ib_send_wr *wr) 533 { 534 u32 ib_op = wr->opcode; 535 int ret = 0; 536 537 rc_sq_wqe->immtdata = get_immtdata(wr); 538 539 switch (ib_op) { 540 case IB_WR_RDMA_READ: 541 case IB_WR_RDMA_WRITE: 542 case IB_WR_RDMA_WRITE_WITH_IMM: 543 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 544 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 545 break; 546 case IB_WR_SEND: 547 case IB_WR_SEND_WITH_IMM: 548 break; 549 case IB_WR_ATOMIC_CMP_AND_SWP: 550 case IB_WR_ATOMIC_FETCH_AND_ADD: 551 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 552 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 553 break; 554 case IB_WR_REG_MR: 555 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 556 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 557 else 558 ret = -EOPNOTSUPP; 559 break; 560 case IB_WR_SEND_WITH_INV: 561 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 562 break; 563 default: 564 ret = -EINVAL; 565 } 566 567 if (unlikely(ret)) 568 return ret; 569 570 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 571 572 return ret; 573 } 574 575 static inline int set_rc_wqe(struct hns_roce_qp *qp, 576 const struct ib_send_wr *wr, 577 void *wqe, unsigned int *sge_idx, 578 unsigned int owner_bit) 579 { 580 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 581 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 582 unsigned int curr_idx = *sge_idx; 583 unsigned int valid_num_sge; 584 u32 msg_len = 0; 585 int ret; 586 587 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 588 589 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 590 591 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 592 if (WARN_ON(ret)) 593 return ret; 594 595 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 596 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 597 598 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 599 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 600 601 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 602 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 603 604 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 605 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 606 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 607 else if (wr->opcode != IB_WR_REG_MR) 608 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 609 &curr_idx, valid_num_sge); 610 611 /* 612 * The pipeline can sequentially post all valid WQEs into WQ buffer, 613 * including new WQEs waiting for the doorbell to update the PI again. 614 * Therefore, the owner bit of WQE MUST be updated after all fields 615 * and extSGEs have been written into DDR instead of cache. 616 */ 617 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 618 dma_wmb(); 619 620 *sge_idx = curr_idx; 621 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 622 623 return ret; 624 } 625 626 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 627 struct hns_roce_qp *qp) 628 { 629 if (unlikely(qp->state == IB_QPS_ERR)) { 630 flush_cqe(hr_dev, qp); 631 } else { 632 struct hns_roce_v2_db sq_db = {}; 633 634 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 635 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 636 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 637 hr_reg_write(&sq_db, DB_SL, qp->sl); 638 639 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 640 } 641 } 642 643 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 644 struct hns_roce_qp *qp) 645 { 646 if (unlikely(qp->state == IB_QPS_ERR)) { 647 flush_cqe(hr_dev, qp); 648 } else { 649 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 650 *qp->rdb.db_record = 651 qp->rq.head & V2_DB_PRODUCER_IDX_M; 652 } else { 653 struct hns_roce_v2_db rq_db = {}; 654 655 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 656 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 657 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 658 659 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 660 qp->rq.db_reg); 661 } 662 } 663 } 664 665 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 666 u64 __iomem *dest) 667 { 668 #define HNS_ROCE_WRITE_TIMES 8 669 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 670 struct hnae3_handle *handle = priv->handle; 671 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 672 int i; 673 674 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 675 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 676 writeq_relaxed(*(val + i), dest + i); 677 } 678 679 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 680 void *wqe) 681 { 682 #define HNS_ROCE_SL_SHIFT 2 683 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 684 685 /* All kinds of DirectWQE have the same header field layout */ 686 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 687 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 688 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 689 qp->sl >> HNS_ROCE_SL_SHIFT); 690 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 691 692 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 693 } 694 695 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 696 const struct ib_send_wr *wr, 697 const struct ib_send_wr **bad_wr) 698 { 699 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 700 struct ib_device *ibdev = &hr_dev->ib_dev; 701 struct hns_roce_qp *qp = to_hr_qp(ibqp); 702 unsigned long flags = 0; 703 unsigned int owner_bit; 704 unsigned int sge_idx; 705 unsigned int wqe_idx; 706 void *wqe = NULL; 707 u32 nreq; 708 int ret; 709 710 spin_lock_irqsave(&qp->sq.lock, flags); 711 712 ret = check_send_valid(hr_dev, qp); 713 if (unlikely(ret)) { 714 *bad_wr = wr; 715 nreq = 0; 716 goto out; 717 } 718 719 sge_idx = qp->next_sge; 720 721 for (nreq = 0; wr; ++nreq, wr = wr->next) { 722 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 723 ret = -ENOMEM; 724 *bad_wr = wr; 725 goto out; 726 } 727 728 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 729 730 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 731 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 732 wr->num_sge, qp->sq.max_gs); 733 ret = -EINVAL; 734 *bad_wr = wr; 735 goto out; 736 } 737 738 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 739 qp->sq.wrid[wqe_idx] = wr->wr_id; 740 owner_bit = 741 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 742 743 /* Corresponding to the QP type, wqe process separately */ 744 if (ibqp->qp_type == IB_QPT_RC) 745 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 746 else 747 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 748 749 if (unlikely(ret)) { 750 *bad_wr = wr; 751 goto out; 752 } 753 } 754 755 out: 756 if (likely(nreq)) { 757 qp->sq.head += nreq; 758 qp->next_sge = sge_idx; 759 760 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 761 write_dwqe(hr_dev, qp, wqe); 762 else 763 update_sq_db(hr_dev, qp); 764 } 765 766 spin_unlock_irqrestore(&qp->sq.lock, flags); 767 768 return ret; 769 } 770 771 static int check_recv_valid(struct hns_roce_dev *hr_dev, 772 struct hns_roce_qp *hr_qp) 773 { 774 struct ib_device *ibdev = &hr_dev->ib_dev; 775 struct ib_qp *ibqp = &hr_qp->ibqp; 776 777 if (unlikely(ibqp->qp_type != IB_QPT_RC && 778 ibqp->qp_type != IB_QPT_GSI && 779 ibqp->qp_type != IB_QPT_UD)) { 780 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 781 ibqp->qp_type); 782 return -EOPNOTSUPP; 783 } 784 785 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 786 return -EIO; 787 788 if (hr_qp->state == IB_QPS_RESET) 789 return -EINVAL; 790 791 return 0; 792 } 793 794 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 795 u32 max_sge, bool rsv) 796 { 797 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 798 u32 i, cnt; 799 800 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 801 /* Skip zero-length sge */ 802 if (!wr->sg_list[i].length) 803 continue; 804 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 805 cnt++; 806 } 807 808 /* Fill a reserved sge to make hw stop reading remaining segments */ 809 if (rsv) { 810 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 811 dseg[cnt].addr = 0; 812 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 813 } else { 814 /* Clear remaining segments to make ROCEE ignore sges */ 815 if (cnt < max_sge) 816 memset(dseg + cnt, 0, 817 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 818 } 819 } 820 821 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 822 u32 wqe_idx, u32 max_sge) 823 { 824 void *wqe = NULL; 825 826 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 827 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 828 } 829 830 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 831 const struct ib_recv_wr *wr, 832 const struct ib_recv_wr **bad_wr) 833 { 834 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 835 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 836 struct ib_device *ibdev = &hr_dev->ib_dev; 837 u32 wqe_idx, nreq, max_sge; 838 unsigned long flags; 839 int ret; 840 841 spin_lock_irqsave(&hr_qp->rq.lock, flags); 842 843 ret = check_recv_valid(hr_dev, hr_qp); 844 if (unlikely(ret)) { 845 *bad_wr = wr; 846 nreq = 0; 847 goto out; 848 } 849 850 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 851 for (nreq = 0; wr; ++nreq, wr = wr->next) { 852 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 853 hr_qp->ibqp.recv_cq))) { 854 ret = -ENOMEM; 855 *bad_wr = wr; 856 goto out; 857 } 858 859 if (unlikely(wr->num_sge > max_sge)) { 860 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 861 wr->num_sge, max_sge); 862 ret = -EINVAL; 863 *bad_wr = wr; 864 goto out; 865 } 866 867 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 868 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 869 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 870 } 871 872 out: 873 if (likely(nreq)) { 874 hr_qp->rq.head += nreq; 875 876 update_rq_db(hr_dev, hr_qp); 877 } 878 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 879 880 return ret; 881 } 882 883 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 884 { 885 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 886 } 887 888 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 889 { 890 return hns_roce_buf_offset(idx_que->mtr.kmem, 891 n << idx_que->entry_shift); 892 } 893 894 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 895 { 896 /* always called with interrupts disabled. */ 897 spin_lock(&srq->lock); 898 899 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 900 srq->idx_que.tail++; 901 902 spin_unlock(&srq->lock); 903 } 904 905 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 906 { 907 struct hns_roce_idx_que *idx_que = &srq->idx_que; 908 909 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 910 } 911 912 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 913 const struct ib_recv_wr *wr) 914 { 915 struct ib_device *ib_dev = srq->ibsrq.device; 916 917 if (unlikely(wr->num_sge > max_sge)) { 918 ibdev_err(ib_dev, 919 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 920 wr->num_sge, max_sge); 921 return -EINVAL; 922 } 923 924 if (unlikely(hns_roce_srqwq_overflow(srq))) { 925 ibdev_err(ib_dev, 926 "failed to check srqwq status, srqwq is full.\n"); 927 return -ENOMEM; 928 } 929 930 return 0; 931 } 932 933 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 934 { 935 struct hns_roce_idx_que *idx_que = &srq->idx_que; 936 u32 pos; 937 938 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 939 if (unlikely(pos == srq->wqe_cnt)) 940 return -ENOSPC; 941 942 bitmap_set(idx_que->bitmap, pos, 1); 943 *wqe_idx = pos; 944 return 0; 945 } 946 947 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 948 { 949 struct hns_roce_idx_que *idx_que = &srq->idx_que; 950 unsigned int head; 951 __le32 *buf; 952 953 head = idx_que->head & (srq->wqe_cnt - 1); 954 955 buf = get_idx_buf(idx_que, head); 956 *buf = cpu_to_le32(wqe_idx); 957 958 idx_que->head++; 959 } 960 961 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 962 { 963 hr_reg_write(db, DB_TAG, srq->srqn); 964 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 965 hr_reg_write(db, DB_PI, srq->idx_que.head); 966 } 967 968 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 969 const struct ib_recv_wr *wr, 970 const struct ib_recv_wr **bad_wr) 971 { 972 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 973 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 974 struct hns_roce_v2_db srq_db; 975 unsigned long flags; 976 int ret = 0; 977 u32 max_sge; 978 u32 wqe_idx; 979 void *wqe; 980 u32 nreq; 981 982 spin_lock_irqsave(&srq->lock, flags); 983 984 max_sge = srq->max_gs - srq->rsv_sge; 985 for (nreq = 0; wr; ++nreq, wr = wr->next) { 986 ret = check_post_srq_valid(srq, max_sge, wr); 987 if (ret) { 988 *bad_wr = wr; 989 break; 990 } 991 992 ret = get_srq_wqe_idx(srq, &wqe_idx); 993 if (unlikely(ret)) { 994 *bad_wr = wr; 995 break; 996 } 997 998 wqe = get_srq_wqe_buf(srq, wqe_idx); 999 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1000 fill_wqe_idx(srq, wqe_idx); 1001 srq->wrid[wqe_idx] = wr->wr_id; 1002 } 1003 1004 if (likely(nreq)) { 1005 update_srq_db(&srq_db, srq); 1006 1007 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1008 } 1009 1010 spin_unlock_irqrestore(&srq->lock, flags); 1011 1012 return ret; 1013 } 1014 1015 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1016 unsigned long instance_stage, 1017 unsigned long reset_stage) 1018 { 1019 /* When hardware reset has been completed once or more, we should stop 1020 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1021 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1022 * stage of soft reset process, we should exit with error, and then 1023 * HNAE3_INIT_CLIENT related process can rollback the operation like 1024 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1025 * process will exit with error to notify NIC driver to reschedule soft 1026 * reset process once again. 1027 */ 1028 hr_dev->is_reset = true; 1029 hr_dev->dis_db = true; 1030 1031 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1032 instance_stage == HNS_ROCE_STATE_INIT) 1033 return CMD_RST_PRC_EBUSY; 1034 1035 return CMD_RST_PRC_SUCCESS; 1036 } 1037 1038 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1039 unsigned long instance_stage, 1040 unsigned long reset_stage) 1041 { 1042 #define HW_RESET_TIMEOUT_US 1000000 1043 #define HW_RESET_SLEEP_US 1000 1044 1045 struct hns_roce_v2_priv *priv = hr_dev->priv; 1046 struct hnae3_handle *handle = priv->handle; 1047 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1048 unsigned long val; 1049 int ret; 1050 1051 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1052 * doorbell to hardware. If now in .init_instance() function, we should 1053 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1054 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1055 * related process can rollback the operation like notifing hardware to 1056 * free resources, HNAE3_INIT_CLIENT related process will exit with 1057 * error to notify NIC driver to reschedule soft reset process once 1058 * again. 1059 */ 1060 hr_dev->dis_db = true; 1061 1062 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1063 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1064 HW_RESET_TIMEOUT_US, false, handle); 1065 if (!ret) 1066 hr_dev->is_reset = true; 1067 1068 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1069 instance_stage == HNS_ROCE_STATE_INIT) 1070 return CMD_RST_PRC_EBUSY; 1071 1072 return CMD_RST_PRC_SUCCESS; 1073 } 1074 1075 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1076 { 1077 struct hns_roce_v2_priv *priv = hr_dev->priv; 1078 struct hnae3_handle *handle = priv->handle; 1079 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1080 1081 /* When software reset is detected at .init_instance() function, we 1082 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1083 * with error. 1084 */ 1085 hr_dev->dis_db = true; 1086 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1087 hr_dev->is_reset = true; 1088 1089 return CMD_RST_PRC_EBUSY; 1090 } 1091 1092 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1093 struct hnae3_handle *handle) 1094 { 1095 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1096 unsigned long instance_stage; /* the current instance stage */ 1097 unsigned long reset_stage; /* the current reset stage */ 1098 unsigned long reset_cnt; 1099 bool sw_resetting; 1100 bool hw_resetting; 1101 1102 /* Get information about reset from NIC driver or RoCE driver itself, 1103 * the meaning of the following variables from NIC driver are described 1104 * as below: 1105 * reset_cnt -- The count value of completed hardware reset. 1106 * hw_resetting -- Whether hardware device is resetting now. 1107 * sw_resetting -- Whether NIC's software reset process is running now. 1108 */ 1109 instance_stage = handle->rinfo.instance_state; 1110 reset_stage = handle->rinfo.reset_state; 1111 reset_cnt = ops->ae_dev_reset_cnt(handle); 1112 if (reset_cnt != hr_dev->reset_cnt) 1113 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1114 reset_stage); 1115 1116 hw_resetting = ops->get_cmdq_stat(handle); 1117 if (hw_resetting) 1118 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1119 reset_stage); 1120 1121 sw_resetting = ops->ae_dev_resetting(handle); 1122 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1123 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1124 1125 return CMD_RST_PRC_OTHERS; 1126 } 1127 1128 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1129 { 1130 struct hns_roce_v2_priv *priv = hr_dev->priv; 1131 struct hnae3_handle *handle = priv->handle; 1132 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1133 1134 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1135 return true; 1136 1137 if (ops->get_hw_reset_stat(handle)) 1138 return true; 1139 1140 if (ops->ae_dev_resetting(handle)) 1141 return true; 1142 1143 return false; 1144 } 1145 1146 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1147 { 1148 struct hns_roce_v2_priv *priv = hr_dev->priv; 1149 u32 status; 1150 1151 if (hr_dev->is_reset) 1152 status = CMD_RST_PRC_SUCCESS; 1153 else 1154 status = check_aedev_reset_status(hr_dev, priv->handle); 1155 1156 *busy = (status == CMD_RST_PRC_EBUSY); 1157 1158 return status == CMD_RST_PRC_OTHERS; 1159 } 1160 1161 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1162 struct hns_roce_v2_cmq_ring *ring) 1163 { 1164 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1165 1166 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1167 &ring->desc_dma_addr, GFP_KERNEL); 1168 if (!ring->desc) 1169 return -ENOMEM; 1170 1171 return 0; 1172 } 1173 1174 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1175 struct hns_roce_v2_cmq_ring *ring) 1176 { 1177 dma_free_coherent(hr_dev->dev, 1178 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1179 ring->desc, ring->desc_dma_addr); 1180 1181 ring->desc_dma_addr = 0; 1182 } 1183 1184 static int init_csq(struct hns_roce_dev *hr_dev, 1185 struct hns_roce_v2_cmq_ring *csq) 1186 { 1187 dma_addr_t dma; 1188 int ret; 1189 1190 csq->desc_num = CMD_CSQ_DESC_NUM; 1191 spin_lock_init(&csq->lock); 1192 csq->flag = TYPE_CSQ; 1193 csq->head = 0; 1194 1195 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1196 if (ret) 1197 return ret; 1198 1199 dma = csq->desc_dma_addr; 1200 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1201 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1202 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1203 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1204 1205 /* Make sure to write CI first and then PI */ 1206 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1207 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1208 1209 return 0; 1210 } 1211 1212 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1213 { 1214 struct hns_roce_v2_priv *priv = hr_dev->priv; 1215 int ret; 1216 1217 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1218 1219 ret = init_csq(hr_dev, &priv->cmq.csq); 1220 if (ret) 1221 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1222 1223 return ret; 1224 } 1225 1226 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1227 { 1228 struct hns_roce_v2_priv *priv = hr_dev->priv; 1229 1230 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1231 } 1232 1233 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1234 enum hns_roce_opcode_type opcode, 1235 bool is_read) 1236 { 1237 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1238 desc->opcode = cpu_to_le16(opcode); 1239 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1240 if (is_read) 1241 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1242 else 1243 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1244 } 1245 1246 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1247 { 1248 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1249 struct hns_roce_v2_priv *priv = hr_dev->priv; 1250 1251 return tail == priv->cmq.csq.head; 1252 } 1253 1254 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1255 { 1256 struct hns_roce_v2_priv *priv = hr_dev->priv; 1257 struct hnae3_handle *handle = priv->handle; 1258 1259 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1260 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1261 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1262 } 1263 1264 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1265 { 1266 struct hns_roce_cmd_errcode errcode_table[] = { 1267 {CMD_EXEC_SUCCESS, 0}, 1268 {CMD_NO_AUTH, -EPERM}, 1269 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1270 {CMD_CRQ_FULL, -EXFULL}, 1271 {CMD_NEXT_ERR, -ENOSR}, 1272 {CMD_NOT_EXEC, -ENOTBLK}, 1273 {CMD_PARA_ERR, -EINVAL}, 1274 {CMD_RESULT_ERR, -ERANGE}, 1275 {CMD_TIMEOUT, -ETIME}, 1276 {CMD_HILINK_ERR, -ENOLINK}, 1277 {CMD_INFO_ILLEGAL, -ENXIO}, 1278 {CMD_INVALID, -EBADR}, 1279 }; 1280 u16 i; 1281 1282 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1283 if (desc_ret == errcode_table[i].return_status) 1284 return errcode_table[i].errno; 1285 return -EIO; 1286 } 1287 1288 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1289 struct hns_roce_cmq_desc *desc, int num) 1290 { 1291 struct hns_roce_v2_priv *priv = hr_dev->priv; 1292 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1293 u32 timeout = 0; 1294 u16 desc_ret; 1295 u32 tail; 1296 int ret; 1297 int i; 1298 1299 spin_lock_bh(&csq->lock); 1300 1301 tail = csq->head; 1302 1303 for (i = 0; i < num; i++) { 1304 csq->desc[csq->head++] = desc[i]; 1305 if (csq->head == csq->desc_num) 1306 csq->head = 0; 1307 } 1308 1309 /* Write to hardware */ 1310 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1311 1312 do { 1313 if (hns_roce_cmq_csq_done(hr_dev)) 1314 break; 1315 udelay(1); 1316 } while (++timeout < priv->cmq.tx_timeout); 1317 1318 if (hns_roce_cmq_csq_done(hr_dev)) { 1319 ret = 0; 1320 for (i = 0; i < num; i++) { 1321 /* check the result of hardware write back */ 1322 desc[i] = csq->desc[tail++]; 1323 if (tail == csq->desc_num) 1324 tail = 0; 1325 1326 desc_ret = le16_to_cpu(desc[i].retval); 1327 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1328 continue; 1329 1330 dev_err_ratelimited(hr_dev->dev, 1331 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1332 desc->opcode, desc_ret); 1333 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1334 } 1335 } else { 1336 /* FW/HW reset or incorrect number of desc */ 1337 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1338 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1339 csq->head, tail); 1340 csq->head = tail; 1341 1342 update_cmdq_status(hr_dev); 1343 1344 ret = -EAGAIN; 1345 } 1346 1347 spin_unlock_bh(&csq->lock); 1348 1349 return ret; 1350 } 1351 1352 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1353 struct hns_roce_cmq_desc *desc, int num) 1354 { 1355 bool busy; 1356 int ret; 1357 1358 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1359 return -EIO; 1360 1361 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1362 return busy ? -EBUSY : 0; 1363 1364 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1365 if (ret) { 1366 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1367 return busy ? -EBUSY : 0; 1368 } 1369 1370 return ret; 1371 } 1372 1373 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1374 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1375 { 1376 struct hns_roce_cmd_mailbox *mbox; 1377 int ret; 1378 1379 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1380 if (IS_ERR(mbox)) 1381 return PTR_ERR(mbox); 1382 1383 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1384 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1385 return ret; 1386 } 1387 1388 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1389 { 1390 struct hns_roce_query_version *resp; 1391 struct hns_roce_cmq_desc desc; 1392 int ret; 1393 1394 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1395 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1396 if (ret) 1397 return ret; 1398 1399 resp = (struct hns_roce_query_version *)desc.data; 1400 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1401 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1402 1403 return 0; 1404 } 1405 1406 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1407 struct hnae3_handle *handle) 1408 { 1409 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1410 unsigned long end; 1411 1412 hr_dev->dis_db = true; 1413 1414 dev_warn(hr_dev->dev, 1415 "func clear is pending, device in resetting state.\n"); 1416 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1417 while (end) { 1418 if (!ops->get_hw_reset_stat(handle)) { 1419 hr_dev->is_reset = true; 1420 dev_info(hr_dev->dev, 1421 "func clear success after reset.\n"); 1422 return; 1423 } 1424 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1425 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1426 } 1427 1428 dev_warn(hr_dev->dev, "func clear failed.\n"); 1429 } 1430 1431 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1432 struct hnae3_handle *handle) 1433 { 1434 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1435 unsigned long end; 1436 1437 hr_dev->dis_db = true; 1438 1439 dev_warn(hr_dev->dev, 1440 "func clear is pending, device in resetting state.\n"); 1441 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1442 while (end) { 1443 if (ops->ae_dev_reset_cnt(handle) != 1444 hr_dev->reset_cnt) { 1445 hr_dev->is_reset = true; 1446 dev_info(hr_dev->dev, 1447 "func clear success after sw reset\n"); 1448 return; 1449 } 1450 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1451 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1452 } 1453 1454 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1455 } 1456 1457 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1458 int flag) 1459 { 1460 struct hns_roce_v2_priv *priv = hr_dev->priv; 1461 struct hnae3_handle *handle = priv->handle; 1462 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1463 1464 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1465 hr_dev->dis_db = true; 1466 hr_dev->is_reset = true; 1467 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1468 return; 1469 } 1470 1471 if (ops->get_hw_reset_stat(handle)) { 1472 func_clr_hw_resetting_state(hr_dev, handle); 1473 return; 1474 } 1475 1476 if (ops->ae_dev_resetting(handle) && 1477 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1478 func_clr_sw_resetting_state(hr_dev, handle); 1479 return; 1480 } 1481 1482 if (retval && !flag) 1483 dev_warn(hr_dev->dev, 1484 "func clear read failed, ret = %d.\n", retval); 1485 1486 dev_warn(hr_dev->dev, "func clear failed.\n"); 1487 } 1488 1489 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1490 { 1491 bool fclr_write_fail_flag = false; 1492 struct hns_roce_func_clear *resp; 1493 struct hns_roce_cmq_desc desc; 1494 unsigned long end; 1495 int ret = 0; 1496 1497 if (check_device_is_in_reset(hr_dev)) 1498 goto out; 1499 1500 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1501 resp = (struct hns_roce_func_clear *)desc.data; 1502 resp->rst_funcid_en = cpu_to_le32(vf_id); 1503 1504 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1505 if (ret) { 1506 fclr_write_fail_flag = true; 1507 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1508 ret); 1509 goto out; 1510 } 1511 1512 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1513 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1514 while (end) { 1515 if (check_device_is_in_reset(hr_dev)) 1516 goto out; 1517 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1518 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1519 1520 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1521 true); 1522 1523 resp->rst_funcid_en = cpu_to_le32(vf_id); 1524 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1525 if (ret) 1526 continue; 1527 1528 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1529 if (vf_id == 0) 1530 hr_dev->is_reset = true; 1531 return; 1532 } 1533 } 1534 1535 out: 1536 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1537 } 1538 1539 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1540 { 1541 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1542 struct hns_roce_cmq_desc desc[2]; 1543 struct hns_roce_cmq_req *req_a; 1544 1545 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1546 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1547 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1548 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1549 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1550 1551 return hns_roce_cmq_send(hr_dev, desc, 2); 1552 } 1553 1554 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1555 { 1556 int ret; 1557 int i; 1558 1559 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1560 return; 1561 1562 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1563 __hns_roce_function_clear(hr_dev, i); 1564 1565 if (i == 0) 1566 continue; 1567 1568 ret = hns_roce_free_vf_resource(hr_dev, i); 1569 if (ret) 1570 ibdev_err(&hr_dev->ib_dev, 1571 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1572 i, ret); 1573 } 1574 } 1575 1576 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1577 { 1578 struct hns_roce_cmq_desc desc; 1579 int ret; 1580 1581 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1582 false); 1583 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1584 if (ret) 1585 ibdev_err(&hr_dev->ib_dev, 1586 "failed to clear extended doorbell info, ret = %d.\n", 1587 ret); 1588 1589 return ret; 1590 } 1591 1592 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1593 { 1594 struct hns_roce_query_fw_info *resp; 1595 struct hns_roce_cmq_desc desc; 1596 int ret; 1597 1598 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1599 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1600 if (ret) 1601 return ret; 1602 1603 resp = (struct hns_roce_query_fw_info *)desc.data; 1604 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1605 1606 return 0; 1607 } 1608 1609 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1610 { 1611 struct hns_roce_cmq_desc desc; 1612 int ret; 1613 1614 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1615 hr_dev->func_num = 1; 1616 return 0; 1617 } 1618 1619 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1620 true); 1621 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1622 if (ret) { 1623 hr_dev->func_num = 1; 1624 return ret; 1625 } 1626 1627 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1628 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1629 1630 return 0; 1631 } 1632 1633 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1634 { 1635 struct hns_roce_cmq_desc desc; 1636 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1637 u32 clock_cycles_of_1us; 1638 1639 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1640 false); 1641 1642 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1643 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1644 else 1645 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1646 1647 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1648 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1649 1650 return hns_roce_cmq_send(hr_dev, &desc, 1); 1651 } 1652 1653 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1654 { 1655 struct hns_roce_cmq_desc desc[2]; 1656 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1657 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1658 struct hns_roce_caps *caps = &hr_dev->caps; 1659 enum hns_roce_opcode_type opcode; 1660 u32 func_num; 1661 int ret; 1662 1663 if (is_vf) { 1664 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1665 func_num = 1; 1666 } else { 1667 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1668 func_num = hr_dev->func_num; 1669 } 1670 1671 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1672 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1673 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1674 1675 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1676 if (ret) 1677 return ret; 1678 1679 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1680 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1681 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1682 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1683 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1684 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1685 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1686 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1687 1688 if (is_vf) { 1689 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1690 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1691 func_num; 1692 } else { 1693 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1694 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1695 func_num; 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1702 { 1703 struct hns_roce_cmq_desc desc; 1704 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1705 struct hns_roce_caps *caps = &hr_dev->caps; 1706 u32 func_num, qp_num; 1707 int ret; 1708 1709 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1710 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1711 if (ret) 1712 return ret; 1713 1714 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1715 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1716 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1717 1718 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1719 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1720 1721 return 0; 1722 } 1723 1724 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1725 { 1726 struct hns_roce_cmq_desc desc; 1727 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1728 struct hns_roce_caps *caps = &hr_dev->caps; 1729 int ret; 1730 1731 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1732 true); 1733 1734 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1735 if (ret) 1736 return ret; 1737 1738 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1739 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1740 1741 return 0; 1742 } 1743 1744 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1745 { 1746 struct device *dev = hr_dev->dev; 1747 int ret; 1748 1749 ret = load_func_res_caps(hr_dev, is_vf); 1750 if (ret) { 1751 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1752 is_vf ? "vf" : "pf"); 1753 return ret; 1754 } 1755 1756 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1757 ret = load_ext_cfg_caps(hr_dev, is_vf); 1758 if (ret) 1759 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1760 ret, is_vf ? "vf" : "pf"); 1761 } 1762 1763 return ret; 1764 } 1765 1766 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1767 { 1768 struct device *dev = hr_dev->dev; 1769 int ret; 1770 1771 ret = query_func_resource_caps(hr_dev, false); 1772 if (ret) 1773 return ret; 1774 1775 ret = load_pf_timer_res_caps(hr_dev); 1776 if (ret) 1777 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1778 ret); 1779 1780 return ret; 1781 } 1782 1783 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1784 { 1785 return query_func_resource_caps(hr_dev, true); 1786 } 1787 1788 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1789 u32 vf_id) 1790 { 1791 struct hns_roce_vf_switch *swt; 1792 struct hns_roce_cmq_desc desc; 1793 int ret; 1794 1795 swt = (struct hns_roce_vf_switch *)desc.data; 1796 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1797 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1798 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1799 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1800 if (ret) 1801 return ret; 1802 1803 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1804 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1805 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1806 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1807 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1808 1809 return hns_roce_cmq_send(hr_dev, &desc, 1); 1810 } 1811 1812 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1813 { 1814 u32 vf_id; 1815 int ret; 1816 1817 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1818 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1819 if (ret) 1820 return ret; 1821 } 1822 return 0; 1823 } 1824 1825 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1826 { 1827 struct hns_roce_cmq_desc desc[2]; 1828 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1829 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1830 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1831 struct hns_roce_caps *caps = &hr_dev->caps; 1832 1833 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1834 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1835 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1836 1837 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1838 1839 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1840 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1841 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1842 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1843 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1844 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1845 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1846 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1847 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1848 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1849 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1850 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1851 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1852 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1853 1854 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1855 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1856 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1857 vf_id * caps->gmv_bt_num); 1858 } else { 1859 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1860 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1861 vf_id * caps->sgid_bt_num); 1862 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1863 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1864 vf_id * caps->smac_bt_num); 1865 } 1866 1867 return hns_roce_cmq_send(hr_dev, desc, 2); 1868 } 1869 1870 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1871 { 1872 struct hns_roce_cmq_desc desc; 1873 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1874 struct hns_roce_caps *caps = &hr_dev->caps; 1875 1876 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1877 1878 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1879 1880 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1881 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1882 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1883 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1884 1885 return hns_roce_cmq_send(hr_dev, &desc, 1); 1886 } 1887 1888 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1889 { 1890 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1891 u32 vf_id; 1892 int ret; 1893 1894 for (vf_id = 0; vf_id < func_num; vf_id++) { 1895 ret = config_vf_hem_resource(hr_dev, vf_id); 1896 if (ret) { 1897 dev_err(hr_dev->dev, 1898 "failed to config vf-%u hem res, ret = %d.\n", 1899 vf_id, ret); 1900 return ret; 1901 } 1902 1903 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1904 ret = config_vf_ext_resource(hr_dev, vf_id); 1905 if (ret) { 1906 dev_err(hr_dev->dev, 1907 "failed to config vf-%u ext res, ret = %d.\n", 1908 vf_id, ret); 1909 return ret; 1910 } 1911 } 1912 } 1913 1914 return 0; 1915 } 1916 1917 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1918 { 1919 struct hns_roce_cmq_desc desc; 1920 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1921 struct hns_roce_caps *caps = &hr_dev->caps; 1922 1923 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1924 1925 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1926 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1927 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1928 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1929 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1930 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1931 1932 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1933 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1934 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1935 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1936 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1937 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1938 1939 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1940 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1941 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1942 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1943 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1944 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1945 1946 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1947 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1948 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1949 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1950 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1951 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1952 1953 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1954 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1955 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1956 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1957 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1958 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1959 1960 return hns_roce_cmq_send(hr_dev, &desc, 1); 1961 } 1962 1963 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1964 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1965 { 1966 u64 obj_per_chunk; 1967 u64 bt_chunk_size = PAGE_SIZE; 1968 u64 buf_chunk_size = PAGE_SIZE; 1969 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1970 1971 *buf_page_size = 0; 1972 *bt_page_size = 0; 1973 1974 switch (hop_num) { 1975 case 3: 1976 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1977 (bt_chunk_size / BA_BYTE_LEN) * 1978 (bt_chunk_size / BA_BYTE_LEN) * 1979 obj_per_chunk_default; 1980 break; 1981 case 2: 1982 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1983 (bt_chunk_size / BA_BYTE_LEN) * 1984 obj_per_chunk_default; 1985 break; 1986 case 1: 1987 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1988 obj_per_chunk_default; 1989 break; 1990 case HNS_ROCE_HOP_NUM_0: 1991 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1992 break; 1993 default: 1994 pr_err("table %u not support hop_num = %u!\n", hem_type, 1995 hop_num); 1996 return; 1997 } 1998 1999 if (hem_type >= HEM_TYPE_MTT) 2000 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2001 else 2002 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2003 } 2004 2005 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2006 { 2007 struct hns_roce_caps *caps = &hr_dev->caps; 2008 2009 /* EQ */ 2010 caps->eqe_ba_pg_sz = 0; 2011 caps->eqe_buf_pg_sz = 0; 2012 2013 /* Link Table */ 2014 caps->llm_buf_pg_sz = 0; 2015 2016 /* MR */ 2017 caps->mpt_ba_pg_sz = 0; 2018 caps->mpt_buf_pg_sz = 0; 2019 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2020 caps->pbl_buf_pg_sz = 0; 2021 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2022 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2023 HEM_TYPE_MTPT); 2024 2025 /* QP */ 2026 caps->qpc_ba_pg_sz = 0; 2027 caps->qpc_buf_pg_sz = 0; 2028 caps->qpc_timer_ba_pg_sz = 0; 2029 caps->qpc_timer_buf_pg_sz = 0; 2030 caps->sccc_ba_pg_sz = 0; 2031 caps->sccc_buf_pg_sz = 0; 2032 caps->mtt_ba_pg_sz = 0; 2033 caps->mtt_buf_pg_sz = 0; 2034 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2035 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2036 HEM_TYPE_QPC); 2037 2038 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2039 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2040 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2041 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2042 2043 /* CQ */ 2044 caps->cqc_ba_pg_sz = 0; 2045 caps->cqc_buf_pg_sz = 0; 2046 caps->cqc_timer_ba_pg_sz = 0; 2047 caps->cqc_timer_buf_pg_sz = 0; 2048 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2049 caps->cqe_buf_pg_sz = 0; 2050 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2051 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2052 HEM_TYPE_CQC); 2053 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2054 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2055 2056 /* SRQ */ 2057 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2058 caps->srqc_ba_pg_sz = 0; 2059 caps->srqc_buf_pg_sz = 0; 2060 caps->srqwqe_ba_pg_sz = 0; 2061 caps->srqwqe_buf_pg_sz = 0; 2062 caps->idx_ba_pg_sz = 0; 2063 caps->idx_buf_pg_sz = 0; 2064 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2065 caps->srqc_hop_num, caps->srqc_bt_num, 2066 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2067 HEM_TYPE_SRQC); 2068 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2069 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2070 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2071 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2072 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2073 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2074 } 2075 2076 /* GMV */ 2077 caps->gmv_ba_pg_sz = 0; 2078 caps->gmv_buf_pg_sz = 0; 2079 } 2080 2081 /* Apply all loaded caps before setting to hardware */ 2082 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2083 { 2084 struct hns_roce_caps *caps = &hr_dev->caps; 2085 struct hns_roce_v2_priv *priv = hr_dev->priv; 2086 2087 /* The following configurations don't need to be got from firmware. */ 2088 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2089 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2090 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2091 2092 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2093 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2094 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2095 2096 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2097 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2098 2099 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2100 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2101 2102 if (!caps->num_comp_vectors) 2103 caps->num_comp_vectors = 2104 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2105 (u32)priv->handle->rinfo.num_vectors - 2106 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2107 2108 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2109 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2110 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2111 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2112 2113 /* The following configurations will be overwritten */ 2114 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2115 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2116 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2117 2118 /* The following configurations are not got from firmware */ 2119 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2120 2121 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2122 caps->gid_table_len[0] = caps->gmv_bt_num * 2123 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2124 2125 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2126 caps->gmv_entry_sz); 2127 } else { 2128 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2129 2130 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2131 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2132 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2133 caps->gid_table_len[0] /= func_num; 2134 } 2135 2136 if (hr_dev->is_vf) { 2137 caps->default_aeq_arm_st = 0x3; 2138 caps->default_ceq_arm_st = 0x3; 2139 caps->default_ceq_max_cnt = 0x1; 2140 caps->default_ceq_period = 0x10; 2141 caps->default_aeq_max_cnt = 0x1; 2142 caps->default_aeq_period = 0x10; 2143 } 2144 2145 set_hem_page_size(hr_dev); 2146 } 2147 2148 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2149 { 2150 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2151 struct hns_roce_caps *caps = &hr_dev->caps; 2152 struct hns_roce_query_pf_caps_a *resp_a; 2153 struct hns_roce_query_pf_caps_b *resp_b; 2154 struct hns_roce_query_pf_caps_c *resp_c; 2155 struct hns_roce_query_pf_caps_d *resp_d; 2156 struct hns_roce_query_pf_caps_e *resp_e; 2157 enum hns_roce_opcode_type cmd; 2158 int ctx_hop_num; 2159 int pbl_hop_num; 2160 int ret; 2161 int i; 2162 2163 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2164 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2165 2166 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2167 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2168 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2169 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2170 else 2171 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2172 } 2173 2174 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2175 if (ret) 2176 return ret; 2177 2178 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2179 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2180 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2181 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2182 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2183 2184 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2185 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2186 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2187 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2188 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2189 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2190 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2191 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2192 caps->num_other_vectors = resp_a->num_other_vectors; 2193 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2194 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2195 2196 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2197 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2198 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2199 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2200 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2201 caps->idx_entry_sz = resp_b->idx_entry_sz; 2202 caps->sccc_sz = resp_b->sccc_sz; 2203 caps->max_mtu = resp_b->max_mtu; 2204 caps->min_cqes = resp_b->min_cqes; 2205 caps->min_wqes = resp_b->min_wqes; 2206 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2207 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2208 caps->phy_num_uars = resp_b->phy_num_uars; 2209 ctx_hop_num = resp_b->ctx_hop_num; 2210 pbl_hop_num = resp_b->pbl_hop_num; 2211 2212 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2213 2214 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2215 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2216 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2217 2218 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2219 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2220 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2221 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2222 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2223 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2224 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2225 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2226 2227 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2228 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2229 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2230 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2231 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2232 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2233 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2234 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2235 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2236 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2237 2238 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2239 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2240 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2241 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2242 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2243 2244 caps->qpc_hop_num = ctx_hop_num; 2245 caps->sccc_hop_num = ctx_hop_num; 2246 caps->srqc_hop_num = ctx_hop_num; 2247 caps->cqc_hop_num = ctx_hop_num; 2248 caps->mpt_hop_num = ctx_hop_num; 2249 caps->mtt_hop_num = pbl_hop_num; 2250 caps->cqe_hop_num = pbl_hop_num; 2251 caps->srqwqe_hop_num = pbl_hop_num; 2252 caps->idx_hop_num = pbl_hop_num; 2253 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2254 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2255 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2256 2257 if (!(caps->page_size_cap & PAGE_SIZE)) 2258 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2259 2260 if (!hr_dev->is_vf) { 2261 caps->cqe_sz = resp_a->cqe_sz; 2262 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2263 caps->default_aeq_arm_st = 2264 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2265 caps->default_ceq_arm_st = 2266 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2267 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2268 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2269 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2270 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2277 { 2278 struct hns_roce_cmq_desc desc; 2279 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2280 2281 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2282 false); 2283 2284 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2285 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2286 2287 return hns_roce_cmq_send(hr_dev, &desc, 1); 2288 } 2289 2290 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2291 { 2292 struct hns_roce_caps *caps = &hr_dev->caps; 2293 int ret; 2294 2295 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2296 return 0; 2297 2298 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2299 caps->qpc_sz); 2300 if (ret) { 2301 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2302 return ret; 2303 } 2304 2305 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2306 caps->sccc_sz); 2307 if (ret) 2308 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2309 2310 return ret; 2311 } 2312 2313 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2314 { 2315 struct device *dev = hr_dev->dev; 2316 int ret; 2317 2318 hr_dev->func_num = 1; 2319 2320 ret = hns_roce_query_caps(hr_dev); 2321 if (ret) { 2322 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2323 return ret; 2324 } 2325 2326 ret = hns_roce_query_vf_resource(hr_dev); 2327 if (ret) { 2328 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2329 return ret; 2330 } 2331 2332 apply_func_caps(hr_dev); 2333 2334 ret = hns_roce_v2_set_bt(hr_dev); 2335 if (ret) 2336 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2337 2338 return ret; 2339 } 2340 2341 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2342 { 2343 struct device *dev = hr_dev->dev; 2344 int ret; 2345 2346 ret = hns_roce_query_func_info(hr_dev); 2347 if (ret) { 2348 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2349 return ret; 2350 } 2351 2352 ret = hns_roce_config_global_param(hr_dev); 2353 if (ret) { 2354 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2355 return ret; 2356 } 2357 2358 ret = hns_roce_set_vf_switch_param(hr_dev); 2359 if (ret) { 2360 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2361 return ret; 2362 } 2363 2364 ret = hns_roce_query_caps(hr_dev); 2365 if (ret) { 2366 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2367 return ret; 2368 } 2369 2370 ret = hns_roce_query_pf_resource(hr_dev); 2371 if (ret) { 2372 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2373 return ret; 2374 } 2375 2376 apply_func_caps(hr_dev); 2377 2378 ret = hns_roce_alloc_vf_resource(hr_dev); 2379 if (ret) { 2380 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2381 return ret; 2382 } 2383 2384 ret = hns_roce_v2_set_bt(hr_dev); 2385 if (ret) { 2386 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2387 return ret; 2388 } 2389 2390 /* Configure the size of QPC, SCCC, etc. */ 2391 return hns_roce_config_entry_size(hr_dev); 2392 } 2393 2394 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2395 { 2396 struct device *dev = hr_dev->dev; 2397 int ret; 2398 2399 ret = hns_roce_cmq_query_hw_info(hr_dev); 2400 if (ret) { 2401 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2402 return ret; 2403 } 2404 2405 ret = hns_roce_query_fw_ver(hr_dev); 2406 if (ret) { 2407 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2408 return ret; 2409 } 2410 2411 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2412 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2413 2414 if (hr_dev->is_vf) 2415 return hns_roce_v2_vf_profile(hr_dev); 2416 else 2417 return hns_roce_v2_pf_profile(hr_dev); 2418 } 2419 2420 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2421 { 2422 u32 i, next_ptr, page_num; 2423 __le64 *entry = cfg_buf; 2424 dma_addr_t addr; 2425 u64 val; 2426 2427 page_num = data_buf->npages; 2428 for (i = 0; i < page_num; i++) { 2429 addr = hns_roce_buf_page(data_buf, i); 2430 if (i == (page_num - 1)) 2431 next_ptr = 0; 2432 else 2433 next_ptr = i + 1; 2434 2435 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2436 entry[i] = cpu_to_le64(val); 2437 } 2438 } 2439 2440 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2441 struct hns_roce_link_table *table) 2442 { 2443 struct hns_roce_cmq_desc desc[2]; 2444 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2445 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2446 struct hns_roce_buf *buf = table->buf; 2447 enum hns_roce_opcode_type opcode; 2448 dma_addr_t addr; 2449 2450 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2451 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2452 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2453 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2454 2455 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2456 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2457 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2458 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2459 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2460 2461 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2462 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2463 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2464 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2465 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2466 2467 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2468 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2469 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2470 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2471 2472 return hns_roce_cmq_send(hr_dev, desc, 2); 2473 } 2474 2475 static struct hns_roce_link_table * 2476 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2477 { 2478 struct hns_roce_v2_priv *priv = hr_dev->priv; 2479 struct hns_roce_link_table *link_tbl; 2480 u32 pg_shift, size, min_size; 2481 2482 link_tbl = &priv->ext_llm; 2483 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2484 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2485 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2486 2487 /* Alloc data table */ 2488 size = max(size, min_size); 2489 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2490 if (IS_ERR(link_tbl->buf)) 2491 return ERR_PTR(-ENOMEM); 2492 2493 /* Alloc config table */ 2494 size = link_tbl->buf->npages * sizeof(u64); 2495 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2496 &link_tbl->table.map, 2497 GFP_KERNEL); 2498 if (!link_tbl->table.buf) { 2499 hns_roce_buf_free(hr_dev, link_tbl->buf); 2500 return ERR_PTR(-ENOMEM); 2501 } 2502 2503 return link_tbl; 2504 } 2505 2506 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2507 struct hns_roce_link_table *tbl) 2508 { 2509 if (tbl->buf) { 2510 u32 size = tbl->buf->npages * sizeof(u64); 2511 2512 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2513 tbl->table.map); 2514 } 2515 2516 hns_roce_buf_free(hr_dev, tbl->buf); 2517 } 2518 2519 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2520 { 2521 struct hns_roce_link_table *link_tbl; 2522 int ret; 2523 2524 link_tbl = alloc_link_table_buf(hr_dev); 2525 if (IS_ERR(link_tbl)) 2526 return -ENOMEM; 2527 2528 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2529 ret = -EINVAL; 2530 goto err_alloc; 2531 } 2532 2533 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2534 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2535 if (ret) 2536 goto err_alloc; 2537 2538 return 0; 2539 2540 err_alloc: 2541 free_link_table_buf(hr_dev, link_tbl); 2542 return ret; 2543 } 2544 2545 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2546 { 2547 struct hns_roce_v2_priv *priv = hr_dev->priv; 2548 2549 free_link_table_buf(hr_dev, &priv->ext_llm); 2550 } 2551 2552 static void free_dip_list(struct hns_roce_dev *hr_dev) 2553 { 2554 struct hns_roce_dip *hr_dip; 2555 struct hns_roce_dip *tmp; 2556 unsigned long flags; 2557 2558 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2559 2560 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2561 list_del(&hr_dip->node); 2562 kfree(hr_dip); 2563 } 2564 2565 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2566 } 2567 2568 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2569 { 2570 struct hns_roce_v2_priv *priv = hr_dev->priv; 2571 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2572 struct ib_device *ibdev = &hr_dev->ib_dev; 2573 struct hns_roce_pd *hr_pd; 2574 struct ib_pd *pd; 2575 2576 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2577 if (ZERO_OR_NULL_PTR(hr_pd)) 2578 return NULL; 2579 pd = &hr_pd->ibpd; 2580 pd->device = ibdev; 2581 2582 if (hns_roce_alloc_pd(pd, NULL)) { 2583 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2584 kfree(hr_pd); 2585 return NULL; 2586 } 2587 free_mr->rsv_pd = to_hr_pd(pd); 2588 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2589 free_mr->rsv_pd->ibpd.uobject = NULL; 2590 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2591 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2592 2593 return pd; 2594 } 2595 2596 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2597 { 2598 struct hns_roce_v2_priv *priv = hr_dev->priv; 2599 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2600 struct ib_device *ibdev = &hr_dev->ib_dev; 2601 struct ib_cq_init_attr cq_init_attr = {}; 2602 struct hns_roce_cq *hr_cq; 2603 struct ib_cq *cq; 2604 2605 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2606 2607 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2608 if (ZERO_OR_NULL_PTR(hr_cq)) 2609 return NULL; 2610 2611 cq = &hr_cq->ib_cq; 2612 cq->device = ibdev; 2613 2614 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2615 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2616 kfree(hr_cq); 2617 return NULL; 2618 } 2619 free_mr->rsv_cq = to_hr_cq(cq); 2620 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2621 free_mr->rsv_cq->ib_cq.uobject = NULL; 2622 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2623 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2624 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2625 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2626 2627 return cq; 2628 } 2629 2630 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2631 struct ib_qp_init_attr *init_attr, int i) 2632 { 2633 struct hns_roce_v2_priv *priv = hr_dev->priv; 2634 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2635 struct ib_device *ibdev = &hr_dev->ib_dev; 2636 struct hns_roce_qp *hr_qp; 2637 struct ib_qp *qp; 2638 int ret; 2639 2640 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2641 if (ZERO_OR_NULL_PTR(hr_qp)) 2642 return -ENOMEM; 2643 2644 qp = &hr_qp->ibqp; 2645 qp->device = ibdev; 2646 2647 ret = hns_roce_create_qp(qp, init_attr, NULL); 2648 if (ret) { 2649 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2650 kfree(hr_qp); 2651 return ret; 2652 } 2653 2654 free_mr->rsv_qp[i] = hr_qp; 2655 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2656 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2657 2658 return 0; 2659 } 2660 2661 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2662 { 2663 struct hns_roce_v2_priv *priv = hr_dev->priv; 2664 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2665 struct ib_qp *qp; 2666 int i; 2667 2668 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2669 if (free_mr->rsv_qp[i]) { 2670 qp = &free_mr->rsv_qp[i]->ibqp; 2671 hns_roce_v2_destroy_qp(qp, NULL); 2672 kfree(free_mr->rsv_qp[i]); 2673 free_mr->rsv_qp[i] = NULL; 2674 } 2675 } 2676 2677 if (free_mr->rsv_cq) { 2678 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2679 kfree(free_mr->rsv_cq); 2680 free_mr->rsv_cq = NULL; 2681 } 2682 2683 if (free_mr->rsv_pd) { 2684 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2685 kfree(free_mr->rsv_pd); 2686 free_mr->rsv_pd = NULL; 2687 } 2688 } 2689 2690 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2691 { 2692 struct hns_roce_v2_priv *priv = hr_dev->priv; 2693 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2694 struct ib_qp_init_attr qp_init_attr = {}; 2695 struct ib_pd *pd; 2696 struct ib_cq *cq; 2697 int ret; 2698 int i; 2699 2700 pd = free_mr_init_pd(hr_dev); 2701 if (!pd) 2702 return -ENOMEM; 2703 2704 cq = free_mr_init_cq(hr_dev); 2705 if (!cq) { 2706 ret = -ENOMEM; 2707 goto create_failed_cq; 2708 } 2709 2710 qp_init_attr.qp_type = IB_QPT_RC; 2711 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2712 qp_init_attr.send_cq = cq; 2713 qp_init_attr.recv_cq = cq; 2714 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2715 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2716 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2717 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2718 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2719 2720 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2721 if (ret) 2722 goto create_failed_qp; 2723 } 2724 2725 return 0; 2726 2727 create_failed_qp: 2728 hns_roce_destroy_cq(cq, NULL); 2729 kfree(cq); 2730 2731 create_failed_cq: 2732 hns_roce_dealloc_pd(pd, NULL); 2733 kfree(pd); 2734 2735 return ret; 2736 } 2737 2738 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2739 struct ib_qp_attr *attr, int sl_num) 2740 { 2741 struct hns_roce_v2_priv *priv = hr_dev->priv; 2742 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2743 struct ib_device *ibdev = &hr_dev->ib_dev; 2744 struct hns_roce_qp *hr_qp; 2745 int loopback; 2746 int mask; 2747 int ret; 2748 2749 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2750 hr_qp->free_mr_en = 1; 2751 hr_qp->ibqp.device = ibdev; 2752 hr_qp->ibqp.qp_type = IB_QPT_RC; 2753 2754 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2755 attr->qp_state = IB_QPS_INIT; 2756 attr->port_num = 1; 2757 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2758 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2759 IB_QPS_INIT, NULL); 2760 if (ret) { 2761 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2762 ret); 2763 return ret; 2764 } 2765 2766 loopback = hr_dev->loop_idc; 2767 /* Set qpc lbi = 1 incidate loopback IO */ 2768 hr_dev->loop_idc = 1; 2769 2770 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2771 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2772 attr->qp_state = IB_QPS_RTR; 2773 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2774 attr->path_mtu = IB_MTU_256; 2775 attr->dest_qp_num = hr_qp->qpn; 2776 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2777 2778 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2779 2780 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2781 IB_QPS_RTR, NULL); 2782 hr_dev->loop_idc = loopback; 2783 if (ret) { 2784 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2785 ret); 2786 return ret; 2787 } 2788 2789 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2790 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2791 attr->qp_state = IB_QPS_RTS; 2792 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2793 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2794 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2795 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2796 IB_QPS_RTS, NULL); 2797 if (ret) 2798 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2799 ret); 2800 2801 return ret; 2802 } 2803 2804 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2805 { 2806 struct hns_roce_v2_priv *priv = hr_dev->priv; 2807 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2808 struct ib_qp_attr attr = {}; 2809 int ret; 2810 int i; 2811 2812 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2813 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2814 rdma_ah_set_port_num(&attr.ah_attr, 1); 2815 2816 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2817 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2818 if (ret) 2819 return ret; 2820 } 2821 2822 return 0; 2823 } 2824 2825 static int free_mr_init(struct hns_roce_dev *hr_dev) 2826 { 2827 struct hns_roce_v2_priv *priv = hr_dev->priv; 2828 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2829 int ret; 2830 2831 mutex_init(&free_mr->mutex); 2832 2833 ret = free_mr_alloc_res(hr_dev); 2834 if (ret) 2835 return ret; 2836 2837 ret = free_mr_modify_qp(hr_dev); 2838 if (ret) 2839 goto err_modify_qp; 2840 2841 return 0; 2842 2843 err_modify_qp: 2844 free_mr_exit(hr_dev); 2845 2846 return ret; 2847 } 2848 2849 static int get_hem_table(struct hns_roce_dev *hr_dev) 2850 { 2851 unsigned int qpc_count; 2852 unsigned int cqc_count; 2853 unsigned int gmv_count; 2854 int ret; 2855 int i; 2856 2857 /* Alloc memory for source address table buffer space chunk */ 2858 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2859 gmv_count++) { 2860 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2861 if (ret) 2862 goto err_gmv_failed; 2863 } 2864 2865 if (hr_dev->is_vf) 2866 return 0; 2867 2868 /* Alloc memory for QPC Timer buffer space chunk */ 2869 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2870 qpc_count++) { 2871 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2872 qpc_count); 2873 if (ret) { 2874 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2875 goto err_qpc_timer_failed; 2876 } 2877 } 2878 2879 /* Alloc memory for CQC Timer buffer space chunk */ 2880 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2881 cqc_count++) { 2882 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2883 cqc_count); 2884 if (ret) { 2885 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2886 goto err_cqc_timer_failed; 2887 } 2888 } 2889 2890 return 0; 2891 2892 err_cqc_timer_failed: 2893 for (i = 0; i < cqc_count; i++) 2894 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2895 2896 err_qpc_timer_failed: 2897 for (i = 0; i < qpc_count; i++) 2898 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2899 2900 err_gmv_failed: 2901 for (i = 0; i < gmv_count; i++) 2902 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2903 2904 return ret; 2905 } 2906 2907 static void put_hem_table(struct hns_roce_dev *hr_dev) 2908 { 2909 int i; 2910 2911 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2912 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2913 2914 if (hr_dev->is_vf) 2915 return; 2916 2917 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2918 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2919 2920 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2921 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2922 } 2923 2924 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2925 { 2926 int ret; 2927 2928 /* The hns ROCEE requires the extdb info to be cleared before using */ 2929 ret = hns_roce_clear_extdb_list_info(hr_dev); 2930 if (ret) 2931 return ret; 2932 2933 ret = get_hem_table(hr_dev); 2934 if (ret) 2935 return ret; 2936 2937 if (hr_dev->is_vf) 2938 return 0; 2939 2940 ret = hns_roce_init_link_table(hr_dev); 2941 if (ret) { 2942 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2943 goto err_llm_init_failed; 2944 } 2945 2946 return 0; 2947 2948 err_llm_init_failed: 2949 put_hem_table(hr_dev); 2950 2951 return ret; 2952 } 2953 2954 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2955 { 2956 hns_roce_function_clear(hr_dev); 2957 2958 if (!hr_dev->is_vf) 2959 hns_roce_free_link_table(hr_dev); 2960 2961 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2962 free_dip_list(hr_dev); 2963 } 2964 2965 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2966 struct hns_roce_mbox_msg *mbox_msg) 2967 { 2968 struct hns_roce_cmq_desc desc; 2969 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2970 2971 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2972 2973 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2974 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2975 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2976 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2977 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2978 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2979 mbox_msg->token); 2980 2981 return hns_roce_cmq_send(hr_dev, &desc, 1); 2982 } 2983 2984 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2985 u8 *complete_status) 2986 { 2987 struct hns_roce_mbox_status *mb_st; 2988 struct hns_roce_cmq_desc desc; 2989 unsigned long end; 2990 int ret = -EBUSY; 2991 u32 status; 2992 bool busy; 2993 2994 mb_st = (struct hns_roce_mbox_status *)desc.data; 2995 end = msecs_to_jiffies(timeout) + jiffies; 2996 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2997 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2998 return -EIO; 2999 3000 status = 0; 3001 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 3002 true); 3003 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 3004 if (!ret) { 3005 status = le32_to_cpu(mb_st->mb_status_hw_run); 3006 /* No pending message exists in ROCEE mbox. */ 3007 if (!(status & MB_ST_HW_RUN_M)) 3008 break; 3009 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3010 break; 3011 } 3012 3013 if (time_after(jiffies, end)) { 3014 dev_err_ratelimited(hr_dev->dev, 3015 "failed to wait mbox status 0x%x\n", 3016 status); 3017 return -ETIMEDOUT; 3018 } 3019 3020 cond_resched(); 3021 ret = -EBUSY; 3022 } 3023 3024 if (!ret) { 3025 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3026 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3027 /* Ignore all errors if the mbox is unavailable. */ 3028 ret = 0; 3029 *complete_status = MB_ST_COMPLETE_M; 3030 } 3031 3032 return ret; 3033 } 3034 3035 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3036 struct hns_roce_mbox_msg *mbox_msg) 3037 { 3038 u8 status = 0; 3039 int ret; 3040 3041 /* Waiting for the mbox to be idle */ 3042 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3043 &status); 3044 if (unlikely(ret)) { 3045 dev_err_ratelimited(hr_dev->dev, 3046 "failed to check post mbox status = 0x%x, ret = %d.\n", 3047 status, ret); 3048 return ret; 3049 } 3050 3051 /* Post new message to mbox */ 3052 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3053 if (ret) 3054 dev_err_ratelimited(hr_dev->dev, 3055 "failed to post mailbox, ret = %d.\n", ret); 3056 3057 return ret; 3058 } 3059 3060 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3061 { 3062 u8 status = 0; 3063 int ret; 3064 3065 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3066 &status); 3067 if (!ret) { 3068 if (status != MB_ST_COMPLETE_SUCC) 3069 return -EBUSY; 3070 } else { 3071 dev_err_ratelimited(hr_dev->dev, 3072 "failed to check mbox status = 0x%x, ret = %d.\n", 3073 status, ret); 3074 } 3075 3076 return ret; 3077 } 3078 3079 static void copy_gid(void *dest, const union ib_gid *gid) 3080 { 3081 #define GID_SIZE 4 3082 const union ib_gid *src = gid; 3083 __le32 (*p)[GID_SIZE] = dest; 3084 int i; 3085 3086 if (!gid) 3087 src = &zgid; 3088 3089 for (i = 0; i < GID_SIZE; i++) 3090 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3091 } 3092 3093 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3094 int gid_index, const union ib_gid *gid, 3095 enum hns_roce_sgid_type sgid_type) 3096 { 3097 struct hns_roce_cmq_desc desc; 3098 struct hns_roce_cfg_sgid_tb *sgid_tb = 3099 (struct hns_roce_cfg_sgid_tb *)desc.data; 3100 3101 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3102 3103 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3104 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3105 3106 copy_gid(&sgid_tb->vf_sgid_l, gid); 3107 3108 return hns_roce_cmq_send(hr_dev, &desc, 1); 3109 } 3110 3111 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3112 int gid_index, const union ib_gid *gid, 3113 enum hns_roce_sgid_type sgid_type, 3114 const struct ib_gid_attr *attr) 3115 { 3116 struct hns_roce_cmq_desc desc[2]; 3117 struct hns_roce_cfg_gmv_tb_a *tb_a = 3118 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3119 struct hns_roce_cfg_gmv_tb_b *tb_b = 3120 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3121 3122 u16 vlan_id = VLAN_CFI_MASK; 3123 u8 mac[ETH_ALEN] = {}; 3124 int ret; 3125 3126 if (gid) { 3127 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3128 if (ret) 3129 return ret; 3130 } 3131 3132 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3133 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3134 3135 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3136 3137 copy_gid(&tb_a->vf_sgid_l, gid); 3138 3139 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3140 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3141 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3142 3143 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3144 3145 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3146 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3147 3148 return hns_roce_cmq_send(hr_dev, desc, 2); 3149 } 3150 3151 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3152 const union ib_gid *gid, 3153 const struct ib_gid_attr *attr) 3154 { 3155 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3156 int ret; 3157 3158 if (gid) { 3159 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3160 if (ipv6_addr_v4mapped((void *)gid)) 3161 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3162 else 3163 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3164 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3165 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3166 } 3167 } 3168 3169 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3170 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3171 else 3172 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3173 3174 if (ret) 3175 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3176 ret); 3177 3178 return ret; 3179 } 3180 3181 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3182 const u8 *addr) 3183 { 3184 struct hns_roce_cmq_desc desc; 3185 struct hns_roce_cfg_smac_tb *smac_tb = 3186 (struct hns_roce_cfg_smac_tb *)desc.data; 3187 u16 reg_smac_h; 3188 u32 reg_smac_l; 3189 3190 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3191 3192 reg_smac_l = *(u32 *)(&addr[0]); 3193 reg_smac_h = *(u16 *)(&addr[4]); 3194 3195 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3196 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3197 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3198 3199 return hns_roce_cmq_send(hr_dev, &desc, 1); 3200 } 3201 3202 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3203 struct hns_roce_v2_mpt_entry *mpt_entry, 3204 struct hns_roce_mr *mr) 3205 { 3206 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3207 struct ib_device *ibdev = &hr_dev->ib_dev; 3208 dma_addr_t pbl_ba; 3209 int i, count; 3210 3211 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3212 min_t(int, ARRAY_SIZE(pages), mr->npages), 3213 &pbl_ba); 3214 if (count < 1) { 3215 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3216 count); 3217 return -ENOBUFS; 3218 } 3219 3220 /* Aligned to the hardware address access unit */ 3221 for (i = 0; i < count; i++) 3222 pages[i] >>= 6; 3223 3224 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3225 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3226 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3227 3228 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3229 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3230 3231 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3232 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3233 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3234 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3235 3236 return 0; 3237 } 3238 3239 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3240 void *mb_buf, struct hns_roce_mr *mr) 3241 { 3242 struct hns_roce_v2_mpt_entry *mpt_entry; 3243 3244 mpt_entry = mb_buf; 3245 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3246 3247 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3248 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3249 3250 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3251 mr->access & IB_ACCESS_MW_BIND); 3252 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3253 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3254 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3255 mr->access & IB_ACCESS_REMOTE_READ); 3256 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3257 mr->access & IB_ACCESS_REMOTE_WRITE); 3258 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3259 mr->access & IB_ACCESS_LOCAL_WRITE); 3260 3261 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3262 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3263 mpt_entry->lkey = cpu_to_le32(mr->key); 3264 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3265 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3266 3267 if (mr->type != MR_TYPE_MR) 3268 hr_reg_enable(mpt_entry, MPT_PA); 3269 3270 if (mr->type == MR_TYPE_DMA) 3271 return 0; 3272 3273 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3274 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3275 3276 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3277 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3278 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3279 3280 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3281 } 3282 3283 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3284 struct hns_roce_mr *mr, int flags, 3285 void *mb_buf) 3286 { 3287 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3288 u32 mr_access_flags = mr->access; 3289 int ret = 0; 3290 3291 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3292 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3293 3294 if (flags & IB_MR_REREG_ACCESS) { 3295 hr_reg_write(mpt_entry, MPT_BIND_EN, 3296 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3297 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3298 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3299 hr_reg_write(mpt_entry, MPT_RR_EN, 3300 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3301 hr_reg_write(mpt_entry, MPT_RW_EN, 3302 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3303 hr_reg_write(mpt_entry, MPT_LW_EN, 3304 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3305 } 3306 3307 if (flags & IB_MR_REREG_TRANS) { 3308 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3309 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3310 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3311 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3312 3313 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3314 } 3315 3316 return ret; 3317 } 3318 3319 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3320 void *mb_buf, struct hns_roce_mr *mr) 3321 { 3322 struct ib_device *ibdev = &hr_dev->ib_dev; 3323 struct hns_roce_v2_mpt_entry *mpt_entry; 3324 dma_addr_t pbl_ba = 0; 3325 3326 mpt_entry = mb_buf; 3327 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3328 3329 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3330 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3331 return -ENOBUFS; 3332 } 3333 3334 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3335 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3336 3337 hr_reg_enable(mpt_entry, MPT_RA_EN); 3338 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3339 3340 hr_reg_enable(mpt_entry, MPT_FRE); 3341 hr_reg_clear(mpt_entry, MPT_MR_MW); 3342 hr_reg_enable(mpt_entry, MPT_BPD); 3343 hr_reg_clear(mpt_entry, MPT_PA); 3344 3345 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3346 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3347 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3348 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3349 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3350 3351 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3352 3353 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3354 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3355 3356 return 0; 3357 } 3358 3359 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3360 { 3361 struct hns_roce_v2_mpt_entry *mpt_entry; 3362 3363 mpt_entry = mb_buf; 3364 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3365 3366 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3367 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3368 3369 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3370 hr_reg_enable(mpt_entry, MPT_LW_EN); 3371 3372 hr_reg_enable(mpt_entry, MPT_MR_MW); 3373 hr_reg_enable(mpt_entry, MPT_BPD); 3374 hr_reg_clear(mpt_entry, MPT_PA); 3375 hr_reg_write(mpt_entry, MPT_BQP, 3376 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3377 3378 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3379 3380 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3381 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3382 mw->pbl_hop_num); 3383 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3384 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3385 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3386 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3387 3388 return 0; 3389 } 3390 3391 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3392 { 3393 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3394 struct ib_device *ibdev = &hr_dev->ib_dev; 3395 const struct ib_send_wr *bad_wr; 3396 struct ib_rdma_wr rdma_wr = {}; 3397 struct ib_send_wr *send_wr; 3398 int ret; 3399 3400 send_wr = &rdma_wr.wr; 3401 send_wr->opcode = IB_WR_RDMA_WRITE; 3402 3403 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3404 if (ret) { 3405 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3406 ret); 3407 return ret; 3408 } 3409 3410 return 0; 3411 } 3412 3413 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3414 struct ib_wc *wc); 3415 3416 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3417 { 3418 struct hns_roce_v2_priv *priv = hr_dev->priv; 3419 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3420 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3421 struct ib_device *ibdev = &hr_dev->ib_dev; 3422 struct hns_roce_qp *hr_qp; 3423 unsigned long end; 3424 int cqe_cnt = 0; 3425 int npolled; 3426 int ret; 3427 int i; 3428 3429 /* 3430 * If the device initialization is not complete or in the uninstall 3431 * process, then there is no need to execute free mr. 3432 */ 3433 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3434 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3435 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3436 return; 3437 3438 mutex_lock(&free_mr->mutex); 3439 3440 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3441 hr_qp = free_mr->rsv_qp[i]; 3442 3443 ret = free_mr_post_send_lp_wqe(hr_qp); 3444 if (ret) { 3445 ibdev_err(ibdev, 3446 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3447 hr_qp->qpn, ret); 3448 break; 3449 } 3450 3451 cqe_cnt++; 3452 } 3453 3454 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3455 while (cqe_cnt) { 3456 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3457 if (npolled < 0) { 3458 ibdev_err(ibdev, 3459 "failed to poll cqe for free mr, remain %d cqe.\n", 3460 cqe_cnt); 3461 goto out; 3462 } 3463 3464 if (time_after(jiffies, end)) { 3465 ibdev_err(ibdev, 3466 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3467 cqe_cnt); 3468 goto out; 3469 } 3470 cqe_cnt -= npolled; 3471 } 3472 3473 out: 3474 mutex_unlock(&free_mr->mutex); 3475 } 3476 3477 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3478 { 3479 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3480 free_mr_send_cmd_to_hw(hr_dev); 3481 } 3482 3483 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3484 { 3485 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3486 } 3487 3488 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3489 { 3490 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3491 3492 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3493 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3494 NULL; 3495 } 3496 3497 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3498 struct hns_roce_cq *hr_cq) 3499 { 3500 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3501 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3502 } else { 3503 struct hns_roce_v2_db cq_db = {}; 3504 3505 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3506 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3507 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3508 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3509 3510 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3511 } 3512 } 3513 3514 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3515 struct hns_roce_srq *srq) 3516 { 3517 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3518 struct hns_roce_v2_cqe *cqe, *dest; 3519 u32 prod_index; 3520 int nfreed = 0; 3521 int wqe_index; 3522 u8 owner_bit; 3523 3524 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3525 ++prod_index) { 3526 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3527 break; 3528 } 3529 3530 /* 3531 * Now backwards through the CQ, removing CQ entries 3532 * that match our QP by overwriting them with next entries. 3533 */ 3534 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3535 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3536 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3537 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3538 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3539 hns_roce_free_srq_wqe(srq, wqe_index); 3540 } 3541 ++nfreed; 3542 } else if (nfreed) { 3543 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3544 hr_cq->ib_cq.cqe); 3545 owner_bit = hr_reg_read(dest, CQE_OWNER); 3546 memcpy(dest, cqe, hr_cq->cqe_size); 3547 hr_reg_write(dest, CQE_OWNER, owner_bit); 3548 } 3549 } 3550 3551 if (nfreed) { 3552 hr_cq->cons_index += nfreed; 3553 update_cq_db(hr_dev, hr_cq); 3554 } 3555 } 3556 3557 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3558 struct hns_roce_srq *srq) 3559 { 3560 spin_lock_irq(&hr_cq->lock); 3561 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3562 spin_unlock_irq(&hr_cq->lock); 3563 } 3564 3565 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3566 struct hns_roce_cq *hr_cq, void *mb_buf, 3567 u64 *mtts, dma_addr_t dma_handle) 3568 { 3569 struct hns_roce_v2_cq_context *cq_context; 3570 3571 cq_context = mb_buf; 3572 memset(cq_context, 0, sizeof(*cq_context)); 3573 3574 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3575 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3576 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3577 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3578 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3579 3580 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3581 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3582 3583 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3584 hr_reg_enable(cq_context, CQC_STASH); 3585 3586 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3587 to_hr_hw_page_addr(mtts[0])); 3588 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3589 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3590 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3591 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3592 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3593 to_hr_hw_page_addr(mtts[1])); 3594 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3595 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3596 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3597 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3598 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3599 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3600 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3601 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3602 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3603 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3604 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3605 ((u32)hr_cq->db.dma) >> 1); 3606 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3607 hr_cq->db.dma >> 32); 3608 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3609 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3610 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3611 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3612 } 3613 3614 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3615 enum ib_cq_notify_flags flags) 3616 { 3617 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3618 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3619 struct hns_roce_v2_db cq_db = {}; 3620 u32 notify_flag; 3621 3622 /* 3623 * flags = 0, then notify_flag : next 3624 * flags = 1, then notify flag : solocited 3625 */ 3626 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3627 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3628 3629 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3630 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3631 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3632 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3633 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3634 3635 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3636 3637 return 0; 3638 } 3639 3640 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3641 int num_entries, struct ib_wc *wc) 3642 { 3643 unsigned int left; 3644 int npolled = 0; 3645 3646 left = wq->head - wq->tail; 3647 if (left == 0) 3648 return 0; 3649 3650 left = min_t(unsigned int, (unsigned int)num_entries, left); 3651 while (npolled < left) { 3652 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3653 wc->status = IB_WC_WR_FLUSH_ERR; 3654 wc->vendor_err = 0; 3655 wc->qp = &hr_qp->ibqp; 3656 3657 wq->tail++; 3658 wc++; 3659 npolled++; 3660 } 3661 3662 return npolled; 3663 } 3664 3665 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3666 struct ib_wc *wc) 3667 { 3668 struct hns_roce_qp *hr_qp; 3669 int npolled = 0; 3670 3671 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3672 npolled += sw_comp(hr_qp, &hr_qp->sq, 3673 num_entries - npolled, wc + npolled); 3674 if (npolled >= num_entries) 3675 goto out; 3676 } 3677 3678 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3679 npolled += sw_comp(hr_qp, &hr_qp->rq, 3680 num_entries - npolled, wc + npolled); 3681 if (npolled >= num_entries) 3682 goto out; 3683 } 3684 3685 out: 3686 return npolled; 3687 } 3688 3689 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3690 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3691 struct ib_wc *wc) 3692 { 3693 static const struct { 3694 u32 cqe_status; 3695 enum ib_wc_status wc_status; 3696 } map[] = { 3697 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3698 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3699 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3700 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3701 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3702 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3703 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3704 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3705 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3706 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3707 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3708 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3709 IB_WC_RETRY_EXC_ERR }, 3710 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3711 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3712 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3713 }; 3714 3715 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3716 int i; 3717 3718 wc->status = IB_WC_GENERAL_ERR; 3719 for (i = 0; i < ARRAY_SIZE(map); i++) 3720 if (cqe_status == map[i].cqe_status) { 3721 wc->status = map[i].wc_status; 3722 break; 3723 } 3724 3725 if (likely(wc->status == IB_WC_SUCCESS || 3726 wc->status == IB_WC_WR_FLUSH_ERR)) 3727 return; 3728 3729 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3730 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3731 cq->cqe_size, false); 3732 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3733 3734 /* 3735 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3736 * the standard protocol, the driver must ignore it and needn't to set 3737 * the QP to an error state. 3738 */ 3739 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3740 return; 3741 3742 flush_cqe(hr_dev, qp); 3743 } 3744 3745 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3746 struct hns_roce_qp **cur_qp) 3747 { 3748 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3749 struct hns_roce_qp *hr_qp = *cur_qp; 3750 u32 qpn; 3751 3752 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3753 3754 if (!hr_qp || qpn != hr_qp->qpn) { 3755 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3756 if (unlikely(!hr_qp)) { 3757 ibdev_err(&hr_dev->ib_dev, 3758 "CQ %06lx with entry for unknown QPN %06x\n", 3759 hr_cq->cqn, qpn); 3760 return -EINVAL; 3761 } 3762 *cur_qp = hr_qp; 3763 } 3764 3765 return 0; 3766 } 3767 3768 /* 3769 * mapped-value = 1 + real-value 3770 * The ib wc opcode's real value is start from 0, In order to distinguish 3771 * between initialized and uninitialized map values, we plus 1 to the actual 3772 * value when defining the mapping, so that the validity can be identified by 3773 * checking whether the mapped value is greater than 0. 3774 */ 3775 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3776 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3777 3778 static const u32 wc_send_op_map[] = { 3779 HR_WC_OP_MAP(SEND, SEND), 3780 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3781 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3782 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3783 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3784 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3785 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3786 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3787 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3788 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3789 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3790 HR_WC_OP_MAP(BIND_MW, REG_MR), 3791 }; 3792 3793 static int to_ib_wc_send_op(u32 hr_opcode) 3794 { 3795 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3796 return -EINVAL; 3797 3798 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3799 -EINVAL; 3800 } 3801 3802 static const u32 wc_recv_op_map[] = { 3803 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3804 HR_WC_OP_MAP(SEND, RECV), 3805 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3806 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3807 }; 3808 3809 static int to_ib_wc_recv_op(u32 hr_opcode) 3810 { 3811 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3812 return -EINVAL; 3813 3814 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3815 -EINVAL; 3816 } 3817 3818 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3819 { 3820 u32 hr_opcode; 3821 int ib_opcode; 3822 3823 wc->wc_flags = 0; 3824 3825 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3826 switch (hr_opcode) { 3827 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3828 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3829 break; 3830 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3831 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3832 wc->wc_flags |= IB_WC_WITH_IMM; 3833 break; 3834 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3835 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3836 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3837 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3838 wc->byte_len = 8; 3839 break; 3840 default: 3841 break; 3842 } 3843 3844 ib_opcode = to_ib_wc_send_op(hr_opcode); 3845 if (ib_opcode < 0) 3846 wc->status = IB_WC_GENERAL_ERR; 3847 else 3848 wc->opcode = ib_opcode; 3849 } 3850 3851 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3852 { 3853 u32 hr_opcode; 3854 int ib_opcode; 3855 3856 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3857 3858 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3859 switch (hr_opcode) { 3860 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3861 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3862 wc->wc_flags = IB_WC_WITH_IMM; 3863 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3864 break; 3865 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3866 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3867 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3868 break; 3869 default: 3870 wc->wc_flags = 0; 3871 } 3872 3873 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3874 if (ib_opcode < 0) 3875 wc->status = IB_WC_GENERAL_ERR; 3876 else 3877 wc->opcode = ib_opcode; 3878 3879 wc->sl = hr_reg_read(cqe, CQE_SL); 3880 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3881 wc->slid = 0; 3882 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3883 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3884 wc->pkey_index = 0; 3885 3886 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3887 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3888 wc->wc_flags |= IB_WC_WITH_VLAN; 3889 } else { 3890 wc->vlan_id = 0xffff; 3891 } 3892 3893 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3894 3895 return 0; 3896 } 3897 3898 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3899 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3900 { 3901 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3902 struct hns_roce_qp *qp = *cur_qp; 3903 struct hns_roce_srq *srq = NULL; 3904 struct hns_roce_v2_cqe *cqe; 3905 struct hns_roce_wq *wq; 3906 int is_send; 3907 u16 wqe_idx; 3908 int ret; 3909 3910 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3911 if (!cqe) 3912 return -EAGAIN; 3913 3914 ++hr_cq->cons_index; 3915 /* Memory barrier */ 3916 rmb(); 3917 3918 ret = get_cur_qp(hr_cq, cqe, &qp); 3919 if (ret) 3920 return ret; 3921 3922 wc->qp = &qp->ibqp; 3923 wc->vendor_err = 0; 3924 3925 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3926 3927 is_send = !hr_reg_read(cqe, CQE_S_R); 3928 if (is_send) { 3929 wq = &qp->sq; 3930 3931 /* If sg_signal_bit is set, tail pointer will be updated to 3932 * the WQE corresponding to the current CQE. 3933 */ 3934 if (qp->sq_signal_bits) 3935 wq->tail += (wqe_idx - (u16)wq->tail) & 3936 (wq->wqe_cnt - 1); 3937 3938 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3939 ++wq->tail; 3940 3941 fill_send_wc(wc, cqe); 3942 } else { 3943 if (qp->ibqp.srq) { 3944 srq = to_hr_srq(qp->ibqp.srq); 3945 wc->wr_id = srq->wrid[wqe_idx]; 3946 hns_roce_free_srq_wqe(srq, wqe_idx); 3947 } else { 3948 wq = &qp->rq; 3949 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3950 ++wq->tail; 3951 } 3952 3953 ret = fill_recv_wc(wc, cqe); 3954 } 3955 3956 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3957 if (unlikely(wc->status != IB_WC_SUCCESS)) 3958 return 0; 3959 3960 return ret; 3961 } 3962 3963 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3964 struct ib_wc *wc) 3965 { 3966 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3967 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3968 struct hns_roce_qp *cur_qp = NULL; 3969 unsigned long flags; 3970 int npolled; 3971 3972 spin_lock_irqsave(&hr_cq->lock, flags); 3973 3974 /* 3975 * When the device starts to reset, the state is RST_DOWN. At this time, 3976 * there may still be some valid CQEs in the hardware that are not 3977 * polled. Therefore, it is not allowed to switch to the software mode 3978 * immediately. When the state changes to UNINIT, CQE no longer exists 3979 * in the hardware, and then switch to software mode. 3980 */ 3981 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3982 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3983 goto out; 3984 } 3985 3986 for (npolled = 0; npolled < num_entries; ++npolled) { 3987 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3988 break; 3989 } 3990 3991 if (npolled) 3992 update_cq_db(hr_dev, hr_cq); 3993 3994 out: 3995 spin_unlock_irqrestore(&hr_cq->lock, flags); 3996 3997 return npolled; 3998 } 3999 4000 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 4001 u32 step_idx, u8 *mbox_cmd) 4002 { 4003 u8 cmd; 4004 4005 switch (type) { 4006 case HEM_TYPE_QPC: 4007 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 4008 break; 4009 case HEM_TYPE_MTPT: 4010 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 4011 break; 4012 case HEM_TYPE_CQC: 4013 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 4014 break; 4015 case HEM_TYPE_SRQC: 4016 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 4017 break; 4018 case HEM_TYPE_SCCC: 4019 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4020 break; 4021 case HEM_TYPE_QPC_TIMER: 4022 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4023 break; 4024 case HEM_TYPE_CQC_TIMER: 4025 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4026 break; 4027 default: 4028 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4029 return -EINVAL; 4030 } 4031 4032 *mbox_cmd = cmd + step_idx; 4033 4034 return 0; 4035 } 4036 4037 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4038 dma_addr_t base_addr) 4039 { 4040 struct hns_roce_cmq_desc desc; 4041 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4042 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4043 u64 addr = to_hr_hw_page_addr(base_addr); 4044 4045 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4046 4047 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4048 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4049 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4050 4051 return hns_roce_cmq_send(hr_dev, &desc, 1); 4052 } 4053 4054 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4055 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4056 { 4057 int ret; 4058 u8 cmd; 4059 4060 if (unlikely(hem_type == HEM_TYPE_GMV)) 4061 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4062 4063 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4064 return 0; 4065 4066 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4067 if (ret < 0) 4068 return ret; 4069 4070 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4071 } 4072 4073 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4074 struct hns_roce_hem_table *table, int obj, 4075 u32 step_idx) 4076 { 4077 struct hns_roce_hem_iter iter; 4078 struct hns_roce_hem_mhop mhop; 4079 struct hns_roce_hem *hem; 4080 unsigned long mhop_obj = obj; 4081 int i, j, k; 4082 int ret = 0; 4083 u64 hem_idx = 0; 4084 u64 l1_idx = 0; 4085 u64 bt_ba = 0; 4086 u32 chunk_ba_num; 4087 u32 hop_num; 4088 4089 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4090 return 0; 4091 4092 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4093 i = mhop.l0_idx; 4094 j = mhop.l1_idx; 4095 k = mhop.l2_idx; 4096 hop_num = mhop.hop_num; 4097 chunk_ba_num = mhop.bt_chunk_size / 8; 4098 4099 if (hop_num == 2) { 4100 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4101 k; 4102 l1_idx = i * chunk_ba_num + j; 4103 } else if (hop_num == 1) { 4104 hem_idx = i * chunk_ba_num + j; 4105 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4106 hem_idx = i; 4107 } 4108 4109 if (table->type == HEM_TYPE_SCCC) 4110 obj = mhop.l0_idx; 4111 4112 if (check_whether_last_step(hop_num, step_idx)) { 4113 hem = table->hem[hem_idx]; 4114 for (hns_roce_hem_first(hem, &iter); 4115 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4116 bt_ba = hns_roce_hem_addr(&iter); 4117 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4118 step_idx); 4119 } 4120 } else { 4121 if (step_idx == 0) 4122 bt_ba = table->bt_l0_dma_addr[i]; 4123 else if (step_idx == 1 && hop_num == 2) 4124 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4125 4126 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4127 } 4128 4129 return ret; 4130 } 4131 4132 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4133 struct hns_roce_hem_table *table, 4134 int tag, u32 step_idx) 4135 { 4136 struct hns_roce_cmd_mailbox *mailbox; 4137 struct device *dev = hr_dev->dev; 4138 u8 cmd = 0xff; 4139 int ret; 4140 4141 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4142 return 0; 4143 4144 switch (table->type) { 4145 case HEM_TYPE_QPC: 4146 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4147 break; 4148 case HEM_TYPE_MTPT: 4149 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4150 break; 4151 case HEM_TYPE_CQC: 4152 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4153 break; 4154 case HEM_TYPE_SRQC: 4155 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4156 break; 4157 case HEM_TYPE_SCCC: 4158 case HEM_TYPE_QPC_TIMER: 4159 case HEM_TYPE_CQC_TIMER: 4160 case HEM_TYPE_GMV: 4161 return 0; 4162 default: 4163 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4164 table->type); 4165 return 0; 4166 } 4167 4168 cmd += step_idx; 4169 4170 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4171 if (IS_ERR(mailbox)) 4172 return PTR_ERR(mailbox); 4173 4174 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4175 4176 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4177 return ret; 4178 } 4179 4180 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4181 struct hns_roce_v2_qp_context *context, 4182 struct hns_roce_v2_qp_context *qpc_mask, 4183 struct hns_roce_qp *hr_qp) 4184 { 4185 struct hns_roce_cmd_mailbox *mailbox; 4186 int qpc_size; 4187 int ret; 4188 4189 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4190 if (IS_ERR(mailbox)) 4191 return PTR_ERR(mailbox); 4192 4193 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4194 qpc_size = hr_dev->caps.qpc_sz; 4195 memcpy(mailbox->buf, context, qpc_size); 4196 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4197 4198 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4199 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4200 4201 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4202 4203 return ret; 4204 } 4205 4206 static void set_access_flags(struct hns_roce_qp *hr_qp, 4207 struct hns_roce_v2_qp_context *context, 4208 struct hns_roce_v2_qp_context *qpc_mask, 4209 const struct ib_qp_attr *attr, int attr_mask) 4210 { 4211 u8 dest_rd_atomic; 4212 u32 access_flags; 4213 4214 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4215 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4216 4217 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4218 attr->qp_access_flags : hr_qp->atomic_rd_en; 4219 4220 if (!dest_rd_atomic) 4221 access_flags &= IB_ACCESS_REMOTE_WRITE; 4222 4223 hr_reg_write_bool(context, QPC_RRE, 4224 access_flags & IB_ACCESS_REMOTE_READ); 4225 hr_reg_clear(qpc_mask, QPC_RRE); 4226 4227 hr_reg_write_bool(context, QPC_RWE, 4228 access_flags & IB_ACCESS_REMOTE_WRITE); 4229 hr_reg_clear(qpc_mask, QPC_RWE); 4230 4231 hr_reg_write_bool(context, QPC_ATE, 4232 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4233 hr_reg_clear(qpc_mask, QPC_ATE); 4234 hr_reg_write_bool(context, QPC_EXT_ATE, 4235 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4236 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4237 } 4238 4239 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4240 struct hns_roce_v2_qp_context *context, 4241 struct hns_roce_v2_qp_context *qpc_mask) 4242 { 4243 hr_reg_write(context, QPC_SGE_SHIFT, 4244 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4245 hr_qp->sge.sge_shift)); 4246 4247 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4248 4249 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4250 } 4251 4252 static inline int get_cqn(struct ib_cq *ib_cq) 4253 { 4254 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4255 } 4256 4257 static inline int get_pdn(struct ib_pd *ib_pd) 4258 { 4259 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4260 } 4261 4262 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4263 const struct ib_qp_attr *attr, 4264 struct hns_roce_v2_qp_context *context, 4265 struct hns_roce_v2_qp_context *qpc_mask) 4266 { 4267 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4268 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4269 4270 /* 4271 * In v2 engine, software pass context and context mask to hardware 4272 * when modifying qp. If software need modify some fields in context, 4273 * we should set all bits of the relevant fields in context mask to 4274 * 0 at the same time, else set them to 0x1. 4275 */ 4276 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4277 4278 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4279 4280 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4281 4282 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4283 4284 /* No VLAN need to set 0xFFF */ 4285 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4286 4287 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4288 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4289 4290 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4291 } 4292 4293 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4294 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4295 4296 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4297 hr_reg_enable(context, QPC_OWNER_MODE); 4298 4299 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4300 lower_32_bits(hr_qp->rdb.dma) >> 1); 4301 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4302 upper_32_bits(hr_qp->rdb.dma)); 4303 4304 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4305 4306 if (ibqp->srq) { 4307 hr_reg_enable(context, QPC_SRQ_EN); 4308 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4309 } 4310 4311 hr_reg_enable(context, QPC_FRE); 4312 4313 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4314 4315 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4316 return; 4317 4318 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4319 hr_reg_enable(&context->ext, QPCEX_STASH); 4320 } 4321 4322 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4323 const struct ib_qp_attr *attr, 4324 struct hns_roce_v2_qp_context *context, 4325 struct hns_roce_v2_qp_context *qpc_mask) 4326 { 4327 /* 4328 * In v2 engine, software pass context and context mask to hardware 4329 * when modifying qp. If software need modify some fields in context, 4330 * we should set all bits of the relevant fields in context mask to 4331 * 0 at the same time, else set them to 0x1. 4332 */ 4333 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4334 hr_reg_clear(qpc_mask, QPC_TST); 4335 4336 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4337 hr_reg_clear(qpc_mask, QPC_PD); 4338 4339 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4340 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4341 4342 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4343 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4344 4345 if (ibqp->srq) { 4346 hr_reg_enable(context, QPC_SRQ_EN); 4347 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4348 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4349 hr_reg_clear(qpc_mask, QPC_SRQN); 4350 } 4351 } 4352 4353 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4354 struct hns_roce_qp *hr_qp, 4355 struct hns_roce_v2_qp_context *context, 4356 struct hns_roce_v2_qp_context *qpc_mask) 4357 { 4358 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4359 u64 wqe_sge_ba; 4360 int count; 4361 4362 /* Search qp buf's mtts */ 4363 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4364 MTT_MIN_COUNT, &wqe_sge_ba); 4365 if (hr_qp->rq.wqe_cnt && count < 1) { 4366 ibdev_err(&hr_dev->ib_dev, 4367 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4368 return -EINVAL; 4369 } 4370 4371 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4372 qpc_mask->wqe_sge_ba = 0; 4373 4374 /* 4375 * In v2 engine, software pass context and context mask to hardware 4376 * when modifying qp. If software need modify some fields in context, 4377 * we should set all bits of the relevant fields in context mask to 4378 * 0 at the same time, else set them to 0x1. 4379 */ 4380 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4381 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4382 4383 hr_reg_write(context, QPC_SQ_HOP_NUM, 4384 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4385 hr_qp->sq.wqe_cnt)); 4386 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4387 4388 hr_reg_write(context, QPC_SGE_HOP_NUM, 4389 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4390 hr_qp->sge.sge_cnt)); 4391 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4392 4393 hr_reg_write(context, QPC_RQ_HOP_NUM, 4394 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4395 hr_qp->rq.wqe_cnt)); 4396 4397 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4398 4399 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4400 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4401 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4402 4403 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4404 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4405 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4406 4407 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4408 qpc_mask->rq_cur_blk_addr = 0; 4409 4410 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4411 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4412 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4413 4414 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4415 qpc_mask->rq_nxt_blk_addr = 0; 4416 4417 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4418 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4419 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4420 4421 return 0; 4422 } 4423 4424 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4425 struct hns_roce_qp *hr_qp, 4426 struct hns_roce_v2_qp_context *context, 4427 struct hns_roce_v2_qp_context *qpc_mask) 4428 { 4429 struct ib_device *ibdev = &hr_dev->ib_dev; 4430 u64 sge_cur_blk = 0; 4431 u64 sq_cur_blk = 0; 4432 int count; 4433 4434 /* search qp buf's mtts */ 4435 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4436 if (count < 1) { 4437 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4438 hr_qp->qpn); 4439 return -EINVAL; 4440 } 4441 if (hr_qp->sge.sge_cnt > 0) { 4442 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4443 hr_qp->sge.offset, 4444 &sge_cur_blk, 1, NULL); 4445 if (count < 1) { 4446 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4447 hr_qp->qpn); 4448 return -EINVAL; 4449 } 4450 } 4451 4452 /* 4453 * In v2 engine, software pass context and context mask to hardware 4454 * when modifying qp. If software need modify some fields in context, 4455 * we should set all bits of the relevant fields in context mask to 4456 * 0 at the same time, else set them to 0x1. 4457 */ 4458 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4459 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4460 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4461 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4462 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4463 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4464 4465 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4466 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4467 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4468 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4469 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4470 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4471 4472 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4473 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4474 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4475 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4476 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4477 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4478 4479 return 0; 4480 } 4481 4482 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4483 const struct ib_qp_attr *attr) 4484 { 4485 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4486 return IB_MTU_4096; 4487 4488 return attr->path_mtu; 4489 } 4490 4491 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4492 const struct ib_qp_attr *attr, int attr_mask, 4493 struct hns_roce_v2_qp_context *context, 4494 struct hns_roce_v2_qp_context *qpc_mask, 4495 struct ib_udata *udata) 4496 { 4497 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4498 struct hns_roce_ucontext, ibucontext); 4499 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4500 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4501 struct ib_device *ibdev = &hr_dev->ib_dev; 4502 dma_addr_t trrl_ba; 4503 dma_addr_t irrl_ba; 4504 enum ib_mtu ib_mtu; 4505 const u8 *smac; 4506 u8 lp_pktn_ini; 4507 u64 *mtts; 4508 u8 *dmac; 4509 u32 port; 4510 int mtu; 4511 int ret; 4512 4513 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4514 if (ret) { 4515 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4516 return ret; 4517 } 4518 4519 /* Search IRRL's mtts */ 4520 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4521 hr_qp->qpn, &irrl_ba); 4522 if (!mtts) { 4523 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4524 return -EINVAL; 4525 } 4526 4527 /* Search TRRL's mtts */ 4528 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4529 hr_qp->qpn, &trrl_ba); 4530 if (!mtts) { 4531 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4532 return -EINVAL; 4533 } 4534 4535 if (attr_mask & IB_QP_ALT_PATH) { 4536 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4537 attr_mask); 4538 return -EINVAL; 4539 } 4540 4541 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4542 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4543 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4544 qpc_mask->trrl_ba = 0; 4545 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4546 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4547 4548 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4549 qpc_mask->irrl_ba = 0; 4550 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4551 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4552 4553 hr_reg_enable(context, QPC_RMT_E2E); 4554 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4555 4556 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4557 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4558 4559 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4560 4561 smac = (const u8 *)hr_dev->dev_addr[port]; 4562 dmac = (u8 *)attr->ah_attr.roce.dmac; 4563 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4564 if (ether_addr_equal_unaligned(dmac, smac) || 4565 hr_dev->loop_idc == 0x1) { 4566 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4567 hr_reg_clear(qpc_mask, QPC_LBI); 4568 } 4569 4570 if (attr_mask & IB_QP_DEST_QPN) { 4571 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4572 hr_reg_clear(qpc_mask, QPC_DQPN); 4573 } 4574 4575 memcpy(&context->dmac, dmac, sizeof(u32)); 4576 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4577 qpc_mask->dmac = 0; 4578 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4579 4580 ib_mtu = get_mtu(ibqp, attr); 4581 hr_qp->path_mtu = ib_mtu; 4582 4583 mtu = ib_mtu_enum_to_int(ib_mtu); 4584 if (WARN_ON(mtu <= 0)) 4585 return -EINVAL; 4586 #define MIN_LP_MSG_LEN 1024 4587 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4588 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4589 4590 if (attr_mask & IB_QP_PATH_MTU) { 4591 hr_reg_write(context, QPC_MTU, ib_mtu); 4592 hr_reg_clear(qpc_mask, QPC_MTU); 4593 } 4594 4595 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4596 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4597 4598 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4599 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4600 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4601 4602 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4603 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4604 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4605 4606 context->rq_rnr_timer = 0; 4607 qpc_mask->rq_rnr_timer = 0; 4608 4609 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4610 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4611 4612 /* rocee send 2^lp_sgen_ini segs every time */ 4613 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4614 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4615 4616 if (udata && ibqp->qp_type == IB_QPT_RC && 4617 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4618 hr_reg_write_bool(context, QPC_RQIE, 4619 hr_dev->caps.flags & 4620 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4621 hr_reg_clear(qpc_mask, QPC_RQIE); 4622 } 4623 4624 if (udata && 4625 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4626 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4627 hr_reg_write_bool(context, QPC_CQEIE, 4628 hr_dev->caps.flags & 4629 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4630 hr_reg_clear(qpc_mask, QPC_CQEIE); 4631 4632 hr_reg_write(context, QPC_CQEIS, 0); 4633 hr_reg_clear(qpc_mask, QPC_CQEIS); 4634 } 4635 4636 return 0; 4637 } 4638 4639 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4640 const struct ib_qp_attr *attr, int attr_mask, 4641 struct hns_roce_v2_qp_context *context, 4642 struct hns_roce_v2_qp_context *qpc_mask) 4643 { 4644 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4645 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4646 struct ib_device *ibdev = &hr_dev->ib_dev; 4647 int ret; 4648 4649 /* Not support alternate path and path migration */ 4650 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4651 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4652 return -EINVAL; 4653 } 4654 4655 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4656 if (ret) { 4657 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4658 return ret; 4659 } 4660 4661 /* 4662 * Set some fields in context to zero, Because the default values 4663 * of all fields in context are zero, we need not set them to 0 again. 4664 * but we should set the relevant fields of context mask to 0. 4665 */ 4666 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4667 4668 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4669 4670 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4671 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4672 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4673 4674 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4675 4676 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4677 4678 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4679 4680 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4681 4682 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4683 4684 return 0; 4685 } 4686 4687 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4688 u32 *dip_idx) 4689 { 4690 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4691 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4692 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4693 u32 *head = &hr_dev->qp_table.idx_table.head; 4694 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4695 struct hns_roce_dip *hr_dip; 4696 unsigned long flags; 4697 int ret = 0; 4698 4699 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4700 4701 spare_idx[*tail] = ibqp->qp_num; 4702 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4703 4704 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4705 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4706 *dip_idx = hr_dip->dip_idx; 4707 goto out; 4708 } 4709 } 4710 4711 /* If no dgid is found, a new dip and a mapping between dgid and 4712 * dip_idx will be created. 4713 */ 4714 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4715 if (!hr_dip) { 4716 ret = -ENOMEM; 4717 goto out; 4718 } 4719 4720 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4721 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4722 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4723 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4724 4725 out: 4726 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4727 return ret; 4728 } 4729 4730 enum { 4731 CONG_DCQCN, 4732 CONG_WINDOW, 4733 }; 4734 4735 enum { 4736 UNSUPPORT_CONG_LEVEL, 4737 SUPPORT_CONG_LEVEL, 4738 }; 4739 4740 enum { 4741 CONG_LDCP, 4742 CONG_HC3, 4743 }; 4744 4745 enum { 4746 DIP_INVALID, 4747 DIP_VALID, 4748 }; 4749 4750 enum { 4751 WND_LIMIT, 4752 WND_UNLIMIT, 4753 }; 4754 4755 static int check_cong_type(struct ib_qp *ibqp, 4756 struct hns_roce_congestion_algorithm *cong_alg) 4757 { 4758 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4759 4760 /* different congestion types match different configurations */ 4761 switch (hr_dev->caps.cong_type) { 4762 case CONG_TYPE_DCQCN: 4763 cong_alg->alg_sel = CONG_DCQCN; 4764 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4765 cong_alg->dip_vld = DIP_INVALID; 4766 cong_alg->wnd_mode_sel = WND_LIMIT; 4767 break; 4768 case CONG_TYPE_LDCP: 4769 cong_alg->alg_sel = CONG_WINDOW; 4770 cong_alg->alg_sub_sel = CONG_LDCP; 4771 cong_alg->dip_vld = DIP_INVALID; 4772 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4773 break; 4774 case CONG_TYPE_HC3: 4775 cong_alg->alg_sel = CONG_WINDOW; 4776 cong_alg->alg_sub_sel = CONG_HC3; 4777 cong_alg->dip_vld = DIP_INVALID; 4778 cong_alg->wnd_mode_sel = WND_LIMIT; 4779 break; 4780 case CONG_TYPE_DIP: 4781 cong_alg->alg_sel = CONG_DCQCN; 4782 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4783 cong_alg->dip_vld = DIP_VALID; 4784 cong_alg->wnd_mode_sel = WND_LIMIT; 4785 break; 4786 default: 4787 ibdev_err(&hr_dev->ib_dev, 4788 "error type(%u) for congestion selection.\n", 4789 hr_dev->caps.cong_type); 4790 return -EINVAL; 4791 } 4792 4793 return 0; 4794 } 4795 4796 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4797 struct hns_roce_v2_qp_context *context, 4798 struct hns_roce_v2_qp_context *qpc_mask) 4799 { 4800 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4801 struct hns_roce_congestion_algorithm cong_field; 4802 struct ib_device *ibdev = ibqp->device; 4803 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4804 u32 dip_idx = 0; 4805 int ret; 4806 4807 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4808 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4809 return 0; 4810 4811 ret = check_cong_type(ibqp, &cong_field); 4812 if (ret) 4813 return ret; 4814 4815 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4816 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4817 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4818 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4819 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4820 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4821 cong_field.alg_sub_sel); 4822 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4823 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4824 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4825 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4826 cong_field.wnd_mode_sel); 4827 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4828 4829 /* if dip is disabled, there is no need to set dip idx */ 4830 if (cong_field.dip_vld == 0) 4831 return 0; 4832 4833 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4834 if (ret) { 4835 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4836 return ret; 4837 } 4838 4839 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4840 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4841 4842 return 0; 4843 } 4844 4845 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4846 const struct ib_qp_attr *attr, 4847 int attr_mask, 4848 struct hns_roce_v2_qp_context *context, 4849 struct hns_roce_v2_qp_context *qpc_mask) 4850 { 4851 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4852 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4853 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4854 struct ib_device *ibdev = &hr_dev->ib_dev; 4855 const struct ib_gid_attr *gid_attr = NULL; 4856 int is_roce_protocol; 4857 u16 vlan_id = 0xffff; 4858 bool is_udp = false; 4859 u8 ib_port; 4860 u8 hr_port; 4861 int ret; 4862 4863 /* 4864 * If free_mr_en of qp is set, it means that this qp comes from 4865 * free mr. This qp will perform the loopback operation. 4866 * In the loopback scenario, only sl needs to be set. 4867 */ 4868 if (hr_qp->free_mr_en) { 4869 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4870 hr_reg_clear(qpc_mask, QPC_SL); 4871 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4872 return 0; 4873 } 4874 4875 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4876 hr_port = ib_port - 1; 4877 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4878 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4879 4880 if (is_roce_protocol) { 4881 gid_attr = attr->ah_attr.grh.sgid_attr; 4882 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4883 if (ret) 4884 return ret; 4885 4886 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4887 } 4888 4889 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4890 if (vlan_id < VLAN_N_VID && 4891 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4892 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4893 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4894 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4895 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4896 } 4897 4898 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4899 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4900 4901 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4902 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4903 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4904 return -EINVAL; 4905 } 4906 4907 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4908 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4909 return -EINVAL; 4910 } 4911 4912 hr_reg_write(context, QPC_UDPSPN, 4913 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4914 attr->dest_qp_num) : 4915 0); 4916 4917 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4918 4919 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4920 4921 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4922 4923 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4924 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4925 4926 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4927 if (ret) 4928 return ret; 4929 4930 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4931 hr_reg_clear(qpc_mask, QPC_TC); 4932 4933 hr_reg_write(context, QPC_FL, grh->flow_label); 4934 hr_reg_clear(qpc_mask, QPC_FL); 4935 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4936 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4937 4938 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4939 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4940 ibdev_err(ibdev, 4941 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 4942 hr_qp->sl, MAX_SERVICE_LEVEL); 4943 return -EINVAL; 4944 } 4945 4946 hr_reg_write(context, QPC_SL, hr_qp->sl); 4947 hr_reg_clear(qpc_mask, QPC_SL); 4948 4949 return 0; 4950 } 4951 4952 static bool check_qp_state(enum ib_qp_state cur_state, 4953 enum ib_qp_state new_state) 4954 { 4955 static const bool sm[][IB_QPS_ERR + 1] = { 4956 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4957 [IB_QPS_INIT] = true }, 4958 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4959 [IB_QPS_INIT] = true, 4960 [IB_QPS_RTR] = true, 4961 [IB_QPS_ERR] = true }, 4962 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4963 [IB_QPS_RTS] = true, 4964 [IB_QPS_ERR] = true }, 4965 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4966 [IB_QPS_RTS] = true, 4967 [IB_QPS_ERR] = true }, 4968 [IB_QPS_SQD] = {}, 4969 [IB_QPS_SQE] = {}, 4970 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4971 [IB_QPS_ERR] = true } 4972 }; 4973 4974 return sm[cur_state][new_state]; 4975 } 4976 4977 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4978 const struct ib_qp_attr *attr, 4979 int attr_mask, 4980 enum ib_qp_state cur_state, 4981 enum ib_qp_state new_state, 4982 struct hns_roce_v2_qp_context *context, 4983 struct hns_roce_v2_qp_context *qpc_mask, 4984 struct ib_udata *udata) 4985 { 4986 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4987 int ret = 0; 4988 4989 if (!check_qp_state(cur_state, new_state)) { 4990 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4991 return -EINVAL; 4992 } 4993 4994 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4995 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4996 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4997 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4998 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4999 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 5000 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 5001 qpc_mask, udata); 5002 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 5003 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 5004 qpc_mask); 5005 } 5006 5007 return ret; 5008 } 5009 5010 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 5011 { 5012 #define QP_ACK_TIMEOUT_MAX_HIP08 20 5013 #define QP_ACK_TIMEOUT_MAX 31 5014 5015 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5016 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 5017 ibdev_warn(&hr_dev->ib_dev, 5018 "local ACK timeout shall be 0 to 20.\n"); 5019 return false; 5020 } 5021 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5022 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5023 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5024 ibdev_warn(&hr_dev->ib_dev, 5025 "local ACK timeout shall be 0 to 31.\n"); 5026 return false; 5027 } 5028 } 5029 5030 return true; 5031 } 5032 5033 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5034 const struct ib_qp_attr *attr, 5035 int attr_mask, 5036 struct hns_roce_v2_qp_context *context, 5037 struct hns_roce_v2_qp_context *qpc_mask) 5038 { 5039 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5040 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5041 int ret = 0; 5042 u8 timeout; 5043 5044 if (attr_mask & IB_QP_AV) { 5045 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5046 qpc_mask); 5047 if (ret) 5048 return ret; 5049 } 5050 5051 if (attr_mask & IB_QP_TIMEOUT) { 5052 timeout = attr->timeout; 5053 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5054 hr_reg_write(context, QPC_AT, timeout); 5055 hr_reg_clear(qpc_mask, QPC_AT); 5056 } 5057 } 5058 5059 if (attr_mask & IB_QP_RETRY_CNT) { 5060 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5061 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5062 5063 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5064 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5065 } 5066 5067 if (attr_mask & IB_QP_RNR_RETRY) { 5068 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5069 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5070 5071 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5072 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5073 } 5074 5075 if (attr_mask & IB_QP_SQ_PSN) { 5076 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5077 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5078 5079 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5080 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5081 5082 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5083 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5084 5085 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5086 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5087 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5088 5089 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5090 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5091 5092 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5093 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5094 } 5095 5096 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5097 attr->max_dest_rd_atomic) { 5098 hr_reg_write(context, QPC_RR_MAX, 5099 fls(attr->max_dest_rd_atomic - 1)); 5100 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5101 } 5102 5103 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5104 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5105 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5106 } 5107 5108 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5109 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5110 5111 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5112 hr_reg_write(context, QPC_MIN_RNR_TIME, 5113 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5114 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5115 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5116 } 5117 5118 if (attr_mask & IB_QP_RQ_PSN) { 5119 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5120 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5121 5122 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5123 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5124 } 5125 5126 if (attr_mask & IB_QP_QKEY) { 5127 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5128 qpc_mask->qkey_xrcd = 0; 5129 hr_qp->qkey = attr->qkey; 5130 } 5131 5132 return ret; 5133 } 5134 5135 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5136 const struct ib_qp_attr *attr, 5137 int attr_mask) 5138 { 5139 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5140 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5141 5142 if (attr_mask & IB_QP_ACCESS_FLAGS) 5143 hr_qp->atomic_rd_en = attr->qp_access_flags; 5144 5145 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5146 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5147 if (attr_mask & IB_QP_PORT) { 5148 hr_qp->port = attr->port_num - 1; 5149 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5150 } 5151 } 5152 5153 static void clear_qp(struct hns_roce_qp *hr_qp) 5154 { 5155 struct ib_qp *ibqp = &hr_qp->ibqp; 5156 5157 if (ibqp->send_cq) 5158 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5159 hr_qp->qpn, NULL); 5160 5161 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5162 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5163 hr_qp->qpn, ibqp->srq ? 5164 to_hr_srq(ibqp->srq) : NULL); 5165 5166 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5167 *hr_qp->rdb.db_record = 0; 5168 5169 hr_qp->rq.head = 0; 5170 hr_qp->rq.tail = 0; 5171 hr_qp->sq.head = 0; 5172 hr_qp->sq.tail = 0; 5173 hr_qp->next_sge = 0; 5174 } 5175 5176 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5177 struct hns_roce_v2_qp_context *context, 5178 struct hns_roce_v2_qp_context *qpc_mask) 5179 { 5180 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5181 unsigned long sq_flag = 0; 5182 unsigned long rq_flag = 0; 5183 5184 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5185 return; 5186 5187 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5188 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5189 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5190 hr_qp->state = IB_QPS_ERR; 5191 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5192 5193 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5194 return; 5195 5196 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5197 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5198 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5199 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5200 } 5201 5202 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5203 const struct ib_qp_attr *attr, 5204 int attr_mask, enum ib_qp_state cur_state, 5205 enum ib_qp_state new_state, struct ib_udata *udata) 5206 { 5207 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5208 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5209 struct hns_roce_v2_qp_context ctx[2]; 5210 struct hns_roce_v2_qp_context *context = ctx; 5211 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5212 struct ib_device *ibdev = &hr_dev->ib_dev; 5213 int ret; 5214 5215 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5216 return -EOPNOTSUPP; 5217 5218 /* 5219 * In v2 engine, software pass context and context mask to hardware 5220 * when modifying qp. If software need modify some fields in context, 5221 * we should set all bits of the relevant fields in context mask to 5222 * 0 at the same time, else set them to 0x1. 5223 */ 5224 memset(context, 0, hr_dev->caps.qpc_sz); 5225 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5226 5227 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5228 new_state, context, qpc_mask, udata); 5229 if (ret) 5230 goto out; 5231 5232 /* When QP state is err, SQ and RQ WQE should be flushed */ 5233 if (new_state == IB_QPS_ERR) 5234 v2_set_flushed_fields(ibqp, context, qpc_mask); 5235 5236 /* Configure the optional fields */ 5237 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5238 qpc_mask); 5239 if (ret) 5240 goto out; 5241 5242 hr_reg_write_bool(context, QPC_INV_CREDIT, 5243 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5244 ibqp->srq); 5245 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5246 5247 /* Every status migrate must change state */ 5248 hr_reg_write(context, QPC_QP_ST, new_state); 5249 hr_reg_clear(qpc_mask, QPC_QP_ST); 5250 5251 /* SW pass context to HW */ 5252 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5253 if (ret) { 5254 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5255 goto out; 5256 } 5257 5258 hr_qp->state = new_state; 5259 5260 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5261 5262 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5263 clear_qp(hr_qp); 5264 5265 out: 5266 return ret; 5267 } 5268 5269 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5270 { 5271 static const enum ib_qp_state map[] = { 5272 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5273 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5274 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5275 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5276 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5277 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5278 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5279 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5280 }; 5281 5282 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5283 } 5284 5285 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5286 void *buffer) 5287 { 5288 struct hns_roce_cmd_mailbox *mailbox; 5289 int ret; 5290 5291 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5292 if (IS_ERR(mailbox)) 5293 return PTR_ERR(mailbox); 5294 5295 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5296 qpn); 5297 if (ret) 5298 goto out; 5299 5300 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5301 5302 out: 5303 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5304 return ret; 5305 } 5306 5307 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5308 struct hns_roce_v2_qp_context *context) 5309 { 5310 u8 timeout; 5311 5312 timeout = (u8)hr_reg_read(context, QPC_AT); 5313 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5314 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5315 5316 return timeout; 5317 } 5318 5319 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5320 int qp_attr_mask, 5321 struct ib_qp_init_attr *qp_init_attr) 5322 { 5323 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5324 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5325 struct hns_roce_v2_qp_context context = {}; 5326 struct ib_device *ibdev = &hr_dev->ib_dev; 5327 int tmp_qp_state; 5328 int state; 5329 int ret; 5330 5331 memset(qp_attr, 0, sizeof(*qp_attr)); 5332 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5333 5334 mutex_lock(&hr_qp->mutex); 5335 5336 if (hr_qp->state == IB_QPS_RESET) { 5337 qp_attr->qp_state = IB_QPS_RESET; 5338 ret = 0; 5339 goto done; 5340 } 5341 5342 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5343 if (ret) { 5344 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5345 ret = -EINVAL; 5346 goto out; 5347 } 5348 5349 state = hr_reg_read(&context, QPC_QP_ST); 5350 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5351 if (tmp_qp_state == -1) { 5352 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5353 ret = -EINVAL; 5354 goto out; 5355 } 5356 hr_qp->state = (u8)tmp_qp_state; 5357 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5358 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5359 qp_attr->path_mig_state = IB_MIG_ARMED; 5360 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5361 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5362 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5363 5364 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5365 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5366 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5367 qp_attr->qp_access_flags = 5368 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5369 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5370 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5371 5372 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5373 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5374 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5375 struct ib_global_route *grh = 5376 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5377 5378 rdma_ah_set_sl(&qp_attr->ah_attr, 5379 hr_reg_read(&context, QPC_SL)); 5380 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5381 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5382 grh->flow_label = hr_reg_read(&context, QPC_FL); 5383 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5384 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5385 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5386 5387 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5388 } 5389 5390 qp_attr->port_num = hr_qp->port + 1; 5391 qp_attr->sq_draining = 0; 5392 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5393 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5394 5395 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5396 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5397 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5398 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5399 5400 done: 5401 qp_attr->cur_qp_state = qp_attr->qp_state; 5402 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5403 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5404 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5405 5406 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5407 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5408 5409 qp_init_attr->qp_context = ibqp->qp_context; 5410 qp_init_attr->qp_type = ibqp->qp_type; 5411 qp_init_attr->recv_cq = ibqp->recv_cq; 5412 qp_init_attr->send_cq = ibqp->send_cq; 5413 qp_init_attr->srq = ibqp->srq; 5414 qp_init_attr->cap = qp_attr->cap; 5415 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5416 5417 out: 5418 mutex_unlock(&hr_qp->mutex); 5419 return ret; 5420 } 5421 5422 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5423 { 5424 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5425 hr_qp->ibqp.qp_type == IB_QPT_UD || 5426 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5427 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5428 hr_qp->state != IB_QPS_RESET); 5429 } 5430 5431 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5432 struct hns_roce_qp *hr_qp, 5433 struct ib_udata *udata) 5434 { 5435 struct ib_device *ibdev = &hr_dev->ib_dev; 5436 struct hns_roce_cq *send_cq, *recv_cq; 5437 unsigned long flags; 5438 int ret = 0; 5439 5440 if (modify_qp_is_ok(hr_qp)) { 5441 /* Modify qp to reset before destroying qp */ 5442 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5443 hr_qp->state, IB_QPS_RESET, udata); 5444 if (ret) 5445 ibdev_err(ibdev, 5446 "failed to modify QP to RST, ret = %d.\n", 5447 ret); 5448 } 5449 5450 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5451 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5452 5453 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5454 hns_roce_lock_cqs(send_cq, recv_cq); 5455 5456 if (!udata) { 5457 if (recv_cq) 5458 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5459 (hr_qp->ibqp.srq ? 5460 to_hr_srq(hr_qp->ibqp.srq) : 5461 NULL)); 5462 5463 if (send_cq && send_cq != recv_cq) 5464 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5465 } 5466 5467 hns_roce_qp_remove(hr_dev, hr_qp); 5468 5469 hns_roce_unlock_cqs(send_cq, recv_cq); 5470 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5471 5472 return ret; 5473 } 5474 5475 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5476 { 5477 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5478 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5479 int ret; 5480 5481 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5482 if (ret) 5483 ibdev_err(&hr_dev->ib_dev, 5484 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5485 hr_qp->qpn, ret); 5486 5487 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5488 5489 return 0; 5490 } 5491 5492 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5493 struct hns_roce_qp *hr_qp) 5494 { 5495 struct ib_device *ibdev = &hr_dev->ib_dev; 5496 struct hns_roce_sccc_clr_done *resp; 5497 struct hns_roce_sccc_clr *clr; 5498 struct hns_roce_cmq_desc desc; 5499 int ret, i; 5500 5501 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5502 return 0; 5503 5504 mutex_lock(&hr_dev->qp_table.scc_mutex); 5505 5506 /* set scc ctx clear done flag */ 5507 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5508 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5509 if (ret) { 5510 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5511 goto out; 5512 } 5513 5514 /* clear scc context */ 5515 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5516 clr = (struct hns_roce_sccc_clr *)desc.data; 5517 clr->qpn = cpu_to_le32(hr_qp->qpn); 5518 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5519 if (ret) { 5520 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5521 goto out; 5522 } 5523 5524 /* query scc context clear is done or not */ 5525 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5526 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5527 hns_roce_cmq_setup_basic_desc(&desc, 5528 HNS_ROCE_OPC_QUERY_SCCC, true); 5529 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5530 if (ret) { 5531 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5532 ret); 5533 goto out; 5534 } 5535 5536 if (resp->clr_done) 5537 goto out; 5538 5539 msleep(20); 5540 } 5541 5542 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5543 ret = -ETIMEDOUT; 5544 5545 out: 5546 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5547 return ret; 5548 } 5549 5550 #define DMA_IDX_SHIFT 3 5551 #define DMA_WQE_SHIFT 3 5552 5553 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5554 struct hns_roce_srq_context *ctx) 5555 { 5556 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5557 struct ib_device *ibdev = srq->ibsrq.device; 5558 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5559 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5560 dma_addr_t dma_handle_idx = 0; 5561 int ret; 5562 5563 /* Get physical address of idx que buf */ 5564 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5565 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5566 if (ret < 1) { 5567 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5568 ret); 5569 return -ENOBUFS; 5570 } 5571 5572 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5573 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5574 5575 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5576 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5577 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5578 5579 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5580 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5581 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5582 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5583 5584 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5585 to_hr_hw_page_addr(mtts_idx[0])); 5586 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5587 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5588 5589 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5590 to_hr_hw_page_addr(mtts_idx[1])); 5591 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5592 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5593 5594 return 0; 5595 } 5596 5597 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5598 { 5599 struct ib_device *ibdev = srq->ibsrq.device; 5600 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5601 struct hns_roce_srq_context *ctx = mb_buf; 5602 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5603 dma_addr_t dma_handle_wqe = 0; 5604 int ret; 5605 5606 memset(ctx, 0, sizeof(*ctx)); 5607 5608 /* Get the physical address of srq buf */ 5609 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5610 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5611 if (ret < 1) { 5612 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5613 ret); 5614 return -ENOBUFS; 5615 } 5616 5617 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5618 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5619 srq->ibsrq.srq_type == IB_SRQT_XRC); 5620 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5621 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5622 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5623 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5624 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5625 hr_reg_write(ctx, SRQC_RQWS, 5626 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5627 5628 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5629 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5630 srq->wqe_cnt)); 5631 5632 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5633 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5634 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5635 5636 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5637 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5638 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5639 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5640 5641 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5642 } 5643 5644 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5645 struct ib_srq_attr *srq_attr, 5646 enum ib_srq_attr_mask srq_attr_mask, 5647 struct ib_udata *udata) 5648 { 5649 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5650 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5651 struct hns_roce_srq_context *srq_context; 5652 struct hns_roce_srq_context *srqc_mask; 5653 struct hns_roce_cmd_mailbox *mailbox; 5654 int ret; 5655 5656 /* Resizing SRQs is not supported yet */ 5657 if (srq_attr_mask & IB_SRQ_MAX_WR) 5658 return -EINVAL; 5659 5660 if (srq_attr_mask & IB_SRQ_LIMIT) { 5661 if (srq_attr->srq_limit > srq->wqe_cnt) 5662 return -EINVAL; 5663 5664 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5665 if (IS_ERR(mailbox)) 5666 return PTR_ERR(mailbox); 5667 5668 srq_context = mailbox->buf; 5669 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5670 5671 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5672 5673 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5674 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5675 5676 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5677 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5678 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5679 if (ret) { 5680 ibdev_err(&hr_dev->ib_dev, 5681 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5682 ret); 5683 return ret; 5684 } 5685 } 5686 5687 return 0; 5688 } 5689 5690 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5691 { 5692 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5693 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5694 struct hns_roce_srq_context *srq_context; 5695 struct hns_roce_cmd_mailbox *mailbox; 5696 int ret; 5697 5698 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5699 if (IS_ERR(mailbox)) 5700 return PTR_ERR(mailbox); 5701 5702 srq_context = mailbox->buf; 5703 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5704 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5705 if (ret) { 5706 ibdev_err(&hr_dev->ib_dev, 5707 "failed to process cmd of querying SRQ, ret = %d.\n", 5708 ret); 5709 goto out; 5710 } 5711 5712 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5713 attr->max_wr = srq->wqe_cnt; 5714 attr->max_sge = srq->max_gs - srq->rsv_sge; 5715 5716 out: 5717 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5718 return ret; 5719 } 5720 5721 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5722 { 5723 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5724 struct hns_roce_v2_cq_context *cq_context; 5725 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5726 struct hns_roce_v2_cq_context *cqc_mask; 5727 struct hns_roce_cmd_mailbox *mailbox; 5728 int ret; 5729 5730 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5731 if (IS_ERR(mailbox)) 5732 return PTR_ERR(mailbox); 5733 5734 cq_context = mailbox->buf; 5735 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5736 5737 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5738 5739 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5740 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5741 5742 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5743 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5744 dev_info(hr_dev->dev, 5745 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5746 cq_period); 5747 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5748 } 5749 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5750 } 5751 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5752 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5753 5754 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5755 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5756 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5757 if (ret) 5758 ibdev_err(&hr_dev->ib_dev, 5759 "failed to process cmd when modifying CQ, ret = %d.\n", 5760 ret); 5761 5762 return ret; 5763 } 5764 5765 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5766 void *buffer) 5767 { 5768 struct hns_roce_v2_cq_context *context; 5769 struct hns_roce_cmd_mailbox *mailbox; 5770 int ret; 5771 5772 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5773 if (IS_ERR(mailbox)) 5774 return PTR_ERR(mailbox); 5775 5776 context = mailbox->buf; 5777 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5778 HNS_ROCE_CMD_QUERY_CQC, cqn); 5779 if (ret) { 5780 ibdev_err(&hr_dev->ib_dev, 5781 "failed to process cmd when querying CQ, ret = %d.\n", 5782 ret); 5783 goto err_mailbox; 5784 } 5785 5786 memcpy(buffer, context, sizeof(*context)); 5787 5788 err_mailbox: 5789 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5790 5791 return ret; 5792 } 5793 5794 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5795 void *buffer) 5796 { 5797 struct hns_roce_v2_mpt_entry *context; 5798 struct hns_roce_cmd_mailbox *mailbox; 5799 int ret; 5800 5801 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5802 if (IS_ERR(mailbox)) 5803 return PTR_ERR(mailbox); 5804 5805 context = mailbox->buf; 5806 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5807 key_to_hw_index(key)); 5808 if (ret) { 5809 ibdev_err(&hr_dev->ib_dev, 5810 "failed to process cmd when querying MPT, ret = %d.\n", 5811 ret); 5812 goto err_mailbox; 5813 } 5814 5815 memcpy(buffer, context, sizeof(*context)); 5816 5817 err_mailbox: 5818 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5819 5820 return ret; 5821 } 5822 5823 static void hns_roce_irq_work_handle(struct work_struct *work) 5824 { 5825 struct hns_roce_work *irq_work = 5826 container_of(work, struct hns_roce_work, work); 5827 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5828 5829 switch (irq_work->event_type) { 5830 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5831 ibdev_info(ibdev, "path migrated succeeded.\n"); 5832 break; 5833 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5834 ibdev_warn(ibdev, "path migration failed.\n"); 5835 break; 5836 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5837 break; 5838 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5839 ibdev_warn(ibdev, "send queue drained.\n"); 5840 break; 5841 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5842 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5843 irq_work->queue_num, irq_work->sub_type); 5844 break; 5845 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5846 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5847 irq_work->queue_num); 5848 break; 5849 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5850 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5851 irq_work->queue_num, irq_work->sub_type); 5852 break; 5853 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5854 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5855 break; 5856 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5857 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5858 break; 5859 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5860 ibdev_err(ibdev, "SRQ catas error.\n"); 5861 break; 5862 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5863 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5864 break; 5865 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5866 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5867 break; 5868 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5869 ibdev_warn(ibdev, "DB overflow.\n"); 5870 break; 5871 case HNS_ROCE_EVENT_TYPE_FLR: 5872 ibdev_warn(ibdev, "function level reset.\n"); 5873 break; 5874 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5875 ibdev_err(ibdev, "xrc domain violation error.\n"); 5876 break; 5877 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5878 ibdev_err(ibdev, "invalid xrceth error.\n"); 5879 break; 5880 default: 5881 break; 5882 } 5883 5884 kfree(irq_work); 5885 } 5886 5887 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5888 struct hns_roce_eq *eq, u32 queue_num) 5889 { 5890 struct hns_roce_work *irq_work; 5891 5892 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5893 if (!irq_work) 5894 return; 5895 5896 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5897 irq_work->hr_dev = hr_dev; 5898 irq_work->event_type = eq->event_type; 5899 irq_work->sub_type = eq->sub_type; 5900 irq_work->queue_num = queue_num; 5901 queue_work(hr_dev->irq_workq, &irq_work->work); 5902 } 5903 5904 static void update_eq_db(struct hns_roce_eq *eq) 5905 { 5906 struct hns_roce_dev *hr_dev = eq->hr_dev; 5907 struct hns_roce_v2_db eq_db = {}; 5908 5909 if (eq->type_flag == HNS_ROCE_AEQ) { 5910 hr_reg_write(&eq_db, EQ_DB_CMD, 5911 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5912 HNS_ROCE_EQ_DB_CMD_AEQ : 5913 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5914 } else { 5915 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5916 5917 hr_reg_write(&eq_db, EQ_DB_CMD, 5918 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5919 HNS_ROCE_EQ_DB_CMD_CEQ : 5920 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5921 } 5922 5923 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5924 5925 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5926 } 5927 5928 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5929 { 5930 struct hns_roce_aeqe *aeqe; 5931 5932 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5933 (eq->cons_index & (eq->entries - 1)) * 5934 eq->eqe_size); 5935 5936 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5937 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5938 } 5939 5940 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5941 struct hns_roce_eq *eq) 5942 { 5943 struct device *dev = hr_dev->dev; 5944 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5945 irqreturn_t aeqe_found = IRQ_NONE; 5946 int event_type; 5947 u32 queue_num; 5948 int sub_type; 5949 5950 while (aeqe) { 5951 /* Make sure we read AEQ entry after we have checked the 5952 * ownership bit 5953 */ 5954 dma_rmb(); 5955 5956 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5957 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5958 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5959 5960 switch (event_type) { 5961 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5962 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5963 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5964 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5965 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5966 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5967 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5968 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5969 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5970 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5971 hns_roce_qp_event(hr_dev, queue_num, event_type); 5972 break; 5973 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5974 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5975 hns_roce_srq_event(hr_dev, queue_num, event_type); 5976 break; 5977 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5978 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5979 hns_roce_cq_event(hr_dev, queue_num, event_type); 5980 break; 5981 case HNS_ROCE_EVENT_TYPE_MB: 5982 hns_roce_cmd_event(hr_dev, 5983 le16_to_cpu(aeqe->event.cmd.token), 5984 aeqe->event.cmd.status, 5985 le64_to_cpu(aeqe->event.cmd.out_param)); 5986 break; 5987 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5988 case HNS_ROCE_EVENT_TYPE_FLR: 5989 break; 5990 default: 5991 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 5992 event_type, eq->eqn, eq->cons_index); 5993 break; 5994 } 5995 5996 eq->event_type = event_type; 5997 eq->sub_type = sub_type; 5998 ++eq->cons_index; 5999 aeqe_found = IRQ_HANDLED; 6000 6001 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 6002 6003 aeqe = next_aeqe_sw_v2(eq); 6004 } 6005 6006 update_eq_db(eq); 6007 6008 return IRQ_RETVAL(aeqe_found); 6009 } 6010 6011 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 6012 { 6013 struct hns_roce_ceqe *ceqe; 6014 6015 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 6016 (eq->cons_index & (eq->entries - 1)) * 6017 eq->eqe_size); 6018 6019 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6020 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6021 } 6022 6023 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6024 struct hns_roce_eq *eq) 6025 { 6026 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6027 irqreturn_t ceqe_found = IRQ_NONE; 6028 u32 cqn; 6029 6030 while (ceqe) { 6031 /* Make sure we read CEQ entry after we have checked the 6032 * ownership bit 6033 */ 6034 dma_rmb(); 6035 6036 cqn = hr_reg_read(ceqe, CEQE_CQN); 6037 6038 hns_roce_cq_completion(hr_dev, cqn); 6039 6040 ++eq->cons_index; 6041 ceqe_found = IRQ_HANDLED; 6042 6043 ceqe = next_ceqe_sw_v2(eq); 6044 } 6045 6046 update_eq_db(eq); 6047 6048 return IRQ_RETVAL(ceqe_found); 6049 } 6050 6051 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6052 { 6053 struct hns_roce_eq *eq = eq_ptr; 6054 struct hns_roce_dev *hr_dev = eq->hr_dev; 6055 irqreturn_t int_work; 6056 6057 if (eq->type_flag == HNS_ROCE_CEQ) 6058 /* Completion event interrupt */ 6059 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6060 else 6061 /* Asynchronous event interrupt */ 6062 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6063 6064 return IRQ_RETVAL(int_work); 6065 } 6066 6067 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6068 u32 int_st) 6069 { 6070 struct pci_dev *pdev = hr_dev->pci_dev; 6071 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6072 const struct hnae3_ae_ops *ops = ae_dev->ops; 6073 irqreturn_t int_work = IRQ_NONE; 6074 u32 int_en; 6075 6076 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6077 6078 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6079 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6080 6081 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6082 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6083 6084 /* Set reset level for reset_event() */ 6085 if (ops->set_default_reset_request) 6086 ops->set_default_reset_request(ae_dev, 6087 HNAE3_FUNC_RESET); 6088 if (ops->reset_event) 6089 ops->reset_event(pdev, NULL); 6090 6091 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6092 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6093 6094 int_work = IRQ_HANDLED; 6095 } else { 6096 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6097 } 6098 6099 return IRQ_RETVAL(int_work); 6100 } 6101 6102 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6103 struct fmea_ram_ecc *ecc_info) 6104 { 6105 struct hns_roce_cmq_desc desc; 6106 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6107 int ret; 6108 6109 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6110 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6111 if (ret) 6112 return ret; 6113 6114 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6115 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6116 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6117 6118 return 0; 6119 } 6120 6121 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6122 { 6123 struct hns_roce_cmq_desc desc; 6124 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6125 u32 addr_upper; 6126 u32 addr_low; 6127 int ret; 6128 6129 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6130 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6131 6132 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6133 if (ret) { 6134 dev_err(hr_dev->dev, 6135 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6136 return ret; 6137 } 6138 6139 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6140 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6141 6142 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6143 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6144 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6145 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6146 6147 return hns_roce_cmq_send(hr_dev, &desc, 1); 6148 } 6149 6150 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6151 { 6152 if (res_type == ECC_RESOURCE_QPC_TIMER || 6153 res_type == ECC_RESOURCE_CQC_TIMER || 6154 res_type == ECC_RESOURCE_SCCC) 6155 return le64_to_cpu(*data); 6156 6157 return le64_to_cpu(*data) << PAGE_SHIFT; 6158 } 6159 6160 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6161 u32 index) 6162 { 6163 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6164 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6165 struct hns_roce_cmd_mailbox *mailbox; 6166 u64 addr; 6167 int ret; 6168 6169 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6170 if (IS_ERR(mailbox)) 6171 return PTR_ERR(mailbox); 6172 6173 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6174 if (ret) { 6175 dev_err(hr_dev->dev, 6176 "failed to execute cmd to read fmea ram, ret = %d.\n", 6177 ret); 6178 goto out; 6179 } 6180 6181 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6182 6183 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6184 if (ret) 6185 dev_err(hr_dev->dev, 6186 "failed to execute cmd to write fmea ram, ret = %d.\n", 6187 ret); 6188 6189 out: 6190 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6191 return ret; 6192 } 6193 6194 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6195 struct fmea_ram_ecc *ecc_info) 6196 { 6197 u32 res_type = ecc_info->res_type; 6198 u32 index = ecc_info->index; 6199 int ret; 6200 6201 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6202 6203 if (res_type >= ECC_RESOURCE_COUNT) { 6204 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6205 res_type); 6206 return; 6207 } 6208 6209 if (res_type == ECC_RESOURCE_GMV) 6210 ret = fmea_recover_gmv(hr_dev, index); 6211 else 6212 ret = fmea_recover_others(hr_dev, res_type, index); 6213 if (ret) 6214 dev_err(hr_dev->dev, 6215 "failed to recover %s, index = %u, ret = %d.\n", 6216 fmea_ram_res[res_type].name, index, ret); 6217 } 6218 6219 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6220 { 6221 struct hns_roce_dev *hr_dev = 6222 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6223 struct fmea_ram_ecc ecc_info = {}; 6224 6225 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6226 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6227 return; 6228 } 6229 6230 if (!ecc_info.is_ecc_err) { 6231 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6232 return; 6233 } 6234 6235 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6236 } 6237 6238 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6239 { 6240 struct hns_roce_dev *hr_dev = dev_id; 6241 irqreturn_t int_work = IRQ_NONE; 6242 u32 int_st; 6243 6244 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6245 6246 if (int_st) { 6247 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6248 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6249 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6250 int_work = IRQ_HANDLED; 6251 } else { 6252 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6253 } 6254 6255 return IRQ_RETVAL(int_work); 6256 } 6257 6258 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6259 int eq_num, u32 enable_flag) 6260 { 6261 int i; 6262 6263 for (i = 0; i < eq_num; i++) 6264 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6265 i * EQ_REG_OFFSET, enable_flag); 6266 6267 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6268 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6269 } 6270 6271 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6272 { 6273 struct device *dev = hr_dev->dev; 6274 int ret; 6275 u8 cmd; 6276 6277 if (eqn < hr_dev->caps.num_comp_vectors) 6278 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6279 else 6280 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6281 6282 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6283 if (ret) 6284 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6285 } 6286 6287 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6288 { 6289 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6290 } 6291 6292 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6293 { 6294 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6295 eq->cons_index = 0; 6296 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6297 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6298 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6299 eq->shift = ilog2((unsigned int)eq->entries); 6300 } 6301 6302 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6303 void *mb_buf) 6304 { 6305 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6306 struct hns_roce_eq_context *eqc; 6307 u64 bt_ba = 0; 6308 int count; 6309 6310 eqc = mb_buf; 6311 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6312 6313 init_eq_config(hr_dev, eq); 6314 6315 /* if not multi-hop, eqe buffer only use one trunk */ 6316 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6317 &bt_ba); 6318 if (count < 1) { 6319 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6320 return -ENOBUFS; 6321 } 6322 6323 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6324 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6325 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6326 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6327 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6328 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6329 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6330 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6331 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6332 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6333 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6334 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6335 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6336 6337 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6338 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6339 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6340 eq->eq_period); 6341 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6342 } 6343 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6344 } 6345 6346 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6347 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6348 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6349 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6350 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6351 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6352 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6353 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6354 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6355 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6356 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6357 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6358 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6359 6360 return 0; 6361 } 6362 6363 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6364 { 6365 struct hns_roce_buf_attr buf_attr = {}; 6366 int err; 6367 6368 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6369 eq->hop_num = 0; 6370 else 6371 eq->hop_num = hr_dev->caps.eqe_hop_num; 6372 6373 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6374 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6375 buf_attr.region[0].hopnum = eq->hop_num; 6376 buf_attr.region_count = 1; 6377 6378 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6379 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6380 0); 6381 if (err) 6382 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6383 6384 return err; 6385 } 6386 6387 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6388 struct hns_roce_eq *eq, u8 eq_cmd) 6389 { 6390 struct hns_roce_cmd_mailbox *mailbox; 6391 int ret; 6392 6393 /* Allocate mailbox memory */ 6394 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6395 if (IS_ERR(mailbox)) 6396 return PTR_ERR(mailbox); 6397 6398 ret = alloc_eq_buf(hr_dev, eq); 6399 if (ret) 6400 goto free_cmd_mbox; 6401 6402 ret = config_eqc(hr_dev, eq, mailbox->buf); 6403 if (ret) 6404 goto err_cmd_mbox; 6405 6406 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6407 if (ret) { 6408 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6409 goto err_cmd_mbox; 6410 } 6411 6412 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6413 6414 return 0; 6415 6416 err_cmd_mbox: 6417 free_eq_buf(hr_dev, eq); 6418 6419 free_cmd_mbox: 6420 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6421 6422 return ret; 6423 } 6424 6425 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6426 int comp_num, int aeq_num, int other_num) 6427 { 6428 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6429 int i, j; 6430 int ret; 6431 6432 for (i = 0; i < irq_num; i++) { 6433 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6434 GFP_KERNEL); 6435 if (!hr_dev->irq_names[i]) { 6436 ret = -ENOMEM; 6437 goto err_kzalloc_failed; 6438 } 6439 } 6440 6441 /* irq contains: abnormal + AEQ + CEQ */ 6442 for (j = 0; j < other_num; j++) 6443 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6444 "hns-abn-%d", j); 6445 6446 for (j = other_num; j < (other_num + aeq_num); j++) 6447 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6448 "hns-aeq-%d", j - other_num); 6449 6450 for (j = (other_num + aeq_num); j < irq_num; j++) 6451 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6452 "hns-ceq-%d", j - other_num - aeq_num); 6453 6454 for (j = 0; j < irq_num; j++) { 6455 if (j < other_num) 6456 ret = request_irq(hr_dev->irq[j], 6457 hns_roce_v2_msix_interrupt_abn, 6458 0, hr_dev->irq_names[j], hr_dev); 6459 6460 else if (j < (other_num + comp_num)) 6461 ret = request_irq(eq_table->eq[j - other_num].irq, 6462 hns_roce_v2_msix_interrupt_eq, 6463 0, hr_dev->irq_names[j + aeq_num], 6464 &eq_table->eq[j - other_num]); 6465 else 6466 ret = request_irq(eq_table->eq[j - other_num].irq, 6467 hns_roce_v2_msix_interrupt_eq, 6468 0, hr_dev->irq_names[j - comp_num], 6469 &eq_table->eq[j - other_num]); 6470 if (ret) { 6471 dev_err(hr_dev->dev, "request irq error!\n"); 6472 goto err_request_failed; 6473 } 6474 } 6475 6476 return 0; 6477 6478 err_request_failed: 6479 for (j -= 1; j >= 0; j--) 6480 if (j < other_num) 6481 free_irq(hr_dev->irq[j], hr_dev); 6482 else 6483 free_irq(eq_table->eq[j - other_num].irq, 6484 &eq_table->eq[j - other_num]); 6485 6486 err_kzalloc_failed: 6487 for (i -= 1; i >= 0; i--) 6488 kfree(hr_dev->irq_names[i]); 6489 6490 return ret; 6491 } 6492 6493 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6494 { 6495 int irq_num; 6496 int eq_num; 6497 int i; 6498 6499 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6500 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6501 6502 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6503 free_irq(hr_dev->irq[i], hr_dev); 6504 6505 for (i = 0; i < eq_num; i++) 6506 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6507 6508 for (i = 0; i < irq_num; i++) 6509 kfree(hr_dev->irq_names[i]); 6510 } 6511 6512 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6513 { 6514 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6515 struct device *dev = hr_dev->dev; 6516 struct hns_roce_eq *eq; 6517 int other_num; 6518 int comp_num; 6519 int aeq_num; 6520 int irq_num; 6521 int eq_num; 6522 u8 eq_cmd; 6523 int ret; 6524 int i; 6525 6526 other_num = hr_dev->caps.num_other_vectors; 6527 comp_num = hr_dev->caps.num_comp_vectors; 6528 aeq_num = hr_dev->caps.num_aeq_vectors; 6529 6530 eq_num = comp_num + aeq_num; 6531 irq_num = eq_num + other_num; 6532 6533 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6534 if (!eq_table->eq) 6535 return -ENOMEM; 6536 6537 /* create eq */ 6538 for (i = 0; i < eq_num; i++) { 6539 eq = &eq_table->eq[i]; 6540 eq->hr_dev = hr_dev; 6541 eq->eqn = i; 6542 if (i < comp_num) { 6543 /* CEQ */ 6544 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6545 eq->type_flag = HNS_ROCE_CEQ; 6546 eq->entries = hr_dev->caps.ceqe_depth; 6547 eq->eqe_size = hr_dev->caps.ceqe_size; 6548 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6549 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6550 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6551 } else { 6552 /* AEQ */ 6553 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6554 eq->type_flag = HNS_ROCE_AEQ; 6555 eq->entries = hr_dev->caps.aeqe_depth; 6556 eq->eqe_size = hr_dev->caps.aeqe_size; 6557 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6558 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6559 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6560 } 6561 6562 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6563 if (ret) { 6564 dev_err(dev, "failed to create eq.\n"); 6565 goto err_create_eq_fail; 6566 } 6567 } 6568 6569 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6570 6571 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6572 if (!hr_dev->irq_workq) { 6573 dev_err(dev, "failed to create irq workqueue.\n"); 6574 ret = -ENOMEM; 6575 goto err_create_eq_fail; 6576 } 6577 6578 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6579 other_num); 6580 if (ret) { 6581 dev_err(dev, "failed to request irq.\n"); 6582 goto err_request_irq_fail; 6583 } 6584 6585 /* enable irq */ 6586 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6587 6588 return 0; 6589 6590 err_request_irq_fail: 6591 destroy_workqueue(hr_dev->irq_workq); 6592 6593 err_create_eq_fail: 6594 for (i -= 1; i >= 0; i--) 6595 free_eq_buf(hr_dev, &eq_table->eq[i]); 6596 kfree(eq_table->eq); 6597 6598 return ret; 6599 } 6600 6601 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6602 { 6603 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6604 int eq_num; 6605 int i; 6606 6607 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6608 6609 /* Disable irq */ 6610 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6611 6612 __hns_roce_free_irq(hr_dev); 6613 destroy_workqueue(hr_dev->irq_workq); 6614 6615 for (i = 0; i < eq_num; i++) { 6616 hns_roce_v2_destroy_eqc(hr_dev, i); 6617 6618 free_eq_buf(hr_dev, &eq_table->eq[i]); 6619 } 6620 6621 kfree(eq_table->eq); 6622 } 6623 6624 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6625 .destroy_qp = hns_roce_v2_destroy_qp, 6626 .modify_cq = hns_roce_v2_modify_cq, 6627 .poll_cq = hns_roce_v2_poll_cq, 6628 .post_recv = hns_roce_v2_post_recv, 6629 .post_send = hns_roce_v2_post_send, 6630 .query_qp = hns_roce_v2_query_qp, 6631 .req_notify_cq = hns_roce_v2_req_notify_cq, 6632 }; 6633 6634 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6635 .modify_srq = hns_roce_v2_modify_srq, 6636 .post_srq_recv = hns_roce_v2_post_srq_recv, 6637 .query_srq = hns_roce_v2_query_srq, 6638 }; 6639 6640 static const struct hns_roce_hw hns_roce_hw_v2 = { 6641 .cmq_init = hns_roce_v2_cmq_init, 6642 .cmq_exit = hns_roce_v2_cmq_exit, 6643 .hw_profile = hns_roce_v2_profile, 6644 .hw_init = hns_roce_v2_init, 6645 .hw_exit = hns_roce_v2_exit, 6646 .post_mbox = v2_post_mbox, 6647 .poll_mbox_done = v2_poll_mbox_done, 6648 .chk_mbox_avail = v2_chk_mbox_is_avail, 6649 .set_gid = hns_roce_v2_set_gid, 6650 .set_mac = hns_roce_v2_set_mac, 6651 .write_mtpt = hns_roce_v2_write_mtpt, 6652 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6653 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6654 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6655 .write_cqc = hns_roce_v2_write_cqc, 6656 .set_hem = hns_roce_v2_set_hem, 6657 .clear_hem = hns_roce_v2_clear_hem, 6658 .modify_qp = hns_roce_v2_modify_qp, 6659 .dereg_mr = hns_roce_v2_dereg_mr, 6660 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6661 .init_eq = hns_roce_v2_init_eq_table, 6662 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6663 .write_srqc = hns_roce_v2_write_srqc, 6664 .query_cqc = hns_roce_v2_query_cqc, 6665 .query_qpc = hns_roce_v2_query_qpc, 6666 .query_mpt = hns_roce_v2_query_mpt, 6667 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6668 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6669 }; 6670 6671 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6672 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6673 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6674 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6675 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6676 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6677 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6678 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6679 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6680 /* required last entry */ 6681 {0, } 6682 }; 6683 6684 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6685 6686 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6687 struct hnae3_handle *handle) 6688 { 6689 struct hns_roce_v2_priv *priv = hr_dev->priv; 6690 const struct pci_device_id *id; 6691 int i; 6692 6693 hr_dev->pci_dev = handle->pdev; 6694 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6695 hr_dev->is_vf = id->driver_data; 6696 hr_dev->dev = &handle->pdev->dev; 6697 hr_dev->hw = &hns_roce_hw_v2; 6698 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6699 hr_dev->odb_offset = hr_dev->sdb_offset; 6700 6701 /* Get info from NIC driver. */ 6702 hr_dev->reg_base = handle->rinfo.roce_io_base; 6703 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6704 hr_dev->caps.num_ports = 1; 6705 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6706 hr_dev->iboe.phy_port[0] = 0; 6707 6708 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6709 hr_dev->iboe.netdevs[0]->dev_addr); 6710 6711 for (i = 0; i < handle->rinfo.num_vectors; i++) 6712 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6713 i + handle->rinfo.base_vector); 6714 6715 /* cmd issue mode: 0 is poll, 1 is event */ 6716 hr_dev->cmd_mod = 1; 6717 hr_dev->loop_idc = 0; 6718 6719 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6720 priv->handle = handle; 6721 } 6722 6723 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6724 { 6725 struct hns_roce_dev *hr_dev; 6726 int ret; 6727 6728 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6729 if (!hr_dev) 6730 return -ENOMEM; 6731 6732 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6733 if (!hr_dev->priv) { 6734 ret = -ENOMEM; 6735 goto error_failed_kzalloc; 6736 } 6737 6738 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6739 6740 ret = hns_roce_init(hr_dev); 6741 if (ret) { 6742 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6743 goto error_failed_cfg; 6744 } 6745 6746 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6747 ret = free_mr_init(hr_dev); 6748 if (ret) { 6749 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6750 goto error_failed_roce_init; 6751 } 6752 } 6753 6754 handle->priv = hr_dev; 6755 6756 return 0; 6757 6758 error_failed_roce_init: 6759 hns_roce_exit(hr_dev); 6760 6761 error_failed_cfg: 6762 kfree(hr_dev->priv); 6763 6764 error_failed_kzalloc: 6765 ib_dealloc_device(&hr_dev->ib_dev); 6766 6767 return ret; 6768 } 6769 6770 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6771 bool reset) 6772 { 6773 struct hns_roce_dev *hr_dev = handle->priv; 6774 6775 if (!hr_dev) 6776 return; 6777 6778 handle->priv = NULL; 6779 6780 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6781 hns_roce_handle_device_err(hr_dev); 6782 6783 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6784 free_mr_exit(hr_dev); 6785 6786 hns_roce_exit(hr_dev); 6787 kfree(hr_dev->priv); 6788 ib_dealloc_device(&hr_dev->ib_dev); 6789 } 6790 6791 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6792 { 6793 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6794 const struct pci_device_id *id; 6795 struct device *dev = &handle->pdev->dev; 6796 int ret; 6797 6798 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6799 6800 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6801 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6802 goto reset_chk_err; 6803 } 6804 6805 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6806 if (!id) 6807 return 0; 6808 6809 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6810 return 0; 6811 6812 ret = __hns_roce_hw_v2_init_instance(handle); 6813 if (ret) { 6814 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6815 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6816 if (ops->ae_dev_resetting(handle) || 6817 ops->get_hw_reset_stat(handle)) 6818 goto reset_chk_err; 6819 else 6820 return ret; 6821 } 6822 6823 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6824 6825 return 0; 6826 6827 reset_chk_err: 6828 dev_err(dev, "Device is busy in resetting state.\n" 6829 "please retry later.\n"); 6830 6831 return -EBUSY; 6832 } 6833 6834 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6835 bool reset) 6836 { 6837 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6838 return; 6839 6840 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6841 6842 __hns_roce_hw_v2_uninit_instance(handle, reset); 6843 6844 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6845 } 6846 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6847 { 6848 struct hns_roce_dev *hr_dev; 6849 6850 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6851 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6852 return 0; 6853 } 6854 6855 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6856 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6857 6858 hr_dev = handle->priv; 6859 if (!hr_dev) 6860 return 0; 6861 6862 hr_dev->active = false; 6863 hr_dev->dis_db = true; 6864 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6865 6866 return 0; 6867 } 6868 6869 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6870 { 6871 struct device *dev = &handle->pdev->dev; 6872 int ret; 6873 6874 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6875 &handle->rinfo.state)) { 6876 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6877 return 0; 6878 } 6879 6880 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6881 6882 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6883 ret = __hns_roce_hw_v2_init_instance(handle); 6884 if (ret) { 6885 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6886 * callback function, RoCE Engine reinitialize. If RoCE reinit 6887 * failed, we should inform NIC driver. 6888 */ 6889 handle->priv = NULL; 6890 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6891 } else { 6892 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6893 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6894 } 6895 6896 return ret; 6897 } 6898 6899 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6900 { 6901 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6902 return 0; 6903 6904 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6905 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6906 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6907 __hns_roce_hw_v2_uninit_instance(handle, false); 6908 6909 return 0; 6910 } 6911 6912 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6913 enum hnae3_reset_notify_type type) 6914 { 6915 int ret = 0; 6916 6917 switch (type) { 6918 case HNAE3_DOWN_CLIENT: 6919 ret = hns_roce_hw_v2_reset_notify_down(handle); 6920 break; 6921 case HNAE3_INIT_CLIENT: 6922 ret = hns_roce_hw_v2_reset_notify_init(handle); 6923 break; 6924 case HNAE3_UNINIT_CLIENT: 6925 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6926 break; 6927 default: 6928 break; 6929 } 6930 6931 return ret; 6932 } 6933 6934 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6935 .init_instance = hns_roce_hw_v2_init_instance, 6936 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6937 .reset_notify = hns_roce_hw_v2_reset_notify, 6938 }; 6939 6940 static struct hnae3_client hns_roce_hw_v2_client = { 6941 .name = "hns_roce_hw_v2", 6942 .type = HNAE3_CLIENT_ROCE, 6943 .ops = &hns_roce_hw_v2_ops, 6944 }; 6945 6946 static int __init hns_roce_hw_v2_init(void) 6947 { 6948 return hnae3_register_client(&hns_roce_hw_v2_client); 6949 } 6950 6951 static void __exit hns_roce_hw_v2_exit(void) 6952 { 6953 hnae3_unregister_client(&hns_roce_hw_v2_client); 6954 } 6955 6956 module_init(hns_roce_hw_v2_init); 6957 module_exit(hns_roce_hw_v2_exit); 6958 6959 MODULE_LICENSE("Dual BSD/GPL"); 6960 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6961 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6962 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6963 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6964