1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (mtu < 0 || len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 377 if (unlikely(hr_qp->state == IB_QPS_RESET || 378 hr_qp->state == IB_QPS_INIT || 379 hr_qp->state == IB_QPS_RTR)) { 380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 381 hr_qp->state); 382 return -EINVAL; 383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 385 hr_dev->state); 386 return -EIO; 387 } 388 389 return 0; 390 } 391 392 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 393 unsigned int *sge_len) 394 { 395 unsigned int valid_num = 0; 396 unsigned int len = 0; 397 int i; 398 399 for (i = 0; i < wr->num_sge; i++) { 400 if (likely(wr->sg_list[i].length)) { 401 len += wr->sg_list[i].length; 402 valid_num++; 403 } 404 } 405 406 *sge_len = len; 407 return valid_num; 408 } 409 410 static __le32 get_immtdata(const struct ib_send_wr *wr) 411 { 412 switch (wr->opcode) { 413 case IB_WR_SEND_WITH_IMM: 414 case IB_WR_RDMA_WRITE_WITH_IMM: 415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 416 default: 417 return 0; 418 } 419 } 420 421 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 422 const struct ib_send_wr *wr) 423 { 424 u32 ib_op = wr->opcode; 425 426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 427 return -EINVAL; 428 429 ud_sq_wqe->immtdata = get_immtdata(wr); 430 431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 432 433 return 0; 434 } 435 436 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 437 struct hns_roce_ah *ah) 438 { 439 struct ib_device *ib_dev = ah->ibah.device; 440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 441 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 446 447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 448 return -EINVAL; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 451 452 ud_sq_wqe->sgid_index = ah->av.gid_index; 453 454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 456 457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 458 return 0; 459 460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 462 463 return 0; 464 } 465 466 static inline int set_ud_wqe(struct hns_roce_qp *qp, 467 const struct ib_send_wr *wr, 468 void *wqe, unsigned int *sge_idx, 469 unsigned int owner_bit) 470 { 471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 473 unsigned int curr_idx = *sge_idx; 474 unsigned int valid_num_sge; 475 u32 msg_len = 0; 476 int ret; 477 478 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 479 480 ret = set_ud_opcode(ud_sq_wqe, wr); 481 if (WARN_ON(ret)) 482 return ret; 483 484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 485 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 487 !!(wr->send_flags & IB_SEND_SIGNALED)); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 489 !!(wr->send_flags & IB_SEND_SOLICITED)); 490 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 494 curr_idx & (qp->sge.sge_cnt - 1)); 495 496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 497 qp->qkey : ud_wr(wr)->remote_qkey); 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 519 520 return 0; 521 } 522 523 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 525 const struct ib_send_wr *wr) 526 { 527 u32 ib_op = wr->opcode; 528 int ret = 0; 529 530 rc_sq_wqe->immtdata = get_immtdata(wr); 531 532 switch (ib_op) { 533 case IB_WR_RDMA_READ: 534 case IB_WR_RDMA_WRITE: 535 case IB_WR_RDMA_WRITE_WITH_IMM: 536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 538 break; 539 case IB_WR_SEND: 540 case IB_WR_SEND_WITH_IMM: 541 break; 542 case IB_WR_ATOMIC_CMP_AND_SWP: 543 case IB_WR_ATOMIC_FETCH_AND_ADD: 544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 546 break; 547 case IB_WR_REG_MR: 548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 549 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 550 else 551 ret = -EOPNOTSUPP; 552 break; 553 case IB_WR_SEND_WITH_INV: 554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 555 break; 556 default: 557 ret = -EINVAL; 558 } 559 560 if (unlikely(ret)) 561 return ret; 562 563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 564 565 return ret; 566 } 567 568 static inline int set_rc_wqe(struct hns_roce_qp *qp, 569 const struct ib_send_wr *wr, 570 void *wqe, unsigned int *sge_idx, 571 unsigned int owner_bit) 572 { 573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 575 unsigned int curr_idx = *sge_idx; 576 unsigned int valid_num_sge; 577 u32 msg_len = 0; 578 int ret; 579 580 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 581 582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 583 584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 585 if (WARN_ON(ret)) 586 return ret; 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 593 594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 596 597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 599 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 600 else if (wr->opcode != IB_WR_REG_MR) 601 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 602 &curr_idx, valid_num_sge); 603 604 /* 605 * The pipeline can sequentially post all valid WQEs into WQ buffer, 606 * including new WQEs waiting for the doorbell to update the PI again. 607 * Therefore, the owner bit of WQE MUST be updated after all fields 608 * and extSGEs have been written into DDR instead of cache. 609 */ 610 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 611 dma_wmb(); 612 613 *sge_idx = curr_idx; 614 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 615 616 return ret; 617 } 618 619 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 620 struct hns_roce_qp *qp) 621 { 622 if (unlikely(qp->state == IB_QPS_ERR)) { 623 flush_cqe(hr_dev, qp); 624 } else { 625 struct hns_roce_v2_db sq_db = {}; 626 627 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 628 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 629 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 630 hr_reg_write(&sq_db, DB_SL, qp->sl); 631 632 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 633 } 634 } 635 636 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 637 struct hns_roce_qp *qp) 638 { 639 if (unlikely(qp->state == IB_QPS_ERR)) { 640 flush_cqe(hr_dev, qp); 641 } else { 642 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 643 *qp->rdb.db_record = 644 qp->rq.head & V2_DB_PRODUCER_IDX_M; 645 } else { 646 struct hns_roce_v2_db rq_db = {}; 647 648 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 649 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 650 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 651 652 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 653 qp->rq.db_reg); 654 } 655 } 656 } 657 658 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 659 u64 __iomem *dest) 660 { 661 #define HNS_ROCE_WRITE_TIMES 8 662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 663 struct hnae3_handle *handle = priv->handle; 664 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 665 int i; 666 667 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 668 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 669 writeq_relaxed(*(val + i), dest + i); 670 } 671 672 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 673 void *wqe) 674 { 675 #define HNS_ROCE_SL_SHIFT 2 676 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 677 678 /* All kinds of DirectWQE have the same header field layout */ 679 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 682 qp->sl >> HNS_ROCE_SL_SHIFT); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 684 685 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 686 } 687 688 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 689 const struct ib_send_wr *wr, 690 const struct ib_send_wr **bad_wr) 691 { 692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 693 struct ib_device *ibdev = &hr_dev->ib_dev; 694 struct hns_roce_qp *qp = to_hr_qp(ibqp); 695 unsigned long flags = 0; 696 unsigned int owner_bit; 697 unsigned int sge_idx; 698 unsigned int wqe_idx; 699 void *wqe = NULL; 700 u32 nreq; 701 int ret; 702 703 spin_lock_irqsave(&qp->sq.lock, flags); 704 705 ret = check_send_valid(hr_dev, qp); 706 if (unlikely(ret)) { 707 *bad_wr = wr; 708 nreq = 0; 709 goto out; 710 } 711 712 sge_idx = qp->next_sge; 713 714 for (nreq = 0; wr; ++nreq, wr = wr->next) { 715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 716 ret = -ENOMEM; 717 *bad_wr = wr; 718 goto out; 719 } 720 721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 722 723 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 725 wr->num_sge, qp->sq.max_gs); 726 ret = -EINVAL; 727 *bad_wr = wr; 728 goto out; 729 } 730 731 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 732 qp->sq.wrid[wqe_idx] = wr->wr_id; 733 owner_bit = 734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 735 736 /* Corresponding to the QP type, wqe process separately */ 737 if (ibqp->qp_type == IB_QPT_RC) 738 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 else 740 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 742 if (unlikely(ret)) { 743 *bad_wr = wr; 744 goto out; 745 } 746 } 747 748 out: 749 if (likely(nreq)) { 750 qp->sq.head += nreq; 751 qp->next_sge = sge_idx; 752 753 if (nreq == 1 && !ret && 754 (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 755 write_dwqe(hr_dev, qp, wqe); 756 else 757 update_sq_db(hr_dev, qp); 758 } 759 760 spin_unlock_irqrestore(&qp->sq.lock, flags); 761 762 return ret; 763 } 764 765 static int check_recv_valid(struct hns_roce_dev *hr_dev, 766 struct hns_roce_qp *hr_qp) 767 { 768 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 769 return -EIO; 770 771 if (hr_qp->state == IB_QPS_RESET) 772 return -EINVAL; 773 774 return 0; 775 } 776 777 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 778 u32 max_sge, bool rsv) 779 { 780 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 781 u32 i, cnt; 782 783 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 784 /* Skip zero-length sge */ 785 if (!wr->sg_list[i].length) 786 continue; 787 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 788 cnt++; 789 } 790 791 /* Fill a reserved sge to make hw stop reading remaining segments */ 792 if (rsv) { 793 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 794 dseg[cnt].addr = 0; 795 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 796 } else { 797 /* Clear remaining segments to make ROCEE ignore sges */ 798 if (cnt < max_sge) 799 memset(dseg + cnt, 0, 800 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 801 } 802 } 803 804 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 805 u32 wqe_idx, u32 max_sge) 806 { 807 void *wqe = NULL; 808 809 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 810 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 811 } 812 813 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 814 const struct ib_recv_wr *wr, 815 const struct ib_recv_wr **bad_wr) 816 { 817 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 818 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 819 struct ib_device *ibdev = &hr_dev->ib_dev; 820 u32 wqe_idx, nreq, max_sge; 821 unsigned long flags; 822 int ret; 823 824 spin_lock_irqsave(&hr_qp->rq.lock, flags); 825 826 ret = check_recv_valid(hr_dev, hr_qp); 827 if (unlikely(ret)) { 828 *bad_wr = wr; 829 nreq = 0; 830 goto out; 831 } 832 833 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 834 for (nreq = 0; wr; ++nreq, wr = wr->next) { 835 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 836 hr_qp->ibqp.recv_cq))) { 837 ret = -ENOMEM; 838 *bad_wr = wr; 839 goto out; 840 } 841 842 if (unlikely(wr->num_sge > max_sge)) { 843 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 844 wr->num_sge, max_sge); 845 ret = -EINVAL; 846 *bad_wr = wr; 847 goto out; 848 } 849 850 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 851 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 852 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 853 } 854 855 out: 856 if (likely(nreq)) { 857 hr_qp->rq.head += nreq; 858 859 update_rq_db(hr_dev, hr_qp); 860 } 861 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 862 863 return ret; 864 } 865 866 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 867 { 868 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 869 } 870 871 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 872 { 873 return hns_roce_buf_offset(idx_que->mtr.kmem, 874 n << idx_que->entry_shift); 875 } 876 877 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 878 { 879 /* always called with interrupts disabled. */ 880 spin_lock(&srq->lock); 881 882 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 883 srq->idx_que.tail++; 884 885 spin_unlock(&srq->lock); 886 } 887 888 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 889 { 890 struct hns_roce_idx_que *idx_que = &srq->idx_que; 891 892 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 893 } 894 895 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 896 const struct ib_recv_wr *wr) 897 { 898 struct ib_device *ib_dev = srq->ibsrq.device; 899 900 if (unlikely(wr->num_sge > max_sge)) { 901 ibdev_err(ib_dev, 902 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 903 wr->num_sge, max_sge); 904 return -EINVAL; 905 } 906 907 if (unlikely(hns_roce_srqwq_overflow(srq))) { 908 ibdev_err(ib_dev, 909 "failed to check srqwq status, srqwq is full.\n"); 910 return -ENOMEM; 911 } 912 913 return 0; 914 } 915 916 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 917 { 918 struct hns_roce_idx_que *idx_que = &srq->idx_que; 919 u32 pos; 920 921 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 922 if (unlikely(pos == srq->wqe_cnt)) 923 return -ENOSPC; 924 925 bitmap_set(idx_que->bitmap, pos, 1); 926 *wqe_idx = pos; 927 return 0; 928 } 929 930 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 931 { 932 struct hns_roce_idx_que *idx_que = &srq->idx_que; 933 unsigned int head; 934 __le32 *buf; 935 936 head = idx_que->head & (srq->wqe_cnt - 1); 937 938 buf = get_idx_buf(idx_que, head); 939 *buf = cpu_to_le32(wqe_idx); 940 941 idx_que->head++; 942 } 943 944 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 945 { 946 hr_reg_write(db, DB_TAG, srq->srqn); 947 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 948 hr_reg_write(db, DB_PI, srq->idx_que.head); 949 } 950 951 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 952 const struct ib_recv_wr *wr, 953 const struct ib_recv_wr **bad_wr) 954 { 955 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 956 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 957 struct hns_roce_v2_db srq_db; 958 unsigned long flags; 959 int ret = 0; 960 u32 max_sge; 961 u32 wqe_idx; 962 void *wqe; 963 u32 nreq; 964 965 spin_lock_irqsave(&srq->lock, flags); 966 967 max_sge = srq->max_gs - srq->rsv_sge; 968 for (nreq = 0; wr; ++nreq, wr = wr->next) { 969 ret = check_post_srq_valid(srq, max_sge, wr); 970 if (ret) { 971 *bad_wr = wr; 972 break; 973 } 974 975 ret = get_srq_wqe_idx(srq, &wqe_idx); 976 if (unlikely(ret)) { 977 *bad_wr = wr; 978 break; 979 } 980 981 wqe = get_srq_wqe_buf(srq, wqe_idx); 982 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 983 fill_wqe_idx(srq, wqe_idx); 984 srq->wrid[wqe_idx] = wr->wr_id; 985 } 986 987 if (likely(nreq)) { 988 update_srq_db(&srq_db, srq); 989 990 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 991 } 992 993 spin_unlock_irqrestore(&srq->lock, flags); 994 995 return ret; 996 } 997 998 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 999 unsigned long instance_stage, 1000 unsigned long reset_stage) 1001 { 1002 /* When hardware reset has been completed once or more, we should stop 1003 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1004 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1005 * stage of soft reset process, we should exit with error, and then 1006 * HNAE3_INIT_CLIENT related process can rollback the operation like 1007 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1008 * process will exit with error to notify NIC driver to reschedule soft 1009 * reset process once again. 1010 */ 1011 hr_dev->is_reset = true; 1012 hr_dev->dis_db = true; 1013 1014 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1015 instance_stage == HNS_ROCE_STATE_INIT) 1016 return CMD_RST_PRC_EBUSY; 1017 1018 return CMD_RST_PRC_SUCCESS; 1019 } 1020 1021 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1022 unsigned long instance_stage, 1023 unsigned long reset_stage) 1024 { 1025 #define HW_RESET_TIMEOUT_US 1000000 1026 #define HW_RESET_SLEEP_US 1000 1027 1028 struct hns_roce_v2_priv *priv = hr_dev->priv; 1029 struct hnae3_handle *handle = priv->handle; 1030 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1031 unsigned long val; 1032 int ret; 1033 1034 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1035 * doorbell to hardware. If now in .init_instance() function, we should 1036 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1037 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1038 * related process can rollback the operation like notifing hardware to 1039 * free resources, HNAE3_INIT_CLIENT related process will exit with 1040 * error to notify NIC driver to reschedule soft reset process once 1041 * again. 1042 */ 1043 hr_dev->dis_db = true; 1044 1045 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1046 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1047 HW_RESET_TIMEOUT_US, false, handle); 1048 if (!ret) 1049 hr_dev->is_reset = true; 1050 1051 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1052 instance_stage == HNS_ROCE_STATE_INIT) 1053 return CMD_RST_PRC_EBUSY; 1054 1055 return CMD_RST_PRC_SUCCESS; 1056 } 1057 1058 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1059 { 1060 struct hns_roce_v2_priv *priv = hr_dev->priv; 1061 struct hnae3_handle *handle = priv->handle; 1062 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1063 1064 /* When software reset is detected at .init_instance() function, we 1065 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1066 * with error. 1067 */ 1068 hr_dev->dis_db = true; 1069 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1070 hr_dev->is_reset = true; 1071 1072 return CMD_RST_PRC_EBUSY; 1073 } 1074 1075 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1076 struct hnae3_handle *handle) 1077 { 1078 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1079 unsigned long instance_stage; /* the current instance stage */ 1080 unsigned long reset_stage; /* the current reset stage */ 1081 unsigned long reset_cnt; 1082 bool sw_resetting; 1083 bool hw_resetting; 1084 1085 /* Get information about reset from NIC driver or RoCE driver itself, 1086 * the meaning of the following variables from NIC driver are described 1087 * as below: 1088 * reset_cnt -- The count value of completed hardware reset. 1089 * hw_resetting -- Whether hardware device is resetting now. 1090 * sw_resetting -- Whether NIC's software reset process is running now. 1091 */ 1092 instance_stage = handle->rinfo.instance_state; 1093 reset_stage = handle->rinfo.reset_state; 1094 reset_cnt = ops->ae_dev_reset_cnt(handle); 1095 if (reset_cnt != hr_dev->reset_cnt) 1096 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1097 reset_stage); 1098 1099 hw_resetting = ops->get_cmdq_stat(handle); 1100 if (hw_resetting) 1101 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1102 reset_stage); 1103 1104 sw_resetting = ops->ae_dev_resetting(handle); 1105 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1106 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1107 1108 return CMD_RST_PRC_OTHERS; 1109 } 1110 1111 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1112 { 1113 struct hns_roce_v2_priv *priv = hr_dev->priv; 1114 struct hnae3_handle *handle = priv->handle; 1115 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1116 1117 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1118 return true; 1119 1120 if (ops->get_hw_reset_stat(handle)) 1121 return true; 1122 1123 if (ops->ae_dev_resetting(handle)) 1124 return true; 1125 1126 return false; 1127 } 1128 1129 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1130 { 1131 struct hns_roce_v2_priv *priv = hr_dev->priv; 1132 u32 status; 1133 1134 if (hr_dev->is_reset) 1135 status = CMD_RST_PRC_SUCCESS; 1136 else 1137 status = check_aedev_reset_status(hr_dev, priv->handle); 1138 1139 *busy = (status == CMD_RST_PRC_EBUSY); 1140 1141 return status == CMD_RST_PRC_OTHERS; 1142 } 1143 1144 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1145 struct hns_roce_v2_cmq_ring *ring) 1146 { 1147 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1148 1149 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1150 &ring->desc_dma_addr, GFP_KERNEL); 1151 if (!ring->desc) 1152 return -ENOMEM; 1153 1154 return 0; 1155 } 1156 1157 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1158 struct hns_roce_v2_cmq_ring *ring) 1159 { 1160 dma_free_coherent(hr_dev->dev, 1161 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1162 ring->desc, ring->desc_dma_addr); 1163 1164 ring->desc_dma_addr = 0; 1165 } 1166 1167 static int init_csq(struct hns_roce_dev *hr_dev, 1168 struct hns_roce_v2_cmq_ring *csq) 1169 { 1170 dma_addr_t dma; 1171 int ret; 1172 1173 csq->desc_num = CMD_CSQ_DESC_NUM; 1174 spin_lock_init(&csq->lock); 1175 csq->flag = TYPE_CSQ; 1176 csq->head = 0; 1177 1178 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1179 if (ret) 1180 return ret; 1181 1182 dma = csq->desc_dma_addr; 1183 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1184 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1185 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1186 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1187 1188 /* Make sure to write CI first and then PI */ 1189 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1190 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1191 1192 return 0; 1193 } 1194 1195 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1196 { 1197 struct hns_roce_v2_priv *priv = hr_dev->priv; 1198 int ret; 1199 1200 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1201 1202 ret = init_csq(hr_dev, &priv->cmq.csq); 1203 if (ret) 1204 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1205 1206 return ret; 1207 } 1208 1209 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1210 { 1211 struct hns_roce_v2_priv *priv = hr_dev->priv; 1212 1213 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1214 } 1215 1216 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1217 enum hns_roce_opcode_type opcode, 1218 bool is_read) 1219 { 1220 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1221 desc->opcode = cpu_to_le16(opcode); 1222 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1223 if (is_read) 1224 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1225 else 1226 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1227 } 1228 1229 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1230 { 1231 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1232 struct hns_roce_v2_priv *priv = hr_dev->priv; 1233 1234 return tail == priv->cmq.csq.head; 1235 } 1236 1237 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1238 { 1239 struct hns_roce_v2_priv *priv = hr_dev->priv; 1240 struct hnae3_handle *handle = priv->handle; 1241 1242 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1243 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1244 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1245 } 1246 1247 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1248 { 1249 struct hns_roce_cmd_errcode errcode_table[] = { 1250 {CMD_EXEC_SUCCESS, 0}, 1251 {CMD_NO_AUTH, -EPERM}, 1252 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1253 {CMD_CRQ_FULL, -EXFULL}, 1254 {CMD_NEXT_ERR, -ENOSR}, 1255 {CMD_NOT_EXEC, -ENOTBLK}, 1256 {CMD_PARA_ERR, -EINVAL}, 1257 {CMD_RESULT_ERR, -ERANGE}, 1258 {CMD_TIMEOUT, -ETIME}, 1259 {CMD_HILINK_ERR, -ENOLINK}, 1260 {CMD_INFO_ILLEGAL, -ENXIO}, 1261 {CMD_INVALID, -EBADR}, 1262 }; 1263 u16 i; 1264 1265 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1266 if (desc_ret == errcode_table[i].return_status) 1267 return errcode_table[i].errno; 1268 return -EIO; 1269 } 1270 1271 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1272 struct hns_roce_cmq_desc *desc, int num) 1273 { 1274 struct hns_roce_v2_priv *priv = hr_dev->priv; 1275 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1276 u32 timeout = 0; 1277 u16 desc_ret; 1278 u32 tail; 1279 int ret; 1280 int i; 1281 1282 spin_lock_bh(&csq->lock); 1283 1284 tail = csq->head; 1285 1286 for (i = 0; i < num; i++) { 1287 csq->desc[csq->head++] = desc[i]; 1288 if (csq->head == csq->desc_num) 1289 csq->head = 0; 1290 } 1291 1292 /* Write to hardware */ 1293 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1294 1295 do { 1296 if (hns_roce_cmq_csq_done(hr_dev)) 1297 break; 1298 udelay(1); 1299 } while (++timeout < priv->cmq.tx_timeout); 1300 1301 if (hns_roce_cmq_csq_done(hr_dev)) { 1302 ret = 0; 1303 for (i = 0; i < num; i++) { 1304 /* check the result of hardware write back */ 1305 desc[i] = csq->desc[tail++]; 1306 if (tail == csq->desc_num) 1307 tail = 0; 1308 1309 desc_ret = le16_to_cpu(desc[i].retval); 1310 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1311 continue; 1312 1313 dev_err_ratelimited(hr_dev->dev, 1314 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1315 desc->opcode, desc_ret); 1316 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1317 } 1318 } else { 1319 /* FW/HW reset or incorrect number of desc */ 1320 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1321 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1322 csq->head, tail); 1323 csq->head = tail; 1324 1325 update_cmdq_status(hr_dev); 1326 1327 ret = -EAGAIN; 1328 } 1329 1330 spin_unlock_bh(&csq->lock); 1331 1332 return ret; 1333 } 1334 1335 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1336 struct hns_roce_cmq_desc *desc, int num) 1337 { 1338 bool busy; 1339 int ret; 1340 1341 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1342 return -EIO; 1343 1344 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1345 return busy ? -EBUSY : 0; 1346 1347 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1348 if (ret) { 1349 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1350 return busy ? -EBUSY : 0; 1351 } 1352 1353 return ret; 1354 } 1355 1356 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1357 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1358 { 1359 struct hns_roce_cmd_mailbox *mbox; 1360 int ret; 1361 1362 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1363 if (IS_ERR(mbox)) 1364 return PTR_ERR(mbox); 1365 1366 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1367 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1368 return ret; 1369 } 1370 1371 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1372 { 1373 struct hns_roce_query_version *resp; 1374 struct hns_roce_cmq_desc desc; 1375 int ret; 1376 1377 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1378 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1379 if (ret) 1380 return ret; 1381 1382 resp = (struct hns_roce_query_version *)desc.data; 1383 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1384 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1385 1386 return 0; 1387 } 1388 1389 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1390 struct hnae3_handle *handle) 1391 { 1392 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1393 unsigned long end; 1394 1395 hr_dev->dis_db = true; 1396 1397 dev_warn(hr_dev->dev, 1398 "func clear is pending, device in resetting state.\n"); 1399 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1400 while (end) { 1401 if (!ops->get_hw_reset_stat(handle)) { 1402 hr_dev->is_reset = true; 1403 dev_info(hr_dev->dev, 1404 "func clear success after reset.\n"); 1405 return; 1406 } 1407 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1408 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1409 } 1410 1411 dev_warn(hr_dev->dev, "func clear failed.\n"); 1412 } 1413 1414 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1415 struct hnae3_handle *handle) 1416 { 1417 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1418 unsigned long end; 1419 1420 hr_dev->dis_db = true; 1421 1422 dev_warn(hr_dev->dev, 1423 "func clear is pending, device in resetting state.\n"); 1424 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1425 while (end) { 1426 if (ops->ae_dev_reset_cnt(handle) != 1427 hr_dev->reset_cnt) { 1428 hr_dev->is_reset = true; 1429 dev_info(hr_dev->dev, 1430 "func clear success after sw reset\n"); 1431 return; 1432 } 1433 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1434 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1435 } 1436 1437 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1438 } 1439 1440 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1441 int flag) 1442 { 1443 struct hns_roce_v2_priv *priv = hr_dev->priv; 1444 struct hnae3_handle *handle = priv->handle; 1445 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1446 1447 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1448 hr_dev->dis_db = true; 1449 hr_dev->is_reset = true; 1450 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1451 return; 1452 } 1453 1454 if (ops->get_hw_reset_stat(handle)) { 1455 func_clr_hw_resetting_state(hr_dev, handle); 1456 return; 1457 } 1458 1459 if (ops->ae_dev_resetting(handle) && 1460 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1461 func_clr_sw_resetting_state(hr_dev, handle); 1462 return; 1463 } 1464 1465 if (retval && !flag) 1466 dev_warn(hr_dev->dev, 1467 "func clear read failed, ret = %d.\n", retval); 1468 1469 dev_warn(hr_dev->dev, "func clear failed.\n"); 1470 } 1471 1472 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1473 { 1474 bool fclr_write_fail_flag = false; 1475 struct hns_roce_func_clear *resp; 1476 struct hns_roce_cmq_desc desc; 1477 unsigned long end; 1478 int ret = 0; 1479 1480 if (check_device_is_in_reset(hr_dev)) 1481 goto out; 1482 1483 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1484 resp = (struct hns_roce_func_clear *)desc.data; 1485 resp->rst_funcid_en = cpu_to_le32(vf_id); 1486 1487 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1488 if (ret) { 1489 fclr_write_fail_flag = true; 1490 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1491 ret); 1492 goto out; 1493 } 1494 1495 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1496 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1497 while (end) { 1498 if (check_device_is_in_reset(hr_dev)) 1499 goto out; 1500 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1501 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1502 1503 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1504 true); 1505 1506 resp->rst_funcid_en = cpu_to_le32(vf_id); 1507 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1508 if (ret) 1509 continue; 1510 1511 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1512 if (vf_id == 0) 1513 hr_dev->is_reset = true; 1514 return; 1515 } 1516 } 1517 1518 out: 1519 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1520 } 1521 1522 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1523 { 1524 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1525 struct hns_roce_cmq_desc desc[2]; 1526 struct hns_roce_cmq_req *req_a; 1527 1528 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1529 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1530 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1531 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1532 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1533 1534 return hns_roce_cmq_send(hr_dev, desc, 2); 1535 } 1536 1537 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1538 { 1539 int ret; 1540 int i; 1541 1542 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1543 return; 1544 1545 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1546 __hns_roce_function_clear(hr_dev, i); 1547 1548 if (i == 0) 1549 continue; 1550 1551 ret = hns_roce_free_vf_resource(hr_dev, i); 1552 if (ret) 1553 ibdev_err(&hr_dev->ib_dev, 1554 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1555 i, ret); 1556 } 1557 } 1558 1559 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1560 { 1561 struct hns_roce_cmq_desc desc; 1562 int ret; 1563 1564 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1565 false); 1566 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1567 if (ret) 1568 ibdev_err(&hr_dev->ib_dev, 1569 "failed to clear extended doorbell info, ret = %d.\n", 1570 ret); 1571 1572 return ret; 1573 } 1574 1575 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1576 { 1577 struct hns_roce_query_fw_info *resp; 1578 struct hns_roce_cmq_desc desc; 1579 int ret; 1580 1581 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1582 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1583 if (ret) 1584 return ret; 1585 1586 resp = (struct hns_roce_query_fw_info *)desc.data; 1587 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1588 1589 return 0; 1590 } 1591 1592 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1593 { 1594 struct hns_roce_cmq_desc desc; 1595 int ret; 1596 1597 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1598 hr_dev->func_num = 1; 1599 return 0; 1600 } 1601 1602 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1603 true); 1604 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1605 if (ret) { 1606 hr_dev->func_num = 1; 1607 return ret; 1608 } 1609 1610 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1611 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1612 1613 return 0; 1614 } 1615 1616 static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, 1617 u64 *stats, u32 port, int *num_counters) 1618 { 1619 #define CNT_PER_DESC 3 1620 struct hns_roce_cmq_desc *desc; 1621 int bd_idx, cnt_idx; 1622 __le64 *cnt_data; 1623 int desc_num; 1624 int ret; 1625 int i; 1626 1627 if (port > hr_dev->caps.num_ports) 1628 return -EINVAL; 1629 1630 desc_num = DIV_ROUND_UP(HNS_ROCE_HW_CNT_TOTAL, CNT_PER_DESC); 1631 desc = kcalloc(desc_num, sizeof(*desc), GFP_KERNEL); 1632 if (!desc) 1633 return -ENOMEM; 1634 1635 for (i = 0; i < desc_num; i++) { 1636 hns_roce_cmq_setup_basic_desc(&desc[i], 1637 HNS_ROCE_OPC_QUERY_COUNTER, true); 1638 if (i != desc_num - 1) 1639 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1640 } 1641 1642 ret = hns_roce_cmq_send(hr_dev, desc, desc_num); 1643 if (ret) { 1644 ibdev_err(&hr_dev->ib_dev, 1645 "failed to get counter, ret = %d.\n", ret); 1646 goto err_out; 1647 } 1648 1649 for (i = 0; i < HNS_ROCE_HW_CNT_TOTAL && i < *num_counters; i++) { 1650 bd_idx = i / CNT_PER_DESC; 1651 if (!(desc[bd_idx].flag & HNS_ROCE_CMD_FLAG_NEXT) && 1652 bd_idx != HNS_ROCE_HW_CNT_TOTAL / CNT_PER_DESC) 1653 break; 1654 1655 cnt_data = (__le64 *)&desc[bd_idx].data[0]; 1656 cnt_idx = i % CNT_PER_DESC; 1657 stats[i] = le64_to_cpu(cnt_data[cnt_idx]); 1658 } 1659 *num_counters = i; 1660 1661 err_out: 1662 kfree(desc); 1663 return ret; 1664 } 1665 1666 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1667 { 1668 struct hns_roce_cmq_desc desc; 1669 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1670 u32 clock_cycles_of_1us; 1671 1672 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1673 false); 1674 1675 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1676 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1677 else 1678 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1679 1680 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1681 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1682 1683 return hns_roce_cmq_send(hr_dev, &desc, 1); 1684 } 1685 1686 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1687 { 1688 struct hns_roce_cmq_desc desc[2]; 1689 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1690 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1691 struct hns_roce_caps *caps = &hr_dev->caps; 1692 enum hns_roce_opcode_type opcode; 1693 u32 func_num; 1694 int ret; 1695 1696 if (is_vf) { 1697 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1698 func_num = 1; 1699 } else { 1700 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1701 func_num = hr_dev->func_num; 1702 } 1703 1704 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1705 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1706 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1707 1708 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1709 if (ret) 1710 return ret; 1711 1712 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1713 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1714 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1715 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1716 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1717 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1718 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1719 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1720 1721 if (is_vf) { 1722 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1723 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1724 func_num; 1725 } else { 1726 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1727 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1728 func_num; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1735 { 1736 struct hns_roce_cmq_desc desc; 1737 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1738 struct hns_roce_caps *caps = &hr_dev->caps; 1739 int ret; 1740 1741 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1742 true); 1743 1744 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1745 if (ret) 1746 return ret; 1747 1748 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1749 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1750 1751 return 0; 1752 } 1753 1754 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1755 { 1756 struct device *dev = hr_dev->dev; 1757 int ret; 1758 1759 ret = load_func_res_caps(hr_dev, false); 1760 if (ret) { 1761 dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret); 1762 return ret; 1763 } 1764 1765 ret = load_pf_timer_res_caps(hr_dev); 1766 if (ret) 1767 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1768 ret); 1769 1770 return ret; 1771 } 1772 1773 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1774 { 1775 struct device *dev = hr_dev->dev; 1776 int ret; 1777 1778 ret = load_func_res_caps(hr_dev, true); 1779 if (ret) 1780 dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret); 1781 1782 return ret; 1783 } 1784 1785 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1786 u32 vf_id) 1787 { 1788 struct hns_roce_vf_switch *swt; 1789 struct hns_roce_cmq_desc desc; 1790 int ret; 1791 1792 swt = (struct hns_roce_vf_switch *)desc.data; 1793 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1794 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1795 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1796 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1797 if (ret) 1798 return ret; 1799 1800 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1801 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1802 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1803 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1804 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1805 1806 return hns_roce_cmq_send(hr_dev, &desc, 1); 1807 } 1808 1809 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1810 { 1811 u32 vf_id; 1812 int ret; 1813 1814 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1815 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1816 if (ret) 1817 return ret; 1818 } 1819 return 0; 1820 } 1821 1822 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1823 { 1824 struct hns_roce_cmq_desc desc[2]; 1825 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1826 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1827 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1828 struct hns_roce_caps *caps = &hr_dev->caps; 1829 1830 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1831 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1832 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1833 1834 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1835 1836 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1837 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1838 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1839 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1840 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1841 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1842 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1843 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1844 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1845 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1846 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1847 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1848 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1849 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1850 1851 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1852 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1853 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1854 vf_id * caps->gmv_bt_num); 1855 } else { 1856 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1857 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1858 vf_id * caps->sgid_bt_num); 1859 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1860 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1861 vf_id * caps->smac_bt_num); 1862 } 1863 1864 return hns_roce_cmq_send(hr_dev, desc, 2); 1865 } 1866 1867 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1868 { 1869 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1870 u32 vf_id; 1871 int ret; 1872 1873 for (vf_id = 0; vf_id < func_num; vf_id++) { 1874 ret = config_vf_hem_resource(hr_dev, vf_id); 1875 if (ret) { 1876 dev_err(hr_dev->dev, 1877 "failed to config vf-%u hem res, ret = %d.\n", 1878 vf_id, ret); 1879 return ret; 1880 } 1881 } 1882 1883 return 0; 1884 } 1885 1886 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1887 { 1888 struct hns_roce_cmq_desc desc; 1889 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1890 struct hns_roce_caps *caps = &hr_dev->caps; 1891 1892 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1893 1894 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1895 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1896 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1897 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1898 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1899 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1900 1901 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1902 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1903 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1904 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1905 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1906 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1907 1908 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1909 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1910 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1911 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1912 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1913 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1914 1915 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1916 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1917 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1918 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1919 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1920 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1921 1922 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1923 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1924 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1925 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1926 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1927 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1928 1929 return hns_roce_cmq_send(hr_dev, &desc, 1); 1930 } 1931 1932 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1933 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1934 { 1935 u64 obj_per_chunk; 1936 u64 bt_chunk_size = PAGE_SIZE; 1937 u64 buf_chunk_size = PAGE_SIZE; 1938 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1939 1940 *buf_page_size = 0; 1941 *bt_page_size = 0; 1942 1943 switch (hop_num) { 1944 case 3: 1945 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1946 (bt_chunk_size / BA_BYTE_LEN) * 1947 (bt_chunk_size / BA_BYTE_LEN) * 1948 obj_per_chunk_default; 1949 break; 1950 case 2: 1951 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1952 (bt_chunk_size / BA_BYTE_LEN) * 1953 obj_per_chunk_default; 1954 break; 1955 case 1: 1956 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1957 obj_per_chunk_default; 1958 break; 1959 case HNS_ROCE_HOP_NUM_0: 1960 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1961 break; 1962 default: 1963 pr_err("table %u not support hop_num = %u!\n", hem_type, 1964 hop_num); 1965 return; 1966 } 1967 1968 if (hem_type >= HEM_TYPE_MTT) 1969 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1970 else 1971 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1972 } 1973 1974 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 1975 { 1976 struct hns_roce_caps *caps = &hr_dev->caps; 1977 1978 /* EQ */ 1979 caps->eqe_ba_pg_sz = 0; 1980 caps->eqe_buf_pg_sz = 0; 1981 1982 /* Link Table */ 1983 caps->llm_buf_pg_sz = 0; 1984 1985 /* MR */ 1986 caps->mpt_ba_pg_sz = 0; 1987 caps->mpt_buf_pg_sz = 0; 1988 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 1989 caps->pbl_buf_pg_sz = 0; 1990 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1991 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1992 HEM_TYPE_MTPT); 1993 1994 /* QP */ 1995 caps->qpc_ba_pg_sz = 0; 1996 caps->qpc_buf_pg_sz = 0; 1997 caps->qpc_timer_ba_pg_sz = 0; 1998 caps->qpc_timer_buf_pg_sz = 0; 1999 caps->sccc_ba_pg_sz = 0; 2000 caps->sccc_buf_pg_sz = 0; 2001 caps->mtt_ba_pg_sz = 0; 2002 caps->mtt_buf_pg_sz = 0; 2003 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2004 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2005 HEM_TYPE_QPC); 2006 2007 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2008 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2009 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2010 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2011 2012 /* CQ */ 2013 caps->cqc_ba_pg_sz = 0; 2014 caps->cqc_buf_pg_sz = 0; 2015 caps->cqc_timer_ba_pg_sz = 0; 2016 caps->cqc_timer_buf_pg_sz = 0; 2017 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2018 caps->cqe_buf_pg_sz = 0; 2019 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2020 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2021 HEM_TYPE_CQC); 2022 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2023 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2024 2025 /* SRQ */ 2026 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2027 caps->srqc_ba_pg_sz = 0; 2028 caps->srqc_buf_pg_sz = 0; 2029 caps->srqwqe_ba_pg_sz = 0; 2030 caps->srqwqe_buf_pg_sz = 0; 2031 caps->idx_ba_pg_sz = 0; 2032 caps->idx_buf_pg_sz = 0; 2033 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2034 caps->srqc_hop_num, caps->srqc_bt_num, 2035 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2036 HEM_TYPE_SRQC); 2037 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2038 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2039 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2040 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2041 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2042 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2043 } 2044 2045 /* GMV */ 2046 caps->gmv_ba_pg_sz = 0; 2047 caps->gmv_buf_pg_sz = 0; 2048 } 2049 2050 /* Apply all loaded caps before setting to hardware */ 2051 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2052 { 2053 struct hns_roce_caps *caps = &hr_dev->caps; 2054 struct hns_roce_v2_priv *priv = hr_dev->priv; 2055 2056 /* The following configurations don't need to be got from firmware. */ 2057 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2058 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2059 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2060 2061 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2062 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2063 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2064 2065 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2066 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2067 2068 if (!caps->num_comp_vectors) 2069 caps->num_comp_vectors = 2070 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2071 (u32)priv->handle->rinfo.num_vectors - 2072 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2073 2074 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2075 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2076 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2077 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2078 2079 /* The following configurations will be overwritten */ 2080 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2081 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2082 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2083 2084 /* The following configurations are not got from firmware */ 2085 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2086 2087 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2088 caps->gid_table_len[0] = caps->gmv_bt_num * 2089 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2090 2091 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2092 caps->gmv_entry_sz); 2093 } else { 2094 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2095 2096 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2097 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2098 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2099 caps->gid_table_len[0] /= func_num; 2100 } 2101 2102 if (hr_dev->is_vf) { 2103 caps->default_aeq_arm_st = 0x3; 2104 caps->default_ceq_arm_st = 0x3; 2105 caps->default_ceq_max_cnt = 0x1; 2106 caps->default_ceq_period = 0x10; 2107 caps->default_aeq_max_cnt = 0x1; 2108 caps->default_aeq_period = 0x10; 2109 } 2110 2111 set_hem_page_size(hr_dev); 2112 } 2113 2114 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2115 { 2116 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2117 struct hns_roce_caps *caps = &hr_dev->caps; 2118 struct hns_roce_query_pf_caps_a *resp_a; 2119 struct hns_roce_query_pf_caps_b *resp_b; 2120 struct hns_roce_query_pf_caps_c *resp_c; 2121 struct hns_roce_query_pf_caps_d *resp_d; 2122 struct hns_roce_query_pf_caps_e *resp_e; 2123 enum hns_roce_opcode_type cmd; 2124 int ctx_hop_num; 2125 int pbl_hop_num; 2126 int ret; 2127 int i; 2128 2129 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2130 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2131 2132 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2133 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2134 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2135 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2136 else 2137 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2138 } 2139 2140 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2141 if (ret) 2142 return ret; 2143 2144 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2145 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2146 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2147 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2148 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2149 2150 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2151 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2152 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2153 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2154 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2155 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2156 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2157 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2158 caps->num_other_vectors = resp_a->num_other_vectors; 2159 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2160 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2161 2162 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2163 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2164 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2165 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2166 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2167 caps->idx_entry_sz = resp_b->idx_entry_sz; 2168 caps->sccc_sz = resp_b->sccc_sz; 2169 caps->max_mtu = resp_b->max_mtu; 2170 caps->min_cqes = resp_b->min_cqes; 2171 caps->min_wqes = resp_b->min_wqes; 2172 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2173 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2174 caps->phy_num_uars = resp_b->phy_num_uars; 2175 ctx_hop_num = resp_b->ctx_hop_num; 2176 pbl_hop_num = resp_b->pbl_hop_num; 2177 2178 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2179 2180 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2181 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2182 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2183 2184 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2185 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2186 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2187 caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS); 2188 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2189 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2190 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2191 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2192 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2193 2194 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2195 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2196 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2197 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2198 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2199 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2200 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2201 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2202 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2203 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2204 2205 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2206 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2207 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2208 caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS); 2209 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2210 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2211 2212 caps->qpc_hop_num = ctx_hop_num; 2213 caps->sccc_hop_num = ctx_hop_num; 2214 caps->srqc_hop_num = ctx_hop_num; 2215 caps->cqc_hop_num = ctx_hop_num; 2216 caps->mpt_hop_num = ctx_hop_num; 2217 caps->mtt_hop_num = pbl_hop_num; 2218 caps->cqe_hop_num = pbl_hop_num; 2219 caps->srqwqe_hop_num = pbl_hop_num; 2220 caps->idx_hop_num = pbl_hop_num; 2221 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2222 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2223 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2224 2225 if (!(caps->page_size_cap & PAGE_SIZE)) 2226 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2227 2228 if (!hr_dev->is_vf) { 2229 caps->cqe_sz = resp_a->cqe_sz; 2230 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2231 caps->default_aeq_arm_st = 2232 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2233 caps->default_ceq_arm_st = 2234 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2235 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2236 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2237 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2238 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2239 } 2240 2241 return 0; 2242 } 2243 2244 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2245 { 2246 struct hns_roce_cmq_desc desc; 2247 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2248 2249 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2250 false); 2251 2252 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2253 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2254 2255 return hns_roce_cmq_send(hr_dev, &desc, 1); 2256 } 2257 2258 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2259 { 2260 struct hns_roce_caps *caps = &hr_dev->caps; 2261 int ret; 2262 2263 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2264 return 0; 2265 2266 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2267 caps->qpc_sz); 2268 if (ret) { 2269 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2270 return ret; 2271 } 2272 2273 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2274 caps->sccc_sz); 2275 if (ret) 2276 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2277 2278 return ret; 2279 } 2280 2281 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2282 { 2283 struct device *dev = hr_dev->dev; 2284 int ret; 2285 2286 hr_dev->func_num = 1; 2287 2288 ret = hns_roce_query_caps(hr_dev); 2289 if (ret) { 2290 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2291 return ret; 2292 } 2293 2294 ret = hns_roce_query_vf_resource(hr_dev); 2295 if (ret) { 2296 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2297 return ret; 2298 } 2299 2300 apply_func_caps(hr_dev); 2301 2302 ret = hns_roce_v2_set_bt(hr_dev); 2303 if (ret) 2304 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2305 2306 return ret; 2307 } 2308 2309 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2310 { 2311 struct device *dev = hr_dev->dev; 2312 int ret; 2313 2314 ret = hns_roce_query_func_info(hr_dev); 2315 if (ret) { 2316 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2317 return ret; 2318 } 2319 2320 ret = hns_roce_config_global_param(hr_dev); 2321 if (ret) { 2322 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2323 return ret; 2324 } 2325 2326 ret = hns_roce_set_vf_switch_param(hr_dev); 2327 if (ret) { 2328 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2329 return ret; 2330 } 2331 2332 ret = hns_roce_query_caps(hr_dev); 2333 if (ret) { 2334 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2335 return ret; 2336 } 2337 2338 ret = hns_roce_query_pf_resource(hr_dev); 2339 if (ret) { 2340 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2341 return ret; 2342 } 2343 2344 apply_func_caps(hr_dev); 2345 2346 ret = hns_roce_alloc_vf_resource(hr_dev); 2347 if (ret) { 2348 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2349 return ret; 2350 } 2351 2352 ret = hns_roce_v2_set_bt(hr_dev); 2353 if (ret) { 2354 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2355 return ret; 2356 } 2357 2358 /* Configure the size of QPC, SCCC, etc. */ 2359 return hns_roce_config_entry_size(hr_dev); 2360 } 2361 2362 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2363 { 2364 struct device *dev = hr_dev->dev; 2365 int ret; 2366 2367 ret = hns_roce_cmq_query_hw_info(hr_dev); 2368 if (ret) { 2369 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2370 return ret; 2371 } 2372 2373 ret = hns_roce_query_fw_ver(hr_dev); 2374 if (ret) { 2375 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2376 return ret; 2377 } 2378 2379 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2380 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2381 2382 if (hr_dev->is_vf) 2383 return hns_roce_v2_vf_profile(hr_dev); 2384 else 2385 return hns_roce_v2_pf_profile(hr_dev); 2386 } 2387 2388 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2389 { 2390 u32 i, next_ptr, page_num; 2391 __le64 *entry = cfg_buf; 2392 dma_addr_t addr; 2393 u64 val; 2394 2395 page_num = data_buf->npages; 2396 for (i = 0; i < page_num; i++) { 2397 addr = hns_roce_buf_page(data_buf, i); 2398 if (i == (page_num - 1)) 2399 next_ptr = 0; 2400 else 2401 next_ptr = i + 1; 2402 2403 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2404 entry[i] = cpu_to_le64(val); 2405 } 2406 } 2407 2408 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2409 struct hns_roce_link_table *table) 2410 { 2411 struct hns_roce_cmq_desc desc[2]; 2412 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2413 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2414 struct hns_roce_buf *buf = table->buf; 2415 enum hns_roce_opcode_type opcode; 2416 dma_addr_t addr; 2417 2418 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2419 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2420 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2421 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2422 2423 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2424 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2425 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2426 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2427 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2428 2429 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2430 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2431 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2432 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2433 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2434 2435 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2436 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2437 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2438 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2439 2440 return hns_roce_cmq_send(hr_dev, desc, 2); 2441 } 2442 2443 static struct hns_roce_link_table * 2444 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2445 { 2446 struct hns_roce_v2_priv *priv = hr_dev->priv; 2447 struct hns_roce_link_table *link_tbl; 2448 u32 pg_shift, size, min_size; 2449 2450 link_tbl = &priv->ext_llm; 2451 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2452 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2453 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2454 2455 /* Alloc data table */ 2456 size = max(size, min_size); 2457 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2458 if (IS_ERR(link_tbl->buf)) 2459 return ERR_PTR(-ENOMEM); 2460 2461 /* Alloc config table */ 2462 size = link_tbl->buf->npages * sizeof(u64); 2463 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2464 &link_tbl->table.map, 2465 GFP_KERNEL); 2466 if (!link_tbl->table.buf) { 2467 hns_roce_buf_free(hr_dev, link_tbl->buf); 2468 return ERR_PTR(-ENOMEM); 2469 } 2470 2471 return link_tbl; 2472 } 2473 2474 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2475 struct hns_roce_link_table *tbl) 2476 { 2477 if (tbl->buf) { 2478 u32 size = tbl->buf->npages * sizeof(u64); 2479 2480 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2481 tbl->table.map); 2482 } 2483 2484 hns_roce_buf_free(hr_dev, tbl->buf); 2485 } 2486 2487 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2488 { 2489 struct hns_roce_link_table *link_tbl; 2490 int ret; 2491 2492 link_tbl = alloc_link_table_buf(hr_dev); 2493 if (IS_ERR(link_tbl)) 2494 return -ENOMEM; 2495 2496 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2497 ret = -EINVAL; 2498 goto err_alloc; 2499 } 2500 2501 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2502 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2503 if (ret) 2504 goto err_alloc; 2505 2506 return 0; 2507 2508 err_alloc: 2509 free_link_table_buf(hr_dev, link_tbl); 2510 return ret; 2511 } 2512 2513 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2514 { 2515 struct hns_roce_v2_priv *priv = hr_dev->priv; 2516 2517 free_link_table_buf(hr_dev, &priv->ext_llm); 2518 } 2519 2520 static void free_dip_list(struct hns_roce_dev *hr_dev) 2521 { 2522 struct hns_roce_dip *hr_dip; 2523 struct hns_roce_dip *tmp; 2524 unsigned long flags; 2525 2526 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2527 2528 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2529 list_del(&hr_dip->node); 2530 kfree(hr_dip); 2531 } 2532 2533 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2534 } 2535 2536 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2537 { 2538 struct hns_roce_v2_priv *priv = hr_dev->priv; 2539 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2540 struct ib_device *ibdev = &hr_dev->ib_dev; 2541 struct hns_roce_pd *hr_pd; 2542 struct ib_pd *pd; 2543 2544 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2545 if (ZERO_OR_NULL_PTR(hr_pd)) 2546 return NULL; 2547 pd = &hr_pd->ibpd; 2548 pd->device = ibdev; 2549 2550 if (hns_roce_alloc_pd(pd, NULL)) { 2551 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2552 kfree(hr_pd); 2553 return NULL; 2554 } 2555 free_mr->rsv_pd = to_hr_pd(pd); 2556 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2557 free_mr->rsv_pd->ibpd.uobject = NULL; 2558 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2559 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2560 2561 return pd; 2562 } 2563 2564 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2565 { 2566 struct hns_roce_v2_priv *priv = hr_dev->priv; 2567 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2568 struct ib_device *ibdev = &hr_dev->ib_dev; 2569 struct ib_cq_init_attr cq_init_attr = {}; 2570 struct hns_roce_cq *hr_cq; 2571 struct ib_cq *cq; 2572 2573 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2574 2575 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2576 if (ZERO_OR_NULL_PTR(hr_cq)) 2577 return NULL; 2578 2579 cq = &hr_cq->ib_cq; 2580 cq->device = ibdev; 2581 2582 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2583 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2584 kfree(hr_cq); 2585 return NULL; 2586 } 2587 free_mr->rsv_cq = to_hr_cq(cq); 2588 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2589 free_mr->rsv_cq->ib_cq.uobject = NULL; 2590 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2591 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2592 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2593 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2594 2595 return cq; 2596 } 2597 2598 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2599 struct ib_qp_init_attr *init_attr, int i) 2600 { 2601 struct hns_roce_v2_priv *priv = hr_dev->priv; 2602 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2603 struct ib_device *ibdev = &hr_dev->ib_dev; 2604 struct hns_roce_qp *hr_qp; 2605 struct ib_qp *qp; 2606 int ret; 2607 2608 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2609 if (ZERO_OR_NULL_PTR(hr_qp)) 2610 return -ENOMEM; 2611 2612 qp = &hr_qp->ibqp; 2613 qp->device = ibdev; 2614 2615 ret = hns_roce_create_qp(qp, init_attr, NULL); 2616 if (ret) { 2617 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2618 kfree(hr_qp); 2619 return ret; 2620 } 2621 2622 free_mr->rsv_qp[i] = hr_qp; 2623 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2624 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2625 2626 return 0; 2627 } 2628 2629 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2630 { 2631 struct hns_roce_v2_priv *priv = hr_dev->priv; 2632 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2633 struct ib_qp *qp; 2634 int i; 2635 2636 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2637 if (free_mr->rsv_qp[i]) { 2638 qp = &free_mr->rsv_qp[i]->ibqp; 2639 hns_roce_v2_destroy_qp(qp, NULL); 2640 kfree(free_mr->rsv_qp[i]); 2641 free_mr->rsv_qp[i] = NULL; 2642 } 2643 } 2644 2645 if (free_mr->rsv_cq) { 2646 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2647 kfree(free_mr->rsv_cq); 2648 free_mr->rsv_cq = NULL; 2649 } 2650 2651 if (free_mr->rsv_pd) { 2652 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2653 kfree(free_mr->rsv_pd); 2654 free_mr->rsv_pd = NULL; 2655 } 2656 } 2657 2658 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2659 { 2660 struct hns_roce_v2_priv *priv = hr_dev->priv; 2661 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2662 struct ib_qp_init_attr qp_init_attr = {}; 2663 struct ib_pd *pd; 2664 struct ib_cq *cq; 2665 int ret; 2666 int i; 2667 2668 pd = free_mr_init_pd(hr_dev); 2669 if (!pd) 2670 return -ENOMEM; 2671 2672 cq = free_mr_init_cq(hr_dev); 2673 if (!cq) { 2674 ret = -ENOMEM; 2675 goto create_failed_cq; 2676 } 2677 2678 qp_init_attr.qp_type = IB_QPT_RC; 2679 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2680 qp_init_attr.send_cq = cq; 2681 qp_init_attr.recv_cq = cq; 2682 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2683 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2684 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2685 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2686 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2687 2688 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2689 if (ret) 2690 goto create_failed_qp; 2691 } 2692 2693 return 0; 2694 2695 create_failed_qp: 2696 hns_roce_destroy_cq(cq, NULL); 2697 kfree(cq); 2698 2699 create_failed_cq: 2700 hns_roce_dealloc_pd(pd, NULL); 2701 kfree(pd); 2702 2703 return ret; 2704 } 2705 2706 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2707 struct ib_qp_attr *attr, int sl_num) 2708 { 2709 struct hns_roce_v2_priv *priv = hr_dev->priv; 2710 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2711 struct ib_device *ibdev = &hr_dev->ib_dev; 2712 struct hns_roce_qp *hr_qp; 2713 int loopback; 2714 int mask; 2715 int ret; 2716 2717 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2718 hr_qp->free_mr_en = 1; 2719 hr_qp->ibqp.device = ibdev; 2720 hr_qp->ibqp.qp_type = IB_QPT_RC; 2721 2722 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2723 attr->qp_state = IB_QPS_INIT; 2724 attr->port_num = 1; 2725 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2726 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2727 IB_QPS_INIT, NULL); 2728 if (ret) { 2729 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2730 ret); 2731 return ret; 2732 } 2733 2734 loopback = hr_dev->loop_idc; 2735 /* Set qpc lbi = 1 incidate loopback IO */ 2736 hr_dev->loop_idc = 1; 2737 2738 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2739 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2740 attr->qp_state = IB_QPS_RTR; 2741 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2742 attr->path_mtu = IB_MTU_256; 2743 attr->dest_qp_num = hr_qp->qpn; 2744 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2745 2746 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2747 2748 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2749 IB_QPS_RTR, NULL); 2750 hr_dev->loop_idc = loopback; 2751 if (ret) { 2752 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2753 ret); 2754 return ret; 2755 } 2756 2757 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2758 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2759 attr->qp_state = IB_QPS_RTS; 2760 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2761 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2762 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2763 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2764 IB_QPS_RTS, NULL); 2765 if (ret) 2766 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2767 ret); 2768 2769 return ret; 2770 } 2771 2772 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2773 { 2774 struct hns_roce_v2_priv *priv = hr_dev->priv; 2775 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2776 struct ib_qp_attr attr = {}; 2777 int ret; 2778 int i; 2779 2780 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2781 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2782 rdma_ah_set_port_num(&attr.ah_attr, 1); 2783 2784 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2785 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2786 if (ret) 2787 return ret; 2788 } 2789 2790 return 0; 2791 } 2792 2793 static int free_mr_init(struct hns_roce_dev *hr_dev) 2794 { 2795 struct hns_roce_v2_priv *priv = hr_dev->priv; 2796 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2797 int ret; 2798 2799 mutex_init(&free_mr->mutex); 2800 2801 ret = free_mr_alloc_res(hr_dev); 2802 if (ret) 2803 return ret; 2804 2805 ret = free_mr_modify_qp(hr_dev); 2806 if (ret) 2807 goto err_modify_qp; 2808 2809 return 0; 2810 2811 err_modify_qp: 2812 free_mr_exit(hr_dev); 2813 2814 return ret; 2815 } 2816 2817 static int get_hem_table(struct hns_roce_dev *hr_dev) 2818 { 2819 unsigned int qpc_count; 2820 unsigned int cqc_count; 2821 unsigned int gmv_count; 2822 int ret; 2823 int i; 2824 2825 /* Alloc memory for source address table buffer space chunk */ 2826 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2827 gmv_count++) { 2828 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2829 if (ret) 2830 goto err_gmv_failed; 2831 } 2832 2833 if (hr_dev->is_vf) 2834 return 0; 2835 2836 /* Alloc memory for QPC Timer buffer space chunk */ 2837 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2838 qpc_count++) { 2839 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2840 qpc_count); 2841 if (ret) { 2842 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2843 goto err_qpc_timer_failed; 2844 } 2845 } 2846 2847 /* Alloc memory for CQC Timer buffer space chunk */ 2848 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2849 cqc_count++) { 2850 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2851 cqc_count); 2852 if (ret) { 2853 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2854 goto err_cqc_timer_failed; 2855 } 2856 } 2857 2858 return 0; 2859 2860 err_cqc_timer_failed: 2861 for (i = 0; i < cqc_count; i++) 2862 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2863 2864 err_qpc_timer_failed: 2865 for (i = 0; i < qpc_count; i++) 2866 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2867 2868 err_gmv_failed: 2869 for (i = 0; i < gmv_count; i++) 2870 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2871 2872 return ret; 2873 } 2874 2875 static void put_hem_table(struct hns_roce_dev *hr_dev) 2876 { 2877 int i; 2878 2879 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2880 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2881 2882 if (hr_dev->is_vf) 2883 return; 2884 2885 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2886 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2887 2888 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2889 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2890 } 2891 2892 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2893 { 2894 int ret; 2895 2896 /* The hns ROCEE requires the extdb info to be cleared before using */ 2897 ret = hns_roce_clear_extdb_list_info(hr_dev); 2898 if (ret) 2899 return ret; 2900 2901 ret = get_hem_table(hr_dev); 2902 if (ret) 2903 return ret; 2904 2905 if (hr_dev->is_vf) 2906 return 0; 2907 2908 ret = hns_roce_init_link_table(hr_dev); 2909 if (ret) { 2910 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2911 goto err_llm_init_failed; 2912 } 2913 2914 return 0; 2915 2916 err_llm_init_failed: 2917 put_hem_table(hr_dev); 2918 2919 return ret; 2920 } 2921 2922 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2923 { 2924 hns_roce_function_clear(hr_dev); 2925 2926 if (!hr_dev->is_vf) 2927 hns_roce_free_link_table(hr_dev); 2928 2929 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2930 free_dip_list(hr_dev); 2931 } 2932 2933 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2934 struct hns_roce_mbox_msg *mbox_msg) 2935 { 2936 struct hns_roce_cmq_desc desc; 2937 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2938 2939 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2940 2941 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2942 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2943 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2944 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2945 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2946 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2947 mbox_msg->token); 2948 2949 return hns_roce_cmq_send(hr_dev, &desc, 1); 2950 } 2951 2952 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2953 u8 *complete_status) 2954 { 2955 struct hns_roce_mbox_status *mb_st; 2956 struct hns_roce_cmq_desc desc; 2957 unsigned long end; 2958 int ret = -EBUSY; 2959 u32 status; 2960 bool busy; 2961 2962 mb_st = (struct hns_roce_mbox_status *)desc.data; 2963 end = msecs_to_jiffies(timeout) + jiffies; 2964 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2965 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2966 return -EIO; 2967 2968 status = 0; 2969 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2970 true); 2971 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2972 if (!ret) { 2973 status = le32_to_cpu(mb_st->mb_status_hw_run); 2974 /* No pending message exists in ROCEE mbox. */ 2975 if (!(status & MB_ST_HW_RUN_M)) 2976 break; 2977 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2978 break; 2979 } 2980 2981 if (time_after(jiffies, end)) { 2982 dev_err_ratelimited(hr_dev->dev, 2983 "failed to wait mbox status 0x%x\n", 2984 status); 2985 return -ETIMEDOUT; 2986 } 2987 2988 cond_resched(); 2989 ret = -EBUSY; 2990 } 2991 2992 if (!ret) { 2993 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2994 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2995 /* Ignore all errors if the mbox is unavailable. */ 2996 ret = 0; 2997 *complete_status = MB_ST_COMPLETE_M; 2998 } 2999 3000 return ret; 3001 } 3002 3003 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3004 struct hns_roce_mbox_msg *mbox_msg) 3005 { 3006 u8 status = 0; 3007 int ret; 3008 3009 /* Waiting for the mbox to be idle */ 3010 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3011 &status); 3012 if (unlikely(ret)) { 3013 dev_err_ratelimited(hr_dev->dev, 3014 "failed to check post mbox status = 0x%x, ret = %d.\n", 3015 status, ret); 3016 return ret; 3017 } 3018 3019 /* Post new message to mbox */ 3020 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3021 if (ret) 3022 dev_err_ratelimited(hr_dev->dev, 3023 "failed to post mailbox, ret = %d.\n", ret); 3024 3025 return ret; 3026 } 3027 3028 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3029 { 3030 u8 status = 0; 3031 int ret; 3032 3033 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3034 &status); 3035 if (!ret) { 3036 if (status != MB_ST_COMPLETE_SUCC) 3037 return -EBUSY; 3038 } else { 3039 dev_err_ratelimited(hr_dev->dev, 3040 "failed to check mbox status = 0x%x, ret = %d.\n", 3041 status, ret); 3042 } 3043 3044 return ret; 3045 } 3046 3047 static void copy_gid(void *dest, const union ib_gid *gid) 3048 { 3049 #define GID_SIZE 4 3050 const union ib_gid *src = gid; 3051 __le32 (*p)[GID_SIZE] = dest; 3052 int i; 3053 3054 if (!gid) 3055 src = &zgid; 3056 3057 for (i = 0; i < GID_SIZE; i++) 3058 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3059 } 3060 3061 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3062 int gid_index, const union ib_gid *gid, 3063 enum hns_roce_sgid_type sgid_type) 3064 { 3065 struct hns_roce_cmq_desc desc; 3066 struct hns_roce_cfg_sgid_tb *sgid_tb = 3067 (struct hns_roce_cfg_sgid_tb *)desc.data; 3068 3069 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3070 3071 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3072 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3073 3074 copy_gid(&sgid_tb->vf_sgid_l, gid); 3075 3076 return hns_roce_cmq_send(hr_dev, &desc, 1); 3077 } 3078 3079 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3080 int gid_index, const union ib_gid *gid, 3081 enum hns_roce_sgid_type sgid_type, 3082 const struct ib_gid_attr *attr) 3083 { 3084 struct hns_roce_cmq_desc desc[2]; 3085 struct hns_roce_cfg_gmv_tb_a *tb_a = 3086 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3087 struct hns_roce_cfg_gmv_tb_b *tb_b = 3088 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3089 3090 u16 vlan_id = VLAN_CFI_MASK; 3091 u8 mac[ETH_ALEN] = {}; 3092 int ret; 3093 3094 if (gid) { 3095 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3096 if (ret) 3097 return ret; 3098 } 3099 3100 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3101 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3102 3103 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3104 3105 copy_gid(&tb_a->vf_sgid_l, gid); 3106 3107 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3108 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3109 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3110 3111 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3112 3113 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3114 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3115 3116 return hns_roce_cmq_send(hr_dev, desc, 2); 3117 } 3118 3119 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3120 const union ib_gid *gid, 3121 const struct ib_gid_attr *attr) 3122 { 3123 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3124 int ret; 3125 3126 if (gid) { 3127 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3128 if (ipv6_addr_v4mapped((void *)gid)) 3129 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3130 else 3131 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3132 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3133 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3134 } 3135 } 3136 3137 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3138 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3139 else 3140 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3141 3142 if (ret) 3143 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3144 ret); 3145 3146 return ret; 3147 } 3148 3149 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3150 const u8 *addr) 3151 { 3152 struct hns_roce_cmq_desc desc; 3153 struct hns_roce_cfg_smac_tb *smac_tb = 3154 (struct hns_roce_cfg_smac_tb *)desc.data; 3155 u16 reg_smac_h; 3156 u32 reg_smac_l; 3157 3158 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3159 3160 reg_smac_l = *(u32 *)(&addr[0]); 3161 reg_smac_h = *(u16 *)(&addr[4]); 3162 3163 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3164 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3165 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3166 3167 return hns_roce_cmq_send(hr_dev, &desc, 1); 3168 } 3169 3170 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3171 struct hns_roce_v2_mpt_entry *mpt_entry, 3172 struct hns_roce_mr *mr) 3173 { 3174 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3175 struct ib_device *ibdev = &hr_dev->ib_dev; 3176 dma_addr_t pbl_ba; 3177 int i, count; 3178 3179 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3180 min_t(int, ARRAY_SIZE(pages), mr->npages), 3181 &pbl_ba); 3182 if (count < 1) { 3183 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3184 count); 3185 return -ENOBUFS; 3186 } 3187 3188 /* Aligned to the hardware address access unit */ 3189 for (i = 0; i < count; i++) 3190 pages[i] >>= 6; 3191 3192 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3193 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3194 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3195 3196 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3197 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3198 3199 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3200 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3201 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3202 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3203 3204 return 0; 3205 } 3206 3207 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3208 void *mb_buf, struct hns_roce_mr *mr) 3209 { 3210 struct hns_roce_v2_mpt_entry *mpt_entry; 3211 3212 mpt_entry = mb_buf; 3213 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3214 3215 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3216 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3217 3218 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3219 mr->access & IB_ACCESS_MW_BIND); 3220 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3221 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3222 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3223 mr->access & IB_ACCESS_REMOTE_READ); 3224 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3225 mr->access & IB_ACCESS_REMOTE_WRITE); 3226 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3227 mr->access & IB_ACCESS_LOCAL_WRITE); 3228 3229 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3230 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3231 mpt_entry->lkey = cpu_to_le32(mr->key); 3232 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3233 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3234 3235 if (mr->type != MR_TYPE_MR) 3236 hr_reg_enable(mpt_entry, MPT_PA); 3237 3238 if (mr->type == MR_TYPE_DMA) 3239 return 0; 3240 3241 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3242 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3243 3244 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3245 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3246 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3247 3248 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3249 } 3250 3251 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3252 struct hns_roce_mr *mr, int flags, 3253 void *mb_buf) 3254 { 3255 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3256 u32 mr_access_flags = mr->access; 3257 int ret = 0; 3258 3259 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3260 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3261 3262 if (flags & IB_MR_REREG_ACCESS) { 3263 hr_reg_write(mpt_entry, MPT_BIND_EN, 3264 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3265 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3266 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3267 hr_reg_write(mpt_entry, MPT_RR_EN, 3268 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3269 hr_reg_write(mpt_entry, MPT_RW_EN, 3270 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3271 hr_reg_write(mpt_entry, MPT_LW_EN, 3272 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3273 } 3274 3275 if (flags & IB_MR_REREG_TRANS) { 3276 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3277 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3278 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3279 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3280 3281 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3282 } 3283 3284 return ret; 3285 } 3286 3287 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3288 void *mb_buf, struct hns_roce_mr *mr) 3289 { 3290 struct ib_device *ibdev = &hr_dev->ib_dev; 3291 struct hns_roce_v2_mpt_entry *mpt_entry; 3292 dma_addr_t pbl_ba = 0; 3293 3294 mpt_entry = mb_buf; 3295 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3296 3297 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3298 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3299 return -ENOBUFS; 3300 } 3301 3302 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3303 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3304 3305 hr_reg_enable(mpt_entry, MPT_RA_EN); 3306 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3307 3308 hr_reg_enable(mpt_entry, MPT_FRE); 3309 hr_reg_clear(mpt_entry, MPT_MR_MW); 3310 hr_reg_enable(mpt_entry, MPT_BPD); 3311 hr_reg_clear(mpt_entry, MPT_PA); 3312 3313 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3314 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3315 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3316 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3317 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3318 3319 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3320 3321 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3322 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3323 3324 return 0; 3325 } 3326 3327 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3328 { 3329 struct hns_roce_v2_mpt_entry *mpt_entry; 3330 3331 mpt_entry = mb_buf; 3332 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3333 3334 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3335 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3336 3337 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3338 hr_reg_enable(mpt_entry, MPT_LW_EN); 3339 3340 hr_reg_enable(mpt_entry, MPT_MR_MW); 3341 hr_reg_enable(mpt_entry, MPT_BPD); 3342 hr_reg_clear(mpt_entry, MPT_PA); 3343 hr_reg_write(mpt_entry, MPT_BQP, 3344 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3345 3346 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3347 3348 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3349 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3350 mw->pbl_hop_num); 3351 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3352 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3353 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3354 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3355 3356 return 0; 3357 } 3358 3359 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3360 { 3361 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3362 struct ib_device *ibdev = &hr_dev->ib_dev; 3363 const struct ib_send_wr *bad_wr; 3364 struct ib_rdma_wr rdma_wr = {}; 3365 struct ib_send_wr *send_wr; 3366 int ret; 3367 3368 send_wr = &rdma_wr.wr; 3369 send_wr->opcode = IB_WR_RDMA_WRITE; 3370 3371 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3372 if (ret) { 3373 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3374 ret); 3375 return ret; 3376 } 3377 3378 return 0; 3379 } 3380 3381 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3382 struct ib_wc *wc); 3383 3384 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3385 { 3386 struct hns_roce_v2_priv *priv = hr_dev->priv; 3387 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3388 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3389 struct ib_device *ibdev = &hr_dev->ib_dev; 3390 struct hns_roce_qp *hr_qp; 3391 unsigned long end; 3392 int cqe_cnt = 0; 3393 int npolled; 3394 int ret; 3395 int i; 3396 3397 /* 3398 * If the device initialization is not complete or in the uninstall 3399 * process, then there is no need to execute free mr. 3400 */ 3401 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3402 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3403 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3404 return; 3405 3406 mutex_lock(&free_mr->mutex); 3407 3408 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3409 hr_qp = free_mr->rsv_qp[i]; 3410 3411 ret = free_mr_post_send_lp_wqe(hr_qp); 3412 if (ret) { 3413 ibdev_err(ibdev, 3414 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3415 hr_qp->qpn, ret); 3416 break; 3417 } 3418 3419 cqe_cnt++; 3420 } 3421 3422 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3423 while (cqe_cnt) { 3424 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3425 if (npolled < 0) { 3426 ibdev_err(ibdev, 3427 "failed to poll cqe for free mr, remain %d cqe.\n", 3428 cqe_cnt); 3429 goto out; 3430 } 3431 3432 if (time_after(jiffies, end)) { 3433 ibdev_err(ibdev, 3434 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3435 cqe_cnt); 3436 goto out; 3437 } 3438 cqe_cnt -= npolled; 3439 } 3440 3441 out: 3442 mutex_unlock(&free_mr->mutex); 3443 } 3444 3445 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3446 { 3447 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3448 free_mr_send_cmd_to_hw(hr_dev); 3449 } 3450 3451 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3452 { 3453 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3454 } 3455 3456 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3457 { 3458 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3459 3460 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3461 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3462 NULL; 3463 } 3464 3465 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3466 struct hns_roce_cq *hr_cq) 3467 { 3468 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3469 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3470 } else { 3471 struct hns_roce_v2_db cq_db = {}; 3472 3473 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3474 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3475 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3476 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3477 3478 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3479 } 3480 } 3481 3482 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3483 struct hns_roce_srq *srq) 3484 { 3485 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3486 struct hns_roce_v2_cqe *cqe, *dest; 3487 u32 prod_index; 3488 int nfreed = 0; 3489 int wqe_index; 3490 u8 owner_bit; 3491 3492 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3493 ++prod_index) { 3494 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3495 break; 3496 } 3497 3498 /* 3499 * Now backwards through the CQ, removing CQ entries 3500 * that match our QP by overwriting them with next entries. 3501 */ 3502 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3503 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3504 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3505 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3506 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3507 hns_roce_free_srq_wqe(srq, wqe_index); 3508 } 3509 ++nfreed; 3510 } else if (nfreed) { 3511 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3512 hr_cq->ib_cq.cqe); 3513 owner_bit = hr_reg_read(dest, CQE_OWNER); 3514 memcpy(dest, cqe, hr_cq->cqe_size); 3515 hr_reg_write(dest, CQE_OWNER, owner_bit); 3516 } 3517 } 3518 3519 if (nfreed) { 3520 hr_cq->cons_index += nfreed; 3521 update_cq_db(hr_dev, hr_cq); 3522 } 3523 } 3524 3525 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3526 struct hns_roce_srq *srq) 3527 { 3528 spin_lock_irq(&hr_cq->lock); 3529 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3530 spin_unlock_irq(&hr_cq->lock); 3531 } 3532 3533 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3534 struct hns_roce_cq *hr_cq, void *mb_buf, 3535 u64 *mtts, dma_addr_t dma_handle) 3536 { 3537 struct hns_roce_v2_cq_context *cq_context; 3538 3539 cq_context = mb_buf; 3540 memset(cq_context, 0, sizeof(*cq_context)); 3541 3542 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3543 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3544 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3545 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3546 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3547 3548 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3549 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3550 3551 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3552 hr_reg_enable(cq_context, CQC_STASH); 3553 3554 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3555 to_hr_hw_page_addr(mtts[0])); 3556 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3557 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3558 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3559 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3560 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3561 to_hr_hw_page_addr(mtts[1])); 3562 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3563 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3564 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3565 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3566 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3567 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3568 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3569 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3570 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3571 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3572 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3573 ((u32)hr_cq->db.dma) >> 1); 3574 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3575 hr_cq->db.dma >> 32); 3576 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3577 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3578 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3579 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3580 } 3581 3582 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3583 enum ib_cq_notify_flags flags) 3584 { 3585 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3586 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3587 struct hns_roce_v2_db cq_db = {}; 3588 u32 notify_flag; 3589 3590 /* 3591 * flags = 0, then notify_flag : next 3592 * flags = 1, then notify flag : solocited 3593 */ 3594 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3595 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3596 3597 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3598 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3599 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3600 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3601 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3602 3603 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3604 3605 return 0; 3606 } 3607 3608 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3609 int num_entries, struct ib_wc *wc) 3610 { 3611 unsigned int left; 3612 int npolled = 0; 3613 3614 left = wq->head - wq->tail; 3615 if (left == 0) 3616 return 0; 3617 3618 left = min_t(unsigned int, (unsigned int)num_entries, left); 3619 while (npolled < left) { 3620 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3621 wc->status = IB_WC_WR_FLUSH_ERR; 3622 wc->vendor_err = 0; 3623 wc->qp = &hr_qp->ibqp; 3624 3625 wq->tail++; 3626 wc++; 3627 npolled++; 3628 } 3629 3630 return npolled; 3631 } 3632 3633 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3634 struct ib_wc *wc) 3635 { 3636 struct hns_roce_qp *hr_qp; 3637 int npolled = 0; 3638 3639 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3640 npolled += sw_comp(hr_qp, &hr_qp->sq, 3641 num_entries - npolled, wc + npolled); 3642 if (npolled >= num_entries) 3643 goto out; 3644 } 3645 3646 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3647 npolled += sw_comp(hr_qp, &hr_qp->rq, 3648 num_entries - npolled, wc + npolled); 3649 if (npolled >= num_entries) 3650 goto out; 3651 } 3652 3653 out: 3654 return npolled; 3655 } 3656 3657 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3658 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3659 struct ib_wc *wc) 3660 { 3661 static const struct { 3662 u32 cqe_status; 3663 enum ib_wc_status wc_status; 3664 } map[] = { 3665 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3666 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3667 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3668 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3669 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3670 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3671 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3672 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3673 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3674 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3675 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3676 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3677 IB_WC_RETRY_EXC_ERR }, 3678 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3679 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3680 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3681 }; 3682 3683 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3684 int i; 3685 3686 wc->status = IB_WC_GENERAL_ERR; 3687 for (i = 0; i < ARRAY_SIZE(map); i++) 3688 if (cqe_status == map[i].cqe_status) { 3689 wc->status = map[i].wc_status; 3690 break; 3691 } 3692 3693 if (likely(wc->status == IB_WC_SUCCESS || 3694 wc->status == IB_WC_WR_FLUSH_ERR)) 3695 return; 3696 3697 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3698 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3699 cq->cqe_size, false); 3700 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3701 3702 /* 3703 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3704 * the standard protocol, the driver must ignore it and needn't to set 3705 * the QP to an error state. 3706 */ 3707 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3708 return; 3709 3710 flush_cqe(hr_dev, qp); 3711 } 3712 3713 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3714 struct hns_roce_qp **cur_qp) 3715 { 3716 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3717 struct hns_roce_qp *hr_qp = *cur_qp; 3718 u32 qpn; 3719 3720 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3721 3722 if (!hr_qp || qpn != hr_qp->qpn) { 3723 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3724 if (unlikely(!hr_qp)) { 3725 ibdev_err(&hr_dev->ib_dev, 3726 "CQ %06lx with entry for unknown QPN %06x\n", 3727 hr_cq->cqn, qpn); 3728 return -EINVAL; 3729 } 3730 *cur_qp = hr_qp; 3731 } 3732 3733 return 0; 3734 } 3735 3736 /* 3737 * mapped-value = 1 + real-value 3738 * The ib wc opcode's real value is start from 0, In order to distinguish 3739 * between initialized and uninitialized map values, we plus 1 to the actual 3740 * value when defining the mapping, so that the validity can be identified by 3741 * checking whether the mapped value is greater than 0. 3742 */ 3743 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3744 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3745 3746 static const u32 wc_send_op_map[] = { 3747 HR_WC_OP_MAP(SEND, SEND), 3748 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3749 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3750 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3751 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3752 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3753 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3754 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3755 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3756 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3757 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3758 HR_WC_OP_MAP(BIND_MW, REG_MR), 3759 }; 3760 3761 static int to_ib_wc_send_op(u32 hr_opcode) 3762 { 3763 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3764 return -EINVAL; 3765 3766 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3767 -EINVAL; 3768 } 3769 3770 static const u32 wc_recv_op_map[] = { 3771 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3772 HR_WC_OP_MAP(SEND, RECV), 3773 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3774 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3775 }; 3776 3777 static int to_ib_wc_recv_op(u32 hr_opcode) 3778 { 3779 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3780 return -EINVAL; 3781 3782 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3783 -EINVAL; 3784 } 3785 3786 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3787 { 3788 u32 hr_opcode; 3789 int ib_opcode; 3790 3791 wc->wc_flags = 0; 3792 3793 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3794 switch (hr_opcode) { 3795 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3796 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3797 break; 3798 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3799 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3800 wc->wc_flags |= IB_WC_WITH_IMM; 3801 break; 3802 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3803 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3804 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3805 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3806 wc->byte_len = 8; 3807 break; 3808 default: 3809 break; 3810 } 3811 3812 ib_opcode = to_ib_wc_send_op(hr_opcode); 3813 if (ib_opcode < 0) 3814 wc->status = IB_WC_GENERAL_ERR; 3815 else 3816 wc->opcode = ib_opcode; 3817 } 3818 3819 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3820 { 3821 u32 hr_opcode; 3822 int ib_opcode; 3823 3824 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3825 3826 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3827 switch (hr_opcode) { 3828 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3829 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3830 wc->wc_flags = IB_WC_WITH_IMM; 3831 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3832 break; 3833 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3834 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3835 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3836 break; 3837 default: 3838 wc->wc_flags = 0; 3839 } 3840 3841 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3842 if (ib_opcode < 0) 3843 wc->status = IB_WC_GENERAL_ERR; 3844 else 3845 wc->opcode = ib_opcode; 3846 3847 wc->sl = hr_reg_read(cqe, CQE_SL); 3848 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3849 wc->slid = 0; 3850 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3851 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3852 wc->pkey_index = 0; 3853 3854 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3855 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3856 wc->wc_flags |= IB_WC_WITH_VLAN; 3857 } else { 3858 wc->vlan_id = 0xffff; 3859 } 3860 3861 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3862 3863 return 0; 3864 } 3865 3866 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3867 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3868 { 3869 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3870 struct hns_roce_qp *qp = *cur_qp; 3871 struct hns_roce_srq *srq = NULL; 3872 struct hns_roce_v2_cqe *cqe; 3873 struct hns_roce_wq *wq; 3874 int is_send; 3875 u16 wqe_idx; 3876 int ret; 3877 3878 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3879 if (!cqe) 3880 return -EAGAIN; 3881 3882 ++hr_cq->cons_index; 3883 /* Memory barrier */ 3884 rmb(); 3885 3886 ret = get_cur_qp(hr_cq, cqe, &qp); 3887 if (ret) 3888 return ret; 3889 3890 wc->qp = &qp->ibqp; 3891 wc->vendor_err = 0; 3892 3893 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3894 3895 is_send = !hr_reg_read(cqe, CQE_S_R); 3896 if (is_send) { 3897 wq = &qp->sq; 3898 3899 /* If sg_signal_bit is set, tail pointer will be updated to 3900 * the WQE corresponding to the current CQE. 3901 */ 3902 if (qp->sq_signal_bits) 3903 wq->tail += (wqe_idx - (u16)wq->tail) & 3904 (wq->wqe_cnt - 1); 3905 3906 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3907 ++wq->tail; 3908 3909 fill_send_wc(wc, cqe); 3910 } else { 3911 if (qp->ibqp.srq) { 3912 srq = to_hr_srq(qp->ibqp.srq); 3913 wc->wr_id = srq->wrid[wqe_idx]; 3914 hns_roce_free_srq_wqe(srq, wqe_idx); 3915 } else { 3916 wq = &qp->rq; 3917 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3918 ++wq->tail; 3919 } 3920 3921 ret = fill_recv_wc(wc, cqe); 3922 } 3923 3924 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3925 if (unlikely(wc->status != IB_WC_SUCCESS)) 3926 return 0; 3927 3928 return ret; 3929 } 3930 3931 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3932 struct ib_wc *wc) 3933 { 3934 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3935 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3936 struct hns_roce_qp *cur_qp = NULL; 3937 unsigned long flags; 3938 int npolled; 3939 3940 spin_lock_irqsave(&hr_cq->lock, flags); 3941 3942 /* 3943 * When the device starts to reset, the state is RST_DOWN. At this time, 3944 * there may still be some valid CQEs in the hardware that are not 3945 * polled. Therefore, it is not allowed to switch to the software mode 3946 * immediately. When the state changes to UNINIT, CQE no longer exists 3947 * in the hardware, and then switch to software mode. 3948 */ 3949 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3950 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3951 goto out; 3952 } 3953 3954 for (npolled = 0; npolled < num_entries; ++npolled) { 3955 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3956 break; 3957 } 3958 3959 if (npolled) 3960 update_cq_db(hr_dev, hr_cq); 3961 3962 out: 3963 spin_unlock_irqrestore(&hr_cq->lock, flags); 3964 3965 return npolled; 3966 } 3967 3968 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3969 u32 step_idx, u8 *mbox_cmd) 3970 { 3971 u8 cmd; 3972 3973 switch (type) { 3974 case HEM_TYPE_QPC: 3975 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 3976 break; 3977 case HEM_TYPE_MTPT: 3978 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 3979 break; 3980 case HEM_TYPE_CQC: 3981 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 3982 break; 3983 case HEM_TYPE_SRQC: 3984 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3985 break; 3986 case HEM_TYPE_SCCC: 3987 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3988 break; 3989 case HEM_TYPE_QPC_TIMER: 3990 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3991 break; 3992 case HEM_TYPE_CQC_TIMER: 3993 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3994 break; 3995 default: 3996 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 3997 return -EINVAL; 3998 } 3999 4000 *mbox_cmd = cmd + step_idx; 4001 4002 return 0; 4003 } 4004 4005 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4006 dma_addr_t base_addr) 4007 { 4008 struct hns_roce_cmq_desc desc; 4009 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4010 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4011 u64 addr = to_hr_hw_page_addr(base_addr); 4012 4013 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4014 4015 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4016 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4017 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4018 4019 return hns_roce_cmq_send(hr_dev, &desc, 1); 4020 } 4021 4022 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4023 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4024 { 4025 int ret; 4026 u8 cmd; 4027 4028 if (unlikely(hem_type == HEM_TYPE_GMV)) 4029 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4030 4031 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4032 return 0; 4033 4034 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4035 if (ret < 0) 4036 return ret; 4037 4038 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4039 } 4040 4041 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4042 struct hns_roce_hem_table *table, int obj, 4043 u32 step_idx) 4044 { 4045 struct hns_roce_hem_iter iter; 4046 struct hns_roce_hem_mhop mhop; 4047 struct hns_roce_hem *hem; 4048 unsigned long mhop_obj = obj; 4049 int i, j, k; 4050 int ret = 0; 4051 u64 hem_idx = 0; 4052 u64 l1_idx = 0; 4053 u64 bt_ba = 0; 4054 u32 chunk_ba_num; 4055 u32 hop_num; 4056 4057 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4058 return 0; 4059 4060 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4061 i = mhop.l0_idx; 4062 j = mhop.l1_idx; 4063 k = mhop.l2_idx; 4064 hop_num = mhop.hop_num; 4065 chunk_ba_num = mhop.bt_chunk_size / 8; 4066 4067 if (hop_num == 2) { 4068 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4069 k; 4070 l1_idx = i * chunk_ba_num + j; 4071 } else if (hop_num == 1) { 4072 hem_idx = i * chunk_ba_num + j; 4073 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4074 hem_idx = i; 4075 } 4076 4077 if (table->type == HEM_TYPE_SCCC) 4078 obj = mhop.l0_idx; 4079 4080 if (check_whether_last_step(hop_num, step_idx)) { 4081 hem = table->hem[hem_idx]; 4082 for (hns_roce_hem_first(hem, &iter); 4083 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4084 bt_ba = hns_roce_hem_addr(&iter); 4085 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4086 step_idx); 4087 } 4088 } else { 4089 if (step_idx == 0) 4090 bt_ba = table->bt_l0_dma_addr[i]; 4091 else if (step_idx == 1 && hop_num == 2) 4092 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4093 4094 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4095 } 4096 4097 return ret; 4098 } 4099 4100 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4101 struct hns_roce_hem_table *table, 4102 int tag, u32 step_idx) 4103 { 4104 struct hns_roce_cmd_mailbox *mailbox; 4105 struct device *dev = hr_dev->dev; 4106 u8 cmd = 0xff; 4107 int ret; 4108 4109 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4110 return 0; 4111 4112 switch (table->type) { 4113 case HEM_TYPE_QPC: 4114 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4115 break; 4116 case HEM_TYPE_MTPT: 4117 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4118 break; 4119 case HEM_TYPE_CQC: 4120 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4121 break; 4122 case HEM_TYPE_SRQC: 4123 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4124 break; 4125 case HEM_TYPE_SCCC: 4126 case HEM_TYPE_QPC_TIMER: 4127 case HEM_TYPE_CQC_TIMER: 4128 case HEM_TYPE_GMV: 4129 return 0; 4130 default: 4131 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4132 table->type); 4133 return 0; 4134 } 4135 4136 cmd += step_idx; 4137 4138 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4139 if (IS_ERR(mailbox)) 4140 return PTR_ERR(mailbox); 4141 4142 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4143 4144 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4145 return ret; 4146 } 4147 4148 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4149 struct hns_roce_v2_qp_context *context, 4150 struct hns_roce_v2_qp_context *qpc_mask, 4151 struct hns_roce_qp *hr_qp) 4152 { 4153 struct hns_roce_cmd_mailbox *mailbox; 4154 int qpc_size; 4155 int ret; 4156 4157 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4158 if (IS_ERR(mailbox)) 4159 return PTR_ERR(mailbox); 4160 4161 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4162 qpc_size = hr_dev->caps.qpc_sz; 4163 memcpy(mailbox->buf, context, qpc_size); 4164 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4165 4166 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4167 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4168 4169 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4170 4171 return ret; 4172 } 4173 4174 static void set_access_flags(struct hns_roce_qp *hr_qp, 4175 struct hns_roce_v2_qp_context *context, 4176 struct hns_roce_v2_qp_context *qpc_mask, 4177 const struct ib_qp_attr *attr, int attr_mask) 4178 { 4179 u8 dest_rd_atomic; 4180 u32 access_flags; 4181 4182 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4183 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4184 4185 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4186 attr->qp_access_flags : hr_qp->atomic_rd_en; 4187 4188 if (!dest_rd_atomic) 4189 access_flags &= IB_ACCESS_REMOTE_WRITE; 4190 4191 hr_reg_write_bool(context, QPC_RRE, 4192 access_flags & IB_ACCESS_REMOTE_READ); 4193 hr_reg_clear(qpc_mask, QPC_RRE); 4194 4195 hr_reg_write_bool(context, QPC_RWE, 4196 access_flags & IB_ACCESS_REMOTE_WRITE); 4197 hr_reg_clear(qpc_mask, QPC_RWE); 4198 4199 hr_reg_write_bool(context, QPC_ATE, 4200 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4201 hr_reg_clear(qpc_mask, QPC_ATE); 4202 hr_reg_write_bool(context, QPC_EXT_ATE, 4203 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4204 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4205 } 4206 4207 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4208 struct hns_roce_v2_qp_context *context, 4209 struct hns_roce_v2_qp_context *qpc_mask) 4210 { 4211 hr_reg_write(context, QPC_SGE_SHIFT, 4212 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4213 hr_qp->sge.sge_shift)); 4214 4215 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4216 4217 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4218 } 4219 4220 static inline int get_cqn(struct ib_cq *ib_cq) 4221 { 4222 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4223 } 4224 4225 static inline int get_pdn(struct ib_pd *ib_pd) 4226 { 4227 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4228 } 4229 4230 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4231 const struct ib_qp_attr *attr, 4232 struct hns_roce_v2_qp_context *context, 4233 struct hns_roce_v2_qp_context *qpc_mask) 4234 { 4235 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4236 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4237 4238 /* 4239 * In v2 engine, software pass context and context mask to hardware 4240 * when modifying qp. If software need modify some fields in context, 4241 * we should set all bits of the relevant fields in context mask to 4242 * 0 at the same time, else set them to 0x1. 4243 */ 4244 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4245 4246 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4247 4248 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4249 4250 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4251 4252 /* No VLAN need to set 0xFFF */ 4253 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4254 4255 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4256 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4257 4258 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4259 } 4260 4261 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4262 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4263 4264 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4265 hr_reg_enable(context, QPC_OWNER_MODE); 4266 4267 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4268 lower_32_bits(hr_qp->rdb.dma) >> 1); 4269 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4270 upper_32_bits(hr_qp->rdb.dma)); 4271 4272 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4273 4274 if (ibqp->srq) { 4275 hr_reg_enable(context, QPC_SRQ_EN); 4276 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4277 } 4278 4279 hr_reg_enable(context, QPC_FRE); 4280 4281 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4282 4283 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4284 return; 4285 4286 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4287 hr_reg_enable(&context->ext, QPCEX_STASH); 4288 } 4289 4290 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4291 const struct ib_qp_attr *attr, 4292 struct hns_roce_v2_qp_context *context, 4293 struct hns_roce_v2_qp_context *qpc_mask) 4294 { 4295 /* 4296 * In v2 engine, software pass context and context mask to hardware 4297 * when modifying qp. If software need modify some fields in context, 4298 * we should set all bits of the relevant fields in context mask to 4299 * 0 at the same time, else set them to 0x1. 4300 */ 4301 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4302 hr_reg_clear(qpc_mask, QPC_TST); 4303 4304 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4305 hr_reg_clear(qpc_mask, QPC_PD); 4306 4307 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4308 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4309 4310 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4311 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4312 4313 if (ibqp->srq) { 4314 hr_reg_enable(context, QPC_SRQ_EN); 4315 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4316 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4317 hr_reg_clear(qpc_mask, QPC_SRQN); 4318 } 4319 } 4320 4321 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4322 struct hns_roce_qp *hr_qp, 4323 struct hns_roce_v2_qp_context *context, 4324 struct hns_roce_v2_qp_context *qpc_mask) 4325 { 4326 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4327 u64 wqe_sge_ba; 4328 int count; 4329 4330 /* Search qp buf's mtts */ 4331 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4332 MTT_MIN_COUNT, &wqe_sge_ba); 4333 if (hr_qp->rq.wqe_cnt && count < 1) { 4334 ibdev_err(&hr_dev->ib_dev, 4335 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4336 return -EINVAL; 4337 } 4338 4339 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4340 qpc_mask->wqe_sge_ba = 0; 4341 4342 /* 4343 * In v2 engine, software pass context and context mask to hardware 4344 * when modifying qp. If software need modify some fields in context, 4345 * we should set all bits of the relevant fields in context mask to 4346 * 0 at the same time, else set them to 0x1. 4347 */ 4348 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4349 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4350 4351 hr_reg_write(context, QPC_SQ_HOP_NUM, 4352 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4353 hr_qp->sq.wqe_cnt)); 4354 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4355 4356 hr_reg_write(context, QPC_SGE_HOP_NUM, 4357 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4358 hr_qp->sge.sge_cnt)); 4359 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4360 4361 hr_reg_write(context, QPC_RQ_HOP_NUM, 4362 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4363 hr_qp->rq.wqe_cnt)); 4364 4365 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4366 4367 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4368 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4369 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4370 4371 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4372 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4373 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4374 4375 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4376 qpc_mask->rq_cur_blk_addr = 0; 4377 4378 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4379 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4380 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4381 4382 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4383 qpc_mask->rq_nxt_blk_addr = 0; 4384 4385 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4386 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4387 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4388 4389 return 0; 4390 } 4391 4392 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4393 struct hns_roce_qp *hr_qp, 4394 struct hns_roce_v2_qp_context *context, 4395 struct hns_roce_v2_qp_context *qpc_mask) 4396 { 4397 struct ib_device *ibdev = &hr_dev->ib_dev; 4398 u64 sge_cur_blk = 0; 4399 u64 sq_cur_blk = 0; 4400 int count; 4401 4402 /* search qp buf's mtts */ 4403 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4404 if (count < 1) { 4405 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4406 hr_qp->qpn); 4407 return -EINVAL; 4408 } 4409 if (hr_qp->sge.sge_cnt > 0) { 4410 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4411 hr_qp->sge.offset, 4412 &sge_cur_blk, 1, NULL); 4413 if (count < 1) { 4414 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4415 hr_qp->qpn); 4416 return -EINVAL; 4417 } 4418 } 4419 4420 /* 4421 * In v2 engine, software pass context and context mask to hardware 4422 * when modifying qp. If software need modify some fields in context, 4423 * we should set all bits of the relevant fields in context mask to 4424 * 0 at the same time, else set them to 0x1. 4425 */ 4426 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4427 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4428 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4429 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4430 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4431 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4432 4433 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4434 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4435 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4436 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4437 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4438 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4439 4440 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4441 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4442 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4443 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4444 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4445 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4446 4447 return 0; 4448 } 4449 4450 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4451 const struct ib_qp_attr *attr) 4452 { 4453 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4454 return IB_MTU_4096; 4455 4456 return attr->path_mtu; 4457 } 4458 4459 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4460 const struct ib_qp_attr *attr, int attr_mask, 4461 struct hns_roce_v2_qp_context *context, 4462 struct hns_roce_v2_qp_context *qpc_mask, 4463 struct ib_udata *udata) 4464 { 4465 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4466 struct hns_roce_ucontext, ibucontext); 4467 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4468 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4469 struct ib_device *ibdev = &hr_dev->ib_dev; 4470 dma_addr_t trrl_ba; 4471 dma_addr_t irrl_ba; 4472 enum ib_mtu ib_mtu; 4473 const u8 *smac; 4474 u8 lp_pktn_ini; 4475 u64 *mtts; 4476 u8 *dmac; 4477 u32 port; 4478 int mtu; 4479 int ret; 4480 4481 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4482 if (ret) { 4483 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4484 return ret; 4485 } 4486 4487 /* Search IRRL's mtts */ 4488 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4489 hr_qp->qpn, &irrl_ba); 4490 if (!mtts) { 4491 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4492 return -EINVAL; 4493 } 4494 4495 /* Search TRRL's mtts */ 4496 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4497 hr_qp->qpn, &trrl_ba); 4498 if (!mtts) { 4499 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4500 return -EINVAL; 4501 } 4502 4503 if (attr_mask & IB_QP_ALT_PATH) { 4504 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4505 attr_mask); 4506 return -EINVAL; 4507 } 4508 4509 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4510 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4511 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4512 qpc_mask->trrl_ba = 0; 4513 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4514 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4515 4516 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4517 qpc_mask->irrl_ba = 0; 4518 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4519 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4520 4521 hr_reg_enable(context, QPC_RMT_E2E); 4522 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4523 4524 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4525 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4526 4527 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4528 4529 smac = (const u8 *)hr_dev->dev_addr[port]; 4530 dmac = (u8 *)attr->ah_attr.roce.dmac; 4531 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4532 if (ether_addr_equal_unaligned(dmac, smac) || 4533 hr_dev->loop_idc == 0x1) { 4534 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4535 hr_reg_clear(qpc_mask, QPC_LBI); 4536 } 4537 4538 if (attr_mask & IB_QP_DEST_QPN) { 4539 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4540 hr_reg_clear(qpc_mask, QPC_DQPN); 4541 } 4542 4543 memcpy(&context->dmac, dmac, sizeof(u32)); 4544 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4545 qpc_mask->dmac = 0; 4546 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4547 4548 ib_mtu = get_mtu(ibqp, attr); 4549 hr_qp->path_mtu = ib_mtu; 4550 4551 mtu = ib_mtu_enum_to_int(ib_mtu); 4552 if (WARN_ON(mtu <= 0)) 4553 return -EINVAL; 4554 #define MIN_LP_MSG_LEN 1024 4555 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4556 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4557 4558 if (attr_mask & IB_QP_PATH_MTU) { 4559 hr_reg_write(context, QPC_MTU, ib_mtu); 4560 hr_reg_clear(qpc_mask, QPC_MTU); 4561 } 4562 4563 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4564 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4565 4566 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4567 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4568 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4569 4570 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4571 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4572 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4573 4574 context->rq_rnr_timer = 0; 4575 qpc_mask->rq_rnr_timer = 0; 4576 4577 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4578 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4579 4580 /* rocee send 2^lp_sgen_ini segs every time */ 4581 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4582 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4583 4584 if (udata && ibqp->qp_type == IB_QPT_RC && 4585 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4586 hr_reg_write_bool(context, QPC_RQIE, 4587 hr_dev->caps.flags & 4588 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4589 hr_reg_clear(qpc_mask, QPC_RQIE); 4590 } 4591 4592 if (udata && 4593 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4594 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4595 hr_reg_write_bool(context, QPC_CQEIE, 4596 hr_dev->caps.flags & 4597 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4598 hr_reg_clear(qpc_mask, QPC_CQEIE); 4599 4600 hr_reg_write(context, QPC_CQEIS, 0); 4601 hr_reg_clear(qpc_mask, QPC_CQEIS); 4602 } 4603 4604 return 0; 4605 } 4606 4607 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4608 const struct ib_qp_attr *attr, int attr_mask, 4609 struct hns_roce_v2_qp_context *context, 4610 struct hns_roce_v2_qp_context *qpc_mask) 4611 { 4612 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4613 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4614 struct ib_device *ibdev = &hr_dev->ib_dev; 4615 int ret; 4616 4617 /* Not support alternate path and path migration */ 4618 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4619 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4620 return -EINVAL; 4621 } 4622 4623 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4624 if (ret) { 4625 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4626 return ret; 4627 } 4628 4629 /* 4630 * Set some fields in context to zero, Because the default values 4631 * of all fields in context are zero, we need not set them to 0 again. 4632 * but we should set the relevant fields of context mask to 0. 4633 */ 4634 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4635 4636 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4637 4638 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4639 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4640 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4641 4642 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4643 4644 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4645 4646 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4647 4648 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4649 4650 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4651 4652 return 0; 4653 } 4654 4655 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4656 u32 *dip_idx) 4657 { 4658 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4659 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4660 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4661 u32 *head = &hr_dev->qp_table.idx_table.head; 4662 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4663 struct hns_roce_dip *hr_dip; 4664 unsigned long flags; 4665 int ret = 0; 4666 4667 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4668 4669 spare_idx[*tail] = ibqp->qp_num; 4670 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4671 4672 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4673 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4674 *dip_idx = hr_dip->dip_idx; 4675 goto out; 4676 } 4677 } 4678 4679 /* If no dgid is found, a new dip and a mapping between dgid and 4680 * dip_idx will be created. 4681 */ 4682 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4683 if (!hr_dip) { 4684 ret = -ENOMEM; 4685 goto out; 4686 } 4687 4688 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4689 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4690 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4691 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4692 4693 out: 4694 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4695 return ret; 4696 } 4697 4698 enum { 4699 CONG_DCQCN, 4700 CONG_WINDOW, 4701 }; 4702 4703 enum { 4704 UNSUPPORT_CONG_LEVEL, 4705 SUPPORT_CONG_LEVEL, 4706 }; 4707 4708 enum { 4709 CONG_LDCP, 4710 CONG_HC3, 4711 }; 4712 4713 enum { 4714 DIP_INVALID, 4715 DIP_VALID, 4716 }; 4717 4718 enum { 4719 WND_LIMIT, 4720 WND_UNLIMIT, 4721 }; 4722 4723 static int check_cong_type(struct ib_qp *ibqp, 4724 struct hns_roce_congestion_algorithm *cong_alg) 4725 { 4726 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4727 4728 if (ibqp->qp_type == IB_QPT_UD) 4729 hr_dev->caps.cong_type = CONG_TYPE_DCQCN; 4730 4731 /* different congestion types match different configurations */ 4732 switch (hr_dev->caps.cong_type) { 4733 case CONG_TYPE_DCQCN: 4734 cong_alg->alg_sel = CONG_DCQCN; 4735 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4736 cong_alg->dip_vld = DIP_INVALID; 4737 cong_alg->wnd_mode_sel = WND_LIMIT; 4738 break; 4739 case CONG_TYPE_LDCP: 4740 cong_alg->alg_sel = CONG_WINDOW; 4741 cong_alg->alg_sub_sel = CONG_LDCP; 4742 cong_alg->dip_vld = DIP_INVALID; 4743 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4744 break; 4745 case CONG_TYPE_HC3: 4746 cong_alg->alg_sel = CONG_WINDOW; 4747 cong_alg->alg_sub_sel = CONG_HC3; 4748 cong_alg->dip_vld = DIP_INVALID; 4749 cong_alg->wnd_mode_sel = WND_LIMIT; 4750 break; 4751 case CONG_TYPE_DIP: 4752 cong_alg->alg_sel = CONG_DCQCN; 4753 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4754 cong_alg->dip_vld = DIP_VALID; 4755 cong_alg->wnd_mode_sel = WND_LIMIT; 4756 break; 4757 default: 4758 ibdev_warn(&hr_dev->ib_dev, 4759 "invalid type(%u) for congestion selection.\n", 4760 hr_dev->caps.cong_type); 4761 hr_dev->caps.cong_type = CONG_TYPE_DCQCN; 4762 cong_alg->alg_sel = CONG_DCQCN; 4763 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4764 cong_alg->dip_vld = DIP_INVALID; 4765 cong_alg->wnd_mode_sel = WND_LIMIT; 4766 break; 4767 } 4768 4769 return 0; 4770 } 4771 4772 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4773 struct hns_roce_v2_qp_context *context, 4774 struct hns_roce_v2_qp_context *qpc_mask) 4775 { 4776 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4777 struct hns_roce_congestion_algorithm cong_field; 4778 struct ib_device *ibdev = ibqp->device; 4779 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4780 u32 dip_idx = 0; 4781 int ret; 4782 4783 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4784 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4785 return 0; 4786 4787 ret = check_cong_type(ibqp, &cong_field); 4788 if (ret) 4789 return ret; 4790 4791 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4792 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4793 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4794 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4795 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4796 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4797 cong_field.alg_sub_sel); 4798 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4799 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4800 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4801 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4802 cong_field.wnd_mode_sel); 4803 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4804 4805 /* if dip is disabled, there is no need to set dip idx */ 4806 if (cong_field.dip_vld == 0) 4807 return 0; 4808 4809 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4810 if (ret) { 4811 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4812 return ret; 4813 } 4814 4815 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4816 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4817 4818 return 0; 4819 } 4820 4821 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4822 const struct ib_qp_attr *attr, 4823 int attr_mask, 4824 struct hns_roce_v2_qp_context *context, 4825 struct hns_roce_v2_qp_context *qpc_mask) 4826 { 4827 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4828 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4829 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4830 struct ib_device *ibdev = &hr_dev->ib_dev; 4831 const struct ib_gid_attr *gid_attr = NULL; 4832 u8 sl = rdma_ah_get_sl(&attr->ah_attr); 4833 int is_roce_protocol; 4834 u16 vlan_id = 0xffff; 4835 bool is_udp = false; 4836 u32 max_sl; 4837 u8 ib_port; 4838 u8 hr_port; 4839 int ret; 4840 4841 max_sl = min_t(u32, MAX_SERVICE_LEVEL, hr_dev->caps.sl_num - 1); 4842 if (unlikely(sl > max_sl)) { 4843 ibdev_err_ratelimited(ibdev, 4844 "failed to fill QPC, sl (%u) shouldn't be larger than %u.\n", 4845 sl, max_sl); 4846 return -EINVAL; 4847 } 4848 4849 /* 4850 * If free_mr_en of qp is set, it means that this qp comes from 4851 * free mr. This qp will perform the loopback operation. 4852 * In the loopback scenario, only sl needs to be set. 4853 */ 4854 if (hr_qp->free_mr_en) { 4855 hr_reg_write(context, QPC_SL, sl); 4856 hr_reg_clear(qpc_mask, QPC_SL); 4857 hr_qp->sl = sl; 4858 return 0; 4859 } 4860 4861 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4862 hr_port = ib_port - 1; 4863 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4864 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4865 4866 if (is_roce_protocol) { 4867 gid_attr = attr->ah_attr.grh.sgid_attr; 4868 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4869 if (ret) 4870 return ret; 4871 4872 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4873 } 4874 4875 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4876 if (vlan_id < VLAN_N_VID && 4877 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4878 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4879 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4880 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4881 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4882 } 4883 4884 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4885 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4886 4887 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4888 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4889 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4890 return -EINVAL; 4891 } 4892 4893 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4894 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4895 return -EINVAL; 4896 } 4897 4898 hr_reg_write(context, QPC_UDPSPN, 4899 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4900 attr->dest_qp_num) : 4901 0); 4902 4903 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4904 4905 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4906 4907 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4908 4909 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4910 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4911 4912 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4913 if (ret) 4914 return ret; 4915 4916 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4917 hr_reg_clear(qpc_mask, QPC_TC); 4918 4919 hr_reg_write(context, QPC_FL, grh->flow_label); 4920 hr_reg_clear(qpc_mask, QPC_FL); 4921 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4922 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4923 4924 hr_qp->sl = sl; 4925 hr_reg_write(context, QPC_SL, hr_qp->sl); 4926 hr_reg_clear(qpc_mask, QPC_SL); 4927 4928 return 0; 4929 } 4930 4931 static bool check_qp_state(enum ib_qp_state cur_state, 4932 enum ib_qp_state new_state) 4933 { 4934 static const bool sm[][IB_QPS_ERR + 1] = { 4935 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4936 [IB_QPS_INIT] = true }, 4937 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4938 [IB_QPS_INIT] = true, 4939 [IB_QPS_RTR] = true, 4940 [IB_QPS_ERR] = true }, 4941 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4942 [IB_QPS_RTS] = true, 4943 [IB_QPS_ERR] = true }, 4944 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4945 [IB_QPS_RTS] = true, 4946 [IB_QPS_ERR] = true }, 4947 [IB_QPS_SQD] = {}, 4948 [IB_QPS_SQE] = {}, 4949 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4950 [IB_QPS_ERR] = true } 4951 }; 4952 4953 return sm[cur_state][new_state]; 4954 } 4955 4956 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4957 const struct ib_qp_attr *attr, 4958 int attr_mask, 4959 enum ib_qp_state cur_state, 4960 enum ib_qp_state new_state, 4961 struct hns_roce_v2_qp_context *context, 4962 struct hns_roce_v2_qp_context *qpc_mask, 4963 struct ib_udata *udata) 4964 { 4965 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4966 int ret = 0; 4967 4968 if (!check_qp_state(cur_state, new_state)) { 4969 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4970 return -EINVAL; 4971 } 4972 4973 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4974 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4975 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4976 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4977 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4978 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4979 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4980 qpc_mask, udata); 4981 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4982 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4983 qpc_mask); 4984 } 4985 4986 return ret; 4987 } 4988 4989 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 4990 { 4991 #define QP_ACK_TIMEOUT_MAX_HIP08 20 4992 #define QP_ACK_TIMEOUT_MAX 31 4993 4994 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4995 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 4996 ibdev_warn(&hr_dev->ib_dev, 4997 "local ACK timeout shall be 0 to 20.\n"); 4998 return false; 4999 } 5000 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5001 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5002 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5003 ibdev_warn(&hr_dev->ib_dev, 5004 "local ACK timeout shall be 0 to 31.\n"); 5005 return false; 5006 } 5007 } 5008 5009 return true; 5010 } 5011 5012 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5013 const struct ib_qp_attr *attr, 5014 int attr_mask, 5015 struct hns_roce_v2_qp_context *context, 5016 struct hns_roce_v2_qp_context *qpc_mask) 5017 { 5018 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5019 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5020 int ret = 0; 5021 u8 timeout; 5022 5023 if (attr_mask & IB_QP_AV) { 5024 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5025 qpc_mask); 5026 if (ret) 5027 return ret; 5028 } 5029 5030 if (attr_mask & IB_QP_TIMEOUT) { 5031 timeout = attr->timeout; 5032 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5033 hr_reg_write(context, QPC_AT, timeout); 5034 hr_reg_clear(qpc_mask, QPC_AT); 5035 } 5036 } 5037 5038 if (attr_mask & IB_QP_RETRY_CNT) { 5039 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5040 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5041 5042 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5043 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5044 } 5045 5046 if (attr_mask & IB_QP_RNR_RETRY) { 5047 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5048 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5049 5050 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5051 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5052 } 5053 5054 if (attr_mask & IB_QP_SQ_PSN) { 5055 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5056 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5057 5058 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5059 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5060 5061 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5062 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5063 5064 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5065 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5066 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5067 5068 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5069 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5070 5071 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5072 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5073 } 5074 5075 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5076 attr->max_dest_rd_atomic) { 5077 hr_reg_write(context, QPC_RR_MAX, 5078 fls(attr->max_dest_rd_atomic - 1)); 5079 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5080 } 5081 5082 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5083 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5084 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5085 } 5086 5087 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5088 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5089 5090 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5091 hr_reg_write(context, QPC_MIN_RNR_TIME, 5092 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5093 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5094 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5095 } 5096 5097 if (attr_mask & IB_QP_RQ_PSN) { 5098 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5099 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5100 5101 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5102 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5103 } 5104 5105 if (attr_mask & IB_QP_QKEY) { 5106 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5107 qpc_mask->qkey_xrcd = 0; 5108 hr_qp->qkey = attr->qkey; 5109 } 5110 5111 return ret; 5112 } 5113 5114 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5115 const struct ib_qp_attr *attr, 5116 int attr_mask) 5117 { 5118 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5119 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5120 5121 if (attr_mask & IB_QP_ACCESS_FLAGS) 5122 hr_qp->atomic_rd_en = attr->qp_access_flags; 5123 5124 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5125 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5126 if (attr_mask & IB_QP_PORT) { 5127 hr_qp->port = attr->port_num - 1; 5128 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5129 } 5130 } 5131 5132 static void clear_qp(struct hns_roce_qp *hr_qp) 5133 { 5134 struct ib_qp *ibqp = &hr_qp->ibqp; 5135 5136 if (ibqp->send_cq) 5137 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5138 hr_qp->qpn, NULL); 5139 5140 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5141 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5142 hr_qp->qpn, ibqp->srq ? 5143 to_hr_srq(ibqp->srq) : NULL); 5144 5145 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5146 *hr_qp->rdb.db_record = 0; 5147 5148 hr_qp->rq.head = 0; 5149 hr_qp->rq.tail = 0; 5150 hr_qp->sq.head = 0; 5151 hr_qp->sq.tail = 0; 5152 hr_qp->next_sge = 0; 5153 } 5154 5155 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5156 struct hns_roce_v2_qp_context *context, 5157 struct hns_roce_v2_qp_context *qpc_mask) 5158 { 5159 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5160 unsigned long sq_flag = 0; 5161 unsigned long rq_flag = 0; 5162 5163 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5164 return; 5165 5166 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5167 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5168 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5169 hr_qp->state = IB_QPS_ERR; 5170 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5171 5172 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5173 return; 5174 5175 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5176 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5177 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5178 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5179 } 5180 5181 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5182 const struct ib_qp_attr *attr, 5183 int attr_mask, enum ib_qp_state cur_state, 5184 enum ib_qp_state new_state, struct ib_udata *udata) 5185 { 5186 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5187 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5188 struct hns_roce_v2_qp_context ctx[2]; 5189 struct hns_roce_v2_qp_context *context = ctx; 5190 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5191 struct ib_device *ibdev = &hr_dev->ib_dev; 5192 int ret; 5193 5194 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5195 return -EOPNOTSUPP; 5196 5197 /* 5198 * In v2 engine, software pass context and context mask to hardware 5199 * when modifying qp. If software need modify some fields in context, 5200 * we should set all bits of the relevant fields in context mask to 5201 * 0 at the same time, else set them to 0x1. 5202 */ 5203 memset(context, 0, hr_dev->caps.qpc_sz); 5204 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5205 5206 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5207 new_state, context, qpc_mask, udata); 5208 if (ret) 5209 goto out; 5210 5211 /* When QP state is err, SQ and RQ WQE should be flushed */ 5212 if (new_state == IB_QPS_ERR) 5213 v2_set_flushed_fields(ibqp, context, qpc_mask); 5214 5215 /* Configure the optional fields */ 5216 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5217 qpc_mask); 5218 if (ret) 5219 goto out; 5220 5221 hr_reg_write_bool(context, QPC_INV_CREDIT, 5222 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5223 ibqp->srq); 5224 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5225 5226 /* Every status migrate must change state */ 5227 hr_reg_write(context, QPC_QP_ST, new_state); 5228 hr_reg_clear(qpc_mask, QPC_QP_ST); 5229 5230 /* SW pass context to HW */ 5231 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5232 if (ret) { 5233 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5234 goto out; 5235 } 5236 5237 hr_qp->state = new_state; 5238 5239 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5240 5241 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5242 clear_qp(hr_qp); 5243 5244 out: 5245 return ret; 5246 } 5247 5248 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5249 { 5250 static const enum ib_qp_state map[] = { 5251 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5252 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5253 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5254 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5255 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5256 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5257 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5258 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5259 }; 5260 5261 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5262 } 5263 5264 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5265 void *buffer) 5266 { 5267 struct hns_roce_cmd_mailbox *mailbox; 5268 int ret; 5269 5270 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5271 if (IS_ERR(mailbox)) 5272 return PTR_ERR(mailbox); 5273 5274 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5275 qpn); 5276 if (ret) 5277 goto out; 5278 5279 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5280 5281 out: 5282 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5283 return ret; 5284 } 5285 5286 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5287 struct hns_roce_v2_qp_context *context) 5288 { 5289 u8 timeout; 5290 5291 timeout = (u8)hr_reg_read(context, QPC_AT); 5292 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5293 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5294 5295 return timeout; 5296 } 5297 5298 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5299 int qp_attr_mask, 5300 struct ib_qp_init_attr *qp_init_attr) 5301 { 5302 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5303 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5304 struct hns_roce_v2_qp_context context = {}; 5305 struct ib_device *ibdev = &hr_dev->ib_dev; 5306 int tmp_qp_state; 5307 int state; 5308 int ret; 5309 5310 memset(qp_attr, 0, sizeof(*qp_attr)); 5311 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5312 5313 mutex_lock(&hr_qp->mutex); 5314 5315 if (hr_qp->state == IB_QPS_RESET) { 5316 qp_attr->qp_state = IB_QPS_RESET; 5317 ret = 0; 5318 goto done; 5319 } 5320 5321 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5322 if (ret) { 5323 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5324 ret = -EINVAL; 5325 goto out; 5326 } 5327 5328 state = hr_reg_read(&context, QPC_QP_ST); 5329 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5330 if (tmp_qp_state == -1) { 5331 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5332 ret = -EINVAL; 5333 goto out; 5334 } 5335 hr_qp->state = (u8)tmp_qp_state; 5336 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5337 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5338 qp_attr->path_mig_state = IB_MIG_ARMED; 5339 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5340 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5341 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5342 5343 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5344 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5345 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5346 qp_attr->qp_access_flags = 5347 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5348 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5349 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5350 5351 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5352 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5353 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5354 struct ib_global_route *grh = 5355 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5356 5357 rdma_ah_set_sl(&qp_attr->ah_attr, 5358 hr_reg_read(&context, QPC_SL)); 5359 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5360 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5361 grh->flow_label = hr_reg_read(&context, QPC_FL); 5362 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5363 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5364 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5365 5366 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5367 } 5368 5369 qp_attr->port_num = hr_qp->port + 1; 5370 qp_attr->sq_draining = 0; 5371 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5372 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5373 5374 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5375 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5376 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5377 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5378 5379 done: 5380 qp_attr->cur_qp_state = qp_attr->qp_state; 5381 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5382 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5383 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5384 5385 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5386 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5387 5388 qp_init_attr->qp_context = ibqp->qp_context; 5389 qp_init_attr->qp_type = ibqp->qp_type; 5390 qp_init_attr->recv_cq = ibqp->recv_cq; 5391 qp_init_attr->send_cq = ibqp->send_cq; 5392 qp_init_attr->srq = ibqp->srq; 5393 qp_init_attr->cap = qp_attr->cap; 5394 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5395 5396 out: 5397 mutex_unlock(&hr_qp->mutex); 5398 return ret; 5399 } 5400 5401 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5402 { 5403 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5404 hr_qp->ibqp.qp_type == IB_QPT_UD || 5405 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5406 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5407 hr_qp->state != IB_QPS_RESET); 5408 } 5409 5410 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5411 struct hns_roce_qp *hr_qp, 5412 struct ib_udata *udata) 5413 { 5414 struct ib_device *ibdev = &hr_dev->ib_dev; 5415 struct hns_roce_cq *send_cq, *recv_cq; 5416 unsigned long flags; 5417 int ret = 0; 5418 5419 if (modify_qp_is_ok(hr_qp)) { 5420 /* Modify qp to reset before destroying qp */ 5421 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5422 hr_qp->state, IB_QPS_RESET, udata); 5423 if (ret) 5424 ibdev_err(ibdev, 5425 "failed to modify QP to RST, ret = %d.\n", 5426 ret); 5427 } 5428 5429 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5430 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5431 5432 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5433 hns_roce_lock_cqs(send_cq, recv_cq); 5434 5435 if (!udata) { 5436 if (recv_cq) 5437 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5438 (hr_qp->ibqp.srq ? 5439 to_hr_srq(hr_qp->ibqp.srq) : 5440 NULL)); 5441 5442 if (send_cq && send_cq != recv_cq) 5443 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5444 } 5445 5446 hns_roce_qp_remove(hr_dev, hr_qp); 5447 5448 hns_roce_unlock_cqs(send_cq, recv_cq); 5449 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5450 5451 return ret; 5452 } 5453 5454 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5455 { 5456 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5457 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5458 int ret; 5459 5460 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5461 if (ret) 5462 ibdev_err(&hr_dev->ib_dev, 5463 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5464 hr_qp->qpn, ret); 5465 5466 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5467 5468 return 0; 5469 } 5470 5471 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5472 struct hns_roce_qp *hr_qp) 5473 { 5474 struct ib_device *ibdev = &hr_dev->ib_dev; 5475 struct hns_roce_sccc_clr_done *resp; 5476 struct hns_roce_sccc_clr *clr; 5477 struct hns_roce_cmq_desc desc; 5478 int ret, i; 5479 5480 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5481 return 0; 5482 5483 mutex_lock(&hr_dev->qp_table.scc_mutex); 5484 5485 /* set scc ctx clear done flag */ 5486 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5487 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5488 if (ret) { 5489 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5490 goto out; 5491 } 5492 5493 /* clear scc context */ 5494 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5495 clr = (struct hns_roce_sccc_clr *)desc.data; 5496 clr->qpn = cpu_to_le32(hr_qp->qpn); 5497 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5498 if (ret) { 5499 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5500 goto out; 5501 } 5502 5503 /* query scc context clear is done or not */ 5504 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5505 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5506 hns_roce_cmq_setup_basic_desc(&desc, 5507 HNS_ROCE_OPC_QUERY_SCCC, true); 5508 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5509 if (ret) { 5510 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5511 ret); 5512 goto out; 5513 } 5514 5515 if (resp->clr_done) 5516 goto out; 5517 5518 msleep(20); 5519 } 5520 5521 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5522 ret = -ETIMEDOUT; 5523 5524 out: 5525 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5526 return ret; 5527 } 5528 5529 #define DMA_IDX_SHIFT 3 5530 #define DMA_WQE_SHIFT 3 5531 5532 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5533 struct hns_roce_srq_context *ctx) 5534 { 5535 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5536 struct ib_device *ibdev = srq->ibsrq.device; 5537 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5538 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5539 dma_addr_t dma_handle_idx = 0; 5540 int ret; 5541 5542 /* Get physical address of idx que buf */ 5543 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5544 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5545 if (ret < 1) { 5546 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5547 ret); 5548 return -ENOBUFS; 5549 } 5550 5551 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5552 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5553 5554 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5555 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5556 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5557 5558 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5559 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5560 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5561 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5562 5563 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5564 to_hr_hw_page_addr(mtts_idx[0])); 5565 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5566 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5567 5568 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5569 to_hr_hw_page_addr(mtts_idx[1])); 5570 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5571 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5572 5573 return 0; 5574 } 5575 5576 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5577 { 5578 struct ib_device *ibdev = srq->ibsrq.device; 5579 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5580 struct hns_roce_srq_context *ctx = mb_buf; 5581 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5582 dma_addr_t dma_handle_wqe = 0; 5583 int ret; 5584 5585 memset(ctx, 0, sizeof(*ctx)); 5586 5587 /* Get the physical address of srq buf */ 5588 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5589 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5590 if (ret < 1) { 5591 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5592 ret); 5593 return -ENOBUFS; 5594 } 5595 5596 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5597 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5598 srq->ibsrq.srq_type == IB_SRQT_XRC); 5599 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5600 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5601 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5602 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5603 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5604 hr_reg_write(ctx, SRQC_RQWS, 5605 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5606 5607 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5608 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5609 srq->wqe_cnt)); 5610 5611 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5612 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5613 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5614 5615 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5616 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5617 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5618 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5619 5620 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5621 } 5622 5623 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5624 struct ib_srq_attr *srq_attr, 5625 enum ib_srq_attr_mask srq_attr_mask, 5626 struct ib_udata *udata) 5627 { 5628 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5629 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5630 struct hns_roce_srq_context *srq_context; 5631 struct hns_roce_srq_context *srqc_mask; 5632 struct hns_roce_cmd_mailbox *mailbox; 5633 int ret; 5634 5635 /* Resizing SRQs is not supported yet */ 5636 if (srq_attr_mask & IB_SRQ_MAX_WR) 5637 return -EINVAL; 5638 5639 if (srq_attr_mask & IB_SRQ_LIMIT) { 5640 if (srq_attr->srq_limit > srq->wqe_cnt) 5641 return -EINVAL; 5642 5643 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5644 if (IS_ERR(mailbox)) 5645 return PTR_ERR(mailbox); 5646 5647 srq_context = mailbox->buf; 5648 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5649 5650 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5651 5652 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5653 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5654 5655 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5656 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5657 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5658 if (ret) { 5659 ibdev_err(&hr_dev->ib_dev, 5660 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5661 ret); 5662 return ret; 5663 } 5664 } 5665 5666 return 0; 5667 } 5668 5669 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5670 { 5671 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5672 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5673 struct hns_roce_srq_context *srq_context; 5674 struct hns_roce_cmd_mailbox *mailbox; 5675 int ret; 5676 5677 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5678 if (IS_ERR(mailbox)) 5679 return PTR_ERR(mailbox); 5680 5681 srq_context = mailbox->buf; 5682 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5683 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5684 if (ret) { 5685 ibdev_err(&hr_dev->ib_dev, 5686 "failed to process cmd of querying SRQ, ret = %d.\n", 5687 ret); 5688 goto out; 5689 } 5690 5691 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5692 attr->max_wr = srq->wqe_cnt; 5693 attr->max_sge = srq->max_gs - srq->rsv_sge; 5694 5695 out: 5696 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5697 return ret; 5698 } 5699 5700 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5701 { 5702 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5703 struct hns_roce_v2_cq_context *cq_context; 5704 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5705 struct hns_roce_v2_cq_context *cqc_mask; 5706 struct hns_roce_cmd_mailbox *mailbox; 5707 int ret; 5708 5709 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5710 if (IS_ERR(mailbox)) 5711 return PTR_ERR(mailbox); 5712 5713 cq_context = mailbox->buf; 5714 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5715 5716 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5717 5718 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5719 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5720 5721 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5722 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5723 dev_info(hr_dev->dev, 5724 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5725 cq_period); 5726 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5727 } 5728 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5729 } 5730 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5731 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5732 5733 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5734 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5735 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5736 if (ret) 5737 ibdev_err(&hr_dev->ib_dev, 5738 "failed to process cmd when modifying CQ, ret = %d.\n", 5739 ret); 5740 5741 return ret; 5742 } 5743 5744 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5745 void *buffer) 5746 { 5747 struct hns_roce_v2_cq_context *context; 5748 struct hns_roce_cmd_mailbox *mailbox; 5749 int ret; 5750 5751 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5752 if (IS_ERR(mailbox)) 5753 return PTR_ERR(mailbox); 5754 5755 context = mailbox->buf; 5756 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5757 HNS_ROCE_CMD_QUERY_CQC, cqn); 5758 if (ret) { 5759 ibdev_err(&hr_dev->ib_dev, 5760 "failed to process cmd when querying CQ, ret = %d.\n", 5761 ret); 5762 goto err_mailbox; 5763 } 5764 5765 memcpy(buffer, context, sizeof(*context)); 5766 5767 err_mailbox: 5768 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5769 5770 return ret; 5771 } 5772 5773 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5774 void *buffer) 5775 { 5776 struct hns_roce_v2_mpt_entry *context; 5777 struct hns_roce_cmd_mailbox *mailbox; 5778 int ret; 5779 5780 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5781 if (IS_ERR(mailbox)) 5782 return PTR_ERR(mailbox); 5783 5784 context = mailbox->buf; 5785 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5786 key_to_hw_index(key)); 5787 if (ret) { 5788 ibdev_err(&hr_dev->ib_dev, 5789 "failed to process cmd when querying MPT, ret = %d.\n", 5790 ret); 5791 goto err_mailbox; 5792 } 5793 5794 memcpy(buffer, context, sizeof(*context)); 5795 5796 err_mailbox: 5797 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5798 5799 return ret; 5800 } 5801 5802 static void hns_roce_irq_work_handle(struct work_struct *work) 5803 { 5804 struct hns_roce_work *irq_work = 5805 container_of(work, struct hns_roce_work, work); 5806 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5807 5808 switch (irq_work->event_type) { 5809 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5810 ibdev_info(ibdev, "path migrated succeeded.\n"); 5811 break; 5812 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5813 ibdev_warn(ibdev, "path migration failed.\n"); 5814 break; 5815 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5816 break; 5817 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5818 ibdev_dbg(ibdev, "send queue drained.\n"); 5819 break; 5820 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5821 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5822 irq_work->queue_num, irq_work->sub_type); 5823 break; 5824 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5825 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5826 irq_work->queue_num); 5827 break; 5828 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5829 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5830 irq_work->queue_num, irq_work->sub_type); 5831 break; 5832 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5833 ibdev_dbg(ibdev, "SRQ limit reach.\n"); 5834 break; 5835 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5836 ibdev_dbg(ibdev, "SRQ last wqe reach.\n"); 5837 break; 5838 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5839 ibdev_err(ibdev, "SRQ catas error.\n"); 5840 break; 5841 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5842 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5843 break; 5844 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5845 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5846 break; 5847 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5848 ibdev_warn(ibdev, "DB overflow.\n"); 5849 break; 5850 case HNS_ROCE_EVENT_TYPE_FLR: 5851 ibdev_warn(ibdev, "function level reset.\n"); 5852 break; 5853 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5854 ibdev_err(ibdev, "xrc domain violation error.\n"); 5855 break; 5856 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5857 ibdev_err(ibdev, "invalid xrceth error.\n"); 5858 break; 5859 default: 5860 break; 5861 } 5862 5863 kfree(irq_work); 5864 } 5865 5866 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5867 struct hns_roce_eq *eq, u32 queue_num) 5868 { 5869 struct hns_roce_work *irq_work; 5870 5871 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5872 if (!irq_work) 5873 return; 5874 5875 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5876 irq_work->hr_dev = hr_dev; 5877 irq_work->event_type = eq->event_type; 5878 irq_work->sub_type = eq->sub_type; 5879 irq_work->queue_num = queue_num; 5880 queue_work(hr_dev->irq_workq, &irq_work->work); 5881 } 5882 5883 static void update_eq_db(struct hns_roce_eq *eq) 5884 { 5885 struct hns_roce_dev *hr_dev = eq->hr_dev; 5886 struct hns_roce_v2_db eq_db = {}; 5887 5888 if (eq->type_flag == HNS_ROCE_AEQ) { 5889 hr_reg_write(&eq_db, EQ_DB_CMD, 5890 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5891 HNS_ROCE_EQ_DB_CMD_AEQ : 5892 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5893 } else { 5894 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5895 5896 hr_reg_write(&eq_db, EQ_DB_CMD, 5897 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5898 HNS_ROCE_EQ_DB_CMD_CEQ : 5899 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5900 } 5901 5902 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5903 5904 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5905 } 5906 5907 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5908 { 5909 struct hns_roce_aeqe *aeqe; 5910 5911 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5912 (eq->cons_index & (eq->entries - 1)) * 5913 eq->eqe_size); 5914 5915 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5916 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5917 } 5918 5919 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5920 struct hns_roce_eq *eq) 5921 { 5922 struct device *dev = hr_dev->dev; 5923 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5924 irqreturn_t aeqe_found = IRQ_NONE; 5925 int event_type; 5926 u32 queue_num; 5927 int sub_type; 5928 5929 while (aeqe) { 5930 /* Make sure we read AEQ entry after we have checked the 5931 * ownership bit 5932 */ 5933 dma_rmb(); 5934 5935 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5936 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5937 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5938 5939 switch (event_type) { 5940 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5941 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5942 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5943 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5944 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5945 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5946 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5947 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5948 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5949 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5950 hns_roce_qp_event(hr_dev, queue_num, event_type); 5951 break; 5952 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5953 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5954 hns_roce_srq_event(hr_dev, queue_num, event_type); 5955 break; 5956 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5957 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5958 hns_roce_cq_event(hr_dev, queue_num, event_type); 5959 break; 5960 case HNS_ROCE_EVENT_TYPE_MB: 5961 hns_roce_cmd_event(hr_dev, 5962 le16_to_cpu(aeqe->event.cmd.token), 5963 aeqe->event.cmd.status, 5964 le64_to_cpu(aeqe->event.cmd.out_param)); 5965 break; 5966 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5967 case HNS_ROCE_EVENT_TYPE_FLR: 5968 break; 5969 default: 5970 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 5971 event_type, eq->eqn, eq->cons_index); 5972 break; 5973 } 5974 5975 eq->event_type = event_type; 5976 eq->sub_type = sub_type; 5977 ++eq->cons_index; 5978 aeqe_found = IRQ_HANDLED; 5979 5980 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5981 5982 aeqe = next_aeqe_sw_v2(eq); 5983 } 5984 5985 update_eq_db(eq); 5986 5987 return IRQ_RETVAL(aeqe_found); 5988 } 5989 5990 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5991 { 5992 struct hns_roce_ceqe *ceqe; 5993 5994 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5995 (eq->cons_index & (eq->entries - 1)) * 5996 eq->eqe_size); 5997 5998 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 5999 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6000 } 6001 6002 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6003 struct hns_roce_eq *eq) 6004 { 6005 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6006 irqreturn_t ceqe_found = IRQ_NONE; 6007 u32 cqn; 6008 6009 while (ceqe) { 6010 /* Make sure we read CEQ entry after we have checked the 6011 * ownership bit 6012 */ 6013 dma_rmb(); 6014 6015 cqn = hr_reg_read(ceqe, CEQE_CQN); 6016 6017 hns_roce_cq_completion(hr_dev, cqn); 6018 6019 ++eq->cons_index; 6020 ceqe_found = IRQ_HANDLED; 6021 6022 ceqe = next_ceqe_sw_v2(eq); 6023 } 6024 6025 update_eq_db(eq); 6026 6027 return IRQ_RETVAL(ceqe_found); 6028 } 6029 6030 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6031 { 6032 struct hns_roce_eq *eq = eq_ptr; 6033 struct hns_roce_dev *hr_dev = eq->hr_dev; 6034 irqreturn_t int_work; 6035 6036 if (eq->type_flag == HNS_ROCE_CEQ) 6037 /* Completion event interrupt */ 6038 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6039 else 6040 /* Asynchronous event interrupt */ 6041 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6042 6043 return IRQ_RETVAL(int_work); 6044 } 6045 6046 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6047 u32 int_st) 6048 { 6049 struct pci_dev *pdev = hr_dev->pci_dev; 6050 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6051 const struct hnae3_ae_ops *ops = ae_dev->ops; 6052 irqreturn_t int_work = IRQ_NONE; 6053 u32 int_en; 6054 6055 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6056 6057 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6058 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6059 6060 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6061 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6062 6063 /* Set reset level for reset_event() */ 6064 if (ops->set_default_reset_request) 6065 ops->set_default_reset_request(ae_dev, 6066 HNAE3_FUNC_RESET); 6067 if (ops->reset_event) 6068 ops->reset_event(pdev, NULL); 6069 6070 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6071 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6072 6073 int_work = IRQ_HANDLED; 6074 } else { 6075 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6076 } 6077 6078 return IRQ_RETVAL(int_work); 6079 } 6080 6081 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6082 struct fmea_ram_ecc *ecc_info) 6083 { 6084 struct hns_roce_cmq_desc desc; 6085 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6086 int ret; 6087 6088 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6089 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6090 if (ret) 6091 return ret; 6092 6093 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6094 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6095 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6096 6097 return 0; 6098 } 6099 6100 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6101 { 6102 struct hns_roce_cmq_desc desc; 6103 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6104 u32 addr_upper; 6105 u32 addr_low; 6106 int ret; 6107 6108 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6109 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6110 6111 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6112 if (ret) { 6113 dev_err(hr_dev->dev, 6114 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6115 return ret; 6116 } 6117 6118 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6119 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6120 6121 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6122 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6123 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6124 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6125 6126 return hns_roce_cmq_send(hr_dev, &desc, 1); 6127 } 6128 6129 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6130 { 6131 if (res_type == ECC_RESOURCE_QPC_TIMER || 6132 res_type == ECC_RESOURCE_CQC_TIMER || 6133 res_type == ECC_RESOURCE_SCCC) 6134 return le64_to_cpu(*data); 6135 6136 return le64_to_cpu(*data) << PAGE_SHIFT; 6137 } 6138 6139 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6140 u32 index) 6141 { 6142 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6143 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6144 struct hns_roce_cmd_mailbox *mailbox; 6145 u64 addr; 6146 int ret; 6147 6148 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6149 if (IS_ERR(mailbox)) 6150 return PTR_ERR(mailbox); 6151 6152 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6153 if (ret) { 6154 dev_err(hr_dev->dev, 6155 "failed to execute cmd to read fmea ram, ret = %d.\n", 6156 ret); 6157 goto out; 6158 } 6159 6160 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6161 6162 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6163 if (ret) 6164 dev_err(hr_dev->dev, 6165 "failed to execute cmd to write fmea ram, ret = %d.\n", 6166 ret); 6167 6168 out: 6169 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6170 return ret; 6171 } 6172 6173 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6174 struct fmea_ram_ecc *ecc_info) 6175 { 6176 u32 res_type = ecc_info->res_type; 6177 u32 index = ecc_info->index; 6178 int ret; 6179 6180 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6181 6182 if (res_type >= ECC_RESOURCE_COUNT) { 6183 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6184 res_type); 6185 return; 6186 } 6187 6188 if (res_type == ECC_RESOURCE_GMV) 6189 ret = fmea_recover_gmv(hr_dev, index); 6190 else 6191 ret = fmea_recover_others(hr_dev, res_type, index); 6192 if (ret) 6193 dev_err(hr_dev->dev, 6194 "failed to recover %s, index = %u, ret = %d.\n", 6195 fmea_ram_res[res_type].name, index, ret); 6196 } 6197 6198 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6199 { 6200 struct hns_roce_dev *hr_dev = 6201 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6202 struct fmea_ram_ecc ecc_info = {}; 6203 6204 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6205 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6206 return; 6207 } 6208 6209 if (!ecc_info.is_ecc_err) { 6210 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6211 return; 6212 } 6213 6214 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6215 } 6216 6217 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6218 { 6219 struct hns_roce_dev *hr_dev = dev_id; 6220 irqreturn_t int_work = IRQ_NONE; 6221 u32 int_st; 6222 6223 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6224 6225 if (int_st) { 6226 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6227 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6228 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6229 int_work = IRQ_HANDLED; 6230 } else { 6231 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6232 } 6233 6234 return IRQ_RETVAL(int_work); 6235 } 6236 6237 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6238 int eq_num, u32 enable_flag) 6239 { 6240 int i; 6241 6242 for (i = 0; i < eq_num; i++) 6243 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6244 i * EQ_REG_OFFSET, enable_flag); 6245 6246 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6247 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6248 } 6249 6250 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6251 { 6252 struct device *dev = hr_dev->dev; 6253 int ret; 6254 u8 cmd; 6255 6256 if (eqn < hr_dev->caps.num_comp_vectors) 6257 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6258 else 6259 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6260 6261 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6262 if (ret) 6263 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6264 } 6265 6266 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6267 { 6268 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6269 } 6270 6271 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6272 { 6273 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6274 eq->cons_index = 0; 6275 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6276 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6277 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6278 eq->shift = ilog2((unsigned int)eq->entries); 6279 } 6280 6281 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6282 void *mb_buf) 6283 { 6284 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6285 struct hns_roce_eq_context *eqc; 6286 u64 bt_ba = 0; 6287 int count; 6288 6289 eqc = mb_buf; 6290 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6291 6292 init_eq_config(hr_dev, eq); 6293 6294 /* if not multi-hop, eqe buffer only use one trunk */ 6295 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6296 &bt_ba); 6297 if (count < 1) { 6298 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6299 return -ENOBUFS; 6300 } 6301 6302 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6303 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6304 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6305 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6306 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6307 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6308 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6309 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6310 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6311 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6312 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6313 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6314 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6315 6316 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6317 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6318 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6319 eq->eq_period); 6320 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6321 } 6322 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6323 } 6324 6325 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6326 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6327 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6328 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6329 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6330 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6331 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6332 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6333 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6334 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6335 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6336 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6337 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6338 6339 return 0; 6340 } 6341 6342 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6343 { 6344 struct hns_roce_buf_attr buf_attr = {}; 6345 int err; 6346 6347 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6348 eq->hop_num = 0; 6349 else 6350 eq->hop_num = hr_dev->caps.eqe_hop_num; 6351 6352 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6353 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6354 buf_attr.region[0].hopnum = eq->hop_num; 6355 buf_attr.region_count = 1; 6356 6357 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6358 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6359 0); 6360 if (err) 6361 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6362 6363 return err; 6364 } 6365 6366 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6367 struct hns_roce_eq *eq, u8 eq_cmd) 6368 { 6369 struct hns_roce_cmd_mailbox *mailbox; 6370 int ret; 6371 6372 /* Allocate mailbox memory */ 6373 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6374 if (IS_ERR(mailbox)) 6375 return PTR_ERR(mailbox); 6376 6377 ret = alloc_eq_buf(hr_dev, eq); 6378 if (ret) 6379 goto free_cmd_mbox; 6380 6381 ret = config_eqc(hr_dev, eq, mailbox->buf); 6382 if (ret) 6383 goto err_cmd_mbox; 6384 6385 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6386 if (ret) { 6387 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6388 goto err_cmd_mbox; 6389 } 6390 6391 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6392 6393 return 0; 6394 6395 err_cmd_mbox: 6396 free_eq_buf(hr_dev, eq); 6397 6398 free_cmd_mbox: 6399 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6400 6401 return ret; 6402 } 6403 6404 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6405 int comp_num, int aeq_num, int other_num) 6406 { 6407 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6408 int i, j; 6409 int ret; 6410 6411 for (i = 0; i < irq_num; i++) { 6412 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6413 GFP_KERNEL); 6414 if (!hr_dev->irq_names[i]) { 6415 ret = -ENOMEM; 6416 goto err_kzalloc_failed; 6417 } 6418 } 6419 6420 /* irq contains: abnormal + AEQ + CEQ */ 6421 for (j = 0; j < other_num; j++) 6422 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6423 "hns-abn-%d", j); 6424 6425 for (j = other_num; j < (other_num + aeq_num); j++) 6426 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6427 "hns-aeq-%d", j - other_num); 6428 6429 for (j = (other_num + aeq_num); j < irq_num; j++) 6430 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6431 "hns-ceq-%d", j - other_num - aeq_num); 6432 6433 for (j = 0; j < irq_num; j++) { 6434 if (j < other_num) 6435 ret = request_irq(hr_dev->irq[j], 6436 hns_roce_v2_msix_interrupt_abn, 6437 0, hr_dev->irq_names[j], hr_dev); 6438 6439 else if (j < (other_num + comp_num)) 6440 ret = request_irq(eq_table->eq[j - other_num].irq, 6441 hns_roce_v2_msix_interrupt_eq, 6442 0, hr_dev->irq_names[j + aeq_num], 6443 &eq_table->eq[j - other_num]); 6444 else 6445 ret = request_irq(eq_table->eq[j - other_num].irq, 6446 hns_roce_v2_msix_interrupt_eq, 6447 0, hr_dev->irq_names[j - comp_num], 6448 &eq_table->eq[j - other_num]); 6449 if (ret) { 6450 dev_err(hr_dev->dev, "request irq error!\n"); 6451 goto err_request_failed; 6452 } 6453 } 6454 6455 return 0; 6456 6457 err_request_failed: 6458 for (j -= 1; j >= 0; j--) 6459 if (j < other_num) 6460 free_irq(hr_dev->irq[j], hr_dev); 6461 else 6462 free_irq(eq_table->eq[j - other_num].irq, 6463 &eq_table->eq[j - other_num]); 6464 6465 err_kzalloc_failed: 6466 for (i -= 1; i >= 0; i--) 6467 kfree(hr_dev->irq_names[i]); 6468 6469 return ret; 6470 } 6471 6472 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6473 { 6474 int irq_num; 6475 int eq_num; 6476 int i; 6477 6478 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6479 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6480 6481 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6482 free_irq(hr_dev->irq[i], hr_dev); 6483 6484 for (i = 0; i < eq_num; i++) 6485 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6486 6487 for (i = 0; i < irq_num; i++) 6488 kfree(hr_dev->irq_names[i]); 6489 } 6490 6491 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6492 { 6493 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6494 struct device *dev = hr_dev->dev; 6495 struct hns_roce_eq *eq; 6496 int other_num; 6497 int comp_num; 6498 int aeq_num; 6499 int irq_num; 6500 int eq_num; 6501 u8 eq_cmd; 6502 int ret; 6503 int i; 6504 6505 other_num = hr_dev->caps.num_other_vectors; 6506 comp_num = hr_dev->caps.num_comp_vectors; 6507 aeq_num = hr_dev->caps.num_aeq_vectors; 6508 6509 eq_num = comp_num + aeq_num; 6510 irq_num = eq_num + other_num; 6511 6512 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6513 if (!eq_table->eq) 6514 return -ENOMEM; 6515 6516 /* create eq */ 6517 for (i = 0; i < eq_num; i++) { 6518 eq = &eq_table->eq[i]; 6519 eq->hr_dev = hr_dev; 6520 eq->eqn = i; 6521 if (i < comp_num) { 6522 /* CEQ */ 6523 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6524 eq->type_flag = HNS_ROCE_CEQ; 6525 eq->entries = hr_dev->caps.ceqe_depth; 6526 eq->eqe_size = hr_dev->caps.ceqe_size; 6527 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6528 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6529 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6530 } else { 6531 /* AEQ */ 6532 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6533 eq->type_flag = HNS_ROCE_AEQ; 6534 eq->entries = hr_dev->caps.aeqe_depth; 6535 eq->eqe_size = hr_dev->caps.aeqe_size; 6536 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6537 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6538 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6539 } 6540 6541 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6542 if (ret) { 6543 dev_err(dev, "failed to create eq.\n"); 6544 goto err_create_eq_fail; 6545 } 6546 } 6547 6548 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6549 6550 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6551 if (!hr_dev->irq_workq) { 6552 dev_err(dev, "failed to create irq workqueue.\n"); 6553 ret = -ENOMEM; 6554 goto err_create_eq_fail; 6555 } 6556 6557 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6558 other_num); 6559 if (ret) { 6560 dev_err(dev, "failed to request irq.\n"); 6561 goto err_request_irq_fail; 6562 } 6563 6564 /* enable irq */ 6565 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6566 6567 return 0; 6568 6569 err_request_irq_fail: 6570 destroy_workqueue(hr_dev->irq_workq); 6571 6572 err_create_eq_fail: 6573 for (i -= 1; i >= 0; i--) 6574 free_eq_buf(hr_dev, &eq_table->eq[i]); 6575 kfree(eq_table->eq); 6576 6577 return ret; 6578 } 6579 6580 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6581 { 6582 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6583 int eq_num; 6584 int i; 6585 6586 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6587 6588 /* Disable irq */ 6589 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6590 6591 __hns_roce_free_irq(hr_dev); 6592 destroy_workqueue(hr_dev->irq_workq); 6593 6594 for (i = 0; i < eq_num; i++) { 6595 hns_roce_v2_destroy_eqc(hr_dev, i); 6596 6597 free_eq_buf(hr_dev, &eq_table->eq[i]); 6598 } 6599 6600 kfree(eq_table->eq); 6601 } 6602 6603 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6604 .destroy_qp = hns_roce_v2_destroy_qp, 6605 .modify_cq = hns_roce_v2_modify_cq, 6606 .poll_cq = hns_roce_v2_poll_cq, 6607 .post_recv = hns_roce_v2_post_recv, 6608 .post_send = hns_roce_v2_post_send, 6609 .query_qp = hns_roce_v2_query_qp, 6610 .req_notify_cq = hns_roce_v2_req_notify_cq, 6611 }; 6612 6613 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6614 .modify_srq = hns_roce_v2_modify_srq, 6615 .post_srq_recv = hns_roce_v2_post_srq_recv, 6616 .query_srq = hns_roce_v2_query_srq, 6617 }; 6618 6619 static const struct hns_roce_hw hns_roce_hw_v2 = { 6620 .cmq_init = hns_roce_v2_cmq_init, 6621 .cmq_exit = hns_roce_v2_cmq_exit, 6622 .hw_profile = hns_roce_v2_profile, 6623 .hw_init = hns_roce_v2_init, 6624 .hw_exit = hns_roce_v2_exit, 6625 .post_mbox = v2_post_mbox, 6626 .poll_mbox_done = v2_poll_mbox_done, 6627 .chk_mbox_avail = v2_chk_mbox_is_avail, 6628 .set_gid = hns_roce_v2_set_gid, 6629 .set_mac = hns_roce_v2_set_mac, 6630 .write_mtpt = hns_roce_v2_write_mtpt, 6631 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6632 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6633 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6634 .write_cqc = hns_roce_v2_write_cqc, 6635 .set_hem = hns_roce_v2_set_hem, 6636 .clear_hem = hns_roce_v2_clear_hem, 6637 .modify_qp = hns_roce_v2_modify_qp, 6638 .dereg_mr = hns_roce_v2_dereg_mr, 6639 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6640 .init_eq = hns_roce_v2_init_eq_table, 6641 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6642 .write_srqc = hns_roce_v2_write_srqc, 6643 .query_cqc = hns_roce_v2_query_cqc, 6644 .query_qpc = hns_roce_v2_query_qpc, 6645 .query_mpt = hns_roce_v2_query_mpt, 6646 .query_hw_counter = hns_roce_hw_v2_query_counter, 6647 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6648 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6649 }; 6650 6651 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6652 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6653 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6654 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6655 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6656 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6657 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6658 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6659 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6660 /* required last entry */ 6661 {0, } 6662 }; 6663 6664 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6665 6666 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6667 struct hnae3_handle *handle) 6668 { 6669 struct hns_roce_v2_priv *priv = hr_dev->priv; 6670 const struct pci_device_id *id; 6671 int i; 6672 6673 hr_dev->pci_dev = handle->pdev; 6674 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6675 hr_dev->is_vf = id->driver_data; 6676 hr_dev->dev = &handle->pdev->dev; 6677 hr_dev->hw = &hns_roce_hw_v2; 6678 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6679 hr_dev->odb_offset = hr_dev->sdb_offset; 6680 6681 /* Get info from NIC driver. */ 6682 hr_dev->reg_base = handle->rinfo.roce_io_base; 6683 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6684 hr_dev->caps.num_ports = 1; 6685 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6686 hr_dev->iboe.phy_port[0] = 0; 6687 6688 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6689 hr_dev->iboe.netdevs[0]->dev_addr); 6690 6691 for (i = 0; i < handle->rinfo.num_vectors; i++) 6692 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6693 i + handle->rinfo.base_vector); 6694 6695 /* cmd issue mode: 0 is poll, 1 is event */ 6696 hr_dev->cmd_mod = 1; 6697 hr_dev->loop_idc = 0; 6698 6699 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6700 priv->handle = handle; 6701 } 6702 6703 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6704 { 6705 struct hns_roce_dev *hr_dev; 6706 int ret; 6707 6708 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6709 if (!hr_dev) 6710 return -ENOMEM; 6711 6712 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6713 if (!hr_dev->priv) { 6714 ret = -ENOMEM; 6715 goto error_failed_kzalloc; 6716 } 6717 6718 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6719 6720 ret = hns_roce_init(hr_dev); 6721 if (ret) { 6722 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6723 goto error_failed_roce_init; 6724 } 6725 6726 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6727 ret = free_mr_init(hr_dev); 6728 if (ret) { 6729 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6730 goto error_failed_free_mr_init; 6731 } 6732 } 6733 6734 handle->priv = hr_dev; 6735 6736 return 0; 6737 6738 error_failed_free_mr_init: 6739 hns_roce_exit(hr_dev); 6740 6741 error_failed_roce_init: 6742 kfree(hr_dev->priv); 6743 6744 error_failed_kzalloc: 6745 ib_dealloc_device(&hr_dev->ib_dev); 6746 6747 return ret; 6748 } 6749 6750 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6751 bool reset) 6752 { 6753 struct hns_roce_dev *hr_dev = handle->priv; 6754 6755 if (!hr_dev) 6756 return; 6757 6758 handle->priv = NULL; 6759 6760 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6761 hns_roce_handle_device_err(hr_dev); 6762 6763 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6764 free_mr_exit(hr_dev); 6765 6766 hns_roce_exit(hr_dev); 6767 kfree(hr_dev->priv); 6768 ib_dealloc_device(&hr_dev->ib_dev); 6769 } 6770 6771 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6772 { 6773 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6774 const struct pci_device_id *id; 6775 struct device *dev = &handle->pdev->dev; 6776 int ret; 6777 6778 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6779 6780 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6781 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6782 goto reset_chk_err; 6783 } 6784 6785 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6786 if (!id) 6787 return 0; 6788 6789 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6790 return 0; 6791 6792 ret = __hns_roce_hw_v2_init_instance(handle); 6793 if (ret) { 6794 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6795 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6796 if (ops->ae_dev_resetting(handle) || 6797 ops->get_hw_reset_stat(handle)) 6798 goto reset_chk_err; 6799 else 6800 return ret; 6801 } 6802 6803 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6804 6805 return 0; 6806 6807 reset_chk_err: 6808 dev_err(dev, "Device is busy in resetting state.\n" 6809 "please retry later.\n"); 6810 6811 return -EBUSY; 6812 } 6813 6814 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6815 bool reset) 6816 { 6817 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6818 return; 6819 6820 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6821 6822 __hns_roce_hw_v2_uninit_instance(handle, reset); 6823 6824 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6825 } 6826 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6827 { 6828 struct hns_roce_dev *hr_dev; 6829 6830 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6831 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6832 return 0; 6833 } 6834 6835 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6836 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6837 6838 hr_dev = handle->priv; 6839 if (!hr_dev) 6840 return 0; 6841 6842 hr_dev->active = false; 6843 hr_dev->dis_db = true; 6844 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6845 6846 return 0; 6847 } 6848 6849 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6850 { 6851 struct device *dev = &handle->pdev->dev; 6852 int ret; 6853 6854 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6855 &handle->rinfo.state)) { 6856 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6857 return 0; 6858 } 6859 6860 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6861 6862 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6863 ret = __hns_roce_hw_v2_init_instance(handle); 6864 if (ret) { 6865 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6866 * callback function, RoCE Engine reinitialize. If RoCE reinit 6867 * failed, we should inform NIC driver. 6868 */ 6869 handle->priv = NULL; 6870 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6871 } else { 6872 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6873 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6874 } 6875 6876 return ret; 6877 } 6878 6879 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6880 { 6881 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6882 return 0; 6883 6884 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6885 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6886 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6887 __hns_roce_hw_v2_uninit_instance(handle, false); 6888 6889 return 0; 6890 } 6891 6892 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6893 enum hnae3_reset_notify_type type) 6894 { 6895 int ret = 0; 6896 6897 switch (type) { 6898 case HNAE3_DOWN_CLIENT: 6899 ret = hns_roce_hw_v2_reset_notify_down(handle); 6900 break; 6901 case HNAE3_INIT_CLIENT: 6902 ret = hns_roce_hw_v2_reset_notify_init(handle); 6903 break; 6904 case HNAE3_UNINIT_CLIENT: 6905 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6906 break; 6907 default: 6908 break; 6909 } 6910 6911 return ret; 6912 } 6913 6914 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6915 .init_instance = hns_roce_hw_v2_init_instance, 6916 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6917 .reset_notify = hns_roce_hw_v2_reset_notify, 6918 }; 6919 6920 static struct hnae3_client hns_roce_hw_v2_client = { 6921 .name = "hns_roce_hw_v2", 6922 .type = HNAE3_CLIENT_ROCE, 6923 .ops = &hns_roce_hw_v2_ops, 6924 }; 6925 6926 static int __init hns_roce_hw_v2_init(void) 6927 { 6928 return hnae3_register_client(&hns_roce_hw_v2_client); 6929 } 6930 6931 static void __exit hns_roce_hw_v2_exit(void) 6932 { 6933 hnae3_unregister_client(&hns_roce_hw_v2_client); 6934 } 6935 6936 module_init(hns_roce_hw_v2_init); 6937 module_exit(hns_roce_hw_v2_exit); 6938 6939 MODULE_LICENSE("Dual BSD/GPL"); 6940 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6941 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6942 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6943 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6944