1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 enum ecc_resource_type { 59 ECC_RESOURCE_QPC, 60 ECC_RESOURCE_CQC, 61 ECC_RESOURCE_MPT, 62 ECC_RESOURCE_SRQC, 63 ECC_RESOURCE_GMV, 64 ECC_RESOURCE_QPC_TIMER, 65 ECC_RESOURCE_CQC_TIMER, 66 ECC_RESOURCE_SCCC, 67 ECC_RESOURCE_COUNT, 68 }; 69 70 static const struct { 71 const char *name; 72 u8 read_bt0_op; 73 u8 write_bt0_op; 74 } fmea_ram_res[] = { 75 { "ECC_RESOURCE_QPC", 76 HNS_ROCE_CMD_READ_QPC_BT0, HNS_ROCE_CMD_WRITE_QPC_BT0 }, 77 { "ECC_RESOURCE_CQC", 78 HNS_ROCE_CMD_READ_CQC_BT0, HNS_ROCE_CMD_WRITE_CQC_BT0 }, 79 { "ECC_RESOURCE_MPT", 80 HNS_ROCE_CMD_READ_MPT_BT0, HNS_ROCE_CMD_WRITE_MPT_BT0 }, 81 { "ECC_RESOURCE_SRQC", 82 HNS_ROCE_CMD_READ_SRQC_BT0, HNS_ROCE_CMD_WRITE_SRQC_BT0 }, 83 /* ECC_RESOURCE_GMV is handled by cmdq, not mailbox */ 84 { "ECC_RESOURCE_GMV", 85 0, 0 }, 86 { "ECC_RESOURCE_QPC_TIMER", 87 HNS_ROCE_CMD_READ_QPC_TIMER_BT0, HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0 }, 88 { "ECC_RESOURCE_CQC_TIMER", 89 HNS_ROCE_CMD_READ_CQC_TIMER_BT0, HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0 }, 90 { "ECC_RESOURCE_SCCC", 91 HNS_ROCE_CMD_READ_SCCC_BT0, HNS_ROCE_CMD_WRITE_SCCC_BT0 }, 92 }; 93 94 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 95 struct ib_sge *sg) 96 { 97 dseg->lkey = cpu_to_le32(sg->lkey); 98 dseg->addr = cpu_to_le64(sg->addr); 99 dseg->len = cpu_to_le32(sg->length); 100 } 101 102 /* 103 * mapped-value = 1 + real-value 104 * The hns wr opcode real value is start from 0, In order to distinguish between 105 * initialized and uninitialized map values, we plus 1 to the actual value when 106 * defining the mapping, so that the validity can be identified by checking the 107 * mapped value is greater than 0. 108 */ 109 #define HR_OPC_MAP(ib_key, hr_key) \ 110 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 111 112 static const u32 hns_roce_op_code[] = { 113 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 114 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 115 HR_OPC_MAP(SEND, SEND), 116 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 117 HR_OPC_MAP(RDMA_READ, RDMA_READ), 118 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 119 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 120 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 121 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 122 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 123 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 124 }; 125 126 static u32 to_hr_opcode(u32 ib_opcode) 127 { 128 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 129 return HNS_ROCE_V2_WQE_OP_MASK; 130 131 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 132 HNS_ROCE_V2_WQE_OP_MASK; 133 } 134 135 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 136 const struct ib_reg_wr *wr) 137 { 138 struct hns_roce_wqe_frmr_seg *fseg = 139 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 140 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 141 u64 pbl_ba; 142 143 /* use ib_access_flags */ 144 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 145 hr_reg_write_bool(fseg, FRMR_ATOMIC, 146 wr->access & IB_ACCESS_REMOTE_ATOMIC); 147 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 148 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 149 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 150 151 /* Data structure reuse may lead to confusion */ 152 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 153 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 154 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 155 156 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 157 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 158 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 159 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 160 161 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 162 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 163 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 164 hr_reg_clear(fseg, FRMR_BLK_MODE); 165 } 166 167 static void set_atomic_seg(const struct ib_send_wr *wr, 168 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 169 unsigned int valid_num_sge) 170 { 171 struct hns_roce_v2_wqe_data_seg *dseg = 172 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 173 struct hns_roce_wqe_atomic_seg *aseg = 174 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 175 176 set_data_seg_v2(dseg, wr->sg_list); 177 178 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 179 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 180 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 181 } else { 182 aseg->fetchadd_swap_data = 183 cpu_to_le64(atomic_wr(wr)->compare_add); 184 aseg->cmp_data = 0; 185 } 186 187 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 188 } 189 190 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 191 const struct ib_send_wr *wr, 192 unsigned int *sge_idx, u32 msg_len) 193 { 194 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 195 unsigned int left_len_in_pg; 196 unsigned int idx = *sge_idx; 197 unsigned int i = 0; 198 unsigned int len; 199 void *addr; 200 void *dseg; 201 202 if (msg_len > qp->sq.ext_sge_cnt * HNS_ROCE_SGE_SIZE) { 203 ibdev_err(ibdev, 204 "no enough extended sge space for inline data.\n"); 205 return -EINVAL; 206 } 207 208 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 209 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 210 len = wr->sg_list[0].length; 211 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 212 213 /* When copying data to extended sge space, the left length in page may 214 * not long enough for current user's sge. So the data should be 215 * splited into several parts, one in the first page, and the others in 216 * the subsequent pages. 217 */ 218 while (1) { 219 if (len <= left_len_in_pg) { 220 memcpy(dseg, addr, len); 221 222 idx += len / HNS_ROCE_SGE_SIZE; 223 224 i++; 225 if (i >= wr->num_sge) 226 break; 227 228 left_len_in_pg -= len; 229 len = wr->sg_list[i].length; 230 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 231 dseg += len; 232 } else { 233 memcpy(dseg, addr, left_len_in_pg); 234 235 len -= left_len_in_pg; 236 addr += left_len_in_pg; 237 idx += left_len_in_pg / HNS_ROCE_SGE_SIZE; 238 dseg = hns_roce_get_extend_sge(qp, 239 idx & (qp->sge.sge_cnt - 1)); 240 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 241 } 242 } 243 244 *sge_idx = idx; 245 246 return 0; 247 } 248 249 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 250 unsigned int *sge_ind, unsigned int cnt) 251 { 252 struct hns_roce_v2_wqe_data_seg *dseg; 253 unsigned int idx = *sge_ind; 254 255 while (cnt > 0) { 256 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 257 if (likely(sge->length)) { 258 set_data_seg_v2(dseg, sge); 259 idx++; 260 cnt--; 261 } 262 sge++; 263 } 264 265 *sge_ind = idx; 266 } 267 268 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 269 { 270 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 271 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 272 273 if (len > qp->max_inline_data || len > mtu) { 274 ibdev_err(&hr_dev->ib_dev, 275 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 276 len, qp->max_inline_data, mtu); 277 return false; 278 } 279 280 return true; 281 } 282 283 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 284 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 285 unsigned int *sge_idx) 286 { 287 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 288 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 289 struct ib_device *ibdev = &hr_dev->ib_dev; 290 unsigned int curr_idx = *sge_idx; 291 void *dseg = rc_sq_wqe; 292 unsigned int i; 293 int ret; 294 295 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 296 ibdev_err(ibdev, "invalid inline parameters!\n"); 297 return -EINVAL; 298 } 299 300 if (!check_inl_data_len(qp, msg_len)) 301 return -EINVAL; 302 303 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 304 305 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 306 hr_reg_clear(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 307 308 for (i = 0; i < wr->num_sge; i++) { 309 memcpy(dseg, ((void *)wr->sg_list[i].addr), 310 wr->sg_list[i].length); 311 dseg += wr->sg_list[i].length; 312 } 313 } else { 314 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_INL_TYPE); 315 316 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 317 if (ret) 318 return ret; 319 320 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, curr_idx - *sge_idx); 321 } 322 323 *sge_idx = curr_idx; 324 325 return 0; 326 } 327 328 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 329 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 330 unsigned int *sge_ind, 331 unsigned int valid_num_sge) 332 { 333 struct hns_roce_v2_wqe_data_seg *dseg = 334 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 335 struct hns_roce_qp *qp = to_hr_qp(ibqp); 336 int j = 0; 337 int i; 338 339 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_MSG_START_SGE_IDX, 340 (*sge_ind) & (qp->sge.sge_cnt - 1)); 341 342 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_INLINE, 343 !!(wr->send_flags & IB_SEND_INLINE)); 344 if (wr->send_flags & IB_SEND_INLINE) 345 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 346 347 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 348 for (i = 0; i < wr->num_sge; i++) { 349 if (likely(wr->sg_list[i].length)) { 350 set_data_seg_v2(dseg, wr->sg_list + i); 351 dseg++; 352 } 353 } 354 } else { 355 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 356 if (likely(wr->sg_list[i].length)) { 357 set_data_seg_v2(dseg, wr->sg_list + i); 358 dseg++; 359 j++; 360 } 361 } 362 363 set_extend_sge(qp, wr->sg_list + i, sge_ind, 364 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 365 } 366 367 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SGE_NUM, valid_num_sge); 368 369 return 0; 370 } 371 372 static int check_send_valid(struct hns_roce_dev *hr_dev, 373 struct hns_roce_qp *hr_qp) 374 { 375 struct ib_device *ibdev = &hr_dev->ib_dev; 376 377 if (unlikely(hr_qp->state == IB_QPS_RESET || 378 hr_qp->state == IB_QPS_INIT || 379 hr_qp->state == IB_QPS_RTR)) { 380 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 381 hr_qp->state); 382 return -EINVAL; 383 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 384 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 385 hr_dev->state); 386 return -EIO; 387 } 388 389 return 0; 390 } 391 392 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 393 unsigned int *sge_len) 394 { 395 unsigned int valid_num = 0; 396 unsigned int len = 0; 397 int i; 398 399 for (i = 0; i < wr->num_sge; i++) { 400 if (likely(wr->sg_list[i].length)) { 401 len += wr->sg_list[i].length; 402 valid_num++; 403 } 404 } 405 406 *sge_len = len; 407 return valid_num; 408 } 409 410 static __le32 get_immtdata(const struct ib_send_wr *wr) 411 { 412 switch (wr->opcode) { 413 case IB_WR_SEND_WITH_IMM: 414 case IB_WR_RDMA_WRITE_WITH_IMM: 415 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 416 default: 417 return 0; 418 } 419 } 420 421 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 422 const struct ib_send_wr *wr) 423 { 424 u32 ib_op = wr->opcode; 425 426 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 427 return -EINVAL; 428 429 ud_sq_wqe->immtdata = get_immtdata(wr); 430 431 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 432 433 return 0; 434 } 435 436 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 437 struct hns_roce_ah *ah) 438 { 439 struct ib_device *ib_dev = ah->ibah.device; 440 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 441 442 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_UDPSPN, ah->av.udp_sport); 443 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_HOPLIMIT, ah->av.hop_limit); 444 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_TCLASS, ah->av.tclass); 445 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_FLOW_LABEL, ah->av.flowlabel); 446 447 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 448 return -EINVAL; 449 450 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SL, ah->av.sl); 451 452 ud_sq_wqe->sgid_index = ah->av.gid_index; 453 454 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 455 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 456 457 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 458 return 0; 459 460 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN_EN, ah->av.vlan_en); 461 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_VLAN, ah->av.vlan_id); 462 463 return 0; 464 } 465 466 static inline int set_ud_wqe(struct hns_roce_qp *qp, 467 const struct ib_send_wr *wr, 468 void *wqe, unsigned int *sge_idx, 469 unsigned int owner_bit) 470 { 471 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 472 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 473 unsigned int curr_idx = *sge_idx; 474 unsigned int valid_num_sge; 475 u32 msg_len = 0; 476 int ret; 477 478 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 479 480 ret = set_ud_opcode(ud_sq_wqe, wr); 481 if (WARN_ON(ret)) 482 return ret; 483 484 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 485 486 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_CQE, 487 !!(wr->send_flags & IB_SEND_SIGNALED)); 488 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SE, 489 !!(wr->send_flags & IB_SEND_SOLICITED)); 490 491 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_PD, to_hr_pd(qp->ibqp.pd)->pdn); 492 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_SGE_NUM, valid_num_sge); 493 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_MSG_START_SGE_IDX, 494 curr_idx & (qp->sge.sge_cnt - 1)); 495 496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 497 qp->qkey : ud_wr(wr)->remote_qkey); 498 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_DQPN, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 hr_reg_write(ud_sq_wqe, UD_SEND_WQE_OWNER, owner_bit); 519 520 return 0; 521 } 522 523 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 524 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 525 const struct ib_send_wr *wr) 526 { 527 u32 ib_op = wr->opcode; 528 int ret = 0; 529 530 rc_sq_wqe->immtdata = get_immtdata(wr); 531 532 switch (ib_op) { 533 case IB_WR_RDMA_READ: 534 case IB_WR_RDMA_WRITE: 535 case IB_WR_RDMA_WRITE_WITH_IMM: 536 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 537 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 538 break; 539 case IB_WR_SEND: 540 case IB_WR_SEND_WITH_IMM: 541 break; 542 case IB_WR_ATOMIC_CMP_AND_SWP: 543 case IB_WR_ATOMIC_FETCH_AND_ADD: 544 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 545 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 546 break; 547 case IB_WR_REG_MR: 548 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 549 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 550 else 551 ret = -EOPNOTSUPP; 552 break; 553 case IB_WR_SEND_WITH_INV: 554 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 555 break; 556 default: 557 ret = -EINVAL; 558 } 559 560 if (unlikely(ret)) 561 return ret; 562 563 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OPCODE, to_hr_opcode(ib_op)); 564 565 return ret; 566 } 567 568 static inline int set_rc_wqe(struct hns_roce_qp *qp, 569 const struct ib_send_wr *wr, 570 void *wqe, unsigned int *sge_idx, 571 unsigned int owner_bit) 572 { 573 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 574 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 575 unsigned int curr_idx = *sge_idx; 576 unsigned int valid_num_sge; 577 u32 msg_len = 0; 578 int ret; 579 580 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 581 582 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 583 584 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 585 if (WARN_ON(ret)) 586 return ret; 587 588 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_FENCE, 589 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 590 591 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_SE, 592 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 593 594 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_CQE, 595 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 596 597 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 598 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 599 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 600 else if (wr->opcode != IB_WR_REG_MR) 601 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 602 &curr_idx, valid_num_sge); 603 604 /* 605 * The pipeline can sequentially post all valid WQEs into WQ buffer, 606 * including new WQEs waiting for the doorbell to update the PI again. 607 * Therefore, the owner bit of WQE MUST be updated after all fields 608 * and extSGEs have been written into DDR instead of cache. 609 */ 610 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 611 dma_wmb(); 612 613 *sge_idx = curr_idx; 614 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_OWNER, owner_bit); 615 616 return ret; 617 } 618 619 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 620 struct hns_roce_qp *qp) 621 { 622 if (unlikely(qp->state == IB_QPS_ERR)) { 623 flush_cqe(hr_dev, qp); 624 } else { 625 struct hns_roce_v2_db sq_db = {}; 626 627 hr_reg_write(&sq_db, DB_TAG, qp->qpn); 628 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 629 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 630 hr_reg_write(&sq_db, DB_SL, qp->sl); 631 632 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 633 } 634 } 635 636 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 637 struct hns_roce_qp *qp) 638 { 639 if (unlikely(qp->state == IB_QPS_ERR)) { 640 flush_cqe(hr_dev, qp); 641 } else { 642 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 643 *qp->rdb.db_record = 644 qp->rq.head & V2_DB_PRODUCER_IDX_M; 645 } else { 646 struct hns_roce_v2_db rq_db = {}; 647 648 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 649 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 650 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 651 652 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 653 qp->rq.db_reg); 654 } 655 } 656 } 657 658 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 659 u64 __iomem *dest) 660 { 661 #define HNS_ROCE_WRITE_TIMES 8 662 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 663 struct hnae3_handle *handle = priv->handle; 664 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 665 int i; 666 667 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 668 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 669 writeq_relaxed(*(val + i), dest + i); 670 } 671 672 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 673 void *wqe) 674 { 675 #define HNS_ROCE_SL_SHIFT 2 676 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 677 678 /* All kinds of DirectWQE have the same header field layout */ 679 hr_reg_enable(rc_sq_wqe, RC_SEND_WQE_FLAG); 680 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_L, qp->sl); 681 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_DB_SL_H, 682 qp->sl >> HNS_ROCE_SL_SHIFT); 683 hr_reg_write(rc_sq_wqe, RC_SEND_WQE_WQE_INDEX, qp->sq.head); 684 685 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 686 } 687 688 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 689 const struct ib_send_wr *wr, 690 const struct ib_send_wr **bad_wr) 691 { 692 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 693 struct ib_device *ibdev = &hr_dev->ib_dev; 694 struct hns_roce_qp *qp = to_hr_qp(ibqp); 695 unsigned long flags = 0; 696 unsigned int owner_bit; 697 unsigned int sge_idx; 698 unsigned int wqe_idx; 699 void *wqe = NULL; 700 u32 nreq; 701 int ret; 702 703 spin_lock_irqsave(&qp->sq.lock, flags); 704 705 ret = check_send_valid(hr_dev, qp); 706 if (unlikely(ret)) { 707 *bad_wr = wr; 708 nreq = 0; 709 goto out; 710 } 711 712 sge_idx = qp->next_sge; 713 714 for (nreq = 0; wr; ++nreq, wr = wr->next) { 715 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 716 ret = -ENOMEM; 717 *bad_wr = wr; 718 goto out; 719 } 720 721 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 722 723 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 724 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 725 wr->num_sge, qp->sq.max_gs); 726 ret = -EINVAL; 727 *bad_wr = wr; 728 goto out; 729 } 730 731 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 732 qp->sq.wrid[wqe_idx] = wr->wr_id; 733 owner_bit = 734 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 735 736 /* Corresponding to the QP type, wqe process separately */ 737 if (ibqp->qp_type == IB_QPT_RC) 738 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 739 else 740 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 741 742 if (unlikely(ret)) { 743 *bad_wr = wr; 744 goto out; 745 } 746 } 747 748 out: 749 if (likely(nreq)) { 750 qp->sq.head += nreq; 751 qp->next_sge = sge_idx; 752 753 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 754 write_dwqe(hr_dev, qp, wqe); 755 else 756 update_sq_db(hr_dev, qp); 757 } 758 759 spin_unlock_irqrestore(&qp->sq.lock, flags); 760 761 return ret; 762 } 763 764 static int check_recv_valid(struct hns_roce_dev *hr_dev, 765 struct hns_roce_qp *hr_qp) 766 { 767 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 768 return -EIO; 769 770 if (hr_qp->state == IB_QPS_RESET) 771 return -EINVAL; 772 773 return 0; 774 } 775 776 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 777 u32 max_sge, bool rsv) 778 { 779 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 780 u32 i, cnt; 781 782 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 783 /* Skip zero-length sge */ 784 if (!wr->sg_list[i].length) 785 continue; 786 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 787 cnt++; 788 } 789 790 /* Fill a reserved sge to make hw stop reading remaining segments */ 791 if (rsv) { 792 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 793 dseg[cnt].addr = 0; 794 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 795 } else { 796 /* Clear remaining segments to make ROCEE ignore sges */ 797 if (cnt < max_sge) 798 memset(dseg + cnt, 0, 799 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 800 } 801 } 802 803 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 804 u32 wqe_idx, u32 max_sge) 805 { 806 void *wqe = NULL; 807 808 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 809 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 810 } 811 812 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 813 const struct ib_recv_wr *wr, 814 const struct ib_recv_wr **bad_wr) 815 { 816 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 817 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 818 struct ib_device *ibdev = &hr_dev->ib_dev; 819 u32 wqe_idx, nreq, max_sge; 820 unsigned long flags; 821 int ret; 822 823 spin_lock_irqsave(&hr_qp->rq.lock, flags); 824 825 ret = check_recv_valid(hr_dev, hr_qp); 826 if (unlikely(ret)) { 827 *bad_wr = wr; 828 nreq = 0; 829 goto out; 830 } 831 832 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 833 for (nreq = 0; wr; ++nreq, wr = wr->next) { 834 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 835 hr_qp->ibqp.recv_cq))) { 836 ret = -ENOMEM; 837 *bad_wr = wr; 838 goto out; 839 } 840 841 if (unlikely(wr->num_sge > max_sge)) { 842 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 843 wr->num_sge, max_sge); 844 ret = -EINVAL; 845 *bad_wr = wr; 846 goto out; 847 } 848 849 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 850 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 851 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 852 } 853 854 out: 855 if (likely(nreq)) { 856 hr_qp->rq.head += nreq; 857 858 update_rq_db(hr_dev, hr_qp); 859 } 860 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 861 862 return ret; 863 } 864 865 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 866 { 867 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 868 } 869 870 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 871 { 872 return hns_roce_buf_offset(idx_que->mtr.kmem, 873 n << idx_que->entry_shift); 874 } 875 876 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 877 { 878 /* always called with interrupts disabled. */ 879 spin_lock(&srq->lock); 880 881 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 882 srq->idx_que.tail++; 883 884 spin_unlock(&srq->lock); 885 } 886 887 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 888 { 889 struct hns_roce_idx_que *idx_que = &srq->idx_que; 890 891 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 892 } 893 894 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 895 const struct ib_recv_wr *wr) 896 { 897 struct ib_device *ib_dev = srq->ibsrq.device; 898 899 if (unlikely(wr->num_sge > max_sge)) { 900 ibdev_err(ib_dev, 901 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 902 wr->num_sge, max_sge); 903 return -EINVAL; 904 } 905 906 if (unlikely(hns_roce_srqwq_overflow(srq))) { 907 ibdev_err(ib_dev, 908 "failed to check srqwq status, srqwq is full.\n"); 909 return -ENOMEM; 910 } 911 912 return 0; 913 } 914 915 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 916 { 917 struct hns_roce_idx_que *idx_que = &srq->idx_que; 918 u32 pos; 919 920 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 921 if (unlikely(pos == srq->wqe_cnt)) 922 return -ENOSPC; 923 924 bitmap_set(idx_que->bitmap, pos, 1); 925 *wqe_idx = pos; 926 return 0; 927 } 928 929 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 930 { 931 struct hns_roce_idx_que *idx_que = &srq->idx_que; 932 unsigned int head; 933 __le32 *buf; 934 935 head = idx_que->head & (srq->wqe_cnt - 1); 936 937 buf = get_idx_buf(idx_que, head); 938 *buf = cpu_to_le32(wqe_idx); 939 940 idx_que->head++; 941 } 942 943 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 944 { 945 hr_reg_write(db, DB_TAG, srq->srqn); 946 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 947 hr_reg_write(db, DB_PI, srq->idx_que.head); 948 } 949 950 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 951 const struct ib_recv_wr *wr, 952 const struct ib_recv_wr **bad_wr) 953 { 954 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 955 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 956 struct hns_roce_v2_db srq_db; 957 unsigned long flags; 958 int ret = 0; 959 u32 max_sge; 960 u32 wqe_idx; 961 void *wqe; 962 u32 nreq; 963 964 spin_lock_irqsave(&srq->lock, flags); 965 966 max_sge = srq->max_gs - srq->rsv_sge; 967 for (nreq = 0; wr; ++nreq, wr = wr->next) { 968 ret = check_post_srq_valid(srq, max_sge, wr); 969 if (ret) { 970 *bad_wr = wr; 971 break; 972 } 973 974 ret = get_srq_wqe_idx(srq, &wqe_idx); 975 if (unlikely(ret)) { 976 *bad_wr = wr; 977 break; 978 } 979 980 wqe = get_srq_wqe_buf(srq, wqe_idx); 981 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 982 fill_wqe_idx(srq, wqe_idx); 983 srq->wrid[wqe_idx] = wr->wr_id; 984 } 985 986 if (likely(nreq)) { 987 update_srq_db(&srq_db, srq); 988 989 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 990 } 991 992 spin_unlock_irqrestore(&srq->lock, flags); 993 994 return ret; 995 } 996 997 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 998 unsigned long instance_stage, 999 unsigned long reset_stage) 1000 { 1001 /* When hardware reset has been completed once or more, we should stop 1002 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1003 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1004 * stage of soft reset process, we should exit with error, and then 1005 * HNAE3_INIT_CLIENT related process can rollback the operation like 1006 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1007 * process will exit with error to notify NIC driver to reschedule soft 1008 * reset process once again. 1009 */ 1010 hr_dev->is_reset = true; 1011 hr_dev->dis_db = true; 1012 1013 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1014 instance_stage == HNS_ROCE_STATE_INIT) 1015 return CMD_RST_PRC_EBUSY; 1016 1017 return CMD_RST_PRC_SUCCESS; 1018 } 1019 1020 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1021 unsigned long instance_stage, 1022 unsigned long reset_stage) 1023 { 1024 #define HW_RESET_TIMEOUT_US 1000000 1025 #define HW_RESET_SLEEP_US 1000 1026 1027 struct hns_roce_v2_priv *priv = hr_dev->priv; 1028 struct hnae3_handle *handle = priv->handle; 1029 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1030 unsigned long val; 1031 int ret; 1032 1033 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1034 * doorbell to hardware. If now in .init_instance() function, we should 1035 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1036 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1037 * related process can rollback the operation like notifing hardware to 1038 * free resources, HNAE3_INIT_CLIENT related process will exit with 1039 * error to notify NIC driver to reschedule soft reset process once 1040 * again. 1041 */ 1042 hr_dev->dis_db = true; 1043 1044 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1045 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1046 HW_RESET_TIMEOUT_US, false, handle); 1047 if (!ret) 1048 hr_dev->is_reset = true; 1049 1050 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1051 instance_stage == HNS_ROCE_STATE_INIT) 1052 return CMD_RST_PRC_EBUSY; 1053 1054 return CMD_RST_PRC_SUCCESS; 1055 } 1056 1057 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1058 { 1059 struct hns_roce_v2_priv *priv = hr_dev->priv; 1060 struct hnae3_handle *handle = priv->handle; 1061 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1062 1063 /* When software reset is detected at .init_instance() function, we 1064 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1065 * with error. 1066 */ 1067 hr_dev->dis_db = true; 1068 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1069 hr_dev->is_reset = true; 1070 1071 return CMD_RST_PRC_EBUSY; 1072 } 1073 1074 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1075 struct hnae3_handle *handle) 1076 { 1077 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1078 unsigned long instance_stage; /* the current instance stage */ 1079 unsigned long reset_stage; /* the current reset stage */ 1080 unsigned long reset_cnt; 1081 bool sw_resetting; 1082 bool hw_resetting; 1083 1084 /* Get information about reset from NIC driver or RoCE driver itself, 1085 * the meaning of the following variables from NIC driver are described 1086 * as below: 1087 * reset_cnt -- The count value of completed hardware reset. 1088 * hw_resetting -- Whether hardware device is resetting now. 1089 * sw_resetting -- Whether NIC's software reset process is running now. 1090 */ 1091 instance_stage = handle->rinfo.instance_state; 1092 reset_stage = handle->rinfo.reset_state; 1093 reset_cnt = ops->ae_dev_reset_cnt(handle); 1094 if (reset_cnt != hr_dev->reset_cnt) 1095 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1096 reset_stage); 1097 1098 hw_resetting = ops->get_cmdq_stat(handle); 1099 if (hw_resetting) 1100 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1101 reset_stage); 1102 1103 sw_resetting = ops->ae_dev_resetting(handle); 1104 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1105 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1106 1107 return CMD_RST_PRC_OTHERS; 1108 } 1109 1110 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1111 { 1112 struct hns_roce_v2_priv *priv = hr_dev->priv; 1113 struct hnae3_handle *handle = priv->handle; 1114 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1115 1116 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1117 return true; 1118 1119 if (ops->get_hw_reset_stat(handle)) 1120 return true; 1121 1122 if (ops->ae_dev_resetting(handle)) 1123 return true; 1124 1125 return false; 1126 } 1127 1128 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1129 { 1130 struct hns_roce_v2_priv *priv = hr_dev->priv; 1131 u32 status; 1132 1133 if (hr_dev->is_reset) 1134 status = CMD_RST_PRC_SUCCESS; 1135 else 1136 status = check_aedev_reset_status(hr_dev, priv->handle); 1137 1138 *busy = (status == CMD_RST_PRC_EBUSY); 1139 1140 return status == CMD_RST_PRC_OTHERS; 1141 } 1142 1143 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1144 struct hns_roce_v2_cmq_ring *ring) 1145 { 1146 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1147 1148 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1149 &ring->desc_dma_addr, GFP_KERNEL); 1150 if (!ring->desc) 1151 return -ENOMEM; 1152 1153 return 0; 1154 } 1155 1156 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1157 struct hns_roce_v2_cmq_ring *ring) 1158 { 1159 dma_free_coherent(hr_dev->dev, 1160 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1161 ring->desc, ring->desc_dma_addr); 1162 1163 ring->desc_dma_addr = 0; 1164 } 1165 1166 static int init_csq(struct hns_roce_dev *hr_dev, 1167 struct hns_roce_v2_cmq_ring *csq) 1168 { 1169 dma_addr_t dma; 1170 int ret; 1171 1172 csq->desc_num = CMD_CSQ_DESC_NUM; 1173 spin_lock_init(&csq->lock); 1174 csq->flag = TYPE_CSQ; 1175 csq->head = 0; 1176 1177 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1178 if (ret) 1179 return ret; 1180 1181 dma = csq->desc_dma_addr; 1182 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1183 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1184 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1185 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1186 1187 /* Make sure to write CI first and then PI */ 1188 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1189 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1190 1191 return 0; 1192 } 1193 1194 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1195 { 1196 struct hns_roce_v2_priv *priv = hr_dev->priv; 1197 int ret; 1198 1199 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1200 1201 ret = init_csq(hr_dev, &priv->cmq.csq); 1202 if (ret) 1203 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1204 1205 return ret; 1206 } 1207 1208 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1209 { 1210 struct hns_roce_v2_priv *priv = hr_dev->priv; 1211 1212 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1213 } 1214 1215 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1216 enum hns_roce_opcode_type opcode, 1217 bool is_read) 1218 { 1219 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1220 desc->opcode = cpu_to_le16(opcode); 1221 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1222 if (is_read) 1223 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1224 else 1225 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1226 } 1227 1228 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1229 { 1230 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1231 struct hns_roce_v2_priv *priv = hr_dev->priv; 1232 1233 return tail == priv->cmq.csq.head; 1234 } 1235 1236 static void update_cmdq_status(struct hns_roce_dev *hr_dev) 1237 { 1238 struct hns_roce_v2_priv *priv = hr_dev->priv; 1239 struct hnae3_handle *handle = priv->handle; 1240 1241 if (handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 1242 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) 1243 hr_dev->cmd.state = HNS_ROCE_CMDQ_STATE_FATAL_ERR; 1244 } 1245 1246 static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 1247 { 1248 struct hns_roce_cmd_errcode errcode_table[] = { 1249 {CMD_EXEC_SUCCESS, 0}, 1250 {CMD_NO_AUTH, -EPERM}, 1251 {CMD_NOT_EXIST, -EOPNOTSUPP}, 1252 {CMD_CRQ_FULL, -EXFULL}, 1253 {CMD_NEXT_ERR, -ENOSR}, 1254 {CMD_NOT_EXEC, -ENOTBLK}, 1255 {CMD_PARA_ERR, -EINVAL}, 1256 {CMD_RESULT_ERR, -ERANGE}, 1257 {CMD_TIMEOUT, -ETIME}, 1258 {CMD_HILINK_ERR, -ENOLINK}, 1259 {CMD_INFO_ILLEGAL, -ENXIO}, 1260 {CMD_INVALID, -EBADR}, 1261 }; 1262 u16 i; 1263 1264 for (i = 0; i < ARRAY_SIZE(errcode_table); i++) 1265 if (desc_ret == errcode_table[i].return_status) 1266 return errcode_table[i].errno; 1267 return -EIO; 1268 } 1269 1270 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1271 struct hns_roce_cmq_desc *desc, int num) 1272 { 1273 struct hns_roce_v2_priv *priv = hr_dev->priv; 1274 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1275 u32 timeout = 0; 1276 u16 desc_ret; 1277 u32 tail; 1278 int ret; 1279 int i; 1280 1281 spin_lock_bh(&csq->lock); 1282 1283 tail = csq->head; 1284 1285 for (i = 0; i < num; i++) { 1286 csq->desc[csq->head++] = desc[i]; 1287 if (csq->head == csq->desc_num) 1288 csq->head = 0; 1289 } 1290 1291 /* Write to hardware */ 1292 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1293 1294 do { 1295 if (hns_roce_cmq_csq_done(hr_dev)) 1296 break; 1297 udelay(1); 1298 } while (++timeout < priv->cmq.tx_timeout); 1299 1300 if (hns_roce_cmq_csq_done(hr_dev)) { 1301 ret = 0; 1302 for (i = 0; i < num; i++) { 1303 /* check the result of hardware write back */ 1304 desc[i] = csq->desc[tail++]; 1305 if (tail == csq->desc_num) 1306 tail = 0; 1307 1308 desc_ret = le16_to_cpu(desc[i].retval); 1309 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1310 continue; 1311 1312 dev_err_ratelimited(hr_dev->dev, 1313 "Cmdq IO error, opcode = 0x%x, return = 0x%x.\n", 1314 desc->opcode, desc_ret); 1315 ret = hns_roce_cmd_err_convert_errno(desc_ret); 1316 } 1317 } else { 1318 /* FW/HW reset or incorrect number of desc */ 1319 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1320 dev_warn(hr_dev->dev, "CMDQ move tail from %u to %u.\n", 1321 csq->head, tail); 1322 csq->head = tail; 1323 1324 update_cmdq_status(hr_dev); 1325 1326 ret = -EAGAIN; 1327 } 1328 1329 spin_unlock_bh(&csq->lock); 1330 1331 return ret; 1332 } 1333 1334 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1335 struct hns_roce_cmq_desc *desc, int num) 1336 { 1337 bool busy; 1338 int ret; 1339 1340 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1341 return -EIO; 1342 1343 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1344 return busy ? -EBUSY : 0; 1345 1346 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1347 if (ret) { 1348 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1349 return busy ? -EBUSY : 0; 1350 } 1351 1352 return ret; 1353 } 1354 1355 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, 1356 dma_addr_t base_addr, u8 cmd, unsigned long tag) 1357 { 1358 struct hns_roce_cmd_mailbox *mbox; 1359 int ret; 1360 1361 mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1362 if (IS_ERR(mbox)) 1363 return PTR_ERR(mbox); 1364 1365 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, cmd, tag); 1366 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1367 return ret; 1368 } 1369 1370 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1371 { 1372 struct hns_roce_query_version *resp; 1373 struct hns_roce_cmq_desc desc; 1374 int ret; 1375 1376 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1377 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1378 if (ret) 1379 return ret; 1380 1381 resp = (struct hns_roce_query_version *)desc.data; 1382 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1383 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1384 1385 return 0; 1386 } 1387 1388 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1389 struct hnae3_handle *handle) 1390 { 1391 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1392 unsigned long end; 1393 1394 hr_dev->dis_db = true; 1395 1396 dev_warn(hr_dev->dev, 1397 "func clear is pending, device in resetting state.\n"); 1398 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1399 while (end) { 1400 if (!ops->get_hw_reset_stat(handle)) { 1401 hr_dev->is_reset = true; 1402 dev_info(hr_dev->dev, 1403 "func clear success after reset.\n"); 1404 return; 1405 } 1406 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1407 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1408 } 1409 1410 dev_warn(hr_dev->dev, "func clear failed.\n"); 1411 } 1412 1413 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1414 struct hnae3_handle *handle) 1415 { 1416 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1417 unsigned long end; 1418 1419 hr_dev->dis_db = true; 1420 1421 dev_warn(hr_dev->dev, 1422 "func clear is pending, device in resetting state.\n"); 1423 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1424 while (end) { 1425 if (ops->ae_dev_reset_cnt(handle) != 1426 hr_dev->reset_cnt) { 1427 hr_dev->is_reset = true; 1428 dev_info(hr_dev->dev, 1429 "func clear success after sw reset\n"); 1430 return; 1431 } 1432 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1433 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1434 } 1435 1436 dev_warn(hr_dev->dev, "func clear failed because of unfinished sw reset\n"); 1437 } 1438 1439 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1440 int flag) 1441 { 1442 struct hns_roce_v2_priv *priv = hr_dev->priv; 1443 struct hnae3_handle *handle = priv->handle; 1444 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1445 1446 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1447 hr_dev->dis_db = true; 1448 hr_dev->is_reset = true; 1449 dev_info(hr_dev->dev, "func clear success after reset.\n"); 1450 return; 1451 } 1452 1453 if (ops->get_hw_reset_stat(handle)) { 1454 func_clr_hw_resetting_state(hr_dev, handle); 1455 return; 1456 } 1457 1458 if (ops->ae_dev_resetting(handle) && 1459 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1460 func_clr_sw_resetting_state(hr_dev, handle); 1461 return; 1462 } 1463 1464 if (retval && !flag) 1465 dev_warn(hr_dev->dev, 1466 "func clear read failed, ret = %d.\n", retval); 1467 1468 dev_warn(hr_dev->dev, "func clear failed.\n"); 1469 } 1470 1471 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1472 { 1473 bool fclr_write_fail_flag = false; 1474 struct hns_roce_func_clear *resp; 1475 struct hns_roce_cmq_desc desc; 1476 unsigned long end; 1477 int ret = 0; 1478 1479 if (check_device_is_in_reset(hr_dev)) 1480 goto out; 1481 1482 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1483 resp = (struct hns_roce_func_clear *)desc.data; 1484 resp->rst_funcid_en = cpu_to_le32(vf_id); 1485 1486 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1487 if (ret) { 1488 fclr_write_fail_flag = true; 1489 dev_err(hr_dev->dev, "func clear write failed, ret = %d.\n", 1490 ret); 1491 goto out; 1492 } 1493 1494 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1495 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1496 while (end) { 1497 if (check_device_is_in_reset(hr_dev)) 1498 goto out; 1499 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1500 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1501 1502 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1503 true); 1504 1505 resp->rst_funcid_en = cpu_to_le32(vf_id); 1506 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1507 if (ret) 1508 continue; 1509 1510 if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) { 1511 if (vf_id == 0) 1512 hr_dev->is_reset = true; 1513 return; 1514 } 1515 } 1516 1517 out: 1518 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1519 } 1520 1521 static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1522 { 1523 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1524 struct hns_roce_cmq_desc desc[2]; 1525 struct hns_roce_cmq_req *req_a; 1526 1527 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1528 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1529 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1530 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1531 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1532 1533 return hns_roce_cmq_send(hr_dev, desc, 2); 1534 } 1535 1536 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1537 { 1538 int ret; 1539 int i; 1540 1541 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 1542 return; 1543 1544 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1545 __hns_roce_function_clear(hr_dev, i); 1546 1547 if (i == 0) 1548 continue; 1549 1550 ret = hns_roce_free_vf_resource(hr_dev, i); 1551 if (ret) 1552 ibdev_err(&hr_dev->ib_dev, 1553 "failed to free vf resource, vf_id = %d, ret = %d.\n", 1554 i, ret); 1555 } 1556 } 1557 1558 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1559 { 1560 struct hns_roce_cmq_desc desc; 1561 int ret; 1562 1563 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1564 false); 1565 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1566 if (ret) 1567 ibdev_err(&hr_dev->ib_dev, 1568 "failed to clear extended doorbell info, ret = %d.\n", 1569 ret); 1570 1571 return ret; 1572 } 1573 1574 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1575 { 1576 struct hns_roce_query_fw_info *resp; 1577 struct hns_roce_cmq_desc desc; 1578 int ret; 1579 1580 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1581 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1582 if (ret) 1583 return ret; 1584 1585 resp = (struct hns_roce_query_fw_info *)desc.data; 1586 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1587 1588 return 0; 1589 } 1590 1591 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1592 { 1593 struct hns_roce_cmq_desc desc; 1594 int ret; 1595 1596 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 1597 hr_dev->func_num = 1; 1598 return 0; 1599 } 1600 1601 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1602 true); 1603 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1604 if (ret) { 1605 hr_dev->func_num = 1; 1606 return ret; 1607 } 1608 1609 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1610 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1611 1612 return 0; 1613 } 1614 1615 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1616 { 1617 struct hns_roce_cmq_desc desc; 1618 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1619 u32 clock_cycles_of_1us; 1620 1621 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1622 false); 1623 1624 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1625 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1626 else 1627 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1628 1629 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1630 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1631 1632 return hns_roce_cmq_send(hr_dev, &desc, 1); 1633 } 1634 1635 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1636 { 1637 struct hns_roce_cmq_desc desc[2]; 1638 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1639 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1640 struct hns_roce_caps *caps = &hr_dev->caps; 1641 enum hns_roce_opcode_type opcode; 1642 u32 func_num; 1643 int ret; 1644 1645 if (is_vf) { 1646 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1647 func_num = 1; 1648 } else { 1649 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1650 func_num = hr_dev->func_num; 1651 } 1652 1653 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1654 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1655 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1656 1657 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1658 if (ret) 1659 return ret; 1660 1661 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1662 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1663 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1664 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1665 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1666 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1667 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1668 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1669 1670 if (is_vf) { 1671 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1672 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1673 func_num; 1674 } else { 1675 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1676 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1677 func_num; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1684 { 1685 struct hns_roce_cmq_desc desc; 1686 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1687 struct hns_roce_caps *caps = &hr_dev->caps; 1688 u32 func_num, qp_num; 1689 int ret; 1690 1691 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1692 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1693 if (ret) 1694 return ret; 1695 1696 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1697 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1698 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1699 1700 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1701 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1702 1703 return 0; 1704 } 1705 1706 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1707 { 1708 struct hns_roce_cmq_desc desc; 1709 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1710 struct hns_roce_caps *caps = &hr_dev->caps; 1711 int ret; 1712 1713 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1714 true); 1715 1716 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1717 if (ret) 1718 return ret; 1719 1720 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1721 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1722 1723 return 0; 1724 } 1725 1726 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1727 { 1728 struct device *dev = hr_dev->dev; 1729 int ret; 1730 1731 ret = load_func_res_caps(hr_dev, is_vf); 1732 if (ret) { 1733 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1734 is_vf ? "vf" : "pf"); 1735 return ret; 1736 } 1737 1738 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1739 ret = load_ext_cfg_caps(hr_dev, is_vf); 1740 if (ret) 1741 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1742 ret, is_vf ? "vf" : "pf"); 1743 } 1744 1745 return ret; 1746 } 1747 1748 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1749 { 1750 struct device *dev = hr_dev->dev; 1751 int ret; 1752 1753 ret = query_func_resource_caps(hr_dev, false); 1754 if (ret) 1755 return ret; 1756 1757 ret = load_pf_timer_res_caps(hr_dev); 1758 if (ret) 1759 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1760 ret); 1761 1762 return ret; 1763 } 1764 1765 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1766 { 1767 return query_func_resource_caps(hr_dev, true); 1768 } 1769 1770 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1771 u32 vf_id) 1772 { 1773 struct hns_roce_vf_switch *swt; 1774 struct hns_roce_cmq_desc desc; 1775 int ret; 1776 1777 swt = (struct hns_roce_vf_switch *)desc.data; 1778 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1779 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1780 hr_reg_write(swt, VF_SWITCH_VF_ID, vf_id); 1781 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1782 if (ret) 1783 return ret; 1784 1785 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1786 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1787 hr_reg_enable(swt, VF_SWITCH_ALW_LPBK); 1788 hr_reg_clear(swt, VF_SWITCH_ALW_LCL_LPBK); 1789 hr_reg_enable(swt, VF_SWITCH_ALW_DST_OVRD); 1790 1791 return hns_roce_cmq_send(hr_dev, &desc, 1); 1792 } 1793 1794 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1795 { 1796 u32 vf_id; 1797 int ret; 1798 1799 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1800 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1801 if (ret) 1802 return ret; 1803 } 1804 return 0; 1805 } 1806 1807 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1808 { 1809 struct hns_roce_cmq_desc desc[2]; 1810 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1811 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1812 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1813 struct hns_roce_caps *caps = &hr_dev->caps; 1814 1815 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1816 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1817 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1818 1819 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1820 1821 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1822 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1823 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1824 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1825 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1826 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1827 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1828 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1829 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1830 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1831 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1832 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1833 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1834 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1835 1836 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1837 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1838 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1839 vf_id * caps->gmv_bt_num); 1840 } else { 1841 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1842 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1843 vf_id * caps->sgid_bt_num); 1844 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1845 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1846 vf_id * caps->smac_bt_num); 1847 } 1848 1849 return hns_roce_cmq_send(hr_dev, desc, 2); 1850 } 1851 1852 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1853 { 1854 struct hns_roce_cmq_desc desc; 1855 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1856 struct hns_roce_caps *caps = &hr_dev->caps; 1857 1858 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1859 1860 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1861 1862 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1863 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1864 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1865 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1866 1867 return hns_roce_cmq_send(hr_dev, &desc, 1); 1868 } 1869 1870 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1871 { 1872 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1873 u32 vf_id; 1874 int ret; 1875 1876 for (vf_id = 0; vf_id < func_num; vf_id++) { 1877 ret = config_vf_hem_resource(hr_dev, vf_id); 1878 if (ret) { 1879 dev_err(hr_dev->dev, 1880 "failed to config vf-%u hem res, ret = %d.\n", 1881 vf_id, ret); 1882 return ret; 1883 } 1884 1885 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1886 ret = config_vf_ext_resource(hr_dev, vf_id); 1887 if (ret) { 1888 dev_err(hr_dev->dev, 1889 "failed to config vf-%u ext res, ret = %d.\n", 1890 vf_id, ret); 1891 return ret; 1892 } 1893 } 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1900 { 1901 struct hns_roce_cmq_desc desc; 1902 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1903 struct hns_roce_caps *caps = &hr_dev->caps; 1904 1905 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1906 1907 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1908 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1909 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1910 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1911 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1912 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1913 1914 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1915 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1916 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1917 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1918 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1919 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1920 1921 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1922 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1923 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1924 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1925 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1926 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1927 1928 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1929 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1930 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1931 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1932 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1933 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1934 1935 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1936 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1937 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1938 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1939 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1940 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1941 1942 return hns_roce_cmq_send(hr_dev, &desc, 1); 1943 } 1944 1945 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 1946 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 1947 { 1948 u64 obj_per_chunk; 1949 u64 bt_chunk_size = PAGE_SIZE; 1950 u64 buf_chunk_size = PAGE_SIZE; 1951 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 1952 1953 *buf_page_size = 0; 1954 *bt_page_size = 0; 1955 1956 switch (hop_num) { 1957 case 3: 1958 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1959 (bt_chunk_size / BA_BYTE_LEN) * 1960 (bt_chunk_size / BA_BYTE_LEN) * 1961 obj_per_chunk_default; 1962 break; 1963 case 2: 1964 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1965 (bt_chunk_size / BA_BYTE_LEN) * 1966 obj_per_chunk_default; 1967 break; 1968 case 1: 1969 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1970 obj_per_chunk_default; 1971 break; 1972 case HNS_ROCE_HOP_NUM_0: 1973 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1974 break; 1975 default: 1976 pr_err("table %u not support hop_num = %u!\n", hem_type, 1977 hop_num); 1978 return; 1979 } 1980 1981 if (hem_type >= HEM_TYPE_MTT) 1982 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1983 else 1984 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1985 } 1986 1987 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 1988 { 1989 struct hns_roce_caps *caps = &hr_dev->caps; 1990 1991 /* EQ */ 1992 caps->eqe_ba_pg_sz = 0; 1993 caps->eqe_buf_pg_sz = 0; 1994 1995 /* Link Table */ 1996 caps->llm_buf_pg_sz = 0; 1997 1998 /* MR */ 1999 caps->mpt_ba_pg_sz = 0; 2000 caps->mpt_buf_pg_sz = 0; 2001 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2002 caps->pbl_buf_pg_sz = 0; 2003 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2004 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2005 HEM_TYPE_MTPT); 2006 2007 /* QP */ 2008 caps->qpc_ba_pg_sz = 0; 2009 caps->qpc_buf_pg_sz = 0; 2010 caps->qpc_timer_ba_pg_sz = 0; 2011 caps->qpc_timer_buf_pg_sz = 0; 2012 caps->sccc_ba_pg_sz = 0; 2013 caps->sccc_buf_pg_sz = 0; 2014 caps->mtt_ba_pg_sz = 0; 2015 caps->mtt_buf_pg_sz = 0; 2016 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2017 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2018 HEM_TYPE_QPC); 2019 2020 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2021 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2022 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2023 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2024 2025 /* CQ */ 2026 caps->cqc_ba_pg_sz = 0; 2027 caps->cqc_buf_pg_sz = 0; 2028 caps->cqc_timer_ba_pg_sz = 0; 2029 caps->cqc_timer_buf_pg_sz = 0; 2030 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2031 caps->cqe_buf_pg_sz = 0; 2032 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2033 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2034 HEM_TYPE_CQC); 2035 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2036 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2037 2038 /* SRQ */ 2039 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2040 caps->srqc_ba_pg_sz = 0; 2041 caps->srqc_buf_pg_sz = 0; 2042 caps->srqwqe_ba_pg_sz = 0; 2043 caps->srqwqe_buf_pg_sz = 0; 2044 caps->idx_ba_pg_sz = 0; 2045 caps->idx_buf_pg_sz = 0; 2046 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2047 caps->srqc_hop_num, caps->srqc_bt_num, 2048 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2049 HEM_TYPE_SRQC); 2050 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2051 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2052 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2053 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2054 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2055 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2056 } 2057 2058 /* GMV */ 2059 caps->gmv_ba_pg_sz = 0; 2060 caps->gmv_buf_pg_sz = 0; 2061 } 2062 2063 /* Apply all loaded caps before setting to hardware */ 2064 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2065 { 2066 struct hns_roce_caps *caps = &hr_dev->caps; 2067 struct hns_roce_v2_priv *priv = hr_dev->priv; 2068 2069 /* The following configurations don't need to be got from firmware. */ 2070 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2071 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2072 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2073 2074 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2075 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2076 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2077 2078 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2079 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2080 2081 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2082 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2083 2084 if (!caps->num_comp_vectors) 2085 caps->num_comp_vectors = 2086 min_t(u32, caps->eqc_bt_num - HNS_ROCE_V2_AEQE_VEC_NUM, 2087 (u32)priv->handle->rinfo.num_vectors - 2088 (HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM)); 2089 2090 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2091 caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM; 2092 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2093 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2094 2095 /* The following configurations will be overwritten */ 2096 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2097 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2098 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2099 2100 /* The following configurations are not got from firmware */ 2101 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2102 2103 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2104 caps->gid_table_len[0] = caps->gmv_bt_num * 2105 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2106 2107 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2108 caps->gmv_entry_sz); 2109 } else { 2110 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2111 2112 caps->eqe_hop_num = HNS_ROCE_V2_EQE_HOP_NUM; 2113 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2114 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2115 caps->gid_table_len[0] /= func_num; 2116 } 2117 2118 if (hr_dev->is_vf) { 2119 caps->default_aeq_arm_st = 0x3; 2120 caps->default_ceq_arm_st = 0x3; 2121 caps->default_ceq_max_cnt = 0x1; 2122 caps->default_ceq_period = 0x10; 2123 caps->default_aeq_max_cnt = 0x1; 2124 caps->default_aeq_period = 0x10; 2125 } 2126 2127 set_hem_page_size(hr_dev); 2128 } 2129 2130 static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) 2131 { 2132 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2133 struct hns_roce_caps *caps = &hr_dev->caps; 2134 struct hns_roce_query_pf_caps_a *resp_a; 2135 struct hns_roce_query_pf_caps_b *resp_b; 2136 struct hns_roce_query_pf_caps_c *resp_c; 2137 struct hns_roce_query_pf_caps_d *resp_d; 2138 struct hns_roce_query_pf_caps_e *resp_e; 2139 enum hns_roce_opcode_type cmd; 2140 int ctx_hop_num; 2141 int pbl_hop_num; 2142 int ret; 2143 int i; 2144 2145 cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM : 2146 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM; 2147 2148 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2149 hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true); 2150 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2151 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2152 else 2153 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2154 } 2155 2156 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2157 if (ret) 2158 return ret; 2159 2160 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2161 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2162 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2163 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2164 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2165 2166 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2167 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2168 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2169 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2170 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2171 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2172 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2173 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2174 caps->num_other_vectors = resp_a->num_other_vectors; 2175 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2176 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2177 2178 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2179 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2180 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2181 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2182 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2183 caps->idx_entry_sz = resp_b->idx_entry_sz; 2184 caps->sccc_sz = resp_b->sccc_sz; 2185 caps->max_mtu = resp_b->max_mtu; 2186 caps->min_cqes = resp_b->min_cqes; 2187 caps->min_wqes = resp_b->min_wqes; 2188 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2189 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2190 caps->phy_num_uars = resp_b->phy_num_uars; 2191 ctx_hop_num = resp_b->ctx_hop_num; 2192 pbl_hop_num = resp_b->pbl_hop_num; 2193 2194 caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS); 2195 2196 caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS); 2197 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2198 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2199 2200 caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS); 2201 caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID); 2202 caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH); 2203 caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS); 2204 caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS); 2205 caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD); 2206 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2207 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2208 2209 caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS); 2210 caps->cong_type = hr_reg_read(resp_d, PF_CAPS_D_CONG_TYPE); 2211 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2212 caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH); 2213 caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS); 2214 caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH); 2215 caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS); 2216 caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS); 2217 caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS); 2218 caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS); 2219 2220 caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS); 2221 caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT); 2222 caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS); 2223 caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS); 2224 caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS); 2225 2226 caps->qpc_hop_num = ctx_hop_num; 2227 caps->sccc_hop_num = ctx_hop_num; 2228 caps->srqc_hop_num = ctx_hop_num; 2229 caps->cqc_hop_num = ctx_hop_num; 2230 caps->mpt_hop_num = ctx_hop_num; 2231 caps->mtt_hop_num = pbl_hop_num; 2232 caps->cqe_hop_num = pbl_hop_num; 2233 caps->srqwqe_hop_num = pbl_hop_num; 2234 caps->idx_hop_num = pbl_hop_num; 2235 caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM); 2236 caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM); 2237 caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM); 2238 2239 if (!(caps->page_size_cap & PAGE_SIZE)) 2240 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 2241 2242 if (!hr_dev->is_vf) { 2243 caps->cqe_sz = resp_a->cqe_sz; 2244 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2245 caps->default_aeq_arm_st = 2246 hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST); 2247 caps->default_ceq_arm_st = 2248 hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST); 2249 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2250 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2251 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2252 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2259 { 2260 struct hns_roce_cmq_desc desc; 2261 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2262 2263 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2264 false); 2265 2266 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2267 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2268 2269 return hns_roce_cmq_send(hr_dev, &desc, 1); 2270 } 2271 2272 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2273 { 2274 struct hns_roce_caps *caps = &hr_dev->caps; 2275 int ret; 2276 2277 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 2278 return 0; 2279 2280 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2281 caps->qpc_sz); 2282 if (ret) { 2283 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2284 return ret; 2285 } 2286 2287 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2288 caps->sccc_sz); 2289 if (ret) 2290 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2291 2292 return ret; 2293 } 2294 2295 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2296 { 2297 struct device *dev = hr_dev->dev; 2298 int ret; 2299 2300 hr_dev->func_num = 1; 2301 2302 ret = hns_roce_query_caps(hr_dev); 2303 if (ret) { 2304 dev_err(dev, "failed to query VF caps, ret = %d.\n", ret); 2305 return ret; 2306 } 2307 2308 ret = hns_roce_query_vf_resource(hr_dev); 2309 if (ret) { 2310 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2311 return ret; 2312 } 2313 2314 apply_func_caps(hr_dev); 2315 2316 ret = hns_roce_v2_set_bt(hr_dev); 2317 if (ret) 2318 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2319 2320 return ret; 2321 } 2322 2323 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2324 { 2325 struct device *dev = hr_dev->dev; 2326 int ret; 2327 2328 ret = hns_roce_query_func_info(hr_dev); 2329 if (ret) { 2330 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2331 return ret; 2332 } 2333 2334 ret = hns_roce_config_global_param(hr_dev); 2335 if (ret) { 2336 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2337 return ret; 2338 } 2339 2340 ret = hns_roce_set_vf_switch_param(hr_dev); 2341 if (ret) { 2342 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2343 return ret; 2344 } 2345 2346 ret = hns_roce_query_caps(hr_dev); 2347 if (ret) { 2348 dev_err(dev, "failed to query PF caps, ret = %d.\n", ret); 2349 return ret; 2350 } 2351 2352 ret = hns_roce_query_pf_resource(hr_dev); 2353 if (ret) { 2354 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2355 return ret; 2356 } 2357 2358 apply_func_caps(hr_dev); 2359 2360 ret = hns_roce_alloc_vf_resource(hr_dev); 2361 if (ret) { 2362 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2363 return ret; 2364 } 2365 2366 ret = hns_roce_v2_set_bt(hr_dev); 2367 if (ret) { 2368 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2369 return ret; 2370 } 2371 2372 /* Configure the size of QPC, SCCC, etc. */ 2373 return hns_roce_config_entry_size(hr_dev); 2374 } 2375 2376 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2377 { 2378 struct device *dev = hr_dev->dev; 2379 int ret; 2380 2381 ret = hns_roce_cmq_query_hw_info(hr_dev); 2382 if (ret) { 2383 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2384 return ret; 2385 } 2386 2387 ret = hns_roce_query_fw_ver(hr_dev); 2388 if (ret) { 2389 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2390 return ret; 2391 } 2392 2393 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2394 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2395 2396 if (hr_dev->is_vf) 2397 return hns_roce_v2_vf_profile(hr_dev); 2398 else 2399 return hns_roce_v2_pf_profile(hr_dev); 2400 } 2401 2402 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2403 { 2404 u32 i, next_ptr, page_num; 2405 __le64 *entry = cfg_buf; 2406 dma_addr_t addr; 2407 u64 val; 2408 2409 page_num = data_buf->npages; 2410 for (i = 0; i < page_num; i++) { 2411 addr = hns_roce_buf_page(data_buf, i); 2412 if (i == (page_num - 1)) 2413 next_ptr = 0; 2414 else 2415 next_ptr = i + 1; 2416 2417 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2418 entry[i] = cpu_to_le64(val); 2419 } 2420 } 2421 2422 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2423 struct hns_roce_link_table *table) 2424 { 2425 struct hns_roce_cmq_desc desc[2]; 2426 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2427 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2428 struct hns_roce_buf *buf = table->buf; 2429 enum hns_roce_opcode_type opcode; 2430 dma_addr_t addr; 2431 2432 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2433 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2434 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2435 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2436 2437 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2438 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2439 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2440 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2441 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2442 2443 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2444 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2445 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2446 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2447 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2448 2449 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2450 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2451 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2452 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2453 2454 return hns_roce_cmq_send(hr_dev, desc, 2); 2455 } 2456 2457 static struct hns_roce_link_table * 2458 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2459 { 2460 struct hns_roce_v2_priv *priv = hr_dev->priv; 2461 struct hns_roce_link_table *link_tbl; 2462 u32 pg_shift, size, min_size; 2463 2464 link_tbl = &priv->ext_llm; 2465 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2466 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2467 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2468 2469 /* Alloc data table */ 2470 size = max(size, min_size); 2471 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2472 if (IS_ERR(link_tbl->buf)) 2473 return ERR_PTR(-ENOMEM); 2474 2475 /* Alloc config table */ 2476 size = link_tbl->buf->npages * sizeof(u64); 2477 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2478 &link_tbl->table.map, 2479 GFP_KERNEL); 2480 if (!link_tbl->table.buf) { 2481 hns_roce_buf_free(hr_dev, link_tbl->buf); 2482 return ERR_PTR(-ENOMEM); 2483 } 2484 2485 return link_tbl; 2486 } 2487 2488 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2489 struct hns_roce_link_table *tbl) 2490 { 2491 if (tbl->buf) { 2492 u32 size = tbl->buf->npages * sizeof(u64); 2493 2494 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2495 tbl->table.map); 2496 } 2497 2498 hns_roce_buf_free(hr_dev, tbl->buf); 2499 } 2500 2501 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2502 { 2503 struct hns_roce_link_table *link_tbl; 2504 int ret; 2505 2506 link_tbl = alloc_link_table_buf(hr_dev); 2507 if (IS_ERR(link_tbl)) 2508 return -ENOMEM; 2509 2510 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2511 ret = -EINVAL; 2512 goto err_alloc; 2513 } 2514 2515 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2516 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2517 if (ret) 2518 goto err_alloc; 2519 2520 return 0; 2521 2522 err_alloc: 2523 free_link_table_buf(hr_dev, link_tbl); 2524 return ret; 2525 } 2526 2527 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2528 { 2529 struct hns_roce_v2_priv *priv = hr_dev->priv; 2530 2531 free_link_table_buf(hr_dev, &priv->ext_llm); 2532 } 2533 2534 static void free_dip_list(struct hns_roce_dev *hr_dev) 2535 { 2536 struct hns_roce_dip *hr_dip; 2537 struct hns_roce_dip *tmp; 2538 unsigned long flags; 2539 2540 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2541 2542 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2543 list_del(&hr_dip->node); 2544 kfree(hr_dip); 2545 } 2546 2547 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2548 } 2549 2550 static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) 2551 { 2552 struct hns_roce_v2_priv *priv = hr_dev->priv; 2553 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2554 struct ib_device *ibdev = &hr_dev->ib_dev; 2555 struct hns_roce_pd *hr_pd; 2556 struct ib_pd *pd; 2557 2558 hr_pd = kzalloc(sizeof(*hr_pd), GFP_KERNEL); 2559 if (ZERO_OR_NULL_PTR(hr_pd)) 2560 return NULL; 2561 pd = &hr_pd->ibpd; 2562 pd->device = ibdev; 2563 2564 if (hns_roce_alloc_pd(pd, NULL)) { 2565 ibdev_err(ibdev, "failed to create pd for free mr.\n"); 2566 kfree(hr_pd); 2567 return NULL; 2568 } 2569 free_mr->rsv_pd = to_hr_pd(pd); 2570 free_mr->rsv_pd->ibpd.device = &hr_dev->ib_dev; 2571 free_mr->rsv_pd->ibpd.uobject = NULL; 2572 free_mr->rsv_pd->ibpd.__internal_mr = NULL; 2573 atomic_set(&free_mr->rsv_pd->ibpd.usecnt, 0); 2574 2575 return pd; 2576 } 2577 2578 static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) 2579 { 2580 struct hns_roce_v2_priv *priv = hr_dev->priv; 2581 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2582 struct ib_device *ibdev = &hr_dev->ib_dev; 2583 struct ib_cq_init_attr cq_init_attr = {}; 2584 struct hns_roce_cq *hr_cq; 2585 struct ib_cq *cq; 2586 2587 cq_init_attr.cqe = HNS_ROCE_FREE_MR_USED_CQE_NUM; 2588 2589 hr_cq = kzalloc(sizeof(*hr_cq), GFP_KERNEL); 2590 if (ZERO_OR_NULL_PTR(hr_cq)) 2591 return NULL; 2592 2593 cq = &hr_cq->ib_cq; 2594 cq->device = ibdev; 2595 2596 if (hns_roce_create_cq(cq, &cq_init_attr, NULL)) { 2597 ibdev_err(ibdev, "failed to create cq for free mr.\n"); 2598 kfree(hr_cq); 2599 return NULL; 2600 } 2601 free_mr->rsv_cq = to_hr_cq(cq); 2602 free_mr->rsv_cq->ib_cq.device = &hr_dev->ib_dev; 2603 free_mr->rsv_cq->ib_cq.uobject = NULL; 2604 free_mr->rsv_cq->ib_cq.comp_handler = NULL; 2605 free_mr->rsv_cq->ib_cq.event_handler = NULL; 2606 free_mr->rsv_cq->ib_cq.cq_context = NULL; 2607 atomic_set(&free_mr->rsv_cq->ib_cq.usecnt, 0); 2608 2609 return cq; 2610 } 2611 2612 static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, 2613 struct ib_qp_init_attr *init_attr, int i) 2614 { 2615 struct hns_roce_v2_priv *priv = hr_dev->priv; 2616 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2617 struct ib_device *ibdev = &hr_dev->ib_dev; 2618 struct hns_roce_qp *hr_qp; 2619 struct ib_qp *qp; 2620 int ret; 2621 2622 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL); 2623 if (ZERO_OR_NULL_PTR(hr_qp)) 2624 return -ENOMEM; 2625 2626 qp = &hr_qp->ibqp; 2627 qp->device = ibdev; 2628 2629 ret = hns_roce_create_qp(qp, init_attr, NULL); 2630 if (ret) { 2631 ibdev_err(ibdev, "failed to create qp for free mr.\n"); 2632 kfree(hr_qp); 2633 return ret; 2634 } 2635 2636 free_mr->rsv_qp[i] = hr_qp; 2637 free_mr->rsv_qp[i]->ibqp.recv_cq = cq; 2638 free_mr->rsv_qp[i]->ibqp.send_cq = cq; 2639 2640 return 0; 2641 } 2642 2643 static void free_mr_exit(struct hns_roce_dev *hr_dev) 2644 { 2645 struct hns_roce_v2_priv *priv = hr_dev->priv; 2646 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2647 struct ib_qp *qp; 2648 int i; 2649 2650 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2651 if (free_mr->rsv_qp[i]) { 2652 qp = &free_mr->rsv_qp[i]->ibqp; 2653 hns_roce_v2_destroy_qp(qp, NULL); 2654 kfree(free_mr->rsv_qp[i]); 2655 free_mr->rsv_qp[i] = NULL; 2656 } 2657 } 2658 2659 if (free_mr->rsv_cq) { 2660 hns_roce_destroy_cq(&free_mr->rsv_cq->ib_cq, NULL); 2661 kfree(free_mr->rsv_cq); 2662 free_mr->rsv_cq = NULL; 2663 } 2664 2665 if (free_mr->rsv_pd) { 2666 hns_roce_dealloc_pd(&free_mr->rsv_pd->ibpd, NULL); 2667 kfree(free_mr->rsv_pd); 2668 free_mr->rsv_pd = NULL; 2669 } 2670 } 2671 2672 static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) 2673 { 2674 struct hns_roce_v2_priv *priv = hr_dev->priv; 2675 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2676 struct ib_qp_init_attr qp_init_attr = {}; 2677 struct ib_pd *pd; 2678 struct ib_cq *cq; 2679 int ret; 2680 int i; 2681 2682 pd = free_mr_init_pd(hr_dev); 2683 if (!pd) 2684 return -ENOMEM; 2685 2686 cq = free_mr_init_cq(hr_dev); 2687 if (!cq) { 2688 ret = -ENOMEM; 2689 goto create_failed_cq; 2690 } 2691 2692 qp_init_attr.qp_type = IB_QPT_RC; 2693 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 2694 qp_init_attr.send_cq = cq; 2695 qp_init_attr.recv_cq = cq; 2696 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2697 qp_init_attr.cap.max_send_wr = HNS_ROCE_FREE_MR_USED_SQWQE_NUM; 2698 qp_init_attr.cap.max_send_sge = HNS_ROCE_FREE_MR_USED_SQSGE_NUM; 2699 qp_init_attr.cap.max_recv_wr = HNS_ROCE_FREE_MR_USED_RQWQE_NUM; 2700 qp_init_attr.cap.max_recv_sge = HNS_ROCE_FREE_MR_USED_RQSGE_NUM; 2701 2702 ret = free_mr_init_qp(hr_dev, cq, &qp_init_attr, i); 2703 if (ret) 2704 goto create_failed_qp; 2705 } 2706 2707 return 0; 2708 2709 create_failed_qp: 2710 hns_roce_destroy_cq(cq, NULL); 2711 kfree(cq); 2712 2713 create_failed_cq: 2714 hns_roce_dealloc_pd(pd, NULL); 2715 kfree(pd); 2716 2717 return ret; 2718 } 2719 2720 static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, 2721 struct ib_qp_attr *attr, int sl_num) 2722 { 2723 struct hns_roce_v2_priv *priv = hr_dev->priv; 2724 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2725 struct ib_device *ibdev = &hr_dev->ib_dev; 2726 struct hns_roce_qp *hr_qp; 2727 int loopback; 2728 int mask; 2729 int ret; 2730 2731 hr_qp = to_hr_qp(&free_mr->rsv_qp[sl_num]->ibqp); 2732 hr_qp->free_mr_en = 1; 2733 hr_qp->ibqp.device = ibdev; 2734 hr_qp->ibqp.qp_type = IB_QPT_RC; 2735 2736 mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS; 2737 attr->qp_state = IB_QPS_INIT; 2738 attr->port_num = 1; 2739 attr->qp_access_flags = IB_ACCESS_REMOTE_WRITE; 2740 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2741 IB_QPS_INIT, NULL); 2742 if (ret) { 2743 ibdev_err(ibdev, "failed to modify qp to init, ret = %d.\n", 2744 ret); 2745 return ret; 2746 } 2747 2748 loopback = hr_dev->loop_idc; 2749 /* Set qpc lbi = 1 incidate loopback IO */ 2750 hr_dev->loop_idc = 1; 2751 2752 mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU | IB_QP_DEST_QPN | 2753 IB_QP_RQ_PSN | IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER; 2754 attr->qp_state = IB_QPS_RTR; 2755 attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 2756 attr->path_mtu = IB_MTU_256; 2757 attr->dest_qp_num = hr_qp->qpn; 2758 attr->rq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2759 2760 rdma_ah_set_sl(&attr->ah_attr, (u8)sl_num); 2761 2762 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_INIT, 2763 IB_QPS_RTR, NULL); 2764 hr_dev->loop_idc = loopback; 2765 if (ret) { 2766 ibdev_err(ibdev, "failed to modify qp to rtr, ret = %d.\n", 2767 ret); 2768 return ret; 2769 } 2770 2771 mask = IB_QP_STATE | IB_QP_SQ_PSN | IB_QP_RETRY_CNT | IB_QP_TIMEOUT | 2772 IB_QP_RNR_RETRY | IB_QP_MAX_QP_RD_ATOMIC; 2773 attr->qp_state = IB_QPS_RTS; 2774 attr->sq_psn = HNS_ROCE_FREE_MR_USED_PSN; 2775 attr->retry_cnt = HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT; 2776 attr->timeout = HNS_ROCE_FREE_MR_USED_QP_TIMEOUT; 2777 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, attr, mask, IB_QPS_RTR, 2778 IB_QPS_RTS, NULL); 2779 if (ret) 2780 ibdev_err(ibdev, "failed to modify qp to rts, ret = %d.\n", 2781 ret); 2782 2783 return ret; 2784 } 2785 2786 static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) 2787 { 2788 struct hns_roce_v2_priv *priv = hr_dev->priv; 2789 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2790 struct ib_qp_attr attr = {}; 2791 int ret; 2792 int i; 2793 2794 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0); 2795 rdma_ah_set_static_rate(&attr.ah_attr, 3); 2796 rdma_ah_set_port_num(&attr.ah_attr, 1); 2797 2798 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 2799 ret = free_mr_modify_rsv_qp(hr_dev, &attr, i); 2800 if (ret) 2801 return ret; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int free_mr_init(struct hns_roce_dev *hr_dev) 2808 { 2809 struct hns_roce_v2_priv *priv = hr_dev->priv; 2810 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 2811 int ret; 2812 2813 mutex_init(&free_mr->mutex); 2814 2815 ret = free_mr_alloc_res(hr_dev); 2816 if (ret) 2817 return ret; 2818 2819 ret = free_mr_modify_qp(hr_dev); 2820 if (ret) 2821 goto err_modify_qp; 2822 2823 return 0; 2824 2825 err_modify_qp: 2826 free_mr_exit(hr_dev); 2827 2828 return ret; 2829 } 2830 2831 static int get_hem_table(struct hns_roce_dev *hr_dev) 2832 { 2833 unsigned int qpc_count; 2834 unsigned int cqc_count; 2835 unsigned int gmv_count; 2836 int ret; 2837 int i; 2838 2839 /* Alloc memory for source address table buffer space chunk */ 2840 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2841 gmv_count++) { 2842 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2843 if (ret) 2844 goto err_gmv_failed; 2845 } 2846 2847 if (hr_dev->is_vf) 2848 return 0; 2849 2850 /* Alloc memory for QPC Timer buffer space chunk */ 2851 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2852 qpc_count++) { 2853 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2854 qpc_count); 2855 if (ret) { 2856 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2857 goto err_qpc_timer_failed; 2858 } 2859 } 2860 2861 /* Alloc memory for CQC Timer buffer space chunk */ 2862 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2863 cqc_count++) { 2864 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2865 cqc_count); 2866 if (ret) { 2867 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2868 goto err_cqc_timer_failed; 2869 } 2870 } 2871 2872 return 0; 2873 2874 err_cqc_timer_failed: 2875 for (i = 0; i < cqc_count; i++) 2876 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2877 2878 err_qpc_timer_failed: 2879 for (i = 0; i < qpc_count; i++) 2880 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2881 2882 err_gmv_failed: 2883 for (i = 0; i < gmv_count; i++) 2884 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2885 2886 return ret; 2887 } 2888 2889 static void put_hem_table(struct hns_roce_dev *hr_dev) 2890 { 2891 int i; 2892 2893 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2894 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2895 2896 if (hr_dev->is_vf) 2897 return; 2898 2899 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2900 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2901 2902 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2903 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2904 } 2905 2906 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2907 { 2908 int ret; 2909 2910 /* The hns ROCEE requires the extdb info to be cleared before using */ 2911 ret = hns_roce_clear_extdb_list_info(hr_dev); 2912 if (ret) 2913 return ret; 2914 2915 ret = get_hem_table(hr_dev); 2916 if (ret) 2917 return ret; 2918 2919 if (hr_dev->is_vf) 2920 return 0; 2921 2922 ret = hns_roce_init_link_table(hr_dev); 2923 if (ret) { 2924 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2925 goto err_llm_init_failed; 2926 } 2927 2928 return 0; 2929 2930 err_llm_init_failed: 2931 put_hem_table(hr_dev); 2932 2933 return ret; 2934 } 2935 2936 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2937 { 2938 hns_roce_function_clear(hr_dev); 2939 2940 if (!hr_dev->is_vf) 2941 hns_roce_free_link_table(hr_dev); 2942 2943 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2944 free_dip_list(hr_dev); 2945 } 2946 2947 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, 2948 struct hns_roce_mbox_msg *mbox_msg) 2949 { 2950 struct hns_roce_cmq_desc desc; 2951 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2952 2953 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2954 2955 mb->in_param_l = cpu_to_le32(mbox_msg->in_param); 2956 mb->in_param_h = cpu_to_le32(mbox_msg->in_param >> 32); 2957 mb->out_param_l = cpu_to_le32(mbox_msg->out_param); 2958 mb->out_param_h = cpu_to_le32(mbox_msg->out_param >> 32); 2959 mb->cmd_tag = cpu_to_le32(mbox_msg->tag << 8 | mbox_msg->cmd); 2960 mb->token_event_en = cpu_to_le32(mbox_msg->event_en << 16 | 2961 mbox_msg->token); 2962 2963 return hns_roce_cmq_send(hr_dev, &desc, 1); 2964 } 2965 2966 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2967 u8 *complete_status) 2968 { 2969 struct hns_roce_mbox_status *mb_st; 2970 struct hns_roce_cmq_desc desc; 2971 unsigned long end; 2972 int ret = -EBUSY; 2973 u32 status; 2974 bool busy; 2975 2976 mb_st = (struct hns_roce_mbox_status *)desc.data; 2977 end = msecs_to_jiffies(timeout) + jiffies; 2978 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2979 if (hr_dev->cmd.state == HNS_ROCE_CMDQ_STATE_FATAL_ERR) 2980 return -EIO; 2981 2982 status = 0; 2983 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2984 true); 2985 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2986 if (!ret) { 2987 status = le32_to_cpu(mb_st->mb_status_hw_run); 2988 /* No pending message exists in ROCEE mbox. */ 2989 if (!(status & MB_ST_HW_RUN_M)) 2990 break; 2991 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2992 break; 2993 } 2994 2995 if (time_after(jiffies, end)) { 2996 dev_err_ratelimited(hr_dev->dev, 2997 "failed to wait mbox status 0x%x\n", 2998 status); 2999 return -ETIMEDOUT; 3000 } 3001 3002 cond_resched(); 3003 ret = -EBUSY; 3004 } 3005 3006 if (!ret) { 3007 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 3008 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 3009 /* Ignore all errors if the mbox is unavailable. */ 3010 ret = 0; 3011 *complete_status = MB_ST_COMPLETE_M; 3012 } 3013 3014 return ret; 3015 } 3016 3017 static int v2_post_mbox(struct hns_roce_dev *hr_dev, 3018 struct hns_roce_mbox_msg *mbox_msg) 3019 { 3020 u8 status = 0; 3021 int ret; 3022 3023 /* Waiting for the mbox to be idle */ 3024 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 3025 &status); 3026 if (unlikely(ret)) { 3027 dev_err_ratelimited(hr_dev->dev, 3028 "failed to check post mbox status = 0x%x, ret = %d.\n", 3029 status, ret); 3030 return ret; 3031 } 3032 3033 /* Post new message to mbox */ 3034 ret = hns_roce_mbox_post(hr_dev, mbox_msg); 3035 if (ret) 3036 dev_err_ratelimited(hr_dev->dev, 3037 "failed to post mailbox, ret = %d.\n", ret); 3038 3039 return ret; 3040 } 3041 3042 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) 3043 { 3044 u8 status = 0; 3045 int ret; 3046 3047 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_CMD_TIMEOUT_MSECS, 3048 &status); 3049 if (!ret) { 3050 if (status != MB_ST_COMPLETE_SUCC) 3051 return -EBUSY; 3052 } else { 3053 dev_err_ratelimited(hr_dev->dev, 3054 "failed to check mbox status = 0x%x, ret = %d.\n", 3055 status, ret); 3056 } 3057 3058 return ret; 3059 } 3060 3061 static void copy_gid(void *dest, const union ib_gid *gid) 3062 { 3063 #define GID_SIZE 4 3064 const union ib_gid *src = gid; 3065 __le32 (*p)[GID_SIZE] = dest; 3066 int i; 3067 3068 if (!gid) 3069 src = &zgid; 3070 3071 for (i = 0; i < GID_SIZE; i++) 3072 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 3073 } 3074 3075 static int config_sgid_table(struct hns_roce_dev *hr_dev, 3076 int gid_index, const union ib_gid *gid, 3077 enum hns_roce_sgid_type sgid_type) 3078 { 3079 struct hns_roce_cmq_desc desc; 3080 struct hns_roce_cfg_sgid_tb *sgid_tb = 3081 (struct hns_roce_cfg_sgid_tb *)desc.data; 3082 3083 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 3084 3085 hr_reg_write(sgid_tb, CFG_SGID_TB_TABLE_IDX, gid_index); 3086 hr_reg_write(sgid_tb, CFG_SGID_TB_VF_SGID_TYPE, sgid_type); 3087 3088 copy_gid(&sgid_tb->vf_sgid_l, gid); 3089 3090 return hns_roce_cmq_send(hr_dev, &desc, 1); 3091 } 3092 3093 static int config_gmv_table(struct hns_roce_dev *hr_dev, 3094 int gid_index, const union ib_gid *gid, 3095 enum hns_roce_sgid_type sgid_type, 3096 const struct ib_gid_attr *attr) 3097 { 3098 struct hns_roce_cmq_desc desc[2]; 3099 struct hns_roce_cfg_gmv_tb_a *tb_a = 3100 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 3101 struct hns_roce_cfg_gmv_tb_b *tb_b = 3102 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 3103 3104 u16 vlan_id = VLAN_CFI_MASK; 3105 u8 mac[ETH_ALEN] = {}; 3106 int ret; 3107 3108 if (gid) { 3109 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 3110 if (ret) 3111 return ret; 3112 } 3113 3114 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3115 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 3116 3117 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 3118 3119 copy_gid(&tb_a->vf_sgid_l, gid); 3120 3121 hr_reg_write(tb_a, GMV_TB_A_VF_SGID_TYPE, sgid_type); 3122 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_EN, vlan_id < VLAN_CFI_MASK); 3123 hr_reg_write(tb_a, GMV_TB_A_VF_VLAN_ID, vlan_id); 3124 3125 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 3126 3127 hr_reg_write(tb_b, GMV_TB_B_SMAC_H, *(u16 *)&mac[4]); 3128 hr_reg_write(tb_b, GMV_TB_B_SGID_IDX, gid_index); 3129 3130 return hns_roce_cmq_send(hr_dev, desc, 2); 3131 } 3132 3133 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, 3134 const union ib_gid *gid, 3135 const struct ib_gid_attr *attr) 3136 { 3137 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 3138 int ret; 3139 3140 if (gid) { 3141 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 3142 if (ipv6_addr_v4mapped((void *)gid)) 3143 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 3144 else 3145 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 3146 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 3147 sgid_type = GID_TYPE_FLAG_ROCE_V1; 3148 } 3149 } 3150 3151 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 3152 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 3153 else 3154 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 3155 3156 if (ret) 3157 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 3158 ret); 3159 3160 return ret; 3161 } 3162 3163 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3164 const u8 *addr) 3165 { 3166 struct hns_roce_cmq_desc desc; 3167 struct hns_roce_cfg_smac_tb *smac_tb = 3168 (struct hns_roce_cfg_smac_tb *)desc.data; 3169 u16 reg_smac_h; 3170 u32 reg_smac_l; 3171 3172 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3173 3174 reg_smac_l = *(u32 *)(&addr[0]); 3175 reg_smac_h = *(u16 *)(&addr[4]); 3176 3177 hr_reg_write(smac_tb, CFG_SMAC_TB_IDX, phy_port); 3178 hr_reg_write(smac_tb, CFG_SMAC_TB_VF_SMAC_H, reg_smac_h); 3179 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3180 3181 return hns_roce_cmq_send(hr_dev, &desc, 1); 3182 } 3183 3184 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3185 struct hns_roce_v2_mpt_entry *mpt_entry, 3186 struct hns_roce_mr *mr) 3187 { 3188 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3189 struct ib_device *ibdev = &hr_dev->ib_dev; 3190 dma_addr_t pbl_ba; 3191 int i, count; 3192 3193 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3194 min_t(int, ARRAY_SIZE(pages), mr->npages), 3195 &pbl_ba); 3196 if (count < 1) { 3197 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3198 count); 3199 return -ENOBUFS; 3200 } 3201 3202 /* Aligned to the hardware address access unit */ 3203 for (i = 0; i < count; i++) 3204 pages[i] >>= 6; 3205 3206 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3207 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3208 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3209 3210 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3211 hr_reg_write(mpt_entry, MPT_PA0_H, upper_32_bits(pages[0])); 3212 3213 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3214 hr_reg_write(mpt_entry, MPT_PA1_H, upper_32_bits(pages[1])); 3215 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3216 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3217 3218 return 0; 3219 } 3220 3221 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3222 void *mb_buf, struct hns_roce_mr *mr) 3223 { 3224 struct hns_roce_v2_mpt_entry *mpt_entry; 3225 3226 mpt_entry = mb_buf; 3227 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3228 3229 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3230 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3231 3232 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3233 mr->access & IB_ACCESS_MW_BIND); 3234 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3235 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3236 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3237 mr->access & IB_ACCESS_REMOTE_READ); 3238 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3239 mr->access & IB_ACCESS_REMOTE_WRITE); 3240 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3241 mr->access & IB_ACCESS_LOCAL_WRITE); 3242 3243 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3244 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3245 mpt_entry->lkey = cpu_to_le32(mr->key); 3246 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3247 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3248 3249 if (mr->type != MR_TYPE_MR) 3250 hr_reg_enable(mpt_entry, MPT_PA); 3251 3252 if (mr->type == MR_TYPE_DMA) 3253 return 0; 3254 3255 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3256 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3257 3258 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3259 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3260 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3261 3262 return set_mtpt_pbl(hr_dev, mpt_entry, mr); 3263 } 3264 3265 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3266 struct hns_roce_mr *mr, int flags, 3267 void *mb_buf) 3268 { 3269 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3270 u32 mr_access_flags = mr->access; 3271 int ret = 0; 3272 3273 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3274 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3275 3276 if (flags & IB_MR_REREG_ACCESS) { 3277 hr_reg_write(mpt_entry, MPT_BIND_EN, 3278 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3279 hr_reg_write(mpt_entry, MPT_ATOMIC_EN, 3280 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3281 hr_reg_write(mpt_entry, MPT_RR_EN, 3282 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3283 hr_reg_write(mpt_entry, MPT_RW_EN, 3284 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3285 hr_reg_write(mpt_entry, MPT_LW_EN, 3286 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3287 } 3288 3289 if (flags & IB_MR_REREG_TRANS) { 3290 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3291 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3292 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3293 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3294 3295 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3296 } 3297 3298 return ret; 3299 } 3300 3301 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3302 void *mb_buf, struct hns_roce_mr *mr) 3303 { 3304 struct ib_device *ibdev = &hr_dev->ib_dev; 3305 struct hns_roce_v2_mpt_entry *mpt_entry; 3306 dma_addr_t pbl_ba = 0; 3307 3308 mpt_entry = mb_buf; 3309 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3310 3311 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3312 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3313 return -ENOBUFS; 3314 } 3315 3316 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3317 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3318 3319 hr_reg_enable(mpt_entry, MPT_RA_EN); 3320 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3321 3322 hr_reg_enable(mpt_entry, MPT_FRE); 3323 hr_reg_clear(mpt_entry, MPT_MR_MW); 3324 hr_reg_enable(mpt_entry, MPT_BPD); 3325 hr_reg_clear(mpt_entry, MPT_PA); 3326 3327 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 1); 3328 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3329 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3330 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3331 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3332 3333 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3334 3335 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3336 hr_reg_write(mpt_entry, MPT_PBL_BA_H, upper_32_bits(pbl_ba >> 3)); 3337 3338 return 0; 3339 } 3340 3341 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3342 { 3343 struct hns_roce_v2_mpt_entry *mpt_entry; 3344 3345 mpt_entry = mb_buf; 3346 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3347 3348 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_FREE); 3349 hr_reg_write(mpt_entry, MPT_PD, mw->pdn); 3350 3351 hr_reg_enable(mpt_entry, MPT_R_INV_EN); 3352 hr_reg_enable(mpt_entry, MPT_LW_EN); 3353 3354 hr_reg_enable(mpt_entry, MPT_MR_MW); 3355 hr_reg_enable(mpt_entry, MPT_BPD); 3356 hr_reg_clear(mpt_entry, MPT_PA); 3357 hr_reg_write(mpt_entry, MPT_BQP, 3358 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3359 3360 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3361 3362 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, 3363 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3364 mw->pbl_hop_num); 3365 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3366 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3367 hr_reg_write(mpt_entry, MPT_PBL_BUF_PG_SZ, 3368 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3369 3370 return 0; 3371 } 3372 3373 static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) 3374 { 3375 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device); 3376 struct ib_device *ibdev = &hr_dev->ib_dev; 3377 const struct ib_send_wr *bad_wr; 3378 struct ib_rdma_wr rdma_wr = {}; 3379 struct ib_send_wr *send_wr; 3380 int ret; 3381 3382 send_wr = &rdma_wr.wr; 3383 send_wr->opcode = IB_WR_RDMA_WRITE; 3384 3385 ret = hns_roce_v2_post_send(&hr_qp->ibqp, send_wr, &bad_wr); 3386 if (ret) { 3387 ibdev_err(ibdev, "failed to post wqe for free mr, ret = %d.\n", 3388 ret); 3389 return ret; 3390 } 3391 3392 return 0; 3393 } 3394 3395 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3396 struct ib_wc *wc); 3397 3398 static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) 3399 { 3400 struct hns_roce_v2_priv *priv = hr_dev->priv; 3401 struct hns_roce_v2_free_mr *free_mr = &priv->free_mr; 3402 struct ib_wc wc[ARRAY_SIZE(free_mr->rsv_qp)]; 3403 struct ib_device *ibdev = &hr_dev->ib_dev; 3404 struct hns_roce_qp *hr_qp; 3405 unsigned long end; 3406 int cqe_cnt = 0; 3407 int npolled; 3408 int ret; 3409 int i; 3410 3411 /* 3412 * If the device initialization is not complete or in the uninstall 3413 * process, then there is no need to execute free mr. 3414 */ 3415 if (priv->handle->rinfo.reset_state == HNS_ROCE_STATE_RST_INIT || 3416 priv->handle->rinfo.instance_state == HNS_ROCE_STATE_INIT || 3417 hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) 3418 return; 3419 3420 mutex_lock(&free_mr->mutex); 3421 3422 for (i = 0; i < ARRAY_SIZE(free_mr->rsv_qp); i++) { 3423 hr_qp = free_mr->rsv_qp[i]; 3424 3425 ret = free_mr_post_send_lp_wqe(hr_qp); 3426 if (ret) { 3427 ibdev_err(ibdev, 3428 "failed to send wqe (qp:0x%lx) for free mr, ret = %d.\n", 3429 hr_qp->qpn, ret); 3430 break; 3431 } 3432 3433 cqe_cnt++; 3434 } 3435 3436 end = msecs_to_jiffies(HNS_ROCE_V2_FREE_MR_TIMEOUT) + jiffies; 3437 while (cqe_cnt) { 3438 npolled = hns_roce_v2_poll_cq(&free_mr->rsv_cq->ib_cq, cqe_cnt, wc); 3439 if (npolled < 0) { 3440 ibdev_err(ibdev, 3441 "failed to poll cqe for free mr, remain %d cqe.\n", 3442 cqe_cnt); 3443 goto out; 3444 } 3445 3446 if (time_after(jiffies, end)) { 3447 ibdev_err(ibdev, 3448 "failed to poll cqe for free mr and timeout, remain %d cqe.\n", 3449 cqe_cnt); 3450 goto out; 3451 } 3452 cqe_cnt -= npolled; 3453 } 3454 3455 out: 3456 mutex_unlock(&free_mr->mutex); 3457 } 3458 3459 static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) 3460 { 3461 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 3462 free_mr_send_cmd_to_hw(hr_dev); 3463 } 3464 3465 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3466 { 3467 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3468 } 3469 3470 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3471 { 3472 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3473 3474 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3475 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3476 NULL; 3477 } 3478 3479 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3480 struct hns_roce_cq *hr_cq) 3481 { 3482 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3483 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3484 } else { 3485 struct hns_roce_v2_db cq_db = {}; 3486 3487 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3488 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3489 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3490 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3491 3492 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3493 } 3494 } 3495 3496 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3497 struct hns_roce_srq *srq) 3498 { 3499 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3500 struct hns_roce_v2_cqe *cqe, *dest; 3501 u32 prod_index; 3502 int nfreed = 0; 3503 int wqe_index; 3504 u8 owner_bit; 3505 3506 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3507 ++prod_index) { 3508 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3509 break; 3510 } 3511 3512 /* 3513 * Now backwards through the CQ, removing CQ entries 3514 * that match our QP by overwriting them with next entries. 3515 */ 3516 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3517 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3518 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3519 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3520 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3521 hns_roce_free_srq_wqe(srq, wqe_index); 3522 } 3523 ++nfreed; 3524 } else if (nfreed) { 3525 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3526 hr_cq->ib_cq.cqe); 3527 owner_bit = hr_reg_read(dest, CQE_OWNER); 3528 memcpy(dest, cqe, hr_cq->cqe_size); 3529 hr_reg_write(dest, CQE_OWNER, owner_bit); 3530 } 3531 } 3532 3533 if (nfreed) { 3534 hr_cq->cons_index += nfreed; 3535 update_cq_db(hr_dev, hr_cq); 3536 } 3537 } 3538 3539 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3540 struct hns_roce_srq *srq) 3541 { 3542 spin_lock_irq(&hr_cq->lock); 3543 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3544 spin_unlock_irq(&hr_cq->lock); 3545 } 3546 3547 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3548 struct hns_roce_cq *hr_cq, void *mb_buf, 3549 u64 *mtts, dma_addr_t dma_handle) 3550 { 3551 struct hns_roce_v2_cq_context *cq_context; 3552 3553 cq_context = mb_buf; 3554 memset(cq_context, 0, sizeof(*cq_context)); 3555 3556 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3557 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3558 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3559 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3560 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3561 3562 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3563 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3564 3565 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3566 hr_reg_enable(cq_context, CQC_STASH); 3567 3568 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3569 to_hr_hw_page_addr(mtts[0])); 3570 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3571 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3572 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3573 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3574 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3575 to_hr_hw_page_addr(mtts[1])); 3576 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3577 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3578 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3579 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3580 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3581 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3582 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3583 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3584 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3585 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3586 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3587 ((u32)hr_cq->db.dma) >> 1); 3588 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3589 hr_cq->db.dma >> 32); 3590 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3591 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3592 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3593 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3594 } 3595 3596 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3597 enum ib_cq_notify_flags flags) 3598 { 3599 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3600 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3601 struct hns_roce_v2_db cq_db = {}; 3602 u32 notify_flag; 3603 3604 /* 3605 * flags = 0, then notify_flag : next 3606 * flags = 1, then notify flag : solocited 3607 */ 3608 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3609 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3610 3611 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3612 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3613 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3614 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3615 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3616 3617 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3618 3619 return 0; 3620 } 3621 3622 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3623 int num_entries, struct ib_wc *wc) 3624 { 3625 unsigned int left; 3626 int npolled = 0; 3627 3628 left = wq->head - wq->tail; 3629 if (left == 0) 3630 return 0; 3631 3632 left = min_t(unsigned int, (unsigned int)num_entries, left); 3633 while (npolled < left) { 3634 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3635 wc->status = IB_WC_WR_FLUSH_ERR; 3636 wc->vendor_err = 0; 3637 wc->qp = &hr_qp->ibqp; 3638 3639 wq->tail++; 3640 wc++; 3641 npolled++; 3642 } 3643 3644 return npolled; 3645 } 3646 3647 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3648 struct ib_wc *wc) 3649 { 3650 struct hns_roce_qp *hr_qp; 3651 int npolled = 0; 3652 3653 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3654 npolled += sw_comp(hr_qp, &hr_qp->sq, 3655 num_entries - npolled, wc + npolled); 3656 if (npolled >= num_entries) 3657 goto out; 3658 } 3659 3660 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3661 npolled += sw_comp(hr_qp, &hr_qp->rq, 3662 num_entries - npolled, wc + npolled); 3663 if (npolled >= num_entries) 3664 goto out; 3665 } 3666 3667 out: 3668 return npolled; 3669 } 3670 3671 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3672 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3673 struct ib_wc *wc) 3674 { 3675 static const struct { 3676 u32 cqe_status; 3677 enum ib_wc_status wc_status; 3678 } map[] = { 3679 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3680 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3681 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3682 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3683 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3684 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3685 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3686 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3687 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3688 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3689 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3690 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3691 IB_WC_RETRY_EXC_ERR }, 3692 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3693 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3694 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3695 }; 3696 3697 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3698 int i; 3699 3700 wc->status = IB_WC_GENERAL_ERR; 3701 for (i = 0; i < ARRAY_SIZE(map); i++) 3702 if (cqe_status == map[i].cqe_status) { 3703 wc->status = map[i].wc_status; 3704 break; 3705 } 3706 3707 if (likely(wc->status == IB_WC_SUCCESS || 3708 wc->status == IB_WC_WR_FLUSH_ERR)) 3709 return; 3710 3711 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3712 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3713 cq->cqe_size, false); 3714 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3715 3716 /* 3717 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3718 * the standard protocol, the driver must ignore it and needn't to set 3719 * the QP to an error state. 3720 */ 3721 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3722 return; 3723 3724 flush_cqe(hr_dev, qp); 3725 } 3726 3727 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3728 struct hns_roce_qp **cur_qp) 3729 { 3730 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3731 struct hns_roce_qp *hr_qp = *cur_qp; 3732 u32 qpn; 3733 3734 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3735 3736 if (!hr_qp || qpn != hr_qp->qpn) { 3737 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3738 if (unlikely(!hr_qp)) { 3739 ibdev_err(&hr_dev->ib_dev, 3740 "CQ %06lx with entry for unknown QPN %06x\n", 3741 hr_cq->cqn, qpn); 3742 return -EINVAL; 3743 } 3744 *cur_qp = hr_qp; 3745 } 3746 3747 return 0; 3748 } 3749 3750 /* 3751 * mapped-value = 1 + real-value 3752 * The ib wc opcode's real value is start from 0, In order to distinguish 3753 * between initialized and uninitialized map values, we plus 1 to the actual 3754 * value when defining the mapping, so that the validity can be identified by 3755 * checking whether the mapped value is greater than 0. 3756 */ 3757 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3758 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3759 3760 static const u32 wc_send_op_map[] = { 3761 HR_WC_OP_MAP(SEND, SEND), 3762 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3763 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3764 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3765 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3766 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3767 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3768 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3769 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3770 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3771 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3772 HR_WC_OP_MAP(BIND_MW, REG_MR), 3773 }; 3774 3775 static int to_ib_wc_send_op(u32 hr_opcode) 3776 { 3777 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3778 return -EINVAL; 3779 3780 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3781 -EINVAL; 3782 } 3783 3784 static const u32 wc_recv_op_map[] = { 3785 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3786 HR_WC_OP_MAP(SEND, RECV), 3787 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3788 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3789 }; 3790 3791 static int to_ib_wc_recv_op(u32 hr_opcode) 3792 { 3793 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3794 return -EINVAL; 3795 3796 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3797 -EINVAL; 3798 } 3799 3800 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3801 { 3802 u32 hr_opcode; 3803 int ib_opcode; 3804 3805 wc->wc_flags = 0; 3806 3807 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3808 switch (hr_opcode) { 3809 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3810 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3811 break; 3812 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3813 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3814 wc->wc_flags |= IB_WC_WITH_IMM; 3815 break; 3816 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3817 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3818 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3819 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3820 wc->byte_len = 8; 3821 break; 3822 default: 3823 break; 3824 } 3825 3826 ib_opcode = to_ib_wc_send_op(hr_opcode); 3827 if (ib_opcode < 0) 3828 wc->status = IB_WC_GENERAL_ERR; 3829 else 3830 wc->opcode = ib_opcode; 3831 } 3832 3833 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3834 { 3835 u32 hr_opcode; 3836 int ib_opcode; 3837 3838 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3839 3840 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3841 switch (hr_opcode) { 3842 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3843 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3844 wc->wc_flags = IB_WC_WITH_IMM; 3845 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3846 break; 3847 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3848 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3849 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3850 break; 3851 default: 3852 wc->wc_flags = 0; 3853 } 3854 3855 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3856 if (ib_opcode < 0) 3857 wc->status = IB_WC_GENERAL_ERR; 3858 else 3859 wc->opcode = ib_opcode; 3860 3861 wc->sl = hr_reg_read(cqe, CQE_SL); 3862 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3863 wc->slid = 0; 3864 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3865 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3866 wc->pkey_index = 0; 3867 3868 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3869 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3870 wc->wc_flags |= IB_WC_WITH_VLAN; 3871 } else { 3872 wc->vlan_id = 0xffff; 3873 } 3874 3875 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3876 3877 return 0; 3878 } 3879 3880 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3881 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3882 { 3883 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3884 struct hns_roce_qp *qp = *cur_qp; 3885 struct hns_roce_srq *srq = NULL; 3886 struct hns_roce_v2_cqe *cqe; 3887 struct hns_roce_wq *wq; 3888 int is_send; 3889 u16 wqe_idx; 3890 int ret; 3891 3892 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3893 if (!cqe) 3894 return -EAGAIN; 3895 3896 ++hr_cq->cons_index; 3897 /* Memory barrier */ 3898 rmb(); 3899 3900 ret = get_cur_qp(hr_cq, cqe, &qp); 3901 if (ret) 3902 return ret; 3903 3904 wc->qp = &qp->ibqp; 3905 wc->vendor_err = 0; 3906 3907 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3908 3909 is_send = !hr_reg_read(cqe, CQE_S_R); 3910 if (is_send) { 3911 wq = &qp->sq; 3912 3913 /* If sg_signal_bit is set, tail pointer will be updated to 3914 * the WQE corresponding to the current CQE. 3915 */ 3916 if (qp->sq_signal_bits) 3917 wq->tail += (wqe_idx - (u16)wq->tail) & 3918 (wq->wqe_cnt - 1); 3919 3920 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3921 ++wq->tail; 3922 3923 fill_send_wc(wc, cqe); 3924 } else { 3925 if (qp->ibqp.srq) { 3926 srq = to_hr_srq(qp->ibqp.srq); 3927 wc->wr_id = srq->wrid[wqe_idx]; 3928 hns_roce_free_srq_wqe(srq, wqe_idx); 3929 } else { 3930 wq = &qp->rq; 3931 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3932 ++wq->tail; 3933 } 3934 3935 ret = fill_recv_wc(wc, cqe); 3936 } 3937 3938 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3939 if (unlikely(wc->status != IB_WC_SUCCESS)) 3940 return 0; 3941 3942 return ret; 3943 } 3944 3945 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3946 struct ib_wc *wc) 3947 { 3948 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3949 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3950 struct hns_roce_qp *cur_qp = NULL; 3951 unsigned long flags; 3952 int npolled; 3953 3954 spin_lock_irqsave(&hr_cq->lock, flags); 3955 3956 /* 3957 * When the device starts to reset, the state is RST_DOWN. At this time, 3958 * there may still be some valid CQEs in the hardware that are not 3959 * polled. Therefore, it is not allowed to switch to the software mode 3960 * immediately. When the state changes to UNINIT, CQE no longer exists 3961 * in the hardware, and then switch to software mode. 3962 */ 3963 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3964 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3965 goto out; 3966 } 3967 3968 for (npolled = 0; npolled < num_entries; ++npolled) { 3969 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3970 break; 3971 } 3972 3973 if (npolled) 3974 update_cq_db(hr_dev, hr_cq); 3975 3976 out: 3977 spin_unlock_irqrestore(&hr_cq->lock, flags); 3978 3979 return npolled; 3980 } 3981 3982 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3983 u32 step_idx, u8 *mbox_cmd) 3984 { 3985 u8 cmd; 3986 3987 switch (type) { 3988 case HEM_TYPE_QPC: 3989 cmd = HNS_ROCE_CMD_WRITE_QPC_BT0; 3990 break; 3991 case HEM_TYPE_MTPT: 3992 cmd = HNS_ROCE_CMD_WRITE_MPT_BT0; 3993 break; 3994 case HEM_TYPE_CQC: 3995 cmd = HNS_ROCE_CMD_WRITE_CQC_BT0; 3996 break; 3997 case HEM_TYPE_SRQC: 3998 cmd = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3999 break; 4000 case HEM_TYPE_SCCC: 4001 cmd = HNS_ROCE_CMD_WRITE_SCCC_BT0; 4002 break; 4003 case HEM_TYPE_QPC_TIMER: 4004 cmd = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 4005 break; 4006 case HEM_TYPE_CQC_TIMER: 4007 cmd = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 4008 break; 4009 default: 4010 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 4011 return -EINVAL; 4012 } 4013 4014 *mbox_cmd = cmd + step_idx; 4015 4016 return 0; 4017 } 4018 4019 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 4020 dma_addr_t base_addr) 4021 { 4022 struct hns_roce_cmq_desc desc; 4023 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 4024 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 4025 u64 addr = to_hr_hw_page_addr(base_addr); 4026 4027 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 4028 4029 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 4030 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 4031 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 4032 4033 return hns_roce_cmq_send(hr_dev, &desc, 1); 4034 } 4035 4036 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 4037 dma_addr_t base_addr, u32 hem_type, u32 step_idx) 4038 { 4039 int ret; 4040 u8 cmd; 4041 4042 if (unlikely(hem_type == HEM_TYPE_GMV)) 4043 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 4044 4045 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 4046 return 0; 4047 4048 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &cmd); 4049 if (ret < 0) 4050 return ret; 4051 4052 return config_hem_ba_to_hw(hr_dev, base_addr, cmd, obj); 4053 } 4054 4055 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 4056 struct hns_roce_hem_table *table, int obj, 4057 u32 step_idx) 4058 { 4059 struct hns_roce_hem_iter iter; 4060 struct hns_roce_hem_mhop mhop; 4061 struct hns_roce_hem *hem; 4062 unsigned long mhop_obj = obj; 4063 int i, j, k; 4064 int ret = 0; 4065 u64 hem_idx = 0; 4066 u64 l1_idx = 0; 4067 u64 bt_ba = 0; 4068 u32 chunk_ba_num; 4069 u32 hop_num; 4070 4071 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4072 return 0; 4073 4074 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 4075 i = mhop.l0_idx; 4076 j = mhop.l1_idx; 4077 k = mhop.l2_idx; 4078 hop_num = mhop.hop_num; 4079 chunk_ba_num = mhop.bt_chunk_size / 8; 4080 4081 if (hop_num == 2) { 4082 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 4083 k; 4084 l1_idx = i * chunk_ba_num + j; 4085 } else if (hop_num == 1) { 4086 hem_idx = i * chunk_ba_num + j; 4087 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 4088 hem_idx = i; 4089 } 4090 4091 if (table->type == HEM_TYPE_SCCC) 4092 obj = mhop.l0_idx; 4093 4094 if (check_whether_last_step(hop_num, step_idx)) { 4095 hem = table->hem[hem_idx]; 4096 for (hns_roce_hem_first(hem, &iter); 4097 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 4098 bt_ba = hns_roce_hem_addr(&iter); 4099 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 4100 step_idx); 4101 } 4102 } else { 4103 if (step_idx == 0) 4104 bt_ba = table->bt_l0_dma_addr[i]; 4105 else if (step_idx == 1 && hop_num == 2) 4106 bt_ba = table->bt_l1_dma_addr[l1_idx]; 4107 4108 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 4109 } 4110 4111 return ret; 4112 } 4113 4114 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 4115 struct hns_roce_hem_table *table, 4116 int tag, u32 step_idx) 4117 { 4118 struct hns_roce_cmd_mailbox *mailbox; 4119 struct device *dev = hr_dev->dev; 4120 u8 cmd = 0xff; 4121 int ret; 4122 4123 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 4124 return 0; 4125 4126 switch (table->type) { 4127 case HEM_TYPE_QPC: 4128 cmd = HNS_ROCE_CMD_DESTROY_QPC_BT0; 4129 break; 4130 case HEM_TYPE_MTPT: 4131 cmd = HNS_ROCE_CMD_DESTROY_MPT_BT0; 4132 break; 4133 case HEM_TYPE_CQC: 4134 cmd = HNS_ROCE_CMD_DESTROY_CQC_BT0; 4135 break; 4136 case HEM_TYPE_SRQC: 4137 cmd = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 4138 break; 4139 case HEM_TYPE_SCCC: 4140 case HEM_TYPE_QPC_TIMER: 4141 case HEM_TYPE_CQC_TIMER: 4142 case HEM_TYPE_GMV: 4143 return 0; 4144 default: 4145 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 4146 table->type); 4147 return 0; 4148 } 4149 4150 cmd += step_idx; 4151 4152 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4153 if (IS_ERR(mailbox)) 4154 return PTR_ERR(mailbox); 4155 4156 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, cmd, tag); 4157 4158 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4159 return ret; 4160 } 4161 4162 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4163 struct hns_roce_v2_qp_context *context, 4164 struct hns_roce_v2_qp_context *qpc_mask, 4165 struct hns_roce_qp *hr_qp) 4166 { 4167 struct hns_roce_cmd_mailbox *mailbox; 4168 int qpc_size; 4169 int ret; 4170 4171 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4172 if (IS_ERR(mailbox)) 4173 return PTR_ERR(mailbox); 4174 4175 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4176 qpc_size = hr_dev->caps.qpc_sz; 4177 memcpy(mailbox->buf, context, qpc_size); 4178 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4179 4180 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 4181 HNS_ROCE_CMD_MODIFY_QPC, hr_qp->qpn); 4182 4183 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4184 4185 return ret; 4186 } 4187 4188 static void set_access_flags(struct hns_roce_qp *hr_qp, 4189 struct hns_roce_v2_qp_context *context, 4190 struct hns_roce_v2_qp_context *qpc_mask, 4191 const struct ib_qp_attr *attr, int attr_mask) 4192 { 4193 u8 dest_rd_atomic; 4194 u32 access_flags; 4195 4196 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4197 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4198 4199 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4200 attr->qp_access_flags : hr_qp->atomic_rd_en; 4201 4202 if (!dest_rd_atomic) 4203 access_flags &= IB_ACCESS_REMOTE_WRITE; 4204 4205 hr_reg_write_bool(context, QPC_RRE, 4206 access_flags & IB_ACCESS_REMOTE_READ); 4207 hr_reg_clear(qpc_mask, QPC_RRE); 4208 4209 hr_reg_write_bool(context, QPC_RWE, 4210 access_flags & IB_ACCESS_REMOTE_WRITE); 4211 hr_reg_clear(qpc_mask, QPC_RWE); 4212 4213 hr_reg_write_bool(context, QPC_ATE, 4214 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4215 hr_reg_clear(qpc_mask, QPC_ATE); 4216 hr_reg_write_bool(context, QPC_EXT_ATE, 4217 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4218 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4219 } 4220 4221 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4222 struct hns_roce_v2_qp_context *context, 4223 struct hns_roce_v2_qp_context *qpc_mask) 4224 { 4225 hr_reg_write(context, QPC_SGE_SHIFT, 4226 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4227 hr_qp->sge.sge_shift)); 4228 4229 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4230 4231 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4232 } 4233 4234 static inline int get_cqn(struct ib_cq *ib_cq) 4235 { 4236 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4237 } 4238 4239 static inline int get_pdn(struct ib_pd *ib_pd) 4240 { 4241 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4242 } 4243 4244 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4245 const struct ib_qp_attr *attr, 4246 struct hns_roce_v2_qp_context *context, 4247 struct hns_roce_v2_qp_context *qpc_mask) 4248 { 4249 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4250 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4251 4252 /* 4253 * In v2 engine, software pass context and context mask to hardware 4254 * when modifying qp. If software need modify some fields in context, 4255 * we should set all bits of the relevant fields in context mask to 4256 * 0 at the same time, else set them to 0x1. 4257 */ 4258 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4259 4260 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4261 4262 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4263 4264 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4265 4266 /* No VLAN need to set 0xFFF */ 4267 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4268 4269 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4270 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4271 4272 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4273 } 4274 4275 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4276 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4277 4278 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4279 hr_reg_enable(context, QPC_OWNER_MODE); 4280 4281 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4282 lower_32_bits(hr_qp->rdb.dma) >> 1); 4283 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4284 upper_32_bits(hr_qp->rdb.dma)); 4285 4286 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4287 4288 if (ibqp->srq) { 4289 hr_reg_enable(context, QPC_SRQ_EN); 4290 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4291 } 4292 4293 hr_reg_enable(context, QPC_FRE); 4294 4295 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4296 4297 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4298 return; 4299 4300 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4301 hr_reg_enable(&context->ext, QPCEX_STASH); 4302 } 4303 4304 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4305 const struct ib_qp_attr *attr, 4306 struct hns_roce_v2_qp_context *context, 4307 struct hns_roce_v2_qp_context *qpc_mask) 4308 { 4309 /* 4310 * In v2 engine, software pass context and context mask to hardware 4311 * when modifying qp. If software need modify some fields in context, 4312 * we should set all bits of the relevant fields in context mask to 4313 * 0 at the same time, else set them to 0x1. 4314 */ 4315 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4316 hr_reg_clear(qpc_mask, QPC_TST); 4317 4318 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4319 hr_reg_clear(qpc_mask, QPC_PD); 4320 4321 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4322 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4323 4324 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4325 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4326 4327 if (ibqp->srq) { 4328 hr_reg_enable(context, QPC_SRQ_EN); 4329 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4330 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4331 hr_reg_clear(qpc_mask, QPC_SRQN); 4332 } 4333 } 4334 4335 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4336 struct hns_roce_qp *hr_qp, 4337 struct hns_roce_v2_qp_context *context, 4338 struct hns_roce_v2_qp_context *qpc_mask) 4339 { 4340 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4341 u64 wqe_sge_ba; 4342 int count; 4343 4344 /* Search qp buf's mtts */ 4345 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4346 MTT_MIN_COUNT, &wqe_sge_ba); 4347 if (hr_qp->rq.wqe_cnt && count < 1) { 4348 ibdev_err(&hr_dev->ib_dev, 4349 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4350 return -EINVAL; 4351 } 4352 4353 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4354 qpc_mask->wqe_sge_ba = 0; 4355 4356 /* 4357 * In v2 engine, software pass context and context mask to hardware 4358 * when modifying qp. If software need modify some fields in context, 4359 * we should set all bits of the relevant fields in context mask to 4360 * 0 at the same time, else set them to 0x1. 4361 */ 4362 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4363 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4364 4365 hr_reg_write(context, QPC_SQ_HOP_NUM, 4366 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4367 hr_qp->sq.wqe_cnt)); 4368 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4369 4370 hr_reg_write(context, QPC_SGE_HOP_NUM, 4371 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4372 hr_qp->sge.sge_cnt)); 4373 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4374 4375 hr_reg_write(context, QPC_RQ_HOP_NUM, 4376 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4377 hr_qp->rq.wqe_cnt)); 4378 4379 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4380 4381 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4382 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4383 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4384 4385 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4386 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4387 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4388 4389 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4390 qpc_mask->rq_cur_blk_addr = 0; 4391 4392 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4393 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4394 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4395 4396 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4397 qpc_mask->rq_nxt_blk_addr = 0; 4398 4399 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4400 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4401 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4402 4403 return 0; 4404 } 4405 4406 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4407 struct hns_roce_qp *hr_qp, 4408 struct hns_roce_v2_qp_context *context, 4409 struct hns_roce_v2_qp_context *qpc_mask) 4410 { 4411 struct ib_device *ibdev = &hr_dev->ib_dev; 4412 u64 sge_cur_blk = 0; 4413 u64 sq_cur_blk = 0; 4414 int count; 4415 4416 /* search qp buf's mtts */ 4417 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4418 if (count < 1) { 4419 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4420 hr_qp->qpn); 4421 return -EINVAL; 4422 } 4423 if (hr_qp->sge.sge_cnt > 0) { 4424 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4425 hr_qp->sge.offset, 4426 &sge_cur_blk, 1, NULL); 4427 if (count < 1) { 4428 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4429 hr_qp->qpn); 4430 return -EINVAL; 4431 } 4432 } 4433 4434 /* 4435 * In v2 engine, software pass context and context mask to hardware 4436 * when modifying qp. If software need modify some fields in context, 4437 * we should set all bits of the relevant fields in context mask to 4438 * 0 at the same time, else set them to 0x1. 4439 */ 4440 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4441 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4442 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4443 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4444 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4445 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4446 4447 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4448 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4449 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4450 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4451 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4452 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4453 4454 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4455 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4456 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4457 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4458 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4459 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4460 4461 return 0; 4462 } 4463 4464 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4465 const struct ib_qp_attr *attr) 4466 { 4467 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4468 return IB_MTU_4096; 4469 4470 return attr->path_mtu; 4471 } 4472 4473 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4474 const struct ib_qp_attr *attr, int attr_mask, 4475 struct hns_roce_v2_qp_context *context, 4476 struct hns_roce_v2_qp_context *qpc_mask, 4477 struct ib_udata *udata) 4478 { 4479 struct hns_roce_ucontext *uctx = rdma_udata_to_drv_context(udata, 4480 struct hns_roce_ucontext, ibucontext); 4481 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4482 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4483 struct ib_device *ibdev = &hr_dev->ib_dev; 4484 dma_addr_t trrl_ba; 4485 dma_addr_t irrl_ba; 4486 enum ib_mtu ib_mtu; 4487 const u8 *smac; 4488 u8 lp_pktn_ini; 4489 u64 *mtts; 4490 u8 *dmac; 4491 u32 port; 4492 int mtu; 4493 int ret; 4494 4495 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4496 if (ret) { 4497 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4498 return ret; 4499 } 4500 4501 /* Search IRRL's mtts */ 4502 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4503 hr_qp->qpn, &irrl_ba); 4504 if (!mtts) { 4505 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4506 return -EINVAL; 4507 } 4508 4509 /* Search TRRL's mtts */ 4510 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4511 hr_qp->qpn, &trrl_ba); 4512 if (!mtts) { 4513 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4514 return -EINVAL; 4515 } 4516 4517 if (attr_mask & IB_QP_ALT_PATH) { 4518 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4519 attr_mask); 4520 return -EINVAL; 4521 } 4522 4523 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4524 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4525 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4526 qpc_mask->trrl_ba = 0; 4527 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4528 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4529 4530 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4531 qpc_mask->irrl_ba = 0; 4532 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4533 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4534 4535 hr_reg_enable(context, QPC_RMT_E2E); 4536 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4537 4538 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4539 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4540 4541 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4542 4543 smac = (const u8 *)hr_dev->dev_addr[port]; 4544 dmac = (u8 *)attr->ah_attr.roce.dmac; 4545 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4546 if (ether_addr_equal_unaligned(dmac, smac) || 4547 hr_dev->loop_idc == 0x1) { 4548 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4549 hr_reg_clear(qpc_mask, QPC_LBI); 4550 } 4551 4552 if (attr_mask & IB_QP_DEST_QPN) { 4553 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4554 hr_reg_clear(qpc_mask, QPC_DQPN); 4555 } 4556 4557 memcpy(&context->dmac, dmac, sizeof(u32)); 4558 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4559 qpc_mask->dmac = 0; 4560 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4561 4562 ib_mtu = get_mtu(ibqp, attr); 4563 hr_qp->path_mtu = ib_mtu; 4564 4565 mtu = ib_mtu_enum_to_int(ib_mtu); 4566 if (WARN_ON(mtu <= 0)) 4567 return -EINVAL; 4568 #define MIN_LP_MSG_LEN 1024 4569 /* mtu * (2 ^ lp_pktn_ini) should be in the range of 1024 to mtu */ 4570 lp_pktn_ini = ilog2(max(mtu, MIN_LP_MSG_LEN) / mtu); 4571 4572 if (attr_mask & IB_QP_PATH_MTU) { 4573 hr_reg_write(context, QPC_MTU, ib_mtu); 4574 hr_reg_clear(qpc_mask, QPC_MTU); 4575 } 4576 4577 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4578 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4579 4580 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4581 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4582 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4583 4584 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4585 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4586 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4587 4588 context->rq_rnr_timer = 0; 4589 qpc_mask->rq_rnr_timer = 0; 4590 4591 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4592 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4593 4594 /* rocee send 2^lp_sgen_ini segs every time */ 4595 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4596 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4597 4598 if (udata && ibqp->qp_type == IB_QPT_RC && 4599 (uctx->config & HNS_ROCE_RQ_INLINE_FLAGS)) { 4600 hr_reg_write_bool(context, QPC_RQIE, 4601 hr_dev->caps.flags & 4602 HNS_ROCE_CAP_FLAG_RQ_INLINE); 4603 hr_reg_clear(qpc_mask, QPC_RQIE); 4604 } 4605 4606 if (udata && 4607 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_XRC_TGT) && 4608 (uctx->config & HNS_ROCE_CQE_INLINE_FLAGS)) { 4609 hr_reg_write_bool(context, QPC_CQEIE, 4610 hr_dev->caps.flags & 4611 HNS_ROCE_CAP_FLAG_CQE_INLINE); 4612 hr_reg_clear(qpc_mask, QPC_CQEIE); 4613 4614 hr_reg_write(context, QPC_CQEIS, 0); 4615 hr_reg_clear(qpc_mask, QPC_CQEIS); 4616 } 4617 4618 return 0; 4619 } 4620 4621 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4622 const struct ib_qp_attr *attr, int attr_mask, 4623 struct hns_roce_v2_qp_context *context, 4624 struct hns_roce_v2_qp_context *qpc_mask) 4625 { 4626 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4627 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4628 struct ib_device *ibdev = &hr_dev->ib_dev; 4629 int ret; 4630 4631 /* Not support alternate path and path migration */ 4632 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4633 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4634 return -EINVAL; 4635 } 4636 4637 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4638 if (ret) { 4639 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4640 return ret; 4641 } 4642 4643 /* 4644 * Set some fields in context to zero, Because the default values 4645 * of all fields in context are zero, we need not set them to 0 again. 4646 * but we should set the relevant fields of context mask to 0. 4647 */ 4648 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4649 4650 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4651 4652 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4653 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4654 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4655 4656 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4657 4658 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4659 4660 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4661 4662 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4663 4664 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4665 4666 return 0; 4667 } 4668 4669 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4670 u32 *dip_idx) 4671 { 4672 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4673 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4674 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4675 u32 *head = &hr_dev->qp_table.idx_table.head; 4676 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4677 struct hns_roce_dip *hr_dip; 4678 unsigned long flags; 4679 int ret = 0; 4680 4681 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4682 4683 spare_idx[*tail] = ibqp->qp_num; 4684 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4685 4686 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4687 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4688 *dip_idx = hr_dip->dip_idx; 4689 goto out; 4690 } 4691 } 4692 4693 /* If no dgid is found, a new dip and a mapping between dgid and 4694 * dip_idx will be created. 4695 */ 4696 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4697 if (!hr_dip) { 4698 ret = -ENOMEM; 4699 goto out; 4700 } 4701 4702 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4703 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4704 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4705 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4706 4707 out: 4708 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4709 return ret; 4710 } 4711 4712 enum { 4713 CONG_DCQCN, 4714 CONG_WINDOW, 4715 }; 4716 4717 enum { 4718 UNSUPPORT_CONG_LEVEL, 4719 SUPPORT_CONG_LEVEL, 4720 }; 4721 4722 enum { 4723 CONG_LDCP, 4724 CONG_HC3, 4725 }; 4726 4727 enum { 4728 DIP_INVALID, 4729 DIP_VALID, 4730 }; 4731 4732 enum { 4733 WND_LIMIT, 4734 WND_UNLIMIT, 4735 }; 4736 4737 static int check_cong_type(struct ib_qp *ibqp, 4738 struct hns_roce_congestion_algorithm *cong_alg) 4739 { 4740 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4741 4742 /* different congestion types match different configurations */ 4743 switch (hr_dev->caps.cong_type) { 4744 case CONG_TYPE_DCQCN: 4745 cong_alg->alg_sel = CONG_DCQCN; 4746 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4747 cong_alg->dip_vld = DIP_INVALID; 4748 cong_alg->wnd_mode_sel = WND_LIMIT; 4749 break; 4750 case CONG_TYPE_LDCP: 4751 cong_alg->alg_sel = CONG_WINDOW; 4752 cong_alg->alg_sub_sel = CONG_LDCP; 4753 cong_alg->dip_vld = DIP_INVALID; 4754 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4755 break; 4756 case CONG_TYPE_HC3: 4757 cong_alg->alg_sel = CONG_WINDOW; 4758 cong_alg->alg_sub_sel = CONG_HC3; 4759 cong_alg->dip_vld = DIP_INVALID; 4760 cong_alg->wnd_mode_sel = WND_LIMIT; 4761 break; 4762 case CONG_TYPE_DIP: 4763 cong_alg->alg_sel = CONG_DCQCN; 4764 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4765 cong_alg->dip_vld = DIP_VALID; 4766 cong_alg->wnd_mode_sel = WND_LIMIT; 4767 break; 4768 default: 4769 ibdev_err(&hr_dev->ib_dev, 4770 "error type(%u) for congestion selection.\n", 4771 hr_dev->caps.cong_type); 4772 return -EINVAL; 4773 } 4774 4775 return 0; 4776 } 4777 4778 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4779 struct hns_roce_v2_qp_context *context, 4780 struct hns_roce_v2_qp_context *qpc_mask) 4781 { 4782 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4783 struct hns_roce_congestion_algorithm cong_field; 4784 struct ib_device *ibdev = ibqp->device; 4785 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4786 u32 dip_idx = 0; 4787 int ret; 4788 4789 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4790 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4791 return 0; 4792 4793 ret = check_cong_type(ibqp, &cong_field); 4794 if (ret) 4795 return ret; 4796 4797 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4798 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4799 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4800 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4801 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4802 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4803 cong_field.alg_sub_sel); 4804 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4805 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4806 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4807 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4808 cong_field.wnd_mode_sel); 4809 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4810 4811 /* if dip is disabled, there is no need to set dip idx */ 4812 if (cong_field.dip_vld == 0) 4813 return 0; 4814 4815 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4816 if (ret) { 4817 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4818 return ret; 4819 } 4820 4821 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4822 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4823 4824 return 0; 4825 } 4826 4827 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4828 const struct ib_qp_attr *attr, 4829 int attr_mask, 4830 struct hns_roce_v2_qp_context *context, 4831 struct hns_roce_v2_qp_context *qpc_mask) 4832 { 4833 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4834 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4835 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4836 struct ib_device *ibdev = &hr_dev->ib_dev; 4837 const struct ib_gid_attr *gid_attr = NULL; 4838 int is_roce_protocol; 4839 u16 vlan_id = 0xffff; 4840 bool is_udp = false; 4841 u8 ib_port; 4842 u8 hr_port; 4843 int ret; 4844 4845 /* 4846 * If free_mr_en of qp is set, it means that this qp comes from 4847 * free mr. This qp will perform the loopback operation. 4848 * In the loopback scenario, only sl needs to be set. 4849 */ 4850 if (hr_qp->free_mr_en) { 4851 hr_reg_write(context, QPC_SL, rdma_ah_get_sl(&attr->ah_attr)); 4852 hr_reg_clear(qpc_mask, QPC_SL); 4853 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4854 return 0; 4855 } 4856 4857 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4858 hr_port = ib_port - 1; 4859 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4860 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4861 4862 if (is_roce_protocol) { 4863 gid_attr = attr->ah_attr.grh.sgid_attr; 4864 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4865 if (ret) 4866 return ret; 4867 4868 is_udp = (gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP); 4869 } 4870 4871 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4872 if (vlan_id < VLAN_N_VID && 4873 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4874 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4875 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4876 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4877 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4878 } 4879 4880 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4881 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4882 4883 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4884 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4885 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4886 return -EINVAL; 4887 } 4888 4889 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4890 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4891 return -EINVAL; 4892 } 4893 4894 hr_reg_write(context, QPC_UDPSPN, 4895 is_udp ? rdma_get_udp_sport(grh->flow_label, ibqp->qp_num, 4896 attr->dest_qp_num) : 4897 0); 4898 4899 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4900 4901 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4902 4903 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4904 4905 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4906 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4907 4908 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4909 if (ret) 4910 return ret; 4911 4912 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4913 hr_reg_clear(qpc_mask, QPC_TC); 4914 4915 hr_reg_write(context, QPC_FL, grh->flow_label); 4916 hr_reg_clear(qpc_mask, QPC_FL); 4917 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4918 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4919 4920 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4921 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4922 ibdev_err(ibdev, 4923 "failed to fill QPC, sl (%u) shouldn't be larger than %d.\n", 4924 hr_qp->sl, MAX_SERVICE_LEVEL); 4925 return -EINVAL; 4926 } 4927 4928 hr_reg_write(context, QPC_SL, hr_qp->sl); 4929 hr_reg_clear(qpc_mask, QPC_SL); 4930 4931 return 0; 4932 } 4933 4934 static bool check_qp_state(enum ib_qp_state cur_state, 4935 enum ib_qp_state new_state) 4936 { 4937 static const bool sm[][IB_QPS_ERR + 1] = { 4938 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4939 [IB_QPS_INIT] = true }, 4940 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4941 [IB_QPS_INIT] = true, 4942 [IB_QPS_RTR] = true, 4943 [IB_QPS_ERR] = true }, 4944 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4945 [IB_QPS_RTS] = true, 4946 [IB_QPS_ERR] = true }, 4947 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4948 [IB_QPS_RTS] = true, 4949 [IB_QPS_ERR] = true }, 4950 [IB_QPS_SQD] = {}, 4951 [IB_QPS_SQE] = {}, 4952 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, 4953 [IB_QPS_ERR] = true } 4954 }; 4955 4956 return sm[cur_state][new_state]; 4957 } 4958 4959 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4960 const struct ib_qp_attr *attr, 4961 int attr_mask, 4962 enum ib_qp_state cur_state, 4963 enum ib_qp_state new_state, 4964 struct hns_roce_v2_qp_context *context, 4965 struct hns_roce_v2_qp_context *qpc_mask, 4966 struct ib_udata *udata) 4967 { 4968 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4969 int ret = 0; 4970 4971 if (!check_qp_state(cur_state, new_state)) { 4972 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4973 return -EINVAL; 4974 } 4975 4976 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4977 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4978 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask); 4979 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4980 modify_qp_init_to_init(ibqp, attr, context, qpc_mask); 4981 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4982 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4983 qpc_mask, udata); 4984 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4985 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4986 qpc_mask); 4987 } 4988 4989 return ret; 4990 } 4991 4992 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 4993 { 4994 #define QP_ACK_TIMEOUT_MAX_HIP08 20 4995 #define QP_ACK_TIMEOUT_MAX 31 4996 4997 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4998 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 4999 ibdev_warn(&hr_dev->ib_dev, 5000 "local ACK timeout shall be 0 to 20.\n"); 5001 return false; 5002 } 5003 *timeout += HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5004 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 5005 if (*timeout > QP_ACK_TIMEOUT_MAX) { 5006 ibdev_warn(&hr_dev->ib_dev, 5007 "local ACK timeout shall be 0 to 31.\n"); 5008 return false; 5009 } 5010 } 5011 5012 return true; 5013 } 5014 5015 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 5016 const struct ib_qp_attr *attr, 5017 int attr_mask, 5018 struct hns_roce_v2_qp_context *context, 5019 struct hns_roce_v2_qp_context *qpc_mask) 5020 { 5021 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5022 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5023 int ret = 0; 5024 u8 timeout; 5025 5026 if (attr_mask & IB_QP_AV) { 5027 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 5028 qpc_mask); 5029 if (ret) 5030 return ret; 5031 } 5032 5033 if (attr_mask & IB_QP_TIMEOUT) { 5034 timeout = attr->timeout; 5035 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 5036 hr_reg_write(context, QPC_AT, timeout); 5037 hr_reg_clear(qpc_mask, QPC_AT); 5038 } 5039 } 5040 5041 if (attr_mask & IB_QP_RETRY_CNT) { 5042 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 5043 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 5044 5045 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 5046 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 5047 } 5048 5049 if (attr_mask & IB_QP_RNR_RETRY) { 5050 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 5051 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 5052 5053 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 5054 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 5055 } 5056 5057 if (attr_mask & IB_QP_SQ_PSN) { 5058 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 5059 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 5060 5061 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 5062 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 5063 5064 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 5065 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 5066 5067 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 5068 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 5069 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 5070 5071 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 5072 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 5073 5074 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 5075 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 5076 } 5077 5078 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 5079 attr->max_dest_rd_atomic) { 5080 hr_reg_write(context, QPC_RR_MAX, 5081 fls(attr->max_dest_rd_atomic - 1)); 5082 hr_reg_clear(qpc_mask, QPC_RR_MAX); 5083 } 5084 5085 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 5086 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 5087 hr_reg_clear(qpc_mask, QPC_SR_MAX); 5088 } 5089 5090 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 5091 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 5092 5093 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 5094 hr_reg_write(context, QPC_MIN_RNR_TIME, 5095 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 5096 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 5097 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 5098 } 5099 5100 if (attr_mask & IB_QP_RQ_PSN) { 5101 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 5102 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 5103 5104 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 5105 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 5106 } 5107 5108 if (attr_mask & IB_QP_QKEY) { 5109 context->qkey_xrcd = cpu_to_le32(attr->qkey); 5110 qpc_mask->qkey_xrcd = 0; 5111 hr_qp->qkey = attr->qkey; 5112 } 5113 5114 return ret; 5115 } 5116 5117 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 5118 const struct ib_qp_attr *attr, 5119 int attr_mask) 5120 { 5121 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5122 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5123 5124 if (attr_mask & IB_QP_ACCESS_FLAGS) 5125 hr_qp->atomic_rd_en = attr->qp_access_flags; 5126 5127 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 5128 hr_qp->resp_depth = attr->max_dest_rd_atomic; 5129 if (attr_mask & IB_QP_PORT) { 5130 hr_qp->port = attr->port_num - 1; 5131 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 5132 } 5133 } 5134 5135 static void clear_qp(struct hns_roce_qp *hr_qp) 5136 { 5137 struct ib_qp *ibqp = &hr_qp->ibqp; 5138 5139 if (ibqp->send_cq) 5140 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 5141 hr_qp->qpn, NULL); 5142 5143 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 5144 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 5145 hr_qp->qpn, ibqp->srq ? 5146 to_hr_srq(ibqp->srq) : NULL); 5147 5148 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 5149 *hr_qp->rdb.db_record = 0; 5150 5151 hr_qp->rq.head = 0; 5152 hr_qp->rq.tail = 0; 5153 hr_qp->sq.head = 0; 5154 hr_qp->sq.tail = 0; 5155 hr_qp->next_sge = 0; 5156 } 5157 5158 static void v2_set_flushed_fields(struct ib_qp *ibqp, 5159 struct hns_roce_v2_qp_context *context, 5160 struct hns_roce_v2_qp_context *qpc_mask) 5161 { 5162 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5163 unsigned long sq_flag = 0; 5164 unsigned long rq_flag = 0; 5165 5166 if (ibqp->qp_type == IB_QPT_XRC_TGT) 5167 return; 5168 5169 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 5170 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 5171 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 5172 hr_qp->state = IB_QPS_ERR; 5173 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 5174 5175 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 5176 return; 5177 5178 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 5179 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5180 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5181 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5182 } 5183 5184 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5185 const struct ib_qp_attr *attr, 5186 int attr_mask, enum ib_qp_state cur_state, 5187 enum ib_qp_state new_state, struct ib_udata *udata) 5188 { 5189 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5190 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5191 struct hns_roce_v2_qp_context ctx[2]; 5192 struct hns_roce_v2_qp_context *context = ctx; 5193 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5194 struct ib_device *ibdev = &hr_dev->ib_dev; 5195 int ret; 5196 5197 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5198 return -EOPNOTSUPP; 5199 5200 /* 5201 * In v2 engine, software pass context and context mask to hardware 5202 * when modifying qp. If software need modify some fields in context, 5203 * we should set all bits of the relevant fields in context mask to 5204 * 0 at the same time, else set them to 0x1. 5205 */ 5206 memset(context, 0, hr_dev->caps.qpc_sz); 5207 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5208 5209 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5210 new_state, context, qpc_mask, udata); 5211 if (ret) 5212 goto out; 5213 5214 /* When QP state is err, SQ and RQ WQE should be flushed */ 5215 if (new_state == IB_QPS_ERR) 5216 v2_set_flushed_fields(ibqp, context, qpc_mask); 5217 5218 /* Configure the optional fields */ 5219 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5220 qpc_mask); 5221 if (ret) 5222 goto out; 5223 5224 hr_reg_write_bool(context, QPC_INV_CREDIT, 5225 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5226 ibqp->srq); 5227 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5228 5229 /* Every status migrate must change state */ 5230 hr_reg_write(context, QPC_QP_ST, new_state); 5231 hr_reg_clear(qpc_mask, QPC_QP_ST); 5232 5233 /* SW pass context to HW */ 5234 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5235 if (ret) { 5236 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5237 goto out; 5238 } 5239 5240 hr_qp->state = new_state; 5241 5242 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5243 5244 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5245 clear_qp(hr_qp); 5246 5247 out: 5248 return ret; 5249 } 5250 5251 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5252 { 5253 static const enum ib_qp_state map[] = { 5254 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5255 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5256 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5257 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5258 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5259 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5260 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5261 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5262 }; 5263 5264 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5265 } 5266 5267 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, 5268 void *buffer) 5269 { 5270 struct hns_roce_cmd_mailbox *mailbox; 5271 int ret; 5272 5273 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5274 if (IS_ERR(mailbox)) 5275 return PTR_ERR(mailbox); 5276 5277 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_QPC, 5278 qpn); 5279 if (ret) 5280 goto out; 5281 5282 memcpy(buffer, mailbox->buf, hr_dev->caps.qpc_sz); 5283 5284 out: 5285 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5286 return ret; 5287 } 5288 5289 static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, 5290 struct hns_roce_v2_qp_context *context) 5291 { 5292 u8 timeout; 5293 5294 timeout = (u8)hr_reg_read(context, QPC_AT); 5295 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 5296 timeout -= HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08; 5297 5298 return timeout; 5299 } 5300 5301 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5302 int qp_attr_mask, 5303 struct ib_qp_init_attr *qp_init_attr) 5304 { 5305 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5306 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5307 struct hns_roce_v2_qp_context context = {}; 5308 struct ib_device *ibdev = &hr_dev->ib_dev; 5309 int tmp_qp_state; 5310 int state; 5311 int ret; 5312 5313 memset(qp_attr, 0, sizeof(*qp_attr)); 5314 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5315 5316 mutex_lock(&hr_qp->mutex); 5317 5318 if (hr_qp->state == IB_QPS_RESET) { 5319 qp_attr->qp_state = IB_QPS_RESET; 5320 ret = 0; 5321 goto done; 5322 } 5323 5324 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp->qpn, &context); 5325 if (ret) { 5326 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5327 ret = -EINVAL; 5328 goto out; 5329 } 5330 5331 state = hr_reg_read(&context, QPC_QP_ST); 5332 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5333 if (tmp_qp_state == -1) { 5334 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5335 ret = -EINVAL; 5336 goto out; 5337 } 5338 hr_qp->state = (u8)tmp_qp_state; 5339 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5340 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5341 qp_attr->path_mig_state = IB_MIG_ARMED; 5342 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5343 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5344 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5345 5346 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5347 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5348 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5349 qp_attr->qp_access_flags = 5350 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5351 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5352 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5353 5354 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5355 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5356 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5357 struct ib_global_route *grh = 5358 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5359 5360 rdma_ah_set_sl(&qp_attr->ah_attr, 5361 hr_reg_read(&context, QPC_SL)); 5362 rdma_ah_set_port_num(&qp_attr->ah_attr, hr_qp->port + 1); 5363 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH); 5364 grh->flow_label = hr_reg_read(&context, QPC_FL); 5365 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5366 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5367 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5368 5369 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5370 } 5371 5372 qp_attr->port_num = hr_qp->port + 1; 5373 qp_attr->sq_draining = 0; 5374 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5375 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5376 5377 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5378 qp_attr->timeout = get_qp_timeout_attr(hr_dev, &context); 5379 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5380 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5381 5382 done: 5383 qp_attr->cur_qp_state = qp_attr->qp_state; 5384 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5385 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5386 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5387 5388 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5389 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5390 5391 qp_init_attr->qp_context = ibqp->qp_context; 5392 qp_init_attr->qp_type = ibqp->qp_type; 5393 qp_init_attr->recv_cq = ibqp->recv_cq; 5394 qp_init_attr->send_cq = ibqp->send_cq; 5395 qp_init_attr->srq = ibqp->srq; 5396 qp_init_attr->cap = qp_attr->cap; 5397 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5398 5399 out: 5400 mutex_unlock(&hr_qp->mutex); 5401 return ret; 5402 } 5403 5404 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5405 { 5406 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5407 hr_qp->ibqp.qp_type == IB_QPT_UD || 5408 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5409 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5410 hr_qp->state != IB_QPS_RESET); 5411 } 5412 5413 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5414 struct hns_roce_qp *hr_qp, 5415 struct ib_udata *udata) 5416 { 5417 struct ib_device *ibdev = &hr_dev->ib_dev; 5418 struct hns_roce_cq *send_cq, *recv_cq; 5419 unsigned long flags; 5420 int ret = 0; 5421 5422 if (modify_qp_is_ok(hr_qp)) { 5423 /* Modify qp to reset before destroying qp */ 5424 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5425 hr_qp->state, IB_QPS_RESET, udata); 5426 if (ret) 5427 ibdev_err(ibdev, 5428 "failed to modify QP to RST, ret = %d.\n", 5429 ret); 5430 } 5431 5432 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5433 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5434 5435 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5436 hns_roce_lock_cqs(send_cq, recv_cq); 5437 5438 if (!udata) { 5439 if (recv_cq) 5440 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5441 (hr_qp->ibqp.srq ? 5442 to_hr_srq(hr_qp->ibqp.srq) : 5443 NULL)); 5444 5445 if (send_cq && send_cq != recv_cq) 5446 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5447 } 5448 5449 hns_roce_qp_remove(hr_dev, hr_qp); 5450 5451 hns_roce_unlock_cqs(send_cq, recv_cq); 5452 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5453 5454 return ret; 5455 } 5456 5457 int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5458 { 5459 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5460 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5461 int ret; 5462 5463 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5464 if (ret) 5465 ibdev_err(&hr_dev->ib_dev, 5466 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5467 hr_qp->qpn, ret); 5468 5469 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5470 5471 return 0; 5472 } 5473 5474 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5475 struct hns_roce_qp *hr_qp) 5476 { 5477 struct ib_device *ibdev = &hr_dev->ib_dev; 5478 struct hns_roce_sccc_clr_done *resp; 5479 struct hns_roce_sccc_clr *clr; 5480 struct hns_roce_cmq_desc desc; 5481 int ret, i; 5482 5483 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5484 return 0; 5485 5486 mutex_lock(&hr_dev->qp_table.scc_mutex); 5487 5488 /* set scc ctx clear done flag */ 5489 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5490 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5491 if (ret) { 5492 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5493 goto out; 5494 } 5495 5496 /* clear scc context */ 5497 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5498 clr = (struct hns_roce_sccc_clr *)desc.data; 5499 clr->qpn = cpu_to_le32(hr_qp->qpn); 5500 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5501 if (ret) { 5502 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5503 goto out; 5504 } 5505 5506 /* query scc context clear is done or not */ 5507 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5508 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5509 hns_roce_cmq_setup_basic_desc(&desc, 5510 HNS_ROCE_OPC_QUERY_SCCC, true); 5511 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5512 if (ret) { 5513 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5514 ret); 5515 goto out; 5516 } 5517 5518 if (resp->clr_done) 5519 goto out; 5520 5521 msleep(20); 5522 } 5523 5524 ibdev_err(ibdev, "query SCC clr done flag overtime.\n"); 5525 ret = -ETIMEDOUT; 5526 5527 out: 5528 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5529 return ret; 5530 } 5531 5532 #define DMA_IDX_SHIFT 3 5533 #define DMA_WQE_SHIFT 3 5534 5535 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5536 struct hns_roce_srq_context *ctx) 5537 { 5538 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5539 struct ib_device *ibdev = srq->ibsrq.device; 5540 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5541 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5542 dma_addr_t dma_handle_idx = 0; 5543 int ret; 5544 5545 /* Get physical address of idx que buf */ 5546 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5547 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5548 if (ret < 1) { 5549 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5550 ret); 5551 return -ENOBUFS; 5552 } 5553 5554 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5555 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5556 5557 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5558 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5559 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5560 5561 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5562 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5563 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5564 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5565 5566 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5567 to_hr_hw_page_addr(mtts_idx[0])); 5568 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5569 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5570 5571 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5572 to_hr_hw_page_addr(mtts_idx[1])); 5573 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5574 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5575 5576 return 0; 5577 } 5578 5579 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5580 { 5581 struct ib_device *ibdev = srq->ibsrq.device; 5582 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5583 struct hns_roce_srq_context *ctx = mb_buf; 5584 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5585 dma_addr_t dma_handle_wqe = 0; 5586 int ret; 5587 5588 memset(ctx, 0, sizeof(*ctx)); 5589 5590 /* Get the physical address of srq buf */ 5591 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5592 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5593 if (ret < 1) { 5594 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5595 ret); 5596 return -ENOBUFS; 5597 } 5598 5599 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5600 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5601 srq->ibsrq.srq_type == IB_SRQT_XRC); 5602 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5603 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5604 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5605 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5606 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5607 hr_reg_write(ctx, SRQC_RQWS, 5608 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5609 5610 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5611 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5612 srq->wqe_cnt)); 5613 5614 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5615 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5616 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5617 5618 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5619 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5620 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5621 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5622 5623 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5624 } 5625 5626 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5627 struct ib_srq_attr *srq_attr, 5628 enum ib_srq_attr_mask srq_attr_mask, 5629 struct ib_udata *udata) 5630 { 5631 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5632 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5633 struct hns_roce_srq_context *srq_context; 5634 struct hns_roce_srq_context *srqc_mask; 5635 struct hns_roce_cmd_mailbox *mailbox; 5636 int ret; 5637 5638 /* Resizing SRQs is not supported yet */ 5639 if (srq_attr_mask & IB_SRQ_MAX_WR) 5640 return -EINVAL; 5641 5642 if (srq_attr_mask & IB_SRQ_LIMIT) { 5643 if (srq_attr->srq_limit > srq->wqe_cnt) 5644 return -EINVAL; 5645 5646 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5647 if (IS_ERR(mailbox)) 5648 return PTR_ERR(mailbox); 5649 5650 srq_context = mailbox->buf; 5651 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5652 5653 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5654 5655 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5656 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5657 5658 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5659 HNS_ROCE_CMD_MODIFY_SRQC, srq->srqn); 5660 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5661 if (ret) { 5662 ibdev_err(&hr_dev->ib_dev, 5663 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5664 ret); 5665 return ret; 5666 } 5667 } 5668 5669 return 0; 5670 } 5671 5672 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5673 { 5674 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5675 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5676 struct hns_roce_srq_context *srq_context; 5677 struct hns_roce_cmd_mailbox *mailbox; 5678 int ret; 5679 5680 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5681 if (IS_ERR(mailbox)) 5682 return PTR_ERR(mailbox); 5683 5684 srq_context = mailbox->buf; 5685 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5686 HNS_ROCE_CMD_QUERY_SRQC, srq->srqn); 5687 if (ret) { 5688 ibdev_err(&hr_dev->ib_dev, 5689 "failed to process cmd of querying SRQ, ret = %d.\n", 5690 ret); 5691 goto out; 5692 } 5693 5694 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5695 attr->max_wr = srq->wqe_cnt; 5696 attr->max_sge = srq->max_gs - srq->rsv_sge; 5697 5698 out: 5699 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5700 return ret; 5701 } 5702 5703 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5704 { 5705 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5706 struct hns_roce_v2_cq_context *cq_context; 5707 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5708 struct hns_roce_v2_cq_context *cqc_mask; 5709 struct hns_roce_cmd_mailbox *mailbox; 5710 int ret; 5711 5712 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5713 if (IS_ERR(mailbox)) 5714 return PTR_ERR(mailbox); 5715 5716 cq_context = mailbox->buf; 5717 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5718 5719 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5720 5721 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5722 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5723 5724 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5725 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5726 dev_info(hr_dev->dev, 5727 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5728 cq_period); 5729 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5730 } 5731 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5732 } 5733 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5734 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5735 5736 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, 5737 HNS_ROCE_CMD_MODIFY_CQC, hr_cq->cqn); 5738 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5739 if (ret) 5740 ibdev_err(&hr_dev->ib_dev, 5741 "failed to process cmd when modifying CQ, ret = %d.\n", 5742 ret); 5743 5744 return ret; 5745 } 5746 5747 static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, 5748 void *buffer) 5749 { 5750 struct hns_roce_v2_cq_context *context; 5751 struct hns_roce_cmd_mailbox *mailbox; 5752 int ret; 5753 5754 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5755 if (IS_ERR(mailbox)) 5756 return PTR_ERR(mailbox); 5757 5758 context = mailbox->buf; 5759 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, 5760 HNS_ROCE_CMD_QUERY_CQC, cqn); 5761 if (ret) { 5762 ibdev_err(&hr_dev->ib_dev, 5763 "failed to process cmd when querying CQ, ret = %d.\n", 5764 ret); 5765 goto err_mailbox; 5766 } 5767 5768 memcpy(buffer, context, sizeof(*context)); 5769 5770 err_mailbox: 5771 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5772 5773 return ret; 5774 } 5775 5776 static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, 5777 void *buffer) 5778 { 5779 struct hns_roce_v2_mpt_entry *context; 5780 struct hns_roce_cmd_mailbox *mailbox; 5781 int ret; 5782 5783 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5784 if (IS_ERR(mailbox)) 5785 return PTR_ERR(mailbox); 5786 5787 context = mailbox->buf; 5788 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, HNS_ROCE_CMD_QUERY_MPT, 5789 key_to_hw_index(key)); 5790 if (ret) { 5791 ibdev_err(&hr_dev->ib_dev, 5792 "failed to process cmd when querying MPT, ret = %d.\n", 5793 ret); 5794 goto err_mailbox; 5795 } 5796 5797 memcpy(buffer, context, sizeof(*context)); 5798 5799 err_mailbox: 5800 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5801 5802 return ret; 5803 } 5804 5805 static void hns_roce_irq_work_handle(struct work_struct *work) 5806 { 5807 struct hns_roce_work *irq_work = 5808 container_of(work, struct hns_roce_work, work); 5809 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5810 5811 switch (irq_work->event_type) { 5812 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5813 ibdev_info(ibdev, "path migrated succeeded.\n"); 5814 break; 5815 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5816 ibdev_warn(ibdev, "path migration failed.\n"); 5817 break; 5818 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5819 break; 5820 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5821 ibdev_warn(ibdev, "send queue drained.\n"); 5822 break; 5823 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5824 ibdev_err(ibdev, "local work queue 0x%x catast error, sub_event type is: %d\n", 5825 irq_work->queue_num, irq_work->sub_type); 5826 break; 5827 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5828 ibdev_err(ibdev, "invalid request local work queue 0x%x error.\n", 5829 irq_work->queue_num); 5830 break; 5831 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5832 ibdev_err(ibdev, "local access violation work queue 0x%x error, sub_event type is: %d\n", 5833 irq_work->queue_num, irq_work->sub_type); 5834 break; 5835 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5836 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5837 break; 5838 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5839 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5840 break; 5841 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5842 ibdev_err(ibdev, "SRQ catas error.\n"); 5843 break; 5844 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5845 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5846 break; 5847 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5848 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5849 break; 5850 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5851 ibdev_warn(ibdev, "DB overflow.\n"); 5852 break; 5853 case HNS_ROCE_EVENT_TYPE_FLR: 5854 ibdev_warn(ibdev, "function level reset.\n"); 5855 break; 5856 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5857 ibdev_err(ibdev, "xrc domain violation error.\n"); 5858 break; 5859 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5860 ibdev_err(ibdev, "invalid xrceth error.\n"); 5861 break; 5862 default: 5863 break; 5864 } 5865 5866 kfree(irq_work); 5867 } 5868 5869 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5870 struct hns_roce_eq *eq, u32 queue_num) 5871 { 5872 struct hns_roce_work *irq_work; 5873 5874 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5875 if (!irq_work) 5876 return; 5877 5878 INIT_WORK(&irq_work->work, hns_roce_irq_work_handle); 5879 irq_work->hr_dev = hr_dev; 5880 irq_work->event_type = eq->event_type; 5881 irq_work->sub_type = eq->sub_type; 5882 irq_work->queue_num = queue_num; 5883 queue_work(hr_dev->irq_workq, &irq_work->work); 5884 } 5885 5886 static void update_eq_db(struct hns_roce_eq *eq) 5887 { 5888 struct hns_roce_dev *hr_dev = eq->hr_dev; 5889 struct hns_roce_v2_db eq_db = {}; 5890 5891 if (eq->type_flag == HNS_ROCE_AEQ) { 5892 hr_reg_write(&eq_db, EQ_DB_CMD, 5893 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5894 HNS_ROCE_EQ_DB_CMD_AEQ : 5895 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5896 } else { 5897 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5898 5899 hr_reg_write(&eq_db, EQ_DB_CMD, 5900 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5901 HNS_ROCE_EQ_DB_CMD_CEQ : 5902 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5903 } 5904 5905 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5906 5907 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5908 } 5909 5910 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5911 { 5912 struct hns_roce_aeqe *aeqe; 5913 5914 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5915 (eq->cons_index & (eq->entries - 1)) * 5916 eq->eqe_size); 5917 5918 return (hr_reg_read(aeqe, AEQE_OWNER) ^ 5919 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5920 } 5921 5922 static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5923 struct hns_roce_eq *eq) 5924 { 5925 struct device *dev = hr_dev->dev; 5926 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5927 irqreturn_t aeqe_found = IRQ_NONE; 5928 int event_type; 5929 u32 queue_num; 5930 int sub_type; 5931 5932 while (aeqe) { 5933 /* Make sure we read AEQ entry after we have checked the 5934 * ownership bit 5935 */ 5936 dma_rmb(); 5937 5938 event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE); 5939 sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE); 5940 queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM); 5941 5942 switch (event_type) { 5943 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5944 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5945 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5946 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5947 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5948 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5949 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5950 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5951 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5952 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5953 hns_roce_qp_event(hr_dev, queue_num, event_type); 5954 break; 5955 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5956 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5957 hns_roce_srq_event(hr_dev, queue_num, event_type); 5958 break; 5959 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5960 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5961 hns_roce_cq_event(hr_dev, queue_num, event_type); 5962 break; 5963 case HNS_ROCE_EVENT_TYPE_MB: 5964 hns_roce_cmd_event(hr_dev, 5965 le16_to_cpu(aeqe->event.cmd.token), 5966 aeqe->event.cmd.status, 5967 le64_to_cpu(aeqe->event.cmd.out_param)); 5968 break; 5969 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5970 case HNS_ROCE_EVENT_TYPE_FLR: 5971 break; 5972 default: 5973 dev_err(dev, "unhandled event %d on EQ %d at idx %u.\n", 5974 event_type, eq->eqn, eq->cons_index); 5975 break; 5976 } 5977 5978 eq->event_type = event_type; 5979 eq->sub_type = sub_type; 5980 ++eq->cons_index; 5981 aeqe_found = IRQ_HANDLED; 5982 5983 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5984 5985 aeqe = next_aeqe_sw_v2(eq); 5986 } 5987 5988 update_eq_db(eq); 5989 5990 return IRQ_RETVAL(aeqe_found); 5991 } 5992 5993 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5994 { 5995 struct hns_roce_ceqe *ceqe; 5996 5997 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5998 (eq->cons_index & (eq->entries - 1)) * 5999 eq->eqe_size); 6000 6001 return (hr_reg_read(ceqe, CEQE_OWNER) ^ 6002 !!(eq->cons_index & eq->entries)) ? ceqe : NULL; 6003 } 6004 6005 static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 6006 struct hns_roce_eq *eq) 6007 { 6008 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 6009 irqreturn_t ceqe_found = IRQ_NONE; 6010 u32 cqn; 6011 6012 while (ceqe) { 6013 /* Make sure we read CEQ entry after we have checked the 6014 * ownership bit 6015 */ 6016 dma_rmb(); 6017 6018 cqn = hr_reg_read(ceqe, CEQE_CQN); 6019 6020 hns_roce_cq_completion(hr_dev, cqn); 6021 6022 ++eq->cons_index; 6023 ceqe_found = IRQ_HANDLED; 6024 6025 ceqe = next_ceqe_sw_v2(eq); 6026 } 6027 6028 update_eq_db(eq); 6029 6030 return IRQ_RETVAL(ceqe_found); 6031 } 6032 6033 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 6034 { 6035 struct hns_roce_eq *eq = eq_ptr; 6036 struct hns_roce_dev *hr_dev = eq->hr_dev; 6037 irqreturn_t int_work; 6038 6039 if (eq->type_flag == HNS_ROCE_CEQ) 6040 /* Completion event interrupt */ 6041 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 6042 else 6043 /* Asynchronous event interrupt */ 6044 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 6045 6046 return IRQ_RETVAL(int_work); 6047 } 6048 6049 static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, 6050 u32 int_st) 6051 { 6052 struct pci_dev *pdev = hr_dev->pci_dev; 6053 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 6054 const struct hnae3_ae_ops *ops = ae_dev->ops; 6055 irqreturn_t int_work = IRQ_NONE; 6056 u32 int_en; 6057 6058 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 6059 6060 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 6061 dev_err(hr_dev->dev, "AEQ overflow!\n"); 6062 6063 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, 6064 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S); 6065 6066 /* Set reset level for reset_event() */ 6067 if (ops->set_default_reset_request) 6068 ops->set_default_reset_request(ae_dev, 6069 HNAE3_FUNC_RESET); 6070 if (ops->reset_event) 6071 ops->reset_event(pdev, NULL); 6072 6073 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 6074 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 6075 6076 int_work = IRQ_HANDLED; 6077 } else { 6078 dev_err(hr_dev->dev, "there is no basic abn irq found.\n"); 6079 } 6080 6081 return IRQ_RETVAL(int_work); 6082 } 6083 6084 static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, 6085 struct fmea_ram_ecc *ecc_info) 6086 { 6087 struct hns_roce_cmq_desc desc; 6088 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6089 int ret; 6090 6091 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_QUERY_RAM_ECC, true); 6092 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6093 if (ret) 6094 return ret; 6095 6096 ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR); 6097 ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE); 6098 ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG); 6099 6100 return 0; 6101 } 6102 6103 static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) 6104 { 6105 struct hns_roce_cmq_desc desc; 6106 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 6107 u32 addr_upper; 6108 u32 addr_low; 6109 int ret; 6110 6111 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, true); 6112 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6113 6114 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 6115 if (ret) { 6116 dev_err(hr_dev->dev, 6117 "failed to execute cmd to read gmv, ret = %d.\n", ret); 6118 return ret; 6119 } 6120 6121 addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L); 6122 addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H); 6123 6124 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 6125 hr_reg_write(req, CFG_GMV_BT_BA_L, addr_low); 6126 hr_reg_write(req, CFG_GMV_BT_BA_H, addr_upper); 6127 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 6128 6129 return hns_roce_cmq_send(hr_dev, &desc, 1); 6130 } 6131 6132 static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) 6133 { 6134 if (res_type == ECC_RESOURCE_QPC_TIMER || 6135 res_type == ECC_RESOURCE_CQC_TIMER || 6136 res_type == ECC_RESOURCE_SCCC) 6137 return le64_to_cpu(*data); 6138 6139 return le64_to_cpu(*data) << PAGE_SHIFT; 6140 } 6141 6142 static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, 6143 u32 index) 6144 { 6145 u8 write_bt0_op = fmea_ram_res[res_type].write_bt0_op; 6146 u8 read_bt0_op = fmea_ram_res[res_type].read_bt0_op; 6147 struct hns_roce_cmd_mailbox *mailbox; 6148 u64 addr; 6149 int ret; 6150 6151 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6152 if (IS_ERR(mailbox)) 6153 return PTR_ERR(mailbox); 6154 6155 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, read_bt0_op, index); 6156 if (ret) { 6157 dev_err(hr_dev->dev, 6158 "failed to execute cmd to read fmea ram, ret = %d.\n", 6159 ret); 6160 goto out; 6161 } 6162 6163 addr = fmea_get_ram_res_addr(res_type, mailbox->buf); 6164 6165 ret = hns_roce_cmd_mbox(hr_dev, addr, 0, write_bt0_op, index); 6166 if (ret) 6167 dev_err(hr_dev->dev, 6168 "failed to execute cmd to write fmea ram, ret = %d.\n", 6169 ret); 6170 6171 out: 6172 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6173 return ret; 6174 } 6175 6176 static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, 6177 struct fmea_ram_ecc *ecc_info) 6178 { 6179 u32 res_type = ecc_info->res_type; 6180 u32 index = ecc_info->index; 6181 int ret; 6182 6183 BUILD_BUG_ON(ARRAY_SIZE(fmea_ram_res) != ECC_RESOURCE_COUNT); 6184 6185 if (res_type >= ECC_RESOURCE_COUNT) { 6186 dev_err(hr_dev->dev, "unsupported fmea ram ecc type %u.\n", 6187 res_type); 6188 return; 6189 } 6190 6191 if (res_type == ECC_RESOURCE_GMV) 6192 ret = fmea_recover_gmv(hr_dev, index); 6193 else 6194 ret = fmea_recover_others(hr_dev, res_type, index); 6195 if (ret) 6196 dev_err(hr_dev->dev, 6197 "failed to recover %s, index = %u, ret = %d.\n", 6198 fmea_ram_res[res_type].name, index, ret); 6199 } 6200 6201 static void fmea_ram_ecc_work(struct work_struct *ecc_work) 6202 { 6203 struct hns_roce_dev *hr_dev = 6204 container_of(ecc_work, struct hns_roce_dev, ecc_work); 6205 struct fmea_ram_ecc ecc_info = {}; 6206 6207 if (fmea_ram_ecc_query(hr_dev, &ecc_info)) { 6208 dev_err(hr_dev->dev, "failed to query fmea ram ecc.\n"); 6209 return; 6210 } 6211 6212 if (!ecc_info.is_ecc_err) { 6213 dev_err(hr_dev->dev, "there is no fmea ram ecc err found.\n"); 6214 return; 6215 } 6216 6217 fmea_ram_ecc_recover(hr_dev, &ecc_info); 6218 } 6219 6220 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 6221 { 6222 struct hns_roce_dev *hr_dev = dev_id; 6223 irqreturn_t int_work = IRQ_NONE; 6224 u32 int_st; 6225 6226 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 6227 6228 if (int_st) { 6229 int_work = abnormal_interrupt_basic(hr_dev, int_st); 6230 } else if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 6231 queue_work(hr_dev->irq_workq, &hr_dev->ecc_work); 6232 int_work = IRQ_HANDLED; 6233 } else { 6234 dev_err(hr_dev->dev, "there is no abnormal irq found.\n"); 6235 } 6236 6237 return IRQ_RETVAL(int_work); 6238 } 6239 6240 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 6241 int eq_num, u32 enable_flag) 6242 { 6243 int i; 6244 6245 for (i = 0; i < eq_num; i++) 6246 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 6247 i * EQ_REG_OFFSET, enable_flag); 6248 6249 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 6250 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 6251 } 6252 6253 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 6254 { 6255 struct device *dev = hr_dev->dev; 6256 int ret; 6257 u8 cmd; 6258 6259 if (eqn < hr_dev->caps.num_comp_vectors) 6260 cmd = HNS_ROCE_CMD_DESTROY_CEQC; 6261 else 6262 cmd = HNS_ROCE_CMD_DESTROY_AEQC; 6263 6264 ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M); 6265 if (ret) 6266 dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn); 6267 } 6268 6269 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6270 { 6271 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 6272 } 6273 6274 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6275 { 6276 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 6277 eq->cons_index = 0; 6278 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 6279 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 6280 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 6281 eq->shift = ilog2((unsigned int)eq->entries); 6282 } 6283 6284 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 6285 void *mb_buf) 6286 { 6287 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 6288 struct hns_roce_eq_context *eqc; 6289 u64 bt_ba = 0; 6290 int count; 6291 6292 eqc = mb_buf; 6293 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 6294 6295 init_eq_config(hr_dev, eq); 6296 6297 /* if not multi-hop, eqe buffer only use one trunk */ 6298 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 6299 &bt_ba); 6300 if (count < 1) { 6301 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 6302 return -ENOBUFS; 6303 } 6304 6305 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 6306 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 6307 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 6308 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 6309 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 6310 hr_reg_write(eqc, EQC_EQN, eq->eqn); 6311 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 6312 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 6313 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 6314 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 6315 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 6316 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 6317 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 6318 6319 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6320 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 6321 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 6322 eq->eq_period); 6323 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 6324 } 6325 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 6326 } 6327 6328 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 6329 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 6330 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 6331 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 6332 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 6333 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 6334 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 6335 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 6336 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 6337 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 6338 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 6339 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 6340 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 6341 6342 return 0; 6343 } 6344 6345 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 6346 { 6347 struct hns_roce_buf_attr buf_attr = {}; 6348 int err; 6349 6350 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 6351 eq->hop_num = 0; 6352 else 6353 eq->hop_num = hr_dev->caps.eqe_hop_num; 6354 6355 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 6356 buf_attr.region[0].size = eq->entries * eq->eqe_size; 6357 buf_attr.region[0].hopnum = eq->hop_num; 6358 buf_attr.region_count = 1; 6359 6360 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 6361 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 6362 0); 6363 if (err) 6364 dev_err(hr_dev->dev, "failed to alloc EQE mtr, err %d\n", err); 6365 6366 return err; 6367 } 6368 6369 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 6370 struct hns_roce_eq *eq, u8 eq_cmd) 6371 { 6372 struct hns_roce_cmd_mailbox *mailbox; 6373 int ret; 6374 6375 /* Allocate mailbox memory */ 6376 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 6377 if (IS_ERR(mailbox)) 6378 return PTR_ERR(mailbox); 6379 6380 ret = alloc_eq_buf(hr_dev, eq); 6381 if (ret) 6382 goto free_cmd_mbox; 6383 6384 ret = config_eqc(hr_dev, eq, mailbox->buf); 6385 if (ret) 6386 goto err_cmd_mbox; 6387 6388 ret = hns_roce_create_hw_ctx(hr_dev, mailbox, eq_cmd, eq->eqn); 6389 if (ret) { 6390 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6391 goto err_cmd_mbox; 6392 } 6393 6394 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6395 6396 return 0; 6397 6398 err_cmd_mbox: 6399 free_eq_buf(hr_dev, eq); 6400 6401 free_cmd_mbox: 6402 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6403 6404 return ret; 6405 } 6406 6407 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6408 int comp_num, int aeq_num, int other_num) 6409 { 6410 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6411 int i, j; 6412 int ret; 6413 6414 for (i = 0; i < irq_num; i++) { 6415 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6416 GFP_KERNEL); 6417 if (!hr_dev->irq_names[i]) { 6418 ret = -ENOMEM; 6419 goto err_kzalloc_failed; 6420 } 6421 } 6422 6423 /* irq contains: abnormal + AEQ + CEQ */ 6424 for (j = 0; j < other_num; j++) 6425 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6426 "hns-abn-%d", j); 6427 6428 for (j = other_num; j < (other_num + aeq_num); j++) 6429 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6430 "hns-aeq-%d", j - other_num); 6431 6432 for (j = (other_num + aeq_num); j < irq_num; j++) 6433 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6434 "hns-ceq-%d", j - other_num - aeq_num); 6435 6436 for (j = 0; j < irq_num; j++) { 6437 if (j < other_num) 6438 ret = request_irq(hr_dev->irq[j], 6439 hns_roce_v2_msix_interrupt_abn, 6440 0, hr_dev->irq_names[j], hr_dev); 6441 6442 else if (j < (other_num + comp_num)) 6443 ret = request_irq(eq_table->eq[j - other_num].irq, 6444 hns_roce_v2_msix_interrupt_eq, 6445 0, hr_dev->irq_names[j + aeq_num], 6446 &eq_table->eq[j - other_num]); 6447 else 6448 ret = request_irq(eq_table->eq[j - other_num].irq, 6449 hns_roce_v2_msix_interrupt_eq, 6450 0, hr_dev->irq_names[j - comp_num], 6451 &eq_table->eq[j - other_num]); 6452 if (ret) { 6453 dev_err(hr_dev->dev, "request irq error!\n"); 6454 goto err_request_failed; 6455 } 6456 } 6457 6458 return 0; 6459 6460 err_request_failed: 6461 for (j -= 1; j >= 0; j--) 6462 if (j < other_num) 6463 free_irq(hr_dev->irq[j], hr_dev); 6464 else 6465 free_irq(eq_table->eq[j - other_num].irq, 6466 &eq_table->eq[j - other_num]); 6467 6468 err_kzalloc_failed: 6469 for (i -= 1; i >= 0; i--) 6470 kfree(hr_dev->irq_names[i]); 6471 6472 return ret; 6473 } 6474 6475 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6476 { 6477 int irq_num; 6478 int eq_num; 6479 int i; 6480 6481 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6482 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6483 6484 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6485 free_irq(hr_dev->irq[i], hr_dev); 6486 6487 for (i = 0; i < eq_num; i++) 6488 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6489 6490 for (i = 0; i < irq_num; i++) 6491 kfree(hr_dev->irq_names[i]); 6492 } 6493 6494 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6495 { 6496 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6497 struct device *dev = hr_dev->dev; 6498 struct hns_roce_eq *eq; 6499 int other_num; 6500 int comp_num; 6501 int aeq_num; 6502 int irq_num; 6503 int eq_num; 6504 u8 eq_cmd; 6505 int ret; 6506 int i; 6507 6508 other_num = hr_dev->caps.num_other_vectors; 6509 comp_num = hr_dev->caps.num_comp_vectors; 6510 aeq_num = hr_dev->caps.num_aeq_vectors; 6511 6512 eq_num = comp_num + aeq_num; 6513 irq_num = eq_num + other_num; 6514 6515 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6516 if (!eq_table->eq) 6517 return -ENOMEM; 6518 6519 /* create eq */ 6520 for (i = 0; i < eq_num; i++) { 6521 eq = &eq_table->eq[i]; 6522 eq->hr_dev = hr_dev; 6523 eq->eqn = i; 6524 if (i < comp_num) { 6525 /* CEQ */ 6526 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6527 eq->type_flag = HNS_ROCE_CEQ; 6528 eq->entries = hr_dev->caps.ceqe_depth; 6529 eq->eqe_size = hr_dev->caps.ceqe_size; 6530 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6531 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6532 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6533 } else { 6534 /* AEQ */ 6535 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6536 eq->type_flag = HNS_ROCE_AEQ; 6537 eq->entries = hr_dev->caps.aeqe_depth; 6538 eq->eqe_size = hr_dev->caps.aeqe_size; 6539 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6540 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6541 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6542 } 6543 6544 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6545 if (ret) { 6546 dev_err(dev, "failed to create eq.\n"); 6547 goto err_create_eq_fail; 6548 } 6549 } 6550 6551 INIT_WORK(&hr_dev->ecc_work, fmea_ram_ecc_work); 6552 6553 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6554 if (!hr_dev->irq_workq) { 6555 dev_err(dev, "failed to create irq workqueue.\n"); 6556 ret = -ENOMEM; 6557 goto err_create_eq_fail; 6558 } 6559 6560 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6561 other_num); 6562 if (ret) { 6563 dev_err(dev, "failed to request irq.\n"); 6564 goto err_request_irq_fail; 6565 } 6566 6567 /* enable irq */ 6568 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6569 6570 return 0; 6571 6572 err_request_irq_fail: 6573 destroy_workqueue(hr_dev->irq_workq); 6574 6575 err_create_eq_fail: 6576 for (i -= 1; i >= 0; i--) 6577 free_eq_buf(hr_dev, &eq_table->eq[i]); 6578 kfree(eq_table->eq); 6579 6580 return ret; 6581 } 6582 6583 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6584 { 6585 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6586 int eq_num; 6587 int i; 6588 6589 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6590 6591 /* Disable irq */ 6592 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6593 6594 __hns_roce_free_irq(hr_dev); 6595 destroy_workqueue(hr_dev->irq_workq); 6596 6597 for (i = 0; i < eq_num; i++) { 6598 hns_roce_v2_destroy_eqc(hr_dev, i); 6599 6600 free_eq_buf(hr_dev, &eq_table->eq[i]); 6601 } 6602 6603 kfree(eq_table->eq); 6604 } 6605 6606 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6607 .destroy_qp = hns_roce_v2_destroy_qp, 6608 .modify_cq = hns_roce_v2_modify_cq, 6609 .poll_cq = hns_roce_v2_poll_cq, 6610 .post_recv = hns_roce_v2_post_recv, 6611 .post_send = hns_roce_v2_post_send, 6612 .query_qp = hns_roce_v2_query_qp, 6613 .req_notify_cq = hns_roce_v2_req_notify_cq, 6614 }; 6615 6616 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6617 .modify_srq = hns_roce_v2_modify_srq, 6618 .post_srq_recv = hns_roce_v2_post_srq_recv, 6619 .query_srq = hns_roce_v2_query_srq, 6620 }; 6621 6622 static const struct hns_roce_hw hns_roce_hw_v2 = { 6623 .cmq_init = hns_roce_v2_cmq_init, 6624 .cmq_exit = hns_roce_v2_cmq_exit, 6625 .hw_profile = hns_roce_v2_profile, 6626 .hw_init = hns_roce_v2_init, 6627 .hw_exit = hns_roce_v2_exit, 6628 .post_mbox = v2_post_mbox, 6629 .poll_mbox_done = v2_poll_mbox_done, 6630 .chk_mbox_avail = v2_chk_mbox_is_avail, 6631 .set_gid = hns_roce_v2_set_gid, 6632 .set_mac = hns_roce_v2_set_mac, 6633 .write_mtpt = hns_roce_v2_write_mtpt, 6634 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6635 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6636 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6637 .write_cqc = hns_roce_v2_write_cqc, 6638 .set_hem = hns_roce_v2_set_hem, 6639 .clear_hem = hns_roce_v2_clear_hem, 6640 .modify_qp = hns_roce_v2_modify_qp, 6641 .dereg_mr = hns_roce_v2_dereg_mr, 6642 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6643 .init_eq = hns_roce_v2_init_eq_table, 6644 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6645 .write_srqc = hns_roce_v2_write_srqc, 6646 .query_cqc = hns_roce_v2_query_cqc, 6647 .query_qpc = hns_roce_v2_query_qpc, 6648 .query_mpt = hns_roce_v2_query_mpt, 6649 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6650 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6651 }; 6652 6653 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6654 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6655 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6656 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6657 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6658 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6659 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6660 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6661 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6662 /* required last entry */ 6663 {0, } 6664 }; 6665 6666 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6667 6668 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6669 struct hnae3_handle *handle) 6670 { 6671 struct hns_roce_v2_priv *priv = hr_dev->priv; 6672 const struct pci_device_id *id; 6673 int i; 6674 6675 hr_dev->pci_dev = handle->pdev; 6676 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6677 hr_dev->is_vf = id->driver_data; 6678 hr_dev->dev = &handle->pdev->dev; 6679 hr_dev->hw = &hns_roce_hw_v2; 6680 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6681 hr_dev->odb_offset = hr_dev->sdb_offset; 6682 6683 /* Get info from NIC driver. */ 6684 hr_dev->reg_base = handle->rinfo.roce_io_base; 6685 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6686 hr_dev->caps.num_ports = 1; 6687 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6688 hr_dev->iboe.phy_port[0] = 0; 6689 6690 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6691 hr_dev->iboe.netdevs[0]->dev_addr); 6692 6693 for (i = 0; i < handle->rinfo.num_vectors; i++) 6694 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6695 i + handle->rinfo.base_vector); 6696 6697 /* cmd issue mode: 0 is poll, 1 is event */ 6698 hr_dev->cmd_mod = 1; 6699 hr_dev->loop_idc = 0; 6700 6701 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6702 priv->handle = handle; 6703 } 6704 6705 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6706 { 6707 struct hns_roce_dev *hr_dev; 6708 int ret; 6709 6710 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6711 if (!hr_dev) 6712 return -ENOMEM; 6713 6714 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6715 if (!hr_dev->priv) { 6716 ret = -ENOMEM; 6717 goto error_failed_kzalloc; 6718 } 6719 6720 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6721 6722 ret = hns_roce_init(hr_dev); 6723 if (ret) { 6724 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6725 goto error_failed_cfg; 6726 } 6727 6728 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 6729 ret = free_mr_init(hr_dev); 6730 if (ret) { 6731 dev_err(hr_dev->dev, "failed to init free mr!\n"); 6732 goto error_failed_roce_init; 6733 } 6734 } 6735 6736 handle->priv = hr_dev; 6737 6738 return 0; 6739 6740 error_failed_roce_init: 6741 hns_roce_exit(hr_dev); 6742 6743 error_failed_cfg: 6744 kfree(hr_dev->priv); 6745 6746 error_failed_kzalloc: 6747 ib_dealloc_device(&hr_dev->ib_dev); 6748 6749 return ret; 6750 } 6751 6752 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6753 bool reset) 6754 { 6755 struct hns_roce_dev *hr_dev = handle->priv; 6756 6757 if (!hr_dev) 6758 return; 6759 6760 handle->priv = NULL; 6761 6762 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6763 hns_roce_handle_device_err(hr_dev); 6764 6765 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 6766 free_mr_exit(hr_dev); 6767 6768 hns_roce_exit(hr_dev); 6769 kfree(hr_dev->priv); 6770 ib_dealloc_device(&hr_dev->ib_dev); 6771 } 6772 6773 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6774 { 6775 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6776 const struct pci_device_id *id; 6777 struct device *dev = &handle->pdev->dev; 6778 int ret; 6779 6780 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6781 6782 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6783 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6784 goto reset_chk_err; 6785 } 6786 6787 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6788 if (!id) 6789 return 0; 6790 6791 if (id->driver_data && handle->pdev->revision == PCI_REVISION_ID_HIP08) 6792 return 0; 6793 6794 ret = __hns_roce_hw_v2_init_instance(handle); 6795 if (ret) { 6796 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6797 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6798 if (ops->ae_dev_resetting(handle) || 6799 ops->get_hw_reset_stat(handle)) 6800 goto reset_chk_err; 6801 else 6802 return ret; 6803 } 6804 6805 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6806 6807 return 0; 6808 6809 reset_chk_err: 6810 dev_err(dev, "Device is busy in resetting state.\n" 6811 "please retry later.\n"); 6812 6813 return -EBUSY; 6814 } 6815 6816 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6817 bool reset) 6818 { 6819 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6820 return; 6821 6822 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6823 6824 __hns_roce_hw_v2_uninit_instance(handle, reset); 6825 6826 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6827 } 6828 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6829 { 6830 struct hns_roce_dev *hr_dev; 6831 6832 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6833 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6834 return 0; 6835 } 6836 6837 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6838 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6839 6840 hr_dev = handle->priv; 6841 if (!hr_dev) 6842 return 0; 6843 6844 hr_dev->active = false; 6845 hr_dev->dis_db = true; 6846 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6847 6848 return 0; 6849 } 6850 6851 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6852 { 6853 struct device *dev = &handle->pdev->dev; 6854 int ret; 6855 6856 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6857 &handle->rinfo.state)) { 6858 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6859 return 0; 6860 } 6861 6862 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6863 6864 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6865 ret = __hns_roce_hw_v2_init_instance(handle); 6866 if (ret) { 6867 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6868 * callback function, RoCE Engine reinitialize. If RoCE reinit 6869 * failed, we should inform NIC driver. 6870 */ 6871 handle->priv = NULL; 6872 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6873 } else { 6874 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6875 dev_info(dev, "reset done, RoCE client reinit finished.\n"); 6876 } 6877 6878 return ret; 6879 } 6880 6881 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6882 { 6883 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6884 return 0; 6885 6886 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6887 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6888 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6889 __hns_roce_hw_v2_uninit_instance(handle, false); 6890 6891 return 0; 6892 } 6893 6894 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6895 enum hnae3_reset_notify_type type) 6896 { 6897 int ret = 0; 6898 6899 switch (type) { 6900 case HNAE3_DOWN_CLIENT: 6901 ret = hns_roce_hw_v2_reset_notify_down(handle); 6902 break; 6903 case HNAE3_INIT_CLIENT: 6904 ret = hns_roce_hw_v2_reset_notify_init(handle); 6905 break; 6906 case HNAE3_UNINIT_CLIENT: 6907 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6908 break; 6909 default: 6910 break; 6911 } 6912 6913 return ret; 6914 } 6915 6916 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6917 .init_instance = hns_roce_hw_v2_init_instance, 6918 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6919 .reset_notify = hns_roce_hw_v2_reset_notify, 6920 }; 6921 6922 static struct hnae3_client hns_roce_hw_v2_client = { 6923 .name = "hns_roce_hw_v2", 6924 .type = HNAE3_CLIENT_ROCE, 6925 .ops = &hns_roce_hw_v2_ops, 6926 }; 6927 6928 static int __init hns_roce_hw_v2_init(void) 6929 { 6930 return hnae3_register_client(&hns_roce_hw_v2_client); 6931 } 6932 6933 static void __exit hns_roce_hw_v2_exit(void) 6934 { 6935 hnae3_unregister_client(&hns_roce_hw_v2_client); 6936 } 6937 6938 module_init(hns_roce_hw_v2_init); 6939 module_exit(hns_roce_hw_v2_exit); 6940 6941 MODULE_LICENSE("Dual BSD/GPL"); 6942 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6943 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6944 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6945 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6946