1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/iopoll.h> 37 #include <linux/kernel.h> 38 #include <linux/types.h> 39 #include <net/addrconf.h> 40 #include <rdma/ib_addr.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_umem.h> 43 #include <rdma/uverbs_ioctl.h> 44 45 #include "hnae3.h" 46 #include "hns_roce_common.h" 47 #include "hns_roce_device.h" 48 #include "hns_roce_cmd.h" 49 #include "hns_roce_hem.h" 50 #include "hns_roce_hw_v2.h" 51 52 enum { 53 CMD_RST_PRC_OTHERS, 54 CMD_RST_PRC_SUCCESS, 55 CMD_RST_PRC_EBUSY, 56 }; 57 58 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 59 struct ib_sge *sg) 60 { 61 dseg->lkey = cpu_to_le32(sg->lkey); 62 dseg->addr = cpu_to_le64(sg->addr); 63 dseg->len = cpu_to_le32(sg->length); 64 } 65 66 /* 67 * mapped-value = 1 + real-value 68 * The hns wr opcode real value is start from 0, In order to distinguish between 69 * initialized and uninitialized map values, we plus 1 to the actual value when 70 * defining the mapping, so that the validity can be identified by checking the 71 * mapped value is greater than 0. 72 */ 73 #define HR_OPC_MAP(ib_key, hr_key) \ 74 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 75 76 static const u32 hns_roce_op_code[] = { 77 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 78 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 79 HR_OPC_MAP(SEND, SEND), 80 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 81 HR_OPC_MAP(RDMA_READ, RDMA_READ), 82 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 83 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 84 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 85 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 86 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 87 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 88 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 89 }; 90 91 static u32 to_hr_opcode(u32 ib_opcode) 92 { 93 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 94 return HNS_ROCE_V2_WQE_OP_MASK; 95 96 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 97 HNS_ROCE_V2_WQE_OP_MASK; 98 } 99 100 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 101 const struct ib_reg_wr *wr) 102 { 103 struct hns_roce_wqe_frmr_seg *fseg = 104 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 105 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 106 u64 pbl_ba; 107 108 /* use ib_access_flags */ 109 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 110 hr_reg_write_bool(fseg, FRMR_ATOMIC, 111 wr->access & IB_ACCESS_REMOTE_ATOMIC); 112 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 113 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 114 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 115 116 /* Data structure reuse may lead to confusion */ 117 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 118 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 119 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 120 121 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 122 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 123 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 124 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 125 126 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 127 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 128 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 129 hr_reg_clear(fseg, FRMR_BLK_MODE); 130 } 131 132 static void set_atomic_seg(const struct ib_send_wr *wr, 133 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 134 unsigned int valid_num_sge) 135 { 136 struct hns_roce_v2_wqe_data_seg *dseg = 137 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 138 struct hns_roce_wqe_atomic_seg *aseg = 139 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 140 141 set_data_seg_v2(dseg, wr->sg_list); 142 143 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 144 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 145 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 146 } else { 147 aseg->fetchadd_swap_data = 148 cpu_to_le64(atomic_wr(wr)->compare_add); 149 aseg->cmp_data = 0; 150 } 151 152 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 153 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 154 } 155 156 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 157 const struct ib_send_wr *wr, 158 unsigned int *sge_idx, u32 msg_len) 159 { 160 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 161 unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg); 162 unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len; 163 unsigned int left_len_in_pg; 164 unsigned int idx = *sge_idx; 165 unsigned int i = 0; 166 unsigned int len; 167 void *addr; 168 void *dseg; 169 170 if (msg_len > ext_sge_sz) { 171 ibdev_err(ibdev, 172 "no enough extended sge space for inline data.\n"); 173 return -EINVAL; 174 } 175 176 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 177 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 178 len = wr->sg_list[0].length; 179 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 180 181 /* When copying data to extended sge space, the left length in page may 182 * not long enough for current user's sge. So the data should be 183 * splited into several parts, one in the first page, and the others in 184 * the subsequent pages. 185 */ 186 while (1) { 187 if (len <= left_len_in_pg) { 188 memcpy(dseg, addr, len); 189 190 idx += len / dseg_len; 191 192 i++; 193 if (i >= wr->num_sge) 194 break; 195 196 left_len_in_pg -= len; 197 len = wr->sg_list[i].length; 198 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 199 dseg += len; 200 } else { 201 memcpy(dseg, addr, left_len_in_pg); 202 203 len -= left_len_in_pg; 204 addr += left_len_in_pg; 205 idx += left_len_in_pg / dseg_len; 206 dseg = hns_roce_get_extend_sge(qp, 207 idx & (qp->sge.sge_cnt - 1)); 208 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 209 } 210 } 211 212 *sge_idx = idx; 213 214 return 0; 215 } 216 217 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 218 unsigned int *sge_ind, unsigned int cnt) 219 { 220 struct hns_roce_v2_wqe_data_seg *dseg; 221 unsigned int idx = *sge_ind; 222 223 while (cnt > 0) { 224 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 225 if (likely(sge->length)) { 226 set_data_seg_v2(dseg, sge); 227 idx++; 228 cnt--; 229 } 230 sge++; 231 } 232 233 *sge_ind = idx; 234 } 235 236 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 237 { 238 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 239 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 240 241 if (len > qp->max_inline_data || len > mtu) { 242 ibdev_err(&hr_dev->ib_dev, 243 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 244 len, qp->max_inline_data, mtu); 245 return false; 246 } 247 248 return true; 249 } 250 251 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 252 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 253 unsigned int *sge_idx) 254 { 255 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 256 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 257 struct ib_device *ibdev = &hr_dev->ib_dev; 258 unsigned int curr_idx = *sge_idx; 259 void *dseg = rc_sq_wqe; 260 unsigned int i; 261 int ret; 262 263 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 264 ibdev_err(ibdev, "invalid inline parameters!\n"); 265 return -EINVAL; 266 } 267 268 if (!check_inl_data_len(qp, msg_len)) 269 return -EINVAL; 270 271 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 272 273 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 274 roce_set_bit(rc_sq_wqe->byte_20, 275 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0); 276 277 for (i = 0; i < wr->num_sge; i++) { 278 memcpy(dseg, ((void *)wr->sg_list[i].addr), 279 wr->sg_list[i].length); 280 dseg += wr->sg_list[i].length; 281 } 282 } else { 283 roce_set_bit(rc_sq_wqe->byte_20, 284 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1); 285 286 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 287 if (ret) 288 return ret; 289 290 roce_set_field(rc_sq_wqe->byte_16, 291 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 292 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, 293 curr_idx - *sge_idx); 294 } 295 296 *sge_idx = curr_idx; 297 298 return 0; 299 } 300 301 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 302 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 303 unsigned int *sge_ind, 304 unsigned int valid_num_sge) 305 { 306 struct hns_roce_v2_wqe_data_seg *dseg = 307 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 308 struct hns_roce_qp *qp = to_hr_qp(ibqp); 309 int j = 0; 310 int i; 311 312 roce_set_field(rc_sq_wqe->byte_20, 313 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 314 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 315 (*sge_ind) & (qp->sge.sge_cnt - 1)); 316 317 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 318 !!(wr->send_flags & IB_SEND_INLINE)); 319 if (wr->send_flags & IB_SEND_INLINE) 320 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 321 322 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 323 for (i = 0; i < wr->num_sge; i++) { 324 if (likely(wr->sg_list[i].length)) { 325 set_data_seg_v2(dseg, wr->sg_list + i); 326 dseg++; 327 } 328 } 329 } else { 330 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 331 if (likely(wr->sg_list[i].length)) { 332 set_data_seg_v2(dseg, wr->sg_list + i); 333 dseg++; 334 j++; 335 } 336 } 337 338 set_extend_sge(qp, wr->sg_list + i, sge_ind, 339 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 340 } 341 342 roce_set_field(rc_sq_wqe->byte_16, 343 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 344 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 345 346 return 0; 347 } 348 349 static int check_send_valid(struct hns_roce_dev *hr_dev, 350 struct hns_roce_qp *hr_qp) 351 { 352 struct ib_device *ibdev = &hr_dev->ib_dev; 353 struct ib_qp *ibqp = &hr_qp->ibqp; 354 355 if (unlikely(ibqp->qp_type != IB_QPT_RC && 356 ibqp->qp_type != IB_QPT_GSI && 357 ibqp->qp_type != IB_QPT_UD)) { 358 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 359 ibqp->qp_type); 360 return -EOPNOTSUPP; 361 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 362 hr_qp->state == IB_QPS_INIT || 363 hr_qp->state == IB_QPS_RTR)) { 364 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 365 hr_qp->state); 366 return -EINVAL; 367 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 368 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 369 hr_dev->state); 370 return -EIO; 371 } 372 373 return 0; 374 } 375 376 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 377 unsigned int *sge_len) 378 { 379 unsigned int valid_num = 0; 380 unsigned int len = 0; 381 int i; 382 383 for (i = 0; i < wr->num_sge; i++) { 384 if (likely(wr->sg_list[i].length)) { 385 len += wr->sg_list[i].length; 386 valid_num++; 387 } 388 } 389 390 *sge_len = len; 391 return valid_num; 392 } 393 394 static __le32 get_immtdata(const struct ib_send_wr *wr) 395 { 396 switch (wr->opcode) { 397 case IB_WR_SEND_WITH_IMM: 398 case IB_WR_RDMA_WRITE_WITH_IMM: 399 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 400 default: 401 return 0; 402 } 403 } 404 405 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 406 const struct ib_send_wr *wr) 407 { 408 u32 ib_op = wr->opcode; 409 410 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 411 return -EINVAL; 412 413 ud_sq_wqe->immtdata = get_immtdata(wr); 414 415 roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 416 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 417 418 return 0; 419 } 420 421 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 422 struct hns_roce_ah *ah) 423 { 424 struct ib_device *ib_dev = ah->ibah.device; 425 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 426 427 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 428 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport); 429 430 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 431 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 432 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 433 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 434 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 435 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 436 437 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 438 return -EINVAL; 439 440 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 441 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 442 443 ud_sq_wqe->sgid_index = ah->av.gid_index; 444 445 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 446 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 447 448 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 449 return 0; 450 451 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 452 ah->av.vlan_en); 453 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 454 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 455 456 return 0; 457 } 458 459 static inline int set_ud_wqe(struct hns_roce_qp *qp, 460 const struct ib_send_wr *wr, 461 void *wqe, unsigned int *sge_idx, 462 unsigned int owner_bit) 463 { 464 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 465 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 466 unsigned int curr_idx = *sge_idx; 467 unsigned int valid_num_sge; 468 u32 msg_len = 0; 469 int ret; 470 471 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 472 473 ret = set_ud_opcode(ud_sq_wqe, wr); 474 if (WARN_ON(ret)) 475 return ret; 476 477 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 478 479 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 480 !!(wr->send_flags & IB_SEND_SIGNALED)); 481 482 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 483 !!(wr->send_flags & IB_SEND_SOLICITED)); 484 485 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 486 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 487 488 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 489 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 490 491 roce_set_field(ud_sq_wqe->byte_20, 492 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 493 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 494 curr_idx & (qp->sge.sge_cnt - 1)); 495 496 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 497 qp->qkey : ud_wr(wr)->remote_qkey); 498 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 499 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 500 501 ret = fill_ud_av(ud_sq_wqe, ah); 502 if (ret) 503 return ret; 504 505 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 506 507 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 508 509 /* 510 * The pipeline can sequentially post all valid WQEs into WQ buffer, 511 * including new WQEs waiting for the doorbell to update the PI again. 512 * Therefore, the owner bit of WQE MUST be updated after all fields 513 * and extSGEs have been written into DDR instead of cache. 514 */ 515 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 516 dma_wmb(); 517 518 *sge_idx = curr_idx; 519 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 520 owner_bit); 521 522 return 0; 523 } 524 525 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 526 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 527 const struct ib_send_wr *wr) 528 { 529 u32 ib_op = wr->opcode; 530 int ret = 0; 531 532 rc_sq_wqe->immtdata = get_immtdata(wr); 533 534 switch (ib_op) { 535 case IB_WR_RDMA_READ: 536 case IB_WR_RDMA_WRITE: 537 case IB_WR_RDMA_WRITE_WITH_IMM: 538 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 539 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 540 break; 541 case IB_WR_SEND: 542 case IB_WR_SEND_WITH_IMM: 543 break; 544 case IB_WR_ATOMIC_CMP_AND_SWP: 545 case IB_WR_ATOMIC_FETCH_AND_ADD: 546 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 547 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 548 break; 549 case IB_WR_REG_MR: 550 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 551 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 552 else 553 ret = -EOPNOTSUPP; 554 break; 555 case IB_WR_LOCAL_INV: 556 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 557 fallthrough; 558 case IB_WR_SEND_WITH_INV: 559 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 560 break; 561 default: 562 ret = -EINVAL; 563 } 564 565 if (unlikely(ret)) 566 return ret; 567 568 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 569 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 570 571 return ret; 572 } 573 static inline int set_rc_wqe(struct hns_roce_qp *qp, 574 const struct ib_send_wr *wr, 575 void *wqe, unsigned int *sge_idx, 576 unsigned int owner_bit) 577 { 578 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 579 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 580 unsigned int curr_idx = *sge_idx; 581 unsigned int valid_num_sge; 582 u32 msg_len = 0; 583 int ret; 584 585 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 586 587 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 588 589 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 590 if (WARN_ON(ret)) 591 return ret; 592 593 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 594 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 595 596 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 597 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 598 599 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 600 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 601 602 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 603 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 604 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 605 else if (wr->opcode != IB_WR_REG_MR) 606 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 607 &curr_idx, valid_num_sge); 608 609 /* 610 * The pipeline can sequentially post all valid WQEs into WQ buffer, 611 * including new WQEs waiting for the doorbell to update the PI again. 612 * Therefore, the owner bit of WQE MUST be updated after all fields 613 * and extSGEs have been written into DDR instead of cache. 614 */ 615 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 616 dma_wmb(); 617 618 *sge_idx = curr_idx; 619 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 620 owner_bit); 621 622 return ret; 623 } 624 625 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 626 struct hns_roce_qp *qp) 627 { 628 if (unlikely(qp->state == IB_QPS_ERR)) { 629 flush_cqe(hr_dev, qp); 630 } else { 631 struct hns_roce_v2_db sq_db = {}; 632 633 hr_reg_write(&sq_db, DB_TAG, qp->doorbell_qpn); 634 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 635 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 636 hr_reg_write(&sq_db, DB_SL, qp->sl); 637 638 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 639 } 640 } 641 642 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 643 struct hns_roce_qp *qp) 644 { 645 if (unlikely(qp->state == IB_QPS_ERR)) { 646 flush_cqe(hr_dev, qp); 647 } else { 648 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 649 *qp->rdb.db_record = 650 qp->rq.head & V2_DB_PRODUCER_IDX_M; 651 } else { 652 struct hns_roce_v2_db rq_db = {}; 653 654 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 655 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 656 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 657 658 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 659 qp->rq.db_reg); 660 } 661 } 662 } 663 664 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 665 u64 __iomem *dest) 666 { 667 #define HNS_ROCE_WRITE_TIMES 8 668 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 669 struct hnae3_handle *handle = priv->handle; 670 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 671 int i; 672 673 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 674 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 675 writeq_relaxed(*(val + i), dest + i); 676 } 677 678 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 679 void *wqe) 680 { 681 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 682 683 /* All kinds of DirectWQE have the same header field layout */ 684 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); 685 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, 686 V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); 687 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, 688 V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); 689 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, 690 V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); 691 692 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 693 } 694 695 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 696 const struct ib_send_wr *wr, 697 const struct ib_send_wr **bad_wr) 698 { 699 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 700 struct ib_device *ibdev = &hr_dev->ib_dev; 701 struct hns_roce_qp *qp = to_hr_qp(ibqp); 702 unsigned long flags = 0; 703 unsigned int owner_bit; 704 unsigned int sge_idx; 705 unsigned int wqe_idx; 706 void *wqe = NULL; 707 u32 nreq; 708 int ret; 709 710 spin_lock_irqsave(&qp->sq.lock, flags); 711 712 ret = check_send_valid(hr_dev, qp); 713 if (unlikely(ret)) { 714 *bad_wr = wr; 715 nreq = 0; 716 goto out; 717 } 718 719 sge_idx = qp->next_sge; 720 721 for (nreq = 0; wr; ++nreq, wr = wr->next) { 722 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 723 ret = -ENOMEM; 724 *bad_wr = wr; 725 goto out; 726 } 727 728 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 729 730 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 731 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 732 wr->num_sge, qp->sq.max_gs); 733 ret = -EINVAL; 734 *bad_wr = wr; 735 goto out; 736 } 737 738 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 739 qp->sq.wrid[wqe_idx] = wr->wr_id; 740 owner_bit = 741 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 742 743 /* Corresponding to the QP type, wqe process separately */ 744 if (ibqp->qp_type == IB_QPT_RC) 745 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 746 else 747 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 748 749 if (unlikely(ret)) { 750 *bad_wr = wr; 751 goto out; 752 } 753 } 754 755 out: 756 if (likely(nreq)) { 757 qp->sq.head += nreq; 758 qp->next_sge = sge_idx; 759 760 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 761 write_dwqe(hr_dev, qp, wqe); 762 else 763 update_sq_db(hr_dev, qp); 764 } 765 766 spin_unlock_irqrestore(&qp->sq.lock, flags); 767 768 return ret; 769 } 770 771 static int check_recv_valid(struct hns_roce_dev *hr_dev, 772 struct hns_roce_qp *hr_qp) 773 { 774 struct ib_device *ibdev = &hr_dev->ib_dev; 775 struct ib_qp *ibqp = &hr_qp->ibqp; 776 777 if (unlikely(ibqp->qp_type != IB_QPT_RC && 778 ibqp->qp_type != IB_QPT_GSI && 779 ibqp->qp_type != IB_QPT_UD)) { 780 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 781 ibqp->qp_type); 782 return -EOPNOTSUPP; 783 } 784 785 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 786 return -EIO; 787 788 if (hr_qp->state == IB_QPS_RESET) 789 return -EINVAL; 790 791 return 0; 792 } 793 794 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 795 u32 max_sge, bool rsv) 796 { 797 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 798 u32 i, cnt; 799 800 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 801 /* Skip zero-length sge */ 802 if (!wr->sg_list[i].length) 803 continue; 804 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 805 cnt++; 806 } 807 808 /* Fill a reserved sge to make hw stop reading remaining segments */ 809 if (rsv) { 810 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 811 dseg[cnt].addr = 0; 812 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 813 } else { 814 /* Clear remaining segments to make ROCEE ignore sges */ 815 if (cnt < max_sge) 816 memset(dseg + cnt, 0, 817 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 818 } 819 } 820 821 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 822 u32 wqe_idx, u32 max_sge) 823 { 824 struct hns_roce_rinl_sge *sge_list; 825 void *wqe = NULL; 826 u32 i; 827 828 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 829 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 830 831 /* rq support inline data */ 832 if (hr_qp->rq_inl_buf.wqe_cnt) { 833 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 834 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 835 for (i = 0; i < wr->num_sge; i++) { 836 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 837 sge_list[i].len = wr->sg_list[i].length; 838 } 839 } 840 } 841 842 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 843 const struct ib_recv_wr *wr, 844 const struct ib_recv_wr **bad_wr) 845 { 846 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 847 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 848 struct ib_device *ibdev = &hr_dev->ib_dev; 849 u32 wqe_idx, nreq, max_sge; 850 unsigned long flags; 851 int ret; 852 853 spin_lock_irqsave(&hr_qp->rq.lock, flags); 854 855 ret = check_recv_valid(hr_dev, hr_qp); 856 if (unlikely(ret)) { 857 *bad_wr = wr; 858 nreq = 0; 859 goto out; 860 } 861 862 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 863 for (nreq = 0; wr; ++nreq, wr = wr->next) { 864 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 865 hr_qp->ibqp.recv_cq))) { 866 ret = -ENOMEM; 867 *bad_wr = wr; 868 goto out; 869 } 870 871 if (unlikely(wr->num_sge > max_sge)) { 872 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 873 wr->num_sge, max_sge); 874 ret = -EINVAL; 875 *bad_wr = wr; 876 goto out; 877 } 878 879 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 880 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 881 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 882 } 883 884 out: 885 if (likely(nreq)) { 886 hr_qp->rq.head += nreq; 887 888 update_rq_db(hr_dev, hr_qp); 889 } 890 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 891 892 return ret; 893 } 894 895 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 896 { 897 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 898 } 899 900 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 901 { 902 return hns_roce_buf_offset(idx_que->mtr.kmem, 903 n << idx_que->entry_shift); 904 } 905 906 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 907 { 908 /* always called with interrupts disabled. */ 909 spin_lock(&srq->lock); 910 911 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 912 srq->idx_que.tail++; 913 914 spin_unlock(&srq->lock); 915 } 916 917 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 918 { 919 struct hns_roce_idx_que *idx_que = &srq->idx_que; 920 921 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 922 } 923 924 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 925 const struct ib_recv_wr *wr) 926 { 927 struct ib_device *ib_dev = srq->ibsrq.device; 928 929 if (unlikely(wr->num_sge > max_sge)) { 930 ibdev_err(ib_dev, 931 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 932 wr->num_sge, max_sge); 933 return -EINVAL; 934 } 935 936 if (unlikely(hns_roce_srqwq_overflow(srq))) { 937 ibdev_err(ib_dev, 938 "failed to check srqwq status, srqwq is full.\n"); 939 return -ENOMEM; 940 } 941 942 return 0; 943 } 944 945 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 946 { 947 struct hns_roce_idx_que *idx_que = &srq->idx_que; 948 u32 pos; 949 950 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 951 if (unlikely(pos == srq->wqe_cnt)) 952 return -ENOSPC; 953 954 bitmap_set(idx_que->bitmap, pos, 1); 955 *wqe_idx = pos; 956 return 0; 957 } 958 959 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 960 { 961 struct hns_roce_idx_que *idx_que = &srq->idx_que; 962 unsigned int head; 963 __le32 *buf; 964 965 head = idx_que->head & (srq->wqe_cnt - 1); 966 967 buf = get_idx_buf(idx_que, head); 968 *buf = cpu_to_le32(wqe_idx); 969 970 idx_que->head++; 971 } 972 973 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 974 { 975 hr_reg_write(db, DB_TAG, srq->srqn); 976 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 977 hr_reg_write(db, DB_PI, srq->idx_que.head); 978 } 979 980 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 981 const struct ib_recv_wr *wr, 982 const struct ib_recv_wr **bad_wr) 983 { 984 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 985 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 986 struct hns_roce_v2_db srq_db; 987 unsigned long flags; 988 int ret = 0; 989 u32 max_sge; 990 u32 wqe_idx; 991 void *wqe; 992 u32 nreq; 993 994 spin_lock_irqsave(&srq->lock, flags); 995 996 max_sge = srq->max_gs - srq->rsv_sge; 997 for (nreq = 0; wr; ++nreq, wr = wr->next) { 998 ret = check_post_srq_valid(srq, max_sge, wr); 999 if (ret) { 1000 *bad_wr = wr; 1001 break; 1002 } 1003 1004 ret = get_srq_wqe_idx(srq, &wqe_idx); 1005 if (unlikely(ret)) { 1006 *bad_wr = wr; 1007 break; 1008 } 1009 1010 wqe = get_srq_wqe_buf(srq, wqe_idx); 1011 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1012 fill_wqe_idx(srq, wqe_idx); 1013 srq->wrid[wqe_idx] = wr->wr_id; 1014 } 1015 1016 if (likely(nreq)) { 1017 update_srq_db(&srq_db, srq); 1018 1019 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1020 } 1021 1022 spin_unlock_irqrestore(&srq->lock, flags); 1023 1024 return ret; 1025 } 1026 1027 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1028 unsigned long instance_stage, 1029 unsigned long reset_stage) 1030 { 1031 /* When hardware reset has been completed once or more, we should stop 1032 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1033 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1034 * stage of soft reset process, we should exit with error, and then 1035 * HNAE3_INIT_CLIENT related process can rollback the operation like 1036 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1037 * process will exit with error to notify NIC driver to reschedule soft 1038 * reset process once again. 1039 */ 1040 hr_dev->is_reset = true; 1041 hr_dev->dis_db = true; 1042 1043 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1044 instance_stage == HNS_ROCE_STATE_INIT) 1045 return CMD_RST_PRC_EBUSY; 1046 1047 return CMD_RST_PRC_SUCCESS; 1048 } 1049 1050 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1051 unsigned long instance_stage, 1052 unsigned long reset_stage) 1053 { 1054 #define HW_RESET_TIMEOUT_US 1000000 1055 #define HW_RESET_SLEEP_US 1000 1056 1057 struct hns_roce_v2_priv *priv = hr_dev->priv; 1058 struct hnae3_handle *handle = priv->handle; 1059 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1060 unsigned long val; 1061 int ret; 1062 1063 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1064 * doorbell to hardware. If now in .init_instance() function, we should 1065 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1066 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1067 * related process can rollback the operation like notifing hardware to 1068 * free resources, HNAE3_INIT_CLIENT related process will exit with 1069 * error to notify NIC driver to reschedule soft reset process once 1070 * again. 1071 */ 1072 hr_dev->dis_db = true; 1073 1074 ret = read_poll_timeout(ops->ae_dev_reset_cnt, val, 1075 val > hr_dev->reset_cnt, HW_RESET_SLEEP_US, 1076 HW_RESET_TIMEOUT_US, false, handle); 1077 if (!ret) 1078 hr_dev->is_reset = true; 1079 1080 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1081 instance_stage == HNS_ROCE_STATE_INIT) 1082 return CMD_RST_PRC_EBUSY; 1083 1084 return CMD_RST_PRC_SUCCESS; 1085 } 1086 1087 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1088 { 1089 struct hns_roce_v2_priv *priv = hr_dev->priv; 1090 struct hnae3_handle *handle = priv->handle; 1091 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1092 1093 /* When software reset is detected at .init_instance() function, we 1094 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1095 * with error. 1096 */ 1097 hr_dev->dis_db = true; 1098 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1099 hr_dev->is_reset = true; 1100 1101 return CMD_RST_PRC_EBUSY; 1102 } 1103 1104 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1105 struct hnae3_handle *handle) 1106 { 1107 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1108 unsigned long instance_stage; /* the current instance stage */ 1109 unsigned long reset_stage; /* the current reset stage */ 1110 unsigned long reset_cnt; 1111 bool sw_resetting; 1112 bool hw_resetting; 1113 1114 /* Get information about reset from NIC driver or RoCE driver itself, 1115 * the meaning of the following variables from NIC driver are described 1116 * as below: 1117 * reset_cnt -- The count value of completed hardware reset. 1118 * hw_resetting -- Whether hardware device is resetting now. 1119 * sw_resetting -- Whether NIC's software reset process is running now. 1120 */ 1121 instance_stage = handle->rinfo.instance_state; 1122 reset_stage = handle->rinfo.reset_state; 1123 reset_cnt = ops->ae_dev_reset_cnt(handle); 1124 if (reset_cnt != hr_dev->reset_cnt) 1125 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1126 reset_stage); 1127 1128 hw_resetting = ops->get_cmdq_stat(handle); 1129 if (hw_resetting) 1130 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1131 reset_stage); 1132 1133 sw_resetting = ops->ae_dev_resetting(handle); 1134 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1135 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1136 1137 return CMD_RST_PRC_OTHERS; 1138 } 1139 1140 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1141 { 1142 struct hns_roce_v2_priv *priv = hr_dev->priv; 1143 struct hnae3_handle *handle = priv->handle; 1144 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1145 1146 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1147 return true; 1148 1149 if (ops->get_hw_reset_stat(handle)) 1150 return true; 1151 1152 if (ops->ae_dev_resetting(handle)) 1153 return true; 1154 1155 return false; 1156 } 1157 1158 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1159 { 1160 struct hns_roce_v2_priv *priv = hr_dev->priv; 1161 u32 status; 1162 1163 if (hr_dev->is_reset) 1164 status = CMD_RST_PRC_SUCCESS; 1165 else 1166 status = check_aedev_reset_status(hr_dev, priv->handle); 1167 1168 *busy = (status == CMD_RST_PRC_EBUSY); 1169 1170 return status == CMD_RST_PRC_OTHERS; 1171 } 1172 1173 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1174 struct hns_roce_v2_cmq_ring *ring) 1175 { 1176 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1177 1178 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1179 &ring->desc_dma_addr, GFP_KERNEL); 1180 if (!ring->desc) 1181 return -ENOMEM; 1182 1183 return 0; 1184 } 1185 1186 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1187 struct hns_roce_v2_cmq_ring *ring) 1188 { 1189 dma_free_coherent(hr_dev->dev, 1190 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1191 ring->desc, ring->desc_dma_addr); 1192 1193 ring->desc_dma_addr = 0; 1194 } 1195 1196 static int init_csq(struct hns_roce_dev *hr_dev, 1197 struct hns_roce_v2_cmq_ring *csq) 1198 { 1199 dma_addr_t dma; 1200 int ret; 1201 1202 csq->desc_num = CMD_CSQ_DESC_NUM; 1203 spin_lock_init(&csq->lock); 1204 csq->flag = TYPE_CSQ; 1205 csq->head = 0; 1206 1207 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1208 if (ret) 1209 return ret; 1210 1211 dma = csq->desc_dma_addr; 1212 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1213 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1214 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1215 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1216 1217 /* Make sure to write CI first and then PI */ 1218 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1219 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1220 1221 return 0; 1222 } 1223 1224 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1225 { 1226 struct hns_roce_v2_priv *priv = hr_dev->priv; 1227 int ret; 1228 1229 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1230 1231 ret = init_csq(hr_dev, &priv->cmq.csq); 1232 if (ret) 1233 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1234 1235 return ret; 1236 } 1237 1238 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1239 { 1240 struct hns_roce_v2_priv *priv = hr_dev->priv; 1241 1242 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1243 } 1244 1245 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1246 enum hns_roce_opcode_type opcode, 1247 bool is_read) 1248 { 1249 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1250 desc->opcode = cpu_to_le16(opcode); 1251 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1252 if (is_read) 1253 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1254 else 1255 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1256 } 1257 1258 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1259 { 1260 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1261 struct hns_roce_v2_priv *priv = hr_dev->priv; 1262 1263 return tail == priv->cmq.csq.head; 1264 } 1265 1266 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1267 struct hns_roce_cmq_desc *desc, int num) 1268 { 1269 struct hns_roce_v2_priv *priv = hr_dev->priv; 1270 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1271 u32 timeout = 0; 1272 u16 desc_ret; 1273 u32 tail; 1274 int ret; 1275 int i; 1276 1277 spin_lock_bh(&csq->lock); 1278 1279 tail = csq->head; 1280 1281 for (i = 0; i < num; i++) { 1282 csq->desc[csq->head++] = desc[i]; 1283 if (csq->head == csq->desc_num) 1284 csq->head = 0; 1285 } 1286 1287 /* Write to hardware */ 1288 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1289 1290 do { 1291 if (hns_roce_cmq_csq_done(hr_dev)) 1292 break; 1293 udelay(1); 1294 } while (++timeout < priv->cmq.tx_timeout); 1295 1296 if (hns_roce_cmq_csq_done(hr_dev)) { 1297 for (ret = 0, i = 0; i < num; i++) { 1298 /* check the result of hardware write back */ 1299 desc[i] = csq->desc[tail++]; 1300 if (tail == csq->desc_num) 1301 tail = 0; 1302 1303 desc_ret = le16_to_cpu(desc[i].retval); 1304 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1305 continue; 1306 1307 dev_err_ratelimited(hr_dev->dev, 1308 "Cmdq IO error, opcode = %x, return = %x\n", 1309 desc->opcode, desc_ret); 1310 ret = -EIO; 1311 } 1312 } else { 1313 /* FW/HW reset or incorrect number of desc */ 1314 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1315 dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n", 1316 csq->head, tail); 1317 csq->head = tail; 1318 1319 ret = -EAGAIN; 1320 } 1321 1322 spin_unlock_bh(&csq->lock); 1323 1324 return ret; 1325 } 1326 1327 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1328 struct hns_roce_cmq_desc *desc, int num) 1329 { 1330 bool busy; 1331 int ret; 1332 1333 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1334 return busy ? -EBUSY : 0; 1335 1336 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1337 if (ret) { 1338 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1339 return busy ? -EBUSY : 0; 1340 } 1341 1342 return ret; 1343 } 1344 1345 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 1346 dma_addr_t base_addr, u16 op) 1347 { 1348 struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1349 int ret; 1350 1351 if (IS_ERR(mbox)) 1352 return PTR_ERR(mbox); 1353 1354 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op, 1355 HNS_ROCE_CMD_TIMEOUT_MSECS); 1356 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1357 return ret; 1358 } 1359 1360 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1361 { 1362 struct hns_roce_query_version *resp; 1363 struct hns_roce_cmq_desc desc; 1364 int ret; 1365 1366 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1367 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1368 if (ret) 1369 return ret; 1370 1371 resp = (struct hns_roce_query_version *)desc.data; 1372 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1373 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1374 1375 return 0; 1376 } 1377 1378 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1379 struct hnae3_handle *handle) 1380 { 1381 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1382 unsigned long end; 1383 1384 hr_dev->dis_db = true; 1385 1386 dev_warn(hr_dev->dev, 1387 "Func clear is pending, device in resetting state.\n"); 1388 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1389 while (end) { 1390 if (!ops->get_hw_reset_stat(handle)) { 1391 hr_dev->is_reset = true; 1392 dev_info(hr_dev->dev, 1393 "Func clear success after reset.\n"); 1394 return; 1395 } 1396 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1397 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1398 } 1399 1400 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1401 } 1402 1403 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1404 struct hnae3_handle *handle) 1405 { 1406 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1407 unsigned long end; 1408 1409 hr_dev->dis_db = true; 1410 1411 dev_warn(hr_dev->dev, 1412 "Func clear is pending, device in resetting state.\n"); 1413 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1414 while (end) { 1415 if (ops->ae_dev_reset_cnt(handle) != 1416 hr_dev->reset_cnt) { 1417 hr_dev->is_reset = true; 1418 dev_info(hr_dev->dev, 1419 "Func clear success after sw reset\n"); 1420 return; 1421 } 1422 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1423 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1424 } 1425 1426 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1427 } 1428 1429 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1430 int flag) 1431 { 1432 struct hns_roce_v2_priv *priv = hr_dev->priv; 1433 struct hnae3_handle *handle = priv->handle; 1434 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1435 1436 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1437 hr_dev->dis_db = true; 1438 hr_dev->is_reset = true; 1439 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1440 return; 1441 } 1442 1443 if (ops->get_hw_reset_stat(handle)) { 1444 func_clr_hw_resetting_state(hr_dev, handle); 1445 return; 1446 } 1447 1448 if (ops->ae_dev_resetting(handle) && 1449 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1450 func_clr_sw_resetting_state(hr_dev, handle); 1451 return; 1452 } 1453 1454 if (retval && !flag) 1455 dev_warn(hr_dev->dev, 1456 "Func clear read failed, ret = %d.\n", retval); 1457 1458 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1459 } 1460 1461 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1462 { 1463 bool fclr_write_fail_flag = false; 1464 struct hns_roce_func_clear *resp; 1465 struct hns_roce_cmq_desc desc; 1466 unsigned long end; 1467 int ret = 0; 1468 1469 if (check_device_is_in_reset(hr_dev)) 1470 goto out; 1471 1472 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1473 resp = (struct hns_roce_func_clear *)desc.data; 1474 resp->rst_funcid_en = cpu_to_le32(vf_id); 1475 1476 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1477 if (ret) { 1478 fclr_write_fail_flag = true; 1479 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1480 ret); 1481 goto out; 1482 } 1483 1484 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1485 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1486 while (end) { 1487 if (check_device_is_in_reset(hr_dev)) 1488 goto out; 1489 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1490 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1491 1492 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1493 true); 1494 1495 resp->rst_funcid_en = cpu_to_le32(vf_id); 1496 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1497 if (ret) 1498 continue; 1499 1500 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1501 if (vf_id == 0) 1502 hr_dev->is_reset = true; 1503 return; 1504 } 1505 } 1506 1507 out: 1508 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1509 } 1510 1511 static void hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1512 { 1513 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1514 struct hns_roce_cmq_desc desc[2]; 1515 struct hns_roce_cmq_req *req_a; 1516 1517 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1518 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1519 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1520 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1521 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1522 hns_roce_cmq_send(hr_dev, desc, 2); 1523 } 1524 1525 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1526 { 1527 int i; 1528 1529 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1530 __hns_roce_function_clear(hr_dev, i); 1531 if (i != 0) 1532 hns_roce_free_vf_resource(hr_dev, i); 1533 } 1534 } 1535 1536 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1537 { 1538 struct hns_roce_cmq_desc desc; 1539 int ret; 1540 1541 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1542 false); 1543 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1544 if (ret) 1545 ibdev_err(&hr_dev->ib_dev, 1546 "failed to clear extended doorbell info, ret = %d.\n", 1547 ret); 1548 1549 return ret; 1550 } 1551 1552 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1553 { 1554 struct hns_roce_query_fw_info *resp; 1555 struct hns_roce_cmq_desc desc; 1556 int ret; 1557 1558 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1559 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1560 if (ret) 1561 return ret; 1562 1563 resp = (struct hns_roce_query_fw_info *)desc.data; 1564 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1565 1566 return 0; 1567 } 1568 1569 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1570 { 1571 struct hns_roce_cmq_desc desc; 1572 int ret; 1573 1574 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) { 1575 hr_dev->func_num = 1; 1576 return 0; 1577 } 1578 1579 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1580 true); 1581 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1582 if (ret) { 1583 hr_dev->func_num = 1; 1584 return ret; 1585 } 1586 1587 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1588 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1589 1590 return 0; 1591 } 1592 1593 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1594 { 1595 struct hns_roce_cmq_desc desc; 1596 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1597 u32 clock_cycles_of_1us; 1598 1599 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1600 false); 1601 1602 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 1603 clock_cycles_of_1us = HNS_ROCE_1NS_CFG; 1604 else 1605 clock_cycles_of_1us = HNS_ROCE_1US_CFG; 1606 1607 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, clock_cycles_of_1us); 1608 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1609 1610 return hns_roce_cmq_send(hr_dev, &desc, 1); 1611 } 1612 1613 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1614 { 1615 struct hns_roce_cmq_desc desc[2]; 1616 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1617 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1618 struct hns_roce_caps *caps = &hr_dev->caps; 1619 enum hns_roce_opcode_type opcode; 1620 u32 func_num; 1621 int ret; 1622 1623 if (is_vf) { 1624 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1625 func_num = 1; 1626 } else { 1627 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1628 func_num = hr_dev->func_num; 1629 } 1630 1631 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1632 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1633 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1634 1635 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1636 if (ret) 1637 return ret; 1638 1639 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1640 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1641 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1642 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1643 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1644 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1645 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1646 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1647 1648 if (is_vf) { 1649 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1650 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1651 func_num; 1652 } else { 1653 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1654 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1655 func_num; 1656 } 1657 1658 return 0; 1659 } 1660 1661 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1662 { 1663 struct hns_roce_cmq_desc desc; 1664 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1665 struct hns_roce_caps *caps = &hr_dev->caps; 1666 u32 func_num, qp_num; 1667 int ret; 1668 1669 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1670 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1671 if (ret) 1672 return ret; 1673 1674 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1675 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1676 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1677 1678 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1679 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1680 1681 return 0; 1682 } 1683 1684 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1685 { 1686 struct hns_roce_cmq_desc desc; 1687 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1688 struct hns_roce_caps *caps = &hr_dev->caps; 1689 int ret; 1690 1691 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1692 true); 1693 1694 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1695 if (ret) 1696 return ret; 1697 1698 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1699 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1700 1701 return 0; 1702 } 1703 1704 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1705 { 1706 struct device *dev = hr_dev->dev; 1707 int ret; 1708 1709 ret = load_func_res_caps(hr_dev, is_vf); 1710 if (ret) { 1711 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1712 is_vf ? "vf" : "pf"); 1713 return ret; 1714 } 1715 1716 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1717 ret = load_ext_cfg_caps(hr_dev, is_vf); 1718 if (ret) 1719 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1720 ret, is_vf ? "vf" : "pf"); 1721 } 1722 1723 return ret; 1724 } 1725 1726 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1727 { 1728 struct device *dev = hr_dev->dev; 1729 int ret; 1730 1731 ret = query_func_resource_caps(hr_dev, false); 1732 if (ret) 1733 return ret; 1734 1735 ret = load_pf_timer_res_caps(hr_dev); 1736 if (ret) 1737 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1738 ret); 1739 1740 return ret; 1741 } 1742 1743 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1744 { 1745 return query_func_resource_caps(hr_dev, true); 1746 } 1747 1748 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1749 u32 vf_id) 1750 { 1751 struct hns_roce_vf_switch *swt; 1752 struct hns_roce_cmq_desc desc; 1753 int ret; 1754 1755 swt = (struct hns_roce_vf_switch *)desc.data; 1756 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1757 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1758 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1759 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1760 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1761 if (ret) 1762 return ret; 1763 1764 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1765 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1766 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1767 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1768 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1769 1770 return hns_roce_cmq_send(hr_dev, &desc, 1); 1771 } 1772 1773 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1774 { 1775 u32 vf_id; 1776 int ret; 1777 1778 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1779 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1780 if (ret) 1781 return ret; 1782 } 1783 return 0; 1784 } 1785 1786 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1787 { 1788 struct hns_roce_cmq_desc desc[2]; 1789 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1790 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1791 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1792 struct hns_roce_caps *caps = &hr_dev->caps; 1793 1794 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1795 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1796 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1797 1798 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1799 1800 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1801 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1802 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1803 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1804 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1805 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1806 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1807 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1808 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1809 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1810 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1811 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1812 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1813 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1814 1815 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1816 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1817 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1818 vf_id * caps->gmv_bt_num); 1819 } else { 1820 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1821 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1822 vf_id * caps->sgid_bt_num); 1823 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1824 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1825 vf_id * caps->smac_bt_num); 1826 } 1827 1828 return hns_roce_cmq_send(hr_dev, desc, 2); 1829 } 1830 1831 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1832 { 1833 struct hns_roce_cmq_desc desc; 1834 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1835 struct hns_roce_caps *caps = &hr_dev->caps; 1836 1837 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1838 1839 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1840 1841 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1842 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1843 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1844 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1845 1846 return hns_roce_cmq_send(hr_dev, &desc, 1); 1847 } 1848 1849 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1850 { 1851 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1852 u32 vf_id; 1853 int ret; 1854 1855 for (vf_id = 0; vf_id < func_num; vf_id++) { 1856 ret = config_vf_hem_resource(hr_dev, vf_id); 1857 if (ret) { 1858 dev_err(hr_dev->dev, 1859 "failed to config vf-%u hem res, ret = %d.\n", 1860 vf_id, ret); 1861 return ret; 1862 } 1863 1864 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1865 ret = config_vf_ext_resource(hr_dev, vf_id); 1866 if (ret) { 1867 dev_err(hr_dev->dev, 1868 "failed to config vf-%u ext res, ret = %d.\n", 1869 vf_id, ret); 1870 return ret; 1871 } 1872 } 1873 } 1874 1875 return 0; 1876 } 1877 1878 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1879 { 1880 struct hns_roce_cmq_desc desc; 1881 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1882 struct hns_roce_caps *caps = &hr_dev->caps; 1883 1884 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1885 1886 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1887 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1888 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1889 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1890 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1891 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1892 1893 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1894 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1895 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1896 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1897 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1898 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1899 1900 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1901 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1902 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1903 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1904 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1905 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1906 1907 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1908 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1909 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1910 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1911 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1912 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1913 1914 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1915 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1916 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1917 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1918 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1919 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1920 1921 return hns_roce_cmq_send(hr_dev, &desc, 1); 1922 } 1923 1924 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1925 static void set_default_caps(struct hns_roce_dev *hr_dev) 1926 { 1927 struct hns_roce_caps *caps = &hr_dev->caps; 1928 1929 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1930 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1931 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1932 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1933 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1934 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1935 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1936 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1937 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1938 1939 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1940 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1941 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1942 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1943 caps->num_comp_vectors = 0; 1944 1945 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1946 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1947 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1948 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1949 1950 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1951 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1952 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1953 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1954 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1955 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1956 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1957 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1958 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1959 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1960 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1961 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1962 caps->reserved_lkey = 0; 1963 caps->reserved_pds = 0; 1964 caps->reserved_mrws = 1; 1965 caps->reserved_uars = 0; 1966 caps->reserved_cqs = 0; 1967 caps->reserved_srqs = 0; 1968 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1969 1970 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1971 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1972 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1973 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1974 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1975 1976 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1977 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1978 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1979 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1980 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1981 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1982 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1983 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1984 1985 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1986 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1987 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 1988 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 1989 1990 caps->pkey_table_len[0] = 1; 1991 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1992 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1993 caps->local_ca_ack_delay = 0; 1994 caps->max_mtu = IB_MTU_4096; 1995 1996 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1997 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1998 1999 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 2000 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 2001 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; 2002 2003 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 2004 2005 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2006 caps->flags |= HNS_ROCE_CAP_FLAG_STASH; 2007 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 2008 } else { 2009 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 2010 2011 /* The following configuration are only valid for HIP08 */ 2012 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 2013 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 2014 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 2015 } 2016 } 2017 2018 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2019 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2020 { 2021 u64 obj_per_chunk; 2022 u64 bt_chunk_size = PAGE_SIZE; 2023 u64 buf_chunk_size = PAGE_SIZE; 2024 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2025 2026 *buf_page_size = 0; 2027 *bt_page_size = 0; 2028 2029 switch (hop_num) { 2030 case 3: 2031 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2032 (bt_chunk_size / BA_BYTE_LEN) * 2033 (bt_chunk_size / BA_BYTE_LEN) * 2034 obj_per_chunk_default; 2035 break; 2036 case 2: 2037 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2038 (bt_chunk_size / BA_BYTE_LEN) * 2039 obj_per_chunk_default; 2040 break; 2041 case 1: 2042 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2043 obj_per_chunk_default; 2044 break; 2045 case HNS_ROCE_HOP_NUM_0: 2046 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2047 break; 2048 default: 2049 pr_err("table %u not support hop_num = %u!\n", hem_type, 2050 hop_num); 2051 return; 2052 } 2053 2054 if (hem_type >= HEM_TYPE_MTT) 2055 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2056 else 2057 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2058 } 2059 2060 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2061 { 2062 struct hns_roce_caps *caps = &hr_dev->caps; 2063 2064 /* EQ */ 2065 caps->eqe_ba_pg_sz = 0; 2066 caps->eqe_buf_pg_sz = 0; 2067 2068 /* Link Table */ 2069 caps->llm_buf_pg_sz = 0; 2070 2071 /* MR */ 2072 caps->mpt_ba_pg_sz = 0; 2073 caps->mpt_buf_pg_sz = 0; 2074 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2075 caps->pbl_buf_pg_sz = 0; 2076 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2077 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2078 HEM_TYPE_MTPT); 2079 2080 /* QP */ 2081 caps->qpc_ba_pg_sz = 0; 2082 caps->qpc_buf_pg_sz = 0; 2083 caps->qpc_timer_ba_pg_sz = 0; 2084 caps->qpc_timer_buf_pg_sz = 0; 2085 caps->sccc_ba_pg_sz = 0; 2086 caps->sccc_buf_pg_sz = 0; 2087 caps->mtt_ba_pg_sz = 0; 2088 caps->mtt_buf_pg_sz = 0; 2089 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2090 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2091 HEM_TYPE_QPC); 2092 2093 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2094 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2095 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2096 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2097 2098 /* CQ */ 2099 caps->cqc_ba_pg_sz = 0; 2100 caps->cqc_buf_pg_sz = 0; 2101 caps->cqc_timer_ba_pg_sz = 0; 2102 caps->cqc_timer_buf_pg_sz = 0; 2103 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2104 caps->cqe_buf_pg_sz = 0; 2105 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2106 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2107 HEM_TYPE_CQC); 2108 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2109 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2110 2111 /* SRQ */ 2112 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2113 caps->srqc_ba_pg_sz = 0; 2114 caps->srqc_buf_pg_sz = 0; 2115 caps->srqwqe_ba_pg_sz = 0; 2116 caps->srqwqe_buf_pg_sz = 0; 2117 caps->idx_ba_pg_sz = 0; 2118 caps->idx_buf_pg_sz = 0; 2119 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2120 caps->srqc_hop_num, caps->srqc_bt_num, 2121 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2122 HEM_TYPE_SRQC); 2123 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2124 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2125 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2126 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2127 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2128 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2129 } 2130 2131 /* GMV */ 2132 caps->gmv_ba_pg_sz = 0; 2133 caps->gmv_buf_pg_sz = 0; 2134 } 2135 2136 /* Apply all loaded caps before setting to hardware */ 2137 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2138 { 2139 struct hns_roce_caps *caps = &hr_dev->caps; 2140 struct hns_roce_v2_priv *priv = hr_dev->priv; 2141 2142 /* The following configurations don't need to be got from firmware. */ 2143 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2144 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2145 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2146 2147 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2148 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2149 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2150 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2151 2152 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2153 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2154 2155 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 2156 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2157 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2158 2159 if (!caps->num_comp_vectors) 2160 caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1, 2161 (u32)priv->handle->rinfo.num_vectors - 2); 2162 2163 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2164 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2165 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2166 2167 /* The following configurations will be overwritten */ 2168 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2169 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2170 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2171 2172 /* The following configurations are not got from firmware */ 2173 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2174 2175 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2176 caps->gid_table_len[0] = caps->gmv_bt_num * 2177 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2178 2179 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2180 caps->gmv_entry_sz); 2181 } else { 2182 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2183 2184 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2185 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2186 caps->gid_table_len[0] /= func_num; 2187 } 2188 2189 if (hr_dev->is_vf) { 2190 caps->default_aeq_arm_st = 0x3; 2191 caps->default_ceq_arm_st = 0x3; 2192 caps->default_ceq_max_cnt = 0x1; 2193 caps->default_ceq_period = 0x10; 2194 caps->default_aeq_max_cnt = 0x1; 2195 caps->default_aeq_period = 0x10; 2196 } 2197 2198 set_hem_page_size(hr_dev); 2199 } 2200 2201 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2202 { 2203 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2204 struct hns_roce_caps *caps = &hr_dev->caps; 2205 struct hns_roce_query_pf_caps_a *resp_a; 2206 struct hns_roce_query_pf_caps_b *resp_b; 2207 struct hns_roce_query_pf_caps_c *resp_c; 2208 struct hns_roce_query_pf_caps_d *resp_d; 2209 struct hns_roce_query_pf_caps_e *resp_e; 2210 int ctx_hop_num; 2211 int pbl_hop_num; 2212 int ret; 2213 int i; 2214 2215 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2216 hns_roce_cmq_setup_basic_desc(&desc[i], 2217 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2218 true); 2219 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2220 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2221 else 2222 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2223 } 2224 2225 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2226 if (ret) 2227 return ret; 2228 2229 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2230 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2231 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2232 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2233 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2234 2235 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2236 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2237 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2238 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2239 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2240 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 2241 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 2242 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 2243 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2244 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2245 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2246 caps->num_other_vectors = resp_a->num_other_vectors; 2247 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2248 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2249 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 2250 caps->cqe_sz = resp_a->cqe_sz; 2251 2252 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2253 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2254 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2255 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2256 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2257 caps->idx_entry_sz = resp_b->idx_entry_sz; 2258 caps->sccc_sz = resp_b->sccc_sz; 2259 caps->max_mtu = resp_b->max_mtu; 2260 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2261 caps->min_cqes = resp_b->min_cqes; 2262 caps->min_wqes = resp_b->min_wqes; 2263 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2264 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2265 caps->phy_num_uars = resp_b->phy_num_uars; 2266 ctx_hop_num = resp_b->ctx_hop_num; 2267 pbl_hop_num = resp_b->pbl_hop_num; 2268 2269 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 2270 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 2271 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 2272 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 2273 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 2274 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 2275 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2276 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2277 2278 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 2279 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 2280 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 2281 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 2282 V2_QUERY_PF_CAPS_C_MAX_GID_M, 2283 V2_QUERY_PF_CAPS_C_MAX_GID_S); 2284 2285 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 2286 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 2287 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 2288 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 2289 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 2290 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 2291 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 2292 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 2293 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 2294 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 2295 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 2296 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 2297 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2298 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2299 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 2300 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 2301 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 2302 caps->cong_type = roce_get_field(resp_d->wq_hop_num_max_srqs, 2303 V2_QUERY_PF_CAPS_D_CONG_TYPE_M, 2304 V2_QUERY_PF_CAPS_D_CONG_TYPE_S); 2305 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2306 2307 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 2308 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 2309 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 2310 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 2311 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 2312 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 2313 2314 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 2315 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 2316 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 2317 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2318 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 2319 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 2320 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2321 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 2322 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 2323 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 2324 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 2325 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 2326 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 2327 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 2328 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 2329 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 2330 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 2331 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 2332 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 2333 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 2334 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 2335 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2336 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 2337 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 2338 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2339 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 2340 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 2341 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 2342 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 2343 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 2344 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 2345 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 2346 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 2347 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 2348 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 2349 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 2350 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2351 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2352 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2353 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2354 2355 caps->qpc_hop_num = ctx_hop_num; 2356 caps->sccc_hop_num = ctx_hop_num; 2357 caps->srqc_hop_num = ctx_hop_num; 2358 caps->cqc_hop_num = ctx_hop_num; 2359 caps->mpt_hop_num = ctx_hop_num; 2360 caps->mtt_hop_num = pbl_hop_num; 2361 caps->cqe_hop_num = pbl_hop_num; 2362 caps->srqwqe_hop_num = pbl_hop_num; 2363 caps->idx_hop_num = pbl_hop_num; 2364 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2365 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 2366 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 2367 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2368 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 2369 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 2370 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2371 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 2372 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 2373 2374 return 0; 2375 } 2376 2377 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2378 { 2379 struct hns_roce_cmq_desc desc; 2380 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2381 2382 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2383 false); 2384 2385 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2386 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2387 2388 return hns_roce_cmq_send(hr_dev, &desc, 1); 2389 } 2390 2391 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2392 { 2393 struct hns_roce_caps *caps = &hr_dev->caps; 2394 int ret; 2395 2396 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 2397 return 0; 2398 2399 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2400 caps->qpc_sz); 2401 if (ret) { 2402 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2403 return ret; 2404 } 2405 2406 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2407 caps->sccc_sz); 2408 if (ret) 2409 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2410 2411 return ret; 2412 } 2413 2414 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2415 { 2416 struct device *dev = hr_dev->dev; 2417 int ret; 2418 2419 hr_dev->func_num = 1; 2420 2421 set_default_caps(hr_dev); 2422 2423 ret = hns_roce_query_vf_resource(hr_dev); 2424 if (ret) { 2425 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2426 return ret; 2427 } 2428 2429 apply_func_caps(hr_dev); 2430 2431 ret = hns_roce_v2_set_bt(hr_dev); 2432 if (ret) 2433 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2434 2435 return ret; 2436 } 2437 2438 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2439 { 2440 struct device *dev = hr_dev->dev; 2441 int ret; 2442 2443 ret = hns_roce_query_func_info(hr_dev); 2444 if (ret) { 2445 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2446 return ret; 2447 } 2448 2449 ret = hns_roce_config_global_param(hr_dev); 2450 if (ret) { 2451 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2452 return ret; 2453 } 2454 2455 ret = hns_roce_set_vf_switch_param(hr_dev); 2456 if (ret) { 2457 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2458 return ret; 2459 } 2460 2461 ret = hns_roce_query_pf_caps(hr_dev); 2462 if (ret) 2463 set_default_caps(hr_dev); 2464 2465 ret = hns_roce_query_pf_resource(hr_dev); 2466 if (ret) { 2467 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2468 return ret; 2469 } 2470 2471 apply_func_caps(hr_dev); 2472 2473 ret = hns_roce_alloc_vf_resource(hr_dev); 2474 if (ret) { 2475 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2476 return ret; 2477 } 2478 2479 ret = hns_roce_v2_set_bt(hr_dev); 2480 if (ret) { 2481 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2482 return ret; 2483 } 2484 2485 /* Configure the size of QPC, SCCC, etc. */ 2486 return hns_roce_config_entry_size(hr_dev); 2487 } 2488 2489 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2490 { 2491 struct device *dev = hr_dev->dev; 2492 int ret; 2493 2494 ret = hns_roce_cmq_query_hw_info(hr_dev); 2495 if (ret) { 2496 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2497 return ret; 2498 } 2499 2500 ret = hns_roce_query_fw_ver(hr_dev); 2501 if (ret) { 2502 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2503 return ret; 2504 } 2505 2506 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2507 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2508 2509 if (hr_dev->is_vf) 2510 return hns_roce_v2_vf_profile(hr_dev); 2511 else 2512 return hns_roce_v2_pf_profile(hr_dev); 2513 } 2514 2515 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2516 { 2517 u32 i, next_ptr, page_num; 2518 __le64 *entry = cfg_buf; 2519 dma_addr_t addr; 2520 u64 val; 2521 2522 page_num = data_buf->npages; 2523 for (i = 0; i < page_num; i++) { 2524 addr = hns_roce_buf_page(data_buf, i); 2525 if (i == (page_num - 1)) 2526 next_ptr = 0; 2527 else 2528 next_ptr = i + 1; 2529 2530 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2531 entry[i] = cpu_to_le64(val); 2532 } 2533 } 2534 2535 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2536 struct hns_roce_link_table *table) 2537 { 2538 struct hns_roce_cmq_desc desc[2]; 2539 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2540 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2541 struct hns_roce_buf *buf = table->buf; 2542 enum hns_roce_opcode_type opcode; 2543 dma_addr_t addr; 2544 2545 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2546 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2547 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2548 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2549 2550 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2551 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2552 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2553 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2554 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2555 2556 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2557 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2558 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2559 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2560 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2561 2562 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2563 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2564 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2565 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2566 2567 return hns_roce_cmq_send(hr_dev, desc, 2); 2568 } 2569 2570 static struct hns_roce_link_table * 2571 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2572 { 2573 struct hns_roce_v2_priv *priv = hr_dev->priv; 2574 struct hns_roce_link_table *link_tbl; 2575 u32 pg_shift, size, min_size; 2576 2577 link_tbl = &priv->ext_llm; 2578 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2579 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2580 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2581 2582 /* Alloc data table */ 2583 size = max(size, min_size); 2584 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2585 if (IS_ERR(link_tbl->buf)) 2586 return ERR_PTR(-ENOMEM); 2587 2588 /* Alloc config table */ 2589 size = link_tbl->buf->npages * sizeof(u64); 2590 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2591 &link_tbl->table.map, 2592 GFP_KERNEL); 2593 if (!link_tbl->table.buf) { 2594 hns_roce_buf_free(hr_dev, link_tbl->buf); 2595 return ERR_PTR(-ENOMEM); 2596 } 2597 2598 return link_tbl; 2599 } 2600 2601 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2602 struct hns_roce_link_table *tbl) 2603 { 2604 if (tbl->buf) { 2605 u32 size = tbl->buf->npages * sizeof(u64); 2606 2607 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2608 tbl->table.map); 2609 } 2610 2611 hns_roce_buf_free(hr_dev, tbl->buf); 2612 } 2613 2614 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2615 { 2616 struct hns_roce_link_table *link_tbl; 2617 int ret; 2618 2619 link_tbl = alloc_link_table_buf(hr_dev); 2620 if (IS_ERR(link_tbl)) 2621 return -ENOMEM; 2622 2623 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2624 ret = -EINVAL; 2625 goto err_alloc; 2626 } 2627 2628 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2629 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2630 if (ret) 2631 goto err_alloc; 2632 2633 return 0; 2634 2635 err_alloc: 2636 free_link_table_buf(hr_dev, link_tbl); 2637 return ret; 2638 } 2639 2640 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2641 { 2642 struct hns_roce_v2_priv *priv = hr_dev->priv; 2643 2644 free_link_table_buf(hr_dev, &priv->ext_llm); 2645 } 2646 2647 static void free_dip_list(struct hns_roce_dev *hr_dev) 2648 { 2649 struct hns_roce_dip *hr_dip; 2650 struct hns_roce_dip *tmp; 2651 unsigned long flags; 2652 2653 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2654 2655 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2656 list_del(&hr_dip->node); 2657 kfree(hr_dip); 2658 } 2659 2660 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2661 } 2662 2663 static int get_hem_table(struct hns_roce_dev *hr_dev) 2664 { 2665 unsigned int qpc_count; 2666 unsigned int cqc_count; 2667 unsigned int gmv_count; 2668 int ret; 2669 int i; 2670 2671 /* Alloc memory for source address table buffer space chunk */ 2672 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2673 gmv_count++) { 2674 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2675 if (ret) 2676 goto err_gmv_failed; 2677 } 2678 2679 if (hr_dev->is_vf) 2680 return 0; 2681 2682 /* Alloc memory for QPC Timer buffer space chunk */ 2683 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2684 qpc_count++) { 2685 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2686 qpc_count); 2687 if (ret) { 2688 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2689 goto err_qpc_timer_failed; 2690 } 2691 } 2692 2693 /* Alloc memory for CQC Timer buffer space chunk */ 2694 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2695 cqc_count++) { 2696 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2697 cqc_count); 2698 if (ret) { 2699 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2700 goto err_cqc_timer_failed; 2701 } 2702 } 2703 2704 return 0; 2705 2706 err_cqc_timer_failed: 2707 for (i = 0; i < cqc_count; i++) 2708 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2709 2710 err_qpc_timer_failed: 2711 for (i = 0; i < qpc_count; i++) 2712 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2713 2714 err_gmv_failed: 2715 for (i = 0; i < gmv_count; i++) 2716 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2717 2718 return ret; 2719 } 2720 2721 static void put_hem_table(struct hns_roce_dev *hr_dev) 2722 { 2723 int i; 2724 2725 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2726 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2727 2728 if (hr_dev->is_vf) 2729 return; 2730 2731 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2732 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2733 2734 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2735 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2736 } 2737 2738 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2739 { 2740 int ret; 2741 2742 /* The hns ROCEE requires the extdb info to be cleared before using */ 2743 ret = hns_roce_clear_extdb_list_info(hr_dev); 2744 if (ret) 2745 return ret; 2746 2747 ret = get_hem_table(hr_dev); 2748 if (ret) 2749 return ret; 2750 2751 if (hr_dev->is_vf) 2752 return 0; 2753 2754 ret = hns_roce_init_link_table(hr_dev); 2755 if (ret) { 2756 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2757 goto err_llm_init_failed; 2758 } 2759 2760 return 0; 2761 2762 err_llm_init_failed: 2763 put_hem_table(hr_dev); 2764 2765 return ret; 2766 } 2767 2768 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2769 { 2770 hns_roce_function_clear(hr_dev); 2771 2772 if (!hr_dev->is_vf) 2773 hns_roce_free_link_table(hr_dev); 2774 2775 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2776 free_dip_list(hr_dev); 2777 } 2778 2779 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2780 u64 out_param, u32 in_modifier, u8 op_modifier, 2781 u16 op, u16 token, int event) 2782 { 2783 struct hns_roce_cmq_desc desc; 2784 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2785 2786 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2787 2788 mb->in_param_l = cpu_to_le32(in_param); 2789 mb->in_param_h = cpu_to_le32(in_param >> 32); 2790 mb->out_param_l = cpu_to_le32(out_param); 2791 mb->out_param_h = cpu_to_le32(out_param >> 32); 2792 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2793 mb->token_event_en = cpu_to_le32(event << 16 | token); 2794 2795 return hns_roce_cmq_send(hr_dev, &desc, 1); 2796 } 2797 2798 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2799 u8 *complete_status) 2800 { 2801 struct hns_roce_mbox_status *mb_st; 2802 struct hns_roce_cmq_desc desc; 2803 unsigned long end; 2804 int ret = -EBUSY; 2805 u32 status; 2806 bool busy; 2807 2808 mb_st = (struct hns_roce_mbox_status *)desc.data; 2809 end = msecs_to_jiffies(timeout) + jiffies; 2810 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2811 status = 0; 2812 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2813 true); 2814 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2815 if (!ret) { 2816 status = le32_to_cpu(mb_st->mb_status_hw_run); 2817 /* No pending message exists in ROCEE mbox. */ 2818 if (!(status & MB_ST_HW_RUN_M)) 2819 break; 2820 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2821 break; 2822 } 2823 2824 if (time_after(jiffies, end)) { 2825 dev_err_ratelimited(hr_dev->dev, 2826 "failed to wait mbox status 0x%x\n", 2827 status); 2828 return -ETIMEDOUT; 2829 } 2830 2831 cond_resched(); 2832 ret = -EBUSY; 2833 } 2834 2835 if (!ret) { 2836 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2837 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2838 /* Ignore all errors if the mbox is unavailable. */ 2839 ret = 0; 2840 *complete_status = MB_ST_COMPLETE_M; 2841 } 2842 2843 return ret; 2844 } 2845 2846 static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2847 u64 out_param, u32 in_modifier, u8 op_modifier, 2848 u16 op, u16 token, int event) 2849 { 2850 u8 status = 0; 2851 int ret; 2852 2853 /* Waiting for the mbox to be idle */ 2854 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 2855 &status); 2856 if (unlikely(ret)) { 2857 dev_err_ratelimited(hr_dev->dev, 2858 "failed to check post mbox status = 0x%x, ret = %d.\n", 2859 status, ret); 2860 return ret; 2861 } 2862 2863 /* Post new message to mbox */ 2864 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2865 op_modifier, op, token, event); 2866 if (ret) 2867 dev_err_ratelimited(hr_dev->dev, 2868 "failed to post mailbox, ret = %d.\n", ret); 2869 2870 return ret; 2871 } 2872 2873 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout) 2874 { 2875 u8 status = 0; 2876 int ret; 2877 2878 ret = v2_wait_mbox_complete(hr_dev, timeout, &status); 2879 if (!ret) { 2880 if (status != MB_ST_COMPLETE_SUCC) 2881 return -EBUSY; 2882 } else { 2883 dev_err_ratelimited(hr_dev->dev, 2884 "failed to check mbox status = 0x%x, ret = %d.\n", 2885 status, ret); 2886 } 2887 2888 return ret; 2889 } 2890 2891 static void copy_gid(void *dest, const union ib_gid *gid) 2892 { 2893 #define GID_SIZE 4 2894 const union ib_gid *src = gid; 2895 __le32 (*p)[GID_SIZE] = dest; 2896 int i; 2897 2898 if (!gid) 2899 src = &zgid; 2900 2901 for (i = 0; i < GID_SIZE; i++) 2902 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 2903 } 2904 2905 static int config_sgid_table(struct hns_roce_dev *hr_dev, 2906 int gid_index, const union ib_gid *gid, 2907 enum hns_roce_sgid_type sgid_type) 2908 { 2909 struct hns_roce_cmq_desc desc; 2910 struct hns_roce_cfg_sgid_tb *sgid_tb = 2911 (struct hns_roce_cfg_sgid_tb *)desc.data; 2912 2913 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2914 2915 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2916 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2917 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2918 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2919 2920 copy_gid(&sgid_tb->vf_sgid_l, gid); 2921 2922 return hns_roce_cmq_send(hr_dev, &desc, 1); 2923 } 2924 2925 static int config_gmv_table(struct hns_roce_dev *hr_dev, 2926 int gid_index, const union ib_gid *gid, 2927 enum hns_roce_sgid_type sgid_type, 2928 const struct ib_gid_attr *attr) 2929 { 2930 struct hns_roce_cmq_desc desc[2]; 2931 struct hns_roce_cfg_gmv_tb_a *tb_a = 2932 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 2933 struct hns_roce_cfg_gmv_tb_b *tb_b = 2934 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 2935 2936 u16 vlan_id = VLAN_CFI_MASK; 2937 u8 mac[ETH_ALEN] = {}; 2938 int ret; 2939 2940 if (gid) { 2941 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 2942 if (ret) 2943 return ret; 2944 } 2945 2946 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2947 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2948 2949 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2950 2951 copy_gid(&tb_a->vf_sgid_l, gid); 2952 2953 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_SGID_TYPE_M, 2954 CFG_GMV_TB_VF_SGID_TYPE_S, sgid_type); 2955 roce_set_bit(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_EN_S, 2956 vlan_id < VLAN_CFI_MASK); 2957 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_ID_M, 2958 CFG_GMV_TB_VF_VLAN_ID_S, vlan_id); 2959 2960 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 2961 roce_set_field(tb_b->vf_smac_h, CFG_GMV_TB_SMAC_H_M, 2962 CFG_GMV_TB_SMAC_H_S, *(u16 *)&mac[4]); 2963 2964 roce_set_field(tb_b->table_idx_rsv, CFG_GMV_TB_SGID_IDX_M, 2965 CFG_GMV_TB_SGID_IDX_S, gid_index); 2966 2967 return hns_roce_cmq_send(hr_dev, desc, 2); 2968 } 2969 2970 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u32 port, 2971 int gid_index, const union ib_gid *gid, 2972 const struct ib_gid_attr *attr) 2973 { 2974 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2975 int ret; 2976 2977 if (gid) { 2978 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2979 if (ipv6_addr_v4mapped((void *)gid)) 2980 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2981 else 2982 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2983 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 2984 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2985 } 2986 } 2987 2988 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 2989 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 2990 else 2991 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2992 2993 if (ret) 2994 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 2995 ret); 2996 2997 return ret; 2998 } 2999 3000 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 3001 const u8 *addr) 3002 { 3003 struct hns_roce_cmq_desc desc; 3004 struct hns_roce_cfg_smac_tb *smac_tb = 3005 (struct hns_roce_cfg_smac_tb *)desc.data; 3006 u16 reg_smac_h; 3007 u32 reg_smac_l; 3008 3009 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 3010 3011 reg_smac_l = *(u32 *)(&addr[0]); 3012 reg_smac_h = *(u16 *)(&addr[4]); 3013 3014 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 3015 CFG_SMAC_TB_IDX_S, phy_port); 3016 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 3017 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 3018 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3019 3020 return hns_roce_cmq_send(hr_dev, &desc, 1); 3021 } 3022 3023 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3024 struct hns_roce_v2_mpt_entry *mpt_entry, 3025 struct hns_roce_mr *mr) 3026 { 3027 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3028 struct ib_device *ibdev = &hr_dev->ib_dev; 3029 dma_addr_t pbl_ba; 3030 int i, count; 3031 3032 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3033 ARRAY_SIZE(pages), &pbl_ba); 3034 if (count < 1) { 3035 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3036 count); 3037 return -ENOBUFS; 3038 } 3039 3040 /* Aligned to the hardware address access unit */ 3041 for (i = 0; i < count; i++) 3042 pages[i] >>= 6; 3043 3044 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3045 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3046 roce_set_field(mpt_entry->byte_48_mode_ba, 3047 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 3048 upper_32_bits(pbl_ba >> 3)); 3049 3050 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3051 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 3052 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 3053 3054 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3055 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 3056 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 3057 roce_set_field(mpt_entry->byte_64_buf_pa1, 3058 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3059 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3060 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3061 3062 return 0; 3063 } 3064 3065 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3066 void *mb_buf, struct hns_roce_mr *mr, 3067 unsigned long mtpt_idx) 3068 { 3069 struct hns_roce_v2_mpt_entry *mpt_entry; 3070 int ret; 3071 3072 mpt_entry = mb_buf; 3073 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3074 3075 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3076 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3077 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3078 3079 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3080 mr->access & IB_ACCESS_MW_BIND); 3081 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3082 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3083 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3084 mr->access & IB_ACCESS_REMOTE_READ); 3085 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3086 mr->access & IB_ACCESS_REMOTE_WRITE); 3087 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3088 mr->access & IB_ACCESS_LOCAL_WRITE); 3089 3090 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3091 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3092 mpt_entry->lkey = cpu_to_le32(mr->key); 3093 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3094 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3095 3096 if (mr->type != MR_TYPE_MR) 3097 hr_reg_enable(mpt_entry, MPT_PA); 3098 3099 if (mr->type == MR_TYPE_DMA) 3100 return 0; 3101 3102 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3103 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3104 3105 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3106 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3107 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3108 3109 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3110 3111 return ret; 3112 } 3113 3114 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3115 struct hns_roce_mr *mr, int flags, 3116 void *mb_buf) 3117 { 3118 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3119 u32 mr_access_flags = mr->access; 3120 int ret = 0; 3121 3122 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3123 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 3124 3125 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3126 V2_MPT_BYTE_4_PD_S, mr->pd); 3127 3128 if (flags & IB_MR_REREG_ACCESS) { 3129 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3130 V2_MPT_BYTE_8_BIND_EN_S, 3131 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3132 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3133 V2_MPT_BYTE_8_ATOMIC_EN_S, 3134 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3135 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 3136 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3137 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 3138 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3139 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 3140 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3141 } 3142 3143 if (flags & IB_MR_REREG_TRANS) { 3144 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3145 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3146 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3147 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3148 3149 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3150 } 3151 3152 return ret; 3153 } 3154 3155 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3156 void *mb_buf, struct hns_roce_mr *mr) 3157 { 3158 struct ib_device *ibdev = &hr_dev->ib_dev; 3159 struct hns_roce_v2_mpt_entry *mpt_entry; 3160 dma_addr_t pbl_ba = 0; 3161 3162 mpt_entry = mb_buf; 3163 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3164 3165 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3166 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3167 return -ENOBUFS; 3168 } 3169 3170 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3171 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3172 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3173 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 3174 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3175 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3176 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3177 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3178 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3179 V2_MPT_BYTE_4_PD_S, mr->pd); 3180 3181 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 3182 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3183 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3184 3185 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 3186 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3187 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 3188 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3189 3190 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3191 3192 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3193 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 3194 V2_MPT_BYTE_48_PBL_BA_H_S, 3195 upper_32_bits(pbl_ba >> 3)); 3196 3197 roce_set_field(mpt_entry->byte_64_buf_pa1, 3198 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3199 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3200 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3201 3202 return 0; 3203 } 3204 3205 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3206 { 3207 struct hns_roce_v2_mpt_entry *mpt_entry; 3208 3209 mpt_entry = mb_buf; 3210 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3211 3212 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3213 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3214 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3215 V2_MPT_BYTE_4_PD_S, mw->pdn); 3216 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3217 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 3218 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3219 mw->pbl_hop_num); 3220 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3221 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3222 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3223 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3224 3225 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3226 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3227 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1); 3228 3229 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3230 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 3231 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3232 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 3233 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3234 3235 roce_set_field(mpt_entry->byte_64_buf_pa1, 3236 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3237 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3238 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3239 3240 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3241 3242 return 0; 3243 } 3244 3245 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3246 { 3247 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3248 } 3249 3250 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3251 { 3252 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3253 3254 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3255 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3256 NULL; 3257 } 3258 3259 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3260 struct hns_roce_cq *hr_cq) 3261 { 3262 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3263 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3264 } else { 3265 struct hns_roce_v2_db cq_db = {}; 3266 3267 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3268 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3269 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3270 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3271 3272 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3273 } 3274 } 3275 3276 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3277 struct hns_roce_srq *srq) 3278 { 3279 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3280 struct hns_roce_v2_cqe *cqe, *dest; 3281 u32 prod_index; 3282 int nfreed = 0; 3283 int wqe_index; 3284 u8 owner_bit; 3285 3286 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3287 ++prod_index) { 3288 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3289 break; 3290 } 3291 3292 /* 3293 * Now backwards through the CQ, removing CQ entries 3294 * that match our QP by overwriting them with next entries. 3295 */ 3296 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3297 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3298 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3299 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3300 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3301 hns_roce_free_srq_wqe(srq, wqe_index); 3302 } 3303 ++nfreed; 3304 } else if (nfreed) { 3305 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3306 hr_cq->ib_cq.cqe); 3307 owner_bit = hr_reg_read(dest, CQE_OWNER); 3308 memcpy(dest, cqe, hr_cq->cqe_size); 3309 hr_reg_write(dest, CQE_OWNER, owner_bit); 3310 } 3311 } 3312 3313 if (nfreed) { 3314 hr_cq->cons_index += nfreed; 3315 update_cq_db(hr_dev, hr_cq); 3316 } 3317 } 3318 3319 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3320 struct hns_roce_srq *srq) 3321 { 3322 spin_lock_irq(&hr_cq->lock); 3323 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3324 spin_unlock_irq(&hr_cq->lock); 3325 } 3326 3327 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3328 struct hns_roce_cq *hr_cq, void *mb_buf, 3329 u64 *mtts, dma_addr_t dma_handle) 3330 { 3331 struct hns_roce_v2_cq_context *cq_context; 3332 3333 cq_context = mb_buf; 3334 memset(cq_context, 0, sizeof(*cq_context)); 3335 3336 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3337 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3338 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3339 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3340 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3341 3342 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3343 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3344 3345 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3346 hr_reg_enable(cq_context, CQC_STASH); 3347 3348 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3349 to_hr_hw_page_addr(mtts[0])); 3350 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3351 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3352 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3353 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3354 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3355 to_hr_hw_page_addr(mtts[1])); 3356 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3357 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3358 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3359 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3360 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3361 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3362 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3363 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3364 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3365 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3366 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3367 ((u32)hr_cq->db.dma) >> 1); 3368 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3369 hr_cq->db.dma >> 32); 3370 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3371 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3372 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3373 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3374 } 3375 3376 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3377 enum ib_cq_notify_flags flags) 3378 { 3379 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3380 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3381 struct hns_roce_v2_db cq_db = {}; 3382 u32 notify_flag; 3383 3384 /* 3385 * flags = 0, then notify_flag : next 3386 * flags = 1, then notify flag : solocited 3387 */ 3388 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3389 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3390 3391 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3392 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3393 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3394 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3395 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3396 3397 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3398 3399 return 0; 3400 } 3401 3402 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3403 struct hns_roce_qp *qp, 3404 struct ib_wc *wc) 3405 { 3406 struct hns_roce_rinl_sge *sge_list; 3407 u32 wr_num, wr_cnt, sge_num; 3408 u32 sge_cnt, data_len, size; 3409 void *wqe_buf; 3410 3411 wr_num = hr_reg_read(cqe, CQE_WQE_IDX); 3412 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1); 3413 3414 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3415 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3416 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt); 3417 data_len = wc->byte_len; 3418 3419 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3420 size = min(sge_list[sge_cnt].len, data_len); 3421 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3422 3423 data_len -= size; 3424 wqe_buf += size; 3425 } 3426 3427 if (unlikely(data_len)) { 3428 wc->status = IB_WC_LOC_LEN_ERR; 3429 return -EAGAIN; 3430 } 3431 3432 return 0; 3433 } 3434 3435 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3436 int num_entries, struct ib_wc *wc) 3437 { 3438 unsigned int left; 3439 int npolled = 0; 3440 3441 left = wq->head - wq->tail; 3442 if (left == 0) 3443 return 0; 3444 3445 left = min_t(unsigned int, (unsigned int)num_entries, left); 3446 while (npolled < left) { 3447 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3448 wc->status = IB_WC_WR_FLUSH_ERR; 3449 wc->vendor_err = 0; 3450 wc->qp = &hr_qp->ibqp; 3451 3452 wq->tail++; 3453 wc++; 3454 npolled++; 3455 } 3456 3457 return npolled; 3458 } 3459 3460 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3461 struct ib_wc *wc) 3462 { 3463 struct hns_roce_qp *hr_qp; 3464 int npolled = 0; 3465 3466 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3467 npolled += sw_comp(hr_qp, &hr_qp->sq, 3468 num_entries - npolled, wc + npolled); 3469 if (npolled >= num_entries) 3470 goto out; 3471 } 3472 3473 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3474 npolled += sw_comp(hr_qp, &hr_qp->rq, 3475 num_entries - npolled, wc + npolled); 3476 if (npolled >= num_entries) 3477 goto out; 3478 } 3479 3480 out: 3481 return npolled; 3482 } 3483 3484 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3485 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3486 struct ib_wc *wc) 3487 { 3488 static const struct { 3489 u32 cqe_status; 3490 enum ib_wc_status wc_status; 3491 } map[] = { 3492 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3493 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3494 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3495 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3496 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3497 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3498 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3499 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3500 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3501 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3502 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3503 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3504 IB_WC_RETRY_EXC_ERR }, 3505 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3506 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3507 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3508 }; 3509 3510 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3511 int i; 3512 3513 wc->status = IB_WC_GENERAL_ERR; 3514 for (i = 0; i < ARRAY_SIZE(map); i++) 3515 if (cqe_status == map[i].cqe_status) { 3516 wc->status = map[i].wc_status; 3517 break; 3518 } 3519 3520 if (likely(wc->status == IB_WC_SUCCESS || 3521 wc->status == IB_WC_WR_FLUSH_ERR)) 3522 return; 3523 3524 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3525 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3526 cq->cqe_size, false); 3527 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3528 3529 /* 3530 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3531 * the standard protocol, the driver must ignore it and needn't to set 3532 * the QP to an error state. 3533 */ 3534 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3535 return; 3536 3537 flush_cqe(hr_dev, qp); 3538 } 3539 3540 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3541 struct hns_roce_qp **cur_qp) 3542 { 3543 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3544 struct hns_roce_qp *hr_qp = *cur_qp; 3545 u32 qpn; 3546 3547 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3548 3549 if (!hr_qp || qpn != hr_qp->qpn) { 3550 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3551 if (unlikely(!hr_qp)) { 3552 ibdev_err(&hr_dev->ib_dev, 3553 "CQ %06lx with entry for unknown QPN %06x\n", 3554 hr_cq->cqn, qpn); 3555 return -EINVAL; 3556 } 3557 *cur_qp = hr_qp; 3558 } 3559 3560 return 0; 3561 } 3562 3563 /* 3564 * mapped-value = 1 + real-value 3565 * The ib wc opcode's real value is start from 0, In order to distinguish 3566 * between initialized and uninitialized map values, we plus 1 to the actual 3567 * value when defining the mapping, so that the validity can be identified by 3568 * checking whether the mapped value is greater than 0. 3569 */ 3570 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3571 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3572 3573 static const u32 wc_send_op_map[] = { 3574 HR_WC_OP_MAP(SEND, SEND), 3575 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3576 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3577 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3578 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3579 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3580 HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV), 3581 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3582 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3583 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3584 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3585 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3586 HR_WC_OP_MAP(BIND_MW, REG_MR), 3587 }; 3588 3589 static int to_ib_wc_send_op(u32 hr_opcode) 3590 { 3591 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3592 return -EINVAL; 3593 3594 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3595 -EINVAL; 3596 } 3597 3598 static const u32 wc_recv_op_map[] = { 3599 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3600 HR_WC_OP_MAP(SEND, RECV), 3601 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3602 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3603 }; 3604 3605 static int to_ib_wc_recv_op(u32 hr_opcode) 3606 { 3607 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3608 return -EINVAL; 3609 3610 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3611 -EINVAL; 3612 } 3613 3614 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3615 { 3616 u32 hr_opcode; 3617 int ib_opcode; 3618 3619 wc->wc_flags = 0; 3620 3621 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3622 switch (hr_opcode) { 3623 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3624 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3625 break; 3626 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3627 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3628 wc->wc_flags |= IB_WC_WITH_IMM; 3629 break; 3630 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3631 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3632 break; 3633 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3634 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3635 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3636 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3637 wc->byte_len = 8; 3638 break; 3639 default: 3640 break; 3641 } 3642 3643 ib_opcode = to_ib_wc_send_op(hr_opcode); 3644 if (ib_opcode < 0) 3645 wc->status = IB_WC_GENERAL_ERR; 3646 else 3647 wc->opcode = ib_opcode; 3648 } 3649 3650 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode, 3651 struct hns_roce_v2_cqe *cqe) 3652 { 3653 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI && 3654 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND || 3655 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3656 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3657 hr_reg_read(cqe, CQE_RQ_INLINE); 3658 } 3659 3660 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3661 { 3662 struct hns_roce_qp *qp = to_hr_qp(wc->qp); 3663 u32 hr_opcode; 3664 int ib_opcode; 3665 int ret; 3666 3667 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3668 3669 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3670 switch (hr_opcode) { 3671 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3672 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3673 wc->wc_flags = IB_WC_WITH_IMM; 3674 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3675 break; 3676 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3677 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3678 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3679 break; 3680 default: 3681 wc->wc_flags = 0; 3682 } 3683 3684 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3685 if (ib_opcode < 0) 3686 wc->status = IB_WC_GENERAL_ERR; 3687 else 3688 wc->opcode = ib_opcode; 3689 3690 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) { 3691 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc); 3692 if (unlikely(ret)) 3693 return ret; 3694 } 3695 3696 wc->sl = hr_reg_read(cqe, CQE_SL); 3697 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3698 wc->slid = 0; 3699 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3700 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3701 wc->pkey_index = 0; 3702 3703 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3704 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3705 wc->wc_flags |= IB_WC_WITH_VLAN; 3706 } else { 3707 wc->vlan_id = 0xffff; 3708 } 3709 3710 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3711 3712 return 0; 3713 } 3714 3715 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3716 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3717 { 3718 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3719 struct hns_roce_qp *qp = *cur_qp; 3720 struct hns_roce_srq *srq = NULL; 3721 struct hns_roce_v2_cqe *cqe; 3722 struct hns_roce_wq *wq; 3723 int is_send; 3724 u16 wqe_idx; 3725 int ret; 3726 3727 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3728 if (!cqe) 3729 return -EAGAIN; 3730 3731 ++hr_cq->cons_index; 3732 /* Memory barrier */ 3733 rmb(); 3734 3735 ret = get_cur_qp(hr_cq, cqe, &qp); 3736 if (ret) 3737 return ret; 3738 3739 wc->qp = &qp->ibqp; 3740 wc->vendor_err = 0; 3741 3742 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3743 3744 is_send = !hr_reg_read(cqe, CQE_S_R); 3745 if (is_send) { 3746 wq = &qp->sq; 3747 3748 /* If sg_signal_bit is set, tail pointer will be updated to 3749 * the WQE corresponding to the current CQE. 3750 */ 3751 if (qp->sq_signal_bits) 3752 wq->tail += (wqe_idx - (u16)wq->tail) & 3753 (wq->wqe_cnt - 1); 3754 3755 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3756 ++wq->tail; 3757 3758 fill_send_wc(wc, cqe); 3759 } else { 3760 if (qp->ibqp.srq) { 3761 srq = to_hr_srq(qp->ibqp.srq); 3762 wc->wr_id = srq->wrid[wqe_idx]; 3763 hns_roce_free_srq_wqe(srq, wqe_idx); 3764 } else { 3765 wq = &qp->rq; 3766 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3767 ++wq->tail; 3768 } 3769 3770 ret = fill_recv_wc(wc, cqe); 3771 } 3772 3773 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3774 if (unlikely(wc->status != IB_WC_SUCCESS)) 3775 return 0; 3776 3777 return ret; 3778 } 3779 3780 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3781 struct ib_wc *wc) 3782 { 3783 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3784 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3785 struct hns_roce_qp *cur_qp = NULL; 3786 unsigned long flags; 3787 int npolled; 3788 3789 spin_lock_irqsave(&hr_cq->lock, flags); 3790 3791 /* 3792 * When the device starts to reset, the state is RST_DOWN. At this time, 3793 * there may still be some valid CQEs in the hardware that are not 3794 * polled. Therefore, it is not allowed to switch to the software mode 3795 * immediately. When the state changes to UNINIT, CQE no longer exists 3796 * in the hardware, and then switch to software mode. 3797 */ 3798 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3799 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3800 goto out; 3801 } 3802 3803 for (npolled = 0; npolled < num_entries; ++npolled) { 3804 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3805 break; 3806 } 3807 3808 if (npolled) 3809 update_cq_db(hr_dev, hr_cq); 3810 3811 out: 3812 spin_unlock_irqrestore(&hr_cq->lock, flags); 3813 3814 return npolled; 3815 } 3816 3817 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3818 int step_idx, u16 *mbox_op) 3819 { 3820 u16 op; 3821 3822 switch (type) { 3823 case HEM_TYPE_QPC: 3824 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3825 break; 3826 case HEM_TYPE_MTPT: 3827 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3828 break; 3829 case HEM_TYPE_CQC: 3830 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3831 break; 3832 case HEM_TYPE_SRQC: 3833 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3834 break; 3835 case HEM_TYPE_SCCC: 3836 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3837 break; 3838 case HEM_TYPE_QPC_TIMER: 3839 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3840 break; 3841 case HEM_TYPE_CQC_TIMER: 3842 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3843 break; 3844 default: 3845 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 3846 return -EINVAL; 3847 } 3848 3849 *mbox_op = op + step_idx; 3850 3851 return 0; 3852 } 3853 3854 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 3855 dma_addr_t base_addr) 3856 { 3857 struct hns_roce_cmq_desc desc; 3858 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 3859 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 3860 u64 addr = to_hr_hw_page_addr(base_addr); 3861 3862 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 3863 3864 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 3865 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 3866 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 3867 3868 return hns_roce_cmq_send(hr_dev, &desc, 1); 3869 } 3870 3871 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 3872 dma_addr_t base_addr, u32 hem_type, int step_idx) 3873 { 3874 int ret; 3875 u16 op; 3876 3877 if (unlikely(hem_type == HEM_TYPE_GMV)) 3878 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 3879 3880 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 3881 return 0; 3882 3883 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op); 3884 if (ret < 0) 3885 return ret; 3886 3887 return config_hem_ba_to_hw(hr_dev, obj, base_addr, op); 3888 } 3889 3890 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3891 struct hns_roce_hem_table *table, int obj, 3892 int step_idx) 3893 { 3894 struct hns_roce_hem_iter iter; 3895 struct hns_roce_hem_mhop mhop; 3896 struct hns_roce_hem *hem; 3897 unsigned long mhop_obj = obj; 3898 int i, j, k; 3899 int ret = 0; 3900 u64 hem_idx = 0; 3901 u64 l1_idx = 0; 3902 u64 bt_ba = 0; 3903 u32 chunk_ba_num; 3904 u32 hop_num; 3905 3906 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3907 return 0; 3908 3909 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3910 i = mhop.l0_idx; 3911 j = mhop.l1_idx; 3912 k = mhop.l2_idx; 3913 hop_num = mhop.hop_num; 3914 chunk_ba_num = mhop.bt_chunk_size / 8; 3915 3916 if (hop_num == 2) { 3917 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3918 k; 3919 l1_idx = i * chunk_ba_num + j; 3920 } else if (hop_num == 1) { 3921 hem_idx = i * chunk_ba_num + j; 3922 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3923 hem_idx = i; 3924 } 3925 3926 if (table->type == HEM_TYPE_SCCC) 3927 obj = mhop.l0_idx; 3928 3929 if (check_whether_last_step(hop_num, step_idx)) { 3930 hem = table->hem[hem_idx]; 3931 for (hns_roce_hem_first(hem, &iter); 3932 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3933 bt_ba = hns_roce_hem_addr(&iter); 3934 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3935 step_idx); 3936 } 3937 } else { 3938 if (step_idx == 0) 3939 bt_ba = table->bt_l0_dma_addr[i]; 3940 else if (step_idx == 1 && hop_num == 2) 3941 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3942 3943 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3944 } 3945 3946 return ret; 3947 } 3948 3949 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3950 struct hns_roce_hem_table *table, int obj, 3951 int step_idx) 3952 { 3953 struct device *dev = hr_dev->dev; 3954 struct hns_roce_cmd_mailbox *mailbox; 3955 int ret; 3956 u16 op = 0xff; 3957 3958 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3959 return 0; 3960 3961 switch (table->type) { 3962 case HEM_TYPE_QPC: 3963 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3964 break; 3965 case HEM_TYPE_MTPT: 3966 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3967 break; 3968 case HEM_TYPE_CQC: 3969 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3970 break; 3971 case HEM_TYPE_SRQC: 3972 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3973 break; 3974 case HEM_TYPE_SCCC: 3975 case HEM_TYPE_QPC_TIMER: 3976 case HEM_TYPE_CQC_TIMER: 3977 case HEM_TYPE_GMV: 3978 return 0; 3979 default: 3980 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 3981 table->type); 3982 return 0; 3983 } 3984 3985 op += step_idx; 3986 3987 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3988 if (IS_ERR(mailbox)) 3989 return PTR_ERR(mailbox); 3990 3991 /* configure the tag and op */ 3992 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3993 HNS_ROCE_CMD_TIMEOUT_MSECS); 3994 3995 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3996 return ret; 3997 } 3998 3999 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 4000 struct hns_roce_v2_qp_context *context, 4001 struct hns_roce_v2_qp_context *qpc_mask, 4002 struct hns_roce_qp *hr_qp) 4003 { 4004 struct hns_roce_cmd_mailbox *mailbox; 4005 int qpc_size; 4006 int ret; 4007 4008 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4009 if (IS_ERR(mailbox)) 4010 return PTR_ERR(mailbox); 4011 4012 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 4013 qpc_size = hr_dev->caps.qpc_sz; 4014 memcpy(mailbox->buf, context, qpc_size); 4015 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4016 4017 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 4018 HNS_ROCE_CMD_MODIFY_QPC, 4019 HNS_ROCE_CMD_TIMEOUT_MSECS); 4020 4021 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4022 4023 return ret; 4024 } 4025 4026 static void set_access_flags(struct hns_roce_qp *hr_qp, 4027 struct hns_roce_v2_qp_context *context, 4028 struct hns_roce_v2_qp_context *qpc_mask, 4029 const struct ib_qp_attr *attr, int attr_mask) 4030 { 4031 u8 dest_rd_atomic; 4032 u32 access_flags; 4033 4034 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4035 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4036 4037 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4038 attr->qp_access_flags : hr_qp->atomic_rd_en; 4039 4040 if (!dest_rd_atomic) 4041 access_flags &= IB_ACCESS_REMOTE_WRITE; 4042 4043 hr_reg_write_bool(context, QPC_RRE, 4044 access_flags & IB_ACCESS_REMOTE_READ); 4045 hr_reg_clear(qpc_mask, QPC_RRE); 4046 4047 hr_reg_write_bool(context, QPC_RWE, 4048 access_flags & IB_ACCESS_REMOTE_WRITE); 4049 hr_reg_clear(qpc_mask, QPC_RWE); 4050 4051 hr_reg_write_bool(context, QPC_ATE, 4052 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4053 hr_reg_clear(qpc_mask, QPC_ATE); 4054 hr_reg_write_bool(context, QPC_EXT_ATE, 4055 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4056 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4057 } 4058 4059 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4060 struct hns_roce_v2_qp_context *context, 4061 struct hns_roce_v2_qp_context *qpc_mask) 4062 { 4063 hr_reg_write(context, QPC_SGE_SHIFT, 4064 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4065 hr_qp->sge.sge_shift)); 4066 4067 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4068 4069 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4070 } 4071 4072 static inline int get_cqn(struct ib_cq *ib_cq) 4073 { 4074 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4075 } 4076 4077 static inline int get_pdn(struct ib_pd *ib_pd) 4078 { 4079 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4080 } 4081 4082 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4083 const struct ib_qp_attr *attr, 4084 int attr_mask, 4085 struct hns_roce_v2_qp_context *context, 4086 struct hns_roce_v2_qp_context *qpc_mask) 4087 { 4088 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4089 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4090 4091 /* 4092 * In v2 engine, software pass context and context mask to hardware 4093 * when modifying qp. If software need modify some fields in context, 4094 * we should set all bits of the relevant fields in context mask to 4095 * 0 at the same time, else set them to 0x1. 4096 */ 4097 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4098 4099 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4100 4101 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4102 4103 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4104 4105 /* No VLAN need to set 0xFFF */ 4106 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4107 4108 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4109 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4110 4111 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4112 } 4113 4114 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4115 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4116 4117 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4118 hr_reg_enable(context, QPC_OWNER_MODE); 4119 4120 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4121 lower_32_bits(hr_qp->rdb.dma) >> 1); 4122 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4123 upper_32_bits(hr_qp->rdb.dma)); 4124 4125 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI) 4126 hr_reg_write_bool(context, QPC_RQIE, 4127 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE); 4128 4129 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4130 4131 if (ibqp->srq) { 4132 hr_reg_enable(context, QPC_SRQ_EN); 4133 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4134 } 4135 4136 hr_reg_enable(context, QPC_FRE); 4137 4138 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4139 4140 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4141 return; 4142 4143 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4144 hr_reg_enable(&context->ext, QPCEX_STASH); 4145 } 4146 4147 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4148 const struct ib_qp_attr *attr, int attr_mask, 4149 struct hns_roce_v2_qp_context *context, 4150 struct hns_roce_v2_qp_context *qpc_mask) 4151 { 4152 /* 4153 * In v2 engine, software pass context and context mask to hardware 4154 * when modifying qp. If software need modify some fields in context, 4155 * we should set all bits of the relevant fields in context mask to 4156 * 0 at the same time, else set them to 0x1. 4157 */ 4158 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4159 hr_reg_clear(qpc_mask, QPC_TST); 4160 4161 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4162 hr_reg_clear(qpc_mask, QPC_PD); 4163 4164 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4165 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4166 4167 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4168 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4169 4170 if (ibqp->srq) { 4171 hr_reg_enable(context, QPC_SRQ_EN); 4172 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4173 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4174 hr_reg_clear(qpc_mask, QPC_SRQN); 4175 } 4176 } 4177 4178 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4179 struct hns_roce_qp *hr_qp, 4180 struct hns_roce_v2_qp_context *context, 4181 struct hns_roce_v2_qp_context *qpc_mask) 4182 { 4183 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4184 u64 wqe_sge_ba; 4185 int count; 4186 4187 /* Search qp buf's mtts */ 4188 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4189 MTT_MIN_COUNT, &wqe_sge_ba); 4190 if (hr_qp->rq.wqe_cnt && count < 1) { 4191 ibdev_err(&hr_dev->ib_dev, 4192 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4193 return -EINVAL; 4194 } 4195 4196 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4197 qpc_mask->wqe_sge_ba = 0; 4198 4199 /* 4200 * In v2 engine, software pass context and context mask to hardware 4201 * when modifying qp. If software need modify some fields in context, 4202 * we should set all bits of the relevant fields in context mask to 4203 * 0 at the same time, else set them to 0x1. 4204 */ 4205 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4206 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4207 4208 hr_reg_write(context, QPC_SQ_HOP_NUM, 4209 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4210 hr_qp->sq.wqe_cnt)); 4211 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4212 4213 hr_reg_write(context, QPC_SGE_HOP_NUM, 4214 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4215 hr_qp->sge.sge_cnt)); 4216 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4217 4218 hr_reg_write(context, QPC_RQ_HOP_NUM, 4219 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4220 hr_qp->rq.wqe_cnt)); 4221 4222 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4223 4224 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4225 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4226 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4227 4228 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4229 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4230 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4231 4232 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4233 qpc_mask->rq_cur_blk_addr = 0; 4234 4235 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4236 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4237 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4238 4239 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4240 qpc_mask->rq_nxt_blk_addr = 0; 4241 4242 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4243 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4244 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4245 4246 return 0; 4247 } 4248 4249 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4250 struct hns_roce_qp *hr_qp, 4251 struct hns_roce_v2_qp_context *context, 4252 struct hns_roce_v2_qp_context *qpc_mask) 4253 { 4254 struct ib_device *ibdev = &hr_dev->ib_dev; 4255 u64 sge_cur_blk = 0; 4256 u64 sq_cur_blk = 0; 4257 int count; 4258 4259 /* search qp buf's mtts */ 4260 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4261 if (count < 1) { 4262 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4263 hr_qp->qpn); 4264 return -EINVAL; 4265 } 4266 if (hr_qp->sge.sge_cnt > 0) { 4267 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4268 hr_qp->sge.offset, 4269 &sge_cur_blk, 1, NULL); 4270 if (count < 1) { 4271 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4272 hr_qp->qpn); 4273 return -EINVAL; 4274 } 4275 } 4276 4277 /* 4278 * In v2 engine, software pass context and context mask to hardware 4279 * when modifying qp. If software need modify some fields in context, 4280 * we should set all bits of the relevant fields in context mask to 4281 * 0 at the same time, else set them to 0x1. 4282 */ 4283 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4284 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4285 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4286 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4287 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4288 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4289 4290 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4291 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4292 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4293 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4294 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4295 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4296 4297 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4298 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4299 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4300 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4301 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4302 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4303 4304 return 0; 4305 } 4306 4307 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4308 const struct ib_qp_attr *attr) 4309 { 4310 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4311 return IB_MTU_4096; 4312 4313 return attr->path_mtu; 4314 } 4315 4316 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4317 const struct ib_qp_attr *attr, int attr_mask, 4318 struct hns_roce_v2_qp_context *context, 4319 struct hns_roce_v2_qp_context *qpc_mask) 4320 { 4321 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4322 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4323 struct ib_device *ibdev = &hr_dev->ib_dev; 4324 dma_addr_t trrl_ba; 4325 dma_addr_t irrl_ba; 4326 enum ib_mtu ib_mtu; 4327 const u8 *smac; 4328 u8 lp_pktn_ini; 4329 u64 *mtts; 4330 u8 *dmac; 4331 u32 port; 4332 int mtu; 4333 int ret; 4334 4335 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4336 if (ret) { 4337 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4338 return ret; 4339 } 4340 4341 /* Search IRRL's mtts */ 4342 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4343 hr_qp->qpn, &irrl_ba); 4344 if (!mtts) { 4345 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4346 return -EINVAL; 4347 } 4348 4349 /* Search TRRL's mtts */ 4350 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4351 hr_qp->qpn, &trrl_ba); 4352 if (!mtts) { 4353 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4354 return -EINVAL; 4355 } 4356 4357 if (attr_mask & IB_QP_ALT_PATH) { 4358 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4359 attr_mask); 4360 return -EINVAL; 4361 } 4362 4363 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4364 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4365 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4366 qpc_mask->trrl_ba = 0; 4367 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4368 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4369 4370 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4371 qpc_mask->irrl_ba = 0; 4372 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4373 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4374 4375 hr_reg_enable(context, QPC_RMT_E2E); 4376 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4377 4378 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4379 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4380 4381 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4382 4383 smac = (const u8 *)hr_dev->dev_addr[port]; 4384 dmac = (u8 *)attr->ah_attr.roce.dmac; 4385 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4386 if (ether_addr_equal_unaligned(dmac, smac) || 4387 hr_dev->loop_idc == 0x1) { 4388 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4389 hr_reg_clear(qpc_mask, QPC_LBI); 4390 } 4391 4392 if (attr_mask & IB_QP_DEST_QPN) { 4393 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4394 hr_reg_clear(qpc_mask, QPC_DQPN); 4395 } 4396 4397 memcpy(&(context->dmac), dmac, sizeof(u32)); 4398 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4399 qpc_mask->dmac = 0; 4400 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4401 4402 ib_mtu = get_mtu(ibqp, attr); 4403 hr_qp->path_mtu = ib_mtu; 4404 4405 mtu = ib_mtu_enum_to_int(ib_mtu); 4406 if (WARN_ON(mtu <= 0)) 4407 return -EINVAL; 4408 #define MAX_LP_MSG_LEN 16384 4409 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */ 4410 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4411 if (WARN_ON(lp_pktn_ini >= 0xF)) 4412 return -EINVAL; 4413 4414 if (attr_mask & IB_QP_PATH_MTU) { 4415 hr_reg_write(context, QPC_MTU, ib_mtu); 4416 hr_reg_clear(qpc_mask, QPC_MTU); 4417 } 4418 4419 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4420 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4421 4422 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4423 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4424 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4425 4426 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4427 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4428 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4429 4430 context->rq_rnr_timer = 0; 4431 qpc_mask->rq_rnr_timer = 0; 4432 4433 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4434 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4435 4436 /* rocee send 2^lp_sgen_ini segs every time */ 4437 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4438 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4439 4440 return 0; 4441 } 4442 4443 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4444 const struct ib_qp_attr *attr, int attr_mask, 4445 struct hns_roce_v2_qp_context *context, 4446 struct hns_roce_v2_qp_context *qpc_mask) 4447 { 4448 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4449 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4450 struct ib_device *ibdev = &hr_dev->ib_dev; 4451 int ret; 4452 4453 /* Not support alternate path and path migration */ 4454 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4455 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4456 return -EINVAL; 4457 } 4458 4459 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4460 if (ret) { 4461 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4462 return ret; 4463 } 4464 4465 /* 4466 * Set some fields in context to zero, Because the default values 4467 * of all fields in context are zero, we need not set them to 0 again. 4468 * but we should set the relevant fields of context mask to 0. 4469 */ 4470 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4471 4472 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4473 4474 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4475 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4476 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4477 4478 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4479 4480 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4481 4482 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4483 4484 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4485 4486 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4487 4488 return 0; 4489 } 4490 4491 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn) 4492 { 4493 if (!fl) 4494 fl = rdma_calc_flow_label(lqpn, rqpn); 4495 4496 return rdma_flow_label_to_udp_sport(fl); 4497 } 4498 4499 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4500 u32 *dip_idx) 4501 { 4502 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4503 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4504 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4505 u32 *head = &hr_dev->qp_table.idx_table.head; 4506 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4507 struct hns_roce_dip *hr_dip; 4508 unsigned long flags; 4509 int ret = 0; 4510 4511 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4512 4513 spare_idx[*tail] = ibqp->qp_num; 4514 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4515 4516 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4517 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4518 *dip_idx = hr_dip->dip_idx; 4519 goto out; 4520 } 4521 } 4522 4523 /* If no dgid is found, a new dip and a mapping between dgid and 4524 * dip_idx will be created. 4525 */ 4526 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4527 if (!hr_dip) { 4528 ret = -ENOMEM; 4529 goto out; 4530 } 4531 4532 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4533 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4534 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4535 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4536 4537 out: 4538 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4539 return ret; 4540 } 4541 4542 enum { 4543 CONG_DCQCN, 4544 CONG_WINDOW, 4545 }; 4546 4547 enum { 4548 UNSUPPORT_CONG_LEVEL, 4549 SUPPORT_CONG_LEVEL, 4550 }; 4551 4552 enum { 4553 CONG_LDCP, 4554 CONG_HC3, 4555 }; 4556 4557 enum { 4558 DIP_INVALID, 4559 DIP_VALID, 4560 }; 4561 4562 enum { 4563 WND_LIMIT, 4564 WND_UNLIMIT, 4565 }; 4566 4567 static int check_cong_type(struct ib_qp *ibqp, 4568 struct hns_roce_congestion_algorithm *cong_alg) 4569 { 4570 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4571 4572 /* different congestion types match different configurations */ 4573 switch (hr_dev->caps.cong_type) { 4574 case CONG_TYPE_DCQCN: 4575 cong_alg->alg_sel = CONG_DCQCN; 4576 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4577 cong_alg->dip_vld = DIP_INVALID; 4578 cong_alg->wnd_mode_sel = WND_LIMIT; 4579 break; 4580 case CONG_TYPE_LDCP: 4581 cong_alg->alg_sel = CONG_WINDOW; 4582 cong_alg->alg_sub_sel = CONG_LDCP; 4583 cong_alg->dip_vld = DIP_INVALID; 4584 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4585 break; 4586 case CONG_TYPE_HC3: 4587 cong_alg->alg_sel = CONG_WINDOW; 4588 cong_alg->alg_sub_sel = CONG_HC3; 4589 cong_alg->dip_vld = DIP_INVALID; 4590 cong_alg->wnd_mode_sel = WND_LIMIT; 4591 break; 4592 case CONG_TYPE_DIP: 4593 cong_alg->alg_sel = CONG_DCQCN; 4594 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4595 cong_alg->dip_vld = DIP_VALID; 4596 cong_alg->wnd_mode_sel = WND_LIMIT; 4597 break; 4598 default: 4599 ibdev_err(&hr_dev->ib_dev, 4600 "error type(%u) for congestion selection.\n", 4601 hr_dev->caps.cong_type); 4602 return -EINVAL; 4603 } 4604 4605 return 0; 4606 } 4607 4608 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4609 struct hns_roce_v2_qp_context *context, 4610 struct hns_roce_v2_qp_context *qpc_mask) 4611 { 4612 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4613 struct hns_roce_congestion_algorithm cong_field; 4614 struct ib_device *ibdev = ibqp->device; 4615 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4616 u32 dip_idx = 0; 4617 int ret; 4618 4619 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4620 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4621 return 0; 4622 4623 ret = check_cong_type(ibqp, &cong_field); 4624 if (ret) 4625 return ret; 4626 4627 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4628 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4629 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4630 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4631 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4632 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4633 cong_field.alg_sub_sel); 4634 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4635 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4636 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4637 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4638 cong_field.wnd_mode_sel); 4639 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4640 4641 /* if dip is disabled, there is no need to set dip idx */ 4642 if (cong_field.dip_vld == 0) 4643 return 0; 4644 4645 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4646 if (ret) { 4647 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4648 return ret; 4649 } 4650 4651 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4652 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4653 4654 return 0; 4655 } 4656 4657 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4658 const struct ib_qp_attr *attr, 4659 int attr_mask, 4660 struct hns_roce_v2_qp_context *context, 4661 struct hns_roce_v2_qp_context *qpc_mask) 4662 { 4663 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4664 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4665 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4666 struct ib_device *ibdev = &hr_dev->ib_dev; 4667 const struct ib_gid_attr *gid_attr = NULL; 4668 int is_roce_protocol; 4669 u16 vlan_id = 0xffff; 4670 bool is_udp = false; 4671 u8 ib_port; 4672 u8 hr_port; 4673 int ret; 4674 4675 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4676 hr_port = ib_port - 1; 4677 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4678 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4679 4680 if (is_roce_protocol) { 4681 gid_attr = attr->ah_attr.grh.sgid_attr; 4682 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4683 if (ret) 4684 return ret; 4685 4686 if (gid_attr) 4687 is_udp = (gid_attr->gid_type == 4688 IB_GID_TYPE_ROCE_UDP_ENCAP); 4689 } 4690 4691 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4692 if (vlan_id < VLAN_N_VID && 4693 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4694 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4695 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4696 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4697 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4698 } 4699 4700 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4701 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4702 4703 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4704 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4705 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4706 return -EINVAL; 4707 } 4708 4709 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4710 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4711 return -EINVAL; 4712 } 4713 4714 hr_reg_write(context, QPC_UDPSPN, 4715 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num, 4716 attr->dest_qp_num) : 0); 4717 4718 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4719 4720 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4721 4722 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4723 4724 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4725 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4726 4727 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4728 if (ret) 4729 return ret; 4730 4731 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4732 hr_reg_clear(qpc_mask, QPC_TC); 4733 4734 hr_reg_write(context, QPC_FL, grh->flow_label); 4735 hr_reg_clear(qpc_mask, QPC_FL); 4736 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4737 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4738 4739 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4740 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4741 ibdev_err(ibdev, 4742 "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n", 4743 hr_qp->sl, MAX_SERVICE_LEVEL); 4744 return -EINVAL; 4745 } 4746 4747 hr_reg_write(context, QPC_SL, hr_qp->sl); 4748 hr_reg_clear(qpc_mask, QPC_SL); 4749 4750 return 0; 4751 } 4752 4753 static bool check_qp_state(enum ib_qp_state cur_state, 4754 enum ib_qp_state new_state) 4755 { 4756 static const bool sm[][IB_QPS_ERR + 1] = { 4757 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4758 [IB_QPS_INIT] = true }, 4759 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4760 [IB_QPS_INIT] = true, 4761 [IB_QPS_RTR] = true, 4762 [IB_QPS_ERR] = true }, 4763 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4764 [IB_QPS_RTS] = true, 4765 [IB_QPS_ERR] = true }, 4766 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4767 [IB_QPS_RTS] = true, 4768 [IB_QPS_ERR] = true }, 4769 [IB_QPS_SQD] = {}, 4770 [IB_QPS_SQE] = {}, 4771 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4772 }; 4773 4774 return sm[cur_state][new_state]; 4775 } 4776 4777 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4778 const struct ib_qp_attr *attr, 4779 int attr_mask, 4780 enum ib_qp_state cur_state, 4781 enum ib_qp_state new_state, 4782 struct hns_roce_v2_qp_context *context, 4783 struct hns_roce_v2_qp_context *qpc_mask) 4784 { 4785 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4786 int ret = 0; 4787 4788 if (!check_qp_state(cur_state, new_state)) { 4789 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4790 return -EINVAL; 4791 } 4792 4793 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4794 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4795 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4796 qpc_mask); 4797 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4798 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4799 qpc_mask); 4800 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4801 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4802 qpc_mask); 4803 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4804 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4805 qpc_mask); 4806 } 4807 4808 return ret; 4809 } 4810 4811 static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) 4812 { 4813 #define QP_ACK_TIMEOUT_MAX_HIP08 20 4814 #define QP_ACK_TIMEOUT_OFFSET 10 4815 #define QP_ACK_TIMEOUT_MAX 31 4816 4817 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4818 if (*timeout > QP_ACK_TIMEOUT_MAX_HIP08) { 4819 ibdev_warn(&hr_dev->ib_dev, 4820 "Local ACK timeout shall be 0 to 20.\n"); 4821 return false; 4822 } 4823 *timeout += QP_ACK_TIMEOUT_OFFSET; 4824 } else if (hr_dev->pci_dev->revision > PCI_REVISION_ID_HIP08) { 4825 if (*timeout > QP_ACK_TIMEOUT_MAX) { 4826 ibdev_warn(&hr_dev->ib_dev, 4827 "Local ACK timeout shall be 0 to 31.\n"); 4828 return false; 4829 } 4830 } 4831 4832 return true; 4833 } 4834 4835 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4836 const struct ib_qp_attr *attr, 4837 int attr_mask, 4838 struct hns_roce_v2_qp_context *context, 4839 struct hns_roce_v2_qp_context *qpc_mask) 4840 { 4841 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4842 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4843 int ret = 0; 4844 u8 timeout; 4845 4846 if (attr_mask & IB_QP_AV) { 4847 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4848 qpc_mask); 4849 if (ret) 4850 return ret; 4851 } 4852 4853 if (attr_mask & IB_QP_TIMEOUT) { 4854 timeout = attr->timeout; 4855 if (check_qp_timeout_cfg_range(hr_dev, &timeout)) { 4856 hr_reg_write(context, QPC_AT, timeout); 4857 hr_reg_clear(qpc_mask, QPC_AT); 4858 } 4859 } 4860 4861 if (attr_mask & IB_QP_RETRY_CNT) { 4862 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 4863 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 4864 4865 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 4866 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 4867 } 4868 4869 if (attr_mask & IB_QP_RNR_RETRY) { 4870 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 4871 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 4872 4873 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 4874 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 4875 } 4876 4877 if (attr_mask & IB_QP_SQ_PSN) { 4878 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 4879 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 4880 4881 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 4882 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 4883 4884 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 4885 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 4886 4887 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 4888 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 4889 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 4890 4891 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 4892 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 4893 4894 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 4895 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 4896 } 4897 4898 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4899 attr->max_dest_rd_atomic) { 4900 hr_reg_write(context, QPC_RR_MAX, 4901 fls(attr->max_dest_rd_atomic - 1)); 4902 hr_reg_clear(qpc_mask, QPC_RR_MAX); 4903 } 4904 4905 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4906 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 4907 hr_reg_clear(qpc_mask, QPC_SR_MAX); 4908 } 4909 4910 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4911 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4912 4913 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4914 hr_reg_write(context, QPC_MIN_RNR_TIME, 4915 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 ? 4916 HNS_ROCE_RNR_TIMER_10NS : attr->min_rnr_timer); 4917 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 4918 } 4919 4920 if (attr_mask & IB_QP_RQ_PSN) { 4921 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 4922 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 4923 4924 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 4925 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 4926 } 4927 4928 if (attr_mask & IB_QP_QKEY) { 4929 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4930 qpc_mask->qkey_xrcd = 0; 4931 hr_qp->qkey = attr->qkey; 4932 } 4933 4934 return ret; 4935 } 4936 4937 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4938 const struct ib_qp_attr *attr, 4939 int attr_mask) 4940 { 4941 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4942 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4943 4944 if (attr_mask & IB_QP_ACCESS_FLAGS) 4945 hr_qp->atomic_rd_en = attr->qp_access_flags; 4946 4947 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4948 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4949 if (attr_mask & IB_QP_PORT) { 4950 hr_qp->port = attr->port_num - 1; 4951 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4952 } 4953 } 4954 4955 static void clear_qp(struct hns_roce_qp *hr_qp) 4956 { 4957 struct ib_qp *ibqp = &hr_qp->ibqp; 4958 4959 if (ibqp->send_cq) 4960 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4961 hr_qp->qpn, NULL); 4962 4963 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 4964 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 4965 hr_qp->qpn, ibqp->srq ? 4966 to_hr_srq(ibqp->srq) : NULL); 4967 4968 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4969 *hr_qp->rdb.db_record = 0; 4970 4971 hr_qp->rq.head = 0; 4972 hr_qp->rq.tail = 0; 4973 hr_qp->sq.head = 0; 4974 hr_qp->sq.tail = 0; 4975 hr_qp->next_sge = 0; 4976 } 4977 4978 static void v2_set_flushed_fields(struct ib_qp *ibqp, 4979 struct hns_roce_v2_qp_context *context, 4980 struct hns_roce_v2_qp_context *qpc_mask) 4981 { 4982 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4983 unsigned long sq_flag = 0; 4984 unsigned long rq_flag = 0; 4985 4986 if (ibqp->qp_type == IB_QPT_XRC_TGT) 4987 return; 4988 4989 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4990 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 4991 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 4992 hr_qp->state = IB_QPS_ERR; 4993 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4994 4995 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 4996 return; 4997 4998 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4999 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 5000 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 5001 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 5002 } 5003 5004 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 5005 const struct ib_qp_attr *attr, 5006 int attr_mask, enum ib_qp_state cur_state, 5007 enum ib_qp_state new_state) 5008 { 5009 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5010 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5011 struct hns_roce_v2_qp_context ctx[2]; 5012 struct hns_roce_v2_qp_context *context = ctx; 5013 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 5014 struct ib_device *ibdev = &hr_dev->ib_dev; 5015 int ret; 5016 5017 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 5018 return -EOPNOTSUPP; 5019 5020 /* 5021 * In v2 engine, software pass context and context mask to hardware 5022 * when modifying qp. If software need modify some fields in context, 5023 * we should set all bits of the relevant fields in context mask to 5024 * 0 at the same time, else set them to 0x1. 5025 */ 5026 memset(context, 0, hr_dev->caps.qpc_sz); 5027 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 5028 5029 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 5030 new_state, context, qpc_mask); 5031 if (ret) 5032 goto out; 5033 5034 /* When QP state is err, SQ and RQ WQE should be flushed */ 5035 if (new_state == IB_QPS_ERR) 5036 v2_set_flushed_fields(ibqp, context, qpc_mask); 5037 5038 /* Configure the optional fields */ 5039 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 5040 qpc_mask); 5041 if (ret) 5042 goto out; 5043 5044 hr_reg_write_bool(context, QPC_INV_CREDIT, 5045 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5046 ibqp->srq); 5047 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5048 5049 /* Every status migrate must change state */ 5050 hr_reg_write(context, QPC_QP_ST, new_state); 5051 hr_reg_clear(qpc_mask, QPC_QP_ST); 5052 5053 /* SW pass context to HW */ 5054 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5055 if (ret) { 5056 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5057 goto out; 5058 } 5059 5060 hr_qp->state = new_state; 5061 5062 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5063 5064 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5065 clear_qp(hr_qp); 5066 5067 out: 5068 return ret; 5069 } 5070 5071 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5072 { 5073 static const enum ib_qp_state map[] = { 5074 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5075 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5076 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5077 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5078 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5079 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5080 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5081 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5082 }; 5083 5084 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5085 } 5086 5087 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 5088 struct hns_roce_qp *hr_qp, 5089 struct hns_roce_v2_qp_context *hr_context) 5090 { 5091 struct hns_roce_cmd_mailbox *mailbox; 5092 int ret; 5093 5094 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5095 if (IS_ERR(mailbox)) 5096 return PTR_ERR(mailbox); 5097 5098 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 5099 HNS_ROCE_CMD_QUERY_QPC, 5100 HNS_ROCE_CMD_TIMEOUT_MSECS); 5101 if (ret) 5102 goto out; 5103 5104 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz); 5105 5106 out: 5107 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5108 return ret; 5109 } 5110 5111 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5112 int qp_attr_mask, 5113 struct ib_qp_init_attr *qp_init_attr) 5114 { 5115 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5116 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5117 struct hns_roce_v2_qp_context context = {}; 5118 struct ib_device *ibdev = &hr_dev->ib_dev; 5119 int tmp_qp_state; 5120 int state; 5121 int ret; 5122 5123 memset(qp_attr, 0, sizeof(*qp_attr)); 5124 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5125 5126 mutex_lock(&hr_qp->mutex); 5127 5128 if (hr_qp->state == IB_QPS_RESET) { 5129 qp_attr->qp_state = IB_QPS_RESET; 5130 ret = 0; 5131 goto done; 5132 } 5133 5134 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 5135 if (ret) { 5136 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5137 ret = -EINVAL; 5138 goto out; 5139 } 5140 5141 state = hr_reg_read(&context, QPC_QP_ST); 5142 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5143 if (tmp_qp_state == -1) { 5144 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5145 ret = -EINVAL; 5146 goto out; 5147 } 5148 hr_qp->state = (u8)tmp_qp_state; 5149 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5150 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5151 qp_attr->path_mig_state = IB_MIG_ARMED; 5152 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5153 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5154 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5155 5156 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5157 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5158 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5159 qp_attr->qp_access_flags = 5160 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5161 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5162 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5163 5164 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5165 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5166 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5167 struct ib_global_route *grh = 5168 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5169 5170 rdma_ah_set_sl(&qp_attr->ah_attr, 5171 hr_reg_read(&context, QPC_SL)); 5172 grh->flow_label = hr_reg_read(&context, QPC_FL); 5173 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5174 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5175 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5176 5177 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5178 } 5179 5180 qp_attr->port_num = hr_qp->port + 1; 5181 qp_attr->sq_draining = 0; 5182 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5183 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5184 5185 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5186 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5187 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5188 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5189 5190 done: 5191 qp_attr->cur_qp_state = qp_attr->qp_state; 5192 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5193 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5194 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5195 5196 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5197 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5198 5199 qp_init_attr->qp_context = ibqp->qp_context; 5200 qp_init_attr->qp_type = ibqp->qp_type; 5201 qp_init_attr->recv_cq = ibqp->recv_cq; 5202 qp_init_attr->send_cq = ibqp->send_cq; 5203 qp_init_attr->srq = ibqp->srq; 5204 qp_init_attr->cap = qp_attr->cap; 5205 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5206 5207 out: 5208 mutex_unlock(&hr_qp->mutex); 5209 return ret; 5210 } 5211 5212 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5213 { 5214 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5215 hr_qp->ibqp.qp_type == IB_QPT_UD || 5216 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5217 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5218 hr_qp->state != IB_QPS_RESET); 5219 } 5220 5221 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5222 struct hns_roce_qp *hr_qp, 5223 struct ib_udata *udata) 5224 { 5225 struct ib_device *ibdev = &hr_dev->ib_dev; 5226 struct hns_roce_cq *send_cq, *recv_cq; 5227 unsigned long flags; 5228 int ret = 0; 5229 5230 if (modify_qp_is_ok(hr_qp)) { 5231 /* Modify qp to reset before destroying qp */ 5232 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5233 hr_qp->state, IB_QPS_RESET); 5234 if (ret) 5235 ibdev_err(ibdev, 5236 "failed to modify QP to RST, ret = %d.\n", 5237 ret); 5238 } 5239 5240 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5241 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5242 5243 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5244 hns_roce_lock_cqs(send_cq, recv_cq); 5245 5246 if (!udata) { 5247 if (recv_cq) 5248 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5249 (hr_qp->ibqp.srq ? 5250 to_hr_srq(hr_qp->ibqp.srq) : 5251 NULL)); 5252 5253 if (send_cq && send_cq != recv_cq) 5254 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5255 } 5256 5257 hns_roce_qp_remove(hr_dev, hr_qp); 5258 5259 hns_roce_unlock_cqs(send_cq, recv_cq); 5260 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5261 5262 return ret; 5263 } 5264 5265 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5266 { 5267 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5268 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5269 int ret; 5270 5271 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5272 if (ret) 5273 ibdev_err(&hr_dev->ib_dev, 5274 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5275 hr_qp->qpn, ret); 5276 5277 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5278 5279 return 0; 5280 } 5281 5282 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5283 struct hns_roce_qp *hr_qp) 5284 { 5285 struct ib_device *ibdev = &hr_dev->ib_dev; 5286 struct hns_roce_sccc_clr_done *resp; 5287 struct hns_roce_sccc_clr *clr; 5288 struct hns_roce_cmq_desc desc; 5289 int ret, i; 5290 5291 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5292 return 0; 5293 5294 mutex_lock(&hr_dev->qp_table.scc_mutex); 5295 5296 /* set scc ctx clear done flag */ 5297 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5298 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5299 if (ret) { 5300 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5301 goto out; 5302 } 5303 5304 /* clear scc context */ 5305 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5306 clr = (struct hns_roce_sccc_clr *)desc.data; 5307 clr->qpn = cpu_to_le32(hr_qp->qpn); 5308 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5309 if (ret) { 5310 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5311 goto out; 5312 } 5313 5314 /* query scc context clear is done or not */ 5315 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5316 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5317 hns_roce_cmq_setup_basic_desc(&desc, 5318 HNS_ROCE_OPC_QUERY_SCCC, true); 5319 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5320 if (ret) { 5321 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5322 ret); 5323 goto out; 5324 } 5325 5326 if (resp->clr_done) 5327 goto out; 5328 5329 msleep(20); 5330 } 5331 5332 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 5333 ret = -ETIMEDOUT; 5334 5335 out: 5336 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5337 return ret; 5338 } 5339 5340 #define DMA_IDX_SHIFT 3 5341 #define DMA_WQE_SHIFT 3 5342 5343 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5344 struct hns_roce_srq_context *ctx) 5345 { 5346 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5347 struct ib_device *ibdev = srq->ibsrq.device; 5348 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5349 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5350 dma_addr_t dma_handle_idx = 0; 5351 int ret; 5352 5353 /* Get physical address of idx que buf */ 5354 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5355 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5356 if (ret < 1) { 5357 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5358 ret); 5359 return -ENOBUFS; 5360 } 5361 5362 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5363 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5364 5365 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5366 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5367 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5368 5369 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5370 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5371 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5372 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5373 5374 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5375 to_hr_hw_page_addr(mtts_idx[0])); 5376 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5377 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5378 5379 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5380 to_hr_hw_page_addr(mtts_idx[1])); 5381 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5382 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5383 5384 return 0; 5385 } 5386 5387 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5388 { 5389 struct ib_device *ibdev = srq->ibsrq.device; 5390 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5391 struct hns_roce_srq_context *ctx = mb_buf; 5392 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5393 dma_addr_t dma_handle_wqe = 0; 5394 int ret; 5395 5396 memset(ctx, 0, sizeof(*ctx)); 5397 5398 /* Get the physical address of srq buf */ 5399 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5400 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5401 if (ret < 1) { 5402 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5403 ret); 5404 return -ENOBUFS; 5405 } 5406 5407 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5408 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5409 srq->ibsrq.srq_type == IB_SRQT_XRC); 5410 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5411 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5412 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5413 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5414 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5415 hr_reg_write(ctx, SRQC_RQWS, 5416 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5417 5418 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5419 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5420 srq->wqe_cnt)); 5421 5422 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5423 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5424 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5425 5426 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5427 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5428 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5429 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5430 5431 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5432 } 5433 5434 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5435 struct ib_srq_attr *srq_attr, 5436 enum ib_srq_attr_mask srq_attr_mask, 5437 struct ib_udata *udata) 5438 { 5439 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5440 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5441 struct hns_roce_srq_context *srq_context; 5442 struct hns_roce_srq_context *srqc_mask; 5443 struct hns_roce_cmd_mailbox *mailbox; 5444 int ret; 5445 5446 /* Resizing SRQs is not supported yet */ 5447 if (srq_attr_mask & IB_SRQ_MAX_WR) 5448 return -EINVAL; 5449 5450 if (srq_attr_mask & IB_SRQ_LIMIT) { 5451 if (srq_attr->srq_limit > srq->wqe_cnt) 5452 return -EINVAL; 5453 5454 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5455 if (IS_ERR(mailbox)) 5456 return PTR_ERR(mailbox); 5457 5458 srq_context = mailbox->buf; 5459 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5460 5461 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5462 5463 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5464 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5465 5466 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5467 HNS_ROCE_CMD_MODIFY_SRQC, 5468 HNS_ROCE_CMD_TIMEOUT_MSECS); 5469 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5470 if (ret) { 5471 ibdev_err(&hr_dev->ib_dev, 5472 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5473 ret); 5474 return ret; 5475 } 5476 } 5477 5478 return 0; 5479 } 5480 5481 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5482 { 5483 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5484 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5485 struct hns_roce_srq_context *srq_context; 5486 struct hns_roce_cmd_mailbox *mailbox; 5487 int ret; 5488 5489 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5490 if (IS_ERR(mailbox)) 5491 return PTR_ERR(mailbox); 5492 5493 srq_context = mailbox->buf; 5494 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5495 HNS_ROCE_CMD_QUERY_SRQC, 5496 HNS_ROCE_CMD_TIMEOUT_MSECS); 5497 if (ret) { 5498 ibdev_err(&hr_dev->ib_dev, 5499 "failed to process cmd of querying SRQ, ret = %d.\n", 5500 ret); 5501 goto out; 5502 } 5503 5504 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5505 attr->max_wr = srq->wqe_cnt; 5506 attr->max_sge = srq->max_gs - srq->rsv_sge; 5507 5508 out: 5509 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5510 return ret; 5511 } 5512 5513 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5514 { 5515 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5516 struct hns_roce_v2_cq_context *cq_context; 5517 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5518 struct hns_roce_v2_cq_context *cqc_mask; 5519 struct hns_roce_cmd_mailbox *mailbox; 5520 int ret; 5521 5522 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5523 if (IS_ERR(mailbox)) 5524 return PTR_ERR(mailbox); 5525 5526 cq_context = mailbox->buf; 5527 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5528 5529 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5530 5531 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5532 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5533 5534 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5535 if (cq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5536 dev_info(hr_dev->dev, 5537 "cq_period(%u) reached the upper limit, adjusted to 65.\n", 5538 cq_period); 5539 cq_period = HNS_ROCE_MAX_CQ_PERIOD; 5540 } 5541 cq_period *= HNS_ROCE_CLOCK_ADJUST; 5542 } 5543 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5544 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5545 5546 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5547 HNS_ROCE_CMD_MODIFY_CQC, 5548 HNS_ROCE_CMD_TIMEOUT_MSECS); 5549 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5550 if (ret) 5551 ibdev_err(&hr_dev->ib_dev, 5552 "failed to process cmd when modifying CQ, ret = %d.\n", 5553 ret); 5554 5555 return ret; 5556 } 5557 5558 static void hns_roce_irq_work_handle(struct work_struct *work) 5559 { 5560 struct hns_roce_work *irq_work = 5561 container_of(work, struct hns_roce_work, work); 5562 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5563 5564 switch (irq_work->event_type) { 5565 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5566 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5567 break; 5568 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5569 ibdev_warn(ibdev, "Path migration failed.\n"); 5570 break; 5571 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5572 break; 5573 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5574 ibdev_warn(ibdev, "Send queue drained.\n"); 5575 break; 5576 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5577 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5578 irq_work->queue_num, irq_work->sub_type); 5579 break; 5580 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5581 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5582 irq_work->queue_num); 5583 break; 5584 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5585 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5586 irq_work->queue_num, irq_work->sub_type); 5587 break; 5588 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5589 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5590 break; 5591 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5592 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5593 break; 5594 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5595 ibdev_err(ibdev, "SRQ catas error.\n"); 5596 break; 5597 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5598 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5599 break; 5600 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5601 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5602 break; 5603 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5604 ibdev_warn(ibdev, "DB overflow.\n"); 5605 break; 5606 case HNS_ROCE_EVENT_TYPE_FLR: 5607 ibdev_warn(ibdev, "Function level reset.\n"); 5608 break; 5609 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5610 ibdev_err(ibdev, "xrc domain violation error.\n"); 5611 break; 5612 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5613 ibdev_err(ibdev, "invalid xrceth error.\n"); 5614 break; 5615 default: 5616 break; 5617 } 5618 5619 kfree(irq_work); 5620 } 5621 5622 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5623 struct hns_roce_eq *eq, u32 queue_num) 5624 { 5625 struct hns_roce_work *irq_work; 5626 5627 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5628 if (!irq_work) 5629 return; 5630 5631 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5632 irq_work->hr_dev = hr_dev; 5633 irq_work->event_type = eq->event_type; 5634 irq_work->sub_type = eq->sub_type; 5635 irq_work->queue_num = queue_num; 5636 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5637 } 5638 5639 static void update_eq_db(struct hns_roce_eq *eq) 5640 { 5641 struct hns_roce_dev *hr_dev = eq->hr_dev; 5642 struct hns_roce_v2_db eq_db = {}; 5643 5644 if (eq->type_flag == HNS_ROCE_AEQ) { 5645 hr_reg_write(&eq_db, EQ_DB_CMD, 5646 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5647 HNS_ROCE_EQ_DB_CMD_AEQ : 5648 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5649 } else { 5650 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5651 5652 hr_reg_write(&eq_db, EQ_DB_CMD, 5653 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5654 HNS_ROCE_EQ_DB_CMD_CEQ : 5655 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5656 } 5657 5658 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5659 5660 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5661 } 5662 5663 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5664 { 5665 struct hns_roce_aeqe *aeqe; 5666 5667 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5668 (eq->cons_index & (eq->entries - 1)) * 5669 eq->eqe_size); 5670 5671 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5672 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5673 } 5674 5675 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5676 struct hns_roce_eq *eq) 5677 { 5678 struct device *dev = hr_dev->dev; 5679 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5680 int aeqe_found = 0; 5681 int event_type; 5682 u32 queue_num; 5683 int sub_type; 5684 5685 while (aeqe) { 5686 /* Make sure we read AEQ entry after we have checked the 5687 * ownership bit 5688 */ 5689 dma_rmb(); 5690 5691 event_type = roce_get_field(aeqe->asyn, 5692 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5693 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5694 sub_type = roce_get_field(aeqe->asyn, 5695 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5696 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5697 queue_num = roce_get_field(aeqe->event.queue_event.num, 5698 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5699 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5700 5701 switch (event_type) { 5702 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5703 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5704 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5705 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5706 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5707 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5708 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5709 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5710 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5711 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5712 hns_roce_qp_event(hr_dev, queue_num, event_type); 5713 break; 5714 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5715 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5716 hns_roce_srq_event(hr_dev, queue_num, event_type); 5717 break; 5718 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5719 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5720 hns_roce_cq_event(hr_dev, queue_num, event_type); 5721 break; 5722 case HNS_ROCE_EVENT_TYPE_MB: 5723 hns_roce_cmd_event(hr_dev, 5724 le16_to_cpu(aeqe->event.cmd.token), 5725 aeqe->event.cmd.status, 5726 le64_to_cpu(aeqe->event.cmd.out_param)); 5727 break; 5728 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5729 case HNS_ROCE_EVENT_TYPE_FLR: 5730 break; 5731 default: 5732 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5733 event_type, eq->eqn, eq->cons_index); 5734 break; 5735 } 5736 5737 eq->event_type = event_type; 5738 eq->sub_type = sub_type; 5739 ++eq->cons_index; 5740 aeqe_found = 1; 5741 5742 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5743 5744 aeqe = next_aeqe_sw_v2(eq); 5745 } 5746 5747 update_eq_db(eq); 5748 return aeqe_found; 5749 } 5750 5751 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5752 { 5753 struct hns_roce_ceqe *ceqe; 5754 5755 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5756 (eq->cons_index & (eq->entries - 1)) * 5757 eq->eqe_size); 5758 5759 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5760 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5761 } 5762 5763 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5764 struct hns_roce_eq *eq) 5765 { 5766 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5767 int ceqe_found = 0; 5768 u32 cqn; 5769 5770 while (ceqe) { 5771 /* Make sure we read CEQ entry after we have checked the 5772 * ownership bit 5773 */ 5774 dma_rmb(); 5775 5776 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5777 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5778 5779 hns_roce_cq_completion(hr_dev, cqn); 5780 5781 ++eq->cons_index; 5782 ceqe_found = 1; 5783 5784 ceqe = next_ceqe_sw_v2(eq); 5785 } 5786 5787 update_eq_db(eq); 5788 5789 return ceqe_found; 5790 } 5791 5792 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5793 { 5794 struct hns_roce_eq *eq = eq_ptr; 5795 struct hns_roce_dev *hr_dev = eq->hr_dev; 5796 int int_work; 5797 5798 if (eq->type_flag == HNS_ROCE_CEQ) 5799 /* Completion event interrupt */ 5800 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5801 else 5802 /* Asychronous event interrupt */ 5803 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5804 5805 return IRQ_RETVAL(int_work); 5806 } 5807 5808 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5809 { 5810 struct hns_roce_dev *hr_dev = dev_id; 5811 struct device *dev = hr_dev->dev; 5812 int int_work = 0; 5813 u32 int_st; 5814 u32 int_en; 5815 5816 /* Abnormal interrupt */ 5817 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5818 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5819 5820 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5821 struct pci_dev *pdev = hr_dev->pci_dev; 5822 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5823 const struct hnae3_ae_ops *ops = ae_dev->ops; 5824 5825 dev_err(dev, "AEQ overflow!\n"); 5826 5827 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5828 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5829 5830 /* Set reset level for reset_event() */ 5831 if (ops->set_default_reset_request) 5832 ops->set_default_reset_request(ae_dev, 5833 HNAE3_FUNC_RESET); 5834 if (ops->reset_event) 5835 ops->reset_event(pdev, NULL); 5836 5837 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5838 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5839 5840 int_work = 1; 5841 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) { 5842 dev_err(dev, "RAS interrupt!\n"); 5843 5844 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S; 5845 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5846 5847 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5848 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5849 5850 int_work = 1; 5851 } else { 5852 dev_err(dev, "There is no abnormal irq found!\n"); 5853 } 5854 5855 return IRQ_RETVAL(int_work); 5856 } 5857 5858 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5859 int eq_num, u32 enable_flag) 5860 { 5861 int i; 5862 5863 for (i = 0; i < eq_num; i++) 5864 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5865 i * EQ_REG_OFFSET, enable_flag); 5866 5867 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 5868 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 5869 } 5870 5871 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5872 { 5873 struct device *dev = hr_dev->dev; 5874 int ret; 5875 5876 if (eqn < hr_dev->caps.num_comp_vectors) 5877 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5878 0, HNS_ROCE_CMD_DESTROY_CEQC, 5879 HNS_ROCE_CMD_TIMEOUT_MSECS); 5880 else 5881 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5882 0, HNS_ROCE_CMD_DESTROY_AEQC, 5883 HNS_ROCE_CMD_TIMEOUT_MSECS); 5884 if (ret) 5885 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5886 } 5887 5888 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5889 { 5890 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5891 } 5892 5893 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5894 { 5895 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5896 eq->cons_index = 0; 5897 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5898 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5899 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5900 eq->shift = ilog2((unsigned int)eq->entries); 5901 } 5902 5903 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5904 void *mb_buf) 5905 { 5906 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5907 struct hns_roce_eq_context *eqc; 5908 u64 bt_ba = 0; 5909 int count; 5910 5911 eqc = mb_buf; 5912 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5913 5914 init_eq_config(hr_dev, eq); 5915 5916 /* if not multi-hop, eqe buffer only use one trunk */ 5917 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5918 &bt_ba); 5919 if (count < 1) { 5920 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5921 return -ENOBUFS; 5922 } 5923 5924 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 5925 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 5926 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 5927 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 5928 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 5929 hr_reg_write(eqc, EQC_EQN, eq->eqn); 5930 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 5931 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 5932 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5933 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 5934 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5935 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 5936 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 5937 5938 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 5939 if (eq->eq_period * HNS_ROCE_CLOCK_ADJUST > USHRT_MAX) { 5940 dev_info(hr_dev->dev, "eq_period(%u) reached the upper limit, adjusted to 65.\n", 5941 eq->eq_period); 5942 eq->eq_period = HNS_ROCE_MAX_EQ_PERIOD; 5943 } 5944 eq->eq_period *= HNS_ROCE_CLOCK_ADJUST; 5945 } 5946 5947 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 5948 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 5949 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 5950 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 5951 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 5952 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 5953 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 5954 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 5955 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 5956 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 5957 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 5958 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 5959 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 5960 5961 return 0; 5962 } 5963 5964 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5965 { 5966 struct hns_roce_buf_attr buf_attr = {}; 5967 int err; 5968 5969 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5970 eq->hop_num = 0; 5971 else 5972 eq->hop_num = hr_dev->caps.eqe_hop_num; 5973 5974 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 5975 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5976 buf_attr.region[0].hopnum = eq->hop_num; 5977 buf_attr.region_count = 1; 5978 5979 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5980 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 5981 0); 5982 if (err) 5983 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5984 5985 return err; 5986 } 5987 5988 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5989 struct hns_roce_eq *eq, 5990 unsigned int eq_cmd) 5991 { 5992 struct hns_roce_cmd_mailbox *mailbox; 5993 int ret; 5994 5995 /* Allocate mailbox memory */ 5996 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5997 if (IS_ERR_OR_NULL(mailbox)) 5998 return -ENOMEM; 5999 6000 ret = alloc_eq_buf(hr_dev, eq); 6001 if (ret) 6002 goto free_cmd_mbox; 6003 6004 ret = config_eqc(hr_dev, eq, mailbox->buf); 6005 if (ret) 6006 goto err_cmd_mbox; 6007 6008 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 6009 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 6010 if (ret) { 6011 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 6012 goto err_cmd_mbox; 6013 } 6014 6015 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6016 6017 return 0; 6018 6019 err_cmd_mbox: 6020 free_eq_buf(hr_dev, eq); 6021 6022 free_cmd_mbox: 6023 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 6024 6025 return ret; 6026 } 6027 6028 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 6029 int comp_num, int aeq_num, int other_num) 6030 { 6031 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6032 int i, j; 6033 int ret; 6034 6035 for (i = 0; i < irq_num; i++) { 6036 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 6037 GFP_KERNEL); 6038 if (!hr_dev->irq_names[i]) { 6039 ret = -ENOMEM; 6040 goto err_kzalloc_failed; 6041 } 6042 } 6043 6044 /* irq contains: abnormal + AEQ + CEQ */ 6045 for (j = 0; j < other_num; j++) 6046 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6047 "hns-abn-%d", j); 6048 6049 for (j = other_num; j < (other_num + aeq_num); j++) 6050 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6051 "hns-aeq-%d", j - other_num); 6052 6053 for (j = (other_num + aeq_num); j < irq_num; j++) 6054 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 6055 "hns-ceq-%d", j - other_num - aeq_num); 6056 6057 for (j = 0; j < irq_num; j++) { 6058 if (j < other_num) 6059 ret = request_irq(hr_dev->irq[j], 6060 hns_roce_v2_msix_interrupt_abn, 6061 0, hr_dev->irq_names[j], hr_dev); 6062 6063 else if (j < (other_num + comp_num)) 6064 ret = request_irq(eq_table->eq[j - other_num].irq, 6065 hns_roce_v2_msix_interrupt_eq, 6066 0, hr_dev->irq_names[j + aeq_num], 6067 &eq_table->eq[j - other_num]); 6068 else 6069 ret = request_irq(eq_table->eq[j - other_num].irq, 6070 hns_roce_v2_msix_interrupt_eq, 6071 0, hr_dev->irq_names[j - comp_num], 6072 &eq_table->eq[j - other_num]); 6073 if (ret) { 6074 dev_err(hr_dev->dev, "Request irq error!\n"); 6075 goto err_request_failed; 6076 } 6077 } 6078 6079 return 0; 6080 6081 err_request_failed: 6082 for (j -= 1; j >= 0; j--) 6083 if (j < other_num) 6084 free_irq(hr_dev->irq[j], hr_dev); 6085 else 6086 free_irq(eq_table->eq[j - other_num].irq, 6087 &eq_table->eq[j - other_num]); 6088 6089 err_kzalloc_failed: 6090 for (i -= 1; i >= 0; i--) 6091 kfree(hr_dev->irq_names[i]); 6092 6093 return ret; 6094 } 6095 6096 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6097 { 6098 int irq_num; 6099 int eq_num; 6100 int i; 6101 6102 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6103 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6104 6105 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6106 free_irq(hr_dev->irq[i], hr_dev); 6107 6108 for (i = 0; i < eq_num; i++) 6109 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6110 6111 for (i = 0; i < irq_num; i++) 6112 kfree(hr_dev->irq_names[i]); 6113 } 6114 6115 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6116 { 6117 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6118 struct device *dev = hr_dev->dev; 6119 struct hns_roce_eq *eq; 6120 unsigned int eq_cmd; 6121 int irq_num; 6122 int eq_num; 6123 int other_num; 6124 int comp_num; 6125 int aeq_num; 6126 int i; 6127 int ret; 6128 6129 other_num = hr_dev->caps.num_other_vectors; 6130 comp_num = hr_dev->caps.num_comp_vectors; 6131 aeq_num = hr_dev->caps.num_aeq_vectors; 6132 6133 eq_num = comp_num + aeq_num; 6134 irq_num = eq_num + other_num; 6135 6136 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6137 if (!eq_table->eq) 6138 return -ENOMEM; 6139 6140 /* create eq */ 6141 for (i = 0; i < eq_num; i++) { 6142 eq = &eq_table->eq[i]; 6143 eq->hr_dev = hr_dev; 6144 eq->eqn = i; 6145 if (i < comp_num) { 6146 /* CEQ */ 6147 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6148 eq->type_flag = HNS_ROCE_CEQ; 6149 eq->entries = hr_dev->caps.ceqe_depth; 6150 eq->eqe_size = hr_dev->caps.ceqe_size; 6151 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6152 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6153 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6154 } else { 6155 /* AEQ */ 6156 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6157 eq->type_flag = HNS_ROCE_AEQ; 6158 eq->entries = hr_dev->caps.aeqe_depth; 6159 eq->eqe_size = hr_dev->caps.aeqe_size; 6160 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6161 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6162 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6163 } 6164 6165 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6166 if (ret) { 6167 dev_err(dev, "failed to create eq.\n"); 6168 goto err_create_eq_fail; 6169 } 6170 } 6171 6172 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6173 if (!hr_dev->irq_workq) { 6174 dev_err(dev, "failed to create irq workqueue.\n"); 6175 ret = -ENOMEM; 6176 goto err_create_eq_fail; 6177 } 6178 6179 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6180 other_num); 6181 if (ret) { 6182 dev_err(dev, "failed to request irq.\n"); 6183 goto err_request_irq_fail; 6184 } 6185 6186 /* enable irq */ 6187 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6188 6189 return 0; 6190 6191 err_request_irq_fail: 6192 destroy_workqueue(hr_dev->irq_workq); 6193 6194 err_create_eq_fail: 6195 for (i -= 1; i >= 0; i--) 6196 free_eq_buf(hr_dev, &eq_table->eq[i]); 6197 kfree(eq_table->eq); 6198 6199 return ret; 6200 } 6201 6202 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6203 { 6204 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6205 int eq_num; 6206 int i; 6207 6208 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6209 6210 /* Disable irq */ 6211 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6212 6213 __hns_roce_free_irq(hr_dev); 6214 destroy_workqueue(hr_dev->irq_workq); 6215 6216 for (i = 0; i < eq_num; i++) { 6217 hns_roce_v2_destroy_eqc(hr_dev, i); 6218 6219 free_eq_buf(hr_dev, &eq_table->eq[i]); 6220 } 6221 6222 kfree(eq_table->eq); 6223 } 6224 6225 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 6226 .query_cqc_info = hns_roce_v2_query_cqc_info, 6227 }; 6228 6229 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6230 .destroy_qp = hns_roce_v2_destroy_qp, 6231 .modify_cq = hns_roce_v2_modify_cq, 6232 .poll_cq = hns_roce_v2_poll_cq, 6233 .post_recv = hns_roce_v2_post_recv, 6234 .post_send = hns_roce_v2_post_send, 6235 .query_qp = hns_roce_v2_query_qp, 6236 .req_notify_cq = hns_roce_v2_req_notify_cq, 6237 }; 6238 6239 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6240 .modify_srq = hns_roce_v2_modify_srq, 6241 .post_srq_recv = hns_roce_v2_post_srq_recv, 6242 .query_srq = hns_roce_v2_query_srq, 6243 }; 6244 6245 static const struct hns_roce_hw hns_roce_hw_v2 = { 6246 .cmq_init = hns_roce_v2_cmq_init, 6247 .cmq_exit = hns_roce_v2_cmq_exit, 6248 .hw_profile = hns_roce_v2_profile, 6249 .hw_init = hns_roce_v2_init, 6250 .hw_exit = hns_roce_v2_exit, 6251 .post_mbox = v2_post_mbox, 6252 .poll_mbox_done = v2_poll_mbox_done, 6253 .chk_mbox_avail = v2_chk_mbox_is_avail, 6254 .set_gid = hns_roce_v2_set_gid, 6255 .set_mac = hns_roce_v2_set_mac, 6256 .write_mtpt = hns_roce_v2_write_mtpt, 6257 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6258 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6259 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6260 .write_cqc = hns_roce_v2_write_cqc, 6261 .set_hem = hns_roce_v2_set_hem, 6262 .clear_hem = hns_roce_v2_clear_hem, 6263 .modify_qp = hns_roce_v2_modify_qp, 6264 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6265 .init_eq = hns_roce_v2_init_eq_table, 6266 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6267 .write_srqc = hns_roce_v2_write_srqc, 6268 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6269 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6270 }; 6271 6272 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6273 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6274 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6275 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6276 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6277 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6278 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6279 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6280 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6281 /* required last entry */ 6282 {0, } 6283 }; 6284 6285 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6286 6287 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6288 struct hnae3_handle *handle) 6289 { 6290 struct hns_roce_v2_priv *priv = hr_dev->priv; 6291 const struct pci_device_id *id; 6292 int i; 6293 6294 hr_dev->pci_dev = handle->pdev; 6295 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6296 hr_dev->is_vf = id->driver_data; 6297 hr_dev->dev = &handle->pdev->dev; 6298 hr_dev->hw = &hns_roce_hw_v2; 6299 hr_dev->dfx = &hns_roce_dfx_hw_v2; 6300 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6301 hr_dev->odb_offset = hr_dev->sdb_offset; 6302 6303 /* Get info from NIC driver. */ 6304 hr_dev->reg_base = handle->rinfo.roce_io_base; 6305 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6306 hr_dev->caps.num_ports = 1; 6307 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6308 hr_dev->iboe.phy_port[0] = 0; 6309 6310 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6311 hr_dev->iboe.netdevs[0]->dev_addr); 6312 6313 for (i = 0; i < handle->rinfo.num_vectors; i++) 6314 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6315 i + handle->rinfo.base_vector); 6316 6317 /* cmd issue mode: 0 is poll, 1 is event */ 6318 hr_dev->cmd_mod = 1; 6319 hr_dev->loop_idc = 0; 6320 6321 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6322 priv->handle = handle; 6323 } 6324 6325 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6326 { 6327 struct hns_roce_dev *hr_dev; 6328 int ret; 6329 6330 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6331 if (!hr_dev) 6332 return -ENOMEM; 6333 6334 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6335 if (!hr_dev->priv) { 6336 ret = -ENOMEM; 6337 goto error_failed_kzalloc; 6338 } 6339 6340 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6341 6342 ret = hns_roce_init(hr_dev); 6343 if (ret) { 6344 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6345 goto error_failed_get_cfg; 6346 } 6347 6348 handle->priv = hr_dev; 6349 6350 return 0; 6351 6352 error_failed_get_cfg: 6353 kfree(hr_dev->priv); 6354 6355 error_failed_kzalloc: 6356 ib_dealloc_device(&hr_dev->ib_dev); 6357 6358 return ret; 6359 } 6360 6361 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6362 bool reset) 6363 { 6364 struct hns_roce_dev *hr_dev = handle->priv; 6365 6366 if (!hr_dev) 6367 return; 6368 6369 handle->priv = NULL; 6370 6371 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6372 hns_roce_handle_device_err(hr_dev); 6373 6374 hns_roce_exit(hr_dev); 6375 kfree(hr_dev->priv); 6376 ib_dealloc_device(&hr_dev->ib_dev); 6377 } 6378 6379 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6380 { 6381 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6382 const struct pci_device_id *id; 6383 struct device *dev = &handle->pdev->dev; 6384 int ret; 6385 6386 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6387 6388 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6389 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6390 goto reset_chk_err; 6391 } 6392 6393 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6394 if (!id) 6395 return 0; 6396 6397 if (id->driver_data && handle->pdev->revision < PCI_REVISION_ID_HIP09) 6398 return 0; 6399 6400 ret = __hns_roce_hw_v2_init_instance(handle); 6401 if (ret) { 6402 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6403 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6404 if (ops->ae_dev_resetting(handle) || 6405 ops->get_hw_reset_stat(handle)) 6406 goto reset_chk_err; 6407 else 6408 return ret; 6409 } 6410 6411 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6412 6413 return 0; 6414 6415 reset_chk_err: 6416 dev_err(dev, "Device is busy in resetting state.\n" 6417 "please retry later.\n"); 6418 6419 return -EBUSY; 6420 } 6421 6422 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6423 bool reset) 6424 { 6425 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6426 return; 6427 6428 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6429 6430 __hns_roce_hw_v2_uninit_instance(handle, reset); 6431 6432 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6433 } 6434 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6435 { 6436 struct hns_roce_dev *hr_dev; 6437 6438 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6439 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6440 return 0; 6441 } 6442 6443 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6444 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6445 6446 hr_dev = handle->priv; 6447 if (!hr_dev) 6448 return 0; 6449 6450 hr_dev->active = false; 6451 hr_dev->dis_db = true; 6452 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6453 6454 return 0; 6455 } 6456 6457 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6458 { 6459 struct device *dev = &handle->pdev->dev; 6460 int ret; 6461 6462 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6463 &handle->rinfo.state)) { 6464 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6465 return 0; 6466 } 6467 6468 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6469 6470 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6471 ret = __hns_roce_hw_v2_init_instance(handle); 6472 if (ret) { 6473 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6474 * callback function, RoCE Engine reinitialize. If RoCE reinit 6475 * failed, we should inform NIC driver. 6476 */ 6477 handle->priv = NULL; 6478 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6479 } else { 6480 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6481 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6482 } 6483 6484 return ret; 6485 } 6486 6487 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6488 { 6489 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6490 return 0; 6491 6492 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6493 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6494 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6495 __hns_roce_hw_v2_uninit_instance(handle, false); 6496 6497 return 0; 6498 } 6499 6500 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6501 enum hnae3_reset_notify_type type) 6502 { 6503 int ret = 0; 6504 6505 switch (type) { 6506 case HNAE3_DOWN_CLIENT: 6507 ret = hns_roce_hw_v2_reset_notify_down(handle); 6508 break; 6509 case HNAE3_INIT_CLIENT: 6510 ret = hns_roce_hw_v2_reset_notify_init(handle); 6511 break; 6512 case HNAE3_UNINIT_CLIENT: 6513 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6514 break; 6515 default: 6516 break; 6517 } 6518 6519 return ret; 6520 } 6521 6522 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6523 .init_instance = hns_roce_hw_v2_init_instance, 6524 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6525 .reset_notify = hns_roce_hw_v2_reset_notify, 6526 }; 6527 6528 static struct hnae3_client hns_roce_hw_v2_client = { 6529 .name = "hns_roce_hw_v2", 6530 .type = HNAE3_CLIENT_ROCE, 6531 .ops = &hns_roce_hw_v2_ops, 6532 }; 6533 6534 static int __init hns_roce_hw_v2_init(void) 6535 { 6536 return hnae3_register_client(&hns_roce_hw_v2_client); 6537 } 6538 6539 static void __exit hns_roce_hw_v2_exit(void) 6540 { 6541 hnae3_unregister_client(&hns_roce_hw_v2_client); 6542 } 6543 6544 module_init(hns_roce_hw_v2_init); 6545 module_exit(hns_roce_hw_v2_exit); 6546 6547 MODULE_LICENSE("Dual BSD/GPL"); 6548 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6549 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6550 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6551 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6552