1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 enum { 52 CMD_RST_PRC_OTHERS, 53 CMD_RST_PRC_SUCCESS, 54 CMD_RST_PRC_EBUSY, 55 }; 56 57 static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 58 struct ib_sge *sg) 59 { 60 dseg->lkey = cpu_to_le32(sg->lkey); 61 dseg->addr = cpu_to_le64(sg->addr); 62 dseg->len = cpu_to_le32(sg->length); 63 } 64 65 /* 66 * mapped-value = 1 + real-value 67 * The hns wr opcode real value is start from 0, In order to distinguish between 68 * initialized and uninitialized map values, we plus 1 to the actual value when 69 * defining the mapping, so that the validity can be identified by checking the 70 * mapped value is greater than 0. 71 */ 72 #define HR_OPC_MAP(ib_key, hr_key) \ 73 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 74 75 static const u32 hns_roce_op_code[] = { 76 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 77 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 78 HR_OPC_MAP(SEND, SEND), 79 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 80 HR_OPC_MAP(RDMA_READ, RDMA_READ), 81 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 82 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 83 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 84 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 85 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 86 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 87 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 88 }; 89 90 static u32 to_hr_opcode(u32 ib_opcode) 91 { 92 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 93 return HNS_ROCE_V2_WQE_OP_MASK; 94 95 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 96 HNS_ROCE_V2_WQE_OP_MASK; 97 } 98 99 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 100 const struct ib_reg_wr *wr) 101 { 102 struct hns_roce_wqe_frmr_seg *fseg = 103 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 104 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 105 u64 pbl_ba; 106 107 /* use ib_access_flags */ 108 hr_reg_write_bool(fseg, FRMR_BIND_EN, wr->access & IB_ACCESS_MW_BIND); 109 hr_reg_write_bool(fseg, FRMR_ATOMIC, 110 wr->access & IB_ACCESS_REMOTE_ATOMIC); 111 hr_reg_write_bool(fseg, FRMR_RR, wr->access & IB_ACCESS_REMOTE_READ); 112 hr_reg_write_bool(fseg, FRMR_RW, wr->access & IB_ACCESS_REMOTE_WRITE); 113 hr_reg_write_bool(fseg, FRMR_LW, wr->access & IB_ACCESS_LOCAL_WRITE); 114 115 /* Data structure reuse may lead to confusion */ 116 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 117 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 118 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 119 120 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 121 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 122 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 123 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 124 125 hr_reg_write(fseg, FRMR_PBL_SIZE, mr->npages); 126 hr_reg_write(fseg, FRMR_PBL_BUF_PG_SZ, 127 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 128 hr_reg_clear(fseg, FRMR_BLK_MODE); 129 } 130 131 static void set_atomic_seg(const struct ib_send_wr *wr, 132 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 133 unsigned int valid_num_sge) 134 { 135 struct hns_roce_v2_wqe_data_seg *dseg = 136 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 137 struct hns_roce_wqe_atomic_seg *aseg = 138 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 139 140 set_data_seg_v2(dseg, wr->sg_list); 141 142 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 143 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 144 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 145 } else { 146 aseg->fetchadd_swap_data = 147 cpu_to_le64(atomic_wr(wr)->compare_add); 148 aseg->cmp_data = 0; 149 } 150 151 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 152 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 153 } 154 155 static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, 156 const struct ib_send_wr *wr, 157 unsigned int *sge_idx, u32 msg_len) 158 { 159 struct ib_device *ibdev = &(to_hr_dev(qp->ibqp.device))->ib_dev; 160 unsigned int dseg_len = sizeof(struct hns_roce_v2_wqe_data_seg); 161 unsigned int ext_sge_sz = qp->sq.max_gs * dseg_len; 162 unsigned int left_len_in_pg; 163 unsigned int idx = *sge_idx; 164 unsigned int i = 0; 165 unsigned int len; 166 void *addr; 167 void *dseg; 168 169 if (msg_len > ext_sge_sz) { 170 ibdev_err(ibdev, 171 "no enough extended sge space for inline data.\n"); 172 return -EINVAL; 173 } 174 175 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 176 left_len_in_pg = hr_hw_page_align((uintptr_t)dseg) - (uintptr_t)dseg; 177 len = wr->sg_list[0].length; 178 addr = (void *)(unsigned long)(wr->sg_list[0].addr); 179 180 /* When copying data to extended sge space, the left length in page may 181 * not long enough for current user's sge. So the data should be 182 * splited into several parts, one in the first page, and the others in 183 * the subsequent pages. 184 */ 185 while (1) { 186 if (len <= left_len_in_pg) { 187 memcpy(dseg, addr, len); 188 189 idx += len / dseg_len; 190 191 i++; 192 if (i >= wr->num_sge) 193 break; 194 195 left_len_in_pg -= len; 196 len = wr->sg_list[i].length; 197 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 198 dseg += len; 199 } else { 200 memcpy(dseg, addr, left_len_in_pg); 201 202 len -= left_len_in_pg; 203 addr += left_len_in_pg; 204 idx += left_len_in_pg / dseg_len; 205 dseg = hns_roce_get_extend_sge(qp, 206 idx & (qp->sge.sge_cnt - 1)); 207 left_len_in_pg = 1 << HNS_HW_PAGE_SHIFT; 208 } 209 } 210 211 *sge_idx = idx; 212 213 return 0; 214 } 215 216 static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, 217 unsigned int *sge_ind, unsigned int cnt) 218 { 219 struct hns_roce_v2_wqe_data_seg *dseg; 220 unsigned int idx = *sge_ind; 221 222 while (cnt > 0) { 223 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 224 if (likely(sge->length)) { 225 set_data_seg_v2(dseg, sge); 226 idx++; 227 cnt--; 228 } 229 sge++; 230 } 231 232 *sge_ind = idx; 233 } 234 235 static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) 236 { 237 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 238 int mtu = ib_mtu_enum_to_int(qp->path_mtu); 239 240 if (len > qp->max_inline_data || len > mtu) { 241 ibdev_err(&hr_dev->ib_dev, 242 "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", 243 len, qp->max_inline_data, mtu); 244 return false; 245 } 246 247 return true; 248 } 249 250 static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 251 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 252 unsigned int *sge_idx) 253 { 254 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 255 u32 msg_len = le32_to_cpu(rc_sq_wqe->msg_len); 256 struct ib_device *ibdev = &hr_dev->ib_dev; 257 unsigned int curr_idx = *sge_idx; 258 void *dseg = rc_sq_wqe; 259 unsigned int i; 260 int ret; 261 262 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 263 ibdev_err(ibdev, "invalid inline parameters!\n"); 264 return -EINVAL; 265 } 266 267 if (!check_inl_data_len(qp, msg_len)) 268 return -EINVAL; 269 270 dseg += sizeof(struct hns_roce_v2_rc_send_wqe); 271 272 if (msg_len <= HNS_ROCE_V2_MAX_RC_INL_INN_SZ) { 273 roce_set_bit(rc_sq_wqe->byte_20, 274 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 0); 275 276 for (i = 0; i < wr->num_sge; i++) { 277 memcpy(dseg, ((void *)wr->sg_list[i].addr), 278 wr->sg_list[i].length); 279 dseg += wr->sg_list[i].length; 280 } 281 } else { 282 roce_set_bit(rc_sq_wqe->byte_20, 283 V2_RC_SEND_WQE_BYTE_20_INL_TYPE_S, 1); 284 285 ret = fill_ext_sge_inl_data(qp, wr, &curr_idx, msg_len); 286 if (ret) 287 return ret; 288 289 roce_set_field(rc_sq_wqe->byte_16, 290 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 291 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, 292 curr_idx - *sge_idx); 293 } 294 295 *sge_idx = curr_idx; 296 297 return 0; 298 } 299 300 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 301 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 302 unsigned int *sge_ind, 303 unsigned int valid_num_sge) 304 { 305 struct hns_roce_v2_wqe_data_seg *dseg = 306 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 307 struct hns_roce_qp *qp = to_hr_qp(ibqp); 308 int j = 0; 309 int i; 310 311 roce_set_field(rc_sq_wqe->byte_20, 312 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 313 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 314 (*sge_ind) & (qp->sge.sge_cnt - 1)); 315 316 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 317 !!(wr->send_flags & IB_SEND_INLINE)); 318 if (wr->send_flags & IB_SEND_INLINE) 319 return set_rc_inl(qp, wr, rc_sq_wqe, sge_ind); 320 321 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 322 for (i = 0; i < wr->num_sge; i++) { 323 if (likely(wr->sg_list[i].length)) { 324 set_data_seg_v2(dseg, wr->sg_list + i); 325 dseg++; 326 } 327 } 328 } else { 329 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; i++) { 330 if (likely(wr->sg_list[i].length)) { 331 set_data_seg_v2(dseg, wr->sg_list + i); 332 dseg++; 333 j++; 334 } 335 } 336 337 set_extend_sge(qp, wr->sg_list + i, sge_ind, 338 valid_num_sge - HNS_ROCE_SGE_IN_WQE); 339 } 340 341 roce_set_field(rc_sq_wqe->byte_16, 342 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 343 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 344 345 return 0; 346 } 347 348 static int check_send_valid(struct hns_roce_dev *hr_dev, 349 struct hns_roce_qp *hr_qp) 350 { 351 struct ib_device *ibdev = &hr_dev->ib_dev; 352 struct ib_qp *ibqp = &hr_qp->ibqp; 353 354 if (unlikely(ibqp->qp_type != IB_QPT_RC && 355 ibqp->qp_type != IB_QPT_GSI && 356 ibqp->qp_type != IB_QPT_UD)) { 357 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 358 ibqp->qp_type); 359 return -EOPNOTSUPP; 360 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 361 hr_qp->state == IB_QPS_INIT || 362 hr_qp->state == IB_QPS_RTR)) { 363 ibdev_err(ibdev, "failed to post WQE, QP state %u!\n", 364 hr_qp->state); 365 return -EINVAL; 366 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 367 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 368 hr_dev->state); 369 return -EIO; 370 } 371 372 return 0; 373 } 374 375 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 376 unsigned int *sge_len) 377 { 378 unsigned int valid_num = 0; 379 unsigned int len = 0; 380 int i; 381 382 for (i = 0; i < wr->num_sge; i++) { 383 if (likely(wr->sg_list[i].length)) { 384 len += wr->sg_list[i].length; 385 valid_num++; 386 } 387 } 388 389 *sge_len = len; 390 return valid_num; 391 } 392 393 static __le32 get_immtdata(const struct ib_send_wr *wr) 394 { 395 switch (wr->opcode) { 396 case IB_WR_SEND_WITH_IMM: 397 case IB_WR_RDMA_WRITE_WITH_IMM: 398 return cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 399 default: 400 return 0; 401 } 402 } 403 404 static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 405 const struct ib_send_wr *wr) 406 { 407 u32 ib_op = wr->opcode; 408 409 if (ib_op != IB_WR_SEND && ib_op != IB_WR_SEND_WITH_IMM) 410 return -EINVAL; 411 412 ud_sq_wqe->immtdata = get_immtdata(wr); 413 414 roce_set_field(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 415 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 416 417 return 0; 418 } 419 420 static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, 421 struct hns_roce_ah *ah) 422 { 423 struct ib_device *ib_dev = ah->ibah.device; 424 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 425 426 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 427 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport); 428 429 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 430 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 431 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 432 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 433 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 434 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 435 436 if (WARN_ON(ah->av.sl > MAX_SERVICE_LEVEL)) 437 return -EINVAL; 438 439 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 440 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 441 442 ud_sq_wqe->sgid_index = ah->av.gid_index; 443 444 memcpy(ud_sq_wqe->dmac, ah->av.mac, ETH_ALEN); 445 memcpy(ud_sq_wqe->dgid, ah->av.dgid, GID_LEN_V2); 446 447 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 448 return 0; 449 450 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 451 ah->av.vlan_en); 452 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 453 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 454 455 return 0; 456 } 457 458 static inline int set_ud_wqe(struct hns_roce_qp *qp, 459 const struct ib_send_wr *wr, 460 void *wqe, unsigned int *sge_idx, 461 unsigned int owner_bit) 462 { 463 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 464 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 465 unsigned int curr_idx = *sge_idx; 466 unsigned int valid_num_sge; 467 u32 msg_len = 0; 468 int ret; 469 470 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 471 472 ret = set_ud_opcode(ud_sq_wqe, wr); 473 if (WARN_ON(ret)) 474 return ret; 475 476 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 477 478 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 479 !!(wr->send_flags & IB_SEND_SIGNALED)); 480 481 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 482 !!(wr->send_flags & IB_SEND_SOLICITED)); 483 484 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 485 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 486 487 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 488 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 489 490 roce_set_field(ud_sq_wqe->byte_20, 491 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 492 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 493 curr_idx & (qp->sge.sge_cnt - 1)); 494 495 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 496 qp->qkey : ud_wr(wr)->remote_qkey); 497 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 498 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 499 500 ret = fill_ud_av(ud_sq_wqe, ah); 501 if (ret) 502 return ret; 503 504 qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; 505 506 set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); 507 508 /* 509 * The pipeline can sequentially post all valid WQEs into WQ buffer, 510 * including new WQEs waiting for the doorbell to update the PI again. 511 * Therefore, the owner bit of WQE MUST be updated after all fields 512 * and extSGEs have been written into DDR instead of cache. 513 */ 514 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 515 dma_wmb(); 516 517 *sge_idx = curr_idx; 518 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 519 owner_bit); 520 521 return 0; 522 } 523 524 static int set_rc_opcode(struct hns_roce_dev *hr_dev, 525 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 526 const struct ib_send_wr *wr) 527 { 528 u32 ib_op = wr->opcode; 529 int ret = 0; 530 531 rc_sq_wqe->immtdata = get_immtdata(wr); 532 533 switch (ib_op) { 534 case IB_WR_RDMA_READ: 535 case IB_WR_RDMA_WRITE: 536 case IB_WR_RDMA_WRITE_WITH_IMM: 537 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 538 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 539 break; 540 case IB_WR_SEND: 541 case IB_WR_SEND_WITH_IMM: 542 break; 543 case IB_WR_ATOMIC_CMP_AND_SWP: 544 case IB_WR_ATOMIC_FETCH_AND_ADD: 545 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 546 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 547 break; 548 case IB_WR_REG_MR: 549 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 550 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 551 else 552 ret = -EOPNOTSUPP; 553 break; 554 case IB_WR_LOCAL_INV: 555 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 556 fallthrough; 557 case IB_WR_SEND_WITH_INV: 558 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 559 break; 560 default: 561 ret = -EINVAL; 562 } 563 564 if (unlikely(ret)) 565 return ret; 566 567 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 568 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, to_hr_opcode(ib_op)); 569 570 return ret; 571 } 572 static inline int set_rc_wqe(struct hns_roce_qp *qp, 573 const struct ib_send_wr *wr, 574 void *wqe, unsigned int *sge_idx, 575 unsigned int owner_bit) 576 { 577 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 578 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 579 unsigned int curr_idx = *sge_idx; 580 unsigned int valid_num_sge; 581 u32 msg_len = 0; 582 int ret; 583 584 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 585 586 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 587 588 ret = set_rc_opcode(hr_dev, rc_sq_wqe, wr); 589 if (WARN_ON(ret)) 590 return ret; 591 592 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 593 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 594 595 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 596 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 597 598 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 599 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 600 601 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 602 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 603 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 604 else if (wr->opcode != IB_WR_REG_MR) 605 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 606 &curr_idx, valid_num_sge); 607 608 /* 609 * The pipeline can sequentially post all valid WQEs into WQ buffer, 610 * including new WQEs waiting for the doorbell to update the PI again. 611 * Therefore, the owner bit of WQE MUST be updated after all fields 612 * and extSGEs have been written into DDR instead of cache. 613 */ 614 if (qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 615 dma_wmb(); 616 617 *sge_idx = curr_idx; 618 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 619 owner_bit); 620 621 return ret; 622 } 623 624 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 625 struct hns_roce_qp *qp) 626 { 627 if (unlikely(qp->state == IB_QPS_ERR)) { 628 flush_cqe(hr_dev, qp); 629 } else { 630 struct hns_roce_v2_db sq_db = {}; 631 632 hr_reg_write(&sq_db, DB_TAG, qp->doorbell_qpn); 633 hr_reg_write(&sq_db, DB_CMD, HNS_ROCE_V2_SQ_DB); 634 hr_reg_write(&sq_db, DB_PI, qp->sq.head); 635 hr_reg_write(&sq_db, DB_SL, qp->sl); 636 637 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg); 638 } 639 } 640 641 static inline void update_rq_db(struct hns_roce_dev *hr_dev, 642 struct hns_roce_qp *qp) 643 { 644 if (unlikely(qp->state == IB_QPS_ERR)) { 645 flush_cqe(hr_dev, qp); 646 } else { 647 if (likely(qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)) { 648 *qp->rdb.db_record = 649 qp->rq.head & V2_DB_PRODUCER_IDX_M; 650 } else { 651 struct hns_roce_v2_db rq_db = {}; 652 653 hr_reg_write(&rq_db, DB_TAG, qp->qpn); 654 hr_reg_write(&rq_db, DB_CMD, HNS_ROCE_V2_RQ_DB); 655 hr_reg_write(&rq_db, DB_PI, qp->rq.head); 656 657 hns_roce_write64(hr_dev, (__le32 *)&rq_db, 658 qp->rq.db_reg); 659 } 660 } 661 } 662 663 static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, 664 u64 __iomem *dest) 665 { 666 #define HNS_ROCE_WRITE_TIMES 8 667 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; 668 struct hnae3_handle *handle = priv->handle; 669 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 670 int i; 671 672 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) 673 for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) 674 writeq_relaxed(*(val + i), dest + i); 675 } 676 677 static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 678 void *wqe) 679 { 680 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 681 682 /* All kinds of DirectWQE have the same header field layout */ 683 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); 684 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, 685 V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); 686 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, 687 V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); 688 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, 689 V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); 690 691 hns_roce_write512(hr_dev, wqe, qp->sq.db_reg); 692 } 693 694 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 695 const struct ib_send_wr *wr, 696 const struct ib_send_wr **bad_wr) 697 { 698 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 699 struct ib_device *ibdev = &hr_dev->ib_dev; 700 struct hns_roce_qp *qp = to_hr_qp(ibqp); 701 unsigned long flags = 0; 702 unsigned int owner_bit; 703 unsigned int sge_idx; 704 unsigned int wqe_idx; 705 void *wqe = NULL; 706 u32 nreq; 707 int ret; 708 709 spin_lock_irqsave(&qp->sq.lock, flags); 710 711 ret = check_send_valid(hr_dev, qp); 712 if (unlikely(ret)) { 713 *bad_wr = wr; 714 nreq = 0; 715 goto out; 716 } 717 718 sge_idx = qp->next_sge; 719 720 for (nreq = 0; wr; ++nreq, wr = wr->next) { 721 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 722 ret = -ENOMEM; 723 *bad_wr = wr; 724 goto out; 725 } 726 727 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 728 729 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 730 ibdev_err(ibdev, "num_sge = %d > qp->sq.max_gs = %u.\n", 731 wr->num_sge, qp->sq.max_gs); 732 ret = -EINVAL; 733 *bad_wr = wr; 734 goto out; 735 } 736 737 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 738 qp->sq.wrid[wqe_idx] = wr->wr_id; 739 owner_bit = 740 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 741 742 /* Corresponding to the QP type, wqe process separately */ 743 if (ibqp->qp_type == IB_QPT_RC) 744 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 745 else 746 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 747 748 if (unlikely(ret)) { 749 *bad_wr = wr; 750 goto out; 751 } 752 } 753 754 out: 755 if (likely(nreq)) { 756 qp->sq.head += nreq; 757 qp->next_sge = sge_idx; 758 759 if (nreq == 1 && (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) 760 write_dwqe(hr_dev, qp, wqe); 761 else 762 update_sq_db(hr_dev, qp); 763 } 764 765 spin_unlock_irqrestore(&qp->sq.lock, flags); 766 767 return ret; 768 } 769 770 static int check_recv_valid(struct hns_roce_dev *hr_dev, 771 struct hns_roce_qp *hr_qp) 772 { 773 struct ib_device *ibdev = &hr_dev->ib_dev; 774 struct ib_qp *ibqp = &hr_qp->ibqp; 775 776 if (unlikely(ibqp->qp_type != IB_QPT_RC && 777 ibqp->qp_type != IB_QPT_GSI && 778 ibqp->qp_type != IB_QPT_UD)) { 779 ibdev_err(ibdev, "unsupported qp type, qp_type = %d.\n", 780 ibqp->qp_type); 781 return -EOPNOTSUPP; 782 } 783 784 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 785 return -EIO; 786 787 if (hr_qp->state == IB_QPS_RESET) 788 return -EINVAL; 789 790 return 0; 791 } 792 793 static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, 794 u32 max_sge, bool rsv) 795 { 796 struct hns_roce_v2_wqe_data_seg *dseg = wqe; 797 u32 i, cnt; 798 799 for (i = 0, cnt = 0; i < wr->num_sge; i++) { 800 /* Skip zero-length sge */ 801 if (!wr->sg_list[i].length) 802 continue; 803 set_data_seg_v2(dseg + cnt, wr->sg_list + i); 804 cnt++; 805 } 806 807 /* Fill a reserved sge to make hw stop reading remaining segments */ 808 if (rsv) { 809 dseg[cnt].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 810 dseg[cnt].addr = 0; 811 dseg[cnt].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 812 } else { 813 /* Clear remaining segments to make ROCEE ignore sges */ 814 if (cnt < max_sge) 815 memset(dseg + cnt, 0, 816 (max_sge - cnt) * HNS_ROCE_SGE_SIZE); 817 } 818 } 819 820 static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, 821 u32 wqe_idx, u32 max_sge) 822 { 823 struct hns_roce_rinl_sge *sge_list; 824 void *wqe = NULL; 825 u32 i; 826 827 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 828 fill_recv_sge_to_wqe(wr, wqe, max_sge, hr_qp->rq.rsv_sge); 829 830 /* rq support inline data */ 831 if (hr_qp->rq_inl_buf.wqe_cnt) { 832 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 833 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = (u32)wr->num_sge; 834 for (i = 0; i < wr->num_sge; i++) { 835 sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr; 836 sge_list[i].len = wr->sg_list[i].length; 837 } 838 } 839 } 840 841 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 842 const struct ib_recv_wr *wr, 843 const struct ib_recv_wr **bad_wr) 844 { 845 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 846 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 847 struct ib_device *ibdev = &hr_dev->ib_dev; 848 u32 wqe_idx, nreq, max_sge; 849 unsigned long flags; 850 int ret; 851 852 spin_lock_irqsave(&hr_qp->rq.lock, flags); 853 854 ret = check_recv_valid(hr_dev, hr_qp); 855 if (unlikely(ret)) { 856 *bad_wr = wr; 857 nreq = 0; 858 goto out; 859 } 860 861 max_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 862 for (nreq = 0; wr; ++nreq, wr = wr->next) { 863 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 864 hr_qp->ibqp.recv_cq))) { 865 ret = -ENOMEM; 866 *bad_wr = wr; 867 goto out; 868 } 869 870 if (unlikely(wr->num_sge > max_sge)) { 871 ibdev_err(ibdev, "num_sge = %d >= max_sge = %u.\n", 872 wr->num_sge, max_sge); 873 ret = -EINVAL; 874 *bad_wr = wr; 875 goto out; 876 } 877 878 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 879 fill_rq_wqe(hr_qp, wr, wqe_idx, max_sge); 880 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 881 } 882 883 out: 884 if (likely(nreq)) { 885 hr_qp->rq.head += nreq; 886 887 update_rq_db(hr_dev, hr_qp); 888 } 889 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 890 891 return ret; 892 } 893 894 static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) 895 { 896 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 897 } 898 899 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) 900 { 901 return hns_roce_buf_offset(idx_que->mtr.kmem, 902 n << idx_que->entry_shift); 903 } 904 905 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) 906 { 907 /* always called with interrupts disabled. */ 908 spin_lock(&srq->lock); 909 910 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 911 srq->idx_que.tail++; 912 913 spin_unlock(&srq->lock); 914 } 915 916 static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) 917 { 918 struct hns_roce_idx_que *idx_que = &srq->idx_que; 919 920 return idx_que->head - idx_que->tail >= srq->wqe_cnt; 921 } 922 923 static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, 924 const struct ib_recv_wr *wr) 925 { 926 struct ib_device *ib_dev = srq->ibsrq.device; 927 928 if (unlikely(wr->num_sge > max_sge)) { 929 ibdev_err(ib_dev, 930 "failed to check sge, wr->num_sge = %d, max_sge = %u.\n", 931 wr->num_sge, max_sge); 932 return -EINVAL; 933 } 934 935 if (unlikely(hns_roce_srqwq_overflow(srq))) { 936 ibdev_err(ib_dev, 937 "failed to check srqwq status, srqwq is full.\n"); 938 return -ENOMEM; 939 } 940 941 return 0; 942 } 943 944 static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) 945 { 946 struct hns_roce_idx_que *idx_que = &srq->idx_que; 947 u32 pos; 948 949 pos = find_first_zero_bit(idx_que->bitmap, srq->wqe_cnt); 950 if (unlikely(pos == srq->wqe_cnt)) 951 return -ENOSPC; 952 953 bitmap_set(idx_que->bitmap, pos, 1); 954 *wqe_idx = pos; 955 return 0; 956 } 957 958 static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) 959 { 960 struct hns_roce_idx_que *idx_que = &srq->idx_que; 961 unsigned int head; 962 __le32 *buf; 963 964 head = idx_que->head & (srq->wqe_cnt - 1); 965 966 buf = get_idx_buf(idx_que, head); 967 *buf = cpu_to_le32(wqe_idx); 968 969 idx_que->head++; 970 } 971 972 static void update_srq_db(struct hns_roce_v2_db *db, struct hns_roce_srq *srq) 973 { 974 hr_reg_write(db, DB_TAG, srq->srqn); 975 hr_reg_write(db, DB_CMD, HNS_ROCE_V2_SRQ_DB); 976 hr_reg_write(db, DB_PI, srq->idx_que.head); 977 } 978 979 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 980 const struct ib_recv_wr *wr, 981 const struct ib_recv_wr **bad_wr) 982 { 983 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 984 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 985 struct hns_roce_v2_db srq_db; 986 unsigned long flags; 987 int ret = 0; 988 u32 max_sge; 989 u32 wqe_idx; 990 void *wqe; 991 u32 nreq; 992 993 spin_lock_irqsave(&srq->lock, flags); 994 995 max_sge = srq->max_gs - srq->rsv_sge; 996 for (nreq = 0; wr; ++nreq, wr = wr->next) { 997 ret = check_post_srq_valid(srq, max_sge, wr); 998 if (ret) { 999 *bad_wr = wr; 1000 break; 1001 } 1002 1003 ret = get_srq_wqe_idx(srq, &wqe_idx); 1004 if (unlikely(ret)) { 1005 *bad_wr = wr; 1006 break; 1007 } 1008 1009 wqe = get_srq_wqe_buf(srq, wqe_idx); 1010 fill_recv_sge_to_wqe(wr, wqe, max_sge, srq->rsv_sge); 1011 fill_wqe_idx(srq, wqe_idx); 1012 srq->wrid[wqe_idx] = wr->wr_id; 1013 } 1014 1015 if (likely(nreq)) { 1016 update_srq_db(&srq_db, srq); 1017 1018 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg); 1019 } 1020 1021 spin_unlock_irqrestore(&srq->lock, flags); 1022 1023 return ret; 1024 } 1025 1026 static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 1027 unsigned long instance_stage, 1028 unsigned long reset_stage) 1029 { 1030 /* When hardware reset has been completed once or more, we should stop 1031 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 1032 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 1033 * stage of soft reset process, we should exit with error, and then 1034 * HNAE3_INIT_CLIENT related process can rollback the operation like 1035 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 1036 * process will exit with error to notify NIC driver to reschedule soft 1037 * reset process once again. 1038 */ 1039 hr_dev->is_reset = true; 1040 hr_dev->dis_db = true; 1041 1042 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 1043 instance_stage == HNS_ROCE_STATE_INIT) 1044 return CMD_RST_PRC_EBUSY; 1045 1046 return CMD_RST_PRC_SUCCESS; 1047 } 1048 1049 static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 1050 unsigned long instance_stage, 1051 unsigned long reset_stage) 1052 { 1053 struct hns_roce_v2_priv *priv = hr_dev->priv; 1054 struct hnae3_handle *handle = priv->handle; 1055 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1056 1057 /* When hardware reset is detected, we should stop sending mailbox&cmq& 1058 * doorbell to hardware. If now in .init_instance() function, we should 1059 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 1060 * process, we should exit with error, and then HNAE3_INIT_CLIENT 1061 * related process can rollback the operation like notifing hardware to 1062 * free resources, HNAE3_INIT_CLIENT related process will exit with 1063 * error to notify NIC driver to reschedule soft reset process once 1064 * again. 1065 */ 1066 hr_dev->dis_db = true; 1067 if (!ops->get_hw_reset_stat(handle)) 1068 hr_dev->is_reset = true; 1069 1070 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 1071 instance_stage == HNS_ROCE_STATE_INIT) 1072 return CMD_RST_PRC_EBUSY; 1073 1074 return CMD_RST_PRC_SUCCESS; 1075 } 1076 1077 static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 1078 { 1079 struct hns_roce_v2_priv *priv = hr_dev->priv; 1080 struct hnae3_handle *handle = priv->handle; 1081 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1082 1083 /* When software reset is detected at .init_instance() function, we 1084 * should stop sending mailbox&cmq&doorbell to hardware, and exit 1085 * with error. 1086 */ 1087 hr_dev->dis_db = true; 1088 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 1089 hr_dev->is_reset = true; 1090 1091 return CMD_RST_PRC_EBUSY; 1092 } 1093 1094 static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, 1095 struct hnae3_handle *handle) 1096 { 1097 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1098 unsigned long instance_stage; /* the current instance stage */ 1099 unsigned long reset_stage; /* the current reset stage */ 1100 unsigned long reset_cnt; 1101 bool sw_resetting; 1102 bool hw_resetting; 1103 1104 /* Get information about reset from NIC driver or RoCE driver itself, 1105 * the meaning of the following variables from NIC driver are described 1106 * as below: 1107 * reset_cnt -- The count value of completed hardware reset. 1108 * hw_resetting -- Whether hardware device is resetting now. 1109 * sw_resetting -- Whether NIC's software reset process is running now. 1110 */ 1111 instance_stage = handle->rinfo.instance_state; 1112 reset_stage = handle->rinfo.reset_state; 1113 reset_cnt = ops->ae_dev_reset_cnt(handle); 1114 if (reset_cnt != hr_dev->reset_cnt) 1115 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 1116 reset_stage); 1117 1118 hw_resetting = ops->get_cmdq_stat(handle); 1119 if (hw_resetting) 1120 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 1121 reset_stage); 1122 1123 sw_resetting = ops->ae_dev_resetting(handle); 1124 if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 1125 return hns_roce_v2_cmd_sw_resetting(hr_dev); 1126 1127 return CMD_RST_PRC_OTHERS; 1128 } 1129 1130 static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) 1131 { 1132 struct hns_roce_v2_priv *priv = hr_dev->priv; 1133 struct hnae3_handle *handle = priv->handle; 1134 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1135 1136 if (hr_dev->reset_cnt != ops->ae_dev_reset_cnt(handle)) 1137 return true; 1138 1139 if (ops->get_hw_reset_stat(handle)) 1140 return true; 1141 1142 if (ops->ae_dev_resetting(handle)) 1143 return true; 1144 1145 return false; 1146 } 1147 1148 static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) 1149 { 1150 struct hns_roce_v2_priv *priv = hr_dev->priv; 1151 u32 status; 1152 1153 if (hr_dev->is_reset) 1154 status = CMD_RST_PRC_SUCCESS; 1155 else 1156 status = check_aedev_reset_status(hr_dev, priv->handle); 1157 1158 *busy = (status == CMD_RST_PRC_EBUSY); 1159 1160 return status == CMD_RST_PRC_OTHERS; 1161 } 1162 1163 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 1164 struct hns_roce_v2_cmq_ring *ring) 1165 { 1166 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 1167 1168 ring->desc = dma_alloc_coherent(hr_dev->dev, size, 1169 &ring->desc_dma_addr, GFP_KERNEL); 1170 if (!ring->desc) 1171 return -ENOMEM; 1172 1173 return 0; 1174 } 1175 1176 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 1177 struct hns_roce_v2_cmq_ring *ring) 1178 { 1179 dma_free_coherent(hr_dev->dev, 1180 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 1181 ring->desc, ring->desc_dma_addr); 1182 1183 ring->desc_dma_addr = 0; 1184 } 1185 1186 static int init_csq(struct hns_roce_dev *hr_dev, 1187 struct hns_roce_v2_cmq_ring *csq) 1188 { 1189 dma_addr_t dma; 1190 int ret; 1191 1192 csq->desc_num = CMD_CSQ_DESC_NUM; 1193 spin_lock_init(&csq->lock); 1194 csq->flag = TYPE_CSQ; 1195 csq->head = 0; 1196 1197 ret = hns_roce_alloc_cmq_desc(hr_dev, csq); 1198 if (ret) 1199 return ret; 1200 1201 dma = csq->desc_dma_addr; 1202 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma)); 1203 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma)); 1204 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 1205 (u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1206 1207 /* Make sure to write CI first and then PI */ 1208 roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0); 1209 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0); 1210 1211 return 0; 1212 } 1213 1214 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1215 { 1216 struct hns_roce_v2_priv *priv = hr_dev->priv; 1217 int ret; 1218 1219 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1220 1221 ret = init_csq(hr_dev, &priv->cmq.csq); 1222 if (ret) 1223 dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret); 1224 1225 return ret; 1226 } 1227 1228 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1229 { 1230 struct hns_roce_v2_priv *priv = hr_dev->priv; 1231 1232 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1233 } 1234 1235 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1236 enum hns_roce_opcode_type opcode, 1237 bool is_read) 1238 { 1239 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1240 desc->opcode = cpu_to_le16(opcode); 1241 desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1242 if (is_read) 1243 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1244 else 1245 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1246 } 1247 1248 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1249 { 1250 u32 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1251 struct hns_roce_v2_priv *priv = hr_dev->priv; 1252 1253 return tail == priv->cmq.csq.head; 1254 } 1255 1256 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1257 struct hns_roce_cmq_desc *desc, int num) 1258 { 1259 struct hns_roce_v2_priv *priv = hr_dev->priv; 1260 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1261 u32 timeout = 0; 1262 u16 desc_ret; 1263 u32 tail; 1264 int ret; 1265 int i; 1266 1267 spin_lock_bh(&csq->lock); 1268 1269 tail = csq->head; 1270 1271 for (i = 0; i < num; i++) { 1272 csq->desc[csq->head++] = desc[i]; 1273 if (csq->head == csq->desc_num) 1274 csq->head = 0; 1275 } 1276 1277 /* Write to hardware */ 1278 roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, csq->head); 1279 1280 do { 1281 if (hns_roce_cmq_csq_done(hr_dev)) 1282 break; 1283 udelay(1); 1284 } while (++timeout < priv->cmq.tx_timeout); 1285 1286 if (hns_roce_cmq_csq_done(hr_dev)) { 1287 for (ret = 0, i = 0; i < num; i++) { 1288 /* check the result of hardware write back */ 1289 desc[i] = csq->desc[tail++]; 1290 if (tail == csq->desc_num) 1291 tail = 0; 1292 1293 desc_ret = le16_to_cpu(desc[i].retval); 1294 if (likely(desc_ret == CMD_EXEC_SUCCESS)) 1295 continue; 1296 1297 dev_err_ratelimited(hr_dev->dev, 1298 "Cmdq IO error, opcode = %x, return = %x\n", 1299 desc->opcode, desc_ret); 1300 ret = -EIO; 1301 } 1302 } else { 1303 /* FW/HW reset or incorrect number of desc */ 1304 tail = roce_read(hr_dev, ROCEE_TX_CMQ_CI_REG); 1305 dev_warn(hr_dev->dev, "CMDQ move tail from %d to %d\n", 1306 csq->head, tail); 1307 csq->head = tail; 1308 1309 ret = -EAGAIN; 1310 } 1311 1312 spin_unlock_bh(&csq->lock); 1313 1314 return ret; 1315 } 1316 1317 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1318 struct hns_roce_cmq_desc *desc, int num) 1319 { 1320 bool busy; 1321 int ret; 1322 1323 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1324 return busy ? -EBUSY : 0; 1325 1326 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1327 if (ret) { 1328 if (!v2_chk_mbox_is_avail(hr_dev, &busy)) 1329 return busy ? -EBUSY : 0; 1330 } 1331 1332 return ret; 1333 } 1334 1335 static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 1336 dma_addr_t base_addr, u16 op) 1337 { 1338 struct hns_roce_cmd_mailbox *mbox = hns_roce_alloc_cmd_mailbox(hr_dev); 1339 int ret; 1340 1341 if (IS_ERR(mbox)) 1342 return PTR_ERR(mbox); 1343 1344 ret = hns_roce_cmd_mbox(hr_dev, base_addr, mbox->dma, obj, 0, op, 1345 HNS_ROCE_CMD_TIMEOUT_MSECS); 1346 hns_roce_free_cmd_mailbox(hr_dev, mbox); 1347 return ret; 1348 } 1349 1350 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1351 { 1352 struct hns_roce_query_version *resp; 1353 struct hns_roce_cmq_desc desc; 1354 int ret; 1355 1356 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1357 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1358 if (ret) 1359 return ret; 1360 1361 resp = (struct hns_roce_query_version *)desc.data; 1362 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1363 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1364 1365 return 0; 1366 } 1367 1368 static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, 1369 struct hnae3_handle *handle) 1370 { 1371 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1372 unsigned long end; 1373 1374 hr_dev->dis_db = true; 1375 1376 dev_warn(hr_dev->dev, 1377 "Func clear is pending, device in resetting state.\n"); 1378 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1379 while (end) { 1380 if (!ops->get_hw_reset_stat(handle)) { 1381 hr_dev->is_reset = true; 1382 dev_info(hr_dev->dev, 1383 "Func clear success after reset.\n"); 1384 return; 1385 } 1386 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1387 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1388 } 1389 1390 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1391 } 1392 1393 static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, 1394 struct hnae3_handle *handle) 1395 { 1396 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1397 unsigned long end; 1398 1399 hr_dev->dis_db = true; 1400 1401 dev_warn(hr_dev->dev, 1402 "Func clear is pending, device in resetting state.\n"); 1403 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1404 while (end) { 1405 if (ops->ae_dev_reset_cnt(handle) != 1406 hr_dev->reset_cnt) { 1407 hr_dev->is_reset = true; 1408 dev_info(hr_dev->dev, 1409 "Func clear success after sw reset\n"); 1410 return; 1411 } 1412 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1413 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1414 } 1415 1416 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1417 } 1418 1419 static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, 1420 int flag) 1421 { 1422 struct hns_roce_v2_priv *priv = hr_dev->priv; 1423 struct hnae3_handle *handle = priv->handle; 1424 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1425 1426 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) { 1427 hr_dev->dis_db = true; 1428 hr_dev->is_reset = true; 1429 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1430 return; 1431 } 1432 1433 if (ops->get_hw_reset_stat(handle)) { 1434 func_clr_hw_resetting_state(hr_dev, handle); 1435 return; 1436 } 1437 1438 if (ops->ae_dev_resetting(handle) && 1439 handle->rinfo.instance_state == HNS_ROCE_STATE_INIT) { 1440 func_clr_sw_resetting_state(hr_dev, handle); 1441 return; 1442 } 1443 1444 if (retval && !flag) 1445 dev_warn(hr_dev->dev, 1446 "Func clear read failed, ret = %d.\n", retval); 1447 1448 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1449 } 1450 1451 static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) 1452 { 1453 bool fclr_write_fail_flag = false; 1454 struct hns_roce_func_clear *resp; 1455 struct hns_roce_cmq_desc desc; 1456 unsigned long end; 1457 int ret = 0; 1458 1459 if (check_device_is_in_reset(hr_dev)) 1460 goto out; 1461 1462 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1463 resp = (struct hns_roce_func_clear *)desc.data; 1464 resp->rst_funcid_en = cpu_to_le32(vf_id); 1465 1466 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1467 if (ret) { 1468 fclr_write_fail_flag = true; 1469 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1470 ret); 1471 goto out; 1472 } 1473 1474 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1475 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1476 while (end) { 1477 if (check_device_is_in_reset(hr_dev)) 1478 goto out; 1479 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1480 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1481 1482 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1483 true); 1484 1485 resp->rst_funcid_en = cpu_to_le32(vf_id); 1486 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1487 if (ret) 1488 continue; 1489 1490 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1491 if (vf_id == 0) 1492 hr_dev->is_reset = true; 1493 return; 1494 } 1495 } 1496 1497 out: 1498 hns_roce_func_clr_rst_proc(hr_dev, ret, fclr_write_fail_flag); 1499 } 1500 1501 static void hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) 1502 { 1503 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1504 struct hns_roce_cmq_desc desc[2]; 1505 struct hns_roce_cmq_req *req_a; 1506 1507 req_a = (struct hns_roce_cmq_req *)desc[0].data; 1508 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1509 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1510 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1511 hr_reg_write(req_a, FUNC_RES_A_VF_ID, vf_id); 1512 hns_roce_cmq_send(hr_dev, desc, 2); 1513 } 1514 1515 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1516 { 1517 int i; 1518 1519 for (i = hr_dev->func_num - 1; i >= 0; i--) { 1520 __hns_roce_function_clear(hr_dev, i); 1521 if (i != 0) 1522 hns_roce_free_vf_resource(hr_dev, i); 1523 } 1524 } 1525 1526 static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) 1527 { 1528 struct hns_roce_cmq_desc desc; 1529 int ret; 1530 1531 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO, 1532 false); 1533 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1534 if (ret) 1535 ibdev_err(&hr_dev->ib_dev, 1536 "failed to clear extended doorbell info, ret = %d.\n", 1537 ret); 1538 1539 return ret; 1540 } 1541 1542 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1543 { 1544 struct hns_roce_query_fw_info *resp; 1545 struct hns_roce_cmq_desc desc; 1546 int ret; 1547 1548 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1549 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1550 if (ret) 1551 return ret; 1552 1553 resp = (struct hns_roce_query_fw_info *)desc.data; 1554 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1555 1556 return 0; 1557 } 1558 1559 static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) 1560 { 1561 struct hns_roce_cmq_desc desc; 1562 int ret; 1563 1564 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) { 1565 hr_dev->func_num = 1; 1566 return 0; 1567 } 1568 1569 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_FUNC_INFO, 1570 true); 1571 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1572 if (ret) { 1573 hr_dev->func_num = 1; 1574 return ret; 1575 } 1576 1577 hr_dev->func_num = le32_to_cpu(desc.func_info.own_func_num); 1578 hr_dev->cong_algo_tmpl_id = le32_to_cpu(desc.func_info.own_mac_id); 1579 1580 return 0; 1581 } 1582 1583 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1584 { 1585 struct hns_roce_cmq_desc desc; 1586 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1587 1588 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1589 false); 1590 1591 hr_reg_write(req, CFG_GLOBAL_PARAM_1US_CYCLES, 0x3e8); 1592 hr_reg_write(req, CFG_GLOBAL_PARAM_UDP_PORT, ROCE_V2_UDP_DPORT); 1593 1594 return hns_roce_cmq_send(hr_dev, &desc, 1); 1595 } 1596 1597 static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1598 { 1599 struct hns_roce_cmq_desc desc[2]; 1600 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1601 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1602 struct hns_roce_caps *caps = &hr_dev->caps; 1603 enum hns_roce_opcode_type opcode; 1604 u32 func_num; 1605 int ret; 1606 1607 if (is_vf) { 1608 opcode = HNS_ROCE_OPC_QUERY_VF_RES; 1609 func_num = 1; 1610 } else { 1611 opcode = HNS_ROCE_OPC_QUERY_PF_RES; 1612 func_num = hr_dev->func_num; 1613 } 1614 1615 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, true); 1616 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1617 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, true); 1618 1619 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1620 if (ret) 1621 return ret; 1622 1623 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; 1624 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; 1625 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; 1626 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; 1627 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; 1628 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; 1629 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; 1630 caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num; 1631 1632 if (is_vf) { 1633 caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num; 1634 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) / 1635 func_num; 1636 } else { 1637 caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num; 1638 caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) / 1639 func_num; 1640 } 1641 1642 return 0; 1643 } 1644 1645 static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1646 { 1647 struct hns_roce_cmq_desc desc; 1648 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1649 struct hns_roce_caps *caps = &hr_dev->caps; 1650 u32 func_num, qp_num; 1651 int ret; 1652 1653 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true); 1654 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1655 if (ret) 1656 return ret; 1657 1658 func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num); 1659 qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num; 1660 caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1661 1662 qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num; 1663 caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM); 1664 1665 return 0; 1666 } 1667 1668 static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 1669 { 1670 struct hns_roce_cmq_desc desc; 1671 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1672 struct hns_roce_caps *caps = &hr_dev->caps; 1673 int ret; 1674 1675 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1676 true); 1677 1678 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1679 if (ret) 1680 return ret; 1681 1682 caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM); 1683 caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM); 1684 1685 return 0; 1686 } 1687 1688 static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf) 1689 { 1690 struct device *dev = hr_dev->dev; 1691 int ret; 1692 1693 ret = load_func_res_caps(hr_dev, is_vf); 1694 if (ret) { 1695 dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret, 1696 is_vf ? "vf" : "pf"); 1697 return ret; 1698 } 1699 1700 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1701 ret = load_ext_cfg_caps(hr_dev, is_vf); 1702 if (ret) 1703 dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n", 1704 ret, is_vf ? "vf" : "pf"); 1705 } 1706 1707 return ret; 1708 } 1709 1710 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1711 { 1712 struct device *dev = hr_dev->dev; 1713 int ret; 1714 1715 ret = query_func_resource_caps(hr_dev, false); 1716 if (ret) 1717 return ret; 1718 1719 ret = load_pf_timer_res_caps(hr_dev); 1720 if (ret) 1721 dev_err(dev, "failed to load pf timer resource, ret = %d.\n", 1722 ret); 1723 1724 return ret; 1725 } 1726 1727 static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) 1728 { 1729 return query_func_resource_caps(hr_dev, true); 1730 } 1731 1732 static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, 1733 u32 vf_id) 1734 { 1735 struct hns_roce_vf_switch *swt; 1736 struct hns_roce_cmq_desc desc; 1737 int ret; 1738 1739 swt = (struct hns_roce_vf_switch *)desc.data; 1740 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1741 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1742 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1743 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1744 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1745 if (ret) 1746 return ret; 1747 1748 desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); 1749 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1750 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1751 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1752 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1753 1754 return hns_roce_cmq_send(hr_dev, &desc, 1); 1755 } 1756 1757 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) 1758 { 1759 u32 vf_id; 1760 int ret; 1761 1762 for (vf_id = 0; vf_id < hr_dev->func_num; vf_id++) { 1763 ret = __hns_roce_set_vf_switch_param(hr_dev, vf_id); 1764 if (ret) 1765 return ret; 1766 } 1767 return 0; 1768 } 1769 1770 static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 1771 { 1772 struct hns_roce_cmq_desc desc[2]; 1773 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 1774 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 1775 enum hns_roce_opcode_type opcode = HNS_ROCE_OPC_ALLOC_VF_RES; 1776 struct hns_roce_caps *caps = &hr_dev->caps; 1777 1778 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 1779 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1780 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 1781 1782 hr_reg_write(r_a, FUNC_RES_A_VF_ID, vf_id); 1783 1784 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_NUM, caps->qpc_bt_num); 1785 hr_reg_write(r_a, FUNC_RES_A_QPC_BT_IDX, vf_id * caps->qpc_bt_num); 1786 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_NUM, caps->srqc_bt_num); 1787 hr_reg_write(r_a, FUNC_RES_A_SRQC_BT_IDX, vf_id * caps->srqc_bt_num); 1788 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_NUM, caps->cqc_bt_num); 1789 hr_reg_write(r_a, FUNC_RES_A_CQC_BT_IDX, vf_id * caps->cqc_bt_num); 1790 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_NUM, caps->mpt_bt_num); 1791 hr_reg_write(r_a, FUNC_RES_A_MPT_BT_IDX, vf_id * caps->mpt_bt_num); 1792 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_NUM, caps->eqc_bt_num); 1793 hr_reg_write(r_a, FUNC_RES_A_EQC_BT_IDX, vf_id * caps->eqc_bt_num); 1794 hr_reg_write(r_b, FUNC_RES_V_QID_NUM, caps->sl_num); 1795 hr_reg_write(r_b, FUNC_RES_B_QID_IDX, vf_id * caps->sl_num); 1796 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_NUM, caps->sccc_bt_num); 1797 hr_reg_write(r_b, FUNC_RES_B_SCCC_BT_IDX, vf_id * caps->sccc_bt_num); 1798 1799 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1800 hr_reg_write(r_b, FUNC_RES_V_GMV_BT_NUM, caps->gmv_bt_num); 1801 hr_reg_write(r_b, FUNC_RES_B_GMV_BT_IDX, 1802 vf_id * caps->gmv_bt_num); 1803 } else { 1804 hr_reg_write(r_b, FUNC_RES_B_SGID_NUM, caps->sgid_bt_num); 1805 hr_reg_write(r_b, FUNC_RES_B_SGID_IDX, 1806 vf_id * caps->sgid_bt_num); 1807 hr_reg_write(r_b, FUNC_RES_B_SMAC_NUM, caps->smac_bt_num); 1808 hr_reg_write(r_b, FUNC_RES_B_SMAC_IDX, 1809 vf_id * caps->smac_bt_num); 1810 } 1811 1812 return hns_roce_cmq_send(hr_dev, desc, 2); 1813 } 1814 1815 static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id) 1816 { 1817 struct hns_roce_cmq_desc desc; 1818 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1819 struct hns_roce_caps *caps = &hr_dev->caps; 1820 1821 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false); 1822 1823 hr_reg_write(req, EXT_CFG_VF_ID, vf_id); 1824 1825 hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps); 1826 hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps); 1827 hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps); 1828 hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps); 1829 1830 return hns_roce_cmq_send(hr_dev, &desc, 1); 1831 } 1832 1833 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1834 { 1835 u32 func_num = max_t(u32, 1, hr_dev->func_num); 1836 u32 vf_id; 1837 int ret; 1838 1839 for (vf_id = 0; vf_id < func_num; vf_id++) { 1840 ret = config_vf_hem_resource(hr_dev, vf_id); 1841 if (ret) { 1842 dev_err(hr_dev->dev, 1843 "failed to config vf-%u hem res, ret = %d.\n", 1844 vf_id, ret); 1845 return ret; 1846 } 1847 1848 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1849 ret = config_vf_ext_resource(hr_dev, vf_id); 1850 if (ret) { 1851 dev_err(hr_dev->dev, 1852 "failed to config vf-%u ext res, ret = %d.\n", 1853 vf_id, ret); 1854 return ret; 1855 } 1856 } 1857 } 1858 1859 return 0; 1860 } 1861 1862 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1863 { 1864 struct hns_roce_cmq_desc desc; 1865 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 1866 struct hns_roce_caps *caps = &hr_dev->caps; 1867 1868 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1869 1870 hr_reg_write(req, CFG_BT_ATTR_QPC_BA_PGSZ, 1871 caps->qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1872 hr_reg_write(req, CFG_BT_ATTR_QPC_BUF_PGSZ, 1873 caps->qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1874 hr_reg_write(req, CFG_BT_ATTR_QPC_HOPNUM, 1875 to_hr_hem_hopnum(caps->qpc_hop_num, caps->num_qps)); 1876 1877 hr_reg_write(req, CFG_BT_ATTR_SRQC_BA_PGSZ, 1878 caps->srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1879 hr_reg_write(req, CFG_BT_ATTR_SRQC_BUF_PGSZ, 1880 caps->srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1881 hr_reg_write(req, CFG_BT_ATTR_SRQC_HOPNUM, 1882 to_hr_hem_hopnum(caps->srqc_hop_num, caps->num_srqs)); 1883 1884 hr_reg_write(req, CFG_BT_ATTR_CQC_BA_PGSZ, 1885 caps->cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1886 hr_reg_write(req, CFG_BT_ATTR_CQC_BUF_PGSZ, 1887 caps->cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1888 hr_reg_write(req, CFG_BT_ATTR_CQC_HOPNUM, 1889 to_hr_hem_hopnum(caps->cqc_hop_num, caps->num_cqs)); 1890 1891 hr_reg_write(req, CFG_BT_ATTR_MPT_BA_PGSZ, 1892 caps->mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1893 hr_reg_write(req, CFG_BT_ATTR_MPT_BUF_PGSZ, 1894 caps->mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1895 hr_reg_write(req, CFG_BT_ATTR_MPT_HOPNUM, 1896 to_hr_hem_hopnum(caps->mpt_hop_num, caps->num_mtpts)); 1897 1898 hr_reg_write(req, CFG_BT_ATTR_SCCC_BA_PGSZ, 1899 caps->sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1900 hr_reg_write(req, CFG_BT_ATTR_SCCC_BUF_PGSZ, 1901 caps->sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1902 hr_reg_write(req, CFG_BT_ATTR_SCCC_HOPNUM, 1903 to_hr_hem_hopnum(caps->sccc_hop_num, caps->num_qps)); 1904 1905 return hns_roce_cmq_send(hr_dev, &desc, 1); 1906 } 1907 1908 /* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */ 1909 static void set_default_caps(struct hns_roce_dev *hr_dev) 1910 { 1911 struct hns_roce_caps *caps = &hr_dev->caps; 1912 1913 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1914 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1915 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1916 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1917 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1918 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1919 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1920 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1921 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1922 1923 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1924 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1925 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1926 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1927 caps->num_comp_vectors = 0; 1928 1929 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1930 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1931 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1932 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1933 1934 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1935 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1936 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1937 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1938 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1939 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1940 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1941 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1942 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1943 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1944 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1945 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1946 caps->reserved_lkey = 0; 1947 caps->reserved_pds = 0; 1948 caps->reserved_mrws = 1; 1949 caps->reserved_uars = 0; 1950 caps->reserved_cqs = 0; 1951 caps->reserved_srqs = 0; 1952 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1953 1954 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1955 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1956 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1957 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1958 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1959 1960 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1961 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1962 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1963 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1964 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1965 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1966 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1967 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1968 1969 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1970 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1971 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB | 1972 HNS_ROCE_CAP_FLAG_QP_RECORD_DB; 1973 1974 caps->pkey_table_len[0] = 1; 1975 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1976 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1977 caps->local_ca_ack_delay = 0; 1978 caps->max_mtu = IB_MTU_4096; 1979 1980 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1981 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1982 1983 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1984 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1985 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC; 1986 1987 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1988 1989 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 1990 caps->flags |= HNS_ROCE_CAP_FLAG_STASH; 1991 caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; 1992 } else { 1993 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1994 1995 /* The following configuration are only valid for HIP08 */ 1996 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ; 1997 caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ; 1998 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE; 1999 } 2000 } 2001 2002 static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, 2003 u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) 2004 { 2005 u64 obj_per_chunk; 2006 u64 bt_chunk_size = PAGE_SIZE; 2007 u64 buf_chunk_size = PAGE_SIZE; 2008 u64 obj_per_chunk_default = buf_chunk_size / obj_size; 2009 2010 *buf_page_size = 0; 2011 *bt_page_size = 0; 2012 2013 switch (hop_num) { 2014 case 3: 2015 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2016 (bt_chunk_size / BA_BYTE_LEN) * 2017 (bt_chunk_size / BA_BYTE_LEN) * 2018 obj_per_chunk_default; 2019 break; 2020 case 2: 2021 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2022 (bt_chunk_size / BA_BYTE_LEN) * 2023 obj_per_chunk_default; 2024 break; 2025 case 1: 2026 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 2027 obj_per_chunk_default; 2028 break; 2029 case HNS_ROCE_HOP_NUM_0: 2030 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 2031 break; 2032 default: 2033 pr_err("table %u not support hop_num = %u!\n", hem_type, 2034 hop_num); 2035 return; 2036 } 2037 2038 if (hem_type >= HEM_TYPE_MTT) 2039 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2040 else 2041 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 2042 } 2043 2044 static void set_hem_page_size(struct hns_roce_dev *hr_dev) 2045 { 2046 struct hns_roce_caps *caps = &hr_dev->caps; 2047 2048 /* EQ */ 2049 caps->eqe_ba_pg_sz = 0; 2050 caps->eqe_buf_pg_sz = 0; 2051 2052 /* Link Table */ 2053 caps->llm_buf_pg_sz = 0; 2054 2055 /* MR */ 2056 caps->mpt_ba_pg_sz = 0; 2057 caps->mpt_buf_pg_sz = 0; 2058 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2059 caps->pbl_buf_pg_sz = 0; 2060 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 2061 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 2062 HEM_TYPE_MTPT); 2063 2064 /* QP */ 2065 caps->qpc_ba_pg_sz = 0; 2066 caps->qpc_buf_pg_sz = 0; 2067 caps->qpc_timer_ba_pg_sz = 0; 2068 caps->qpc_timer_buf_pg_sz = 0; 2069 caps->sccc_ba_pg_sz = 0; 2070 caps->sccc_buf_pg_sz = 0; 2071 caps->mtt_ba_pg_sz = 0; 2072 caps->mtt_buf_pg_sz = 0; 2073 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num, 2074 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 2075 HEM_TYPE_QPC); 2076 2077 if (caps->flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 2078 calc_pg_sz(caps->num_qps, caps->sccc_sz, caps->sccc_hop_num, 2079 caps->sccc_bt_num, &caps->sccc_buf_pg_sz, 2080 &caps->sccc_ba_pg_sz, HEM_TYPE_SCCC); 2081 2082 /* CQ */ 2083 caps->cqc_ba_pg_sz = 0; 2084 caps->cqc_buf_pg_sz = 0; 2085 caps->cqc_timer_ba_pg_sz = 0; 2086 caps->cqc_timer_buf_pg_sz = 0; 2087 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 2088 caps->cqe_buf_pg_sz = 0; 2089 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 2090 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 2091 HEM_TYPE_CQC); 2092 calc_pg_sz(caps->max_cqes, caps->cqe_sz, caps->cqe_hop_num, 2093 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2094 2095 /* SRQ */ 2096 if (caps->flags & HNS_ROCE_CAP_FLAG_SRQ) { 2097 caps->srqc_ba_pg_sz = 0; 2098 caps->srqc_buf_pg_sz = 0; 2099 caps->srqwqe_ba_pg_sz = 0; 2100 caps->srqwqe_buf_pg_sz = 0; 2101 caps->idx_ba_pg_sz = 0; 2102 caps->idx_buf_pg_sz = 0; 2103 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, 2104 caps->srqc_hop_num, caps->srqc_bt_num, 2105 &caps->srqc_buf_pg_sz, &caps->srqc_ba_pg_sz, 2106 HEM_TYPE_SRQC); 2107 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2108 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2109 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2110 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, 2111 caps->idx_hop_num, 1, &caps->idx_buf_pg_sz, 2112 &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2113 } 2114 2115 /* GMV */ 2116 caps->gmv_ba_pg_sz = 0; 2117 caps->gmv_buf_pg_sz = 0; 2118 } 2119 2120 /* Apply all loaded caps before setting to hardware */ 2121 static void apply_func_caps(struct hns_roce_dev *hr_dev) 2122 { 2123 struct hns_roce_caps *caps = &hr_dev->caps; 2124 struct hns_roce_v2_priv *priv = hr_dev->priv; 2125 2126 /* The following configurations don't need to be got from firmware. */ 2127 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 2128 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 2129 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 2130 2131 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2132 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2133 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2134 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2135 2136 caps->num_xrcds = HNS_ROCE_V2_MAX_XRCD_NUM; 2137 caps->reserved_xrcds = HNS_ROCE_V2_RSV_XRCD_NUM; 2138 2139 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 2140 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 2141 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 2142 2143 if (!caps->num_comp_vectors) 2144 caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1, 2145 (u32)priv->handle->rinfo.num_vectors - 2); 2146 2147 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 2148 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE; 2149 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE; 2150 2151 /* The following configurations will be overwritten */ 2152 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ; 2153 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE; 2154 caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ; 2155 2156 /* The following configurations are not got from firmware */ 2157 caps->gmv_entry_sz = HNS_ROCE_V3_GMV_ENTRY_SZ; 2158 2159 caps->gmv_hop_num = HNS_ROCE_HOP_NUM_0; 2160 caps->gid_table_len[0] = caps->gmv_bt_num * 2161 (HNS_HW_PAGE_SIZE / caps->gmv_entry_sz); 2162 2163 caps->gmv_entry_num = caps->gmv_bt_num * (PAGE_SIZE / 2164 caps->gmv_entry_sz); 2165 } else { 2166 u32 func_num = max_t(u32, 1, hr_dev->func_num); 2167 2168 caps->ceqe_size = HNS_ROCE_CEQE_SIZE; 2169 caps->aeqe_size = HNS_ROCE_AEQE_SIZE; 2170 caps->gid_table_len[0] /= func_num; 2171 } 2172 2173 if (hr_dev->is_vf) { 2174 caps->default_aeq_arm_st = 0x3; 2175 caps->default_ceq_arm_st = 0x3; 2176 caps->default_ceq_max_cnt = 0x1; 2177 caps->default_ceq_period = 0x10; 2178 caps->default_aeq_max_cnt = 0x1; 2179 caps->default_aeq_period = 0x10; 2180 } 2181 2182 set_hem_page_size(hr_dev); 2183 } 2184 2185 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 2186 { 2187 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 2188 struct hns_roce_caps *caps = &hr_dev->caps; 2189 struct hns_roce_query_pf_caps_a *resp_a; 2190 struct hns_roce_query_pf_caps_b *resp_b; 2191 struct hns_roce_query_pf_caps_c *resp_c; 2192 struct hns_roce_query_pf_caps_d *resp_d; 2193 struct hns_roce_query_pf_caps_e *resp_e; 2194 int ctx_hop_num; 2195 int pbl_hop_num; 2196 int ret; 2197 int i; 2198 2199 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 2200 hns_roce_cmq_setup_basic_desc(&desc[i], 2201 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 2202 true); 2203 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 2204 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2205 else 2206 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2207 } 2208 2209 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 2210 if (ret) 2211 return ret; 2212 2213 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 2214 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 2215 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 2216 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 2217 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 2218 2219 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 2220 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 2221 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 2222 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 2223 caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg); 2224 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 2225 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 2226 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 2227 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 2228 caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges); 2229 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 2230 caps->num_other_vectors = resp_a->num_other_vectors; 2231 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 2232 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 2233 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 2234 caps->cqe_sz = resp_a->cqe_sz; 2235 2236 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 2237 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 2238 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 2239 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 2240 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 2241 caps->idx_entry_sz = resp_b->idx_entry_sz; 2242 caps->sccc_sz = resp_b->sccc_sz; 2243 caps->max_mtu = resp_b->max_mtu; 2244 caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz); 2245 caps->min_cqes = resp_b->min_cqes; 2246 caps->min_wqes = resp_b->min_wqes; 2247 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 2248 caps->pkey_table_len[0] = resp_b->pkey_table_len; 2249 caps->phy_num_uars = resp_b->phy_num_uars; 2250 ctx_hop_num = resp_b->ctx_hop_num; 2251 pbl_hop_num = resp_b->pbl_hop_num; 2252 2253 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 2254 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 2255 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 2256 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 2257 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 2258 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 2259 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 2260 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 2261 2262 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 2263 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 2264 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 2265 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 2266 V2_QUERY_PF_CAPS_C_MAX_GID_M, 2267 V2_QUERY_PF_CAPS_C_MAX_GID_S); 2268 2269 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 2270 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 2271 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 2272 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 2273 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 2274 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 2275 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 2276 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 2277 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 2278 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 2279 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 2280 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 2281 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 2282 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 2283 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 2284 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 2285 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 2286 caps->cong_type = roce_get_field(resp_d->wq_hop_num_max_srqs, 2287 V2_QUERY_PF_CAPS_D_CONG_TYPE_M, 2288 V2_QUERY_PF_CAPS_D_CONG_TYPE_S); 2289 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 2290 2291 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 2292 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 2293 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 2294 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 2295 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 2296 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 2297 2298 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 2299 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 2300 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 2301 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2302 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 2303 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 2304 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 2305 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 2306 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 2307 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 2308 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 2309 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 2310 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 2311 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 2312 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 2313 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 2314 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 2315 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 2316 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 2317 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 2318 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 2319 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2320 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 2321 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 2322 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 2323 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 2324 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 2325 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 2326 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 2327 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 2328 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 2329 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 2330 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 2331 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 2332 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 2333 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 2334 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 2335 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 2336 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 2337 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 2338 2339 caps->qpc_hop_num = ctx_hop_num; 2340 caps->sccc_hop_num = ctx_hop_num; 2341 caps->srqc_hop_num = ctx_hop_num; 2342 caps->cqc_hop_num = ctx_hop_num; 2343 caps->mpt_hop_num = ctx_hop_num; 2344 caps->mtt_hop_num = pbl_hop_num; 2345 caps->cqe_hop_num = pbl_hop_num; 2346 caps->srqwqe_hop_num = pbl_hop_num; 2347 caps->idx_hop_num = pbl_hop_num; 2348 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2349 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 2350 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 2351 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2352 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 2353 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 2354 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 2355 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 2356 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 2357 2358 return 0; 2359 } 2360 2361 static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) 2362 { 2363 struct hns_roce_cmq_desc desc; 2364 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 2365 2366 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE, 2367 false); 2368 2369 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_TYPE, type); 2370 hr_reg_write(req, CFG_HEM_ENTRY_SIZE_VALUE, val); 2371 2372 return hns_roce_cmq_send(hr_dev, &desc, 1); 2373 } 2374 2375 static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 2376 { 2377 struct hns_roce_caps *caps = &hr_dev->caps; 2378 int ret; 2379 2380 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09) 2381 return 0; 2382 2383 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_QPC_SIZE, 2384 caps->qpc_sz); 2385 if (ret) { 2386 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret); 2387 return ret; 2388 } 2389 2390 ret = config_hem_entry_size(hr_dev, HNS_ROCE_CFG_SCCC_SIZE, 2391 caps->sccc_sz); 2392 if (ret) 2393 dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret); 2394 2395 return ret; 2396 } 2397 2398 static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 2399 { 2400 struct device *dev = hr_dev->dev; 2401 int ret; 2402 2403 hr_dev->func_num = 1; 2404 2405 set_default_caps(hr_dev); 2406 2407 ret = hns_roce_query_vf_resource(hr_dev); 2408 if (ret) { 2409 dev_err(dev, "failed to query VF resource, ret = %d.\n", ret); 2410 return ret; 2411 } 2412 2413 apply_func_caps(hr_dev); 2414 2415 ret = hns_roce_v2_set_bt(hr_dev); 2416 if (ret) 2417 dev_err(dev, "failed to config VF BA table, ret = %d.\n", ret); 2418 2419 return ret; 2420 } 2421 2422 static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 2423 { 2424 struct device *dev = hr_dev->dev; 2425 int ret; 2426 2427 ret = hns_roce_query_func_info(hr_dev); 2428 if (ret) { 2429 dev_err(dev, "failed to query func info, ret = %d.\n", ret); 2430 return ret; 2431 } 2432 2433 ret = hns_roce_config_global_param(hr_dev); 2434 if (ret) { 2435 dev_err(dev, "failed to config global param, ret = %d.\n", ret); 2436 return ret; 2437 } 2438 2439 ret = hns_roce_set_vf_switch_param(hr_dev); 2440 if (ret) { 2441 dev_err(dev, "failed to set switch param, ret = %d.\n", ret); 2442 return ret; 2443 } 2444 2445 ret = hns_roce_query_pf_caps(hr_dev); 2446 if (ret) 2447 set_default_caps(hr_dev); 2448 2449 ret = hns_roce_query_pf_resource(hr_dev); 2450 if (ret) { 2451 dev_err(dev, "failed to query pf resource, ret = %d.\n", ret); 2452 return ret; 2453 } 2454 2455 apply_func_caps(hr_dev); 2456 2457 ret = hns_roce_alloc_vf_resource(hr_dev); 2458 if (ret) { 2459 dev_err(dev, "failed to alloc vf resource, ret = %d.\n", ret); 2460 return ret; 2461 } 2462 2463 ret = hns_roce_v2_set_bt(hr_dev); 2464 if (ret) { 2465 dev_err(dev, "failed to config BA table, ret = %d.\n", ret); 2466 return ret; 2467 } 2468 2469 /* Configure the size of QPC, SCCC, etc. */ 2470 return hns_roce_config_entry_size(hr_dev); 2471 } 2472 2473 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2474 { 2475 struct device *dev = hr_dev->dev; 2476 int ret; 2477 2478 ret = hns_roce_cmq_query_hw_info(hr_dev); 2479 if (ret) { 2480 dev_err(dev, "failed to query hardware info, ret = %d.\n", ret); 2481 return ret; 2482 } 2483 2484 ret = hns_roce_query_fw_ver(hr_dev); 2485 if (ret) { 2486 dev_err(dev, "failed to query firmware info, ret = %d.\n", ret); 2487 return ret; 2488 } 2489 2490 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2491 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2492 2493 if (hr_dev->is_vf) 2494 return hns_roce_v2_vf_profile(hr_dev); 2495 else 2496 return hns_roce_v2_pf_profile(hr_dev); 2497 } 2498 2499 static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) 2500 { 2501 u32 i, next_ptr, page_num; 2502 __le64 *entry = cfg_buf; 2503 dma_addr_t addr; 2504 u64 val; 2505 2506 page_num = data_buf->npages; 2507 for (i = 0; i < page_num; i++) { 2508 addr = hns_roce_buf_page(data_buf, i); 2509 if (i == (page_num - 1)) 2510 next_ptr = 0; 2511 else 2512 next_ptr = i + 1; 2513 2514 val = HNS_ROCE_EXT_LLM_ENTRY(addr, (u64)next_ptr); 2515 entry[i] = cpu_to_le64(val); 2516 } 2517 } 2518 2519 static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 2520 struct hns_roce_link_table *table) 2521 { 2522 struct hns_roce_cmq_desc desc[2]; 2523 struct hns_roce_cmq_req *r_a = (struct hns_roce_cmq_req *)desc[0].data; 2524 struct hns_roce_cmq_req *r_b = (struct hns_roce_cmq_req *)desc[1].data; 2525 struct hns_roce_buf *buf = table->buf; 2526 enum hns_roce_opcode_type opcode; 2527 dma_addr_t addr; 2528 2529 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2530 hns_roce_cmq_setup_basic_desc(&desc[0], opcode, false); 2531 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2532 hns_roce_cmq_setup_basic_desc(&desc[1], opcode, false); 2533 2534 hr_reg_write(r_a, CFG_LLM_A_BA_L, lower_32_bits(table->table.map)); 2535 hr_reg_write(r_a, CFG_LLM_A_BA_H, upper_32_bits(table->table.map)); 2536 hr_reg_write(r_a, CFG_LLM_A_DEPTH, buf->npages); 2537 hr_reg_write(r_a, CFG_LLM_A_PGSZ, to_hr_hw_page_shift(buf->page_shift)); 2538 hr_reg_enable(r_a, CFG_LLM_A_INIT_EN); 2539 2540 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, 0)); 2541 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_L, lower_32_bits(addr)); 2542 hr_reg_write(r_a, CFG_LLM_A_HEAD_BA_H, upper_32_bits(addr)); 2543 hr_reg_write(r_a, CFG_LLM_A_HEAD_NXTPTR, 1); 2544 hr_reg_write(r_a, CFG_LLM_A_HEAD_PTR, 0); 2545 2546 addr = to_hr_hw_page_addr(hns_roce_buf_page(buf, buf->npages - 1)); 2547 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_L, lower_32_bits(addr)); 2548 hr_reg_write(r_b, CFG_LLM_B_TAIL_BA_H, upper_32_bits(addr)); 2549 hr_reg_write(r_b, CFG_LLM_B_TAIL_PTR, buf->npages - 1); 2550 2551 return hns_roce_cmq_send(hr_dev, desc, 2); 2552 } 2553 2554 static struct hns_roce_link_table * 2555 alloc_link_table_buf(struct hns_roce_dev *hr_dev) 2556 { 2557 struct hns_roce_v2_priv *priv = hr_dev->priv; 2558 struct hns_roce_link_table *link_tbl; 2559 u32 pg_shift, size, min_size; 2560 2561 link_tbl = &priv->ext_llm; 2562 pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT; 2563 size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ; 2564 min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift; 2565 2566 /* Alloc data table */ 2567 size = max(size, min_size); 2568 link_tbl->buf = hns_roce_buf_alloc(hr_dev, size, pg_shift, 0); 2569 if (IS_ERR(link_tbl->buf)) 2570 return ERR_PTR(-ENOMEM); 2571 2572 /* Alloc config table */ 2573 size = link_tbl->buf->npages * sizeof(u64); 2574 link_tbl->table.buf = dma_alloc_coherent(hr_dev->dev, size, 2575 &link_tbl->table.map, 2576 GFP_KERNEL); 2577 if (!link_tbl->table.buf) { 2578 hns_roce_buf_free(hr_dev, link_tbl->buf); 2579 return ERR_PTR(-ENOMEM); 2580 } 2581 2582 return link_tbl; 2583 } 2584 2585 static void free_link_table_buf(struct hns_roce_dev *hr_dev, 2586 struct hns_roce_link_table *tbl) 2587 { 2588 if (tbl->buf) { 2589 u32 size = tbl->buf->npages * sizeof(u64); 2590 2591 dma_free_coherent(hr_dev->dev, size, tbl->table.buf, 2592 tbl->table.map); 2593 } 2594 2595 hns_roce_buf_free(hr_dev, tbl->buf); 2596 } 2597 2598 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) 2599 { 2600 struct hns_roce_link_table *link_tbl; 2601 int ret; 2602 2603 link_tbl = alloc_link_table_buf(hr_dev); 2604 if (IS_ERR(link_tbl)) 2605 return -ENOMEM; 2606 2607 if (WARN_ON(link_tbl->buf->npages > HNS_ROCE_V2_EXT_LLM_MAX_DEPTH)) { 2608 ret = -EINVAL; 2609 goto err_alloc; 2610 } 2611 2612 config_llm_table(link_tbl->buf, link_tbl->table.buf); 2613 ret = set_llm_cfg_to_hw(hr_dev, link_tbl); 2614 if (ret) 2615 goto err_alloc; 2616 2617 return 0; 2618 2619 err_alloc: 2620 free_link_table_buf(hr_dev, link_tbl); 2621 return ret; 2622 } 2623 2624 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) 2625 { 2626 struct hns_roce_v2_priv *priv = hr_dev->priv; 2627 2628 free_link_table_buf(hr_dev, &priv->ext_llm); 2629 } 2630 2631 static void free_dip_list(struct hns_roce_dev *hr_dev) 2632 { 2633 struct hns_roce_dip *hr_dip; 2634 struct hns_roce_dip *tmp; 2635 unsigned long flags; 2636 2637 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 2638 2639 list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) { 2640 list_del(&hr_dip->node); 2641 kfree(hr_dip); 2642 } 2643 2644 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 2645 } 2646 2647 static int get_hem_table(struct hns_roce_dev *hr_dev) 2648 { 2649 unsigned int qpc_count; 2650 unsigned int cqc_count; 2651 unsigned int gmv_count; 2652 int ret; 2653 int i; 2654 2655 /* Alloc memory for source address table buffer space chunk */ 2656 for (gmv_count = 0; gmv_count < hr_dev->caps.gmv_entry_num; 2657 gmv_count++) { 2658 ret = hns_roce_table_get(hr_dev, &hr_dev->gmv_table, gmv_count); 2659 if (ret) 2660 goto err_gmv_failed; 2661 } 2662 2663 if (hr_dev->is_vf) 2664 return 0; 2665 2666 /* Alloc memory for QPC Timer buffer space chunk */ 2667 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2668 qpc_count++) { 2669 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2670 qpc_count); 2671 if (ret) { 2672 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2673 goto err_qpc_timer_failed; 2674 } 2675 } 2676 2677 /* Alloc memory for CQC Timer buffer space chunk */ 2678 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2679 cqc_count++) { 2680 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2681 cqc_count); 2682 if (ret) { 2683 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2684 goto err_cqc_timer_failed; 2685 } 2686 } 2687 2688 return 0; 2689 2690 err_cqc_timer_failed: 2691 for (i = 0; i < cqc_count; i++) 2692 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2693 2694 err_qpc_timer_failed: 2695 for (i = 0; i < qpc_count; i++) 2696 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2697 2698 err_gmv_failed: 2699 for (i = 0; i < gmv_count; i++) 2700 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2701 2702 return ret; 2703 } 2704 2705 static void put_hem_table(struct hns_roce_dev *hr_dev) 2706 { 2707 int i; 2708 2709 for (i = 0; i < hr_dev->caps.gmv_entry_num; i++) 2710 hns_roce_table_put(hr_dev, &hr_dev->gmv_table, i); 2711 2712 if (hr_dev->is_vf) 2713 return; 2714 2715 for (i = 0; i < hr_dev->caps.qpc_timer_bt_num; i++) 2716 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2717 2718 for (i = 0; i < hr_dev->caps.cqc_timer_bt_num; i++) 2719 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2720 } 2721 2722 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2723 { 2724 int ret; 2725 2726 /* The hns ROCEE requires the extdb info to be cleared before using */ 2727 ret = hns_roce_clear_extdb_list_info(hr_dev); 2728 if (ret) 2729 return ret; 2730 2731 ret = get_hem_table(hr_dev); 2732 if (ret) 2733 return ret; 2734 2735 if (hr_dev->is_vf) 2736 return 0; 2737 2738 ret = hns_roce_init_link_table(hr_dev); 2739 if (ret) { 2740 dev_err(hr_dev->dev, "failed to init llm, ret = %d.\n", ret); 2741 goto err_llm_init_failed; 2742 } 2743 2744 return 0; 2745 2746 err_llm_init_failed: 2747 put_hem_table(hr_dev); 2748 2749 return ret; 2750 } 2751 2752 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2753 { 2754 hns_roce_function_clear(hr_dev); 2755 2756 if (!hr_dev->is_vf) 2757 hns_roce_free_link_table(hr_dev); 2758 2759 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09) 2760 free_dip_list(hr_dev); 2761 } 2762 2763 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2764 u64 out_param, u32 in_modifier, u8 op_modifier, 2765 u16 op, u16 token, int event) 2766 { 2767 struct hns_roce_cmq_desc desc; 2768 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2769 2770 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2771 2772 mb->in_param_l = cpu_to_le32(in_param); 2773 mb->in_param_h = cpu_to_le32(in_param >> 32); 2774 mb->out_param_l = cpu_to_le32(out_param); 2775 mb->out_param_h = cpu_to_le32(out_param >> 32); 2776 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2777 mb->token_event_en = cpu_to_le32(event << 16 | token); 2778 2779 return hns_roce_cmq_send(hr_dev, &desc, 1); 2780 } 2781 2782 static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, 2783 u8 *complete_status) 2784 { 2785 struct hns_roce_mbox_status *mb_st; 2786 struct hns_roce_cmq_desc desc; 2787 unsigned long end; 2788 int ret = -EBUSY; 2789 u32 status; 2790 bool busy; 2791 2792 mb_st = (struct hns_roce_mbox_status *)desc.data; 2793 end = msecs_to_jiffies(timeout) + jiffies; 2794 while (v2_chk_mbox_is_avail(hr_dev, &busy)) { 2795 status = 0; 2796 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, 2797 true); 2798 ret = __hns_roce_cmq_send(hr_dev, &desc, 1); 2799 if (!ret) { 2800 status = le32_to_cpu(mb_st->mb_status_hw_run); 2801 /* No pending message exists in ROCEE mbox. */ 2802 if (!(status & MB_ST_HW_RUN_M)) 2803 break; 2804 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2805 break; 2806 } 2807 2808 if (time_after(jiffies, end)) { 2809 dev_err_ratelimited(hr_dev->dev, 2810 "failed to wait mbox status 0x%x\n", 2811 status); 2812 return -ETIMEDOUT; 2813 } 2814 2815 cond_resched(); 2816 ret = -EBUSY; 2817 } 2818 2819 if (!ret) { 2820 *complete_status = (u8)(status & MB_ST_COMPLETE_M); 2821 } else if (!v2_chk_mbox_is_avail(hr_dev, &busy)) { 2822 /* Ignore all errors if the mbox is unavailable. */ 2823 ret = 0; 2824 *complete_status = MB_ST_COMPLETE_M; 2825 } 2826 2827 return ret; 2828 } 2829 2830 static int v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2831 u64 out_param, u32 in_modifier, u8 op_modifier, 2832 u16 op, u16 token, int event) 2833 { 2834 u8 status = 0; 2835 int ret; 2836 2837 /* Waiting for the mbox to be idle */ 2838 ret = v2_wait_mbox_complete(hr_dev, HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS, 2839 &status); 2840 if (unlikely(ret)) { 2841 dev_err_ratelimited(hr_dev->dev, 2842 "failed to check post mbox status = 0x%x, ret = %d.\n", 2843 status, ret); 2844 return ret; 2845 } 2846 2847 /* Post new message to mbox */ 2848 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2849 op_modifier, op, token, event); 2850 if (ret) 2851 dev_err_ratelimited(hr_dev->dev, 2852 "failed to post mailbox, ret = %d.\n", ret); 2853 2854 return ret; 2855 } 2856 2857 static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev, unsigned int timeout) 2858 { 2859 u8 status = 0; 2860 int ret; 2861 2862 ret = v2_wait_mbox_complete(hr_dev, timeout, &status); 2863 if (!ret) { 2864 if (status != MB_ST_COMPLETE_SUCC) 2865 return -EBUSY; 2866 } else { 2867 dev_err_ratelimited(hr_dev->dev, 2868 "failed to check mbox status = 0x%x, ret = %d.\n", 2869 status, ret); 2870 } 2871 2872 return ret; 2873 } 2874 2875 static void copy_gid(void *dest, const union ib_gid *gid) 2876 { 2877 #define GID_SIZE 4 2878 const union ib_gid *src = gid; 2879 __le32 (*p)[GID_SIZE] = dest; 2880 int i; 2881 2882 if (!gid) 2883 src = &zgid; 2884 2885 for (i = 0; i < GID_SIZE; i++) 2886 (*p)[i] = cpu_to_le32(*(u32 *)&src->raw[i * sizeof(u32)]); 2887 } 2888 2889 static int config_sgid_table(struct hns_roce_dev *hr_dev, 2890 int gid_index, const union ib_gid *gid, 2891 enum hns_roce_sgid_type sgid_type) 2892 { 2893 struct hns_roce_cmq_desc desc; 2894 struct hns_roce_cfg_sgid_tb *sgid_tb = 2895 (struct hns_roce_cfg_sgid_tb *)desc.data; 2896 2897 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2898 2899 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2900 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2901 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2902 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2903 2904 copy_gid(&sgid_tb->vf_sgid_l, gid); 2905 2906 return hns_roce_cmq_send(hr_dev, &desc, 1); 2907 } 2908 2909 static int config_gmv_table(struct hns_roce_dev *hr_dev, 2910 int gid_index, const union ib_gid *gid, 2911 enum hns_roce_sgid_type sgid_type, 2912 const struct ib_gid_attr *attr) 2913 { 2914 struct hns_roce_cmq_desc desc[2]; 2915 struct hns_roce_cfg_gmv_tb_a *tb_a = 2916 (struct hns_roce_cfg_gmv_tb_a *)desc[0].data; 2917 struct hns_roce_cfg_gmv_tb_b *tb_b = 2918 (struct hns_roce_cfg_gmv_tb_b *)desc[1].data; 2919 2920 u16 vlan_id = VLAN_CFI_MASK; 2921 u8 mac[ETH_ALEN] = {}; 2922 int ret; 2923 2924 if (gid) { 2925 ret = rdma_read_gid_l2_fields(attr, &vlan_id, mac); 2926 if (ret) 2927 return ret; 2928 } 2929 2930 hns_roce_cmq_setup_basic_desc(&desc[0], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2931 desc[0].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2932 2933 hns_roce_cmq_setup_basic_desc(&desc[1], HNS_ROCE_OPC_CFG_GMV_TBL, false); 2934 2935 copy_gid(&tb_a->vf_sgid_l, gid); 2936 2937 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_SGID_TYPE_M, 2938 CFG_GMV_TB_VF_SGID_TYPE_S, sgid_type); 2939 roce_set_bit(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_EN_S, 2940 vlan_id < VLAN_CFI_MASK); 2941 roce_set_field(tb_a->vf_sgid_type_vlan, CFG_GMV_TB_VF_VLAN_ID_M, 2942 CFG_GMV_TB_VF_VLAN_ID_S, vlan_id); 2943 2944 tb_b->vf_smac_l = cpu_to_le32(*(u32 *)mac); 2945 roce_set_field(tb_b->vf_smac_h, CFG_GMV_TB_SMAC_H_M, 2946 CFG_GMV_TB_SMAC_H_S, *(u16 *)&mac[4]); 2947 2948 roce_set_field(tb_b->table_idx_rsv, CFG_GMV_TB_SGID_IDX_M, 2949 CFG_GMV_TB_SGID_IDX_S, gid_index); 2950 2951 return hns_roce_cmq_send(hr_dev, desc, 2); 2952 } 2953 2954 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u32 port, 2955 int gid_index, const union ib_gid *gid, 2956 const struct ib_gid_attr *attr) 2957 { 2958 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2959 int ret; 2960 2961 if (gid) { 2962 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2963 if (ipv6_addr_v4mapped((void *)gid)) 2964 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2965 else 2966 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2967 } else if (attr->gid_type == IB_GID_TYPE_ROCE) { 2968 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2969 } 2970 } 2971 2972 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 2973 ret = config_gmv_table(hr_dev, gid_index, gid, sgid_type, attr); 2974 else 2975 ret = config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2976 2977 if (ret) 2978 ibdev_err(&hr_dev->ib_dev, "failed to set gid, ret = %d!\n", 2979 ret); 2980 2981 return ret; 2982 } 2983 2984 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2985 const u8 *addr) 2986 { 2987 struct hns_roce_cmq_desc desc; 2988 struct hns_roce_cfg_smac_tb *smac_tb = 2989 (struct hns_roce_cfg_smac_tb *)desc.data; 2990 u16 reg_smac_h; 2991 u32 reg_smac_l; 2992 2993 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 2994 2995 reg_smac_l = *(u32 *)(&addr[0]); 2996 reg_smac_h = *(u16 *)(&addr[4]); 2997 2998 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 2999 CFG_SMAC_TB_IDX_S, phy_port); 3000 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 3001 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 3002 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 3003 3004 return hns_roce_cmq_send(hr_dev, &desc, 1); 3005 } 3006 3007 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 3008 struct hns_roce_v2_mpt_entry *mpt_entry, 3009 struct hns_roce_mr *mr) 3010 { 3011 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 3012 struct ib_device *ibdev = &hr_dev->ib_dev; 3013 dma_addr_t pbl_ba; 3014 int i, count; 3015 3016 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 3017 ARRAY_SIZE(pages), &pbl_ba); 3018 if (count < 1) { 3019 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 3020 count); 3021 return -ENOBUFS; 3022 } 3023 3024 /* Aligned to the hardware address access unit */ 3025 for (i = 0; i < count; i++) 3026 pages[i] >>= 6; 3027 3028 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3029 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 3030 roce_set_field(mpt_entry->byte_48_mode_ba, 3031 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 3032 upper_32_bits(pbl_ba >> 3)); 3033 3034 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 3035 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 3036 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 3037 3038 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 3039 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 3040 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 3041 roce_set_field(mpt_entry->byte_64_buf_pa1, 3042 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3043 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3044 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3045 3046 return 0; 3047 } 3048 3049 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 3050 void *mb_buf, struct hns_roce_mr *mr, 3051 unsigned long mtpt_idx) 3052 { 3053 struct hns_roce_v2_mpt_entry *mpt_entry; 3054 int ret; 3055 3056 mpt_entry = mb_buf; 3057 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3058 3059 hr_reg_write(mpt_entry, MPT_ST, V2_MPT_ST_VALID); 3060 hr_reg_write(mpt_entry, MPT_PD, mr->pd); 3061 hr_reg_enable(mpt_entry, MPT_L_INV_EN); 3062 3063 hr_reg_write_bool(mpt_entry, MPT_BIND_EN, 3064 mr->access & IB_ACCESS_MW_BIND); 3065 hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, 3066 mr->access & IB_ACCESS_REMOTE_ATOMIC); 3067 hr_reg_write_bool(mpt_entry, MPT_RR_EN, 3068 mr->access & IB_ACCESS_REMOTE_READ); 3069 hr_reg_write_bool(mpt_entry, MPT_RW_EN, 3070 mr->access & IB_ACCESS_REMOTE_WRITE); 3071 hr_reg_write_bool(mpt_entry, MPT_LW_EN, 3072 mr->access & IB_ACCESS_LOCAL_WRITE); 3073 3074 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3075 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3076 mpt_entry->lkey = cpu_to_le32(mr->key); 3077 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3078 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3079 3080 if (mr->type != MR_TYPE_MR) 3081 hr_reg_enable(mpt_entry, MPT_PA); 3082 3083 if (mr->type == MR_TYPE_DMA) 3084 return 0; 3085 3086 if (mr->pbl_hop_num != HNS_ROCE_HOP_NUM_0) 3087 hr_reg_write(mpt_entry, MPT_PBL_HOP_NUM, mr->pbl_hop_num); 3088 3089 hr_reg_write(mpt_entry, MPT_PBL_BA_PG_SZ, 3090 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3091 hr_reg_enable(mpt_entry, MPT_INNER_PA_VLD); 3092 3093 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3094 3095 return ret; 3096 } 3097 3098 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 3099 struct hns_roce_mr *mr, int flags, 3100 void *mb_buf) 3101 { 3102 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 3103 u32 mr_access_flags = mr->access; 3104 int ret = 0; 3105 3106 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3107 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 3108 3109 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3110 V2_MPT_BYTE_4_PD_S, mr->pd); 3111 3112 if (flags & IB_MR_REREG_ACCESS) { 3113 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3114 V2_MPT_BYTE_8_BIND_EN_S, 3115 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 3116 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 3117 V2_MPT_BYTE_8_ATOMIC_EN_S, 3118 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 3119 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 3120 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 3121 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 3122 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 3123 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 3124 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 3125 } 3126 3127 if (flags & IB_MR_REREG_TRANS) { 3128 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 3129 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 3130 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 3131 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 3132 3133 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 3134 } 3135 3136 return ret; 3137 } 3138 3139 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 3140 void *mb_buf, struct hns_roce_mr *mr) 3141 { 3142 struct ib_device *ibdev = &hr_dev->ib_dev; 3143 struct hns_roce_v2_mpt_entry *mpt_entry; 3144 dma_addr_t pbl_ba = 0; 3145 3146 mpt_entry = mb_buf; 3147 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3148 3149 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 3150 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 3151 return -ENOBUFS; 3152 } 3153 3154 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3155 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3156 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3157 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 3158 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3159 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3160 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3161 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 3162 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3163 V2_MPT_BYTE_4_PD_S, mr->pd); 3164 3165 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 3166 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3167 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3168 3169 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 3170 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3171 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 3172 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3173 3174 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 3175 3176 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 3177 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 3178 V2_MPT_BYTE_48_PBL_BA_H_S, 3179 upper_32_bits(pbl_ba >> 3)); 3180 3181 roce_set_field(mpt_entry->byte_64_buf_pa1, 3182 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3183 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3184 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 3185 3186 return 0; 3187 } 3188 3189 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 3190 { 3191 struct hns_roce_v2_mpt_entry *mpt_entry; 3192 3193 mpt_entry = mb_buf; 3194 memset(mpt_entry, 0, sizeof(*mpt_entry)); 3195 3196 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 3197 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 3198 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 3199 V2_MPT_BYTE_4_PD_S, mw->pdn); 3200 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 3201 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 3202 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 3203 mw->pbl_hop_num); 3204 roce_set_field(mpt_entry->byte_4_pd_hop_st, 3205 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 3206 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 3207 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 3208 3209 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 3210 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 3211 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 1); 3212 3213 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 3214 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 3215 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 3216 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 3217 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 3218 3219 roce_set_field(mpt_entry->byte_64_buf_pa1, 3220 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 3221 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 3222 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 3223 3224 mpt_entry->lkey = cpu_to_le32(mw->rkey); 3225 3226 return 0; 3227 } 3228 3229 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 3230 { 3231 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size); 3232 } 3233 3234 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) 3235 { 3236 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 3237 3238 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 3239 return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe : 3240 NULL; 3241 } 3242 3243 static inline void update_cq_db(struct hns_roce_dev *hr_dev, 3244 struct hns_roce_cq *hr_cq) 3245 { 3246 if (likely(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB)) { 3247 *hr_cq->set_ci_db = hr_cq->cons_index & V2_CQ_DB_CONS_IDX_M; 3248 } else { 3249 struct hns_roce_v2_db cq_db = {}; 3250 3251 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3252 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB); 3253 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3254 hr_reg_write(&cq_db, DB_CQ_CMD_SN, 1); 3255 3256 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3257 } 3258 } 3259 3260 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3261 struct hns_roce_srq *srq) 3262 { 3263 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3264 struct hns_roce_v2_cqe *cqe, *dest; 3265 u32 prod_index; 3266 int nfreed = 0; 3267 int wqe_index; 3268 u8 owner_bit; 3269 3270 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 3271 ++prod_index) { 3272 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 3273 break; 3274 } 3275 3276 /* 3277 * Now backwards through the CQ, removing CQ entries 3278 * that match our QP by overwriting them with next entries. 3279 */ 3280 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 3281 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 3282 if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) { 3283 if (srq && hr_reg_read(cqe, CQE_S_R)) { 3284 wqe_index = hr_reg_read(cqe, CQE_WQE_IDX); 3285 hns_roce_free_srq_wqe(srq, wqe_index); 3286 } 3287 ++nfreed; 3288 } else if (nfreed) { 3289 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 3290 hr_cq->ib_cq.cqe); 3291 owner_bit = hr_reg_read(dest, CQE_OWNER); 3292 memcpy(dest, cqe, hr_cq->cqe_size); 3293 hr_reg_write(dest, CQE_OWNER, owner_bit); 3294 } 3295 } 3296 3297 if (nfreed) { 3298 hr_cq->cons_index += nfreed; 3299 update_cq_db(hr_dev, hr_cq); 3300 } 3301 } 3302 3303 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 3304 struct hns_roce_srq *srq) 3305 { 3306 spin_lock_irq(&hr_cq->lock); 3307 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 3308 spin_unlock_irq(&hr_cq->lock); 3309 } 3310 3311 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 3312 struct hns_roce_cq *hr_cq, void *mb_buf, 3313 u64 *mtts, dma_addr_t dma_handle) 3314 { 3315 struct hns_roce_v2_cq_context *cq_context; 3316 3317 cq_context = mb_buf; 3318 memset(cq_context, 0, sizeof(*cq_context)); 3319 3320 hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID); 3321 hr_reg_write(cq_context, CQC_ARM_ST, NO_ARMED); 3322 hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth)); 3323 hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector); 3324 hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn); 3325 3326 if (hr_cq->cqe_size == HNS_ROCE_V3_CQE_SIZE) 3327 hr_reg_write(cq_context, CQC_CQE_SIZE, CQE_SIZE_64B); 3328 3329 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 3330 hr_reg_enable(cq_context, CQC_STASH); 3331 3332 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_L, 3333 to_hr_hw_page_addr(mtts[0])); 3334 hr_reg_write(cq_context, CQC_CQE_CUR_BLK_ADDR_H, 3335 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3336 hr_reg_write(cq_context, CQC_CQE_HOP_NUM, hr_dev->caps.cqe_hop_num == 3337 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 3338 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_L, 3339 to_hr_hw_page_addr(mtts[1])); 3340 hr_reg_write(cq_context, CQC_CQE_NEX_BLK_ADDR_H, 3341 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3342 hr_reg_write(cq_context, CQC_CQE_BAR_PG_SZ, 3343 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 3344 hr_reg_write(cq_context, CQC_CQE_BUF_PG_SZ, 3345 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 3346 hr_reg_write(cq_context, CQC_CQE_BA_L, dma_handle >> 3); 3347 hr_reg_write(cq_context, CQC_CQE_BA_H, (dma_handle >> (32 + 3))); 3348 hr_reg_write_bool(cq_context, CQC_DB_RECORD_EN, 3349 hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB); 3350 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_L, 3351 ((u32)hr_cq->db.dma) >> 1); 3352 hr_reg_write(cq_context, CQC_CQE_DB_RECORD_ADDR_H, 3353 hr_cq->db.dma >> 32); 3354 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, 3355 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 3356 hr_reg_write(cq_context, CQC_CQ_PERIOD, 3357 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 3358 } 3359 3360 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 3361 enum ib_cq_notify_flags flags) 3362 { 3363 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3364 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3365 struct hns_roce_v2_db cq_db = {}; 3366 u32 notify_flag; 3367 3368 /* 3369 * flags = 0, then notify_flag : next 3370 * flags = 1, then notify flag : solocited 3371 */ 3372 notify_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 3373 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 3374 3375 hr_reg_write(&cq_db, DB_TAG, hr_cq->cqn); 3376 hr_reg_write(&cq_db, DB_CMD, HNS_ROCE_V2_CQ_DB_NOTIFY); 3377 hr_reg_write(&cq_db, DB_CQ_CI, hr_cq->cons_index); 3378 hr_reg_write(&cq_db, DB_CQ_CMD_SN, hr_cq->arm_sn); 3379 hr_reg_write(&cq_db, DB_CQ_NOTIFY, notify_flag); 3380 3381 hns_roce_write64(hr_dev, (__le32 *)&cq_db, hr_cq->db_reg); 3382 3383 return 0; 3384 } 3385 3386 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 3387 struct hns_roce_qp *qp, 3388 struct ib_wc *wc) 3389 { 3390 struct hns_roce_rinl_sge *sge_list; 3391 u32 wr_num, wr_cnt, sge_num; 3392 u32 sge_cnt, data_len, size; 3393 void *wqe_buf; 3394 3395 wr_num = hr_reg_read(cqe, CQE_WQE_IDX); 3396 wr_cnt = wr_num & (qp->rq.wqe_cnt - 1); 3397 3398 sge_list = qp->rq_inl_buf.wqe_list[wr_cnt].sg_list; 3399 sge_num = qp->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 3400 wqe_buf = hns_roce_get_recv_wqe(qp, wr_cnt); 3401 data_len = wc->byte_len; 3402 3403 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 3404 size = min(sge_list[sge_cnt].len, data_len); 3405 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 3406 3407 data_len -= size; 3408 wqe_buf += size; 3409 } 3410 3411 if (unlikely(data_len)) { 3412 wc->status = IB_WC_LOC_LEN_ERR; 3413 return -EAGAIN; 3414 } 3415 3416 return 0; 3417 } 3418 3419 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 3420 int num_entries, struct ib_wc *wc) 3421 { 3422 unsigned int left; 3423 int npolled = 0; 3424 3425 left = wq->head - wq->tail; 3426 if (left == 0) 3427 return 0; 3428 3429 left = min_t(unsigned int, (unsigned int)num_entries, left); 3430 while (npolled < left) { 3431 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3432 wc->status = IB_WC_WR_FLUSH_ERR; 3433 wc->vendor_err = 0; 3434 wc->qp = &hr_qp->ibqp; 3435 3436 wq->tail++; 3437 wc++; 3438 npolled++; 3439 } 3440 3441 return npolled; 3442 } 3443 3444 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3445 struct ib_wc *wc) 3446 { 3447 struct hns_roce_qp *hr_qp; 3448 int npolled = 0; 3449 3450 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3451 npolled += sw_comp(hr_qp, &hr_qp->sq, 3452 num_entries - npolled, wc + npolled); 3453 if (npolled >= num_entries) 3454 goto out; 3455 } 3456 3457 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3458 npolled += sw_comp(hr_qp, &hr_qp->rq, 3459 num_entries - npolled, wc + npolled); 3460 if (npolled >= num_entries) 3461 goto out; 3462 } 3463 3464 out: 3465 return npolled; 3466 } 3467 3468 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3469 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, 3470 struct ib_wc *wc) 3471 { 3472 static const struct { 3473 u32 cqe_status; 3474 enum ib_wc_status wc_status; 3475 } map[] = { 3476 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3477 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3478 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3479 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3480 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3481 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3482 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3483 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3484 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3485 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3486 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3487 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3488 IB_WC_RETRY_EXC_ERR }, 3489 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3490 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3491 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3492 }; 3493 3494 u32 cqe_status = hr_reg_read(cqe, CQE_STATUS); 3495 int i; 3496 3497 wc->status = IB_WC_GENERAL_ERR; 3498 for (i = 0; i < ARRAY_SIZE(map); i++) 3499 if (cqe_status == map[i].cqe_status) { 3500 wc->status = map[i].wc_status; 3501 break; 3502 } 3503 3504 if (likely(wc->status == IB_WC_SUCCESS || 3505 wc->status == IB_WC_WR_FLUSH_ERR)) 3506 return; 3507 3508 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3509 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3510 cq->cqe_size, false); 3511 wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS); 3512 3513 /* 3514 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3515 * the standard protocol, the driver must ignore it and needn't to set 3516 * the QP to an error state. 3517 */ 3518 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3519 return; 3520 3521 flush_cqe(hr_dev, qp); 3522 } 3523 3524 static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, 3525 struct hns_roce_qp **cur_qp) 3526 { 3527 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3528 struct hns_roce_qp *hr_qp = *cur_qp; 3529 u32 qpn; 3530 3531 qpn = hr_reg_read(cqe, CQE_LCL_QPN); 3532 3533 if (!hr_qp || qpn != hr_qp->qpn) { 3534 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3535 if (unlikely(!hr_qp)) { 3536 ibdev_err(&hr_dev->ib_dev, 3537 "CQ %06lx with entry for unknown QPN %06x\n", 3538 hr_cq->cqn, qpn); 3539 return -EINVAL; 3540 } 3541 *cur_qp = hr_qp; 3542 } 3543 3544 return 0; 3545 } 3546 3547 /* 3548 * mapped-value = 1 + real-value 3549 * The ib wc opcode's real value is start from 0, In order to distinguish 3550 * between initialized and uninitialized map values, we plus 1 to the actual 3551 * value when defining the mapping, so that the validity can be identified by 3552 * checking whether the mapped value is greater than 0. 3553 */ 3554 #define HR_WC_OP_MAP(hr_key, ib_key) \ 3555 [HNS_ROCE_V2_WQE_OP_ ## hr_key] = 1 + IB_WC_ ## ib_key 3556 3557 static const u32 wc_send_op_map[] = { 3558 HR_WC_OP_MAP(SEND, SEND), 3559 HR_WC_OP_MAP(SEND_WITH_INV, SEND), 3560 HR_WC_OP_MAP(SEND_WITH_IMM, SEND), 3561 HR_WC_OP_MAP(RDMA_READ, RDMA_READ), 3562 HR_WC_OP_MAP(RDMA_WRITE, RDMA_WRITE), 3563 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE), 3564 HR_WC_OP_MAP(LOCAL_INV, LOCAL_INV), 3565 HR_WC_OP_MAP(ATOM_CMP_AND_SWAP, COMP_SWAP), 3566 HR_WC_OP_MAP(ATOM_FETCH_AND_ADD, FETCH_ADD), 3567 HR_WC_OP_MAP(ATOM_MSK_CMP_AND_SWAP, MASKED_COMP_SWAP), 3568 HR_WC_OP_MAP(ATOM_MSK_FETCH_AND_ADD, MASKED_FETCH_ADD), 3569 HR_WC_OP_MAP(FAST_REG_PMR, REG_MR), 3570 HR_WC_OP_MAP(BIND_MW, REG_MR), 3571 }; 3572 3573 static int to_ib_wc_send_op(u32 hr_opcode) 3574 { 3575 if (hr_opcode >= ARRAY_SIZE(wc_send_op_map)) 3576 return -EINVAL; 3577 3578 return wc_send_op_map[hr_opcode] ? wc_send_op_map[hr_opcode] - 1 : 3579 -EINVAL; 3580 } 3581 3582 static const u32 wc_recv_op_map[] = { 3583 HR_WC_OP_MAP(RDMA_WRITE_WITH_IMM, WITH_IMM), 3584 HR_WC_OP_MAP(SEND, RECV), 3585 HR_WC_OP_MAP(SEND_WITH_IMM, WITH_IMM), 3586 HR_WC_OP_MAP(SEND_WITH_INV, RECV), 3587 }; 3588 3589 static int to_ib_wc_recv_op(u32 hr_opcode) 3590 { 3591 if (hr_opcode >= ARRAY_SIZE(wc_recv_op_map)) 3592 return -EINVAL; 3593 3594 return wc_recv_op_map[hr_opcode] ? wc_recv_op_map[hr_opcode] - 1 : 3595 -EINVAL; 3596 } 3597 3598 static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3599 { 3600 u32 hr_opcode; 3601 int ib_opcode; 3602 3603 wc->wc_flags = 0; 3604 3605 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3606 switch (hr_opcode) { 3607 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3608 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3609 break; 3610 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3611 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3612 wc->wc_flags |= IB_WC_WITH_IMM; 3613 break; 3614 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3615 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3616 break; 3617 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3618 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3619 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3620 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3621 wc->byte_len = 8; 3622 break; 3623 default: 3624 break; 3625 } 3626 3627 ib_opcode = to_ib_wc_send_op(hr_opcode); 3628 if (ib_opcode < 0) 3629 wc->status = IB_WC_GENERAL_ERR; 3630 else 3631 wc->opcode = ib_opcode; 3632 } 3633 3634 static inline bool is_rq_inl_enabled(struct ib_wc *wc, u32 hr_opcode, 3635 struct hns_roce_v2_cqe *cqe) 3636 { 3637 return wc->qp->qp_type != IB_QPT_UD && wc->qp->qp_type != IB_QPT_GSI && 3638 (hr_opcode == HNS_ROCE_V2_OPCODE_SEND || 3639 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3640 hr_opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3641 hr_reg_read(cqe, CQE_RQ_INLINE); 3642 } 3643 3644 static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) 3645 { 3646 struct hns_roce_qp *qp = to_hr_qp(wc->qp); 3647 u32 hr_opcode; 3648 int ib_opcode; 3649 int ret; 3650 3651 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3652 3653 hr_opcode = hr_reg_read(cqe, CQE_OPCODE); 3654 switch (hr_opcode) { 3655 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3656 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3657 wc->wc_flags = IB_WC_WITH_IMM; 3658 wc->ex.imm_data = cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3659 break; 3660 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3661 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3662 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3663 break; 3664 default: 3665 wc->wc_flags = 0; 3666 } 3667 3668 ib_opcode = to_ib_wc_recv_op(hr_opcode); 3669 if (ib_opcode < 0) 3670 wc->status = IB_WC_GENERAL_ERR; 3671 else 3672 wc->opcode = ib_opcode; 3673 3674 if (is_rq_inl_enabled(wc, hr_opcode, cqe)) { 3675 ret = hns_roce_handle_recv_inl_wqe(cqe, qp, wc); 3676 if (unlikely(ret)) 3677 return ret; 3678 } 3679 3680 wc->sl = hr_reg_read(cqe, CQE_SL); 3681 wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN); 3682 wc->slid = 0; 3683 wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0; 3684 wc->port_num = hr_reg_read(cqe, CQE_PORTN); 3685 wc->pkey_index = 0; 3686 3687 if (hr_reg_read(cqe, CQE_VID_VLD)) { 3688 wc->vlan_id = hr_reg_read(cqe, CQE_VID); 3689 wc->wc_flags |= IB_WC_WITH_VLAN; 3690 } else { 3691 wc->vlan_id = 0xffff; 3692 } 3693 3694 wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE); 3695 3696 return 0; 3697 } 3698 3699 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3700 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3701 { 3702 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3703 struct hns_roce_qp *qp = *cur_qp; 3704 struct hns_roce_srq *srq = NULL; 3705 struct hns_roce_v2_cqe *cqe; 3706 struct hns_roce_wq *wq; 3707 int is_send; 3708 u16 wqe_idx; 3709 int ret; 3710 3711 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3712 if (!cqe) 3713 return -EAGAIN; 3714 3715 ++hr_cq->cons_index; 3716 /* Memory barrier */ 3717 rmb(); 3718 3719 ret = get_cur_qp(hr_cq, cqe, &qp); 3720 if (ret) 3721 return ret; 3722 3723 wc->qp = &qp->ibqp; 3724 wc->vendor_err = 0; 3725 3726 wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX); 3727 3728 is_send = !hr_reg_read(cqe, CQE_S_R); 3729 if (is_send) { 3730 wq = &qp->sq; 3731 3732 /* If sg_signal_bit is set, tail pointer will be updated to 3733 * the WQE corresponding to the current CQE. 3734 */ 3735 if (qp->sq_signal_bits) 3736 wq->tail += (wqe_idx - (u16)wq->tail) & 3737 (wq->wqe_cnt - 1); 3738 3739 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3740 ++wq->tail; 3741 3742 fill_send_wc(wc, cqe); 3743 } else { 3744 if (qp->ibqp.srq) { 3745 srq = to_hr_srq(qp->ibqp.srq); 3746 wc->wr_id = srq->wrid[wqe_idx]; 3747 hns_roce_free_srq_wqe(srq, wqe_idx); 3748 } else { 3749 wq = &qp->rq; 3750 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3751 ++wq->tail; 3752 } 3753 3754 ret = fill_recv_wc(wc, cqe); 3755 } 3756 3757 get_cqe_status(hr_dev, qp, hr_cq, cqe, wc); 3758 if (unlikely(wc->status != IB_WC_SUCCESS)) 3759 return 0; 3760 3761 return ret; 3762 } 3763 3764 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3765 struct ib_wc *wc) 3766 { 3767 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3768 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3769 struct hns_roce_qp *cur_qp = NULL; 3770 unsigned long flags; 3771 int npolled; 3772 3773 spin_lock_irqsave(&hr_cq->lock, flags); 3774 3775 /* 3776 * When the device starts to reset, the state is RST_DOWN. At this time, 3777 * there may still be some valid CQEs in the hardware that are not 3778 * polled. Therefore, it is not allowed to switch to the software mode 3779 * immediately. When the state changes to UNINIT, CQE no longer exists 3780 * in the hardware, and then switch to software mode. 3781 */ 3782 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3783 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3784 goto out; 3785 } 3786 3787 for (npolled = 0; npolled < num_entries; ++npolled) { 3788 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3789 break; 3790 } 3791 3792 if (npolled) 3793 update_cq_db(hr_dev, hr_cq); 3794 3795 out: 3796 spin_unlock_irqrestore(&hr_cq->lock, flags); 3797 3798 return npolled; 3799 } 3800 3801 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3802 int step_idx, u16 *mbox_op) 3803 { 3804 u16 op; 3805 3806 switch (type) { 3807 case HEM_TYPE_QPC: 3808 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3809 break; 3810 case HEM_TYPE_MTPT: 3811 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3812 break; 3813 case HEM_TYPE_CQC: 3814 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3815 break; 3816 case HEM_TYPE_SRQC: 3817 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3818 break; 3819 case HEM_TYPE_SCCC: 3820 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3821 break; 3822 case HEM_TYPE_QPC_TIMER: 3823 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3824 break; 3825 case HEM_TYPE_CQC_TIMER: 3826 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3827 break; 3828 default: 3829 dev_warn(hr_dev->dev, "failed to check hem type %u.\n", type); 3830 return -EINVAL; 3831 } 3832 3833 *mbox_op = op + step_idx; 3834 3835 return 0; 3836 } 3837 3838 static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, 3839 dma_addr_t base_addr) 3840 { 3841 struct hns_roce_cmq_desc desc; 3842 struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data; 3843 u32 idx = obj / (HNS_HW_PAGE_SIZE / hr_dev->caps.gmv_entry_sz); 3844 u64 addr = to_hr_hw_page_addr(base_addr); 3845 3846 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GMV_BT, false); 3847 3848 hr_reg_write(req, CFG_GMV_BT_BA_L, lower_32_bits(addr)); 3849 hr_reg_write(req, CFG_GMV_BT_BA_H, upper_32_bits(addr)); 3850 hr_reg_write(req, CFG_GMV_BT_IDX, idx); 3851 3852 return hns_roce_cmq_send(hr_dev, &desc, 1); 3853 } 3854 3855 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, 3856 dma_addr_t base_addr, u32 hem_type, int step_idx) 3857 { 3858 int ret; 3859 u16 op; 3860 3861 if (unlikely(hem_type == HEM_TYPE_GMV)) 3862 return config_gmv_ba_to_hw(hr_dev, obj, base_addr); 3863 3864 if (unlikely(hem_type == HEM_TYPE_SCCC && step_idx)) 3865 return 0; 3866 3867 ret = get_op_for_set_hem(hr_dev, hem_type, step_idx, &op); 3868 if (ret < 0) 3869 return ret; 3870 3871 return config_hem_ba_to_hw(hr_dev, obj, base_addr, op); 3872 } 3873 3874 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3875 struct hns_roce_hem_table *table, int obj, 3876 int step_idx) 3877 { 3878 struct hns_roce_hem_iter iter; 3879 struct hns_roce_hem_mhop mhop; 3880 struct hns_roce_hem *hem; 3881 unsigned long mhop_obj = obj; 3882 int i, j, k; 3883 int ret = 0; 3884 u64 hem_idx = 0; 3885 u64 l1_idx = 0; 3886 u64 bt_ba = 0; 3887 u32 chunk_ba_num; 3888 u32 hop_num; 3889 3890 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3891 return 0; 3892 3893 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3894 i = mhop.l0_idx; 3895 j = mhop.l1_idx; 3896 k = mhop.l2_idx; 3897 hop_num = mhop.hop_num; 3898 chunk_ba_num = mhop.bt_chunk_size / 8; 3899 3900 if (hop_num == 2) { 3901 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3902 k; 3903 l1_idx = i * chunk_ba_num + j; 3904 } else if (hop_num == 1) { 3905 hem_idx = i * chunk_ba_num + j; 3906 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3907 hem_idx = i; 3908 } 3909 3910 if (table->type == HEM_TYPE_SCCC) 3911 obj = mhop.l0_idx; 3912 3913 if (check_whether_last_step(hop_num, step_idx)) { 3914 hem = table->hem[hem_idx]; 3915 for (hns_roce_hem_first(hem, &iter); 3916 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3917 bt_ba = hns_roce_hem_addr(&iter); 3918 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3919 step_idx); 3920 } 3921 } else { 3922 if (step_idx == 0) 3923 bt_ba = table->bt_l0_dma_addr[i]; 3924 else if (step_idx == 1 && hop_num == 2) 3925 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3926 3927 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3928 } 3929 3930 return ret; 3931 } 3932 3933 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3934 struct hns_roce_hem_table *table, int obj, 3935 int step_idx) 3936 { 3937 struct device *dev = hr_dev->dev; 3938 struct hns_roce_cmd_mailbox *mailbox; 3939 int ret; 3940 u16 op = 0xff; 3941 3942 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3943 return 0; 3944 3945 switch (table->type) { 3946 case HEM_TYPE_QPC: 3947 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3948 break; 3949 case HEM_TYPE_MTPT: 3950 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3951 break; 3952 case HEM_TYPE_CQC: 3953 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3954 break; 3955 case HEM_TYPE_SRQC: 3956 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3957 break; 3958 case HEM_TYPE_SCCC: 3959 case HEM_TYPE_QPC_TIMER: 3960 case HEM_TYPE_CQC_TIMER: 3961 case HEM_TYPE_GMV: 3962 return 0; 3963 default: 3964 dev_warn(dev, "table %u not to be destroyed by mailbox!\n", 3965 table->type); 3966 return 0; 3967 } 3968 3969 op += step_idx; 3970 3971 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3972 if (IS_ERR(mailbox)) 3973 return PTR_ERR(mailbox); 3974 3975 /* configure the tag and op */ 3976 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3977 HNS_ROCE_CMD_TIMEOUT_MSECS); 3978 3979 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3980 return ret; 3981 } 3982 3983 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3984 struct hns_roce_v2_qp_context *context, 3985 struct hns_roce_v2_qp_context *qpc_mask, 3986 struct hns_roce_qp *hr_qp) 3987 { 3988 struct hns_roce_cmd_mailbox *mailbox; 3989 int qpc_size; 3990 int ret; 3991 3992 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3993 if (IS_ERR(mailbox)) 3994 return PTR_ERR(mailbox); 3995 3996 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */ 3997 qpc_size = hr_dev->caps.qpc_sz; 3998 memcpy(mailbox->buf, context, qpc_size); 3999 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size); 4000 4001 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 4002 HNS_ROCE_CMD_MODIFY_QPC, 4003 HNS_ROCE_CMD_TIMEOUT_MSECS); 4004 4005 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4006 4007 return ret; 4008 } 4009 4010 static void set_access_flags(struct hns_roce_qp *hr_qp, 4011 struct hns_roce_v2_qp_context *context, 4012 struct hns_roce_v2_qp_context *qpc_mask, 4013 const struct ib_qp_attr *attr, int attr_mask) 4014 { 4015 u8 dest_rd_atomic; 4016 u32 access_flags; 4017 4018 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 4019 attr->max_dest_rd_atomic : hr_qp->resp_depth; 4020 4021 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 4022 attr->qp_access_flags : hr_qp->atomic_rd_en; 4023 4024 if (!dest_rd_atomic) 4025 access_flags &= IB_ACCESS_REMOTE_WRITE; 4026 4027 hr_reg_write_bool(context, QPC_RRE, 4028 access_flags & IB_ACCESS_REMOTE_READ); 4029 hr_reg_clear(qpc_mask, QPC_RRE); 4030 4031 hr_reg_write_bool(context, QPC_RWE, 4032 access_flags & IB_ACCESS_REMOTE_WRITE); 4033 hr_reg_clear(qpc_mask, QPC_RWE); 4034 4035 hr_reg_write_bool(context, QPC_ATE, 4036 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4037 hr_reg_clear(qpc_mask, QPC_ATE); 4038 hr_reg_write_bool(context, QPC_EXT_ATE, 4039 access_flags & IB_ACCESS_REMOTE_ATOMIC); 4040 hr_reg_clear(qpc_mask, QPC_EXT_ATE); 4041 } 4042 4043 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 4044 struct hns_roce_v2_qp_context *context, 4045 struct hns_roce_v2_qp_context *qpc_mask) 4046 { 4047 hr_reg_write(context, QPC_SGE_SHIFT, 4048 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 4049 hr_qp->sge.sge_shift)); 4050 4051 hr_reg_write(context, QPC_SQ_SHIFT, ilog2(hr_qp->sq.wqe_cnt)); 4052 4053 hr_reg_write(context, QPC_RQ_SHIFT, ilog2(hr_qp->rq.wqe_cnt)); 4054 } 4055 4056 static inline int get_cqn(struct ib_cq *ib_cq) 4057 { 4058 return ib_cq ? to_hr_cq(ib_cq)->cqn : 0; 4059 } 4060 4061 static inline int get_pdn(struct ib_pd *ib_pd) 4062 { 4063 return ib_pd ? to_hr_pd(ib_pd)->pdn : 0; 4064 } 4065 4066 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 4067 const struct ib_qp_attr *attr, 4068 int attr_mask, 4069 struct hns_roce_v2_qp_context *context, 4070 struct hns_roce_v2_qp_context *qpc_mask) 4071 { 4072 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4073 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4074 4075 /* 4076 * In v2 engine, software pass context and context mask to hardware 4077 * when modifying qp. If software need modify some fields in context, 4078 * we should set all bits of the relevant fields in context mask to 4079 * 0 at the same time, else set them to 0x1. 4080 */ 4081 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4082 4083 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4084 4085 hr_reg_write(context, QPC_RQWS, ilog2(hr_qp->rq.max_gs)); 4086 4087 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 4088 4089 /* No VLAN need to set 0xFFF */ 4090 hr_reg_write(context, QPC_VLAN_ID, 0xfff); 4091 4092 if (ibqp->qp_type == IB_QPT_XRC_TGT) { 4093 context->qkey_xrcd = cpu_to_le32(hr_qp->xrcdn); 4094 4095 hr_reg_enable(context, QPC_XRC_QP_TYPE); 4096 } 4097 4098 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4099 hr_reg_enable(context, QPC_RQ_RECORD_EN); 4100 4101 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_OWNER_DB) 4102 hr_reg_enable(context, QPC_OWNER_MODE); 4103 4104 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_L, 4105 lower_32_bits(hr_qp->rdb.dma) >> 1); 4106 hr_reg_write(context, QPC_RQ_DB_RECORD_ADDR_H, 4107 upper_32_bits(hr_qp->rdb.dma)); 4108 4109 if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI) 4110 hr_reg_write_bool(context, QPC_RQIE, 4111 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE); 4112 4113 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4114 4115 if (ibqp->srq) { 4116 hr_reg_enable(context, QPC_SRQ_EN); 4117 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4118 } 4119 4120 hr_reg_enable(context, QPC_FRE); 4121 4122 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4123 4124 if (hr_dev->caps.qpc_sz < HNS_ROCE_V3_QPC_SZ) 4125 return; 4126 4127 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_STASH) 4128 hr_reg_enable(&context->ext, QPCEX_STASH); 4129 } 4130 4131 static void modify_qp_init_to_init(struct ib_qp *ibqp, 4132 const struct ib_qp_attr *attr, int attr_mask, 4133 struct hns_roce_v2_qp_context *context, 4134 struct hns_roce_v2_qp_context *qpc_mask) 4135 { 4136 /* 4137 * In v2 engine, software pass context and context mask to hardware 4138 * when modifying qp. If software need modify some fields in context, 4139 * we should set all bits of the relevant fields in context mask to 4140 * 0 at the same time, else set them to 0x1. 4141 */ 4142 hr_reg_write(context, QPC_TST, to_hr_qp_type(ibqp->qp_type)); 4143 hr_reg_clear(qpc_mask, QPC_TST); 4144 4145 hr_reg_write(context, QPC_PD, get_pdn(ibqp->pd)); 4146 hr_reg_clear(qpc_mask, QPC_PD); 4147 4148 hr_reg_write(context, QPC_RX_CQN, get_cqn(ibqp->recv_cq)); 4149 hr_reg_clear(qpc_mask, QPC_RX_CQN); 4150 4151 hr_reg_write(context, QPC_TX_CQN, get_cqn(ibqp->send_cq)); 4152 hr_reg_clear(qpc_mask, QPC_TX_CQN); 4153 4154 if (ibqp->srq) { 4155 hr_reg_enable(context, QPC_SRQ_EN); 4156 hr_reg_clear(qpc_mask, QPC_SRQ_EN); 4157 hr_reg_write(context, QPC_SRQN, to_hr_srq(ibqp->srq)->srqn); 4158 hr_reg_clear(qpc_mask, QPC_SRQN); 4159 } 4160 } 4161 4162 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 4163 struct hns_roce_qp *hr_qp, 4164 struct hns_roce_v2_qp_context *context, 4165 struct hns_roce_v2_qp_context *qpc_mask) 4166 { 4167 u64 mtts[MTT_MIN_COUNT] = { 0 }; 4168 u64 wqe_sge_ba; 4169 int count; 4170 4171 /* Search qp buf's mtts */ 4172 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 4173 MTT_MIN_COUNT, &wqe_sge_ba); 4174 if (hr_qp->rq.wqe_cnt && count < 1) { 4175 ibdev_err(&hr_dev->ib_dev, 4176 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 4177 return -EINVAL; 4178 } 4179 4180 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 4181 qpc_mask->wqe_sge_ba = 0; 4182 4183 /* 4184 * In v2 engine, software pass context and context mask to hardware 4185 * when modifying qp. If software need modify some fields in context, 4186 * we should set all bits of the relevant fields in context mask to 4187 * 0 at the same time, else set them to 0x1. 4188 */ 4189 hr_reg_write(context, QPC_WQE_SGE_BA_H, wqe_sge_ba >> (32 + 3)); 4190 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_H); 4191 4192 hr_reg_write(context, QPC_SQ_HOP_NUM, 4193 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 4194 hr_qp->sq.wqe_cnt)); 4195 hr_reg_clear(qpc_mask, QPC_SQ_HOP_NUM); 4196 4197 hr_reg_write(context, QPC_SGE_HOP_NUM, 4198 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 4199 hr_qp->sge.sge_cnt)); 4200 hr_reg_clear(qpc_mask, QPC_SGE_HOP_NUM); 4201 4202 hr_reg_write(context, QPC_RQ_HOP_NUM, 4203 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 4204 hr_qp->rq.wqe_cnt)); 4205 4206 hr_reg_clear(qpc_mask, QPC_RQ_HOP_NUM); 4207 4208 hr_reg_write(context, QPC_WQE_SGE_BA_PG_SZ, 4209 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 4210 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BA_PG_SZ); 4211 4212 hr_reg_write(context, QPC_WQE_SGE_BUF_PG_SZ, 4213 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 4214 hr_reg_clear(qpc_mask, QPC_WQE_SGE_BUF_PG_SZ); 4215 4216 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 4217 qpc_mask->rq_cur_blk_addr = 0; 4218 4219 hr_reg_write(context, QPC_RQ_CUR_BLK_ADDR_H, 4220 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 4221 hr_reg_clear(qpc_mask, QPC_RQ_CUR_BLK_ADDR_H); 4222 4223 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 4224 qpc_mask->rq_nxt_blk_addr = 0; 4225 4226 hr_reg_write(context, QPC_RQ_NXT_BLK_ADDR_H, 4227 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 4228 hr_reg_clear(qpc_mask, QPC_RQ_NXT_BLK_ADDR_H); 4229 4230 return 0; 4231 } 4232 4233 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 4234 struct hns_roce_qp *hr_qp, 4235 struct hns_roce_v2_qp_context *context, 4236 struct hns_roce_v2_qp_context *qpc_mask) 4237 { 4238 struct ib_device *ibdev = &hr_dev->ib_dev; 4239 u64 sge_cur_blk = 0; 4240 u64 sq_cur_blk = 0; 4241 int count; 4242 4243 /* search qp buf's mtts */ 4244 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 4245 if (count < 1) { 4246 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 4247 hr_qp->qpn); 4248 return -EINVAL; 4249 } 4250 if (hr_qp->sge.sge_cnt > 0) { 4251 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 4252 hr_qp->sge.offset, 4253 &sge_cur_blk, 1, NULL); 4254 if (count < 1) { 4255 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 4256 hr_qp->qpn); 4257 return -EINVAL; 4258 } 4259 } 4260 4261 /* 4262 * In v2 engine, software pass context and context mask to hardware 4263 * when modifying qp. If software need modify some fields in context, 4264 * we should set all bits of the relevant fields in context mask to 4265 * 0 at the same time, else set them to 0x1. 4266 */ 4267 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_L, 4268 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4269 hr_reg_write(context, QPC_SQ_CUR_BLK_ADDR_H, 4270 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4271 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_L); 4272 hr_reg_clear(qpc_mask, QPC_SQ_CUR_BLK_ADDR_H); 4273 4274 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_L, 4275 lower_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4276 hr_reg_write(context, QPC_SQ_CUR_SGE_BLK_ADDR_H, 4277 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 4278 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_L); 4279 hr_reg_clear(qpc_mask, QPC_SQ_CUR_SGE_BLK_ADDR_H); 4280 4281 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_L, 4282 lower_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4283 hr_reg_write(context, QPC_RX_SQ_CUR_BLK_ADDR_H, 4284 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 4285 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_L); 4286 hr_reg_clear(qpc_mask, QPC_RX_SQ_CUR_BLK_ADDR_H); 4287 4288 return 0; 4289 } 4290 4291 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 4292 const struct ib_qp_attr *attr) 4293 { 4294 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 4295 return IB_MTU_4096; 4296 4297 return attr->path_mtu; 4298 } 4299 4300 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 4301 const struct ib_qp_attr *attr, int attr_mask, 4302 struct hns_roce_v2_qp_context *context, 4303 struct hns_roce_v2_qp_context *qpc_mask) 4304 { 4305 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4306 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4307 struct ib_device *ibdev = &hr_dev->ib_dev; 4308 dma_addr_t trrl_ba; 4309 dma_addr_t irrl_ba; 4310 enum ib_mtu ib_mtu; 4311 const u8 *smac; 4312 u8 lp_pktn_ini; 4313 u64 *mtts; 4314 u8 *dmac; 4315 u32 port; 4316 int mtu; 4317 int ret; 4318 4319 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 4320 if (ret) { 4321 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 4322 return ret; 4323 } 4324 4325 /* Search IRRL's mtts */ 4326 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 4327 hr_qp->qpn, &irrl_ba); 4328 if (!mtts) { 4329 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 4330 return -EINVAL; 4331 } 4332 4333 /* Search TRRL's mtts */ 4334 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 4335 hr_qp->qpn, &trrl_ba); 4336 if (!mtts) { 4337 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 4338 return -EINVAL; 4339 } 4340 4341 if (attr_mask & IB_QP_ALT_PATH) { 4342 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 4343 attr_mask); 4344 return -EINVAL; 4345 } 4346 4347 hr_reg_write(context, QPC_TRRL_BA_L, trrl_ba >> 4); 4348 hr_reg_clear(qpc_mask, QPC_TRRL_BA_L); 4349 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 4350 qpc_mask->trrl_ba = 0; 4351 hr_reg_write(context, QPC_TRRL_BA_H, trrl_ba >> (32 + 16 + 4)); 4352 hr_reg_clear(qpc_mask, QPC_TRRL_BA_H); 4353 4354 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4355 qpc_mask->irrl_ba = 0; 4356 hr_reg_write(context, QPC_IRRL_BA_H, irrl_ba >> (32 + 6)); 4357 hr_reg_clear(qpc_mask, QPC_IRRL_BA_H); 4358 4359 hr_reg_enable(context, QPC_RMT_E2E); 4360 hr_reg_clear(qpc_mask, QPC_RMT_E2E); 4361 4362 hr_reg_write(context, QPC_SIG_TYPE, hr_qp->sq_signal_bits); 4363 hr_reg_clear(qpc_mask, QPC_SIG_TYPE); 4364 4365 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4366 4367 smac = (const u8 *)hr_dev->dev_addr[port]; 4368 dmac = (u8 *)attr->ah_attr.roce.dmac; 4369 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4370 if (ether_addr_equal_unaligned(dmac, smac) || 4371 hr_dev->loop_idc == 0x1) { 4372 hr_reg_write(context, QPC_LBI, hr_dev->loop_idc); 4373 hr_reg_clear(qpc_mask, QPC_LBI); 4374 } 4375 4376 if (attr_mask & IB_QP_DEST_QPN) { 4377 hr_reg_write(context, QPC_DQPN, attr->dest_qp_num); 4378 hr_reg_clear(qpc_mask, QPC_DQPN); 4379 } 4380 4381 memcpy(&(context->dmac), dmac, sizeof(u32)); 4382 hr_reg_write(context, QPC_DMAC_H, *((u16 *)(&dmac[4]))); 4383 qpc_mask->dmac = 0; 4384 hr_reg_clear(qpc_mask, QPC_DMAC_H); 4385 4386 ib_mtu = get_mtu(ibqp, attr); 4387 hr_qp->path_mtu = ib_mtu; 4388 4389 mtu = ib_mtu_enum_to_int(ib_mtu); 4390 if (WARN_ON(mtu <= 0)) 4391 return -EINVAL; 4392 #define MAX_LP_MSG_LEN 16384 4393 /* MTU * (2 ^ LP_PKTN_INI) shouldn't be bigger than 16KB */ 4394 lp_pktn_ini = ilog2(MAX_LP_MSG_LEN / mtu); 4395 if (WARN_ON(lp_pktn_ini >= 0xF)) 4396 return -EINVAL; 4397 4398 if (attr_mask & IB_QP_PATH_MTU) { 4399 hr_reg_write(context, QPC_MTU, ib_mtu); 4400 hr_reg_clear(qpc_mask, QPC_MTU); 4401 } 4402 4403 hr_reg_write(context, QPC_LP_PKTN_INI, lp_pktn_ini); 4404 hr_reg_clear(qpc_mask, QPC_LP_PKTN_INI); 4405 4406 /* ACK_REQ_FREQ should be larger than or equal to LP_PKTN_INI */ 4407 hr_reg_write(context, QPC_ACK_REQ_FREQ, lp_pktn_ini); 4408 hr_reg_clear(qpc_mask, QPC_ACK_REQ_FREQ); 4409 4410 hr_reg_clear(qpc_mask, QPC_RX_REQ_PSN_ERR); 4411 hr_reg_clear(qpc_mask, QPC_RX_REQ_MSN); 4412 hr_reg_clear(qpc_mask, QPC_RX_REQ_LAST_OPTYPE); 4413 4414 context->rq_rnr_timer = 0; 4415 qpc_mask->rq_rnr_timer = 0; 4416 4417 hr_reg_clear(qpc_mask, QPC_TRRL_HEAD_MAX); 4418 hr_reg_clear(qpc_mask, QPC_TRRL_TAIL_MAX); 4419 4420 /* rocee send 2^lp_sgen_ini segs every time */ 4421 hr_reg_write(context, QPC_LP_SGEN_INI, 3); 4422 hr_reg_clear(qpc_mask, QPC_LP_SGEN_INI); 4423 4424 return 0; 4425 } 4426 4427 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4428 const struct ib_qp_attr *attr, int attr_mask, 4429 struct hns_roce_v2_qp_context *context, 4430 struct hns_roce_v2_qp_context *qpc_mask) 4431 { 4432 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4433 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4434 struct ib_device *ibdev = &hr_dev->ib_dev; 4435 int ret; 4436 4437 /* Not support alternate path and path migration */ 4438 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4439 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4440 return -EINVAL; 4441 } 4442 4443 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4444 if (ret) { 4445 ibdev_err(ibdev, "failed to config sq buf, ret = %d.\n", ret); 4446 return ret; 4447 } 4448 4449 /* 4450 * Set some fields in context to zero, Because the default values 4451 * of all fields in context are zero, we need not set them to 0 again. 4452 * but we should set the relevant fields of context mask to 0. 4453 */ 4454 hr_reg_clear(qpc_mask, QPC_IRRL_SGE_IDX); 4455 4456 hr_reg_clear(qpc_mask, QPC_RX_ACK_MSN); 4457 4458 hr_reg_clear(qpc_mask, QPC_ACK_LAST_OPTYPE); 4459 hr_reg_clear(qpc_mask, QPC_IRRL_PSN_VLD); 4460 hr_reg_clear(qpc_mask, QPC_IRRL_PSN); 4461 4462 hr_reg_clear(qpc_mask, QPC_IRRL_TAIL_REAL); 4463 4464 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_MSN); 4465 4466 hr_reg_clear(qpc_mask, QPC_RNR_RETRY_FLAG); 4467 4468 hr_reg_clear(qpc_mask, QPC_CHECK_FLG); 4469 4470 hr_reg_clear(qpc_mask, QPC_V2_IRRL_HEAD); 4471 4472 return 0; 4473 } 4474 4475 static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn) 4476 { 4477 if (!fl) 4478 fl = rdma_calc_flow_label(lqpn, rqpn); 4479 4480 return rdma_flow_label_to_udp_sport(fl); 4481 } 4482 4483 static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4484 u32 *dip_idx) 4485 { 4486 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4487 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4488 u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx; 4489 u32 *head = &hr_dev->qp_table.idx_table.head; 4490 u32 *tail = &hr_dev->qp_table.idx_table.tail; 4491 struct hns_roce_dip *hr_dip; 4492 unsigned long flags; 4493 int ret = 0; 4494 4495 spin_lock_irqsave(&hr_dev->dip_list_lock, flags); 4496 4497 spare_idx[*tail] = ibqp->qp_num; 4498 *tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1); 4499 4500 list_for_each_entry(hr_dip, &hr_dev->dip_list, node) { 4501 if (!memcmp(grh->dgid.raw, hr_dip->dgid, 16)) { 4502 *dip_idx = hr_dip->dip_idx; 4503 goto out; 4504 } 4505 } 4506 4507 /* If no dgid is found, a new dip and a mapping between dgid and 4508 * dip_idx will be created. 4509 */ 4510 hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC); 4511 if (!hr_dip) { 4512 ret = -ENOMEM; 4513 goto out; 4514 } 4515 4516 memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4517 hr_dip->dip_idx = *dip_idx = spare_idx[*head]; 4518 *head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1); 4519 list_add_tail(&hr_dip->node, &hr_dev->dip_list); 4520 4521 out: 4522 spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags); 4523 return ret; 4524 } 4525 4526 enum { 4527 CONG_DCQCN, 4528 CONG_WINDOW, 4529 }; 4530 4531 enum { 4532 UNSUPPORT_CONG_LEVEL, 4533 SUPPORT_CONG_LEVEL, 4534 }; 4535 4536 enum { 4537 CONG_LDCP, 4538 CONG_HC3, 4539 }; 4540 4541 enum { 4542 DIP_INVALID, 4543 DIP_VALID, 4544 }; 4545 4546 enum { 4547 WND_LIMIT, 4548 WND_UNLIMIT, 4549 }; 4550 4551 static int check_cong_type(struct ib_qp *ibqp, 4552 struct hns_roce_congestion_algorithm *cong_alg) 4553 { 4554 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4555 4556 /* different congestion types match different configurations */ 4557 switch (hr_dev->caps.cong_type) { 4558 case CONG_TYPE_DCQCN: 4559 cong_alg->alg_sel = CONG_DCQCN; 4560 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4561 cong_alg->dip_vld = DIP_INVALID; 4562 cong_alg->wnd_mode_sel = WND_LIMIT; 4563 break; 4564 case CONG_TYPE_LDCP: 4565 cong_alg->alg_sel = CONG_WINDOW; 4566 cong_alg->alg_sub_sel = CONG_LDCP; 4567 cong_alg->dip_vld = DIP_INVALID; 4568 cong_alg->wnd_mode_sel = WND_UNLIMIT; 4569 break; 4570 case CONG_TYPE_HC3: 4571 cong_alg->alg_sel = CONG_WINDOW; 4572 cong_alg->alg_sub_sel = CONG_HC3; 4573 cong_alg->dip_vld = DIP_INVALID; 4574 cong_alg->wnd_mode_sel = WND_LIMIT; 4575 break; 4576 case CONG_TYPE_DIP: 4577 cong_alg->alg_sel = CONG_DCQCN; 4578 cong_alg->alg_sub_sel = UNSUPPORT_CONG_LEVEL; 4579 cong_alg->dip_vld = DIP_VALID; 4580 cong_alg->wnd_mode_sel = WND_LIMIT; 4581 break; 4582 default: 4583 ibdev_err(&hr_dev->ib_dev, 4584 "error type(%u) for congestion selection.\n", 4585 hr_dev->caps.cong_type); 4586 return -EINVAL; 4587 } 4588 4589 return 0; 4590 } 4591 4592 static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 4593 struct hns_roce_v2_qp_context *context, 4594 struct hns_roce_v2_qp_context *qpc_mask) 4595 { 4596 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4597 struct hns_roce_congestion_algorithm cong_field; 4598 struct ib_device *ibdev = ibqp->device; 4599 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 4600 u32 dip_idx = 0; 4601 int ret; 4602 4603 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08 || 4604 grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE) 4605 return 0; 4606 4607 ret = check_cong_type(ibqp, &cong_field); 4608 if (ret) 4609 return ret; 4610 4611 hr_reg_write(context, QPC_CONG_ALGO_TMPL_ID, hr_dev->cong_algo_tmpl_id + 4612 hr_dev->caps.cong_type * HNS_ROCE_CONG_SIZE); 4613 hr_reg_clear(qpc_mask, QPC_CONG_ALGO_TMPL_ID); 4614 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SEL, cong_field.alg_sel); 4615 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SEL); 4616 hr_reg_write(&context->ext, QPCEX_CONG_ALG_SUB_SEL, 4617 cong_field.alg_sub_sel); 4618 hr_reg_clear(&qpc_mask->ext, QPCEX_CONG_ALG_SUB_SEL); 4619 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX_VLD, cong_field.dip_vld); 4620 hr_reg_clear(&qpc_mask->ext, QPCEX_DIP_CTX_IDX_VLD); 4621 hr_reg_write(&context->ext, QPCEX_SQ_RQ_NOT_FORBID_EN, 4622 cong_field.wnd_mode_sel); 4623 hr_reg_clear(&qpc_mask->ext, QPCEX_SQ_RQ_NOT_FORBID_EN); 4624 4625 /* if dip is disabled, there is no need to set dip idx */ 4626 if (cong_field.dip_vld == 0) 4627 return 0; 4628 4629 ret = get_dip_ctx_idx(ibqp, attr, &dip_idx); 4630 if (ret) { 4631 ibdev_err(ibdev, "failed to fill cong field, ret = %d.\n", ret); 4632 return ret; 4633 } 4634 4635 hr_reg_write(&context->ext, QPCEX_DIP_CTX_IDX, dip_idx); 4636 hr_reg_write(&qpc_mask->ext, QPCEX_DIP_CTX_IDX, 0); 4637 4638 return 0; 4639 } 4640 4641 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4642 const struct ib_qp_attr *attr, 4643 int attr_mask, 4644 struct hns_roce_v2_qp_context *context, 4645 struct hns_roce_v2_qp_context *qpc_mask) 4646 { 4647 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4648 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4649 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4650 struct ib_device *ibdev = &hr_dev->ib_dev; 4651 const struct ib_gid_attr *gid_attr = NULL; 4652 int is_roce_protocol; 4653 u16 vlan_id = 0xffff; 4654 bool is_udp = false; 4655 u8 ib_port; 4656 u8 hr_port; 4657 int ret; 4658 4659 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4660 hr_port = ib_port - 1; 4661 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4662 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4663 4664 if (is_roce_protocol) { 4665 gid_attr = attr->ah_attr.grh.sgid_attr; 4666 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4667 if (ret) 4668 return ret; 4669 4670 if (gid_attr) 4671 is_udp = (gid_attr->gid_type == 4672 IB_GID_TYPE_ROCE_UDP_ENCAP); 4673 } 4674 4675 /* Only HIP08 needs to set the vlan_en bits in QPC */ 4676 if (vlan_id < VLAN_N_VID && 4677 hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) { 4678 hr_reg_enable(context, QPC_RQ_VLAN_EN); 4679 hr_reg_clear(qpc_mask, QPC_RQ_VLAN_EN); 4680 hr_reg_enable(context, QPC_SQ_VLAN_EN); 4681 hr_reg_clear(qpc_mask, QPC_SQ_VLAN_EN); 4682 } 4683 4684 hr_reg_write(context, QPC_VLAN_ID, vlan_id); 4685 hr_reg_clear(qpc_mask, QPC_VLAN_ID); 4686 4687 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4688 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4689 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4690 return -EINVAL; 4691 } 4692 4693 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4694 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4695 return -EINVAL; 4696 } 4697 4698 hr_reg_write(context, QPC_UDPSPN, 4699 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num, 4700 attr->dest_qp_num) : 0); 4701 4702 hr_reg_clear(qpc_mask, QPC_UDPSPN); 4703 4704 hr_reg_write(context, QPC_GMV_IDX, grh->sgid_index); 4705 4706 hr_reg_clear(qpc_mask, QPC_GMV_IDX); 4707 4708 hr_reg_write(context, QPC_HOPLIMIT, grh->hop_limit); 4709 hr_reg_clear(qpc_mask, QPC_HOPLIMIT); 4710 4711 ret = fill_cong_field(ibqp, attr, context, qpc_mask); 4712 if (ret) 4713 return ret; 4714 4715 hr_reg_write(context, QPC_TC, get_tclass(&attr->ah_attr.grh)); 4716 hr_reg_clear(qpc_mask, QPC_TC); 4717 4718 hr_reg_write(context, QPC_FL, grh->flow_label); 4719 hr_reg_clear(qpc_mask, QPC_FL); 4720 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4721 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4722 4723 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4724 if (unlikely(hr_qp->sl > MAX_SERVICE_LEVEL)) { 4725 ibdev_err(ibdev, 4726 "failed to fill QPC, sl (%d) shouldn't be larger than %d.\n", 4727 hr_qp->sl, MAX_SERVICE_LEVEL); 4728 return -EINVAL; 4729 } 4730 4731 hr_reg_write(context, QPC_SL, hr_qp->sl); 4732 hr_reg_clear(qpc_mask, QPC_SL); 4733 4734 return 0; 4735 } 4736 4737 static bool check_qp_state(enum ib_qp_state cur_state, 4738 enum ib_qp_state new_state) 4739 { 4740 static const bool sm[][IB_QPS_ERR + 1] = { 4741 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4742 [IB_QPS_INIT] = true }, 4743 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4744 [IB_QPS_INIT] = true, 4745 [IB_QPS_RTR] = true, 4746 [IB_QPS_ERR] = true }, 4747 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4748 [IB_QPS_RTS] = true, 4749 [IB_QPS_ERR] = true }, 4750 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4751 [IB_QPS_RTS] = true, 4752 [IB_QPS_ERR] = true }, 4753 [IB_QPS_SQD] = {}, 4754 [IB_QPS_SQE] = {}, 4755 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4756 }; 4757 4758 return sm[cur_state][new_state]; 4759 } 4760 4761 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4762 const struct ib_qp_attr *attr, 4763 int attr_mask, 4764 enum ib_qp_state cur_state, 4765 enum ib_qp_state new_state, 4766 struct hns_roce_v2_qp_context *context, 4767 struct hns_roce_v2_qp_context *qpc_mask) 4768 { 4769 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4770 int ret = 0; 4771 4772 if (!check_qp_state(cur_state, new_state)) { 4773 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4774 return -EINVAL; 4775 } 4776 4777 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4778 memset(qpc_mask, 0, hr_dev->caps.qpc_sz); 4779 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4780 qpc_mask); 4781 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4782 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4783 qpc_mask); 4784 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4785 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4786 qpc_mask); 4787 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4788 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4789 qpc_mask); 4790 } 4791 4792 return ret; 4793 } 4794 4795 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4796 const struct ib_qp_attr *attr, 4797 int attr_mask, 4798 struct hns_roce_v2_qp_context *context, 4799 struct hns_roce_v2_qp_context *qpc_mask) 4800 { 4801 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4802 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4803 int ret = 0; 4804 4805 if (attr_mask & IB_QP_AV) { 4806 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4807 qpc_mask); 4808 if (ret) 4809 return ret; 4810 } 4811 4812 if (attr_mask & IB_QP_TIMEOUT) { 4813 if (attr->timeout < 31) { 4814 hr_reg_write(context, QPC_AT, attr->timeout); 4815 hr_reg_clear(qpc_mask, QPC_AT); 4816 } else { 4817 ibdev_warn(&hr_dev->ib_dev, 4818 "Local ACK timeout shall be 0 to 30.\n"); 4819 } 4820 } 4821 4822 if (attr_mask & IB_QP_RETRY_CNT) { 4823 hr_reg_write(context, QPC_RETRY_NUM_INIT, attr->retry_cnt); 4824 hr_reg_clear(qpc_mask, QPC_RETRY_NUM_INIT); 4825 4826 hr_reg_write(context, QPC_RETRY_CNT, attr->retry_cnt); 4827 hr_reg_clear(qpc_mask, QPC_RETRY_CNT); 4828 } 4829 4830 if (attr_mask & IB_QP_RNR_RETRY) { 4831 hr_reg_write(context, QPC_RNR_NUM_INIT, attr->rnr_retry); 4832 hr_reg_clear(qpc_mask, QPC_RNR_NUM_INIT); 4833 4834 hr_reg_write(context, QPC_RNR_CNT, attr->rnr_retry); 4835 hr_reg_clear(qpc_mask, QPC_RNR_CNT); 4836 } 4837 4838 if (attr_mask & IB_QP_SQ_PSN) { 4839 hr_reg_write(context, QPC_SQ_CUR_PSN, attr->sq_psn); 4840 hr_reg_clear(qpc_mask, QPC_SQ_CUR_PSN); 4841 4842 hr_reg_write(context, QPC_SQ_MAX_PSN, attr->sq_psn); 4843 hr_reg_clear(qpc_mask, QPC_SQ_MAX_PSN); 4844 4845 hr_reg_write(context, QPC_RETRY_MSG_PSN_L, attr->sq_psn); 4846 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_L); 4847 4848 hr_reg_write(context, QPC_RETRY_MSG_PSN_H, 4849 attr->sq_psn >> RETRY_MSG_PSN_SHIFT); 4850 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_PSN_H); 4851 4852 hr_reg_write(context, QPC_RETRY_MSG_FPKT_PSN, attr->sq_psn); 4853 hr_reg_clear(qpc_mask, QPC_RETRY_MSG_FPKT_PSN); 4854 4855 hr_reg_write(context, QPC_RX_ACK_EPSN, attr->sq_psn); 4856 hr_reg_clear(qpc_mask, QPC_RX_ACK_EPSN); 4857 } 4858 4859 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4860 attr->max_dest_rd_atomic) { 4861 hr_reg_write(context, QPC_RR_MAX, 4862 fls(attr->max_dest_rd_atomic - 1)); 4863 hr_reg_clear(qpc_mask, QPC_RR_MAX); 4864 } 4865 4866 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4867 hr_reg_write(context, QPC_SR_MAX, fls(attr->max_rd_atomic - 1)); 4868 hr_reg_clear(qpc_mask, QPC_SR_MAX); 4869 } 4870 4871 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4872 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4873 4874 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4875 hr_reg_write(context, QPC_MIN_RNR_TIME, attr->min_rnr_timer); 4876 hr_reg_clear(qpc_mask, QPC_MIN_RNR_TIME); 4877 } 4878 4879 if (attr_mask & IB_QP_RQ_PSN) { 4880 hr_reg_write(context, QPC_RX_REQ_EPSN, attr->rq_psn); 4881 hr_reg_clear(qpc_mask, QPC_RX_REQ_EPSN); 4882 4883 hr_reg_write(context, QPC_RAQ_PSN, attr->rq_psn - 1); 4884 hr_reg_clear(qpc_mask, QPC_RAQ_PSN); 4885 } 4886 4887 if (attr_mask & IB_QP_QKEY) { 4888 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4889 qpc_mask->qkey_xrcd = 0; 4890 hr_qp->qkey = attr->qkey; 4891 } 4892 4893 return ret; 4894 } 4895 4896 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4897 const struct ib_qp_attr *attr, 4898 int attr_mask) 4899 { 4900 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4901 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4902 4903 if (attr_mask & IB_QP_ACCESS_FLAGS) 4904 hr_qp->atomic_rd_en = attr->qp_access_flags; 4905 4906 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4907 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4908 if (attr_mask & IB_QP_PORT) { 4909 hr_qp->port = attr->port_num - 1; 4910 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4911 } 4912 } 4913 4914 static void clear_qp(struct hns_roce_qp *hr_qp) 4915 { 4916 struct ib_qp *ibqp = &hr_qp->ibqp; 4917 4918 if (ibqp->send_cq) 4919 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4920 hr_qp->qpn, NULL); 4921 4922 if (ibqp->recv_cq && ibqp->recv_cq != ibqp->send_cq) 4923 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), 4924 hr_qp->qpn, ibqp->srq ? 4925 to_hr_srq(ibqp->srq) : NULL); 4926 4927 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 4928 *hr_qp->rdb.db_record = 0; 4929 4930 hr_qp->rq.head = 0; 4931 hr_qp->rq.tail = 0; 4932 hr_qp->sq.head = 0; 4933 hr_qp->sq.tail = 0; 4934 hr_qp->next_sge = 0; 4935 } 4936 4937 static void v2_set_flushed_fields(struct ib_qp *ibqp, 4938 struct hns_roce_v2_qp_context *context, 4939 struct hns_roce_v2_qp_context *qpc_mask) 4940 { 4941 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4942 unsigned long sq_flag = 0; 4943 unsigned long rq_flag = 0; 4944 4945 if (ibqp->qp_type == IB_QPT_XRC_TGT) 4946 return; 4947 4948 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4949 hr_reg_write(context, QPC_SQ_PRODUCER_IDX, hr_qp->sq.head); 4950 hr_reg_clear(qpc_mask, QPC_SQ_PRODUCER_IDX); 4951 hr_qp->state = IB_QPS_ERR; 4952 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4953 4954 if (ibqp->srq || ibqp->qp_type == IB_QPT_XRC_INI) /* no RQ */ 4955 return; 4956 4957 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4958 hr_reg_write(context, QPC_RQ_PRODUCER_IDX, hr_qp->rq.head); 4959 hr_reg_clear(qpc_mask, QPC_RQ_PRODUCER_IDX); 4960 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4961 } 4962 4963 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4964 const struct ib_qp_attr *attr, 4965 int attr_mask, enum ib_qp_state cur_state, 4966 enum ib_qp_state new_state) 4967 { 4968 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4969 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4970 struct hns_roce_v2_qp_context ctx[2]; 4971 struct hns_roce_v2_qp_context *context = ctx; 4972 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4973 struct ib_device *ibdev = &hr_dev->ib_dev; 4974 int ret; 4975 4976 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 4977 return -EOPNOTSUPP; 4978 4979 /* 4980 * In v2 engine, software pass context and context mask to hardware 4981 * when modifying qp. If software need modify some fields in context, 4982 * we should set all bits of the relevant fields in context mask to 4983 * 0 at the same time, else set them to 0x1. 4984 */ 4985 memset(context, 0, hr_dev->caps.qpc_sz); 4986 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz); 4987 4988 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4989 new_state, context, qpc_mask); 4990 if (ret) 4991 goto out; 4992 4993 /* When QP state is err, SQ and RQ WQE should be flushed */ 4994 if (new_state == IB_QPS_ERR) 4995 v2_set_flushed_fields(ibqp, context, qpc_mask); 4996 4997 /* Configure the optional fields */ 4998 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 4999 qpc_mask); 5000 if (ret) 5001 goto out; 5002 5003 hr_reg_write_bool(context, QPC_INV_CREDIT, 5004 to_hr_qp_type(hr_qp->ibqp.qp_type) == SERV_TYPE_XRC || 5005 ibqp->srq); 5006 hr_reg_clear(qpc_mask, QPC_INV_CREDIT); 5007 5008 /* Every status migrate must change state */ 5009 hr_reg_write(context, QPC_QP_ST, new_state); 5010 hr_reg_clear(qpc_mask, QPC_QP_ST); 5011 5012 /* SW pass context to HW */ 5013 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp); 5014 if (ret) { 5015 ibdev_err(ibdev, "failed to modify QP, ret = %d.\n", ret); 5016 goto out; 5017 } 5018 5019 hr_qp->state = new_state; 5020 5021 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 5022 5023 if (new_state == IB_QPS_RESET && !ibqp->uobject) 5024 clear_qp(hr_qp); 5025 5026 out: 5027 return ret; 5028 } 5029 5030 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 5031 { 5032 static const enum ib_qp_state map[] = { 5033 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 5034 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 5035 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 5036 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 5037 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 5038 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 5039 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 5040 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 5041 }; 5042 5043 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 5044 } 5045 5046 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 5047 struct hns_roce_qp *hr_qp, 5048 struct hns_roce_v2_qp_context *hr_context) 5049 { 5050 struct hns_roce_cmd_mailbox *mailbox; 5051 int ret; 5052 5053 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5054 if (IS_ERR(mailbox)) 5055 return PTR_ERR(mailbox); 5056 5057 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 5058 HNS_ROCE_CMD_QUERY_QPC, 5059 HNS_ROCE_CMD_TIMEOUT_MSECS); 5060 if (ret) 5061 goto out; 5062 5063 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz); 5064 5065 out: 5066 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5067 return ret; 5068 } 5069 5070 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 5071 int qp_attr_mask, 5072 struct ib_qp_init_attr *qp_init_attr) 5073 { 5074 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5075 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5076 struct hns_roce_v2_qp_context context = {}; 5077 struct ib_device *ibdev = &hr_dev->ib_dev; 5078 int tmp_qp_state; 5079 int state; 5080 int ret; 5081 5082 memset(qp_attr, 0, sizeof(*qp_attr)); 5083 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 5084 5085 mutex_lock(&hr_qp->mutex); 5086 5087 if (hr_qp->state == IB_QPS_RESET) { 5088 qp_attr->qp_state = IB_QPS_RESET; 5089 ret = 0; 5090 goto done; 5091 } 5092 5093 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 5094 if (ret) { 5095 ibdev_err(ibdev, "failed to query QPC, ret = %d.\n", ret); 5096 ret = -EINVAL; 5097 goto out; 5098 } 5099 5100 state = hr_reg_read(&context, QPC_QP_ST); 5101 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 5102 if (tmp_qp_state == -1) { 5103 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 5104 ret = -EINVAL; 5105 goto out; 5106 } 5107 hr_qp->state = (u8)tmp_qp_state; 5108 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 5109 qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU); 5110 qp_attr->path_mig_state = IB_MIG_ARMED; 5111 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 5112 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 5113 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 5114 5115 qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN); 5116 qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN); 5117 qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN); 5118 qp_attr->qp_access_flags = 5119 ((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) | 5120 ((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) | 5121 ((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S); 5122 5123 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 5124 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5125 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) { 5126 struct ib_global_route *grh = 5127 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 5128 5129 rdma_ah_set_sl(&qp_attr->ah_attr, 5130 hr_reg_read(&context, QPC_SL)); 5131 grh->flow_label = hr_reg_read(&context, QPC_FL); 5132 grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX); 5133 grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT); 5134 grh->traffic_class = hr_reg_read(&context, QPC_TC); 5135 5136 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 5137 } 5138 5139 qp_attr->port_num = hr_qp->port + 1; 5140 qp_attr->sq_draining = 0; 5141 qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX); 5142 qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX); 5143 5144 qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME); 5145 qp_attr->timeout = (u8)hr_reg_read(&context, QPC_AT); 5146 qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT); 5147 qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT); 5148 5149 done: 5150 qp_attr->cur_qp_state = qp_attr->qp_state; 5151 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 5152 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs - hr_qp->rq.rsv_sge; 5153 qp_attr->cap.max_inline_data = hr_qp->max_inline_data; 5154 5155 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 5156 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 5157 5158 qp_init_attr->qp_context = ibqp->qp_context; 5159 qp_init_attr->qp_type = ibqp->qp_type; 5160 qp_init_attr->recv_cq = ibqp->recv_cq; 5161 qp_init_attr->send_cq = ibqp->send_cq; 5162 qp_init_attr->srq = ibqp->srq; 5163 qp_init_attr->cap = qp_attr->cap; 5164 qp_init_attr->sq_sig_type = hr_qp->sq_signal_bits; 5165 5166 out: 5167 mutex_unlock(&hr_qp->mutex); 5168 return ret; 5169 } 5170 5171 static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) 5172 { 5173 return ((hr_qp->ibqp.qp_type == IB_QPT_RC || 5174 hr_qp->ibqp.qp_type == IB_QPT_UD || 5175 hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || 5176 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT) && 5177 hr_qp->state != IB_QPS_RESET); 5178 } 5179 5180 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 5181 struct hns_roce_qp *hr_qp, 5182 struct ib_udata *udata) 5183 { 5184 struct ib_device *ibdev = &hr_dev->ib_dev; 5185 struct hns_roce_cq *send_cq, *recv_cq; 5186 unsigned long flags; 5187 int ret = 0; 5188 5189 if (modify_qp_is_ok(hr_qp)) { 5190 /* Modify qp to reset before destroying qp */ 5191 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 5192 hr_qp->state, IB_QPS_RESET); 5193 if (ret) 5194 ibdev_err(ibdev, 5195 "failed to modify QP to RST, ret = %d.\n", 5196 ret); 5197 } 5198 5199 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 5200 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 5201 5202 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 5203 hns_roce_lock_cqs(send_cq, recv_cq); 5204 5205 if (!udata) { 5206 if (recv_cq) 5207 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 5208 (hr_qp->ibqp.srq ? 5209 to_hr_srq(hr_qp->ibqp.srq) : 5210 NULL)); 5211 5212 if (send_cq && send_cq != recv_cq) 5213 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 5214 } 5215 5216 hns_roce_qp_remove(hr_dev, hr_qp); 5217 5218 hns_roce_unlock_cqs(send_cq, recv_cq); 5219 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 5220 5221 return ret; 5222 } 5223 5224 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 5225 { 5226 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 5227 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 5228 int ret; 5229 5230 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 5231 if (ret) 5232 ibdev_err(&hr_dev->ib_dev, 5233 "failed to destroy QP, QPN = 0x%06lx, ret = %d.\n", 5234 hr_qp->qpn, ret); 5235 5236 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 5237 5238 return 0; 5239 } 5240 5241 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 5242 struct hns_roce_qp *hr_qp) 5243 { 5244 struct ib_device *ibdev = &hr_dev->ib_dev; 5245 struct hns_roce_sccc_clr_done *resp; 5246 struct hns_roce_sccc_clr *clr; 5247 struct hns_roce_cmq_desc desc; 5248 int ret, i; 5249 5250 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 5251 return 0; 5252 5253 mutex_lock(&hr_dev->qp_table.scc_mutex); 5254 5255 /* set scc ctx clear done flag */ 5256 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 5257 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5258 if (ret) { 5259 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d.\n", ret); 5260 goto out; 5261 } 5262 5263 /* clear scc context */ 5264 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 5265 clr = (struct hns_roce_sccc_clr *)desc.data; 5266 clr->qpn = cpu_to_le32(hr_qp->qpn); 5267 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5268 if (ret) { 5269 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d.\n", ret); 5270 goto out; 5271 } 5272 5273 /* query scc context clear is done or not */ 5274 resp = (struct hns_roce_sccc_clr_done *)desc.data; 5275 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 5276 hns_roce_cmq_setup_basic_desc(&desc, 5277 HNS_ROCE_OPC_QUERY_SCCC, true); 5278 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 5279 if (ret) { 5280 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 5281 ret); 5282 goto out; 5283 } 5284 5285 if (resp->clr_done) 5286 goto out; 5287 5288 msleep(20); 5289 } 5290 5291 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 5292 ret = -ETIMEDOUT; 5293 5294 out: 5295 mutex_unlock(&hr_dev->qp_table.scc_mutex); 5296 return ret; 5297 } 5298 5299 #define DMA_IDX_SHIFT 3 5300 #define DMA_WQE_SHIFT 3 5301 5302 static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, 5303 struct hns_roce_srq_context *ctx) 5304 { 5305 struct hns_roce_idx_que *idx_que = &srq->idx_que; 5306 struct ib_device *ibdev = srq->ibsrq.device; 5307 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5308 u64 mtts_idx[MTT_MIN_COUNT] = {}; 5309 dma_addr_t dma_handle_idx = 0; 5310 int ret; 5311 5312 /* Get physical address of idx que buf */ 5313 ret = hns_roce_mtr_find(hr_dev, &idx_que->mtr, 0, mtts_idx, 5314 ARRAY_SIZE(mtts_idx), &dma_handle_idx); 5315 if (ret < 1) { 5316 ibdev_err(ibdev, "failed to find mtr for SRQ idx, ret = %d.\n", 5317 ret); 5318 return -ENOBUFS; 5319 } 5320 5321 hr_reg_write(ctx, SRQC_IDX_HOP_NUM, 5322 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, srq->wqe_cnt)); 5323 5324 hr_reg_write(ctx, SRQC_IDX_BT_BA_L, dma_handle_idx >> DMA_IDX_SHIFT); 5325 hr_reg_write(ctx, SRQC_IDX_BT_BA_H, 5326 upper_32_bits(dma_handle_idx >> DMA_IDX_SHIFT)); 5327 5328 hr_reg_write(ctx, SRQC_IDX_BA_PG_SZ, 5329 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.ba_pg_shift)); 5330 hr_reg_write(ctx, SRQC_IDX_BUF_PG_SZ, 5331 to_hr_hw_page_shift(idx_que->mtr.hem_cfg.buf_pg_shift)); 5332 5333 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_L, 5334 to_hr_hw_page_addr(mtts_idx[0])); 5335 hr_reg_write(ctx, SRQC_IDX_CUR_BLK_ADDR_H, 5336 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 5337 5338 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_L, 5339 to_hr_hw_page_addr(mtts_idx[1])); 5340 hr_reg_write(ctx, SRQC_IDX_NXT_BLK_ADDR_H, 5341 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 5342 5343 return 0; 5344 } 5345 5346 static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) 5347 { 5348 struct ib_device *ibdev = srq->ibsrq.device; 5349 struct hns_roce_dev *hr_dev = to_hr_dev(ibdev); 5350 struct hns_roce_srq_context *ctx = mb_buf; 5351 u64 mtts_wqe[MTT_MIN_COUNT] = {}; 5352 dma_addr_t dma_handle_wqe = 0; 5353 int ret; 5354 5355 memset(ctx, 0, sizeof(*ctx)); 5356 5357 /* Get the physical address of srq buf */ 5358 ret = hns_roce_mtr_find(hr_dev, &srq->buf_mtr, 0, mtts_wqe, 5359 ARRAY_SIZE(mtts_wqe), &dma_handle_wqe); 5360 if (ret < 1) { 5361 ibdev_err(ibdev, "failed to find mtr for SRQ WQE, ret = %d.\n", 5362 ret); 5363 return -ENOBUFS; 5364 } 5365 5366 hr_reg_write(ctx, SRQC_SRQ_ST, 1); 5367 hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, 5368 srq->ibsrq.srq_type == IB_SRQT_XRC); 5369 hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); 5370 hr_reg_write(ctx, SRQC_SRQN, srq->srqn); 5371 hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); 5372 hr_reg_write(ctx, SRQC_XRC_CQN, srq->cqn); 5373 hr_reg_write(ctx, SRQC_SHIFT, ilog2(srq->wqe_cnt)); 5374 hr_reg_write(ctx, SRQC_RQWS, 5375 srq->max_gs <= 0 ? 0 : fls(srq->max_gs - 1)); 5376 5377 hr_reg_write(ctx, SRQC_WQE_HOP_NUM, 5378 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 5379 srq->wqe_cnt)); 5380 5381 hr_reg_write(ctx, SRQC_WQE_BT_BA_L, dma_handle_wqe >> DMA_WQE_SHIFT); 5382 hr_reg_write(ctx, SRQC_WQE_BT_BA_H, 5383 upper_32_bits(dma_handle_wqe >> DMA_WQE_SHIFT)); 5384 5385 hr_reg_write(ctx, SRQC_WQE_BA_PG_SZ, 5386 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 5387 hr_reg_write(ctx, SRQC_WQE_BUF_PG_SZ, 5388 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 5389 5390 return hns_roce_v2_write_srqc_index_queue(srq, ctx); 5391 } 5392 5393 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 5394 struct ib_srq_attr *srq_attr, 5395 enum ib_srq_attr_mask srq_attr_mask, 5396 struct ib_udata *udata) 5397 { 5398 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5399 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5400 struct hns_roce_srq_context *srq_context; 5401 struct hns_roce_srq_context *srqc_mask; 5402 struct hns_roce_cmd_mailbox *mailbox; 5403 int ret; 5404 5405 /* Resizing SRQs is not supported yet */ 5406 if (srq_attr_mask & IB_SRQ_MAX_WR) 5407 return -EINVAL; 5408 5409 if (srq_attr_mask & IB_SRQ_LIMIT) { 5410 if (srq_attr->srq_limit > srq->wqe_cnt) 5411 return -EINVAL; 5412 5413 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5414 if (IS_ERR(mailbox)) 5415 return PTR_ERR(mailbox); 5416 5417 srq_context = mailbox->buf; 5418 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5419 5420 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5421 5422 hr_reg_write(srq_context, SRQC_LIMIT_WL, srq_attr->srq_limit); 5423 hr_reg_clear(srqc_mask, SRQC_LIMIT_WL); 5424 5425 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5426 HNS_ROCE_CMD_MODIFY_SRQC, 5427 HNS_ROCE_CMD_TIMEOUT_MSECS); 5428 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5429 if (ret) { 5430 ibdev_err(&hr_dev->ib_dev, 5431 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5432 ret); 5433 return ret; 5434 } 5435 } 5436 5437 return 0; 5438 } 5439 5440 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5441 { 5442 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5443 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5444 struct hns_roce_srq_context *srq_context; 5445 struct hns_roce_cmd_mailbox *mailbox; 5446 int ret; 5447 5448 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5449 if (IS_ERR(mailbox)) 5450 return PTR_ERR(mailbox); 5451 5452 srq_context = mailbox->buf; 5453 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5454 HNS_ROCE_CMD_QUERY_SRQC, 5455 HNS_ROCE_CMD_TIMEOUT_MSECS); 5456 if (ret) { 5457 ibdev_err(&hr_dev->ib_dev, 5458 "failed to process cmd of querying SRQ, ret = %d.\n", 5459 ret); 5460 goto out; 5461 } 5462 5463 attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL); 5464 attr->max_wr = srq->wqe_cnt; 5465 attr->max_sge = srq->max_gs - srq->rsv_sge; 5466 5467 out: 5468 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5469 return ret; 5470 } 5471 5472 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5473 { 5474 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5475 struct hns_roce_v2_cq_context *cq_context; 5476 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5477 struct hns_roce_v2_cq_context *cqc_mask; 5478 struct hns_roce_cmd_mailbox *mailbox; 5479 int ret; 5480 5481 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5482 if (IS_ERR(mailbox)) 5483 return PTR_ERR(mailbox); 5484 5485 cq_context = mailbox->buf; 5486 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5487 5488 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5489 5490 hr_reg_write(cq_context, CQC_CQ_MAX_CNT, cq_count); 5491 hr_reg_clear(cqc_mask, CQC_CQ_MAX_CNT); 5492 hr_reg_write(cq_context, CQC_CQ_PERIOD, cq_period); 5493 hr_reg_clear(cqc_mask, CQC_CQ_PERIOD); 5494 5495 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5496 HNS_ROCE_CMD_MODIFY_CQC, 5497 HNS_ROCE_CMD_TIMEOUT_MSECS); 5498 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5499 if (ret) 5500 ibdev_err(&hr_dev->ib_dev, 5501 "failed to process cmd when modifying CQ, ret = %d.\n", 5502 ret); 5503 5504 return ret; 5505 } 5506 5507 static void hns_roce_irq_work_handle(struct work_struct *work) 5508 { 5509 struct hns_roce_work *irq_work = 5510 container_of(work, struct hns_roce_work, work); 5511 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5512 5513 switch (irq_work->event_type) { 5514 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5515 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5516 break; 5517 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5518 ibdev_warn(ibdev, "Path migration failed.\n"); 5519 break; 5520 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5521 break; 5522 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5523 ibdev_warn(ibdev, "Send queue drained.\n"); 5524 break; 5525 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5526 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5527 irq_work->queue_num, irq_work->sub_type); 5528 break; 5529 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5530 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5531 irq_work->queue_num); 5532 break; 5533 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5534 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5535 irq_work->queue_num, irq_work->sub_type); 5536 break; 5537 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5538 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5539 break; 5540 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5541 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5542 break; 5543 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5544 ibdev_err(ibdev, "SRQ catas error.\n"); 5545 break; 5546 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5547 ibdev_err(ibdev, "CQ 0x%x access err.\n", irq_work->queue_num); 5548 break; 5549 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5550 ibdev_warn(ibdev, "CQ 0x%x overflow\n", irq_work->queue_num); 5551 break; 5552 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5553 ibdev_warn(ibdev, "DB overflow.\n"); 5554 break; 5555 case HNS_ROCE_EVENT_TYPE_FLR: 5556 ibdev_warn(ibdev, "Function level reset.\n"); 5557 break; 5558 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5559 ibdev_err(ibdev, "xrc domain violation error.\n"); 5560 break; 5561 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5562 ibdev_err(ibdev, "invalid xrceth error.\n"); 5563 break; 5564 default: 5565 break; 5566 } 5567 5568 kfree(irq_work); 5569 } 5570 5571 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5572 struct hns_roce_eq *eq, u32 queue_num) 5573 { 5574 struct hns_roce_work *irq_work; 5575 5576 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5577 if (!irq_work) 5578 return; 5579 5580 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5581 irq_work->hr_dev = hr_dev; 5582 irq_work->event_type = eq->event_type; 5583 irq_work->sub_type = eq->sub_type; 5584 irq_work->queue_num = queue_num; 5585 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5586 } 5587 5588 static void update_eq_db(struct hns_roce_eq *eq) 5589 { 5590 struct hns_roce_dev *hr_dev = eq->hr_dev; 5591 struct hns_roce_v2_db eq_db = {}; 5592 5593 if (eq->type_flag == HNS_ROCE_AEQ) { 5594 hr_reg_write(&eq_db, EQ_DB_CMD, 5595 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5596 HNS_ROCE_EQ_DB_CMD_AEQ : 5597 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5598 } else { 5599 hr_reg_write(&eq_db, EQ_DB_TAG, eq->eqn); 5600 5601 hr_reg_write(&eq_db, EQ_DB_CMD, 5602 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5603 HNS_ROCE_EQ_DB_CMD_CEQ : 5604 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5605 } 5606 5607 hr_reg_write(&eq_db, EQ_DB_CI, eq->cons_index); 5608 5609 hns_roce_write64(hr_dev, (__le32 *)&eq_db, eq->db_reg); 5610 } 5611 5612 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5613 { 5614 struct hns_roce_aeqe *aeqe; 5615 5616 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5617 (eq->cons_index & (eq->entries - 1)) * 5618 eq->eqe_size); 5619 5620 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5621 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5622 } 5623 5624 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5625 struct hns_roce_eq *eq) 5626 { 5627 struct device *dev = hr_dev->dev; 5628 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5629 int aeqe_found = 0; 5630 int event_type; 5631 u32 queue_num; 5632 int sub_type; 5633 5634 while (aeqe) { 5635 /* Make sure we read AEQ entry after we have checked the 5636 * ownership bit 5637 */ 5638 dma_rmb(); 5639 5640 event_type = roce_get_field(aeqe->asyn, 5641 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5642 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5643 sub_type = roce_get_field(aeqe->asyn, 5644 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5645 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5646 queue_num = roce_get_field(aeqe->event.queue_event.num, 5647 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5648 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5649 5650 switch (event_type) { 5651 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5652 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5653 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5654 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5655 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5656 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5657 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5658 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5659 case HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION: 5660 case HNS_ROCE_EVENT_TYPE_INVALID_XRCETH: 5661 hns_roce_qp_event(hr_dev, queue_num, event_type); 5662 break; 5663 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5664 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5665 hns_roce_srq_event(hr_dev, queue_num, event_type); 5666 break; 5667 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5668 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5669 hns_roce_cq_event(hr_dev, queue_num, event_type); 5670 break; 5671 case HNS_ROCE_EVENT_TYPE_MB: 5672 hns_roce_cmd_event(hr_dev, 5673 le16_to_cpu(aeqe->event.cmd.token), 5674 aeqe->event.cmd.status, 5675 le64_to_cpu(aeqe->event.cmd.out_param)); 5676 break; 5677 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5678 case HNS_ROCE_EVENT_TYPE_FLR: 5679 break; 5680 default: 5681 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5682 event_type, eq->eqn, eq->cons_index); 5683 break; 5684 } 5685 5686 eq->event_type = event_type; 5687 eq->sub_type = sub_type; 5688 ++eq->cons_index; 5689 aeqe_found = 1; 5690 5691 hns_roce_v2_init_irq_work(hr_dev, eq, queue_num); 5692 5693 aeqe = next_aeqe_sw_v2(eq); 5694 } 5695 5696 update_eq_db(eq); 5697 return aeqe_found; 5698 } 5699 5700 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5701 { 5702 struct hns_roce_ceqe *ceqe; 5703 5704 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5705 (eq->cons_index & (eq->entries - 1)) * 5706 eq->eqe_size); 5707 5708 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5709 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5710 } 5711 5712 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5713 struct hns_roce_eq *eq) 5714 { 5715 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5716 int ceqe_found = 0; 5717 u32 cqn; 5718 5719 while (ceqe) { 5720 /* Make sure we read CEQ entry after we have checked the 5721 * ownership bit 5722 */ 5723 dma_rmb(); 5724 5725 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5726 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5727 5728 hns_roce_cq_completion(hr_dev, cqn); 5729 5730 ++eq->cons_index; 5731 ceqe_found = 1; 5732 5733 ceqe = next_ceqe_sw_v2(eq); 5734 } 5735 5736 update_eq_db(eq); 5737 5738 return ceqe_found; 5739 } 5740 5741 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5742 { 5743 struct hns_roce_eq *eq = eq_ptr; 5744 struct hns_roce_dev *hr_dev = eq->hr_dev; 5745 int int_work; 5746 5747 if (eq->type_flag == HNS_ROCE_CEQ) 5748 /* Completion event interrupt */ 5749 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5750 else 5751 /* Asychronous event interrupt */ 5752 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5753 5754 return IRQ_RETVAL(int_work); 5755 } 5756 5757 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5758 { 5759 struct hns_roce_dev *hr_dev = dev_id; 5760 struct device *dev = hr_dev->dev; 5761 int int_work = 0; 5762 u32 int_st; 5763 u32 int_en; 5764 5765 /* Abnormal interrupt */ 5766 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5767 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5768 5769 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5770 struct pci_dev *pdev = hr_dev->pci_dev; 5771 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5772 const struct hnae3_ae_ops *ops = ae_dev->ops; 5773 5774 dev_err(dev, "AEQ overflow!\n"); 5775 5776 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5777 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5778 5779 /* Set reset level for reset_event() */ 5780 if (ops->set_default_reset_request) 5781 ops->set_default_reset_request(ae_dev, 5782 HNAE3_FUNC_RESET); 5783 if (ops->reset_event) 5784 ops->reset_event(pdev, NULL); 5785 5786 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5787 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5788 5789 int_work = 1; 5790 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) { 5791 dev_err(dev, "RAS interrupt!\n"); 5792 5793 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S; 5794 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5795 5796 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5797 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5798 5799 int_work = 1; 5800 } else { 5801 dev_err(dev, "There is no abnormal irq found!\n"); 5802 } 5803 5804 return IRQ_RETVAL(int_work); 5805 } 5806 5807 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5808 int eq_num, u32 enable_flag) 5809 { 5810 int i; 5811 5812 for (i = 0; i < eq_num; i++) 5813 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5814 i * EQ_REG_OFFSET, enable_flag); 5815 5816 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, enable_flag); 5817 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag); 5818 } 5819 5820 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5821 { 5822 struct device *dev = hr_dev->dev; 5823 int ret; 5824 5825 if (eqn < hr_dev->caps.num_comp_vectors) 5826 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5827 0, HNS_ROCE_CMD_DESTROY_CEQC, 5828 HNS_ROCE_CMD_TIMEOUT_MSECS); 5829 else 5830 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5831 0, HNS_ROCE_CMD_DESTROY_AEQC, 5832 HNS_ROCE_CMD_TIMEOUT_MSECS); 5833 if (ret) 5834 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5835 } 5836 5837 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5838 { 5839 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5840 } 5841 5842 static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5843 { 5844 eq->db_reg = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5845 eq->cons_index = 0; 5846 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5847 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5848 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5849 eq->shift = ilog2((unsigned int)eq->entries); 5850 } 5851 5852 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5853 void *mb_buf) 5854 { 5855 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5856 struct hns_roce_eq_context *eqc; 5857 u64 bt_ba = 0; 5858 int count; 5859 5860 eqc = mb_buf; 5861 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5862 5863 init_eq_config(hr_dev, eq); 5864 5865 /* if not multi-hop, eqe buffer only use one trunk */ 5866 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5867 &bt_ba); 5868 if (count < 1) { 5869 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5870 return -ENOBUFS; 5871 } 5872 5873 hr_reg_write(eqc, EQC_EQ_ST, HNS_ROCE_V2_EQ_STATE_VALID); 5874 hr_reg_write(eqc, EQC_EQE_HOP_NUM, eq->hop_num); 5875 hr_reg_write(eqc, EQC_OVER_IGNORE, eq->over_ignore); 5876 hr_reg_write(eqc, EQC_COALESCE, eq->coalesce); 5877 hr_reg_write(eqc, EQC_ARM_ST, eq->arm_st); 5878 hr_reg_write(eqc, EQC_EQN, eq->eqn); 5879 hr_reg_write(eqc, EQC_EQE_CNT, HNS_ROCE_EQ_INIT_EQE_CNT); 5880 hr_reg_write(eqc, EQC_EQE_BA_PG_SZ, 5881 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5882 hr_reg_write(eqc, EQC_EQE_BUF_PG_SZ, 5883 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5884 hr_reg_write(eqc, EQC_EQ_PROD_INDX, HNS_ROCE_EQ_INIT_PROD_IDX); 5885 hr_reg_write(eqc, EQC_EQ_MAX_CNT, eq->eq_max_cnt); 5886 5887 hr_reg_write(eqc, EQC_EQ_PERIOD, eq->eq_period); 5888 hr_reg_write(eqc, EQC_EQE_REPORT_TIMER, HNS_ROCE_EQ_INIT_REPORT_TIMER); 5889 hr_reg_write(eqc, EQC_EQE_BA_L, bt_ba >> 3); 5890 hr_reg_write(eqc, EQC_EQE_BA_H, bt_ba >> 35); 5891 hr_reg_write(eqc, EQC_SHIFT, eq->shift); 5892 hr_reg_write(eqc, EQC_MSI_INDX, HNS_ROCE_EQ_INIT_MSI_IDX); 5893 hr_reg_write(eqc, EQC_CUR_EQE_BA_L, eqe_ba[0] >> 12); 5894 hr_reg_write(eqc, EQC_CUR_EQE_BA_M, eqe_ba[0] >> 28); 5895 hr_reg_write(eqc, EQC_CUR_EQE_BA_H, eqe_ba[0] >> 60); 5896 hr_reg_write(eqc, EQC_EQ_CONS_INDX, HNS_ROCE_EQ_INIT_CONS_IDX); 5897 hr_reg_write(eqc, EQC_NEX_EQE_BA_L, eqe_ba[1] >> 12); 5898 hr_reg_write(eqc, EQC_NEX_EQE_BA_H, eqe_ba[1] >> 44); 5899 hr_reg_write(eqc, EQC_EQE_SIZE, eq->eqe_size == HNS_ROCE_V3_EQE_SIZE); 5900 5901 return 0; 5902 } 5903 5904 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5905 { 5906 struct hns_roce_buf_attr buf_attr = {}; 5907 int err; 5908 5909 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5910 eq->hop_num = 0; 5911 else 5912 eq->hop_num = hr_dev->caps.eqe_hop_num; 5913 5914 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT; 5915 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5916 buf_attr.region[0].hopnum = eq->hop_num; 5917 buf_attr.region_count = 1; 5918 5919 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5920 hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT, NULL, 5921 0); 5922 if (err) 5923 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5924 5925 return err; 5926 } 5927 5928 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5929 struct hns_roce_eq *eq, 5930 unsigned int eq_cmd) 5931 { 5932 struct hns_roce_cmd_mailbox *mailbox; 5933 int ret; 5934 5935 /* Allocate mailbox memory */ 5936 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5937 if (IS_ERR_OR_NULL(mailbox)) 5938 return -ENOMEM; 5939 5940 ret = alloc_eq_buf(hr_dev, eq); 5941 if (ret) 5942 goto free_cmd_mbox; 5943 5944 ret = config_eqc(hr_dev, eq, mailbox->buf); 5945 if (ret) 5946 goto err_cmd_mbox; 5947 5948 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5949 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5950 if (ret) { 5951 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5952 goto err_cmd_mbox; 5953 } 5954 5955 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5956 5957 return 0; 5958 5959 err_cmd_mbox: 5960 free_eq_buf(hr_dev, eq); 5961 5962 free_cmd_mbox: 5963 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5964 5965 return ret; 5966 } 5967 5968 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5969 int comp_num, int aeq_num, int other_num) 5970 { 5971 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5972 int i, j; 5973 int ret; 5974 5975 for (i = 0; i < irq_num; i++) { 5976 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5977 GFP_KERNEL); 5978 if (!hr_dev->irq_names[i]) { 5979 ret = -ENOMEM; 5980 goto err_kzalloc_failed; 5981 } 5982 } 5983 5984 /* irq contains: abnormal + AEQ + CEQ */ 5985 for (j = 0; j < other_num; j++) 5986 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5987 "hns-abn-%d", j); 5988 5989 for (j = other_num; j < (other_num + aeq_num); j++) 5990 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5991 "hns-aeq-%d", j - other_num); 5992 5993 for (j = (other_num + aeq_num); j < irq_num; j++) 5994 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5995 "hns-ceq-%d", j - other_num - aeq_num); 5996 5997 for (j = 0; j < irq_num; j++) { 5998 if (j < other_num) 5999 ret = request_irq(hr_dev->irq[j], 6000 hns_roce_v2_msix_interrupt_abn, 6001 0, hr_dev->irq_names[j], hr_dev); 6002 6003 else if (j < (other_num + comp_num)) 6004 ret = request_irq(eq_table->eq[j - other_num].irq, 6005 hns_roce_v2_msix_interrupt_eq, 6006 0, hr_dev->irq_names[j + aeq_num], 6007 &eq_table->eq[j - other_num]); 6008 else 6009 ret = request_irq(eq_table->eq[j - other_num].irq, 6010 hns_roce_v2_msix_interrupt_eq, 6011 0, hr_dev->irq_names[j - comp_num], 6012 &eq_table->eq[j - other_num]); 6013 if (ret) { 6014 dev_err(hr_dev->dev, "Request irq error!\n"); 6015 goto err_request_failed; 6016 } 6017 } 6018 6019 return 0; 6020 6021 err_request_failed: 6022 for (j -= 1; j >= 0; j--) 6023 if (j < other_num) 6024 free_irq(hr_dev->irq[j], hr_dev); 6025 else 6026 free_irq(eq_table->eq[j - other_num].irq, 6027 &eq_table->eq[j - other_num]); 6028 6029 err_kzalloc_failed: 6030 for (i -= 1; i >= 0; i--) 6031 kfree(hr_dev->irq_names[i]); 6032 6033 return ret; 6034 } 6035 6036 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 6037 { 6038 int irq_num; 6039 int eq_num; 6040 int i; 6041 6042 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6043 irq_num = eq_num + hr_dev->caps.num_other_vectors; 6044 6045 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 6046 free_irq(hr_dev->irq[i], hr_dev); 6047 6048 for (i = 0; i < eq_num; i++) 6049 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 6050 6051 for (i = 0; i < irq_num; i++) 6052 kfree(hr_dev->irq_names[i]); 6053 } 6054 6055 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 6056 { 6057 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6058 struct device *dev = hr_dev->dev; 6059 struct hns_roce_eq *eq; 6060 unsigned int eq_cmd; 6061 int irq_num; 6062 int eq_num; 6063 int other_num; 6064 int comp_num; 6065 int aeq_num; 6066 int i; 6067 int ret; 6068 6069 other_num = hr_dev->caps.num_other_vectors; 6070 comp_num = hr_dev->caps.num_comp_vectors; 6071 aeq_num = hr_dev->caps.num_aeq_vectors; 6072 6073 eq_num = comp_num + aeq_num; 6074 irq_num = eq_num + other_num; 6075 6076 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 6077 if (!eq_table->eq) 6078 return -ENOMEM; 6079 6080 /* create eq */ 6081 for (i = 0; i < eq_num; i++) { 6082 eq = &eq_table->eq[i]; 6083 eq->hr_dev = hr_dev; 6084 eq->eqn = i; 6085 if (i < comp_num) { 6086 /* CEQ */ 6087 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 6088 eq->type_flag = HNS_ROCE_CEQ; 6089 eq->entries = hr_dev->caps.ceqe_depth; 6090 eq->eqe_size = hr_dev->caps.ceqe_size; 6091 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 6092 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 6093 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 6094 } else { 6095 /* AEQ */ 6096 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 6097 eq->type_flag = HNS_ROCE_AEQ; 6098 eq->entries = hr_dev->caps.aeqe_depth; 6099 eq->eqe_size = hr_dev->caps.aeqe_size; 6100 eq->irq = hr_dev->irq[i - comp_num + other_num]; 6101 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 6102 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 6103 } 6104 6105 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 6106 if (ret) { 6107 dev_err(dev, "failed to create eq.\n"); 6108 goto err_create_eq_fail; 6109 } 6110 } 6111 6112 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 6113 if (!hr_dev->irq_workq) { 6114 dev_err(dev, "failed to create irq workqueue.\n"); 6115 ret = -ENOMEM; 6116 goto err_create_eq_fail; 6117 } 6118 6119 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, aeq_num, 6120 other_num); 6121 if (ret) { 6122 dev_err(dev, "failed to request irq.\n"); 6123 goto err_request_irq_fail; 6124 } 6125 6126 /* enable irq */ 6127 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 6128 6129 return 0; 6130 6131 err_request_irq_fail: 6132 destroy_workqueue(hr_dev->irq_workq); 6133 6134 err_create_eq_fail: 6135 for (i -= 1; i >= 0; i--) 6136 free_eq_buf(hr_dev, &eq_table->eq[i]); 6137 kfree(eq_table->eq); 6138 6139 return ret; 6140 } 6141 6142 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 6143 { 6144 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 6145 int eq_num; 6146 int i; 6147 6148 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 6149 6150 /* Disable irq */ 6151 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 6152 6153 __hns_roce_free_irq(hr_dev); 6154 destroy_workqueue(hr_dev->irq_workq); 6155 6156 for (i = 0; i < eq_num; i++) { 6157 hns_roce_v2_destroy_eqc(hr_dev, i); 6158 6159 free_eq_buf(hr_dev, &eq_table->eq[i]); 6160 } 6161 6162 kfree(eq_table->eq); 6163 } 6164 6165 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 6166 .query_cqc_info = hns_roce_v2_query_cqc_info, 6167 }; 6168 6169 static const struct ib_device_ops hns_roce_v2_dev_ops = { 6170 .destroy_qp = hns_roce_v2_destroy_qp, 6171 .modify_cq = hns_roce_v2_modify_cq, 6172 .poll_cq = hns_roce_v2_poll_cq, 6173 .post_recv = hns_roce_v2_post_recv, 6174 .post_send = hns_roce_v2_post_send, 6175 .query_qp = hns_roce_v2_query_qp, 6176 .req_notify_cq = hns_roce_v2_req_notify_cq, 6177 }; 6178 6179 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 6180 .modify_srq = hns_roce_v2_modify_srq, 6181 .post_srq_recv = hns_roce_v2_post_srq_recv, 6182 .query_srq = hns_roce_v2_query_srq, 6183 }; 6184 6185 static const struct hns_roce_hw hns_roce_hw_v2 = { 6186 .cmq_init = hns_roce_v2_cmq_init, 6187 .cmq_exit = hns_roce_v2_cmq_exit, 6188 .hw_profile = hns_roce_v2_profile, 6189 .hw_init = hns_roce_v2_init, 6190 .hw_exit = hns_roce_v2_exit, 6191 .post_mbox = v2_post_mbox, 6192 .poll_mbox_done = v2_poll_mbox_done, 6193 .chk_mbox_avail = v2_chk_mbox_is_avail, 6194 .set_gid = hns_roce_v2_set_gid, 6195 .set_mac = hns_roce_v2_set_mac, 6196 .write_mtpt = hns_roce_v2_write_mtpt, 6197 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 6198 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 6199 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 6200 .write_cqc = hns_roce_v2_write_cqc, 6201 .set_hem = hns_roce_v2_set_hem, 6202 .clear_hem = hns_roce_v2_clear_hem, 6203 .modify_qp = hns_roce_v2_modify_qp, 6204 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 6205 .init_eq = hns_roce_v2_init_eq_table, 6206 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 6207 .write_srqc = hns_roce_v2_write_srqc, 6208 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 6209 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 6210 }; 6211 6212 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 6213 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 6214 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 6215 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 6216 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 6217 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 6218 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 6219 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 6220 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 6221 /* required last entry */ 6222 {0, } 6223 }; 6224 6225 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 6226 6227 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 6228 struct hnae3_handle *handle) 6229 { 6230 struct hns_roce_v2_priv *priv = hr_dev->priv; 6231 const struct pci_device_id *id; 6232 int i; 6233 6234 hr_dev->pci_dev = handle->pdev; 6235 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev); 6236 hr_dev->is_vf = id->driver_data; 6237 hr_dev->dev = &handle->pdev->dev; 6238 hr_dev->hw = &hns_roce_hw_v2; 6239 hr_dev->dfx = &hns_roce_dfx_hw_v2; 6240 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 6241 hr_dev->odb_offset = hr_dev->sdb_offset; 6242 6243 /* Get info from NIC driver. */ 6244 hr_dev->reg_base = handle->rinfo.roce_io_base; 6245 hr_dev->mem_base = handle->rinfo.roce_mem_base; 6246 hr_dev->caps.num_ports = 1; 6247 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 6248 hr_dev->iboe.phy_port[0] = 0; 6249 6250 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 6251 hr_dev->iboe.netdevs[0]->dev_addr); 6252 6253 for (i = 0; i < handle->rinfo.num_vectors; i++) 6254 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 6255 i + handle->rinfo.base_vector); 6256 6257 /* cmd issue mode: 0 is poll, 1 is event */ 6258 hr_dev->cmd_mod = 1; 6259 hr_dev->loop_idc = 0; 6260 6261 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 6262 priv->handle = handle; 6263 } 6264 6265 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6266 { 6267 struct hns_roce_dev *hr_dev; 6268 int ret; 6269 6270 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6271 if (!hr_dev) 6272 return -ENOMEM; 6273 6274 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6275 if (!hr_dev->priv) { 6276 ret = -ENOMEM; 6277 goto error_failed_kzalloc; 6278 } 6279 6280 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6281 6282 ret = hns_roce_init(hr_dev); 6283 if (ret) { 6284 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6285 goto error_failed_get_cfg; 6286 } 6287 6288 handle->priv = hr_dev; 6289 6290 return 0; 6291 6292 error_failed_get_cfg: 6293 kfree(hr_dev->priv); 6294 6295 error_failed_kzalloc: 6296 ib_dealloc_device(&hr_dev->ib_dev); 6297 6298 return ret; 6299 } 6300 6301 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6302 bool reset) 6303 { 6304 struct hns_roce_dev *hr_dev = handle->priv; 6305 6306 if (!hr_dev) 6307 return; 6308 6309 handle->priv = NULL; 6310 6311 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6312 hns_roce_handle_device_err(hr_dev); 6313 6314 hns_roce_exit(hr_dev); 6315 kfree(hr_dev->priv); 6316 ib_dealloc_device(&hr_dev->ib_dev); 6317 } 6318 6319 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6320 { 6321 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6322 const struct pci_device_id *id; 6323 struct device *dev = &handle->pdev->dev; 6324 int ret; 6325 6326 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6327 6328 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6329 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6330 goto reset_chk_err; 6331 } 6332 6333 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6334 if (!id) 6335 return 0; 6336 6337 if (id->driver_data && handle->pdev->revision < PCI_REVISION_ID_HIP09) 6338 return 0; 6339 6340 ret = __hns_roce_hw_v2_init_instance(handle); 6341 if (ret) { 6342 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6343 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6344 if (ops->ae_dev_resetting(handle) || 6345 ops->get_hw_reset_stat(handle)) 6346 goto reset_chk_err; 6347 else 6348 return ret; 6349 } 6350 6351 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6352 6353 return 0; 6354 6355 reset_chk_err: 6356 dev_err(dev, "Device is busy in resetting state.\n" 6357 "please retry later.\n"); 6358 6359 return -EBUSY; 6360 } 6361 6362 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6363 bool reset) 6364 { 6365 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6366 return; 6367 6368 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6369 6370 __hns_roce_hw_v2_uninit_instance(handle, reset); 6371 6372 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6373 } 6374 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6375 { 6376 struct hns_roce_dev *hr_dev; 6377 6378 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6379 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6380 return 0; 6381 } 6382 6383 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6384 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6385 6386 hr_dev = handle->priv; 6387 if (!hr_dev) 6388 return 0; 6389 6390 hr_dev->is_reset = true; 6391 hr_dev->active = false; 6392 hr_dev->dis_db = true; 6393 6394 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6395 6396 return 0; 6397 } 6398 6399 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6400 { 6401 struct device *dev = &handle->pdev->dev; 6402 int ret; 6403 6404 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6405 &handle->rinfo.state)) { 6406 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6407 return 0; 6408 } 6409 6410 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6411 6412 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6413 ret = __hns_roce_hw_v2_init_instance(handle); 6414 if (ret) { 6415 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6416 * callback function, RoCE Engine reinitialize. If RoCE reinit 6417 * failed, we should inform NIC driver. 6418 */ 6419 handle->priv = NULL; 6420 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6421 } else { 6422 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6423 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6424 } 6425 6426 return ret; 6427 } 6428 6429 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6430 { 6431 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6432 return 0; 6433 6434 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6435 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6436 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6437 __hns_roce_hw_v2_uninit_instance(handle, false); 6438 6439 return 0; 6440 } 6441 6442 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6443 enum hnae3_reset_notify_type type) 6444 { 6445 int ret = 0; 6446 6447 switch (type) { 6448 case HNAE3_DOWN_CLIENT: 6449 ret = hns_roce_hw_v2_reset_notify_down(handle); 6450 break; 6451 case HNAE3_INIT_CLIENT: 6452 ret = hns_roce_hw_v2_reset_notify_init(handle); 6453 break; 6454 case HNAE3_UNINIT_CLIENT: 6455 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6456 break; 6457 default: 6458 break; 6459 } 6460 6461 return ret; 6462 } 6463 6464 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6465 .init_instance = hns_roce_hw_v2_init_instance, 6466 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6467 .reset_notify = hns_roce_hw_v2_reset_notify, 6468 }; 6469 6470 static struct hnae3_client hns_roce_hw_v2_client = { 6471 .name = "hns_roce_hw_v2", 6472 .type = HNAE3_CLIENT_ROCE, 6473 .ops = &hns_roce_hw_v2_ops, 6474 }; 6475 6476 static int __init hns_roce_hw_v2_init(void) 6477 { 6478 return hnae3_register_client(&hns_roce_hw_v2_client); 6479 } 6480 6481 static void __exit hns_roce_hw_v2_exit(void) 6482 { 6483 hnae3_unregister_client(&hns_roce_hw_v2_client); 6484 } 6485 6486 module_init(hns_roce_hw_v2_init); 6487 module_exit(hns_roce_hw_v2_exit); 6488 6489 MODULE_LICENSE("Dual BSD/GPL"); 6490 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6491 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6492 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6493 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6494