1 /* 2 * Copyright (c) 2016-2017 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/acpi.h> 34 #include <linux/etherdevice.h> 35 #include <linux/interrupt.h> 36 #include <linux/kernel.h> 37 #include <linux/types.h> 38 #include <net/addrconf.h> 39 #include <rdma/ib_addr.h> 40 #include <rdma/ib_cache.h> 41 #include <rdma/ib_umem.h> 42 #include <rdma/uverbs_ioctl.h> 43 44 #include "hnae3.h" 45 #include "hns_roce_common.h" 46 #include "hns_roce_device.h" 47 #include "hns_roce_cmd.h" 48 #include "hns_roce_hem.h" 49 #include "hns_roce_hw_v2.h" 50 51 static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, 52 struct ib_sge *sg) 53 { 54 dseg->lkey = cpu_to_le32(sg->lkey); 55 dseg->addr = cpu_to_le64(sg->addr); 56 dseg->len = cpu_to_le32(sg->length); 57 } 58 59 /* 60 * mapped-value = 1 + real-value 61 * The hns wr opcode real value is start from 0, In order to distinguish between 62 * initialized and uninitialized map values, we plus 1 to the actual value when 63 * defining the mapping, so that the validity can be identified by checking the 64 * mapped value is greater than 0. 65 */ 66 #define HR_OPC_MAP(ib_key, hr_key) \ 67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key 68 69 static const u32 hns_roce_op_code[] = { 70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), 71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), 72 HR_OPC_MAP(SEND, SEND), 73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), 74 HR_OPC_MAP(RDMA_READ, RDMA_READ), 75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), 76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), 77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), 78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV), 79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), 80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), 81 HR_OPC_MAP(REG_MR, FAST_REG_PMR), 82 }; 83 84 static u32 to_hr_opcode(u32 ib_opcode) 85 { 86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) 87 return HNS_ROCE_V2_WQE_OP_MASK; 88 89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : 90 HNS_ROCE_V2_WQE_OP_MASK; 91 } 92 93 static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 94 const struct ib_reg_wr *wr) 95 { 96 struct hns_roce_wqe_frmr_seg *fseg = 97 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 98 struct hns_roce_mr *mr = to_hr_mr(wr->mr); 99 u64 pbl_ba; 100 101 /* use ib_access_flags */ 102 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, 103 wr->access & IB_ACCESS_MW_BIND ? 1 : 0); 104 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, 105 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 106 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, 107 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); 108 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, 109 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 110 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, 111 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 112 113 /* Data structure reuse may lead to confusion */ 114 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba; 115 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba)); 116 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba)); 117 118 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); 119 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); 120 rc_sq_wqe->rkey = cpu_to_le32(wr->key); 121 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); 122 123 fseg->pbl_size = cpu_to_le32(mr->npages); 124 roce_set_field(fseg->mode_buf_pg_sz, 125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, 126 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, 127 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 128 roce_set_bit(fseg->mode_buf_pg_sz, 129 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); 130 } 131 132 static void set_atomic_seg(const struct ib_send_wr *wr, 133 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 134 unsigned int valid_num_sge) 135 { 136 struct hns_roce_v2_wqe_data_seg *dseg = 137 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 138 struct hns_roce_wqe_atomic_seg *aseg = 139 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg); 140 141 set_data_seg_v2(dseg, wr->sg_list); 142 143 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 144 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); 145 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); 146 } else { 147 aseg->fetchadd_swap_data = 148 cpu_to_le64(atomic_wr(wr)->compare_add); 149 aseg->cmp_data = 0; 150 } 151 152 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 153 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 154 } 155 156 static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr, 157 unsigned int *sge_ind, unsigned int valid_num_sge) 158 { 159 struct hns_roce_v2_wqe_data_seg *dseg; 160 unsigned int cnt = valid_num_sge; 161 struct ib_sge *sge = wr->sg_list; 162 unsigned int idx = *sge_ind; 163 164 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 165 cnt -= HNS_ROCE_SGE_IN_WQE; 166 sge += HNS_ROCE_SGE_IN_WQE; 167 } 168 169 while (cnt > 0) { 170 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1)); 171 set_data_seg_v2(dseg, sge); 172 idx++; 173 sge++; 174 cnt--; 175 } 176 177 *sge_ind = idx; 178 } 179 180 static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, 181 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, 182 unsigned int *sge_ind, 183 unsigned int valid_num_sge) 184 { 185 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 186 struct hns_roce_v2_wqe_data_seg *dseg = 187 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe); 188 struct ib_device *ibdev = &hr_dev->ib_dev; 189 struct hns_roce_qp *qp = to_hr_qp(ibqp); 190 void *wqe = dseg; 191 int j = 0; 192 int i; 193 194 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) { 195 if (unlikely(le32_to_cpu(rc_sq_wqe->msg_len) > 196 hr_dev->caps.max_sq_inline)) { 197 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal", 198 rc_sq_wqe->msg_len, 199 hr_dev->caps.max_sq_inline); 200 return -EINVAL; 201 } 202 203 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) { 204 ibdev_err(ibdev, "Not support inline data!\n"); 205 return -EINVAL; 206 } 207 208 for (i = 0; i < wr->num_sge; i++) { 209 memcpy(wqe, ((void *)wr->sg_list[i].addr), 210 wr->sg_list[i].length); 211 wqe += wr->sg_list[i].length; 212 } 213 214 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, 215 1); 216 } else { 217 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) { 218 for (i = 0; i < wr->num_sge; i++) { 219 if (likely(wr->sg_list[i].length)) { 220 set_data_seg_v2(dseg, wr->sg_list + i); 221 dseg++; 222 } 223 } 224 } else { 225 roce_set_field(rc_sq_wqe->byte_20, 226 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 227 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 228 (*sge_ind) & (qp->sge.sge_cnt - 1)); 229 230 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE; 231 i++) { 232 if (likely(wr->sg_list[i].length)) { 233 set_data_seg_v2(dseg, wr->sg_list + i); 234 dseg++; 235 j++; 236 } 237 } 238 239 set_extend_sge(qp, wr, sge_ind, valid_num_sge); 240 } 241 242 roce_set_field(rc_sq_wqe->byte_16, 243 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, 244 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 245 } 246 247 return 0; 248 } 249 250 static int check_send_valid(struct hns_roce_dev *hr_dev, 251 struct hns_roce_qp *hr_qp) 252 { 253 struct ib_device *ibdev = &hr_dev->ib_dev; 254 struct ib_qp *ibqp = &hr_qp->ibqp; 255 256 if (unlikely(ibqp->qp_type != IB_QPT_RC && 257 ibqp->qp_type != IB_QPT_GSI && 258 ibqp->qp_type != IB_QPT_UD)) { 259 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", 260 ibqp->qp_type); 261 return -EOPNOTSUPP; 262 } else if (unlikely(hr_qp->state == IB_QPS_RESET || 263 hr_qp->state == IB_QPS_INIT || 264 hr_qp->state == IB_QPS_RTR)) { 265 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n", 266 hr_qp->state); 267 return -EINVAL; 268 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { 269 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", 270 hr_dev->state); 271 return -EIO; 272 } 273 274 return 0; 275 } 276 277 static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, 278 unsigned int *sge_len) 279 { 280 unsigned int valid_num = 0; 281 unsigned int len = 0; 282 int i; 283 284 for (i = 0; i < wr->num_sge; i++) { 285 if (likely(wr->sg_list[i].length)) { 286 len += wr->sg_list[i].length; 287 valid_num++; 288 } 289 } 290 291 *sge_len = len; 292 return valid_num; 293 } 294 295 static inline int set_ud_wqe(struct hns_roce_qp *qp, 296 const struct ib_send_wr *wr, 297 void *wqe, unsigned int *sge_idx, 298 unsigned int owner_bit) 299 { 300 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); 301 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); 302 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; 303 unsigned int curr_idx = *sge_idx; 304 int valid_num_sge; 305 u32 msg_len = 0; 306 bool loopback; 307 u8 *smac; 308 309 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 310 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); 311 312 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, 313 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); 314 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, 315 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); 316 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, 317 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); 318 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, 319 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); 320 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, 321 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]); 322 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, 323 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]); 324 325 /* MAC loopback */ 326 smac = (u8 *)hr_dev->dev_addr[qp->port]; 327 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0; 328 329 roce_set_bit(ud_sq_wqe->byte_40, 330 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); 331 332 roce_set_field(ud_sq_wqe->byte_4, 333 V2_UD_SEND_WQE_BYTE_4_OPCODE_M, 334 V2_UD_SEND_WQE_BYTE_4_OPCODE_S, 335 HNS_ROCE_V2_WQE_OP_SEND); 336 337 ud_sq_wqe->msg_len = cpu_to_le32(msg_len); 338 339 switch (wr->opcode) { 340 case IB_WR_SEND_WITH_IMM: 341 case IB_WR_RDMA_WRITE_WITH_IMM: 342 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 343 break; 344 default: 345 ud_sq_wqe->immtdata = 0; 346 break; 347 } 348 349 /* Set sig attr */ 350 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, 351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 352 353 /* Set se attr */ 354 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, 355 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 356 357 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, 358 owner_bit); 359 360 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, 361 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); 362 363 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, 364 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); 365 366 roce_set_field(ud_sq_wqe->byte_20, 367 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, 368 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, 369 curr_idx & (qp->sge.sge_cnt - 1)); 370 371 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, 372 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); 373 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? 374 qp->qkey : ud_wr(wr)->remote_qkey); 375 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, 376 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); 377 378 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, 379 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); 380 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, 381 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); 382 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, 383 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); 384 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, 385 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); 386 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, 387 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); 388 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M, 389 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port); 390 391 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, 392 ah->av.vlan_en ? 1 : 0); 393 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, 394 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index); 395 396 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2); 397 398 set_extend_sge(qp, wr, &curr_idx, valid_num_sge); 399 400 *sge_idx = curr_idx; 401 402 return 0; 403 } 404 405 static inline int set_rc_wqe(struct hns_roce_qp *qp, 406 const struct ib_send_wr *wr, 407 void *wqe, unsigned int *sge_idx, 408 unsigned int owner_bit) 409 { 410 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; 411 unsigned int curr_idx = *sge_idx; 412 unsigned int valid_num_sge; 413 u32 msg_len = 0; 414 int ret = 0; 415 416 valid_num_sge = calc_wr_sge_num(wr, &msg_len); 417 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); 418 419 rc_sq_wqe->msg_len = cpu_to_le32(msg_len); 420 421 switch (wr->opcode) { 422 case IB_WR_SEND_WITH_IMM: 423 case IB_WR_RDMA_WRITE_WITH_IMM: 424 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); 425 break; 426 case IB_WR_SEND_WITH_INV: 427 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 428 break; 429 default: 430 rc_sq_wqe->immtdata = 0; 431 break; 432 } 433 434 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, 435 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); 436 437 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, 438 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); 439 440 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, 441 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); 442 443 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, 444 owner_bit); 445 446 switch (wr->opcode) { 447 case IB_WR_RDMA_READ: 448 case IB_WR_RDMA_WRITE: 449 case IB_WR_RDMA_WRITE_WITH_IMM: 450 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); 451 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); 452 break; 453 case IB_WR_LOCAL_INV: 454 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); 455 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); 456 break; 457 case IB_WR_REG_MR: 458 set_frmr_seg(rc_sq_wqe, reg_wr(wr)); 459 break; 460 case IB_WR_ATOMIC_CMP_AND_SWP: 461 case IB_WR_ATOMIC_FETCH_AND_ADD: 462 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); 463 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); 464 break; 465 default: 466 break; 467 } 468 469 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, 470 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, 471 to_hr_opcode(wr->opcode)); 472 473 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || 474 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) 475 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge); 476 else if (wr->opcode != IB_WR_REG_MR) 477 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, 478 &curr_idx, valid_num_sge); 479 480 *sge_idx = curr_idx; 481 482 return ret; 483 } 484 485 static inline void update_sq_db(struct hns_roce_dev *hr_dev, 486 struct hns_roce_qp *qp) 487 { 488 /* 489 * Hip08 hardware cannot flush the WQEs in SQ if the QP state 490 * gets into errored mode. Hence, as a workaround to this 491 * hardware limitation, driver needs to assist in flushing. But 492 * the flushing operation uses mailbox to convey the QP state to 493 * the hardware and which can sleep due to the mutex protection 494 * around the mailbox calls. Hence, use the deferred flush for 495 * now. 496 */ 497 if (qp->state == IB_QPS_ERR) { 498 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 499 init_flush_work(hr_dev, qp); 500 } else { 501 struct hns_roce_v2_db sq_db = {}; 502 503 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, 504 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); 505 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, 506 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); 507 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, 508 V2_DB_PARAMETER_IDX_S, qp->sq.head); 509 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, 510 V2_DB_PARAMETER_SL_S, qp->sl); 511 512 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l); 513 } 514 } 515 516 static int hns_roce_v2_post_send(struct ib_qp *ibqp, 517 const struct ib_send_wr *wr, 518 const struct ib_send_wr **bad_wr) 519 { 520 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 521 struct ib_device *ibdev = &hr_dev->ib_dev; 522 struct hns_roce_qp *qp = to_hr_qp(ibqp); 523 unsigned long flags = 0; 524 unsigned int owner_bit; 525 unsigned int sge_idx; 526 unsigned int wqe_idx; 527 void *wqe = NULL; 528 int nreq; 529 int ret; 530 531 spin_lock_irqsave(&qp->sq.lock, flags); 532 533 ret = check_send_valid(hr_dev, qp); 534 if (unlikely(ret)) { 535 *bad_wr = wr; 536 nreq = 0; 537 goto out; 538 } 539 540 sge_idx = qp->next_sge; 541 542 for (nreq = 0; wr; ++nreq, wr = wr->next) { 543 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 544 ret = -ENOMEM; 545 *bad_wr = wr; 546 goto out; 547 } 548 549 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); 550 551 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 552 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n", 553 wr->num_sge, qp->sq.max_gs); 554 ret = -EINVAL; 555 *bad_wr = wr; 556 goto out; 557 } 558 559 wqe = hns_roce_get_send_wqe(qp, wqe_idx); 560 qp->sq.wrid[wqe_idx] = wr->wr_id; 561 owner_bit = 562 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); 563 564 /* Corresponding to the QP type, wqe process separately */ 565 if (ibqp->qp_type == IB_QPT_GSI) 566 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); 567 else if (ibqp->qp_type == IB_QPT_RC) 568 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); 569 570 if (unlikely(ret)) { 571 *bad_wr = wr; 572 goto out; 573 } 574 } 575 576 out: 577 if (likely(nreq)) { 578 qp->sq.head += nreq; 579 qp->next_sge = sge_idx; 580 /* Memory barrier */ 581 wmb(); 582 update_sq_db(hr_dev, qp); 583 } 584 585 spin_unlock_irqrestore(&qp->sq.lock, flags); 586 587 return ret; 588 } 589 590 static int check_recv_valid(struct hns_roce_dev *hr_dev, 591 struct hns_roce_qp *hr_qp) 592 { 593 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) 594 return -EIO; 595 else if (hr_qp->state == IB_QPS_RESET) 596 return -EINVAL; 597 598 return 0; 599 } 600 601 static int hns_roce_v2_post_recv(struct ib_qp *ibqp, 602 const struct ib_recv_wr *wr, 603 const struct ib_recv_wr **bad_wr) 604 { 605 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 606 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 607 struct ib_device *ibdev = &hr_dev->ib_dev; 608 struct hns_roce_v2_wqe_data_seg *dseg; 609 struct hns_roce_rinl_sge *sge_list; 610 unsigned long flags; 611 void *wqe = NULL; 612 u32 wqe_idx; 613 int nreq; 614 int ret; 615 int i; 616 617 spin_lock_irqsave(&hr_qp->rq.lock, flags); 618 619 ret = check_recv_valid(hr_dev, hr_qp); 620 if (unlikely(ret)) { 621 *bad_wr = wr; 622 nreq = 0; 623 goto out; 624 } 625 626 for (nreq = 0; wr; ++nreq, wr = wr->next) { 627 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq, 628 hr_qp->ibqp.recv_cq))) { 629 ret = -ENOMEM; 630 *bad_wr = wr; 631 goto out; 632 } 633 634 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); 635 636 if (unlikely(wr->num_sge >= hr_qp->rq.max_gs)) { 637 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n", 638 wr->num_sge, hr_qp->rq.max_gs); 639 ret = -EINVAL; 640 *bad_wr = wr; 641 goto out; 642 } 643 644 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); 645 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 646 for (i = 0; i < wr->num_sge; i++) { 647 if (!wr->sg_list[i].length) 648 continue; 649 set_data_seg_v2(dseg, wr->sg_list + i); 650 dseg++; 651 } 652 653 if (wr->num_sge < hr_qp->rq.max_gs) { 654 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 655 dseg->addr = 0; 656 dseg->len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 657 } 658 659 /* rq support inline data */ 660 if (hr_qp->rq_inl_buf.wqe_cnt) { 661 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; 662 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = 663 (u32)wr->num_sge; 664 for (i = 0; i < wr->num_sge; i++) { 665 sge_list[i].addr = 666 (void *)(u64)wr->sg_list[i].addr; 667 sge_list[i].len = wr->sg_list[i].length; 668 } 669 } 670 671 hr_qp->rq.wrid[wqe_idx] = wr->wr_id; 672 } 673 674 out: 675 if (likely(nreq)) { 676 hr_qp->rq.head += nreq; 677 /* Memory barrier */ 678 wmb(); 679 680 /* 681 * Hip08 hardware cannot flush the WQEs in RQ if the QP state 682 * gets into errored mode. Hence, as a workaround to this 683 * hardware limitation, driver needs to assist in flushing. But 684 * the flushing operation uses mailbox to convey the QP state to 685 * the hardware and which can sleep due to the mutex protection 686 * around the mailbox calls. Hence, use the deferred flush for 687 * now. 688 */ 689 if (hr_qp->state == IB_QPS_ERR) { 690 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, 691 &hr_qp->flush_flag)) 692 init_flush_work(hr_dev, hr_qp); 693 } else { 694 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; 695 } 696 } 697 spin_unlock_irqrestore(&hr_qp->rq.lock, flags); 698 699 return ret; 700 } 701 702 static void *get_srq_wqe(struct hns_roce_srq *srq, int n) 703 { 704 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); 705 } 706 707 static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n) 708 { 709 return hns_roce_buf_offset(idx_que->mtr.kmem, 710 n << idx_que->entry_shift); 711 } 712 713 static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index) 714 { 715 /* always called with interrupts disabled. */ 716 spin_lock(&srq->lock); 717 718 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); 719 srq->tail++; 720 721 spin_unlock(&srq->lock); 722 } 723 724 static int find_empty_entry(struct hns_roce_idx_que *idx_que, 725 unsigned long size) 726 { 727 int wqe_idx; 728 729 if (unlikely(bitmap_full(idx_que->bitmap, size))) 730 return -ENOSPC; 731 732 wqe_idx = find_first_zero_bit(idx_que->bitmap, size); 733 734 bitmap_set(idx_que->bitmap, wqe_idx, 1); 735 736 return wqe_idx; 737 } 738 739 static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, 740 const struct ib_recv_wr *wr, 741 const struct ib_recv_wr **bad_wr) 742 { 743 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 744 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 745 struct hns_roce_v2_wqe_data_seg *dseg; 746 struct hns_roce_v2_db srq_db; 747 unsigned long flags; 748 __le32 *srq_idx; 749 int ret = 0; 750 int wqe_idx; 751 void *wqe; 752 int nreq; 753 int ind; 754 int i; 755 756 spin_lock_irqsave(&srq->lock, flags); 757 758 ind = srq->head & (srq->wqe_cnt - 1); 759 760 for (nreq = 0; wr; ++nreq, wr = wr->next) { 761 if (unlikely(wr->num_sge >= srq->max_gs)) { 762 ret = -EINVAL; 763 *bad_wr = wr; 764 break; 765 } 766 767 if (unlikely(srq->head == srq->tail)) { 768 ret = -ENOMEM; 769 *bad_wr = wr; 770 break; 771 } 772 773 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt); 774 if (unlikely(wqe_idx < 0)) { 775 ret = -ENOMEM; 776 *bad_wr = wr; 777 break; 778 } 779 780 wqe = get_srq_wqe(srq, wqe_idx); 781 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; 782 783 for (i = 0; i < wr->num_sge; ++i) { 784 dseg[i].len = cpu_to_le32(wr->sg_list[i].length); 785 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey); 786 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr); 787 } 788 789 if (wr->num_sge < srq->max_gs) { 790 dseg[i].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH); 791 dseg[i].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); 792 dseg[i].addr = 0; 793 } 794 795 srq_idx = get_idx_buf(&srq->idx_que, ind); 796 *srq_idx = cpu_to_le32(wqe_idx); 797 798 srq->wrid[wqe_idx] = wr->wr_id; 799 ind = (ind + 1) & (srq->wqe_cnt - 1); 800 } 801 802 if (likely(nreq)) { 803 srq->head += nreq; 804 805 /* 806 * Make sure that descriptors are written before 807 * doorbell record. 808 */ 809 wmb(); 810 811 srq_db.byte_4 = 812 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S | 813 (srq->srqn & V2_DB_BYTE_4_TAG_M)); 814 srq_db.parameter = 815 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M); 816 817 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l); 818 } 819 820 spin_unlock_irqrestore(&srq->lock, flags); 821 822 return ret; 823 } 824 825 static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, 826 unsigned long instance_stage, 827 unsigned long reset_stage) 828 { 829 /* When hardware reset has been completed once or more, we should stop 830 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() 831 * function, we should exit with error. If now at HNAE3_INIT_CLIENT 832 * stage of soft reset process, we should exit with error, and then 833 * HNAE3_INIT_CLIENT related process can rollback the operation like 834 * notifing hardware to free resources, HNAE3_INIT_CLIENT related 835 * process will exit with error to notify NIC driver to reschedule soft 836 * reset process once again. 837 */ 838 hr_dev->is_reset = true; 839 hr_dev->dis_db = true; 840 841 if (reset_stage == HNS_ROCE_STATE_RST_INIT || 842 instance_stage == HNS_ROCE_STATE_INIT) 843 return CMD_RST_PRC_EBUSY; 844 845 return CMD_RST_PRC_SUCCESS; 846 } 847 848 static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, 849 unsigned long instance_stage, 850 unsigned long reset_stage) 851 { 852 struct hns_roce_v2_priv *priv = hr_dev->priv; 853 struct hnae3_handle *handle = priv->handle; 854 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 855 856 /* When hardware reset is detected, we should stop sending mailbox&cmq& 857 * doorbell to hardware. If now in .init_instance() function, we should 858 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset 859 * process, we should exit with error, and then HNAE3_INIT_CLIENT 860 * related process can rollback the operation like notifing hardware to 861 * free resources, HNAE3_INIT_CLIENT related process will exit with 862 * error to notify NIC driver to reschedule soft reset process once 863 * again. 864 */ 865 hr_dev->dis_db = true; 866 if (!ops->get_hw_reset_stat(handle)) 867 hr_dev->is_reset = true; 868 869 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || 870 instance_stage == HNS_ROCE_STATE_INIT) 871 return CMD_RST_PRC_EBUSY; 872 873 return CMD_RST_PRC_SUCCESS; 874 } 875 876 static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) 877 { 878 struct hns_roce_v2_priv *priv = hr_dev->priv; 879 struct hnae3_handle *handle = priv->handle; 880 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 881 882 /* When software reset is detected at .init_instance() function, we 883 * should stop sending mailbox&cmq&doorbell to hardware, and exit 884 * with error. 885 */ 886 hr_dev->dis_db = true; 887 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) 888 hr_dev->is_reset = true; 889 890 return CMD_RST_PRC_EBUSY; 891 } 892 893 static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev) 894 { 895 struct hns_roce_v2_priv *priv = hr_dev->priv; 896 struct hnae3_handle *handle = priv->handle; 897 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 898 unsigned long instance_stage; /* the current instance stage */ 899 unsigned long reset_stage; /* the current reset stage */ 900 unsigned long reset_cnt; 901 bool sw_resetting; 902 bool hw_resetting; 903 904 if (hr_dev->is_reset) 905 return CMD_RST_PRC_SUCCESS; 906 907 /* Get information about reset from NIC driver or RoCE driver itself, 908 * the meaning of the following variables from NIC driver are described 909 * as below: 910 * reset_cnt -- The count value of completed hardware reset. 911 * hw_resetting -- Whether hardware device is resetting now. 912 * sw_resetting -- Whether NIC's software reset process is running now. 913 */ 914 instance_stage = handle->rinfo.instance_state; 915 reset_stage = handle->rinfo.reset_state; 916 reset_cnt = ops->ae_dev_reset_cnt(handle); 917 hw_resetting = ops->get_cmdq_stat(handle); 918 sw_resetting = ops->ae_dev_resetting(handle); 919 920 if (reset_cnt != hr_dev->reset_cnt) 921 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, 922 reset_stage); 923 else if (hw_resetting) 924 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, 925 reset_stage); 926 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) 927 return hns_roce_v2_cmd_sw_resetting(hr_dev); 928 929 return 0; 930 } 931 932 static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) 933 { 934 int ntu = ring->next_to_use; 935 int ntc = ring->next_to_clean; 936 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 937 938 return ring->desc_num - used - 1; 939 } 940 941 static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, 942 struct hns_roce_v2_cmq_ring *ring) 943 { 944 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); 945 946 ring->desc = kzalloc(size, GFP_KERNEL); 947 if (!ring->desc) 948 return -ENOMEM; 949 950 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, 951 DMA_BIDIRECTIONAL); 952 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { 953 ring->desc_dma_addr = 0; 954 kfree(ring->desc); 955 ring->desc = NULL; 956 return -ENOMEM; 957 } 958 959 return 0; 960 } 961 962 static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, 963 struct hns_roce_v2_cmq_ring *ring) 964 { 965 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, 966 ring->desc_num * sizeof(struct hns_roce_cmq_desc), 967 DMA_BIDIRECTIONAL); 968 969 ring->desc_dma_addr = 0; 970 kfree(ring->desc); 971 } 972 973 static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) 974 { 975 struct hns_roce_v2_priv *priv = hr_dev->priv; 976 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 977 &priv->cmq.csq : &priv->cmq.crq; 978 979 ring->flag = ring_type; 980 ring->next_to_clean = 0; 981 ring->next_to_use = 0; 982 983 return hns_roce_alloc_cmq_desc(hr_dev, ring); 984 } 985 986 static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) 987 { 988 struct hns_roce_v2_priv *priv = hr_dev->priv; 989 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? 990 &priv->cmq.csq : &priv->cmq.crq; 991 dma_addr_t dma = ring->desc_dma_addr; 992 993 if (ring_type == TYPE_CSQ) { 994 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); 995 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, 996 upper_32_bits(dma)); 997 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, 998 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 999 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); 1000 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); 1001 } else { 1002 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); 1003 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, 1004 upper_32_bits(dma)); 1005 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, 1006 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); 1007 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); 1008 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); 1009 } 1010 } 1011 1012 static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) 1013 { 1014 struct hns_roce_v2_priv *priv = hr_dev->priv; 1015 int ret; 1016 1017 /* Setup the queue entries for command queue */ 1018 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; 1019 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; 1020 1021 /* Setup the lock for command queue */ 1022 spin_lock_init(&priv->cmq.csq.lock); 1023 spin_lock_init(&priv->cmq.crq.lock); 1024 1025 /* Setup Tx write back timeout */ 1026 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; 1027 1028 /* Init CSQ */ 1029 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); 1030 if (ret) { 1031 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); 1032 return ret; 1033 } 1034 1035 /* Init CRQ */ 1036 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); 1037 if (ret) { 1038 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); 1039 goto err_crq; 1040 } 1041 1042 /* Init CSQ REG */ 1043 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); 1044 1045 /* Init CRQ REG */ 1046 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); 1047 1048 return 0; 1049 1050 err_crq: 1051 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1052 1053 return ret; 1054 } 1055 1056 static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) 1057 { 1058 struct hns_roce_v2_priv *priv = hr_dev->priv; 1059 1060 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); 1061 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); 1062 } 1063 1064 static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, 1065 enum hns_roce_opcode_type opcode, 1066 bool is_read) 1067 { 1068 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); 1069 desc->opcode = cpu_to_le16(opcode); 1070 desc->flag = 1071 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1072 if (is_read) 1073 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); 1074 else 1075 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1076 } 1077 1078 static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) 1079 { 1080 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1081 struct hns_roce_v2_priv *priv = hr_dev->priv; 1082 1083 return head == priv->cmq.csq.next_to_use; 1084 } 1085 1086 static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) 1087 { 1088 struct hns_roce_v2_priv *priv = hr_dev->priv; 1089 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1090 struct hns_roce_cmq_desc *desc; 1091 u16 ntc = csq->next_to_clean; 1092 u32 head; 1093 int clean = 0; 1094 1095 desc = &csq->desc[ntc]; 1096 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); 1097 while (head != ntc) { 1098 memset(desc, 0, sizeof(*desc)); 1099 ntc++; 1100 if (ntc == csq->desc_num) 1101 ntc = 0; 1102 desc = &csq->desc[ntc]; 1103 clean++; 1104 } 1105 csq->next_to_clean = ntc; 1106 1107 return clean; 1108 } 1109 1110 static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1111 struct hns_roce_cmq_desc *desc, int num) 1112 { 1113 struct hns_roce_v2_priv *priv = hr_dev->priv; 1114 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; 1115 struct hns_roce_cmq_desc *desc_to_use; 1116 bool complete = false; 1117 u32 timeout = 0; 1118 int handle = 0; 1119 u16 desc_ret; 1120 int ret = 0; 1121 int ntc; 1122 1123 spin_lock_bh(&csq->lock); 1124 1125 if (num > hns_roce_cmq_space(csq)) { 1126 spin_unlock_bh(&csq->lock); 1127 return -EBUSY; 1128 } 1129 1130 /* 1131 * Record the location of desc in the cmq for this time 1132 * which will be use for hardware to write back 1133 */ 1134 ntc = csq->next_to_use; 1135 1136 while (handle < num) { 1137 desc_to_use = &csq->desc[csq->next_to_use]; 1138 *desc_to_use = desc[handle]; 1139 dev_dbg(hr_dev->dev, "set cmq desc:\n"); 1140 csq->next_to_use++; 1141 if (csq->next_to_use == csq->desc_num) 1142 csq->next_to_use = 0; 1143 handle++; 1144 } 1145 1146 /* Write to hardware */ 1147 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); 1148 1149 /* 1150 * If the command is sync, wait for the firmware to write back, 1151 * if multi descriptors to be sent, use the first one to check 1152 */ 1153 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { 1154 do { 1155 if (hns_roce_cmq_csq_done(hr_dev)) 1156 break; 1157 udelay(1); 1158 timeout++; 1159 } while (timeout < priv->cmq.tx_timeout); 1160 } 1161 1162 if (hns_roce_cmq_csq_done(hr_dev)) { 1163 complete = true; 1164 handle = 0; 1165 while (handle < num) { 1166 /* get the result of hardware write back */ 1167 desc_to_use = &csq->desc[ntc]; 1168 desc[handle] = *desc_to_use; 1169 dev_dbg(hr_dev->dev, "Get cmq desc:\n"); 1170 desc_ret = le16_to_cpu(desc[handle].retval); 1171 if (desc_ret == CMD_EXEC_SUCCESS) 1172 ret = 0; 1173 else 1174 ret = -EIO; 1175 priv->cmq.last_status = desc_ret; 1176 ntc++; 1177 handle++; 1178 if (ntc == csq->desc_num) 1179 ntc = 0; 1180 } 1181 } 1182 1183 if (!complete) 1184 ret = -EAGAIN; 1185 1186 /* clean the command send queue */ 1187 handle = hns_roce_cmq_csq_clean(hr_dev); 1188 if (handle != num) 1189 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", 1190 handle, num); 1191 1192 spin_unlock_bh(&csq->lock); 1193 1194 return ret; 1195 } 1196 1197 static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 1198 struct hns_roce_cmq_desc *desc, int num) 1199 { 1200 int retval; 1201 int ret; 1202 1203 ret = hns_roce_v2_rst_process_cmd(hr_dev); 1204 if (ret == CMD_RST_PRC_SUCCESS) 1205 return 0; 1206 if (ret == CMD_RST_PRC_EBUSY) 1207 return -EBUSY; 1208 1209 ret = __hns_roce_cmq_send(hr_dev, desc, num); 1210 if (ret) { 1211 retval = hns_roce_v2_rst_process_cmd(hr_dev); 1212 if (retval == CMD_RST_PRC_SUCCESS) 1213 return 0; 1214 else if (retval == CMD_RST_PRC_EBUSY) 1215 return -EBUSY; 1216 } 1217 1218 return ret; 1219 } 1220 1221 static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) 1222 { 1223 struct hns_roce_query_version *resp; 1224 struct hns_roce_cmq_desc desc; 1225 int ret; 1226 1227 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); 1228 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1229 if (ret) 1230 return ret; 1231 1232 resp = (struct hns_roce_query_version *)desc.data; 1233 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); 1234 hr_dev->vendor_id = hr_dev->pci_dev->vendor; 1235 1236 return 0; 1237 } 1238 1239 static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev) 1240 { 1241 struct hns_roce_v2_priv *priv = hr_dev->priv; 1242 struct hnae3_handle *handle = priv->handle; 1243 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1244 unsigned long reset_cnt; 1245 bool sw_resetting; 1246 bool hw_resetting; 1247 1248 reset_cnt = ops->ae_dev_reset_cnt(handle); 1249 hw_resetting = ops->get_hw_reset_stat(handle); 1250 sw_resetting = ops->ae_dev_resetting(handle); 1251 1252 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting) 1253 return true; 1254 1255 return false; 1256 } 1257 1258 static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval, 1259 int flag) 1260 { 1261 struct hns_roce_v2_priv *priv = hr_dev->priv; 1262 struct hnae3_handle *handle = priv->handle; 1263 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 1264 unsigned long instance_stage; 1265 unsigned long reset_cnt; 1266 unsigned long end; 1267 bool sw_resetting; 1268 bool hw_resetting; 1269 1270 instance_stage = handle->rinfo.instance_state; 1271 reset_cnt = ops->ae_dev_reset_cnt(handle); 1272 hw_resetting = ops->get_hw_reset_stat(handle); 1273 sw_resetting = ops->ae_dev_resetting(handle); 1274 1275 if (reset_cnt != hr_dev->reset_cnt) { 1276 hr_dev->dis_db = true; 1277 hr_dev->is_reset = true; 1278 dev_info(hr_dev->dev, "Func clear success after reset.\n"); 1279 } else if (hw_resetting) { 1280 hr_dev->dis_db = true; 1281 1282 dev_warn(hr_dev->dev, 1283 "Func clear is pending, device in resetting state.\n"); 1284 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1285 while (end) { 1286 if (!ops->get_hw_reset_stat(handle)) { 1287 hr_dev->is_reset = true; 1288 dev_info(hr_dev->dev, 1289 "Func clear success after reset.\n"); 1290 return; 1291 } 1292 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1293 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1294 } 1295 1296 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1297 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) { 1298 hr_dev->dis_db = true; 1299 1300 dev_warn(hr_dev->dev, 1301 "Func clear is pending, device in resetting state.\n"); 1302 end = HNS_ROCE_V2_HW_RST_TIMEOUT; 1303 while (end) { 1304 if (ops->ae_dev_reset_cnt(handle) != 1305 hr_dev->reset_cnt) { 1306 hr_dev->is_reset = true; 1307 dev_info(hr_dev->dev, 1308 "Func clear success after sw reset\n"); 1309 return; 1310 } 1311 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); 1312 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; 1313 } 1314 1315 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); 1316 } else { 1317 if (retval && !flag) 1318 dev_warn(hr_dev->dev, 1319 "Func clear read failed, ret = %d.\n", retval); 1320 1321 dev_warn(hr_dev->dev, "Func clear failed.\n"); 1322 } 1323 } 1324 static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) 1325 { 1326 bool fclr_write_fail_flag = false; 1327 struct hns_roce_func_clear *resp; 1328 struct hns_roce_cmq_desc desc; 1329 unsigned long end; 1330 int ret = 0; 1331 1332 if (hns_roce_func_clr_chk_rst(hr_dev)) 1333 goto out; 1334 1335 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); 1336 resp = (struct hns_roce_func_clear *)desc.data; 1337 1338 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1339 if (ret) { 1340 fclr_write_fail_flag = true; 1341 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", 1342 ret); 1343 goto out; 1344 } 1345 1346 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); 1347 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; 1348 while (end) { 1349 if (hns_roce_func_clr_chk_rst(hr_dev)) 1350 goto out; 1351 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); 1352 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; 1353 1354 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, 1355 true); 1356 1357 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1358 if (ret) 1359 continue; 1360 1361 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { 1362 hr_dev->is_reset = true; 1363 return; 1364 } 1365 } 1366 1367 out: 1368 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag); 1369 } 1370 1371 static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) 1372 { 1373 struct hns_roce_query_fw_info *resp; 1374 struct hns_roce_cmq_desc desc; 1375 int ret; 1376 1377 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); 1378 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1379 if (ret) 1380 return ret; 1381 1382 resp = (struct hns_roce_query_fw_info *)desc.data; 1383 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); 1384 1385 return 0; 1386 } 1387 1388 static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) 1389 { 1390 struct hns_roce_cfg_global_param *req; 1391 struct hns_roce_cmq_desc desc; 1392 1393 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, 1394 false); 1395 1396 req = (struct hns_roce_cfg_global_param *)desc.data; 1397 memset(req, 0, sizeof(*req)); 1398 roce_set_field(req->time_cfg_udp_port, 1399 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, 1400 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); 1401 roce_set_field(req->time_cfg_udp_port, 1402 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, 1403 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); 1404 1405 return hns_roce_cmq_send(hr_dev, &desc, 1); 1406 } 1407 1408 static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) 1409 { 1410 struct hns_roce_cmq_desc desc[2]; 1411 struct hns_roce_pf_res_a *req_a; 1412 struct hns_roce_pf_res_b *req_b; 1413 int ret; 1414 int i; 1415 1416 for (i = 0; i < 2; i++) { 1417 hns_roce_cmq_setup_basic_desc(&desc[i], 1418 HNS_ROCE_OPC_QUERY_PF_RES, true); 1419 1420 if (i == 0) 1421 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1422 else 1423 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1424 } 1425 1426 ret = hns_roce_cmq_send(hr_dev, desc, 2); 1427 if (ret) 1428 return ret; 1429 1430 req_a = (struct hns_roce_pf_res_a *)desc[0].data; 1431 req_b = (struct hns_roce_pf_res_b *)desc[1].data; 1432 1433 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, 1434 PF_RES_DATA_1_PF_QPC_BT_NUM_M, 1435 PF_RES_DATA_1_PF_QPC_BT_NUM_S); 1436 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, 1437 PF_RES_DATA_2_PF_SRQC_BT_NUM_M, 1438 PF_RES_DATA_2_PF_SRQC_BT_NUM_S); 1439 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, 1440 PF_RES_DATA_3_PF_CQC_BT_NUM_M, 1441 PF_RES_DATA_3_PF_CQC_BT_NUM_S); 1442 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, 1443 PF_RES_DATA_4_PF_MPT_BT_NUM_M, 1444 PF_RES_DATA_4_PF_MPT_BT_NUM_S); 1445 1446 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, 1447 PF_RES_DATA_3_PF_SL_NUM_M, 1448 PF_RES_DATA_3_PF_SL_NUM_S); 1449 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, 1450 PF_RES_DATA_4_PF_SCCC_BT_NUM_M, 1451 PF_RES_DATA_4_PF_SCCC_BT_NUM_S); 1452 1453 return 0; 1454 } 1455 1456 static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev) 1457 { 1458 struct hns_roce_pf_timer_res_a *req_a; 1459 struct hns_roce_cmq_desc desc; 1460 int ret; 1461 1462 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES, 1463 true); 1464 1465 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1466 if (ret) 1467 return ret; 1468 1469 req_a = (struct hns_roce_pf_timer_res_a *)desc.data; 1470 1471 hr_dev->caps.qpc_timer_bt_num = 1472 roce_get_field(req_a->qpc_timer_bt_idx_num, 1473 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M, 1474 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S); 1475 hr_dev->caps.cqc_timer_bt_num = 1476 roce_get_field(req_a->cqc_timer_bt_idx_num, 1477 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M, 1478 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S); 1479 1480 return 0; 1481 } 1482 1483 static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) 1484 { 1485 struct hns_roce_cmq_desc desc; 1486 struct hns_roce_vf_switch *swt; 1487 int ret; 1488 1489 swt = (struct hns_roce_vf_switch *)desc.data; 1490 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); 1491 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); 1492 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, 1493 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); 1494 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 1495 if (ret) 1496 return ret; 1497 1498 desc.flag = 1499 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); 1500 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); 1501 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); 1502 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); 1503 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); 1504 1505 return hns_roce_cmq_send(hr_dev, &desc, 1); 1506 } 1507 1508 static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 1509 { 1510 struct hns_roce_cmq_desc desc[2]; 1511 struct hns_roce_vf_res_a *req_a; 1512 struct hns_roce_vf_res_b *req_b; 1513 int i; 1514 1515 req_a = (struct hns_roce_vf_res_a *)desc[0].data; 1516 req_b = (struct hns_roce_vf_res_b *)desc[1].data; 1517 for (i = 0; i < 2; i++) { 1518 hns_roce_cmq_setup_basic_desc(&desc[i], 1519 HNS_ROCE_OPC_ALLOC_VF_RES, false); 1520 1521 if (i == 0) 1522 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1523 else 1524 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1525 } 1526 1527 roce_set_field(req_a->vf_qpc_bt_idx_num, 1528 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, 1529 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); 1530 roce_set_field(req_a->vf_qpc_bt_idx_num, 1531 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, 1532 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM); 1533 1534 roce_set_field(req_a->vf_srqc_bt_idx_num, 1535 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, 1536 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); 1537 roce_set_field(req_a->vf_srqc_bt_idx_num, 1538 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, 1539 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, 1540 HNS_ROCE_VF_SRQC_BT_NUM); 1541 1542 roce_set_field(req_a->vf_cqc_bt_idx_num, 1543 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, 1544 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); 1545 roce_set_field(req_a->vf_cqc_bt_idx_num, 1546 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, 1547 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM); 1548 1549 roce_set_field(req_a->vf_mpt_bt_idx_num, 1550 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, 1551 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); 1552 roce_set_field(req_a->vf_mpt_bt_idx_num, 1553 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, 1554 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM); 1555 1556 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M, 1557 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); 1558 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M, 1559 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM); 1560 1561 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M, 1562 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); 1563 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M, 1564 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM); 1565 1566 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M, 1567 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); 1568 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M, 1569 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM); 1570 1571 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M, 1572 VF_RES_B_DATA_3_VF_QID_IDX_S, 0); 1573 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M, 1574 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM); 1575 1576 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M, 1577 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0); 1578 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M, 1579 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S, 1580 HNS_ROCE_VF_SCCC_BT_NUM); 1581 1582 return hns_roce_cmq_send(hr_dev, desc, 2); 1583 } 1584 1585 static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 1586 { 1587 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; 1588 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; 1589 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; 1590 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; 1591 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num; 1592 struct hns_roce_cfg_bt_attr *req; 1593 struct hns_roce_cmq_desc desc; 1594 1595 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); 1596 req = (struct hns_roce_cfg_bt_attr *)desc.data; 1597 memset(req, 0, sizeof(*req)); 1598 1599 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, 1600 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, 1601 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); 1602 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, 1603 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, 1604 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); 1605 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, 1606 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, 1607 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); 1608 1609 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, 1610 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, 1611 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); 1612 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, 1613 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, 1614 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); 1615 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, 1616 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, 1617 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); 1618 1619 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, 1620 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, 1621 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); 1622 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, 1623 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, 1624 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); 1625 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, 1626 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, 1627 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); 1628 1629 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, 1630 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, 1631 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); 1632 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, 1633 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, 1634 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); 1635 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, 1636 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, 1637 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); 1638 1639 roce_set_field(req->vf_sccc_cfg, 1640 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M, 1641 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S, 1642 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET); 1643 roce_set_field(req->vf_sccc_cfg, 1644 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M, 1645 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S, 1646 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET); 1647 roce_set_field(req->vf_sccc_cfg, 1648 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M, 1649 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S, 1650 sccc_hop_num == 1651 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num); 1652 1653 return hns_roce_cmq_send(hr_dev, &desc, 1); 1654 } 1655 1656 static void set_default_caps(struct hns_roce_dev *hr_dev) 1657 { 1658 struct hns_roce_caps *caps = &hr_dev->caps; 1659 1660 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; 1661 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; 1662 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; 1663 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; 1664 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; 1665 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; 1666 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; 1667 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; 1668 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; 1669 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; 1670 caps->num_uars = HNS_ROCE_V2_UAR_NUM; 1671 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; 1672 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; 1673 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; 1674 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; 1675 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; 1676 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1677 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1678 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1679 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1680 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; 1681 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; 1682 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; 1683 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; 1684 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; 1685 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; 1686 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; 1687 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; 1688 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; 1689 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; 1690 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; 1691 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; 1692 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1693 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; 1694 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; 1695 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; 1696 caps->reserved_lkey = 0; 1697 caps->reserved_pds = 0; 1698 caps->reserved_mrws = 1; 1699 caps->reserved_uars = 0; 1700 caps->reserved_cqs = 0; 1701 caps->reserved_srqs = 0; 1702 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; 1703 1704 caps->qpc_ba_pg_sz = 0; 1705 caps->qpc_buf_pg_sz = 0; 1706 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1707 caps->srqc_ba_pg_sz = 0; 1708 caps->srqc_buf_pg_sz = 0; 1709 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1710 caps->cqc_ba_pg_sz = 0; 1711 caps->cqc_buf_pg_sz = 0; 1712 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1713 caps->mpt_ba_pg_sz = 0; 1714 caps->mpt_buf_pg_sz = 0; 1715 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; 1716 caps->mtt_ba_pg_sz = 0; 1717 caps->mtt_buf_pg_sz = 0; 1718 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; 1719 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; 1720 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; 1721 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; 1722 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; 1723 caps->cqe_buf_pg_sz = 0; 1724 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; 1725 caps->srqwqe_ba_pg_sz = 0; 1726 caps->srqwqe_buf_pg_sz = 0; 1727 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; 1728 caps->idx_ba_pg_sz = 0; 1729 caps->idx_buf_pg_sz = 0; 1730 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; 1731 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; 1732 1733 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | 1734 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | 1735 HNS_ROCE_CAP_FLAG_RQ_INLINE | 1736 HNS_ROCE_CAP_FLAG_RECORD_DB | 1737 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; 1738 1739 caps->pkey_table_len[0] = 1; 1740 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; 1741 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; 1742 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; 1743 caps->local_ca_ack_delay = 0; 1744 caps->max_mtu = IB_MTU_4096; 1745 1746 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; 1747 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; 1748 1749 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | 1750 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | 1751 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; 1752 1753 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; 1754 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1755 caps->qpc_timer_ba_pg_sz = 0; 1756 caps->qpc_timer_buf_pg_sz = 0; 1757 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1758 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; 1759 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1760 caps->cqc_timer_ba_pg_sz = 0; 1761 caps->cqc_timer_buf_pg_sz = 0; 1762 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 1763 1764 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ; 1765 caps->sccc_ba_pg_sz = 0; 1766 caps->sccc_buf_pg_sz = 0; 1767 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; 1768 } 1769 1770 static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num, 1771 int *buf_page_size, int *bt_page_size, u32 hem_type) 1772 { 1773 u64 obj_per_chunk; 1774 int bt_chunk_size = 1 << PAGE_SHIFT; 1775 int buf_chunk_size = 1 << PAGE_SHIFT; 1776 int obj_per_chunk_default = buf_chunk_size / obj_size; 1777 1778 *buf_page_size = 0; 1779 *bt_page_size = 0; 1780 1781 switch (hop_num) { 1782 case 3: 1783 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1784 (bt_chunk_size / BA_BYTE_LEN) * 1785 (bt_chunk_size / BA_BYTE_LEN) * 1786 obj_per_chunk_default; 1787 break; 1788 case 2: 1789 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1790 (bt_chunk_size / BA_BYTE_LEN) * 1791 obj_per_chunk_default; 1792 break; 1793 case 1: 1794 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * 1795 obj_per_chunk_default; 1796 break; 1797 case HNS_ROCE_HOP_NUM_0: 1798 obj_per_chunk = ctx_bt_num * obj_per_chunk_default; 1799 break; 1800 default: 1801 pr_err("Table %d not support hop_num = %d!\n", hem_type, 1802 hop_num); 1803 return; 1804 } 1805 1806 if (hem_type >= HEM_TYPE_MTT) 1807 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1808 else 1809 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); 1810 } 1811 1812 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 1813 { 1814 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; 1815 struct hns_roce_caps *caps = &hr_dev->caps; 1816 struct hns_roce_query_pf_caps_a *resp_a; 1817 struct hns_roce_query_pf_caps_b *resp_b; 1818 struct hns_roce_query_pf_caps_c *resp_c; 1819 struct hns_roce_query_pf_caps_d *resp_d; 1820 struct hns_roce_query_pf_caps_e *resp_e; 1821 int ctx_hop_num; 1822 int pbl_hop_num; 1823 int ret; 1824 int i; 1825 1826 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { 1827 hns_roce_cmq_setup_basic_desc(&desc[i], 1828 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, 1829 true); 1830 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) 1831 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1832 else 1833 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 1834 } 1835 1836 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); 1837 if (ret) 1838 return ret; 1839 1840 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; 1841 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; 1842 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; 1843 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; 1844 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; 1845 1846 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; 1847 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); 1848 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); 1849 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); 1850 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); 1851 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); 1852 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); 1853 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); 1854 caps->num_aeq_vectors = resp_a->num_aeq_vectors; 1855 caps->num_other_vectors = resp_a->num_other_vectors; 1856 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; 1857 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; 1858 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; 1859 caps->cq_entry_sz = resp_a->cq_entry_sz; 1860 1861 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; 1862 caps->irrl_entry_sz = resp_b->irrl_entry_sz; 1863 caps->trrl_entry_sz = resp_b->trrl_entry_sz; 1864 caps->cqc_entry_sz = resp_b->cqc_entry_sz; 1865 caps->srqc_entry_sz = resp_b->srqc_entry_sz; 1866 caps->idx_entry_sz = resp_b->idx_entry_sz; 1867 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz; 1868 caps->max_mtu = resp_b->max_mtu; 1869 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz); 1870 caps->min_cqes = resp_b->min_cqes; 1871 caps->min_wqes = resp_b->min_wqes; 1872 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); 1873 caps->pkey_table_len[0] = resp_b->pkey_table_len; 1874 caps->phy_num_uars = resp_b->phy_num_uars; 1875 ctx_hop_num = resp_b->ctx_hop_num; 1876 pbl_hop_num = resp_b->pbl_hop_num; 1877 1878 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, 1879 V2_QUERY_PF_CAPS_C_NUM_PDS_M, 1880 V2_QUERY_PF_CAPS_C_NUM_PDS_S); 1881 caps->flags = roce_get_field(resp_c->cap_flags_num_pds, 1882 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, 1883 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); 1884 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) << 1885 HNS_ROCE_CAP_FLAGS_EX_SHIFT; 1886 1887 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, 1888 V2_QUERY_PF_CAPS_C_NUM_CQS_M, 1889 V2_QUERY_PF_CAPS_C_NUM_CQS_S); 1890 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, 1891 V2_QUERY_PF_CAPS_C_MAX_GID_M, 1892 V2_QUERY_PF_CAPS_C_MAX_GID_S); 1893 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, 1894 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, 1895 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); 1896 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, 1897 V2_QUERY_PF_CAPS_C_NUM_MRWS_M, 1898 V2_QUERY_PF_CAPS_C_NUM_MRWS_S); 1899 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, 1900 V2_QUERY_PF_CAPS_C_NUM_QPS_M, 1901 V2_QUERY_PF_CAPS_C_NUM_QPS_S); 1902 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, 1903 V2_QUERY_PF_CAPS_C_MAX_ORD_M, 1904 V2_QUERY_PF_CAPS_C_MAX_ORD_S); 1905 caps->max_qp_dest_rdma = caps->max_qp_init_rdma; 1906 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); 1907 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, 1908 V2_QUERY_PF_CAPS_D_NUM_SRQS_M, 1909 V2_QUERY_PF_CAPS_D_NUM_SRQS_S); 1910 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); 1911 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, 1912 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, 1913 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); 1914 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, 1915 V2_QUERY_PF_CAPS_D_NUM_CEQS_M, 1916 V2_QUERY_PF_CAPS_D_NUM_CEQS_S); 1917 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, 1918 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, 1919 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); 1920 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1921 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, 1922 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); 1923 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, 1924 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, 1925 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); 1926 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, 1927 V2_QUERY_PF_CAPS_D_RSV_PDS_M, 1928 V2_QUERY_PF_CAPS_D_RSV_PDS_S); 1929 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, 1930 V2_QUERY_PF_CAPS_D_NUM_UARS_M, 1931 V2_QUERY_PF_CAPS_D_NUM_UARS_S); 1932 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, 1933 V2_QUERY_PF_CAPS_D_RSV_QPS_M, 1934 V2_QUERY_PF_CAPS_D_RSV_QPS_S); 1935 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, 1936 V2_QUERY_PF_CAPS_D_RSV_UARS_M, 1937 V2_QUERY_PF_CAPS_D_RSV_UARS_S); 1938 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1939 V2_QUERY_PF_CAPS_E_RSV_MRWS_M, 1940 V2_QUERY_PF_CAPS_E_RSV_MRWS_S); 1941 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, 1942 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, 1943 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); 1944 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, 1945 V2_QUERY_PF_CAPS_E_RSV_CQS_M, 1946 V2_QUERY_PF_CAPS_E_RSV_CQS_S); 1947 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, 1948 V2_QUERY_PF_CAPS_E_RSV_SRQS_M, 1949 V2_QUERY_PF_CAPS_E_RSV_SRQS_S); 1950 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, 1951 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, 1952 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); 1953 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); 1954 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); 1955 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); 1956 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); 1957 1958 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; 1959 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; 1960 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; 1961 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; 1962 caps->mtt_ba_pg_sz = 0; 1963 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; 1964 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; 1965 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; 1966 1967 caps->qpc_hop_num = ctx_hop_num; 1968 caps->srqc_hop_num = ctx_hop_num; 1969 caps->cqc_hop_num = ctx_hop_num; 1970 caps->mpt_hop_num = ctx_hop_num; 1971 caps->mtt_hop_num = pbl_hop_num; 1972 caps->cqe_hop_num = pbl_hop_num; 1973 caps->srqwqe_hop_num = pbl_hop_num; 1974 caps->idx_hop_num = pbl_hop_num; 1975 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1976 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, 1977 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); 1978 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1979 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, 1980 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); 1981 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, 1982 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, 1983 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); 1984 1985 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num, 1986 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, 1987 HEM_TYPE_QPC); 1988 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, 1989 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, 1990 HEM_TYPE_MTPT); 1991 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, 1992 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, 1993 HEM_TYPE_CQC); 1994 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num, 1995 caps->srqc_bt_num, &caps->srqc_buf_pg_sz, 1996 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC); 1997 1998 caps->sccc_hop_num = ctx_hop_num; 1999 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2000 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; 2001 2002 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz, 2003 caps->sccc_hop_num, caps->sccc_bt_num, 2004 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz, 2005 HEM_TYPE_SCCC); 2006 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, 2007 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, 2008 &caps->cqc_timer_buf_pg_sz, 2009 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); 2010 2011 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num, 2012 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); 2013 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, 2014 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, 2015 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); 2016 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num, 2017 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX); 2018 2019 return 0; 2020 } 2021 2022 static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) 2023 { 2024 struct hns_roce_caps *caps = &hr_dev->caps; 2025 int ret; 2026 2027 ret = hns_roce_cmq_query_hw_info(hr_dev); 2028 if (ret) { 2029 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n", 2030 ret); 2031 return ret; 2032 } 2033 2034 ret = hns_roce_query_fw_ver(hr_dev); 2035 if (ret) { 2036 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", 2037 ret); 2038 return ret; 2039 } 2040 2041 ret = hns_roce_config_global_param(hr_dev); 2042 if (ret) { 2043 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", 2044 ret); 2045 return ret; 2046 } 2047 2048 /* Get pf resource owned by every pf */ 2049 ret = hns_roce_query_pf_resource(hr_dev); 2050 if (ret) { 2051 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", 2052 ret); 2053 return ret; 2054 } 2055 2056 ret = hns_roce_query_pf_timer_resource(hr_dev); 2057 if (ret) { 2058 dev_err(hr_dev->dev, 2059 "failed to query pf timer resource, ret = %d.\n", ret); 2060 return ret; 2061 } 2062 2063 ret = hns_roce_set_vf_switch_param(hr_dev, 0); 2064 if (ret) { 2065 dev_err(hr_dev->dev, 2066 "failed to set function switch param, ret = %d.\n", 2067 ret); 2068 return ret; 2069 } 2070 2071 hr_dev->vendor_part_id = hr_dev->pci_dev->device; 2072 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); 2073 2074 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; 2075 caps->pbl_buf_pg_sz = 0; 2076 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; 2077 caps->eqe_ba_pg_sz = 0; 2078 caps->eqe_buf_pg_sz = 0; 2079 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; 2080 caps->tsq_buf_pg_sz = 0; 2081 2082 ret = hns_roce_query_pf_caps(hr_dev); 2083 if (ret) 2084 set_default_caps(hr_dev); 2085 2086 ret = hns_roce_alloc_vf_resource(hr_dev); 2087 if (ret) { 2088 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", 2089 ret); 2090 return ret; 2091 } 2092 2093 ret = hns_roce_v2_set_bt(hr_dev); 2094 if (ret) 2095 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", 2096 ret); 2097 2098 return ret; 2099 } 2100 2101 static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, 2102 enum hns_roce_link_table_type type) 2103 { 2104 struct hns_roce_cmq_desc desc[2]; 2105 struct hns_roce_cfg_llm_a *req_a = 2106 (struct hns_roce_cfg_llm_a *)desc[0].data; 2107 struct hns_roce_cfg_llm_b *req_b = 2108 (struct hns_roce_cfg_llm_b *)desc[1].data; 2109 struct hns_roce_v2_priv *priv = hr_dev->priv; 2110 struct hns_roce_link_table *link_tbl; 2111 struct hns_roce_link_table_entry *entry; 2112 enum hns_roce_opcode_type opcode; 2113 u32 page_num; 2114 int i; 2115 2116 switch (type) { 2117 case TSQ_LINK_TABLE: 2118 link_tbl = &priv->tsq; 2119 opcode = HNS_ROCE_OPC_CFG_EXT_LLM; 2120 break; 2121 case TPQ_LINK_TABLE: 2122 link_tbl = &priv->tpq; 2123 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; 2124 break; 2125 default: 2126 return -EINVAL; 2127 } 2128 2129 page_num = link_tbl->npages; 2130 entry = link_tbl->table.buf; 2131 2132 for (i = 0; i < 2; i++) { 2133 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false); 2134 2135 if (i == 0) 2136 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2137 else 2138 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); 2139 } 2140 2141 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff); 2142 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32); 2143 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M, 2144 CFG_LLM_QUE_DEPTH_S, link_tbl->npages); 2145 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M, 2146 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz); 2147 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M, 2148 CFG_LLM_INIT_EN_S, 1); 2149 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0); 2150 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr); 2151 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S, 2152 0); 2153 2154 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0); 2155 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M, 2156 CFG_LLM_TAIL_BA_H_S, 2157 entry[page_num - 1].blk_ba1_nxt_ptr & 2158 HNS_ROCE_LINK_TABLE_BA1_M); 2159 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S, 2160 (entry[page_num - 2].blk_ba1_nxt_ptr & 2161 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> 2162 HNS_ROCE_LINK_TABLE_NXT_PTR_S); 2163 2164 return hns_roce_cmq_send(hr_dev, desc, 2); 2165 } 2166 2167 static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, 2168 enum hns_roce_link_table_type type) 2169 { 2170 struct hns_roce_v2_priv *priv = hr_dev->priv; 2171 struct hns_roce_link_table *link_tbl; 2172 struct hns_roce_link_table_entry *entry; 2173 struct device *dev = hr_dev->dev; 2174 u32 buf_chk_sz; 2175 dma_addr_t t; 2176 int func_num = 1; 2177 int pg_num_a; 2178 int pg_num_b; 2179 int pg_num; 2180 int size; 2181 int i; 2182 2183 switch (type) { 2184 case TSQ_LINK_TABLE: 2185 link_tbl = &priv->tsq; 2186 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); 2187 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; 2188 pg_num_b = hr_dev->caps.sl_num * 4 + 2; 2189 break; 2190 case TPQ_LINK_TABLE: 2191 link_tbl = &priv->tpq; 2192 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); 2193 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; 2194 pg_num_b = 2 * 4 * func_num + 2; 2195 break; 2196 default: 2197 return -EINVAL; 2198 } 2199 2200 pg_num = max(pg_num_a, pg_num_b); 2201 size = pg_num * sizeof(struct hns_roce_link_table_entry); 2202 2203 link_tbl->table.buf = dma_alloc_coherent(dev, size, 2204 &link_tbl->table.map, 2205 GFP_KERNEL); 2206 if (!link_tbl->table.buf) 2207 goto out; 2208 2209 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), 2210 GFP_KERNEL); 2211 if (!link_tbl->pg_list) 2212 goto err_kcalloc_failed; 2213 2214 entry = link_tbl->table.buf; 2215 for (i = 0; i < pg_num; ++i) { 2216 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, 2217 &t, GFP_KERNEL); 2218 if (!link_tbl->pg_list[i].buf) 2219 goto err_alloc_buf_failed; 2220 2221 link_tbl->pg_list[i].map = t; 2222 2223 entry[i].blk_ba0 = (u32)(t >> 12); 2224 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44); 2225 2226 if (i < (pg_num - 1)) 2227 entry[i].blk_ba1_nxt_ptr |= 2228 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S; 2229 2230 } 2231 link_tbl->npages = pg_num; 2232 link_tbl->pg_sz = buf_chk_sz; 2233 2234 return hns_roce_config_link_table(hr_dev, type); 2235 2236 err_alloc_buf_failed: 2237 for (i -= 1; i >= 0; i--) 2238 dma_free_coherent(dev, buf_chk_sz, 2239 link_tbl->pg_list[i].buf, 2240 link_tbl->pg_list[i].map); 2241 kfree(link_tbl->pg_list); 2242 2243 err_kcalloc_failed: 2244 dma_free_coherent(dev, size, link_tbl->table.buf, 2245 link_tbl->table.map); 2246 2247 out: 2248 return -ENOMEM; 2249 } 2250 2251 static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, 2252 struct hns_roce_link_table *link_tbl) 2253 { 2254 struct device *dev = hr_dev->dev; 2255 int size; 2256 int i; 2257 2258 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); 2259 2260 for (i = 0; i < link_tbl->npages; ++i) 2261 if (link_tbl->pg_list[i].buf) 2262 dma_free_coherent(dev, link_tbl->pg_sz, 2263 link_tbl->pg_list[i].buf, 2264 link_tbl->pg_list[i].map); 2265 kfree(link_tbl->pg_list); 2266 2267 dma_free_coherent(dev, size, link_tbl->table.buf, 2268 link_tbl->table.map); 2269 } 2270 2271 static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) 2272 { 2273 struct hns_roce_v2_priv *priv = hr_dev->priv; 2274 int qpc_count, cqc_count; 2275 int ret, i; 2276 2277 /* TSQ includes SQ doorbell and ack doorbell */ 2278 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); 2279 if (ret) { 2280 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret); 2281 return ret; 2282 } 2283 2284 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); 2285 if (ret) { 2286 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret); 2287 goto err_tpq_init_failed; 2288 } 2289 2290 /* Alloc memory for QPC Timer buffer space chunk */ 2291 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; 2292 qpc_count++) { 2293 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, 2294 qpc_count); 2295 if (ret) { 2296 dev_err(hr_dev->dev, "QPC Timer get failed\n"); 2297 goto err_qpc_timer_failed; 2298 } 2299 } 2300 2301 /* Alloc memory for CQC Timer buffer space chunk */ 2302 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; 2303 cqc_count++) { 2304 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, 2305 cqc_count); 2306 if (ret) { 2307 dev_err(hr_dev->dev, "CQC Timer get failed\n"); 2308 goto err_cqc_timer_failed; 2309 } 2310 } 2311 2312 return 0; 2313 2314 err_cqc_timer_failed: 2315 for (i = 0; i < cqc_count; i++) 2316 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); 2317 2318 err_qpc_timer_failed: 2319 for (i = 0; i < qpc_count; i++) 2320 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); 2321 2322 hns_roce_free_link_table(hr_dev, &priv->tpq); 2323 2324 err_tpq_init_failed: 2325 hns_roce_free_link_table(hr_dev, &priv->tsq); 2326 2327 return ret; 2328 } 2329 2330 static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) 2331 { 2332 struct hns_roce_v2_priv *priv = hr_dev->priv; 2333 2334 hns_roce_function_clear(hr_dev); 2335 2336 hns_roce_free_link_table(hr_dev, &priv->tpq); 2337 hns_roce_free_link_table(hr_dev, &priv->tsq); 2338 } 2339 2340 static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev) 2341 { 2342 struct hns_roce_cmq_desc desc; 2343 struct hns_roce_mbox_status *mb_st = 2344 (struct hns_roce_mbox_status *)desc.data; 2345 enum hns_roce_cmd_return_status status; 2346 2347 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true); 2348 2349 status = hns_roce_cmq_send(hr_dev, &desc, 1); 2350 if (status) 2351 return status; 2352 2353 return le32_to_cpu(mb_st->mb_status_hw_run); 2354 } 2355 2356 static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) 2357 { 2358 u32 status = hns_roce_query_mbox_status(hr_dev); 2359 2360 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; 2361 } 2362 2363 static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) 2364 { 2365 u32 status = hns_roce_query_mbox_status(hr_dev); 2366 2367 return status & HNS_ROCE_HW_MB_STATUS_MASK; 2368 } 2369 2370 static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, 2371 u64 out_param, u32 in_modifier, u8 op_modifier, 2372 u16 op, u16 token, int event) 2373 { 2374 struct hns_roce_cmq_desc desc; 2375 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; 2376 2377 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); 2378 2379 mb->in_param_l = cpu_to_le32(in_param); 2380 mb->in_param_h = cpu_to_le32(in_param >> 32); 2381 mb->out_param_l = cpu_to_le32(out_param); 2382 mb->out_param_h = cpu_to_le32(out_param >> 32); 2383 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); 2384 mb->token_event_en = cpu_to_le32(event << 16 | token); 2385 2386 return hns_roce_cmq_send(hr_dev, &desc, 1); 2387 } 2388 2389 static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, 2390 u64 out_param, u32 in_modifier, u8 op_modifier, 2391 u16 op, u16 token, int event) 2392 { 2393 struct device *dev = hr_dev->dev; 2394 unsigned long end; 2395 int ret; 2396 2397 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; 2398 while (hns_roce_v2_cmd_pending(hr_dev)) { 2399 if (time_after(jiffies, end)) { 2400 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, 2401 (int)end); 2402 return -EAGAIN; 2403 } 2404 cond_resched(); 2405 } 2406 2407 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, 2408 op_modifier, op, token, event); 2409 if (ret) 2410 dev_err(dev, "Post mailbox fail(%d)\n", ret); 2411 2412 return ret; 2413 } 2414 2415 static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, 2416 unsigned long timeout) 2417 { 2418 struct device *dev = hr_dev->dev; 2419 unsigned long end; 2420 u32 status; 2421 2422 end = msecs_to_jiffies(timeout) + jiffies; 2423 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) 2424 cond_resched(); 2425 2426 if (hns_roce_v2_cmd_pending(hr_dev)) { 2427 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); 2428 return -ETIMEDOUT; 2429 } 2430 2431 status = hns_roce_v2_cmd_complete(hr_dev); 2432 if (status != 0x1) { 2433 if (status == CMD_RST_PRC_EBUSY) 2434 return status; 2435 2436 dev_err(dev, "mailbox status 0x%x!\n", status); 2437 return -EBUSY; 2438 } 2439 2440 return 0; 2441 } 2442 2443 static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev, 2444 int gid_index, const union ib_gid *gid, 2445 enum hns_roce_sgid_type sgid_type) 2446 { 2447 struct hns_roce_cmq_desc desc; 2448 struct hns_roce_cfg_sgid_tb *sgid_tb = 2449 (struct hns_roce_cfg_sgid_tb *)desc.data; 2450 u32 *p; 2451 2452 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); 2453 2454 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, 2455 CFG_SGID_TB_TABLE_IDX_S, gid_index); 2456 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, 2457 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); 2458 2459 p = (u32 *)&gid->raw[0]; 2460 sgid_tb->vf_sgid_l = cpu_to_le32(*p); 2461 2462 p = (u32 *)&gid->raw[4]; 2463 sgid_tb->vf_sgid_ml = cpu_to_le32(*p); 2464 2465 p = (u32 *)&gid->raw[8]; 2466 sgid_tb->vf_sgid_mh = cpu_to_le32(*p); 2467 2468 p = (u32 *)&gid->raw[0xc]; 2469 sgid_tb->vf_sgid_h = cpu_to_le32(*p); 2470 2471 return hns_roce_cmq_send(hr_dev, &desc, 1); 2472 } 2473 2474 static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, 2475 int gid_index, const union ib_gid *gid, 2476 const struct ib_gid_attr *attr) 2477 { 2478 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; 2479 int ret; 2480 2481 if (!gid || !attr) 2482 return -EINVAL; 2483 2484 if (attr->gid_type == IB_GID_TYPE_ROCE) 2485 sgid_type = GID_TYPE_FLAG_ROCE_V1; 2486 2487 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 2488 if (ipv6_addr_v4mapped((void *)gid)) 2489 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; 2490 else 2491 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; 2492 } 2493 2494 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type); 2495 if (ret) 2496 ibdev_err(&hr_dev->ib_dev, 2497 "failed to configure sgid table, ret = %d!\n", 2498 ret); 2499 2500 return ret; 2501 } 2502 2503 static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, 2504 u8 *addr) 2505 { 2506 struct hns_roce_cmq_desc desc; 2507 struct hns_roce_cfg_smac_tb *smac_tb = 2508 (struct hns_roce_cfg_smac_tb *)desc.data; 2509 u16 reg_smac_h; 2510 u32 reg_smac_l; 2511 2512 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); 2513 2514 reg_smac_l = *(u32 *)(&addr[0]); 2515 reg_smac_h = *(u16 *)(&addr[4]); 2516 2517 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, 2518 CFG_SMAC_TB_IDX_S, phy_port); 2519 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, 2520 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); 2521 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); 2522 2523 return hns_roce_cmq_send(hr_dev, &desc, 1); 2524 } 2525 2526 static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, 2527 struct hns_roce_v2_mpt_entry *mpt_entry, 2528 struct hns_roce_mr *mr) 2529 { 2530 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 }; 2531 struct ib_device *ibdev = &hr_dev->ib_dev; 2532 dma_addr_t pbl_ba; 2533 int i, count; 2534 2535 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages, 2536 ARRAY_SIZE(pages), &pbl_ba); 2537 if (count < 1) { 2538 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n", 2539 count); 2540 return -ENOBUFS; 2541 } 2542 2543 /* Aligned to the hardware address access unit */ 2544 for (i = 0; i < count; i++) 2545 pages[i] >>= 6; 2546 2547 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2548 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3); 2549 roce_set_field(mpt_entry->byte_48_mode_ba, 2550 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, 2551 upper_32_bits(pbl_ba >> 3)); 2552 2553 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); 2554 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, 2555 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); 2556 2557 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); 2558 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, 2559 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); 2560 roce_set_field(mpt_entry->byte_64_buf_pa1, 2561 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2562 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2563 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2564 2565 return 0; 2566 } 2567 2568 static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, 2569 void *mb_buf, struct hns_roce_mr *mr, 2570 unsigned long mtpt_idx) 2571 { 2572 struct hns_roce_v2_mpt_entry *mpt_entry; 2573 int ret; 2574 2575 mpt_entry = mb_buf; 2576 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2577 2578 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2579 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2580 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2581 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == 2582 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); 2583 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2584 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2585 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2586 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2587 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2588 V2_MPT_BYTE_4_PD_S, mr->pd); 2589 2590 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); 2591 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0); 2592 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2593 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, 2594 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); 2595 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 2596 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2597 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2598 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); 2599 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2600 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); 2601 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2602 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); 2603 2604 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 2605 mr->type == MR_TYPE_MR ? 0 : 1); 2606 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, 2607 1); 2608 2609 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); 2610 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); 2611 mpt_entry->lkey = cpu_to_le32(mr->key); 2612 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); 2613 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); 2614 2615 if (mr->type == MR_TYPE_DMA) 2616 return 0; 2617 2618 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2619 2620 return ret; 2621 } 2622 2623 static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, 2624 struct hns_roce_mr *mr, int flags, 2625 u32 pdn, int mr_access_flags, u64 iova, 2626 u64 size, void *mb_buf) 2627 { 2628 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; 2629 int ret = 0; 2630 2631 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2632 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); 2633 2634 if (flags & IB_MR_REREG_PD) { 2635 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2636 V2_MPT_BYTE_4_PD_S, pdn); 2637 mr->pd = pdn; 2638 } 2639 2640 if (flags & IB_MR_REREG_ACCESS) { 2641 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2642 V2_MPT_BYTE_8_BIND_EN_S, 2643 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); 2644 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, 2645 V2_MPT_BYTE_8_ATOMIC_EN_S, 2646 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); 2647 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, 2648 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); 2649 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, 2650 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); 2651 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, 2652 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); 2653 } 2654 2655 if (flags & IB_MR_REREG_TRANS) { 2656 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); 2657 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); 2658 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); 2659 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); 2660 2661 mr->iova = iova; 2662 mr->size = size; 2663 2664 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr); 2665 } 2666 2667 return ret; 2668 } 2669 2670 static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev, 2671 void *mb_buf, struct hns_roce_mr *mr) 2672 { 2673 struct ib_device *ibdev = &hr_dev->ib_dev; 2674 struct hns_roce_v2_mpt_entry *mpt_entry; 2675 dma_addr_t pbl_ba = 0; 2676 2677 mpt_entry = mb_buf; 2678 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2679 2680 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) { 2681 ibdev_err(ibdev, "failed to find frmr mtr.\n"); 2682 return -ENOBUFS; 2683 } 2684 2685 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2686 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2687 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2688 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); 2689 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2690 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2691 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2692 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift)); 2693 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2694 V2_MPT_BYTE_4_PD_S, mr->pd); 2695 2696 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); 2697 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2698 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2699 2700 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); 2701 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2702 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); 2703 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2704 2705 mpt_entry->pbl_size = cpu_to_le32(mr->npages); 2706 2707 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3)); 2708 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, 2709 V2_MPT_BYTE_48_PBL_BA_H_S, 2710 upper_32_bits(pbl_ba >> 3)); 2711 2712 roce_set_field(mpt_entry->byte_64_buf_pa1, 2713 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2714 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2715 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift)); 2716 2717 return 0; 2718 } 2719 2720 static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) 2721 { 2722 struct hns_roce_v2_mpt_entry *mpt_entry; 2723 2724 mpt_entry = mb_buf; 2725 memset(mpt_entry, 0, sizeof(*mpt_entry)); 2726 2727 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, 2728 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); 2729 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, 2730 V2_MPT_BYTE_4_PD_S, mw->pdn); 2731 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, 2732 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 2733 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : 2734 mw->pbl_hop_num); 2735 roce_set_field(mpt_entry->byte_4_pd_hop_st, 2736 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, 2737 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, 2738 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); 2739 2740 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); 2741 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); 2742 2743 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); 2744 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); 2745 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); 2746 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, 2747 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); 2748 2749 roce_set_field(mpt_entry->byte_64_buf_pa1, 2750 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, 2751 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, 2752 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); 2753 2754 mpt_entry->lkey = cpu_to_le32(mw->rkey); 2755 2756 return 0; 2757 } 2758 2759 static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2760 { 2761 return hns_roce_buf_offset(hr_cq->mtr.kmem, 2762 n * HNS_ROCE_V2_CQE_ENTRY_SIZE); 2763 } 2764 2765 static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) 2766 { 2767 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); 2768 2769 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ 2770 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ 2771 !!(n & hr_cq->cq_depth)) ? cqe : NULL; 2772 } 2773 2774 static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci) 2775 { 2776 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M; 2777 } 2778 2779 static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2780 struct hns_roce_srq *srq) 2781 { 2782 struct hns_roce_v2_cqe *cqe, *dest; 2783 u32 prod_index; 2784 int nfreed = 0; 2785 int wqe_index; 2786 u8 owner_bit; 2787 2788 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); 2789 ++prod_index) { 2790 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) 2791 break; 2792 } 2793 2794 /* 2795 * Now backwards through the CQ, removing CQ entries 2796 * that match our QP by overwriting them with next entries. 2797 */ 2798 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 2799 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); 2800 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 2801 V2_CQE_BYTE_16_LCL_QPN_S) & 2802 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { 2803 if (srq && 2804 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) { 2805 wqe_index = roce_get_field(cqe->byte_4, 2806 V2_CQE_BYTE_4_WQE_INDX_M, 2807 V2_CQE_BYTE_4_WQE_INDX_S); 2808 hns_roce_free_srq_wqe(srq, wqe_index); 2809 } 2810 ++nfreed; 2811 } else if (nfreed) { 2812 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & 2813 hr_cq->ib_cq.cqe); 2814 owner_bit = roce_get_bit(dest->byte_4, 2815 V2_CQE_BYTE_4_OWNER_S); 2816 memcpy(dest, cqe, sizeof(*cqe)); 2817 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, 2818 owner_bit); 2819 } 2820 } 2821 2822 if (nfreed) { 2823 hr_cq->cons_index += nfreed; 2824 /* 2825 * Make sure update of buffer contents is done before 2826 * updating consumer index. 2827 */ 2828 wmb(); 2829 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 2830 } 2831 } 2832 2833 static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, 2834 struct hns_roce_srq *srq) 2835 { 2836 spin_lock_irq(&hr_cq->lock); 2837 __hns_roce_v2_cq_clean(hr_cq, qpn, srq); 2838 spin_unlock_irq(&hr_cq->lock); 2839 } 2840 2841 static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, 2842 struct hns_roce_cq *hr_cq, void *mb_buf, 2843 u64 *mtts, dma_addr_t dma_handle) 2844 { 2845 struct hns_roce_v2_cq_context *cq_context; 2846 2847 cq_context = mb_buf; 2848 memset(cq_context, 0, sizeof(*cq_context)); 2849 2850 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, 2851 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); 2852 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, 2853 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); 2854 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, 2855 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); 2856 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, 2857 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); 2858 2859 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, 2860 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); 2861 2862 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 2863 2864 roce_set_field(cq_context->byte_16_hop_addr, 2865 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, 2866 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, 2867 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 2868 roce_set_field(cq_context->byte_16_hop_addr, 2869 V2_CQC_BYTE_16_CQE_HOP_NUM_M, 2870 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == 2871 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); 2872 2873 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 2874 roce_set_field(cq_context->byte_24_pgsz_addr, 2875 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, 2876 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, 2877 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 2878 roce_set_field(cq_context->byte_24_pgsz_addr, 2879 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, 2880 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, 2881 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); 2882 roce_set_field(cq_context->byte_24_pgsz_addr, 2883 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, 2884 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, 2885 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); 2886 2887 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); 2888 2889 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, 2890 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); 2891 2892 roce_set_bit(cq_context->byte_44_db_record, 2893 V2_CQC_BYTE_44_DB_RECORD_EN_S, 2894 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0); 2895 2896 roce_set_field(cq_context->byte_44_db_record, 2897 V2_CQC_BYTE_44_DB_RECORD_ADDR_M, 2898 V2_CQC_BYTE_44_DB_RECORD_ADDR_S, 2899 ((u32)hr_cq->db.dma) >> 1); 2900 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); 2901 2902 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2903 V2_CQC_BYTE_56_CQ_MAX_CNT_M, 2904 V2_CQC_BYTE_56_CQ_MAX_CNT_S, 2905 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); 2906 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 2907 V2_CQC_BYTE_56_CQ_PERIOD_M, 2908 V2_CQC_BYTE_56_CQ_PERIOD_S, 2909 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); 2910 } 2911 2912 static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, 2913 enum ib_cq_notify_flags flags) 2914 { 2915 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 2916 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 2917 u32 notification_flag; 2918 __le32 doorbell[2]; 2919 2920 doorbell[0] = 0; 2921 doorbell[1] = 0; 2922 2923 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? 2924 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; 2925 /* 2926 * flags = 0; Notification Flag = 1, next 2927 * flags = 1; Notification Flag = 0, solocited 2928 */ 2929 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, 2930 hr_cq->cqn); 2931 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, 2932 HNS_ROCE_V2_CQ_DB_NTR); 2933 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, 2934 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index); 2935 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, 2936 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); 2937 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, 2938 notification_flag); 2939 2940 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l); 2941 2942 return 0; 2943 } 2944 2945 static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, 2946 struct hns_roce_qp **cur_qp, 2947 struct ib_wc *wc) 2948 { 2949 struct hns_roce_rinl_sge *sge_list; 2950 u32 wr_num, wr_cnt, sge_num; 2951 u32 sge_cnt, data_len, size; 2952 void *wqe_buf; 2953 2954 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, 2955 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; 2956 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); 2957 2958 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; 2959 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; 2960 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt); 2961 data_len = wc->byte_len; 2962 2963 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { 2964 size = min(sge_list[sge_cnt].len, data_len); 2965 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); 2966 2967 data_len -= size; 2968 wqe_buf += size; 2969 } 2970 2971 if (unlikely(data_len)) { 2972 wc->status = IB_WC_LOC_LEN_ERR; 2973 return -EAGAIN; 2974 } 2975 2976 return 0; 2977 } 2978 2979 static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, 2980 int num_entries, struct ib_wc *wc) 2981 { 2982 unsigned int left; 2983 int npolled = 0; 2984 2985 left = wq->head - wq->tail; 2986 if (left == 0) 2987 return 0; 2988 2989 left = min_t(unsigned int, (unsigned int)num_entries, left); 2990 while (npolled < left) { 2991 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 2992 wc->status = IB_WC_WR_FLUSH_ERR; 2993 wc->vendor_err = 0; 2994 wc->qp = &hr_qp->ibqp; 2995 2996 wq->tail++; 2997 wc++; 2998 npolled++; 2999 } 3000 3001 return npolled; 3002 } 3003 3004 static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, 3005 struct ib_wc *wc) 3006 { 3007 struct hns_roce_qp *hr_qp; 3008 int npolled = 0; 3009 3010 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { 3011 npolled += sw_comp(hr_qp, &hr_qp->sq, 3012 num_entries - npolled, wc + npolled); 3013 if (npolled >= num_entries) 3014 goto out; 3015 } 3016 3017 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { 3018 npolled += sw_comp(hr_qp, &hr_qp->rq, 3019 num_entries - npolled, wc + npolled); 3020 if (npolled >= num_entries) 3021 goto out; 3022 } 3023 3024 out: 3025 return npolled; 3026 } 3027 3028 static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, 3029 struct hns_roce_v2_cqe *cqe, struct ib_wc *wc) 3030 { 3031 static const struct { 3032 u32 cqe_status; 3033 enum ib_wc_status wc_status; 3034 } map[] = { 3035 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, 3036 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, 3037 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, 3038 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, 3039 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, 3040 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, 3041 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, 3042 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, 3043 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, 3044 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, 3045 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, 3046 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, 3047 IB_WC_RETRY_EXC_ERR }, 3048 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, 3049 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, 3050 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR} 3051 }; 3052 3053 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, 3054 V2_CQE_BYTE_4_STATUS_S); 3055 int i; 3056 3057 wc->status = IB_WC_GENERAL_ERR; 3058 for (i = 0; i < ARRAY_SIZE(map); i++) 3059 if (cqe_status == map[i].cqe_status) { 3060 wc->status = map[i].wc_status; 3061 break; 3062 } 3063 3064 if (likely(wc->status == IB_WC_SUCCESS || 3065 wc->status == IB_WC_WR_FLUSH_ERR)) 3066 return; 3067 3068 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); 3069 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, 3070 sizeof(*cqe), false); 3071 3072 /* 3073 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in 3074 * the standard protocol, the driver must ignore it and needn't to set 3075 * the QP to an error state. 3076 */ 3077 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR) 3078 return; 3079 3080 /* 3081 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets 3082 * into errored mode. Hence, as a workaround to this hardware 3083 * limitation, driver needs to assist in flushing. But the flushing 3084 * operation uses mailbox to convey the QP state to the hardware and 3085 * which can sleep due to the mutex protection around the mailbox calls. 3086 * Hence, use the deferred flush for now. Once wc error detected, the 3087 * flushing operation is needed. 3088 */ 3089 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) 3090 init_flush_work(hr_dev, qp); 3091 } 3092 3093 static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, 3094 struct hns_roce_qp **cur_qp, struct ib_wc *wc) 3095 { 3096 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); 3097 struct hns_roce_srq *srq = NULL; 3098 struct hns_roce_v2_cqe *cqe; 3099 struct hns_roce_qp *hr_qp; 3100 struct hns_roce_wq *wq; 3101 int is_send; 3102 u16 wqe_ctr; 3103 u32 opcode; 3104 int qpn; 3105 int ret; 3106 3107 /* Find cqe according to consumer index */ 3108 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index); 3109 if (!cqe) 3110 return -EAGAIN; 3111 3112 ++hr_cq->cons_index; 3113 /* Memory barrier */ 3114 rmb(); 3115 3116 /* 0->SQ, 1->RQ */ 3117 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); 3118 3119 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, 3120 V2_CQE_BYTE_16_LCL_QPN_S); 3121 3122 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { 3123 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); 3124 if (unlikely(!hr_qp)) { 3125 ibdev_err(&hr_dev->ib_dev, 3126 "CQ %06lx with entry for unknown QPN %06x\n", 3127 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK); 3128 return -EINVAL; 3129 } 3130 *cur_qp = hr_qp; 3131 } 3132 3133 wc->qp = &(*cur_qp)->ibqp; 3134 wc->vendor_err = 0; 3135 3136 if (is_send) { 3137 wq = &(*cur_qp)->sq; 3138 if ((*cur_qp)->sq_signal_bits) { 3139 /* 3140 * If sg_signal_bit is 1, 3141 * firstly tail pointer updated to wqe 3142 * which current cqe correspond to 3143 */ 3144 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3145 V2_CQE_BYTE_4_WQE_INDX_M, 3146 V2_CQE_BYTE_4_WQE_INDX_S); 3147 wq->tail += (wqe_ctr - (u16)wq->tail) & 3148 (wq->wqe_cnt - 1); 3149 } 3150 3151 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3152 ++wq->tail; 3153 } else if ((*cur_qp)->ibqp.srq) { 3154 srq = to_hr_srq((*cur_qp)->ibqp.srq); 3155 wqe_ctr = (u16)roce_get_field(cqe->byte_4, 3156 V2_CQE_BYTE_4_WQE_INDX_M, 3157 V2_CQE_BYTE_4_WQE_INDX_S); 3158 wc->wr_id = srq->wrid[wqe_ctr]; 3159 hns_roce_free_srq_wqe(srq, wqe_ctr); 3160 } else { 3161 /* Update tail pointer, record wr_id */ 3162 wq = &(*cur_qp)->rq; 3163 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; 3164 ++wq->tail; 3165 } 3166 3167 get_cqe_status(hr_dev, *cur_qp, cqe, wc); 3168 if (unlikely(wc->status != IB_WC_SUCCESS)) 3169 return 0; 3170 3171 if (is_send) { 3172 wc->wc_flags = 0; 3173 /* SQ corresponding to CQE */ 3174 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3175 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { 3176 case HNS_ROCE_V2_WQE_OP_SEND: 3177 wc->opcode = IB_WC_SEND; 3178 break; 3179 case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV: 3180 wc->opcode = IB_WC_SEND; 3181 break; 3182 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM: 3183 wc->opcode = IB_WC_SEND; 3184 wc->wc_flags |= IB_WC_WITH_IMM; 3185 break; 3186 case HNS_ROCE_V2_WQE_OP_RDMA_READ: 3187 wc->opcode = IB_WC_RDMA_READ; 3188 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3189 break; 3190 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE: 3191 wc->opcode = IB_WC_RDMA_WRITE; 3192 break; 3193 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM: 3194 wc->opcode = IB_WC_RDMA_WRITE; 3195 wc->wc_flags |= IB_WC_WITH_IMM; 3196 break; 3197 case HNS_ROCE_V2_WQE_OP_LOCAL_INV: 3198 wc->opcode = IB_WC_LOCAL_INV; 3199 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 3200 break; 3201 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP: 3202 wc->opcode = IB_WC_COMP_SWAP; 3203 wc->byte_len = 8; 3204 break; 3205 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD: 3206 wc->opcode = IB_WC_FETCH_ADD; 3207 wc->byte_len = 8; 3208 break; 3209 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP: 3210 wc->opcode = IB_WC_MASKED_COMP_SWAP; 3211 wc->byte_len = 8; 3212 break; 3213 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD: 3214 wc->opcode = IB_WC_MASKED_FETCH_ADD; 3215 wc->byte_len = 8; 3216 break; 3217 case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR: 3218 wc->opcode = IB_WC_REG_MR; 3219 break; 3220 case HNS_ROCE_V2_WQE_OP_BIND_MW: 3221 wc->opcode = IB_WC_REG_MR; 3222 break; 3223 default: 3224 wc->status = IB_WC_GENERAL_ERR; 3225 break; 3226 } 3227 } else { 3228 /* RQ correspond to CQE */ 3229 wc->byte_len = le32_to_cpu(cqe->byte_cnt); 3230 3231 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, 3232 V2_CQE_BYTE_4_OPCODE_S); 3233 switch (opcode & 0x1f) { 3234 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: 3235 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 3236 wc->wc_flags = IB_WC_WITH_IMM; 3237 wc->ex.imm_data = 3238 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3239 break; 3240 case HNS_ROCE_V2_OPCODE_SEND: 3241 wc->opcode = IB_WC_RECV; 3242 wc->wc_flags = 0; 3243 break; 3244 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: 3245 wc->opcode = IB_WC_RECV; 3246 wc->wc_flags = IB_WC_WITH_IMM; 3247 wc->ex.imm_data = 3248 cpu_to_be32(le32_to_cpu(cqe->immtdata)); 3249 break; 3250 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: 3251 wc->opcode = IB_WC_RECV; 3252 wc->wc_flags = IB_WC_WITH_INVALIDATE; 3253 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); 3254 break; 3255 default: 3256 wc->status = IB_WC_GENERAL_ERR; 3257 break; 3258 } 3259 3260 if ((wc->qp->qp_type == IB_QPT_RC || 3261 wc->qp->qp_type == IB_QPT_UC) && 3262 (opcode == HNS_ROCE_V2_OPCODE_SEND || 3263 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || 3264 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && 3265 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { 3266 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); 3267 if (unlikely(ret)) 3268 return -EAGAIN; 3269 } 3270 3271 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, 3272 V2_CQE_BYTE_32_SL_S); 3273 wc->src_qp = (u8)roce_get_field(cqe->byte_32, 3274 V2_CQE_BYTE_32_RMT_QPN_M, 3275 V2_CQE_BYTE_32_RMT_QPN_S); 3276 wc->slid = 0; 3277 wc->wc_flags |= (roce_get_bit(cqe->byte_32, 3278 V2_CQE_BYTE_32_GRH_S) ? 3279 IB_WC_GRH : 0); 3280 wc->port_num = roce_get_field(cqe->byte_32, 3281 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); 3282 wc->pkey_index = 0; 3283 3284 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) { 3285 wc->vlan_id = (u16)roce_get_field(cqe->byte_28, 3286 V2_CQE_BYTE_28_VID_M, 3287 V2_CQE_BYTE_28_VID_S); 3288 wc->wc_flags |= IB_WC_WITH_VLAN; 3289 } else { 3290 wc->vlan_id = 0xffff; 3291 } 3292 3293 wc->network_hdr_type = roce_get_field(cqe->byte_28, 3294 V2_CQE_BYTE_28_PORT_TYPE_M, 3295 V2_CQE_BYTE_28_PORT_TYPE_S); 3296 } 3297 3298 return 0; 3299 } 3300 3301 static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, 3302 struct ib_wc *wc) 3303 { 3304 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); 3305 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); 3306 struct hns_roce_qp *cur_qp = NULL; 3307 unsigned long flags; 3308 int npolled; 3309 3310 spin_lock_irqsave(&hr_cq->lock, flags); 3311 3312 /* 3313 * When the device starts to reset, the state is RST_DOWN. At this time, 3314 * there may still be some valid CQEs in the hardware that are not 3315 * polled. Therefore, it is not allowed to switch to the software mode 3316 * immediately. When the state changes to UNINIT, CQE no longer exists 3317 * in the hardware, and then switch to software mode. 3318 */ 3319 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { 3320 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); 3321 goto out; 3322 } 3323 3324 for (npolled = 0; npolled < num_entries; ++npolled) { 3325 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) 3326 break; 3327 } 3328 3329 if (npolled) { 3330 /* Memory barrier */ 3331 wmb(); 3332 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); 3333 } 3334 3335 out: 3336 spin_unlock_irqrestore(&hr_cq->lock, flags); 3337 3338 return npolled; 3339 } 3340 3341 static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, 3342 int step_idx) 3343 { 3344 int op; 3345 3346 if (type == HEM_TYPE_SCCC && step_idx) 3347 return -EINVAL; 3348 3349 switch (type) { 3350 case HEM_TYPE_QPC: 3351 op = HNS_ROCE_CMD_WRITE_QPC_BT0; 3352 break; 3353 case HEM_TYPE_MTPT: 3354 op = HNS_ROCE_CMD_WRITE_MPT_BT0; 3355 break; 3356 case HEM_TYPE_CQC: 3357 op = HNS_ROCE_CMD_WRITE_CQC_BT0; 3358 break; 3359 case HEM_TYPE_SRQC: 3360 op = HNS_ROCE_CMD_WRITE_SRQC_BT0; 3361 break; 3362 case HEM_TYPE_SCCC: 3363 op = HNS_ROCE_CMD_WRITE_SCCC_BT0; 3364 break; 3365 case HEM_TYPE_QPC_TIMER: 3366 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; 3367 break; 3368 case HEM_TYPE_CQC_TIMER: 3369 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; 3370 break; 3371 default: 3372 dev_warn(hr_dev->dev, 3373 "Table %d not to be written by mailbox!\n", type); 3374 return -EINVAL; 3375 } 3376 3377 return op + step_idx; 3378 } 3379 3380 static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba, 3381 u32 hem_type, int step_idx) 3382 { 3383 struct hns_roce_cmd_mailbox *mailbox; 3384 int ret; 3385 int op; 3386 3387 op = get_op_for_set_hem(hr_dev, hem_type, step_idx); 3388 if (op < 0) 3389 return 0; 3390 3391 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3392 if (IS_ERR(mailbox)) 3393 return PTR_ERR(mailbox); 3394 3395 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, 3396 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); 3397 3398 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3399 3400 return ret; 3401 } 3402 3403 static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, 3404 struct hns_roce_hem_table *table, int obj, 3405 int step_idx) 3406 { 3407 struct hns_roce_hem_iter iter; 3408 struct hns_roce_hem_mhop mhop; 3409 struct hns_roce_hem *hem; 3410 unsigned long mhop_obj = obj; 3411 int i, j, k; 3412 int ret = 0; 3413 u64 hem_idx = 0; 3414 u64 l1_idx = 0; 3415 u64 bt_ba = 0; 3416 u32 chunk_ba_num; 3417 u32 hop_num; 3418 3419 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3420 return 0; 3421 3422 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); 3423 i = mhop.l0_idx; 3424 j = mhop.l1_idx; 3425 k = mhop.l2_idx; 3426 hop_num = mhop.hop_num; 3427 chunk_ba_num = mhop.bt_chunk_size / 8; 3428 3429 if (hop_num == 2) { 3430 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + 3431 k; 3432 l1_idx = i * chunk_ba_num + j; 3433 } else if (hop_num == 1) { 3434 hem_idx = i * chunk_ba_num + j; 3435 } else if (hop_num == HNS_ROCE_HOP_NUM_0) { 3436 hem_idx = i; 3437 } 3438 3439 if (table->type == HEM_TYPE_SCCC) 3440 obj = mhop.l0_idx; 3441 3442 if (check_whether_last_step(hop_num, step_idx)) { 3443 hem = table->hem[hem_idx]; 3444 for (hns_roce_hem_first(hem, &iter); 3445 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { 3446 bt_ba = hns_roce_hem_addr(&iter); 3447 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, 3448 step_idx); 3449 } 3450 } else { 3451 if (step_idx == 0) 3452 bt_ba = table->bt_l0_dma_addr[i]; 3453 else if (step_idx == 1 && hop_num == 2) 3454 bt_ba = table->bt_l1_dma_addr[l1_idx]; 3455 3456 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx); 3457 } 3458 3459 return ret; 3460 } 3461 3462 static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, 3463 struct hns_roce_hem_table *table, int obj, 3464 int step_idx) 3465 { 3466 struct device *dev = hr_dev->dev; 3467 struct hns_roce_cmd_mailbox *mailbox; 3468 int ret; 3469 u16 op = 0xff; 3470 3471 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) 3472 return 0; 3473 3474 switch (table->type) { 3475 case HEM_TYPE_QPC: 3476 op = HNS_ROCE_CMD_DESTROY_QPC_BT0; 3477 break; 3478 case HEM_TYPE_MTPT: 3479 op = HNS_ROCE_CMD_DESTROY_MPT_BT0; 3480 break; 3481 case HEM_TYPE_CQC: 3482 op = HNS_ROCE_CMD_DESTROY_CQC_BT0; 3483 break; 3484 case HEM_TYPE_SCCC: 3485 case HEM_TYPE_QPC_TIMER: 3486 case HEM_TYPE_CQC_TIMER: 3487 break; 3488 case HEM_TYPE_SRQC: 3489 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; 3490 break; 3491 default: 3492 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", 3493 table->type); 3494 return 0; 3495 } 3496 3497 if (table->type == HEM_TYPE_SCCC || 3498 table->type == HEM_TYPE_QPC_TIMER || 3499 table->type == HEM_TYPE_CQC_TIMER) 3500 return 0; 3501 3502 op += step_idx; 3503 3504 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3505 if (IS_ERR(mailbox)) 3506 return PTR_ERR(mailbox); 3507 3508 /* configure the tag and op */ 3509 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, 3510 HNS_ROCE_CMD_TIMEOUT_MSECS); 3511 3512 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3513 return ret; 3514 } 3515 3516 static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, 3517 struct hns_roce_v2_qp_context *context, 3518 struct hns_roce_qp *hr_qp) 3519 { 3520 struct hns_roce_cmd_mailbox *mailbox; 3521 int ret; 3522 3523 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 3524 if (IS_ERR(mailbox)) 3525 return PTR_ERR(mailbox); 3526 3527 memcpy(mailbox->buf, context, sizeof(*context) * 2); 3528 3529 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 3530 HNS_ROCE_CMD_MODIFY_QPC, 3531 HNS_ROCE_CMD_TIMEOUT_MSECS); 3532 3533 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 3534 3535 return ret; 3536 } 3537 3538 static void set_access_flags(struct hns_roce_qp *hr_qp, 3539 struct hns_roce_v2_qp_context *context, 3540 struct hns_roce_v2_qp_context *qpc_mask, 3541 const struct ib_qp_attr *attr, int attr_mask) 3542 { 3543 u8 dest_rd_atomic; 3544 u32 access_flags; 3545 3546 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? 3547 attr->max_dest_rd_atomic : hr_qp->resp_depth; 3548 3549 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? 3550 attr->qp_access_flags : hr_qp->atomic_rd_en; 3551 3552 if (!dest_rd_atomic) 3553 access_flags &= IB_ACCESS_REMOTE_WRITE; 3554 3555 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3556 !!(access_flags & IB_ACCESS_REMOTE_READ)); 3557 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); 3558 3559 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3560 !!(access_flags & IB_ACCESS_REMOTE_WRITE)); 3561 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); 3562 3563 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3564 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3565 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); 3566 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 3567 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3568 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0); 3569 } 3570 3571 static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, 3572 struct hns_roce_v2_qp_context *context, 3573 struct hns_roce_v2_qp_context *qpc_mask) 3574 { 3575 roce_set_field(context->byte_4_sqpn_tst, 3576 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S, 3577 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt, 3578 hr_qp->sge.sge_shift)); 3579 3580 roce_set_field(context->byte_20_smac_sgid_idx, 3581 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 3582 ilog2(hr_qp->sq.wqe_cnt)); 3583 3584 roce_set_field(context->byte_20_smac_sgid_idx, 3585 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 3586 ilog2(hr_qp->rq.wqe_cnt)); 3587 } 3588 3589 static void modify_qp_reset_to_init(struct ib_qp *ibqp, 3590 const struct ib_qp_attr *attr, 3591 int attr_mask, 3592 struct hns_roce_v2_qp_context *context, 3593 struct hns_roce_v2_qp_context *qpc_mask) 3594 { 3595 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3596 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3597 3598 /* 3599 * In v2 engine, software pass context and context mask to hardware 3600 * when modifying qp. If software need modify some fields in context, 3601 * we should set all bits of the relevant fields in context mask to 3602 * 0 at the same time, else set them to 0x1. 3603 */ 3604 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3605 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3606 3607 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3608 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3609 3610 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3611 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3612 3613 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, 3614 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); 3615 3616 set_qpc_wqe_cnt(hr_qp, context, qpc_mask); 3617 3618 /* No VLAN need to set 0xFFF */ 3619 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 3620 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); 3621 3622 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB) 3623 roce_set_bit(context->byte_68_rq_db, 3624 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); 3625 3626 roce_set_field(context->byte_68_rq_db, 3627 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, 3628 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 3629 ((u32)hr_qp->rdb.dma) >> 1); 3630 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32); 3631 3632 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 3633 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); 3634 3635 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3636 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3637 if (ibqp->srq) { 3638 roce_set_field(context->byte_76_srqn_op_en, 3639 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3640 to_hr_srq(ibqp->srq)->srqn); 3641 roce_set_bit(context->byte_76_srqn_op_en, 3642 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3643 } 3644 3645 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, 3646 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); 3647 3648 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); 3649 3650 hr_qp->access_flags = attr->qp_access_flags; 3651 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3652 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3653 } 3654 3655 static void modify_qp_init_to_init(struct ib_qp *ibqp, 3656 const struct ib_qp_attr *attr, int attr_mask, 3657 struct hns_roce_v2_qp_context *context, 3658 struct hns_roce_v2_qp_context *qpc_mask) 3659 { 3660 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3661 3662 /* 3663 * In v2 engine, software pass context and context mask to hardware 3664 * when modifying qp. If software need modify some fields in context, 3665 * we should set all bits of the relevant fields in context mask to 3666 * 0 at the same time, else set them to 0x1. 3667 */ 3668 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3669 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); 3670 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, 3671 V2_QPC_BYTE_4_TST_S, 0); 3672 3673 if (attr_mask & IB_QP_ACCESS_FLAGS) { 3674 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3675 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); 3676 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3677 0); 3678 3679 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3680 !!(attr->qp_access_flags & 3681 IB_ACCESS_REMOTE_WRITE)); 3682 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3683 0); 3684 3685 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3686 !!(attr->qp_access_flags & 3687 IB_ACCESS_REMOTE_ATOMIC)); 3688 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3689 0); 3690 roce_set_bit(context->byte_76_srqn_op_en, 3691 V2_QPC_BYTE_76_EXT_ATE_S, 3692 !!(attr->qp_access_flags & 3693 IB_ACCESS_REMOTE_ATOMIC)); 3694 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3695 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3696 } else { 3697 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3698 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); 3699 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 3700 0); 3701 3702 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3703 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); 3704 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 3705 0); 3706 3707 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3708 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3709 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 3710 0); 3711 roce_set_bit(context->byte_76_srqn_op_en, 3712 V2_QPC_BYTE_76_EXT_ATE_S, 3713 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); 3714 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3715 V2_QPC_BYTE_76_EXT_ATE_S, 0); 3716 } 3717 3718 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3719 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); 3720 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, 3721 V2_QPC_BYTE_16_PD_S, 0); 3722 3723 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3724 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); 3725 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, 3726 V2_QPC_BYTE_80_RX_CQN_S, 0); 3727 3728 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3729 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); 3730 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, 3731 V2_QPC_BYTE_252_TX_CQN_S, 0); 3732 3733 if (ibqp->srq) { 3734 roce_set_bit(context->byte_76_srqn_op_en, 3735 V2_QPC_BYTE_76_SRQ_EN_S, 1); 3736 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 3737 V2_QPC_BYTE_76_SRQ_EN_S, 0); 3738 roce_set_field(context->byte_76_srqn_op_en, 3739 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 3740 to_hr_srq(ibqp->srq)->srqn); 3741 roce_set_field(qpc_mask->byte_76_srqn_op_en, 3742 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); 3743 } 3744 3745 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3746 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); 3747 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, 3748 V2_QPC_BYTE_4_SQPN_S, 0); 3749 3750 if (attr_mask & IB_QP_DEST_QPN) { 3751 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 3752 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); 3753 roce_set_field(qpc_mask->byte_56_dqpn_err, 3754 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 3755 } 3756 } 3757 3758 static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, 3759 struct hns_roce_qp *hr_qp, 3760 struct hns_roce_v2_qp_context *context, 3761 struct hns_roce_v2_qp_context *qpc_mask) 3762 { 3763 u64 mtts[MTT_MIN_COUNT] = { 0 }; 3764 u64 wqe_sge_ba; 3765 int count; 3766 3767 /* Search qp buf's mtts */ 3768 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts, 3769 MTT_MIN_COUNT, &wqe_sge_ba); 3770 if (hr_qp->rq.wqe_cnt && count < 1) { 3771 ibdev_err(&hr_dev->ib_dev, 3772 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn); 3773 return -EINVAL; 3774 } 3775 3776 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); 3777 qpc_mask->wqe_sge_ba = 0; 3778 3779 /* 3780 * In v2 engine, software pass context and context mask to hardware 3781 * when modifying qp. If software need modify some fields in context, 3782 * we should set all bits of the relevant fields in context mask to 3783 * 0 at the same time, else set them to 0x1. 3784 */ 3785 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3786 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3)); 3787 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, 3788 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); 3789 3790 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3791 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 3792 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num, 3793 hr_qp->sq.wqe_cnt)); 3794 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, 3795 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); 3796 3797 roce_set_field(context->byte_20_smac_sgid_idx, 3798 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3799 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 3800 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num, 3801 hr_qp->sge.sge_cnt)); 3802 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3803 V2_QPC_BYTE_20_SGE_HOP_NUM_M, 3804 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); 3805 3806 roce_set_field(context->byte_20_smac_sgid_idx, 3807 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3808 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 3809 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num, 3810 hr_qp->rq.wqe_cnt)); 3811 3812 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 3813 V2_QPC_BYTE_20_RQ_HOP_NUM_M, 3814 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); 3815 3816 roce_set_field(context->byte_16_buf_ba_pg_sz, 3817 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3818 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 3819 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); 3820 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3821 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, 3822 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); 3823 3824 roce_set_field(context->byte_16_buf_ba_pg_sz, 3825 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3826 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 3827 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); 3828 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, 3829 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, 3830 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); 3831 3832 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); 3833 qpc_mask->rq_cur_blk_addr = 0; 3834 3835 roce_set_field(context->byte_92_srq_info, 3836 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3837 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 3838 upper_32_bits(to_hr_hw_page_addr(mtts[0]))); 3839 roce_set_field(qpc_mask->byte_92_srq_info, 3840 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, 3841 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); 3842 3843 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); 3844 qpc_mask->rq_nxt_blk_addr = 0; 3845 3846 roce_set_field(context->byte_104_rq_sge, 3847 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3848 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 3849 upper_32_bits(to_hr_hw_page_addr(mtts[1]))); 3850 roce_set_field(qpc_mask->byte_104_rq_sge, 3851 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, 3852 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); 3853 3854 roce_set_field(context->byte_84_rq_ci_pi, 3855 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3856 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); 3857 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3858 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 3859 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 3860 3861 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 3862 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, 3863 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); 3864 3865 return 0; 3866 } 3867 3868 static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, 3869 struct hns_roce_qp *hr_qp, 3870 struct hns_roce_v2_qp_context *context, 3871 struct hns_roce_v2_qp_context *qpc_mask) 3872 { 3873 struct ib_device *ibdev = &hr_dev->ib_dev; 3874 u64 sge_cur_blk = 0; 3875 u64 sq_cur_blk = 0; 3876 int count; 3877 3878 /* search qp buf's mtts */ 3879 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); 3880 if (count < 1) { 3881 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n", 3882 hr_qp->qpn); 3883 return -EINVAL; 3884 } 3885 if (hr_qp->sge.sge_cnt > 0) { 3886 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 3887 hr_qp->sge.offset, 3888 &sge_cur_blk, 1, NULL); 3889 if (count < 1) { 3890 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n", 3891 hr_qp->qpn); 3892 return -EINVAL; 3893 } 3894 } 3895 3896 /* 3897 * In v2 engine, software pass context and context mask to hardware 3898 * when modifying qp. If software need modify some fields in context, 3899 * we should set all bits of the relevant fields in context mask to 3900 * 0 at the same time, else set them to 0x1. 3901 */ 3902 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3903 roce_set_field(context->byte_168_irrl_idx, 3904 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3905 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 3906 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3907 qpc_mask->sq_cur_blk_addr = 0; 3908 roce_set_field(qpc_mask->byte_168_irrl_idx, 3909 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, 3910 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); 3911 3912 context->sq_cur_sge_blk_addr = 3913 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)); 3914 roce_set_field(context->byte_184_irrl_idx, 3915 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3916 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 3917 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk))); 3918 qpc_mask->sq_cur_sge_blk_addr = 0; 3919 roce_set_field(qpc_mask->byte_184_irrl_idx, 3920 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, 3921 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); 3922 3923 context->rx_sq_cur_blk_addr = 3924 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); 3925 roce_set_field(context->byte_232_irrl_sge, 3926 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3927 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 3928 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); 3929 qpc_mask->rx_sq_cur_blk_addr = 0; 3930 roce_set_field(qpc_mask->byte_232_irrl_sge, 3931 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, 3932 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); 3933 3934 return 0; 3935 } 3936 3937 static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, 3938 const struct ib_qp_attr *attr) 3939 { 3940 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) 3941 return IB_MTU_4096; 3942 3943 return attr->path_mtu; 3944 } 3945 3946 static int modify_qp_init_to_rtr(struct ib_qp *ibqp, 3947 const struct ib_qp_attr *attr, int attr_mask, 3948 struct hns_roce_v2_qp_context *context, 3949 struct hns_roce_v2_qp_context *qpc_mask) 3950 { 3951 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 3952 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3953 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3954 struct ib_device *ibdev = &hr_dev->ib_dev; 3955 dma_addr_t trrl_ba; 3956 dma_addr_t irrl_ba; 3957 enum ib_mtu mtu; 3958 u8 port_num; 3959 u64 *mtts; 3960 u8 *dmac; 3961 u8 *smac; 3962 int port; 3963 int ret; 3964 3965 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask); 3966 if (ret) { 3967 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret); 3968 return ret; 3969 } 3970 3971 /* Search IRRL's mtts */ 3972 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, 3973 hr_qp->qpn, &irrl_ba); 3974 if (!mtts) { 3975 ibdev_err(ibdev, "failed to find qp irrl_table.\n"); 3976 return -EINVAL; 3977 } 3978 3979 /* Search TRRL's mtts */ 3980 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, 3981 hr_qp->qpn, &trrl_ba); 3982 if (!mtts) { 3983 ibdev_err(ibdev, "failed to find qp trrl_table.\n"); 3984 return -EINVAL; 3985 } 3986 3987 if (attr_mask & IB_QP_ALT_PATH) { 3988 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n", 3989 attr_mask); 3990 return -EINVAL; 3991 } 3992 3993 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3994 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4); 3995 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, 3996 V2_QPC_BYTE_132_TRRL_BA_S, 0); 3997 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4)); 3998 qpc_mask->trrl_ba = 0; 3999 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4000 V2_QPC_BYTE_140_TRRL_BA_S, 4001 (u32)(trrl_ba >> (32 + 16 + 4))); 4002 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, 4003 V2_QPC_BYTE_140_TRRL_BA_S, 0); 4004 4005 context->irrl_ba = cpu_to_le32(irrl_ba >> 6); 4006 qpc_mask->irrl_ba = 0; 4007 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4008 V2_QPC_BYTE_208_IRRL_BA_S, 4009 irrl_ba >> (32 + 6)); 4010 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, 4011 V2_QPC_BYTE_208_IRRL_BA_S, 0); 4012 4013 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); 4014 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); 4015 4016 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4017 hr_qp->sq_signal_bits); 4018 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, 4019 0); 4020 4021 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; 4022 4023 smac = (u8 *)hr_dev->dev_addr[port]; 4024 dmac = (u8 *)attr->ah_attr.roce.dmac; 4025 /* when dmac equals smac or loop_idc is 1, it should loopback */ 4026 if (ether_addr_equal_unaligned(dmac, smac) || 4027 hr_dev->loop_idc == 0x1) { 4028 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); 4029 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); 4030 } 4031 4032 if (attr_mask & IB_QP_DEST_QPN) { 4033 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, 4034 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); 4035 roce_set_field(qpc_mask->byte_56_dqpn_err, 4036 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); 4037 } 4038 4039 /* Configure GID index */ 4040 port_num = rdma_ah_get_port_num(&attr->ah_attr); 4041 roce_set_field(context->byte_20_smac_sgid_idx, 4042 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4043 hns_get_gid_index(hr_dev, port_num - 1, 4044 grh->sgid_index)); 4045 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4046 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4047 4048 memcpy(&(context->dmac), dmac, sizeof(u32)); 4049 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4050 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); 4051 qpc_mask->dmac = 0; 4052 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, 4053 V2_QPC_BYTE_52_DMAC_S, 0); 4054 4055 mtu = get_mtu(ibqp, attr); 4056 4057 if (attr_mask & IB_QP_PATH_MTU) { 4058 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4059 V2_QPC_BYTE_24_MTU_S, mtu); 4060 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, 4061 V2_QPC_BYTE_24_MTU_S, 0); 4062 } 4063 4064 #define MAX_LP_MSG_LEN 65536 4065 /* MTU*(2^LP_PKTN_INI) shouldn't be bigger than 64kb */ 4066 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4067 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4068 ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu))); 4069 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, 4070 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); 4071 4072 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4073 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); 4074 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, 4075 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); 4076 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4077 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, 4078 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); 4079 4080 context->rq_rnr_timer = 0; 4081 qpc_mask->rq_rnr_timer = 0; 4082 4083 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, 4084 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); 4085 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, 4086 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); 4087 4088 /* rocee send 2^lp_sgen_ini segs every time */ 4089 roce_set_field(context->byte_168_irrl_idx, 4090 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4091 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); 4092 roce_set_field(qpc_mask->byte_168_irrl_idx, 4093 V2_QPC_BYTE_168_LP_SGEN_INI_M, 4094 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); 4095 4096 return 0; 4097 } 4098 4099 static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, 4100 const struct ib_qp_attr *attr, int attr_mask, 4101 struct hns_roce_v2_qp_context *context, 4102 struct hns_roce_v2_qp_context *qpc_mask) 4103 { 4104 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4105 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4106 struct ib_device *ibdev = &hr_dev->ib_dev; 4107 int ret; 4108 4109 /* Not support alternate path and path migration */ 4110 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { 4111 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); 4112 return -EINVAL; 4113 } 4114 4115 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask); 4116 if (ret) { 4117 ibdev_err(ibdev, "failed to config sq buf, ret %d\n", ret); 4118 return ret; 4119 } 4120 4121 /* 4122 * Set some fields in context to zero, Because the default values 4123 * of all fields in context are zero, we need not set them to 0 again. 4124 * but we should set the relevant fields of context mask to 0. 4125 */ 4126 roce_set_field(qpc_mask->byte_232_irrl_sge, 4127 V2_QPC_BYTE_232_IRRL_SGE_IDX_M, 4128 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); 4129 4130 roce_set_field(qpc_mask->byte_240_irrl_tail, 4131 V2_QPC_BYTE_240_RX_ACK_MSN_M, 4132 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); 4133 4134 roce_set_field(qpc_mask->byte_248_ack_psn, 4135 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, 4136 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); 4137 roce_set_bit(qpc_mask->byte_248_ack_psn, 4138 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); 4139 roce_set_field(qpc_mask->byte_248_ack_psn, 4140 V2_QPC_BYTE_248_IRRL_PSN_M, 4141 V2_QPC_BYTE_248_IRRL_PSN_S, 0); 4142 4143 roce_set_field(qpc_mask->byte_240_irrl_tail, 4144 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, 4145 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); 4146 4147 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4148 V2_QPC_BYTE_220_RETRY_MSG_MSN_M, 4149 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); 4150 4151 roce_set_bit(qpc_mask->byte_248_ack_psn, 4152 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); 4153 4154 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, 4155 V2_QPC_BYTE_212_CHECK_FLG_S, 0); 4156 4157 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4158 V2_QPC_BYTE_212_LSN_S, 0x100); 4159 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, 4160 V2_QPC_BYTE_212_LSN_S, 0); 4161 4162 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, 4163 V2_QPC_BYTE_196_IRRL_HEAD_S, 0); 4164 4165 return 0; 4166 } 4167 4168 static int hns_roce_v2_set_path(struct ib_qp *ibqp, 4169 const struct ib_qp_attr *attr, 4170 int attr_mask, 4171 struct hns_roce_v2_qp_context *context, 4172 struct hns_roce_v2_qp_context *qpc_mask) 4173 { 4174 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); 4175 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4176 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4177 struct ib_device *ibdev = &hr_dev->ib_dev; 4178 const struct ib_gid_attr *gid_attr = NULL; 4179 int is_roce_protocol; 4180 u16 vlan_id = 0xffff; 4181 bool is_udp = false; 4182 u8 ib_port; 4183 u8 hr_port; 4184 int ret; 4185 4186 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; 4187 hr_port = ib_port - 1; 4188 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && 4189 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 4190 4191 if (is_roce_protocol) { 4192 gid_attr = attr->ah_attr.grh.sgid_attr; 4193 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); 4194 if (ret) 4195 return ret; 4196 4197 if (gid_attr) 4198 is_udp = (gid_attr->gid_type == 4199 IB_GID_TYPE_ROCE_UDP_ENCAP); 4200 } 4201 4202 if (vlan_id < VLAN_N_VID) { 4203 roce_set_bit(context->byte_76_srqn_op_en, 4204 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1); 4205 roce_set_bit(qpc_mask->byte_76_srqn_op_en, 4206 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0); 4207 roce_set_bit(context->byte_168_irrl_idx, 4208 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1); 4209 roce_set_bit(qpc_mask->byte_168_irrl_idx, 4210 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0); 4211 } 4212 4213 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4214 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id); 4215 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, 4216 V2_QPC_BYTE_24_VLAN_ID_S, 0); 4217 4218 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { 4219 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", 4220 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); 4221 return -EINVAL; 4222 } 4223 4224 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { 4225 ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); 4226 return -EINVAL; 4227 } 4228 4229 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4230 V2_QPC_BYTE_52_UDPSPN_S, 4231 is_udp ? 0x12b7 : 0); 4232 4233 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, 4234 V2_QPC_BYTE_52_UDPSPN_S, 0); 4235 4236 roce_set_field(context->byte_20_smac_sgid_idx, 4237 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 4238 grh->sgid_index); 4239 4240 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, 4241 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); 4242 4243 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4244 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); 4245 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, 4246 V2_QPC_BYTE_24_HOP_LIMIT_S, 0); 4247 4248 if (is_udp) 4249 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4250 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2); 4251 else 4252 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4253 V2_QPC_BYTE_24_TC_S, grh->traffic_class); 4254 4255 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, 4256 V2_QPC_BYTE_24_TC_S, 0); 4257 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4258 V2_QPC_BYTE_28_FL_S, grh->flow_label); 4259 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, 4260 V2_QPC_BYTE_28_FL_S, 0); 4261 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); 4262 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); 4263 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4264 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); 4265 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, 4266 V2_QPC_BYTE_28_SL_S, 0); 4267 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); 4268 4269 return 0; 4270 } 4271 4272 static bool check_qp_state(enum ib_qp_state cur_state, 4273 enum ib_qp_state new_state) 4274 { 4275 static const bool sm[][IB_QPS_ERR + 1] = { 4276 [IB_QPS_RESET] = { [IB_QPS_RESET] = true, 4277 [IB_QPS_INIT] = true }, 4278 [IB_QPS_INIT] = { [IB_QPS_RESET] = true, 4279 [IB_QPS_INIT] = true, 4280 [IB_QPS_RTR] = true, 4281 [IB_QPS_ERR] = true }, 4282 [IB_QPS_RTR] = { [IB_QPS_RESET] = true, 4283 [IB_QPS_RTS] = true, 4284 [IB_QPS_ERR] = true }, 4285 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, 4286 [IB_QPS_RTS] = true, 4287 [IB_QPS_ERR] = true }, 4288 [IB_QPS_SQD] = {}, 4289 [IB_QPS_SQE] = {}, 4290 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } 4291 }; 4292 4293 return sm[cur_state][new_state]; 4294 } 4295 4296 static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, 4297 const struct ib_qp_attr *attr, 4298 int attr_mask, 4299 enum ib_qp_state cur_state, 4300 enum ib_qp_state new_state, 4301 struct hns_roce_v2_qp_context *context, 4302 struct hns_roce_v2_qp_context *qpc_mask) 4303 { 4304 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4305 int ret = 0; 4306 4307 if (!check_qp_state(cur_state, new_state)) { 4308 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); 4309 return -EINVAL; 4310 } 4311 4312 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 4313 memset(qpc_mask, 0, sizeof(*qpc_mask)); 4314 modify_qp_reset_to_init(ibqp, attr, attr_mask, context, 4315 qpc_mask); 4316 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 4317 modify_qp_init_to_init(ibqp, attr, attr_mask, context, 4318 qpc_mask); 4319 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 4320 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, 4321 qpc_mask); 4322 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { 4323 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, 4324 qpc_mask); 4325 } 4326 4327 return ret; 4328 } 4329 4330 static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, 4331 const struct ib_qp_attr *attr, 4332 int attr_mask, 4333 struct hns_roce_v2_qp_context *context, 4334 struct hns_roce_v2_qp_context *qpc_mask) 4335 { 4336 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4337 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4338 int ret = 0; 4339 4340 if (attr_mask & IB_QP_AV) { 4341 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, 4342 qpc_mask); 4343 if (ret) 4344 return ret; 4345 } 4346 4347 if (attr_mask & IB_QP_TIMEOUT) { 4348 if (attr->timeout < 31) { 4349 roce_set_field(context->byte_28_at_fl, 4350 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4351 attr->timeout); 4352 roce_set_field(qpc_mask->byte_28_at_fl, 4353 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, 4354 0); 4355 } else { 4356 ibdev_warn(&hr_dev->ib_dev, 4357 "Local ACK timeout shall be 0 to 30.\n"); 4358 } 4359 } 4360 4361 if (attr_mask & IB_QP_RETRY_CNT) { 4362 roce_set_field(context->byte_212_lsn, 4363 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4364 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 4365 attr->retry_cnt); 4366 roce_set_field(qpc_mask->byte_212_lsn, 4367 V2_QPC_BYTE_212_RETRY_NUM_INIT_M, 4368 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); 4369 4370 roce_set_field(context->byte_212_lsn, 4371 V2_QPC_BYTE_212_RETRY_CNT_M, 4372 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); 4373 roce_set_field(qpc_mask->byte_212_lsn, 4374 V2_QPC_BYTE_212_RETRY_CNT_M, 4375 V2_QPC_BYTE_212_RETRY_CNT_S, 0); 4376 } 4377 4378 if (attr_mask & IB_QP_RNR_RETRY) { 4379 roce_set_field(context->byte_244_rnr_rxack, 4380 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4381 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); 4382 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4383 V2_QPC_BYTE_244_RNR_NUM_INIT_M, 4384 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); 4385 4386 roce_set_field(context->byte_244_rnr_rxack, 4387 V2_QPC_BYTE_244_RNR_CNT_M, 4388 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); 4389 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4390 V2_QPC_BYTE_244_RNR_CNT_M, 4391 V2_QPC_BYTE_244_RNR_CNT_S, 0); 4392 } 4393 4394 /* RC&UC&UD required attr */ 4395 if (attr_mask & IB_QP_SQ_PSN) { 4396 roce_set_field(context->byte_172_sq_psn, 4397 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4398 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); 4399 roce_set_field(qpc_mask->byte_172_sq_psn, 4400 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4401 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); 4402 4403 roce_set_field(context->byte_196_sq_psn, 4404 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4405 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); 4406 roce_set_field(qpc_mask->byte_196_sq_psn, 4407 V2_QPC_BYTE_196_SQ_MAX_PSN_M, 4408 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); 4409 4410 roce_set_field(context->byte_220_retry_psn_msn, 4411 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4412 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); 4413 roce_set_field(qpc_mask->byte_220_retry_psn_msn, 4414 V2_QPC_BYTE_220_RETRY_MSG_PSN_M, 4415 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); 4416 4417 roce_set_field(context->byte_224_retry_msg, 4418 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4419 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 4420 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S); 4421 roce_set_field(qpc_mask->byte_224_retry_msg, 4422 V2_QPC_BYTE_224_RETRY_MSG_PSN_M, 4423 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); 4424 4425 roce_set_field(context->byte_224_retry_msg, 4426 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4427 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 4428 attr->sq_psn); 4429 roce_set_field(qpc_mask->byte_224_retry_msg, 4430 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, 4431 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); 4432 4433 roce_set_field(context->byte_244_rnr_rxack, 4434 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4435 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); 4436 roce_set_field(qpc_mask->byte_244_rnr_rxack, 4437 V2_QPC_BYTE_244_RX_ACK_EPSN_M, 4438 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); 4439 } 4440 4441 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && 4442 attr->max_dest_rd_atomic) { 4443 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4444 V2_QPC_BYTE_140_RR_MAX_S, 4445 fls(attr->max_dest_rd_atomic - 1)); 4446 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, 4447 V2_QPC_BYTE_140_RR_MAX_S, 0); 4448 } 4449 4450 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { 4451 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, 4452 V2_QPC_BYTE_208_SR_MAX_S, 4453 fls(attr->max_rd_atomic - 1)); 4454 roce_set_field(qpc_mask->byte_208_irrl, 4455 V2_QPC_BYTE_208_SR_MAX_M, 4456 V2_QPC_BYTE_208_SR_MAX_S, 0); 4457 } 4458 4459 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) 4460 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); 4461 4462 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 4463 roce_set_field(context->byte_80_rnr_rx_cqn, 4464 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4465 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 4466 attr->min_rnr_timer); 4467 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, 4468 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4469 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); 4470 } 4471 4472 /* RC&UC required attr */ 4473 if (attr_mask & IB_QP_RQ_PSN) { 4474 roce_set_field(context->byte_108_rx_reqepsn, 4475 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4476 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); 4477 roce_set_field(qpc_mask->byte_108_rx_reqepsn, 4478 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4479 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); 4480 4481 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, 4482 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); 4483 roce_set_field(qpc_mask->byte_152_raq, 4484 V2_QPC_BYTE_152_RAQ_PSN_M, 4485 V2_QPC_BYTE_152_RAQ_PSN_S, 0); 4486 } 4487 4488 if (attr_mask & IB_QP_QKEY) { 4489 context->qkey_xrcd = cpu_to_le32(attr->qkey); 4490 qpc_mask->qkey_xrcd = 0; 4491 hr_qp->qkey = attr->qkey; 4492 } 4493 4494 return ret; 4495 } 4496 4497 static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, 4498 const struct ib_qp_attr *attr, 4499 int attr_mask) 4500 { 4501 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4502 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4503 4504 if (attr_mask & IB_QP_ACCESS_FLAGS) 4505 hr_qp->atomic_rd_en = attr->qp_access_flags; 4506 4507 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 4508 hr_qp->resp_depth = attr->max_dest_rd_atomic; 4509 if (attr_mask & IB_QP_PORT) { 4510 hr_qp->port = attr->port_num - 1; 4511 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; 4512 } 4513 } 4514 4515 static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, 4516 const struct ib_qp_attr *attr, 4517 int attr_mask, enum ib_qp_state cur_state, 4518 enum ib_qp_state new_state) 4519 { 4520 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4521 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4522 struct hns_roce_v2_qp_context ctx[2]; 4523 struct hns_roce_v2_qp_context *context = ctx; 4524 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; 4525 struct ib_device *ibdev = &hr_dev->ib_dev; 4526 unsigned long sq_flag = 0; 4527 unsigned long rq_flag = 0; 4528 int ret; 4529 4530 /* 4531 * In v2 engine, software pass context and context mask to hardware 4532 * when modifying qp. If software need modify some fields in context, 4533 * we should set all bits of the relevant fields in context mask to 4534 * 0 at the same time, else set them to 0x1. 4535 */ 4536 memset(context, 0, sizeof(*context)); 4537 memset(qpc_mask, 0xff, sizeof(*qpc_mask)); 4538 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, 4539 new_state, context, qpc_mask); 4540 if (ret) 4541 goto out; 4542 4543 /* When QP state is err, SQ and RQ WQE should be flushed */ 4544 if (new_state == IB_QPS_ERR) { 4545 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); 4546 hr_qp->state = IB_QPS_ERR; 4547 roce_set_field(context->byte_160_sq_ci_pi, 4548 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4549 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 4550 hr_qp->sq.head); 4551 roce_set_field(qpc_mask->byte_160_sq_ci_pi, 4552 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, 4553 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); 4554 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); 4555 4556 if (!ibqp->srq) { 4557 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); 4558 roce_set_field(context->byte_84_rq_ci_pi, 4559 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4560 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 4561 hr_qp->rq.head); 4562 roce_set_field(qpc_mask->byte_84_rq_ci_pi, 4563 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, 4564 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); 4565 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); 4566 } 4567 } 4568 4569 /* Configure the optional fields */ 4570 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, 4571 qpc_mask); 4572 if (ret) 4573 goto out; 4574 4575 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, 4576 ibqp->srq ? 1 : 0); 4577 roce_set_bit(qpc_mask->byte_108_rx_reqepsn, 4578 V2_QPC_BYTE_108_INV_CREDIT_S, 0); 4579 4580 /* Every status migrate must change state */ 4581 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4582 V2_QPC_BYTE_60_QP_ST_S, new_state); 4583 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, 4584 V2_QPC_BYTE_60_QP_ST_S, 0); 4585 4586 /* SW pass context to HW */ 4587 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp); 4588 if (ret) { 4589 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret); 4590 goto out; 4591 } 4592 4593 hr_qp->state = new_state; 4594 4595 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); 4596 4597 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 4598 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 4599 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 4600 if (ibqp->send_cq != ibqp->recv_cq) 4601 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), 4602 hr_qp->qpn, NULL); 4603 4604 hr_qp->rq.head = 0; 4605 hr_qp->rq.tail = 0; 4606 hr_qp->sq.head = 0; 4607 hr_qp->sq.tail = 0; 4608 hr_qp->next_sge = 0; 4609 if (hr_qp->rq.wqe_cnt) 4610 *hr_qp->rdb.db_record = 0; 4611 } 4612 4613 out: 4614 return ret; 4615 } 4616 4617 static int to_ib_qp_st(enum hns_roce_v2_qp_state state) 4618 { 4619 static const enum ib_qp_state map[] = { 4620 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, 4621 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, 4622 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, 4623 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, 4624 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, 4625 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, 4626 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, 4627 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD 4628 }; 4629 4630 return (state < ARRAY_SIZE(map)) ? map[state] : -1; 4631 } 4632 4633 static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, 4634 struct hns_roce_qp *hr_qp, 4635 struct hns_roce_v2_qp_context *hr_context) 4636 { 4637 struct hns_roce_cmd_mailbox *mailbox; 4638 int ret; 4639 4640 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 4641 if (IS_ERR(mailbox)) 4642 return PTR_ERR(mailbox); 4643 4644 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 4645 HNS_ROCE_CMD_QUERY_QPC, 4646 HNS_ROCE_CMD_TIMEOUT_MSECS); 4647 if (ret) 4648 goto out; 4649 4650 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 4651 4652 out: 4653 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 4654 return ret; 4655 } 4656 4657 static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4658 int qp_attr_mask, 4659 struct ib_qp_init_attr *qp_init_attr) 4660 { 4661 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4662 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4663 struct hns_roce_v2_qp_context context = {}; 4664 struct ib_device *ibdev = &hr_dev->ib_dev; 4665 int tmp_qp_state; 4666 int state; 4667 int ret; 4668 4669 memset(qp_attr, 0, sizeof(*qp_attr)); 4670 memset(qp_init_attr, 0, sizeof(*qp_init_attr)); 4671 4672 mutex_lock(&hr_qp->mutex); 4673 4674 if (hr_qp->state == IB_QPS_RESET) { 4675 qp_attr->qp_state = IB_QPS_RESET; 4676 ret = 0; 4677 goto done; 4678 } 4679 4680 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); 4681 if (ret) { 4682 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret); 4683 ret = -EINVAL; 4684 goto out; 4685 } 4686 4687 state = roce_get_field(context.byte_60_qpst_tempid, 4688 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); 4689 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); 4690 if (tmp_qp_state == -1) { 4691 ibdev_err(ibdev, "Illegal ib_qp_state\n"); 4692 ret = -EINVAL; 4693 goto out; 4694 } 4695 hr_qp->state = (u8)tmp_qp_state; 4696 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; 4697 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc, 4698 V2_QPC_BYTE_24_MTU_M, 4699 V2_QPC_BYTE_24_MTU_S); 4700 qp_attr->path_mig_state = IB_MIG_ARMED; 4701 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 4702 if (hr_qp->ibqp.qp_type == IB_QPT_UD) 4703 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd); 4704 4705 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn, 4706 V2_QPC_BYTE_108_RX_REQ_EPSN_M, 4707 V2_QPC_BYTE_108_RX_REQ_EPSN_S); 4708 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn, 4709 V2_QPC_BYTE_172_SQ_CUR_PSN_M, 4710 V2_QPC_BYTE_172_SQ_CUR_PSN_S); 4711 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err, 4712 V2_QPC_BYTE_56_DQPN_M, 4713 V2_QPC_BYTE_56_DQPN_S); 4714 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en, 4715 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) | 4716 ((roce_get_bit(context.byte_76_srqn_op_en, 4717 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) | 4718 ((roce_get_bit(context.byte_76_srqn_op_en, 4719 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); 4720 4721 if (hr_qp->ibqp.qp_type == IB_QPT_RC || 4722 hr_qp->ibqp.qp_type == IB_QPT_UC) { 4723 struct ib_global_route *grh = 4724 rdma_ah_retrieve_grh(&qp_attr->ah_attr); 4725 4726 rdma_ah_set_sl(&qp_attr->ah_attr, 4727 roce_get_field(context.byte_28_at_fl, 4728 V2_QPC_BYTE_28_SL_M, 4729 V2_QPC_BYTE_28_SL_S)); 4730 grh->flow_label = roce_get_field(context.byte_28_at_fl, 4731 V2_QPC_BYTE_28_FL_M, 4732 V2_QPC_BYTE_28_FL_S); 4733 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx, 4734 V2_QPC_BYTE_20_SGID_IDX_M, 4735 V2_QPC_BYTE_20_SGID_IDX_S); 4736 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc, 4737 V2_QPC_BYTE_24_HOP_LIMIT_M, 4738 V2_QPC_BYTE_24_HOP_LIMIT_S); 4739 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc, 4740 V2_QPC_BYTE_24_TC_M, 4741 V2_QPC_BYTE_24_TC_S); 4742 4743 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); 4744 } 4745 4746 qp_attr->port_num = hr_qp->port + 1; 4747 qp_attr->sq_draining = 0; 4748 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl, 4749 V2_QPC_BYTE_208_SR_MAX_M, 4750 V2_QPC_BYTE_208_SR_MAX_S); 4751 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, 4752 V2_QPC_BYTE_140_RR_MAX_M, 4753 V2_QPC_BYTE_140_RR_MAX_S); 4754 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, 4755 V2_QPC_BYTE_80_MIN_RNR_TIME_M, 4756 V2_QPC_BYTE_80_MIN_RNR_TIME_S); 4757 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl, 4758 V2_QPC_BYTE_28_AT_M, 4759 V2_QPC_BYTE_28_AT_S); 4760 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn, 4761 V2_QPC_BYTE_212_RETRY_CNT_M, 4762 V2_QPC_BYTE_212_RETRY_CNT_S); 4763 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer); 4764 4765 done: 4766 qp_attr->cur_qp_state = qp_attr->qp_state; 4767 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; 4768 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; 4769 4770 if (!ibqp->uobject) { 4771 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; 4772 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; 4773 } else { 4774 qp_attr->cap.max_send_wr = 0; 4775 qp_attr->cap.max_send_sge = 0; 4776 } 4777 4778 qp_init_attr->cap = qp_attr->cap; 4779 4780 out: 4781 mutex_unlock(&hr_qp->mutex); 4782 return ret; 4783 } 4784 4785 static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, 4786 struct hns_roce_qp *hr_qp, 4787 struct ib_udata *udata) 4788 { 4789 struct ib_device *ibdev = &hr_dev->ib_dev; 4790 struct hns_roce_cq *send_cq, *recv_cq; 4791 unsigned long flags; 4792 int ret = 0; 4793 4794 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { 4795 /* Modify qp to reset before destroying qp */ 4796 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, 4797 hr_qp->state, IB_QPS_RESET); 4798 if (ret) 4799 ibdev_err(ibdev, 4800 "failed to modify QP to RST, ret = %d\n", 4801 ret); 4802 } 4803 4804 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; 4805 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; 4806 4807 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 4808 hns_roce_lock_cqs(send_cq, recv_cq); 4809 4810 if (!udata) { 4811 if (recv_cq) 4812 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, 4813 (hr_qp->ibqp.srq ? 4814 to_hr_srq(hr_qp->ibqp.srq) : 4815 NULL)); 4816 4817 if (send_cq && send_cq != recv_cq) 4818 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); 4819 4820 } 4821 4822 hns_roce_qp_remove(hr_dev, hr_qp); 4823 4824 hns_roce_unlock_cqs(send_cq, recv_cq); 4825 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 4826 4827 return ret; 4828 } 4829 4830 static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) 4831 { 4832 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 4833 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 4834 int ret; 4835 4836 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); 4837 if (ret) 4838 ibdev_err(&hr_dev->ib_dev, 4839 "failed to destroy QP 0x%06lx, ret = %d\n", 4840 hr_qp->qpn, ret); 4841 4842 hns_roce_qp_destroy(hr_dev, hr_qp, udata); 4843 4844 return 0; 4845 } 4846 4847 static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, 4848 struct hns_roce_qp *hr_qp) 4849 { 4850 struct ib_device *ibdev = &hr_dev->ib_dev; 4851 struct hns_roce_sccc_clr_done *resp; 4852 struct hns_roce_sccc_clr *clr; 4853 struct hns_roce_cmq_desc desc; 4854 int ret, i; 4855 4856 mutex_lock(&hr_dev->qp_table.scc_mutex); 4857 4858 /* set scc ctx clear done flag */ 4859 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); 4860 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4861 if (ret) { 4862 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret); 4863 goto out; 4864 } 4865 4866 /* clear scc context */ 4867 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); 4868 clr = (struct hns_roce_sccc_clr *)desc.data; 4869 clr->qpn = cpu_to_le32(hr_qp->qpn); 4870 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4871 if (ret) { 4872 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret); 4873 goto out; 4874 } 4875 4876 /* query scc context clear is done or not */ 4877 resp = (struct hns_roce_sccc_clr_done *)desc.data; 4878 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { 4879 hns_roce_cmq_setup_basic_desc(&desc, 4880 HNS_ROCE_OPC_QUERY_SCCC, true); 4881 ret = hns_roce_cmq_send(hr_dev, &desc, 1); 4882 if (ret) { 4883 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", 4884 ret); 4885 goto out; 4886 } 4887 4888 if (resp->clr_done) 4889 goto out; 4890 4891 msleep(20); 4892 } 4893 4894 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); 4895 ret = -ETIMEDOUT; 4896 4897 out: 4898 mutex_unlock(&hr_dev->qp_table.scc_mutex); 4899 return ret; 4900 } 4901 4902 static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev, 4903 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, 4904 u32 cqn, void *mb_buf, u64 *mtts_wqe, 4905 u64 *mtts_idx, dma_addr_t dma_handle_wqe, 4906 dma_addr_t dma_handle_idx) 4907 { 4908 struct hns_roce_srq_context *srq_context; 4909 4910 srq_context = mb_buf; 4911 memset(srq_context, 0, sizeof(*srq_context)); 4912 4913 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M, 4914 SRQC_BYTE_4_SRQ_ST_S, 1); 4915 4916 roce_set_field(srq_context->byte_4_srqn_srqst, 4917 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M, 4918 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S, 4919 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num, 4920 srq->wqe_cnt)); 4921 roce_set_field(srq_context->byte_4_srqn_srqst, 4922 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S, 4923 ilog2(srq->wqe_cnt)); 4924 4925 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M, 4926 SRQC_BYTE_4_SRQN_S, srq->srqn); 4927 4928 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M, 4929 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 4930 4931 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M, 4932 SRQC_BYTE_12_SRQ_XRCD_S, xrcd); 4933 4934 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3)); 4935 4936 roce_set_field(srq_context->byte_24_wqe_bt_ba, 4937 SRQC_BYTE_24_SRQ_WQE_BT_BA_M, 4938 SRQC_BYTE_24_SRQ_WQE_BT_BA_S, 4939 dma_handle_wqe >> 35); 4940 4941 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M, 4942 SRQC_BYTE_28_PD_S, pdn); 4943 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M, 4944 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 : 4945 fls(srq->max_gs - 1)); 4946 4947 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3); 4948 roce_set_field(srq_context->rsv_idx_bt_ba, 4949 SRQC_BYTE_36_SRQ_IDX_BT_BA_M, 4950 SRQC_BYTE_36_SRQ_IDX_BT_BA_S, 4951 dma_handle_idx >> 35); 4952 4953 srq_context->idx_cur_blk_addr = 4954 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0])); 4955 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4956 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M, 4957 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S, 4958 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); 4959 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4960 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M, 4961 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S, 4962 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num, 4963 srq->wqe_cnt)); 4964 4965 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4966 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M, 4967 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S, 4968 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift)); 4969 roce_set_field(srq_context->byte_44_idxbufpgsz_addr, 4970 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M, 4971 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S, 4972 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift)); 4973 4974 srq_context->idx_nxt_blk_addr = 4975 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1])); 4976 roce_set_field(srq_context->rsv_idxnxtblkaddr, 4977 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M, 4978 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S, 4979 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); 4980 roce_set_field(srq_context->byte_56_xrc_cqn, 4981 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S, 4982 cqn); 4983 roce_set_field(srq_context->byte_56_xrc_cqn, 4984 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M, 4985 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S, 4986 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); 4987 roce_set_field(srq_context->byte_56_xrc_cqn, 4988 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M, 4989 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S, 4990 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); 4991 4992 roce_set_bit(srq_context->db_record_addr_record_en, 4993 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0); 4994 } 4995 4996 static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, 4997 struct ib_srq_attr *srq_attr, 4998 enum ib_srq_attr_mask srq_attr_mask, 4999 struct ib_udata *udata) 5000 { 5001 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5002 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5003 struct hns_roce_srq_context *srq_context; 5004 struct hns_roce_srq_context *srqc_mask; 5005 struct hns_roce_cmd_mailbox *mailbox; 5006 int ret; 5007 5008 if (srq_attr_mask & IB_SRQ_LIMIT) { 5009 if (srq_attr->srq_limit >= srq->wqe_cnt) 5010 return -EINVAL; 5011 5012 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5013 if (IS_ERR(mailbox)) 5014 return PTR_ERR(mailbox); 5015 5016 srq_context = mailbox->buf; 5017 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; 5018 5019 memset(srqc_mask, 0xff, sizeof(*srqc_mask)); 5020 5021 roce_set_field(srq_context->byte_8_limit_wl, 5022 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5023 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit); 5024 roce_set_field(srqc_mask->byte_8_limit_wl, 5025 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5026 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); 5027 5028 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, 5029 HNS_ROCE_CMD_MODIFY_SRQC, 5030 HNS_ROCE_CMD_TIMEOUT_MSECS); 5031 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5032 if (ret) { 5033 ibdev_err(&hr_dev->ib_dev, 5034 "failed to handle cmd of modifying SRQ, ret = %d.\n", 5035 ret); 5036 return ret; 5037 } 5038 } 5039 5040 return 0; 5041 } 5042 5043 static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) 5044 { 5045 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); 5046 struct hns_roce_srq *srq = to_hr_srq(ibsrq); 5047 struct hns_roce_srq_context *srq_context; 5048 struct hns_roce_cmd_mailbox *mailbox; 5049 int limit_wl; 5050 int ret; 5051 5052 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5053 if (IS_ERR(mailbox)) 5054 return PTR_ERR(mailbox); 5055 5056 srq_context = mailbox->buf; 5057 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, 5058 HNS_ROCE_CMD_QUERY_SRQC, 5059 HNS_ROCE_CMD_TIMEOUT_MSECS); 5060 if (ret) { 5061 ibdev_err(&hr_dev->ib_dev, 5062 "failed to process cmd of querying SRQ, ret = %d.\n", 5063 ret); 5064 goto out; 5065 } 5066 5067 limit_wl = roce_get_field(srq_context->byte_8_limit_wl, 5068 SRQC_BYTE_8_SRQ_LIMIT_WL_M, 5069 SRQC_BYTE_8_SRQ_LIMIT_WL_S); 5070 5071 attr->srq_limit = limit_wl; 5072 attr->max_wr = srq->wqe_cnt - 1; 5073 attr->max_sge = srq->max_gs - HNS_ROCE_RESERVED_SGE; 5074 5075 out: 5076 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5077 return ret; 5078 } 5079 5080 static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) 5081 { 5082 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); 5083 struct hns_roce_v2_cq_context *cq_context; 5084 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 5085 struct hns_roce_v2_cq_context *cqc_mask; 5086 struct hns_roce_cmd_mailbox *mailbox; 5087 int ret; 5088 5089 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5090 if (IS_ERR(mailbox)) 5091 return PTR_ERR(mailbox); 5092 5093 cq_context = mailbox->buf; 5094 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; 5095 5096 memset(cqc_mask, 0xff, sizeof(*cqc_mask)); 5097 5098 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5099 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5100 cq_count); 5101 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5102 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, 5103 0); 5104 roce_set_field(cq_context->byte_56_cqe_period_maxcnt, 5105 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5106 cq_period); 5107 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, 5108 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, 5109 0); 5110 5111 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, 5112 HNS_ROCE_CMD_MODIFY_CQC, 5113 HNS_ROCE_CMD_TIMEOUT_MSECS); 5114 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5115 if (ret) 5116 ibdev_err(&hr_dev->ib_dev, 5117 "failed to process cmd when modifying CQ, ret = %d\n", 5118 ret); 5119 5120 return ret; 5121 } 5122 5123 static void hns_roce_irq_work_handle(struct work_struct *work) 5124 { 5125 struct hns_roce_work *irq_work = 5126 container_of(work, struct hns_roce_work, work); 5127 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; 5128 u32 qpn = irq_work->qpn; 5129 u32 cqn = irq_work->cqn; 5130 5131 switch (irq_work->event_type) { 5132 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5133 ibdev_info(ibdev, "Path migrated succeeded.\n"); 5134 break; 5135 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5136 ibdev_warn(ibdev, "Path migration failed.\n"); 5137 break; 5138 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5139 break; 5140 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5141 ibdev_warn(ibdev, "Send queue drained.\n"); 5142 break; 5143 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5144 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", 5145 qpn, irq_work->sub_type); 5146 break; 5147 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5148 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", 5149 qpn); 5150 break; 5151 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5152 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", 5153 qpn, irq_work->sub_type); 5154 break; 5155 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5156 ibdev_warn(ibdev, "SRQ limit reach.\n"); 5157 break; 5158 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5159 ibdev_warn(ibdev, "SRQ last wqe reach.\n"); 5160 break; 5161 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5162 ibdev_err(ibdev, "SRQ catas error.\n"); 5163 break; 5164 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5165 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn); 5166 break; 5167 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5168 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn); 5169 break; 5170 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5171 ibdev_warn(ibdev, "DB overflow.\n"); 5172 break; 5173 case HNS_ROCE_EVENT_TYPE_FLR: 5174 ibdev_warn(ibdev, "Function level reset.\n"); 5175 break; 5176 default: 5177 break; 5178 } 5179 5180 kfree(irq_work); 5181 } 5182 5183 static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, 5184 struct hns_roce_eq *eq, 5185 u32 qpn, u32 cqn) 5186 { 5187 struct hns_roce_work *irq_work; 5188 5189 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); 5190 if (!irq_work) 5191 return; 5192 5193 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); 5194 irq_work->hr_dev = hr_dev; 5195 irq_work->qpn = qpn; 5196 irq_work->cqn = cqn; 5197 irq_work->event_type = eq->event_type; 5198 irq_work->sub_type = eq->sub_type; 5199 queue_work(hr_dev->irq_workq, &(irq_work->work)); 5200 } 5201 5202 static void set_eq_cons_index_v2(struct hns_roce_eq *eq) 5203 { 5204 struct hns_roce_dev *hr_dev = eq->hr_dev; 5205 __le32 doorbell[2] = {}; 5206 5207 if (eq->type_flag == HNS_ROCE_AEQ) { 5208 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5209 HNS_ROCE_V2_EQ_DB_CMD_S, 5210 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5211 HNS_ROCE_EQ_DB_CMD_AEQ : 5212 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); 5213 } else { 5214 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, 5215 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); 5216 5217 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, 5218 HNS_ROCE_V2_EQ_DB_CMD_S, 5219 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? 5220 HNS_ROCE_EQ_DB_CMD_CEQ : 5221 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); 5222 } 5223 5224 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, 5225 HNS_ROCE_V2_EQ_DB_PARA_S, 5226 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); 5227 5228 hns_roce_write64(hr_dev, doorbell, eq->doorbell); 5229 } 5230 5231 static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) 5232 { 5233 struct hns_roce_aeqe *aeqe; 5234 5235 aeqe = hns_roce_buf_offset(eq->mtr.kmem, 5236 (eq->cons_index & (eq->entries - 1)) * 5237 HNS_ROCE_AEQ_ENTRY_SIZE); 5238 5239 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ 5240 !!(eq->cons_index & eq->entries)) ? aeqe : NULL; 5241 } 5242 5243 static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, 5244 struct hns_roce_eq *eq) 5245 { 5246 struct device *dev = hr_dev->dev; 5247 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); 5248 int aeqe_found = 0; 5249 int event_type; 5250 int sub_type; 5251 u32 srqn; 5252 u32 qpn; 5253 u32 cqn; 5254 5255 while (aeqe) { 5256 /* Make sure we read AEQ entry after we have checked the 5257 * ownership bit 5258 */ 5259 dma_rmb(); 5260 5261 event_type = roce_get_field(aeqe->asyn, 5262 HNS_ROCE_V2_AEQE_EVENT_TYPE_M, 5263 HNS_ROCE_V2_AEQE_EVENT_TYPE_S); 5264 sub_type = roce_get_field(aeqe->asyn, 5265 HNS_ROCE_V2_AEQE_SUB_TYPE_M, 5266 HNS_ROCE_V2_AEQE_SUB_TYPE_S); 5267 qpn = roce_get_field(aeqe->event.qp_event.qp, 5268 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5269 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5270 cqn = roce_get_field(aeqe->event.cq_event.cq, 5271 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5272 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5273 srqn = roce_get_field(aeqe->event.srq_event.srq, 5274 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, 5275 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); 5276 5277 switch (event_type) { 5278 case HNS_ROCE_EVENT_TYPE_PATH_MIG: 5279 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: 5280 case HNS_ROCE_EVENT_TYPE_COMM_EST: 5281 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: 5282 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: 5283 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: 5284 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: 5285 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: 5286 hns_roce_qp_event(hr_dev, qpn, event_type); 5287 break; 5288 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: 5289 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: 5290 hns_roce_srq_event(hr_dev, srqn, event_type); 5291 break; 5292 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: 5293 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: 5294 hns_roce_cq_event(hr_dev, cqn, event_type); 5295 break; 5296 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: 5297 break; 5298 case HNS_ROCE_EVENT_TYPE_MB: 5299 hns_roce_cmd_event(hr_dev, 5300 le16_to_cpu(aeqe->event.cmd.token), 5301 aeqe->event.cmd.status, 5302 le64_to_cpu(aeqe->event.cmd.out_param)); 5303 break; 5304 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: 5305 break; 5306 case HNS_ROCE_EVENT_TYPE_FLR: 5307 break; 5308 default: 5309 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", 5310 event_type, eq->eqn, eq->cons_index); 5311 break; 5312 } 5313 5314 eq->event_type = event_type; 5315 eq->sub_type = sub_type; 5316 ++eq->cons_index; 5317 aeqe_found = 1; 5318 5319 if (eq->cons_index > (2 * eq->entries - 1)) 5320 eq->cons_index = 0; 5321 5322 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn); 5323 5324 aeqe = next_aeqe_sw_v2(eq); 5325 } 5326 5327 set_eq_cons_index_v2(eq); 5328 return aeqe_found; 5329 } 5330 5331 static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) 5332 { 5333 struct hns_roce_ceqe *ceqe; 5334 5335 ceqe = hns_roce_buf_offset(eq->mtr.kmem, 5336 (eq->cons_index & (eq->entries - 1)) * 5337 HNS_ROCE_CEQ_ENTRY_SIZE); 5338 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ 5339 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; 5340 } 5341 5342 static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, 5343 struct hns_roce_eq *eq) 5344 { 5345 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); 5346 int ceqe_found = 0; 5347 u32 cqn; 5348 5349 while (ceqe) { 5350 /* Make sure we read CEQ entry after we have checked the 5351 * ownership bit 5352 */ 5353 dma_rmb(); 5354 5355 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, 5356 HNS_ROCE_V2_CEQE_COMP_CQN_S); 5357 5358 hns_roce_cq_completion(hr_dev, cqn); 5359 5360 ++eq->cons_index; 5361 ceqe_found = 1; 5362 5363 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1)) 5364 eq->cons_index = 0; 5365 5366 ceqe = next_ceqe_sw_v2(eq); 5367 } 5368 5369 set_eq_cons_index_v2(eq); 5370 5371 return ceqe_found; 5372 } 5373 5374 static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 5375 { 5376 struct hns_roce_eq *eq = eq_ptr; 5377 struct hns_roce_dev *hr_dev = eq->hr_dev; 5378 int int_work = 0; 5379 5380 if (eq->type_flag == HNS_ROCE_CEQ) 5381 /* Completion event interrupt */ 5382 int_work = hns_roce_v2_ceq_int(hr_dev, eq); 5383 else 5384 /* Asychronous event interrupt */ 5385 int_work = hns_roce_v2_aeq_int(hr_dev, eq); 5386 5387 return IRQ_RETVAL(int_work); 5388 } 5389 5390 static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 5391 { 5392 struct hns_roce_dev *hr_dev = dev_id; 5393 struct device *dev = hr_dev->dev; 5394 int int_work = 0; 5395 u32 int_st; 5396 u32 int_en; 5397 5398 /* Abnormal interrupt */ 5399 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); 5400 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); 5401 5402 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { 5403 struct pci_dev *pdev = hr_dev->pci_dev; 5404 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5405 const struct hnae3_ae_ops *ops = ae_dev->ops; 5406 5407 dev_err(dev, "AEQ overflow!\n"); 5408 5409 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; 5410 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5411 5412 /* Set reset level for reset_event() */ 5413 if (ops->set_default_reset_request) 5414 ops->set_default_reset_request(ae_dev, 5415 HNAE3_FUNC_RESET); 5416 if (ops->reset_event) 5417 ops->reset_event(pdev, NULL); 5418 5419 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5420 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5421 5422 int_work = 1; 5423 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { 5424 dev_err(dev, "BUS ERR!\n"); 5425 5426 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S; 5427 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5428 5429 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5430 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5431 5432 int_work = 1; 5433 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { 5434 dev_err(dev, "OTHER ERR!\n"); 5435 5436 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S; 5437 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); 5438 5439 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; 5440 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); 5441 5442 int_work = 1; 5443 } else 5444 dev_err(dev, "There is no abnormal irq found!\n"); 5445 5446 return IRQ_RETVAL(int_work); 5447 } 5448 5449 static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 5450 int eq_num, int enable_flag) 5451 { 5452 int i; 5453 5454 if (enable_flag == EQ_ENABLE) { 5455 for (i = 0; i < eq_num; i++) 5456 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5457 i * EQ_REG_OFFSET, 5458 HNS_ROCE_V2_VF_EVENT_INT_EN_M); 5459 5460 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5461 HNS_ROCE_V2_VF_ABN_INT_EN_M); 5462 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5463 HNS_ROCE_V2_VF_ABN_INT_CFG_M); 5464 } else { 5465 for (i = 0; i < eq_num; i++) 5466 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + 5467 i * EQ_REG_OFFSET, 5468 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); 5469 5470 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, 5471 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); 5472 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, 5473 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); 5474 } 5475 } 5476 5477 static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) 5478 { 5479 struct device *dev = hr_dev->dev; 5480 int ret; 5481 5482 if (eqn < hr_dev->caps.num_comp_vectors) 5483 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5484 0, HNS_ROCE_CMD_DESTROY_CEQC, 5485 HNS_ROCE_CMD_TIMEOUT_MSECS); 5486 else 5487 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, 5488 0, HNS_ROCE_CMD_DESTROY_AEQC, 5489 HNS_ROCE_CMD_TIMEOUT_MSECS); 5490 if (ret) 5491 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); 5492 } 5493 5494 static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5495 { 5496 hns_roce_mtr_destroy(hr_dev, &eq->mtr); 5497 } 5498 5499 static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, 5500 void *mb_buf) 5501 { 5502 u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; 5503 struct hns_roce_eq_context *eqc; 5504 u64 bt_ba = 0; 5505 int count; 5506 5507 eqc = mb_buf; 5508 memset(eqc, 0, sizeof(struct hns_roce_eq_context)); 5509 5510 /* init eqc */ 5511 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; 5512 eq->cons_index = 0; 5513 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; 5514 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; 5515 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; 5516 eq->shift = ilog2((unsigned int)eq->entries); 5517 5518 /* if not multi-hop, eqe buffer only use one trunk */ 5519 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, 5520 &bt_ba); 5521 if (count < 1) { 5522 dev_err(hr_dev->dev, "failed to find EQE mtr\n"); 5523 return -ENOBUFS; 5524 } 5525 5526 /* set eqc state */ 5527 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, 5528 HNS_ROCE_V2_EQ_STATE_VALID); 5529 5530 /* set eqe hop num */ 5531 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, 5532 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); 5533 5534 /* set eqc over_ignore */ 5535 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, 5536 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); 5537 5538 /* set eqc coalesce */ 5539 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M, 5540 HNS_ROCE_EQC_COALESCE_S, eq->coalesce); 5541 5542 /* set eqc arm_state */ 5543 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, 5544 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); 5545 5546 /* set eqn */ 5547 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, 5548 eq->eqn); 5549 5550 /* set eqe_cnt */ 5551 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, 5552 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); 5553 5554 /* set eqe_ba_pg_sz */ 5555 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M, 5556 HNS_ROCE_EQC_BA_PG_SZ_S, 5557 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); 5558 5559 /* set eqe_buf_pg_sz */ 5560 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M, 5561 HNS_ROCE_EQC_BUF_PG_SZ_S, 5562 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); 5563 5564 /* set eq_producer_idx */ 5565 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M, 5566 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX); 5567 5568 /* set eq_max_cnt */ 5569 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M, 5570 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); 5571 5572 /* set eq_period */ 5573 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M, 5574 HNS_ROCE_EQC_PERIOD_S, eq->eq_period); 5575 5576 /* set eqe_report_timer */ 5577 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M, 5578 HNS_ROCE_EQC_REPORT_TIMER_S, 5579 HNS_ROCE_EQ_INIT_REPORT_TIMER); 5580 5581 /* set bt_ba [34:3] */ 5582 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M, 5583 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3); 5584 5585 /* set bt_ba [64:35] */ 5586 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M, 5587 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35); 5588 5589 /* set eq shift */ 5590 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S, 5591 eq->shift); 5592 5593 /* set eq MSI_IDX */ 5594 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M, 5595 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX); 5596 5597 /* set cur_eqe_ba [27:12] */ 5598 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M, 5599 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12); 5600 5601 /* set cur_eqe_ba [59:28] */ 5602 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M, 5603 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28); 5604 5605 /* set cur_eqe_ba [63:60] */ 5606 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M, 5607 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60); 5608 5609 /* set eq consumer idx */ 5610 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M, 5611 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX); 5612 5613 /* set nex_eqe_ba[43:12] */ 5614 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M, 5615 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12); 5616 5617 /* set nex_eqe_ba[63:44] */ 5618 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M, 5619 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44); 5620 5621 return 0; 5622 } 5623 5624 static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) 5625 { 5626 struct hns_roce_buf_attr buf_attr = {}; 5627 int err; 5628 5629 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) 5630 eq->hop_num = 0; 5631 else 5632 eq->hop_num = hr_dev->caps.eqe_hop_num; 5633 5634 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT; 5635 buf_attr.region[0].size = eq->entries * eq->eqe_size; 5636 buf_attr.region[0].hopnum = eq->hop_num; 5637 buf_attr.region_count = 1; 5638 buf_attr.fixed_page = true; 5639 5640 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, 5641 hr_dev->caps.eqe_ba_pg_sz + 5642 HNS_HW_PAGE_SHIFT, NULL, 0); 5643 if (err) 5644 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); 5645 5646 return err; 5647 } 5648 5649 static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, 5650 struct hns_roce_eq *eq, 5651 unsigned int eq_cmd) 5652 { 5653 struct hns_roce_cmd_mailbox *mailbox; 5654 int ret; 5655 5656 /* Allocate mailbox memory */ 5657 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 5658 if (IS_ERR_OR_NULL(mailbox)) 5659 return -ENOMEM; 5660 5661 ret = alloc_eq_buf(hr_dev, eq); 5662 if (ret) 5663 goto free_cmd_mbox; 5664 5665 ret = config_eqc(hr_dev, eq, mailbox->buf); 5666 if (ret) 5667 goto err_cmd_mbox; 5668 5669 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, 5670 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); 5671 if (ret) { 5672 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); 5673 goto err_cmd_mbox; 5674 } 5675 5676 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5677 5678 return 0; 5679 5680 err_cmd_mbox: 5681 free_eq_buf(hr_dev, eq); 5682 5683 free_cmd_mbox: 5684 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 5685 5686 return ret; 5687 } 5688 5689 static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, 5690 int comp_num, int aeq_num, int other_num) 5691 { 5692 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5693 int i, j; 5694 int ret; 5695 5696 for (i = 0; i < irq_num; i++) { 5697 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, 5698 GFP_KERNEL); 5699 if (!hr_dev->irq_names[i]) { 5700 ret = -ENOMEM; 5701 goto err_kzalloc_failed; 5702 } 5703 } 5704 5705 /* irq contains: abnormal + AEQ + CEQ */ 5706 for (j = 0; j < other_num; j++) 5707 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5708 "hns-abn-%d", j); 5709 5710 for (j = other_num; j < (other_num + aeq_num); j++) 5711 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5712 "hns-aeq-%d", j - other_num); 5713 5714 for (j = (other_num + aeq_num); j < irq_num; j++) 5715 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, 5716 "hns-ceq-%d", j - other_num - aeq_num); 5717 5718 for (j = 0; j < irq_num; j++) { 5719 if (j < other_num) 5720 ret = request_irq(hr_dev->irq[j], 5721 hns_roce_v2_msix_interrupt_abn, 5722 0, hr_dev->irq_names[j], hr_dev); 5723 5724 else if (j < (other_num + comp_num)) 5725 ret = request_irq(eq_table->eq[j - other_num].irq, 5726 hns_roce_v2_msix_interrupt_eq, 5727 0, hr_dev->irq_names[j + aeq_num], 5728 &eq_table->eq[j - other_num]); 5729 else 5730 ret = request_irq(eq_table->eq[j - other_num].irq, 5731 hns_roce_v2_msix_interrupt_eq, 5732 0, hr_dev->irq_names[j - comp_num], 5733 &eq_table->eq[j - other_num]); 5734 if (ret) { 5735 dev_err(hr_dev->dev, "Request irq error!\n"); 5736 goto err_request_failed; 5737 } 5738 } 5739 5740 return 0; 5741 5742 err_request_failed: 5743 for (j -= 1; j >= 0; j--) 5744 if (j < other_num) 5745 free_irq(hr_dev->irq[j], hr_dev); 5746 else 5747 free_irq(eq_table->eq[j - other_num].irq, 5748 &eq_table->eq[j - other_num]); 5749 5750 err_kzalloc_failed: 5751 for (i -= 1; i >= 0; i--) 5752 kfree(hr_dev->irq_names[i]); 5753 5754 return ret; 5755 } 5756 5757 static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) 5758 { 5759 int irq_num; 5760 int eq_num; 5761 int i; 5762 5763 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5764 irq_num = eq_num + hr_dev->caps.num_other_vectors; 5765 5766 for (i = 0; i < hr_dev->caps.num_other_vectors; i++) 5767 free_irq(hr_dev->irq[i], hr_dev); 5768 5769 for (i = 0; i < eq_num; i++) 5770 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); 5771 5772 for (i = 0; i < irq_num; i++) 5773 kfree(hr_dev->irq_names[i]); 5774 } 5775 5776 static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 5777 { 5778 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5779 struct device *dev = hr_dev->dev; 5780 struct hns_roce_eq *eq; 5781 unsigned int eq_cmd; 5782 int irq_num; 5783 int eq_num; 5784 int other_num; 5785 int comp_num; 5786 int aeq_num; 5787 int i; 5788 int ret; 5789 5790 other_num = hr_dev->caps.num_other_vectors; 5791 comp_num = hr_dev->caps.num_comp_vectors; 5792 aeq_num = hr_dev->caps.num_aeq_vectors; 5793 5794 eq_num = comp_num + aeq_num; 5795 irq_num = eq_num + other_num; 5796 5797 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); 5798 if (!eq_table->eq) 5799 return -ENOMEM; 5800 5801 /* create eq */ 5802 for (i = 0; i < eq_num; i++) { 5803 eq = &eq_table->eq[i]; 5804 eq->hr_dev = hr_dev; 5805 eq->eqn = i; 5806 if (i < comp_num) { 5807 /* CEQ */ 5808 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; 5809 eq->type_flag = HNS_ROCE_CEQ; 5810 eq->entries = hr_dev->caps.ceqe_depth; 5811 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; 5812 eq->irq = hr_dev->irq[i + other_num + aeq_num]; 5813 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; 5814 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; 5815 } else { 5816 /* AEQ */ 5817 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; 5818 eq->type_flag = HNS_ROCE_AEQ; 5819 eq->entries = hr_dev->caps.aeqe_depth; 5820 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; 5821 eq->irq = hr_dev->irq[i - comp_num + other_num]; 5822 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; 5823 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; 5824 } 5825 5826 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); 5827 if (ret) { 5828 dev_err(dev, "eq create failed.\n"); 5829 goto err_create_eq_fail; 5830 } 5831 } 5832 5833 /* enable irq */ 5834 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); 5835 5836 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, 5837 aeq_num, other_num); 5838 if (ret) { 5839 dev_err(dev, "Request irq failed.\n"); 5840 goto err_request_irq_fail; 5841 } 5842 5843 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); 5844 if (!hr_dev->irq_workq) { 5845 dev_err(dev, "Create irq workqueue failed!\n"); 5846 ret = -ENOMEM; 5847 goto err_create_wq_fail; 5848 } 5849 5850 return 0; 5851 5852 err_create_wq_fail: 5853 __hns_roce_free_irq(hr_dev); 5854 5855 err_request_irq_fail: 5856 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5857 5858 err_create_eq_fail: 5859 for (i -= 1; i >= 0; i--) 5860 free_eq_buf(hr_dev, &eq_table->eq[i]); 5861 kfree(eq_table->eq); 5862 5863 return ret; 5864 } 5865 5866 static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 5867 { 5868 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; 5869 int eq_num; 5870 int i; 5871 5872 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; 5873 5874 /* Disable irq */ 5875 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); 5876 5877 __hns_roce_free_irq(hr_dev); 5878 5879 for (i = 0; i < eq_num; i++) { 5880 hns_roce_v2_destroy_eqc(hr_dev, i); 5881 5882 free_eq_buf(hr_dev, &eq_table->eq[i]); 5883 } 5884 5885 kfree(eq_table->eq); 5886 5887 flush_workqueue(hr_dev->irq_workq); 5888 destroy_workqueue(hr_dev->irq_workq); 5889 } 5890 5891 static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { 5892 .query_cqc_info = hns_roce_v2_query_cqc_info, 5893 }; 5894 5895 static const struct ib_device_ops hns_roce_v2_dev_ops = { 5896 .destroy_qp = hns_roce_v2_destroy_qp, 5897 .modify_cq = hns_roce_v2_modify_cq, 5898 .poll_cq = hns_roce_v2_poll_cq, 5899 .post_recv = hns_roce_v2_post_recv, 5900 .post_send = hns_roce_v2_post_send, 5901 .query_qp = hns_roce_v2_query_qp, 5902 .req_notify_cq = hns_roce_v2_req_notify_cq, 5903 }; 5904 5905 static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { 5906 .modify_srq = hns_roce_v2_modify_srq, 5907 .post_srq_recv = hns_roce_v2_post_srq_recv, 5908 .query_srq = hns_roce_v2_query_srq, 5909 }; 5910 5911 static const struct hns_roce_hw hns_roce_hw_v2 = { 5912 .cmq_init = hns_roce_v2_cmq_init, 5913 .cmq_exit = hns_roce_v2_cmq_exit, 5914 .hw_profile = hns_roce_v2_profile, 5915 .hw_init = hns_roce_v2_init, 5916 .hw_exit = hns_roce_v2_exit, 5917 .post_mbox = hns_roce_v2_post_mbox, 5918 .chk_mbox = hns_roce_v2_chk_mbox, 5919 .rst_prc_mbox = hns_roce_v2_rst_process_cmd, 5920 .set_gid = hns_roce_v2_set_gid, 5921 .set_mac = hns_roce_v2_set_mac, 5922 .write_mtpt = hns_roce_v2_write_mtpt, 5923 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, 5924 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, 5925 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, 5926 .write_cqc = hns_roce_v2_write_cqc, 5927 .set_hem = hns_roce_v2_set_hem, 5928 .clear_hem = hns_roce_v2_clear_hem, 5929 .modify_qp = hns_roce_v2_modify_qp, 5930 .query_qp = hns_roce_v2_query_qp, 5931 .destroy_qp = hns_roce_v2_destroy_qp, 5932 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, 5933 .modify_cq = hns_roce_v2_modify_cq, 5934 .post_send = hns_roce_v2_post_send, 5935 .post_recv = hns_roce_v2_post_recv, 5936 .req_notify_cq = hns_roce_v2_req_notify_cq, 5937 .poll_cq = hns_roce_v2_poll_cq, 5938 .init_eq = hns_roce_v2_init_eq_table, 5939 .cleanup_eq = hns_roce_v2_cleanup_eq_table, 5940 .write_srqc = hns_roce_v2_write_srqc, 5941 .modify_srq = hns_roce_v2_modify_srq, 5942 .query_srq = hns_roce_v2_query_srq, 5943 .post_srq_recv = hns_roce_v2_post_srq_recv, 5944 .hns_roce_dev_ops = &hns_roce_v2_dev_ops, 5945 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, 5946 }; 5947 5948 static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { 5949 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 5950 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 5951 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 5952 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 5953 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 5954 /* required last entry */ 5955 {0, } 5956 }; 5957 5958 MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); 5959 5960 static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, 5961 struct hnae3_handle *handle) 5962 { 5963 struct hns_roce_v2_priv *priv = hr_dev->priv; 5964 int i; 5965 5966 hr_dev->pci_dev = handle->pdev; 5967 hr_dev->dev = &handle->pdev->dev; 5968 hr_dev->hw = &hns_roce_hw_v2; 5969 hr_dev->dfx = &hns_roce_dfx_hw_v2; 5970 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; 5971 hr_dev->odb_offset = hr_dev->sdb_offset; 5972 5973 /* Get info from NIC driver. */ 5974 hr_dev->reg_base = handle->rinfo.roce_io_base; 5975 hr_dev->caps.num_ports = 1; 5976 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; 5977 hr_dev->iboe.phy_port[0] = 0; 5978 5979 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, 5980 hr_dev->iboe.netdevs[0]->dev_addr); 5981 5982 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) 5983 hr_dev->irq[i] = pci_irq_vector(handle->pdev, 5984 i + handle->rinfo.base_vector); 5985 5986 /* cmd issue mode: 0 is poll, 1 is event */ 5987 hr_dev->cmd_mod = 1; 5988 hr_dev->loop_idc = 0; 5989 5990 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); 5991 priv->handle = handle; 5992 } 5993 5994 static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 5995 { 5996 struct hns_roce_dev *hr_dev; 5997 int ret; 5998 5999 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); 6000 if (!hr_dev) 6001 return -ENOMEM; 6002 6003 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); 6004 if (!hr_dev->priv) { 6005 ret = -ENOMEM; 6006 goto error_failed_kzalloc; 6007 } 6008 6009 hns_roce_hw_v2_get_cfg(hr_dev, handle); 6010 6011 ret = hns_roce_init(hr_dev); 6012 if (ret) { 6013 dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); 6014 goto error_failed_get_cfg; 6015 } 6016 6017 handle->priv = hr_dev; 6018 6019 return 0; 6020 6021 error_failed_get_cfg: 6022 kfree(hr_dev->priv); 6023 6024 error_failed_kzalloc: 6025 ib_dealloc_device(&hr_dev->ib_dev); 6026 6027 return ret; 6028 } 6029 6030 static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6031 bool reset) 6032 { 6033 struct hns_roce_dev *hr_dev = handle->priv; 6034 6035 if (!hr_dev) 6036 return; 6037 6038 handle->priv = NULL; 6039 6040 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; 6041 hns_roce_handle_device_err(hr_dev); 6042 6043 hns_roce_exit(hr_dev); 6044 kfree(hr_dev->priv); 6045 ib_dealloc_device(&hr_dev->ib_dev); 6046 } 6047 6048 static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) 6049 { 6050 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 6051 const struct pci_device_id *id; 6052 struct device *dev = &handle->pdev->dev; 6053 int ret; 6054 6055 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; 6056 6057 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { 6058 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6059 goto reset_chk_err; 6060 } 6061 6062 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); 6063 if (!id) 6064 return 0; 6065 6066 ret = __hns_roce_hw_v2_init_instance(handle); 6067 if (ret) { 6068 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6069 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); 6070 if (ops->ae_dev_resetting(handle) || 6071 ops->get_hw_reset_stat(handle)) 6072 goto reset_chk_err; 6073 else 6074 return ret; 6075 } 6076 6077 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; 6078 6079 6080 return 0; 6081 6082 reset_chk_err: 6083 dev_err(dev, "Device is busy in resetting state.\n" 6084 "please retry later.\n"); 6085 6086 return -EBUSY; 6087 } 6088 6089 static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, 6090 bool reset) 6091 { 6092 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) 6093 return; 6094 6095 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; 6096 6097 __hns_roce_hw_v2_uninit_instance(handle, reset); 6098 6099 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; 6100 } 6101 static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) 6102 { 6103 struct hns_roce_dev *hr_dev; 6104 6105 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { 6106 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6107 return 0; 6108 } 6109 6110 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; 6111 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); 6112 6113 hr_dev = handle->priv; 6114 if (!hr_dev) 6115 return 0; 6116 6117 hr_dev->is_reset = true; 6118 hr_dev->active = false; 6119 hr_dev->dis_db = true; 6120 6121 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; 6122 6123 return 0; 6124 } 6125 6126 static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) 6127 { 6128 struct device *dev = &handle->pdev->dev; 6129 int ret; 6130 6131 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, 6132 &handle->rinfo.state)) { 6133 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6134 return 0; 6135 } 6136 6137 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; 6138 6139 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); 6140 ret = __hns_roce_hw_v2_init_instance(handle); 6141 if (ret) { 6142 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify 6143 * callback function, RoCE Engine reinitialize. If RoCE reinit 6144 * failed, we should inform NIC driver. 6145 */ 6146 handle->priv = NULL; 6147 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); 6148 } else { 6149 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; 6150 dev_info(dev, "Reset done, RoCE client reinit finished.\n"); 6151 } 6152 6153 return ret; 6154 } 6155 6156 static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) 6157 { 6158 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) 6159 return 0; 6160 6161 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; 6162 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); 6163 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); 6164 __hns_roce_hw_v2_uninit_instance(handle, false); 6165 6166 return 0; 6167 } 6168 6169 static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, 6170 enum hnae3_reset_notify_type type) 6171 { 6172 int ret = 0; 6173 6174 switch (type) { 6175 case HNAE3_DOWN_CLIENT: 6176 ret = hns_roce_hw_v2_reset_notify_down(handle); 6177 break; 6178 case HNAE3_INIT_CLIENT: 6179 ret = hns_roce_hw_v2_reset_notify_init(handle); 6180 break; 6181 case HNAE3_UNINIT_CLIENT: 6182 ret = hns_roce_hw_v2_reset_notify_uninit(handle); 6183 break; 6184 default: 6185 break; 6186 } 6187 6188 return ret; 6189 } 6190 6191 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 6192 .init_instance = hns_roce_hw_v2_init_instance, 6193 .uninit_instance = hns_roce_hw_v2_uninit_instance, 6194 .reset_notify = hns_roce_hw_v2_reset_notify, 6195 }; 6196 6197 static struct hnae3_client hns_roce_hw_v2_client = { 6198 .name = "hns_roce_hw_v2", 6199 .type = HNAE3_CLIENT_ROCE, 6200 .ops = &hns_roce_hw_v2_ops, 6201 }; 6202 6203 static int __init hns_roce_hw_v2_init(void) 6204 { 6205 return hnae3_register_client(&hns_roce_hw_v2_client); 6206 } 6207 6208 static void __exit hns_roce_hw_v2_exit(void) 6209 { 6210 hnae3_unregister_client(&hns_roce_hw_v2_client); 6211 } 6212 6213 module_init(hns_roce_hw_v2_init); 6214 module_exit(hns_roce_hw_v2_exit); 6215 6216 MODULE_LICENSE("Dual BSD/GPL"); 6217 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 6218 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 6219 MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); 6220 MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); 6221