1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 41 42 #define MAC_ADDR_OCTET_NUM 6 43 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 44 45 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b)) 46 47 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 48 49 #define HNS_ROCE_BA_SIZE (32 * 4096) 50 51 /* Hardware specification only for v1 engine */ 52 #define HNS_ROCE_MIN_CQE_NUM 0x40 53 #define HNS_ROCE_MIN_WQE_NUM 0x20 54 55 /* Hardware specification only for v1 engine */ 56 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 57 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 58 59 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 60 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 62 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 63 #define HNS_ROCE_MIN_CQE_CNT 16 64 65 #define HNS_ROCE_MAX_IRQ_NUM 128 66 67 #define EQ_ENABLE 1 68 #define EQ_DISABLE 0 69 70 #define HNS_ROCE_CEQ 0 71 #define HNS_ROCE_AEQ 1 72 73 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 74 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 75 76 /* 4G/4K = 1M */ 77 #define HNS_ROCE_SL_SHIFT 28 78 #define HNS_ROCE_TCLASS_SHIFT 20 79 #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff 80 81 #define HNS_ROCE_MAX_PORTS 6 82 #define HNS_ROCE_MAX_GID_NUM 16 83 #define HNS_ROCE_GID_SIZE 16 84 85 #define HNS_ROCE_HOP_NUM_0 0xff 86 87 #define BITMAP_NO_RR 0 88 #define BITMAP_RR 1 89 90 #define MR_TYPE_MR 0x00 91 #define MR_TYPE_FRMR 0x01 92 #define MR_TYPE_DMA 0x03 93 94 #define HNS_ROCE_FRMR_MAX_PA 512 95 96 #define PKEY_ID 0xffff 97 #define GUID_LEN 8 98 #define NODE_DESC_SIZE 64 99 #define DB_REG_OFFSET 0x1000 100 101 #define SERV_TYPE_RC 0 102 #define SERV_TYPE_RD 1 103 #define SERV_TYPE_UC 2 104 #define SERV_TYPE_UD 3 105 106 /* Configure to HW for PAGE_SIZE larger than 4KB */ 107 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 108 109 #define PAGES_SHIFT_8 8 110 #define PAGES_SHIFT_16 16 111 #define PAGES_SHIFT_24 24 112 #define PAGES_SHIFT_32 32 113 114 enum { 115 HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0, 116 HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1, 117 }; 118 119 enum { 120 HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0, 121 }; 122 123 enum hns_roce_qp_state { 124 HNS_ROCE_QP_STATE_RST, 125 HNS_ROCE_QP_STATE_INIT, 126 HNS_ROCE_QP_STATE_RTR, 127 HNS_ROCE_QP_STATE_RTS, 128 HNS_ROCE_QP_STATE_SQD, 129 HNS_ROCE_QP_STATE_ERR, 130 HNS_ROCE_QP_NUM_STATE, 131 }; 132 133 enum hns_roce_event { 134 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 135 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 136 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 137 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 138 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 139 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 140 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 141 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 142 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 143 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 144 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 145 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 146 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 147 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 148 /* 0x10 and 0x11 is unused in currently application case */ 149 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 150 HNS_ROCE_EVENT_TYPE_MB = 0x13, 151 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 152 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 153 }; 154 155 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 156 enum { 157 HNS_ROCE_LWQCE_QPC_ERROR = 1, 158 HNS_ROCE_LWQCE_MTU_ERROR = 2, 159 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 160 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 161 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 162 HNS_ROCE_LWQCE_SL_ERROR = 6, 163 HNS_ROCE_LWQCE_PORT_ERROR = 7, 164 }; 165 166 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 167 enum { 168 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 169 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 170 HNS_ROCE_LAVWQE_VA_ERROR = 3, 171 HNS_ROCE_LAVWQE_PD_ERROR = 4, 172 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 173 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 174 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 175 }; 176 177 /* DOORBELL overflow subtype */ 178 enum { 179 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 180 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 181 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 182 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 183 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 184 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 185 }; 186 187 enum { 188 /* RQ&SRQ related operations */ 189 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 190 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 191 }; 192 193 enum { 194 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 195 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 196 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 197 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 198 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 199 HNS_ROCE_CAP_FLAG_MW = BIT(7), 200 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 201 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 202 }; 203 204 enum hns_roce_mtt_type { 205 MTT_TYPE_WQE, 206 MTT_TYPE_CQE, 207 }; 208 209 enum { 210 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 211 }; 212 213 #define HNS_ROCE_CMD_SUCCESS 1 214 215 #define HNS_ROCE_PORT_DOWN 0 216 #define HNS_ROCE_PORT_UP 1 217 218 #define HNS_ROCE_MTT_ENTRY_PER_SEG 8 219 220 #define PAGE_ADDR_SHIFT 12 221 222 struct hns_roce_uar { 223 u64 pfn; 224 unsigned long index; 225 unsigned long logic_idx; 226 }; 227 228 struct hns_roce_ucontext { 229 struct ib_ucontext ibucontext; 230 struct hns_roce_uar uar; 231 struct list_head page_list; 232 struct mutex page_mutex; 233 }; 234 235 struct hns_roce_pd { 236 struct ib_pd ibpd; 237 unsigned long pdn; 238 }; 239 240 struct hns_roce_bitmap { 241 /* Bitmap Traversal last a bit which is 1 */ 242 unsigned long last; 243 unsigned long top; 244 unsigned long max; 245 unsigned long reserved_top; 246 unsigned long mask; 247 spinlock_t lock; 248 unsigned long *table; 249 }; 250 251 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */ 252 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ 253 /* Every bit repesent to a partner free/used status in bitmap */ 254 /* 255 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 256 * Bit = 1 represent to idle and available; bit = 0: not available 257 */ 258 struct hns_roce_buddy { 259 /* Members point to every order level bitmap */ 260 unsigned long **bits; 261 /* Represent to avail bits of the order level bitmap */ 262 u32 *num_free; 263 int max_order; 264 spinlock_t lock; 265 }; 266 267 /* For Hardware Entry Memory */ 268 struct hns_roce_hem_table { 269 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 270 u32 type; 271 /* HEM array elment num */ 272 unsigned long num_hem; 273 /* HEM entry record obj total num */ 274 unsigned long num_obj; 275 /*Single obj size */ 276 unsigned long obj_size; 277 unsigned long table_chunk_size; 278 int lowmem; 279 struct mutex mutex; 280 struct hns_roce_hem **hem; 281 u64 **bt_l1; 282 dma_addr_t *bt_l1_dma_addr; 283 u64 **bt_l0; 284 dma_addr_t *bt_l0_dma_addr; 285 }; 286 287 struct hns_roce_mtt { 288 unsigned long first_seg; 289 int order; 290 int page_shift; 291 enum hns_roce_mtt_type mtt_type; 292 }; 293 294 struct hns_roce_mw { 295 struct ib_mw ibmw; 296 u32 pdn; 297 u32 rkey; 298 int enabled; /* MW's active status */ 299 u32 pbl_hop_num; 300 u32 pbl_ba_pg_sz; 301 u32 pbl_buf_pg_sz; 302 }; 303 304 /* Only support 4K page size for mr register */ 305 #define MR_SIZE_4K 0 306 307 struct hns_roce_mr { 308 struct ib_mr ibmr; 309 struct ib_umem *umem; 310 u64 iova; /* MR's virtual orignal addr */ 311 u64 size; /* Address range of MR */ 312 u32 key; /* Key of MR */ 313 u32 pd; /* PD num of MR */ 314 u32 access;/* Access permission of MR */ 315 u32 npages; 316 int enabled; /* MR's active status */ 317 int type; /* MR's register type */ 318 u64 *pbl_buf;/* MR's PBL space */ 319 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ 320 u32 pbl_size;/* PA number in the PBL */ 321 u64 pbl_ba;/* page table address */ 322 u32 l0_chunk_last_num;/* L0 last number */ 323 u32 l1_chunk_last_num;/* L1 last number */ 324 u64 **pbl_bt_l2;/* PBL BT L2 */ 325 u64 **pbl_bt_l1;/* PBL BT L1 */ 326 u64 *pbl_bt_l0;/* PBL BT L0 */ 327 dma_addr_t *pbl_l2_dma_addr;/* PBL BT L2 dma addr */ 328 dma_addr_t *pbl_l1_dma_addr;/* PBL BT L1 dma addr */ 329 dma_addr_t pbl_l0_dma_addr;/* PBL BT L0 dma addr */ 330 u32 pbl_ba_pg_sz;/* BT chunk page size */ 331 u32 pbl_buf_pg_sz;/* buf chunk page size */ 332 u32 pbl_hop_num;/* multi-hop number */ 333 }; 334 335 struct hns_roce_mr_table { 336 struct hns_roce_bitmap mtpt_bitmap; 337 struct hns_roce_buddy mtt_buddy; 338 struct hns_roce_hem_table mtt_table; 339 struct hns_roce_hem_table mtpt_table; 340 struct hns_roce_buddy mtt_cqe_buddy; 341 struct hns_roce_hem_table mtt_cqe_table; 342 }; 343 344 struct hns_roce_wq { 345 u64 *wrid; /* Work request ID */ 346 spinlock_t lock; 347 int wqe_cnt; /* WQE num */ 348 u32 max_post; 349 int max_gs; 350 int offset; 351 int wqe_shift;/* WQE size */ 352 u32 head; 353 u32 tail; 354 void __iomem *db_reg_l; 355 }; 356 357 struct hns_roce_sge { 358 int sge_cnt; /* SGE num */ 359 int offset; 360 int sge_shift;/* SGE size */ 361 }; 362 363 struct hns_roce_buf_list { 364 void *buf; 365 dma_addr_t map; 366 }; 367 368 struct hns_roce_buf { 369 struct hns_roce_buf_list direct; 370 struct hns_roce_buf_list *page_list; 371 int nbufs; 372 u32 npages; 373 int page_shift; 374 }; 375 376 struct hns_roce_db_pgdir { 377 struct list_head list; 378 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 379 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / 2); 380 unsigned long *bits[2]; 381 u32 *page; 382 dma_addr_t db_dma; 383 }; 384 385 struct hns_roce_user_db_page { 386 struct list_head list; 387 struct ib_umem *umem; 388 unsigned long user_virt; 389 refcount_t refcount; 390 }; 391 392 struct hns_roce_db { 393 u32 *db_record; 394 union { 395 struct hns_roce_db_pgdir *pgdir; 396 struct hns_roce_user_db_page *user_page; 397 } u; 398 dma_addr_t dma; 399 void *virt_addr; 400 int index; 401 int order; 402 }; 403 404 struct hns_roce_cq_buf { 405 struct hns_roce_buf hr_buf; 406 struct hns_roce_mtt hr_mtt; 407 }; 408 409 struct hns_roce_cq { 410 struct ib_cq ib_cq; 411 struct hns_roce_cq_buf hr_buf; 412 struct hns_roce_db db; 413 u8 db_en; 414 spinlock_t lock; 415 struct ib_umem *umem; 416 void (*comp)(struct hns_roce_cq *cq); 417 void (*event)(struct hns_roce_cq *cq, enum hns_roce_event event_type); 418 419 struct hns_roce_uar *uar; 420 u32 cq_depth; 421 u32 cons_index; 422 u32 *set_ci_db; 423 void __iomem *cq_db_l; 424 u16 *tptr_addr; 425 int arm_sn; 426 unsigned long cqn; 427 u32 vector; 428 atomic_t refcount; 429 struct completion free; 430 }; 431 432 struct hns_roce_srq { 433 struct ib_srq ibsrq; 434 int srqn; 435 }; 436 437 struct hns_roce_uar_table { 438 struct hns_roce_bitmap bitmap; 439 }; 440 441 struct hns_roce_qp_table { 442 struct hns_roce_bitmap bitmap; 443 spinlock_t lock; 444 struct hns_roce_hem_table qp_table; 445 struct hns_roce_hem_table irrl_table; 446 struct hns_roce_hem_table trrl_table; 447 }; 448 449 struct hns_roce_cq_table { 450 struct hns_roce_bitmap bitmap; 451 spinlock_t lock; 452 struct radix_tree_root tree; 453 struct hns_roce_hem_table table; 454 }; 455 456 struct hns_roce_raq_table { 457 struct hns_roce_buf_list *e_raq_buf; 458 }; 459 460 struct hns_roce_av { 461 __le32 port_pd; 462 u8 gid_index; 463 u8 stat_rate; 464 u8 hop_limit; 465 __le32 sl_tclass_flowlabel; 466 u8 dgid[HNS_ROCE_GID_SIZE]; 467 u8 mac[6]; 468 __le16 vlan; 469 bool vlan_en; 470 }; 471 472 struct hns_roce_ah { 473 struct ib_ah ibah; 474 struct hns_roce_av av; 475 }; 476 477 struct hns_roce_cmd_context { 478 struct completion done; 479 int result; 480 int next; 481 u64 out_param; 482 u16 token; 483 }; 484 485 struct hns_roce_cmdq { 486 struct dma_pool *pool; 487 struct mutex hcr_mutex; 488 struct semaphore poll_sem; 489 /* 490 * Event mode: cmd register mutex protection, 491 * ensure to not exceed max_cmds and user use limit region 492 */ 493 struct semaphore event_sem; 494 int max_cmds; 495 spinlock_t context_lock; 496 int free_head; 497 struct hns_roce_cmd_context *context; 498 /* 499 * Result of get integer part 500 * which max_comds compute according a power of 2 501 */ 502 u16 token_mask; 503 /* 504 * Process whether use event mode, init default non-zero 505 * After the event queue of cmd event ready, 506 * can switch into event mode 507 * close device, switch into poll mode(non event mode) 508 */ 509 u8 use_events; 510 u8 toggle; 511 }; 512 513 struct hns_roce_cmd_mailbox { 514 void *buf; 515 dma_addr_t dma; 516 }; 517 518 struct hns_roce_dev; 519 520 struct hns_roce_rinl_sge { 521 void *addr; 522 u32 len; 523 }; 524 525 struct hns_roce_rinl_wqe { 526 struct hns_roce_rinl_sge *sg_list; 527 u32 sge_cnt; 528 }; 529 530 struct hns_roce_rinl_buf { 531 struct hns_roce_rinl_wqe *wqe_list; 532 u32 wqe_cnt; 533 }; 534 535 struct hns_roce_qp { 536 struct ib_qp ibqp; 537 struct hns_roce_buf hr_buf; 538 struct hns_roce_wq rq; 539 struct hns_roce_db rdb; 540 struct hns_roce_db sdb; 541 u8 rdb_en; 542 u8 sdb_en; 543 u32 doorbell_qpn; 544 __le32 sq_signal_bits; 545 u32 sq_next_wqe; 546 int sq_max_wqes_per_wr; 547 int sq_spare_wqes; 548 struct hns_roce_wq sq; 549 550 struct ib_umem *umem; 551 struct hns_roce_mtt mtt; 552 u32 buff_size; 553 struct mutex mutex; 554 u8 port; 555 u8 phy_port; 556 u8 sl; 557 u8 resp_depth; 558 u8 state; 559 u32 access_flags; 560 u32 atomic_rd_en; 561 u32 pkey_index; 562 u32 qkey; 563 void (*event)(struct hns_roce_qp *qp, 564 enum hns_roce_event event_type); 565 unsigned long qpn; 566 567 atomic_t refcount; 568 struct completion free; 569 570 struct hns_roce_sge sge; 571 u32 next_sge; 572 573 struct hns_roce_rinl_buf rq_inl_buf; 574 }; 575 576 struct hns_roce_sqp { 577 struct hns_roce_qp hr_qp; 578 }; 579 580 struct hns_roce_ib_iboe { 581 spinlock_t lock; 582 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 583 struct notifier_block nb; 584 u8 phy_port[HNS_ROCE_MAX_PORTS]; 585 }; 586 587 enum { 588 HNS_ROCE_EQ_STAT_INVALID = 0, 589 HNS_ROCE_EQ_STAT_VALID = 2, 590 }; 591 592 struct hns_roce_ceqe { 593 u32 comp; 594 }; 595 596 struct hns_roce_aeqe { 597 __le32 asyn; 598 union { 599 struct { 600 __le32 qp; 601 u32 rsv0; 602 u32 rsv1; 603 } qp_event; 604 605 struct { 606 __le32 cq; 607 u32 rsv0; 608 u32 rsv1; 609 } cq_event; 610 611 struct { 612 __le32 ceqe; 613 u32 rsv0; 614 u32 rsv1; 615 } ce_event; 616 617 struct { 618 __le64 out_param; 619 __le16 token; 620 u8 status; 621 u8 rsv0; 622 } __packed cmd; 623 } event; 624 }; 625 626 struct hns_roce_eq { 627 struct hns_roce_dev *hr_dev; 628 void __iomem *doorbell; 629 630 int type_flag;/* Aeq:1 ceq:0 */ 631 int eqn; 632 u32 entries; 633 int log_entries; 634 int eqe_size; 635 int irq; 636 int log_page_size; 637 int cons_index; 638 struct hns_roce_buf_list *buf_list; 639 int over_ignore; 640 int coalesce; 641 int arm_st; 642 u64 eqe_ba; 643 int eqe_ba_pg_sz; 644 int eqe_buf_pg_sz; 645 int hop_num; 646 u64 *bt_l0; /* Base address table for L0 */ 647 u64 **bt_l1; /* Base address table for L1 */ 648 u64 **buf; 649 dma_addr_t l0_dma; 650 dma_addr_t *l1_dma; 651 dma_addr_t *buf_dma; 652 u32 l0_last_num; /* L0 last chunk num */ 653 u32 l1_last_num; /* L1 last chunk num */ 654 int eq_max_cnt; 655 int eq_period; 656 int shift; 657 dma_addr_t cur_eqe_ba; 658 dma_addr_t nxt_eqe_ba; 659 int event_type; 660 int sub_type; 661 }; 662 663 struct hns_roce_eq_table { 664 struct hns_roce_eq *eq; 665 void __iomem **eqc_base; /* only for hw v1 */ 666 }; 667 668 struct hns_roce_caps { 669 u64 fw_ver; 670 u8 num_ports; 671 int gid_table_len[HNS_ROCE_MAX_PORTS]; 672 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 673 int local_ca_ack_delay; 674 int num_uars; 675 u32 phy_num_uars; 676 u32 max_sq_sg; /* 2 */ 677 u32 max_sq_inline; /* 32 */ 678 u32 max_rq_sg; /* 2 */ 679 u32 max_extend_sg; 680 int num_qps; /* 256k */ 681 int reserved_qps; 682 u32 max_wqes; /* 16k */ 683 u32 max_sq_desc_sz; /* 64 */ 684 u32 max_rq_desc_sz; /* 64 */ 685 u32 max_srq_desc_sz; 686 int max_qp_init_rdma; 687 int max_qp_dest_rdma; 688 int num_cqs; 689 int max_cqes; 690 int min_cqes; 691 u32 min_wqes; 692 int reserved_cqs; 693 int num_aeq_vectors; /* 1 */ 694 int num_comp_vectors; 695 int num_other_vectors; 696 int num_mtpts; 697 u32 num_mtt_segs; 698 u32 num_cqe_segs; 699 int reserved_mrws; 700 int reserved_uars; 701 int num_pds; 702 int reserved_pds; 703 u32 mtt_entry_sz; 704 u32 cq_entry_sz; 705 u32 page_size_cap; 706 u32 reserved_lkey; 707 int mtpt_entry_sz; 708 int qpc_entry_sz; 709 int irrl_entry_sz; 710 int trrl_entry_sz; 711 int cqc_entry_sz; 712 u32 pbl_ba_pg_sz; 713 u32 pbl_buf_pg_sz; 714 u32 pbl_hop_num; 715 int aeqe_depth; 716 int ceqe_depth; 717 enum ib_mtu max_mtu; 718 u32 qpc_bt_num; 719 u32 srqc_bt_num; 720 u32 cqc_bt_num; 721 u32 mpt_bt_num; 722 u32 qpc_ba_pg_sz; 723 u32 qpc_buf_pg_sz; 724 u32 qpc_hop_num; 725 u32 srqc_ba_pg_sz; 726 u32 srqc_buf_pg_sz; 727 u32 srqc_hop_num; 728 u32 cqc_ba_pg_sz; 729 u32 cqc_buf_pg_sz; 730 u32 cqc_hop_num; 731 u32 mpt_ba_pg_sz; 732 u32 mpt_buf_pg_sz; 733 u32 mpt_hop_num; 734 u32 mtt_ba_pg_sz; 735 u32 mtt_buf_pg_sz; 736 u32 mtt_hop_num; 737 u32 cqe_ba_pg_sz; 738 u32 cqe_buf_pg_sz; 739 u32 cqe_hop_num; 740 u32 eqe_ba_pg_sz; 741 u32 eqe_buf_pg_sz; 742 u32 eqe_hop_num; 743 u32 sl_num; 744 u32 tsq_buf_pg_sz; 745 u32 tpq_buf_pg_sz; 746 u32 chunk_sz; /* chunk size in non multihop mode*/ 747 u64 flags; 748 }; 749 750 struct hns_roce_work { 751 struct hns_roce_dev *hr_dev; 752 struct work_struct work; 753 u32 qpn; 754 u32 cqn; 755 int event_type; 756 int sub_type; 757 }; 758 759 struct hns_roce_hw { 760 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 761 int (*cmq_init)(struct hns_roce_dev *hr_dev); 762 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 763 int (*hw_profile)(struct hns_roce_dev *hr_dev); 764 int (*hw_init)(struct hns_roce_dev *hr_dev); 765 void (*hw_exit)(struct hns_roce_dev *hr_dev); 766 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 767 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 768 u16 token, int event); 769 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 770 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 771 const union ib_gid *gid, const struct ib_gid_attr *attr); 772 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 773 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 774 enum ib_mtu mtu); 775 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 776 unsigned long mtpt_idx); 777 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 778 struct hns_roce_mr *mr, int flags, u32 pdn, 779 int mr_access_flags, u64 iova, u64 size, 780 void *mb_buf); 781 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 782 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 783 void (*write_cqc)(struct hns_roce_dev *hr_dev, 784 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 785 dma_addr_t dma_handle, int nent, u32 vector); 786 int (*set_hem)(struct hns_roce_dev *hr_dev, 787 struct hns_roce_hem_table *table, int obj, int step_idx); 788 int (*clear_hem)(struct hns_roce_dev *hr_dev, 789 struct hns_roce_hem_table *table, int obj, 790 int step_idx); 791 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 792 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 793 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 794 int attr_mask, enum ib_qp_state cur_state, 795 enum ib_qp_state new_state); 796 int (*destroy_qp)(struct ib_qp *ibqp); 797 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 798 const struct ib_send_wr **bad_wr); 799 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 800 const struct ib_recv_wr **bad_recv_wr); 801 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 802 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 803 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr); 804 int (*destroy_cq)(struct ib_cq *ibcq); 805 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 806 int (*init_eq)(struct hns_roce_dev *hr_dev); 807 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 808 }; 809 810 struct hns_roce_dev { 811 struct ib_device ib_dev; 812 struct platform_device *pdev; 813 struct pci_dev *pci_dev; 814 struct device *dev; 815 struct hns_roce_uar priv_uar; 816 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 817 spinlock_t sm_lock; 818 spinlock_t bt_cmd_lock; 819 bool active; 820 bool is_reset; 821 struct hns_roce_ib_iboe iboe; 822 823 struct list_head pgdir_list; 824 struct mutex pgdir_mutex; 825 int irq[HNS_ROCE_MAX_IRQ_NUM]; 826 u8 __iomem *reg_base; 827 struct hns_roce_caps caps; 828 struct radix_tree_root qp_table_tree; 829 830 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM]; 831 u64 sys_image_guid; 832 u32 vendor_id; 833 u32 vendor_part_id; 834 u32 hw_rev; 835 void __iomem *priv_addr; 836 837 struct hns_roce_cmdq cmd; 838 struct hns_roce_bitmap pd_bitmap; 839 struct hns_roce_uar_table uar_table; 840 struct hns_roce_mr_table mr_table; 841 struct hns_roce_cq_table cq_table; 842 struct hns_roce_qp_table qp_table; 843 struct hns_roce_eq_table eq_table; 844 845 int cmd_mod; 846 int loop_idc; 847 u32 sdb_offset; 848 u32 odb_offset; 849 dma_addr_t tptr_dma_addr; /*only for hw v1*/ 850 u32 tptr_size; /*only for hw v1*/ 851 const struct hns_roce_hw *hw; 852 void *priv; 853 struct workqueue_struct *irq_workq; 854 }; 855 856 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 857 { 858 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 859 } 860 861 static inline struct hns_roce_ucontext 862 *to_hr_ucontext(struct ib_ucontext *ibucontext) 863 { 864 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 865 } 866 867 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 868 { 869 return container_of(ibpd, struct hns_roce_pd, ibpd); 870 } 871 872 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 873 { 874 return container_of(ibah, struct hns_roce_ah, ibah); 875 } 876 877 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 878 { 879 return container_of(ibmr, struct hns_roce_mr, ibmr); 880 } 881 882 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 883 { 884 return container_of(ibmw, struct hns_roce_mw, ibmw); 885 } 886 887 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 888 { 889 return container_of(ibqp, struct hns_roce_qp, ibqp); 890 } 891 892 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 893 { 894 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 895 } 896 897 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 898 { 899 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 900 } 901 902 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp) 903 { 904 return container_of(hr_qp, struct hns_roce_sqp, hr_qp); 905 } 906 907 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 908 { 909 __raw_writeq(*(u64 *) val, dest); 910 } 911 912 static inline struct hns_roce_qp 913 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 914 { 915 return radix_tree_lookup(&hr_dev->qp_table_tree, 916 qpn & (hr_dev->caps.num_qps - 1)); 917 } 918 919 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 920 { 921 u32 page_size = 1 << buf->page_shift; 922 923 if (buf->nbufs == 1) 924 return (char *)(buf->direct.buf) + offset; 925 else 926 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 927 (offset & (page_size - 1)); 928 } 929 930 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 931 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 932 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 933 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 934 935 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 936 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 937 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 938 u64 out_param); 939 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 940 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 941 942 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, 943 struct hns_roce_mtt *mtt); 944 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, 945 struct hns_roce_mtt *mtt); 946 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, 947 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf); 948 949 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 950 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 951 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev); 952 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 953 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 954 955 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 956 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 957 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 958 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 959 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 960 961 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 962 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 963 int rr); 964 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 965 u32 reserved_bot, u32 resetrved_top); 966 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 967 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 968 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 969 int align, unsigned long *obj); 970 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 971 unsigned long obj, int cnt, 972 int rr); 973 974 struct ib_ah *hns_roce_create_ah(struct ib_pd *pd, 975 struct rdma_ah_attr *ah_attr, 976 struct ib_udata *udata); 977 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 978 int hns_roce_destroy_ah(struct ib_ah *ah); 979 980 struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev, 981 struct ib_ucontext *context, 982 struct ib_udata *udata); 983 int hns_roce_dealloc_pd(struct ib_pd *pd); 984 985 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 986 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 987 u64 virt_addr, int access_flags, 988 struct ib_udata *udata); 989 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 990 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 991 struct ib_udata *udata); 992 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 993 u32 max_num_sg); 994 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 995 unsigned int *sg_offset); 996 int hns_roce_dereg_mr(struct ib_mr *ibmr); 997 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev, 998 struct hns_roce_cmd_mailbox *mailbox, 999 unsigned long mpt_index); 1000 unsigned long key_to_hw_index(u32 key); 1001 1002 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, 1003 struct ib_udata *udata); 1004 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1005 1006 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 1007 struct hns_roce_buf *buf); 1008 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1009 struct hns_roce_buf *buf, u32 page_shift); 1010 1011 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 1012 struct hns_roce_mtt *mtt, struct ib_umem *umem); 1013 1014 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1015 struct ib_qp_init_attr *init_attr, 1016 struct ib_udata *udata); 1017 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1018 int attr_mask, struct ib_udata *udata); 1019 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1020 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1021 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n); 1022 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1023 struct ib_cq *ib_cq); 1024 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1025 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1026 struct hns_roce_cq *recv_cq); 1027 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1028 struct hns_roce_cq *recv_cq); 1029 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1030 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1031 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 1032 int cnt); 1033 __be32 send_ieth(const struct ib_send_wr *wr); 1034 int to_hr_qp_type(int qp_type); 1035 1036 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev, 1037 const struct ib_cq_init_attr *attr, 1038 struct ib_ucontext *context, 1039 struct ib_udata *udata); 1040 1041 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq); 1042 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq); 1043 1044 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1045 struct hns_roce_db *db); 1046 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1047 struct hns_roce_db *db); 1048 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1049 int order); 1050 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1051 1052 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1053 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1054 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1055 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1056 int hns_roce_init(struct hns_roce_dev *hr_dev); 1057 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1058 1059 #endif /* _HNS_ROCE_DEVICE_H */ 1060