1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define DRV_NAME "hns_roce" 40 41 #define PCI_REVISION_ID_HIP08 0x21 42 #define PCI_REVISION_ID_HIP09 0x30 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 49 50 #define HNS_ROCE_BA_SIZE (32 * 4096) 51 52 #define BA_BYTE_LEN 8 53 54 /* Hardware specification only for v1 engine */ 55 #define HNS_ROCE_MIN_CQE_NUM 0x40 56 #define HNS_ROCE_MIN_WQE_NUM 0x20 57 58 /* Hardware specification only for v1 engine */ 59 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 60 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 61 62 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 63 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 64 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 65 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 66 #define HNS_ROCE_MIN_CQE_CNT 16 67 68 #define HNS_ROCE_MAX_IRQ_NUM 128 69 70 #define HNS_ROCE_SGE_IN_WQE 2 71 #define HNS_ROCE_SGE_SHIFT 4 72 73 #define EQ_ENABLE 1 74 #define EQ_DISABLE 0 75 76 #define HNS_ROCE_CEQ 0 77 #define HNS_ROCE_AEQ 1 78 79 #define HNS_ROCE_CEQE_SIZE 0x4 80 #define HNS_ROCE_AEQE_SIZE 0x10 81 82 #define HNS_ROCE_V3_EQE_SIZE 0x40 83 84 #define HNS_ROCE_V2_CQE_SIZE 32 85 #define HNS_ROCE_V3_CQE_SIZE 64 86 87 #define HNS_ROCE_V2_QPC_SZ 256 88 #define HNS_ROCE_V3_QPC_SZ 512 89 90 #define HNS_ROCE_MAX_PORTS 6 91 #define HNS_ROCE_GID_SIZE 16 92 #define HNS_ROCE_SGE_SIZE 16 93 94 #define HNS_ROCE_HOP_NUM_0 0xff 95 96 #define BITMAP_NO_RR 0 97 #define BITMAP_RR 1 98 99 #define MR_TYPE_MR 0x00 100 #define MR_TYPE_FRMR 0x01 101 #define MR_TYPE_DMA 0x03 102 103 #define HNS_ROCE_FRMR_MAX_PA 512 104 105 #define PKEY_ID 0xffff 106 #define GUID_LEN 8 107 #define NODE_DESC_SIZE 64 108 #define DB_REG_OFFSET 0x1000 109 110 /* Configure to HW for PAGE_SIZE larger than 4KB */ 111 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 112 113 #define PAGES_SHIFT_8 8 114 #define PAGES_SHIFT_16 16 115 #define PAGES_SHIFT_24 24 116 #define PAGES_SHIFT_32 32 117 118 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 119 #define SRQ_DB_REG 0x230 120 121 #define HNS_ROCE_QP_BANK_NUM 8 122 123 /* The chip implementation of the consumer index is calculated 124 * according to twice the actual EQ depth 125 */ 126 #define EQ_DEPTH_COEFF 2 127 128 enum { 129 SERV_TYPE_RC, 130 SERV_TYPE_UC, 131 SERV_TYPE_RD, 132 SERV_TYPE_UD, 133 }; 134 135 enum hns_roce_qp_state { 136 HNS_ROCE_QP_STATE_RST, 137 HNS_ROCE_QP_STATE_INIT, 138 HNS_ROCE_QP_STATE_RTR, 139 HNS_ROCE_QP_STATE_RTS, 140 HNS_ROCE_QP_STATE_SQD, 141 HNS_ROCE_QP_STATE_ERR, 142 HNS_ROCE_QP_NUM_STATE, 143 }; 144 145 enum hns_roce_event { 146 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 147 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 148 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 149 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 150 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 151 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 152 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 153 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 154 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 155 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 156 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 157 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 158 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 159 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 160 /* 0x10 and 0x11 is unused in currently application case */ 161 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 162 HNS_ROCE_EVENT_TYPE_MB = 0x13, 163 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 164 }; 165 166 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 167 enum { 168 HNS_ROCE_LWQCE_QPC_ERROR = 1, 169 HNS_ROCE_LWQCE_MTU_ERROR = 2, 170 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 171 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 172 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 173 HNS_ROCE_LWQCE_SL_ERROR = 6, 174 HNS_ROCE_LWQCE_PORT_ERROR = 7, 175 }; 176 177 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 178 enum { 179 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 180 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 181 HNS_ROCE_LAVWQE_VA_ERROR = 3, 182 HNS_ROCE_LAVWQE_PD_ERROR = 4, 183 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 184 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 185 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 186 }; 187 188 /* DOORBELL overflow subtype */ 189 enum { 190 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 191 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 192 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 193 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 194 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 195 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 196 }; 197 198 enum { 199 /* RQ&SRQ related operations */ 200 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 201 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 202 }; 203 204 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 205 206 enum { 207 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 208 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 209 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 210 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 211 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 212 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 213 HNS_ROCE_CAP_FLAG_MW = BIT(7), 214 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 215 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 216 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 217 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 218 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 219 }; 220 221 #define HNS_ROCE_DB_TYPE_COUNT 2 222 #define HNS_ROCE_DB_UNIT_SIZE 4 223 224 enum { 225 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 226 }; 227 228 enum hns_roce_reset_stage { 229 HNS_ROCE_STATE_NON_RST, 230 HNS_ROCE_STATE_RST_BEF_DOWN, 231 HNS_ROCE_STATE_RST_DOWN, 232 HNS_ROCE_STATE_RST_UNINIT, 233 HNS_ROCE_STATE_RST_INIT, 234 HNS_ROCE_STATE_RST_INITED, 235 }; 236 237 enum hns_roce_instance_state { 238 HNS_ROCE_STATE_NON_INIT, 239 HNS_ROCE_STATE_INIT, 240 HNS_ROCE_STATE_INITED, 241 HNS_ROCE_STATE_UNINIT, 242 }; 243 244 enum { 245 HNS_ROCE_RST_DIRECT_RETURN = 0, 246 }; 247 248 enum { 249 CMD_RST_PRC_OTHERS, 250 CMD_RST_PRC_SUCCESS, 251 CMD_RST_PRC_EBUSY, 252 }; 253 254 #define HNS_ROCE_CMD_SUCCESS 1 255 256 #define HNS_ROCE_PORT_DOWN 0 257 #define HNS_ROCE_PORT_UP 1 258 259 /* The minimum page size is 4K for hardware */ 260 #define HNS_HW_PAGE_SHIFT 12 261 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 262 263 struct hns_roce_uar { 264 u64 pfn; 265 unsigned long index; 266 unsigned long logic_idx; 267 }; 268 269 struct hns_roce_ucontext { 270 struct ib_ucontext ibucontext; 271 struct hns_roce_uar uar; 272 struct list_head page_list; 273 struct mutex page_mutex; 274 }; 275 276 struct hns_roce_pd { 277 struct ib_pd ibpd; 278 unsigned long pdn; 279 }; 280 281 struct hns_roce_bitmap { 282 /* Bitmap Traversal last a bit which is 1 */ 283 unsigned long last; 284 unsigned long top; 285 unsigned long max; 286 unsigned long reserved_top; 287 unsigned long mask; 288 spinlock_t lock; 289 unsigned long *table; 290 }; 291 292 /* For Hardware Entry Memory */ 293 struct hns_roce_hem_table { 294 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 295 u32 type; 296 /* HEM array elment num */ 297 unsigned long num_hem; 298 /* HEM entry record obj total num */ 299 unsigned long num_obj; 300 /* Single obj size */ 301 unsigned long obj_size; 302 unsigned long table_chunk_size; 303 int lowmem; 304 struct mutex mutex; 305 struct hns_roce_hem **hem; 306 u64 **bt_l1; 307 dma_addr_t *bt_l1_dma_addr; 308 u64 **bt_l0; 309 dma_addr_t *bt_l0_dma_addr; 310 }; 311 312 struct hns_roce_buf_region { 313 u32 offset; /* page offset */ 314 u32 count; /* page count */ 315 int hopnum; /* addressing hop num */ 316 }; 317 318 #define HNS_ROCE_MAX_BT_REGION 3 319 #define HNS_ROCE_MAX_BT_LEVEL 3 320 struct hns_roce_hem_list { 321 struct list_head root_bt; 322 /* link all bt dma mem by hop config */ 323 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 324 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 325 dma_addr_t root_ba; /* pointer to the root ba table */ 326 }; 327 328 struct hns_roce_buf_attr { 329 struct { 330 size_t size; /* region size */ 331 int hopnum; /* multi-hop addressing hop num */ 332 } region[HNS_ROCE_MAX_BT_REGION]; 333 unsigned int region_count; /* valid region count */ 334 unsigned int page_shift; /* buffer page shift */ 335 bool fixed_page; /* decide page shift is fixed-size or maximum size */ 336 unsigned int user_access; /* umem access flag */ 337 bool mtt_only; /* only alloc buffer-required MTT memory */ 338 }; 339 340 struct hns_roce_hem_cfg { 341 dma_addr_t root_ba; /* root BA table's address */ 342 bool is_direct; /* addressing without BA table */ 343 unsigned int ba_pg_shift; /* BA table page shift */ 344 unsigned int buf_pg_shift; /* buffer page shift */ 345 unsigned int buf_pg_count; /* buffer page count */ 346 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 347 unsigned int region_count; 348 }; 349 350 /* memory translate region */ 351 struct hns_roce_mtr { 352 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 353 struct ib_umem *umem; /* user space buffer */ 354 struct hns_roce_buf *kmem; /* kernel space buffer */ 355 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 356 }; 357 358 struct hns_roce_mw { 359 struct ib_mw ibmw; 360 u32 pdn; 361 u32 rkey; 362 int enabled; /* MW's active status */ 363 u32 pbl_hop_num; 364 u32 pbl_ba_pg_sz; 365 u32 pbl_buf_pg_sz; 366 }; 367 368 /* Only support 4K page size for mr register */ 369 #define MR_SIZE_4K 0 370 371 struct hns_roce_mr { 372 struct ib_mr ibmr; 373 u64 iova; /* MR's virtual orignal addr */ 374 u64 size; /* Address range of MR */ 375 u32 key; /* Key of MR */ 376 u32 pd; /* PD num of MR */ 377 u32 access; /* Access permission of MR */ 378 int enabled; /* MR's active status */ 379 int type; /* MR's register type */ 380 u32 pbl_hop_num; /* multi-hop number */ 381 struct hns_roce_mtr pbl_mtr; 382 u32 npages; 383 dma_addr_t *page_list; 384 }; 385 386 struct hns_roce_mr_table { 387 struct hns_roce_bitmap mtpt_bitmap; 388 struct hns_roce_hem_table mtpt_table; 389 }; 390 391 struct hns_roce_wq { 392 u64 *wrid; /* Work request ID */ 393 spinlock_t lock; 394 u32 wqe_cnt; /* WQE num */ 395 u32 max_gs; 396 int offset; 397 int wqe_shift; /* WQE size */ 398 u32 head; 399 u32 tail; 400 void __iomem *db_reg_l; 401 }; 402 403 struct hns_roce_sge { 404 unsigned int sge_cnt; /* SGE num */ 405 int offset; 406 int sge_shift; /* SGE size */ 407 }; 408 409 struct hns_roce_buf_list { 410 void *buf; 411 dma_addr_t map; 412 }; 413 414 /* 415 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 416 * dma address range. 417 * 418 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 419 * 420 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 421 * the allocated size is smaller than the required size. 422 */ 423 enum { 424 HNS_ROCE_BUF_DIRECT = BIT(0), 425 HNS_ROCE_BUF_NOSLEEP = BIT(1), 426 HNS_ROCE_BUF_NOFAIL = BIT(2), 427 }; 428 429 struct hns_roce_buf { 430 struct hns_roce_buf_list *trunk_list; 431 u32 ntrunks; 432 u32 npages; 433 unsigned int trunk_shift; 434 unsigned int page_shift; 435 }; 436 437 struct hns_roce_db_pgdir { 438 struct list_head list; 439 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 440 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 441 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 442 u32 *page; 443 dma_addr_t db_dma; 444 }; 445 446 struct hns_roce_user_db_page { 447 struct list_head list; 448 struct ib_umem *umem; 449 unsigned long user_virt; 450 refcount_t refcount; 451 }; 452 453 struct hns_roce_db { 454 u32 *db_record; 455 union { 456 struct hns_roce_db_pgdir *pgdir; 457 struct hns_roce_user_db_page *user_page; 458 } u; 459 dma_addr_t dma; 460 void *virt_addr; 461 unsigned long index; 462 unsigned long order; 463 }; 464 465 struct hns_roce_cq { 466 struct ib_cq ib_cq; 467 struct hns_roce_mtr mtr; 468 struct hns_roce_db db; 469 u32 flags; 470 spinlock_t lock; 471 u32 cq_depth; 472 u32 cons_index; 473 u32 *set_ci_db; 474 void __iomem *cq_db_l; 475 u16 *tptr_addr; 476 int arm_sn; 477 int cqe_size; 478 unsigned long cqn; 479 u32 vector; 480 atomic_t refcount; 481 struct completion free; 482 struct list_head sq_list; /* all qps on this send cq */ 483 struct list_head rq_list; /* all qps on this recv cq */ 484 int is_armed; /* cq is armed */ 485 struct list_head node; /* all armed cqs are on a list */ 486 }; 487 488 struct hns_roce_idx_que { 489 struct hns_roce_mtr mtr; 490 int entry_shift; 491 unsigned long *bitmap; 492 }; 493 494 struct hns_roce_srq { 495 struct ib_srq ibsrq; 496 unsigned long srqn; 497 u32 wqe_cnt; 498 int max_gs; 499 int wqe_shift; 500 void __iomem *db_reg_l; 501 502 atomic_t refcount; 503 struct completion free; 504 505 struct hns_roce_mtr buf_mtr; 506 507 u64 *wrid; 508 struct hns_roce_idx_que idx_que; 509 spinlock_t lock; 510 u16 head; 511 u16 tail; 512 struct mutex mutex; 513 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 514 }; 515 516 struct hns_roce_uar_table { 517 struct hns_roce_bitmap bitmap; 518 }; 519 520 struct hns_roce_bank { 521 struct ida ida; 522 u32 inuse; /* Number of IDs allocated */ 523 u32 min; /* Lowest ID to allocate. */ 524 u32 max; /* Highest ID to allocate. */ 525 u32 next; /* Next ID to allocate. */ 526 }; 527 528 struct hns_roce_qp_table { 529 struct hns_roce_hem_table qp_table; 530 struct hns_roce_hem_table irrl_table; 531 struct hns_roce_hem_table trrl_table; 532 struct hns_roce_hem_table sccc_table; 533 struct mutex scc_mutex; 534 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 535 spinlock_t bank_lock; 536 }; 537 538 struct hns_roce_cq_table { 539 struct hns_roce_bitmap bitmap; 540 struct xarray array; 541 struct hns_roce_hem_table table; 542 }; 543 544 struct hns_roce_srq_table { 545 struct hns_roce_bitmap bitmap; 546 struct xarray xa; 547 struct hns_roce_hem_table table; 548 }; 549 550 struct hns_roce_raq_table { 551 struct hns_roce_buf_list *e_raq_buf; 552 }; 553 554 struct hns_roce_av { 555 u8 port; 556 u8 gid_index; 557 u8 stat_rate; 558 u8 hop_limit; 559 u32 flowlabel; 560 u16 udp_sport; 561 u8 sl; 562 u8 tclass; 563 u8 dgid[HNS_ROCE_GID_SIZE]; 564 u8 mac[ETH_ALEN]; 565 u16 vlan_id; 566 u8 vlan_en; 567 }; 568 569 struct hns_roce_ah { 570 struct ib_ah ibah; 571 struct hns_roce_av av; 572 }; 573 574 struct hns_roce_cmd_context { 575 struct completion done; 576 int result; 577 int next; 578 u64 out_param; 579 u16 token; 580 }; 581 582 struct hns_roce_cmdq { 583 struct dma_pool *pool; 584 struct mutex hcr_mutex; 585 struct semaphore poll_sem; 586 /* 587 * Event mode: cmd register mutex protection, 588 * ensure to not exceed max_cmds and user use limit region 589 */ 590 struct semaphore event_sem; 591 int max_cmds; 592 spinlock_t context_lock; 593 int free_head; 594 struct hns_roce_cmd_context *context; 595 /* 596 * Result of get integer part 597 * which max_comds compute according a power of 2 598 */ 599 u16 token_mask; 600 /* 601 * Process whether use event mode, init default non-zero 602 * After the event queue of cmd event ready, 603 * can switch into event mode 604 * close device, switch into poll mode(non event mode) 605 */ 606 u8 use_events; 607 }; 608 609 struct hns_roce_cmd_mailbox { 610 void *buf; 611 dma_addr_t dma; 612 }; 613 614 struct hns_roce_dev; 615 616 struct hns_roce_rinl_sge { 617 void *addr; 618 u32 len; 619 }; 620 621 struct hns_roce_rinl_wqe { 622 struct hns_roce_rinl_sge *sg_list; 623 u32 sge_cnt; 624 }; 625 626 struct hns_roce_rinl_buf { 627 struct hns_roce_rinl_wqe *wqe_list; 628 u32 wqe_cnt; 629 }; 630 631 enum { 632 HNS_ROCE_FLUSH_FLAG = 0, 633 }; 634 635 struct hns_roce_work { 636 struct hns_roce_dev *hr_dev; 637 struct work_struct work; 638 int event_type; 639 int sub_type; 640 u32 queue_num; 641 }; 642 643 struct hns_roce_qp { 644 struct ib_qp ibqp; 645 struct hns_roce_wq rq; 646 struct hns_roce_db rdb; 647 struct hns_roce_db sdb; 648 unsigned long en_flags; 649 u32 doorbell_qpn; 650 u32 sq_signal_bits; 651 struct hns_roce_wq sq; 652 653 struct hns_roce_mtr mtr; 654 655 u32 buff_size; 656 struct mutex mutex; 657 u8 port; 658 u8 phy_port; 659 u8 sl; 660 u8 resp_depth; 661 u8 state; 662 u32 access_flags; 663 u32 atomic_rd_en; 664 u32 pkey_index; 665 u32 qkey; 666 void (*event)(struct hns_roce_qp *qp, 667 enum hns_roce_event event_type); 668 unsigned long qpn; 669 670 atomic_t refcount; 671 struct completion free; 672 673 struct hns_roce_sge sge; 674 u32 next_sge; 675 enum ib_mtu path_mtu; 676 u32 max_inline_data; 677 678 /* 0: flush needed, 1: unneeded */ 679 unsigned long flush_flag; 680 struct hns_roce_work flush_work; 681 struct hns_roce_rinl_buf rq_inl_buf; 682 struct list_head node; /* all qps are on a list */ 683 struct list_head rq_node; /* all recv qps are on a list */ 684 struct list_head sq_node; /* all send qps are on a list */ 685 }; 686 687 struct hns_roce_ib_iboe { 688 spinlock_t lock; 689 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 690 struct notifier_block nb; 691 u8 phy_port[HNS_ROCE_MAX_PORTS]; 692 }; 693 694 enum { 695 HNS_ROCE_EQ_STAT_INVALID = 0, 696 HNS_ROCE_EQ_STAT_VALID = 2, 697 }; 698 699 struct hns_roce_ceqe { 700 __le32 comp; 701 __le32 rsv[15]; 702 }; 703 704 struct hns_roce_aeqe { 705 __le32 asyn; 706 union { 707 struct { 708 __le32 num; 709 u32 rsv0; 710 u32 rsv1; 711 } queue_event; 712 713 struct { 714 __le64 out_param; 715 __le16 token; 716 u8 status; 717 u8 rsv0; 718 } __packed cmd; 719 } event; 720 __le32 rsv[12]; 721 }; 722 723 struct hns_roce_eq { 724 struct hns_roce_dev *hr_dev; 725 void __iomem *doorbell; 726 727 int type_flag; /* Aeq:1 ceq:0 */ 728 int eqn; 729 u32 entries; 730 u32 log_entries; 731 int eqe_size; 732 int irq; 733 int log_page_size; 734 u32 cons_index; 735 struct hns_roce_buf_list *buf_list; 736 int over_ignore; 737 int coalesce; 738 int arm_st; 739 int hop_num; 740 struct hns_roce_mtr mtr; 741 u16 eq_max_cnt; 742 u32 eq_period; 743 int shift; 744 int event_type; 745 int sub_type; 746 }; 747 748 struct hns_roce_eq_table { 749 struct hns_roce_eq *eq; 750 void __iomem **eqc_base; /* only for hw v1 */ 751 }; 752 753 struct hns_roce_caps { 754 u64 fw_ver; 755 u8 num_ports; 756 int gid_table_len[HNS_ROCE_MAX_PORTS]; 757 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 758 int local_ca_ack_delay; 759 int num_uars; 760 u32 phy_num_uars; 761 u32 max_sq_sg; 762 u32 max_sq_inline; 763 u32 max_rq_sg; 764 u32 max_extend_sg; 765 u32 num_qps; 766 u32 reserved_qps; 767 int num_qpc_timer; 768 int num_cqc_timer; 769 int num_srqs; 770 u32 max_wqes; 771 u32 max_srq_wrs; 772 u32 max_srq_sges; 773 u32 max_sq_desc_sz; 774 u32 max_rq_desc_sz; 775 u32 max_srq_desc_sz; 776 int max_qp_init_rdma; 777 int max_qp_dest_rdma; 778 u32 num_cqs; 779 u32 max_cqes; 780 u32 min_cqes; 781 u32 min_wqes; 782 int reserved_cqs; 783 int reserved_srqs; 784 int num_aeq_vectors; 785 int num_comp_vectors; 786 int num_other_vectors; 787 u32 num_mtpts; 788 u32 num_mtt_segs; 789 u32 num_cqe_segs; 790 u32 num_srqwqe_segs; 791 u32 num_idx_segs; 792 int reserved_mrws; 793 int reserved_uars; 794 int num_pds; 795 int reserved_pds; 796 u32 mtt_entry_sz; 797 u32 cqe_sz; 798 u32 page_size_cap; 799 u32 reserved_lkey; 800 int mtpt_entry_sz; 801 int qpc_sz; 802 int irrl_entry_sz; 803 int trrl_entry_sz; 804 int cqc_entry_sz; 805 int sccc_sz; 806 int qpc_timer_entry_sz; 807 int cqc_timer_entry_sz; 808 int srqc_entry_sz; 809 int idx_entry_sz; 810 u32 pbl_ba_pg_sz; 811 u32 pbl_buf_pg_sz; 812 u32 pbl_hop_num; 813 int aeqe_depth; 814 int ceqe_depth; 815 u32 aeqe_size; 816 u32 ceqe_size; 817 enum ib_mtu max_mtu; 818 u32 qpc_bt_num; 819 u32 qpc_timer_bt_num; 820 u32 srqc_bt_num; 821 u32 cqc_bt_num; 822 u32 cqc_timer_bt_num; 823 u32 mpt_bt_num; 824 u32 sccc_bt_num; 825 u32 gmv_bt_num; 826 u32 qpc_ba_pg_sz; 827 u32 qpc_buf_pg_sz; 828 u32 qpc_hop_num; 829 u32 srqc_ba_pg_sz; 830 u32 srqc_buf_pg_sz; 831 u32 srqc_hop_num; 832 u32 cqc_ba_pg_sz; 833 u32 cqc_buf_pg_sz; 834 u32 cqc_hop_num; 835 u32 mpt_ba_pg_sz; 836 u32 mpt_buf_pg_sz; 837 u32 mpt_hop_num; 838 u32 mtt_ba_pg_sz; 839 u32 mtt_buf_pg_sz; 840 u32 mtt_hop_num; 841 u32 wqe_sq_hop_num; 842 u32 wqe_sge_hop_num; 843 u32 wqe_rq_hop_num; 844 u32 sccc_ba_pg_sz; 845 u32 sccc_buf_pg_sz; 846 u32 sccc_hop_num; 847 u32 qpc_timer_ba_pg_sz; 848 u32 qpc_timer_buf_pg_sz; 849 u32 qpc_timer_hop_num; 850 u32 cqc_timer_ba_pg_sz; 851 u32 cqc_timer_buf_pg_sz; 852 u32 cqc_timer_hop_num; 853 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 854 u32 cqe_buf_pg_sz; 855 u32 cqe_hop_num; 856 u32 srqwqe_ba_pg_sz; 857 u32 srqwqe_buf_pg_sz; 858 u32 srqwqe_hop_num; 859 u32 idx_ba_pg_sz; 860 u32 idx_buf_pg_sz; 861 u32 idx_hop_num; 862 u32 eqe_ba_pg_sz; 863 u32 eqe_buf_pg_sz; 864 u32 eqe_hop_num; 865 u32 gmv_entry_num; 866 u32 gmv_entry_sz; 867 u32 gmv_ba_pg_sz; 868 u32 gmv_buf_pg_sz; 869 u32 gmv_hop_num; 870 u32 sl_num; 871 u32 tsq_buf_pg_sz; 872 u32 tpq_buf_pg_sz; 873 u32 chunk_sz; /* chunk size in non multihop mode */ 874 u64 flags; 875 u16 default_ceq_max_cnt; 876 u16 default_ceq_period; 877 u16 default_aeq_max_cnt; 878 u16 default_aeq_period; 879 u16 default_aeq_arm_st; 880 u16 default_ceq_arm_st; 881 }; 882 883 struct hns_roce_dfx_hw { 884 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 885 int *buffer); 886 }; 887 888 enum hns_roce_device_state { 889 HNS_ROCE_DEVICE_STATE_INITED, 890 HNS_ROCE_DEVICE_STATE_RST_DOWN, 891 HNS_ROCE_DEVICE_STATE_UNINIT, 892 }; 893 894 struct hns_roce_hw { 895 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 896 int (*cmq_init)(struct hns_roce_dev *hr_dev); 897 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 898 int (*hw_profile)(struct hns_roce_dev *hr_dev); 899 int (*hw_init)(struct hns_roce_dev *hr_dev); 900 void (*hw_exit)(struct hns_roce_dev *hr_dev); 901 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 902 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 903 u16 token, int event); 904 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout); 905 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 906 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 907 const union ib_gid *gid, const struct ib_gid_attr *attr); 908 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 909 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 910 enum ib_mtu mtu); 911 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 912 struct hns_roce_mr *mr, unsigned long mtpt_idx); 913 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 914 struct hns_roce_mr *mr, int flags, u32 pdn, 915 int mr_access_flags, u64 iova, u64 size, 916 void *mb_buf); 917 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 918 struct hns_roce_mr *mr); 919 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 920 void (*write_cqc)(struct hns_roce_dev *hr_dev, 921 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 922 dma_addr_t dma_handle); 923 int (*set_hem)(struct hns_roce_dev *hr_dev, 924 struct hns_roce_hem_table *table, int obj, int step_idx); 925 int (*clear_hem)(struct hns_roce_dev *hr_dev, 926 struct hns_roce_hem_table *table, int obj, 927 int step_idx); 928 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 929 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 930 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 931 int attr_mask, enum ib_qp_state cur_state, 932 enum ib_qp_state new_state); 933 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 934 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 935 struct hns_roce_qp *hr_qp); 936 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 937 const struct ib_send_wr **bad_wr); 938 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 939 const struct ib_recv_wr **bad_recv_wr); 940 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 941 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 942 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 943 struct ib_udata *udata); 944 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 945 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 946 int (*init_eq)(struct hns_roce_dev *hr_dev); 947 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 948 void (*write_srqc)(struct hns_roce_dev *hr_dev, 949 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 950 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 951 dma_addr_t dma_handle_wqe, 952 dma_addr_t dma_handle_idx); 953 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 954 enum ib_srq_attr_mask srq_attr_mask, 955 struct ib_udata *udata); 956 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 957 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 958 const struct ib_recv_wr **bad_wr); 959 const struct ib_device_ops *hns_roce_dev_ops; 960 const struct ib_device_ops *hns_roce_dev_srq_ops; 961 }; 962 963 struct hns_roce_dev { 964 struct ib_device ib_dev; 965 struct platform_device *pdev; 966 struct pci_dev *pci_dev; 967 struct device *dev; 968 struct hns_roce_uar priv_uar; 969 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 970 spinlock_t sm_lock; 971 spinlock_t bt_cmd_lock; 972 bool active; 973 bool is_reset; 974 bool dis_db; 975 unsigned long reset_cnt; 976 struct hns_roce_ib_iboe iboe; 977 enum hns_roce_device_state state; 978 struct list_head qp_list; /* list of all qps on this dev */ 979 spinlock_t qp_list_lock; /* protect qp_list */ 980 981 struct list_head pgdir_list; 982 struct mutex pgdir_mutex; 983 int irq[HNS_ROCE_MAX_IRQ_NUM]; 984 u8 __iomem *reg_base; 985 struct hns_roce_caps caps; 986 struct xarray qp_table_xa; 987 988 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 989 u64 sys_image_guid; 990 u32 vendor_id; 991 u32 vendor_part_id; 992 u32 hw_rev; 993 void __iomem *priv_addr; 994 995 struct hns_roce_cmdq cmd; 996 struct hns_roce_bitmap pd_bitmap; 997 struct hns_roce_uar_table uar_table; 998 struct hns_roce_mr_table mr_table; 999 struct hns_roce_cq_table cq_table; 1000 struct hns_roce_srq_table srq_table; 1001 struct hns_roce_qp_table qp_table; 1002 struct hns_roce_eq_table eq_table; 1003 struct hns_roce_hem_table qpc_timer_table; 1004 struct hns_roce_hem_table cqc_timer_table; 1005 /* GMV is the memory area that the driver allocates for the hardware 1006 * to store SGID, SMAC and VLAN information. 1007 */ 1008 struct hns_roce_hem_table gmv_table; 1009 1010 int cmd_mod; 1011 int loop_idc; 1012 u32 sdb_offset; 1013 u32 odb_offset; 1014 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1015 u32 tptr_size; /* only for hw v1 */ 1016 const struct hns_roce_hw *hw; 1017 void *priv; 1018 struct workqueue_struct *irq_workq; 1019 const struct hns_roce_dfx_hw *dfx; 1020 }; 1021 1022 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1023 { 1024 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1025 } 1026 1027 static inline struct hns_roce_ucontext 1028 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1029 { 1030 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1031 } 1032 1033 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1034 { 1035 return container_of(ibpd, struct hns_roce_pd, ibpd); 1036 } 1037 1038 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1039 { 1040 return container_of(ibah, struct hns_roce_ah, ibah); 1041 } 1042 1043 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1044 { 1045 return container_of(ibmr, struct hns_roce_mr, ibmr); 1046 } 1047 1048 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1049 { 1050 return container_of(ibmw, struct hns_roce_mw, ibmw); 1051 } 1052 1053 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1054 { 1055 return container_of(ibqp, struct hns_roce_qp, ibqp); 1056 } 1057 1058 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1059 { 1060 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1061 } 1062 1063 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1064 { 1065 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1066 } 1067 1068 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1069 { 1070 __raw_writeq(*(u64 *) val, dest); 1071 } 1072 1073 static inline struct hns_roce_qp 1074 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1075 { 1076 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1077 } 1078 1079 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1080 unsigned int offset) 1081 { 1082 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1083 (offset & ((1 << buf->trunk_shift) - 1)); 1084 } 1085 1086 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1087 { 1088 unsigned int offset = idx << buf->page_shift; 1089 1090 return buf->trunk_list[offset >> buf->trunk_shift].map + 1091 (offset & ((1 << buf->trunk_shift) - 1)); 1092 } 1093 1094 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1095 1096 static inline u64 to_hr_hw_page_addr(u64 addr) 1097 { 1098 return addr >> HNS_HW_PAGE_SHIFT; 1099 } 1100 1101 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1102 { 1103 return page_shift - HNS_HW_PAGE_SHIFT; 1104 } 1105 1106 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1107 { 1108 if (count > 0) 1109 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1110 1111 return 0; 1112 } 1113 1114 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1115 { 1116 return hr_hw_page_align(count << buf_shift); 1117 } 1118 1119 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1120 { 1121 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1122 } 1123 1124 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1125 { 1126 if (!count) 1127 return 0; 1128 1129 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1130 } 1131 1132 #define DSCP_SHIFT 2 1133 1134 static inline u8 get_tclass(const struct ib_global_route *grh) 1135 { 1136 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1137 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1138 } 1139 1140 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1141 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1142 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1143 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1144 1145 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1146 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1147 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1148 u64 out_param); 1149 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1150 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1151 1152 /* hns roce hw need current block and next block addr from mtt */ 1153 #define MTT_MIN_COUNT 2 1154 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1155 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1156 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1157 struct hns_roce_buf_attr *buf_attr, 1158 unsigned int page_shift, struct ib_udata *udata, 1159 unsigned long user_addr); 1160 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1161 struct hns_roce_mtr *mtr); 1162 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1163 dma_addr_t *pages, unsigned int page_cnt); 1164 1165 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1166 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1167 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1168 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1169 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1170 1171 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1172 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1173 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1174 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1175 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1176 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1177 1178 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1179 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1180 int rr); 1181 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1182 u32 reserved_bot, u32 resetrved_top); 1183 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1184 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1185 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1186 int align, unsigned long *obj); 1187 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1188 unsigned long obj, int cnt, 1189 int rr); 1190 1191 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1192 struct ib_udata *udata); 1193 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1194 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1195 { 1196 return 0; 1197 } 1198 1199 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1200 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1201 1202 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1203 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1204 u64 virt_addr, int access_flags, 1205 struct ib_udata *udata); 1206 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1207 u64 length, u64 virt_addr, 1208 int mr_access_flags, struct ib_pd *pd, 1209 struct ib_udata *udata); 1210 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1211 u32 max_num_sg); 1212 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1213 unsigned int *sg_offset); 1214 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1215 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1216 struct hns_roce_cmd_mailbox *mailbox, 1217 unsigned long mpt_index); 1218 unsigned long key_to_hw_index(u32 key); 1219 1220 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1221 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1222 1223 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1224 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1225 u32 page_shift, u32 flags); 1226 1227 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1228 int buf_cnt, int start, struct hns_roce_buf *buf); 1229 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1230 int buf_cnt, int start, struct ib_umem *umem, 1231 unsigned int page_shift); 1232 1233 int hns_roce_create_srq(struct ib_srq *srq, 1234 struct ib_srq_init_attr *srq_init_attr, 1235 struct ib_udata *udata); 1236 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1237 enum ib_srq_attr_mask srq_attr_mask, 1238 struct ib_udata *udata); 1239 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1240 1241 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1242 struct ib_qp_init_attr *init_attr, 1243 struct ib_udata *udata); 1244 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1245 int attr_mask, struct ib_udata *udata); 1246 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1247 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1248 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1249 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1250 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1251 struct ib_cq *ib_cq); 1252 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1253 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1254 struct hns_roce_cq *recv_cq); 1255 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1256 struct hns_roce_cq *recv_cq); 1257 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1258 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1259 struct ib_udata *udata); 1260 __be32 send_ieth(const struct ib_send_wr *wr); 1261 int to_hr_qp_type(int qp_type); 1262 1263 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1264 struct ib_udata *udata); 1265 1266 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1267 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1268 struct ib_udata *udata, unsigned long virt, 1269 struct hns_roce_db *db); 1270 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1271 struct hns_roce_db *db); 1272 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1273 int order); 1274 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1275 1276 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1277 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1278 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1279 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1280 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1281 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1282 int hns_roce_init(struct hns_roce_dev *hr_dev); 1283 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1284 1285 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, 1286 struct ib_cq *ib_cq); 1287 #endif /* _HNS_ROCE_DEVICE_H */ 1288