1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 /* hip08 is a pci device, it includes two version according pci version id */ 41 #define PCI_REVISION_ID_HIP08_A 0x20 42 #define PCI_REVISION_ID_HIP08_B 0x21 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 49 50 #define HNS_ROCE_BA_SIZE (32 * 4096) 51 52 #define BA_BYTE_LEN 8 53 54 /* Hardware specification only for v1 engine */ 55 #define HNS_ROCE_MIN_CQE_NUM 0x40 56 #define HNS_ROCE_MIN_WQE_NUM 0x20 57 58 /* Hardware specification only for v1 engine */ 59 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 60 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 61 #define HNS_ROCE_MAX_SGE_NUM 2 62 63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 65 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 67 #define HNS_ROCE_MIN_CQE_CNT 16 68 69 #define HNS_ROCE_MAX_IRQ_NUM 128 70 71 #define HNS_ROCE_SGE_IN_WQE 2 72 #define HNS_ROCE_SGE_SHIFT 4 73 74 #define EQ_ENABLE 1 75 #define EQ_DISABLE 0 76 77 #define HNS_ROCE_CEQ 0 78 #define HNS_ROCE_AEQ 1 79 80 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 81 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 82 83 #define HNS_ROCE_SL_SHIFT 28 84 #define HNS_ROCE_TCLASS_SHIFT 20 85 #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff 86 87 #define HNS_ROCE_MAX_PORTS 6 88 #define HNS_ROCE_MAX_GID_NUM 16 89 #define HNS_ROCE_GID_SIZE 16 90 #define HNS_ROCE_SGE_SIZE 16 91 92 #define HNS_ROCE_HOP_NUM_0 0xff 93 94 #define BITMAP_NO_RR 0 95 #define BITMAP_RR 1 96 97 #define MR_TYPE_MR 0x00 98 #define MR_TYPE_FRMR 0x01 99 #define MR_TYPE_DMA 0x03 100 101 #define HNS_ROCE_FRMR_MAX_PA 512 102 103 #define PKEY_ID 0xffff 104 #define GUID_LEN 8 105 #define NODE_DESC_SIZE 64 106 #define DB_REG_OFFSET 0x1000 107 108 /* Configure to HW for PAGE_SIZE larger than 4KB */ 109 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 110 111 #define PAGES_SHIFT_8 8 112 #define PAGES_SHIFT_16 16 113 #define PAGES_SHIFT_24 24 114 #define PAGES_SHIFT_32 32 115 116 #define HNS_ROCE_PCI_BAR_NUM 2 117 118 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 119 #define SRQ_DB_REG 0x230 120 121 /* The chip implementation of the consumer index is calculated 122 * according to twice the actual EQ depth 123 */ 124 #define EQ_DEPTH_COEFF 2 125 126 enum { 127 SERV_TYPE_RC, 128 SERV_TYPE_UC, 129 SERV_TYPE_RD, 130 SERV_TYPE_UD, 131 }; 132 133 enum { 134 HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0, 135 HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1, 136 }; 137 138 enum { 139 HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0, 140 }; 141 142 enum hns_roce_qp_state { 143 HNS_ROCE_QP_STATE_RST, 144 HNS_ROCE_QP_STATE_INIT, 145 HNS_ROCE_QP_STATE_RTR, 146 HNS_ROCE_QP_STATE_RTS, 147 HNS_ROCE_QP_STATE_SQD, 148 HNS_ROCE_QP_STATE_ERR, 149 HNS_ROCE_QP_NUM_STATE, 150 }; 151 152 enum hns_roce_event { 153 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 154 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 155 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 156 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 157 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 158 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 159 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 160 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 161 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 162 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 163 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 164 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 165 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 166 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 167 /* 0x10 and 0x11 is unused in currently application case */ 168 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 169 HNS_ROCE_EVENT_TYPE_MB = 0x13, 170 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 171 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 172 }; 173 174 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 175 enum { 176 HNS_ROCE_LWQCE_QPC_ERROR = 1, 177 HNS_ROCE_LWQCE_MTU_ERROR = 2, 178 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 179 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 180 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 181 HNS_ROCE_LWQCE_SL_ERROR = 6, 182 HNS_ROCE_LWQCE_PORT_ERROR = 7, 183 }; 184 185 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 186 enum { 187 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 188 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 189 HNS_ROCE_LAVWQE_VA_ERROR = 3, 190 HNS_ROCE_LAVWQE_PD_ERROR = 4, 191 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 192 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 193 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 194 }; 195 196 /* DOORBELL overflow subtype */ 197 enum { 198 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 199 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 200 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 201 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 202 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 203 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 204 }; 205 206 enum { 207 /* RQ&SRQ related operations */ 208 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 209 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 210 }; 211 212 enum { 213 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 214 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 215 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 216 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 217 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 218 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 219 HNS_ROCE_CAP_FLAG_MW = BIT(7), 220 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 221 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 222 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 223 }; 224 225 enum hns_roce_mtt_type { 226 MTT_TYPE_WQE, 227 MTT_TYPE_CQE, 228 MTT_TYPE_SRQWQE, 229 MTT_TYPE_IDX 230 }; 231 232 #define HNS_ROCE_DB_TYPE_COUNT 2 233 #define HNS_ROCE_DB_UNIT_SIZE 4 234 235 enum { 236 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 237 }; 238 239 enum hns_roce_reset_stage { 240 HNS_ROCE_STATE_NON_RST, 241 HNS_ROCE_STATE_RST_BEF_DOWN, 242 HNS_ROCE_STATE_RST_DOWN, 243 HNS_ROCE_STATE_RST_UNINIT, 244 HNS_ROCE_STATE_RST_INIT, 245 HNS_ROCE_STATE_RST_INITED, 246 }; 247 248 enum hns_roce_instance_state { 249 HNS_ROCE_STATE_NON_INIT, 250 HNS_ROCE_STATE_INIT, 251 HNS_ROCE_STATE_INITED, 252 HNS_ROCE_STATE_UNINIT, 253 }; 254 255 enum { 256 HNS_ROCE_RST_DIRECT_RETURN = 0, 257 }; 258 259 enum { 260 CMD_RST_PRC_OTHERS, 261 CMD_RST_PRC_SUCCESS, 262 CMD_RST_PRC_EBUSY, 263 }; 264 265 #define HNS_ROCE_CMD_SUCCESS 1 266 267 #define HNS_ROCE_PORT_DOWN 0 268 #define HNS_ROCE_PORT_UP 1 269 270 #define HNS_ROCE_MTT_ENTRY_PER_SEG 8 271 272 #define PAGE_ADDR_SHIFT 12 273 274 struct hns_roce_uar { 275 u64 pfn; 276 unsigned long index; 277 unsigned long logic_idx; 278 }; 279 280 struct hns_roce_ucontext { 281 struct ib_ucontext ibucontext; 282 struct hns_roce_uar uar; 283 struct list_head page_list; 284 struct mutex page_mutex; 285 }; 286 287 struct hns_roce_pd { 288 struct ib_pd ibpd; 289 unsigned long pdn; 290 }; 291 292 struct hns_roce_bitmap { 293 /* Bitmap Traversal last a bit which is 1 */ 294 unsigned long last; 295 unsigned long top; 296 unsigned long max; 297 unsigned long reserved_top; 298 unsigned long mask; 299 spinlock_t lock; 300 unsigned long *table; 301 }; 302 303 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */ 304 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ 305 /* Every bit repesent to a partner free/used status in bitmap */ 306 /* 307 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 308 * Bit = 1 represent to idle and available; bit = 0: not available 309 */ 310 struct hns_roce_buddy { 311 /* Members point to every order level bitmap */ 312 unsigned long **bits; 313 /* Represent to avail bits of the order level bitmap */ 314 u32 *num_free; 315 int max_order; 316 spinlock_t lock; 317 }; 318 319 /* For Hardware Entry Memory */ 320 struct hns_roce_hem_table { 321 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 322 u32 type; 323 /* HEM array elment num */ 324 unsigned long num_hem; 325 /* HEM entry record obj total num */ 326 unsigned long num_obj; 327 /* Single obj size */ 328 unsigned long obj_size; 329 unsigned long table_chunk_size; 330 int lowmem; 331 struct mutex mutex; 332 struct hns_roce_hem **hem; 333 u64 **bt_l1; 334 dma_addr_t *bt_l1_dma_addr; 335 u64 **bt_l0; 336 dma_addr_t *bt_l0_dma_addr; 337 }; 338 339 struct hns_roce_mtt { 340 unsigned long first_seg; 341 int order; 342 int page_shift; 343 enum hns_roce_mtt_type mtt_type; 344 }; 345 346 struct hns_roce_buf_region { 347 int offset; /* page offset */ 348 u32 count; /* page count */ 349 int hopnum; /* addressing hop num */ 350 }; 351 352 #define HNS_ROCE_MAX_BT_REGION 3 353 #define HNS_ROCE_MAX_BT_LEVEL 3 354 struct hns_roce_hem_list { 355 struct list_head root_bt; 356 /* link all bt dma mem by hop config */ 357 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 358 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 359 dma_addr_t root_ba; /* pointer to the root ba table */ 360 int bt_pg_shift; 361 }; 362 363 /* memory translate region */ 364 struct hns_roce_mtr { 365 struct hns_roce_hem_list hem_list; 366 int buf_pg_shift; 367 }; 368 369 struct hns_roce_mw { 370 struct ib_mw ibmw; 371 u32 pdn; 372 u32 rkey; 373 int enabled; /* MW's active status */ 374 u32 pbl_hop_num; 375 u32 pbl_ba_pg_sz; 376 u32 pbl_buf_pg_sz; 377 }; 378 379 /* Only support 4K page size for mr register */ 380 #define MR_SIZE_4K 0 381 382 struct hns_roce_mr { 383 struct ib_mr ibmr; 384 struct ib_umem *umem; 385 u64 iova; /* MR's virtual orignal addr */ 386 u64 size; /* Address range of MR */ 387 u32 key; /* Key of MR */ 388 u32 pd; /* PD num of MR */ 389 u32 access; /* Access permission of MR */ 390 u32 npages; 391 int enabled; /* MR's active status */ 392 int type; /* MR's register type */ 393 u64 *pbl_buf; /* MR's PBL space */ 394 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ 395 u32 pbl_size; /* PA number in the PBL */ 396 u64 pbl_ba; /* page table address */ 397 u32 l0_chunk_last_num; /* L0 last number */ 398 u32 l1_chunk_last_num; /* L1 last number */ 399 u64 **pbl_bt_l2; /* PBL BT L2 */ 400 u64 **pbl_bt_l1; /* PBL BT L1 */ 401 u64 *pbl_bt_l0; /* PBL BT L0 */ 402 dma_addr_t *pbl_l2_dma_addr; /* PBL BT L2 dma addr */ 403 dma_addr_t *pbl_l1_dma_addr; /* PBL BT L1 dma addr */ 404 dma_addr_t pbl_l0_dma_addr; /* PBL BT L0 dma addr */ 405 u32 pbl_ba_pg_sz; /* BT chunk page size */ 406 u32 pbl_buf_pg_sz; /* buf chunk page size */ 407 u32 pbl_hop_num; /* multi-hop number */ 408 }; 409 410 struct hns_roce_mr_table { 411 struct hns_roce_bitmap mtpt_bitmap; 412 struct hns_roce_buddy mtt_buddy; 413 struct hns_roce_hem_table mtt_table; 414 struct hns_roce_hem_table mtpt_table; 415 struct hns_roce_buddy mtt_cqe_buddy; 416 struct hns_roce_hem_table mtt_cqe_table; 417 struct hns_roce_buddy mtt_srqwqe_buddy; 418 struct hns_roce_hem_table mtt_srqwqe_table; 419 struct hns_roce_buddy mtt_idx_buddy; 420 struct hns_roce_hem_table mtt_idx_table; 421 }; 422 423 struct hns_roce_wq { 424 u64 *wrid; /* Work request ID */ 425 spinlock_t lock; 426 u32 wqe_cnt; /* WQE num */ 427 int max_gs; 428 int offset; 429 int wqe_shift; /* WQE size */ 430 u32 head; 431 u32 tail; 432 void __iomem *db_reg_l; 433 }; 434 435 struct hns_roce_sge { 436 int sge_cnt; /* SGE num */ 437 int offset; 438 int sge_shift; /* SGE size */ 439 }; 440 441 struct hns_roce_buf_list { 442 void *buf; 443 dma_addr_t map; 444 }; 445 446 struct hns_roce_buf { 447 struct hns_roce_buf_list direct; 448 struct hns_roce_buf_list *page_list; 449 int nbufs; 450 u32 npages; 451 u32 size; 452 int page_shift; 453 }; 454 455 struct hns_roce_db_pgdir { 456 struct list_head list; 457 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 458 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 459 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 460 u32 *page; 461 dma_addr_t db_dma; 462 }; 463 464 struct hns_roce_user_db_page { 465 struct list_head list; 466 struct ib_umem *umem; 467 unsigned long user_virt; 468 refcount_t refcount; 469 }; 470 471 struct hns_roce_db { 472 u32 *db_record; 473 union { 474 struct hns_roce_db_pgdir *pgdir; 475 struct hns_roce_user_db_page *user_page; 476 } u; 477 dma_addr_t dma; 478 void *virt_addr; 479 int index; 480 int order; 481 }; 482 483 struct hns_roce_cq { 484 struct ib_cq ib_cq; 485 struct hns_roce_buf buf; 486 struct hns_roce_mtt mtt; 487 struct hns_roce_db db; 488 u8 db_en; 489 spinlock_t lock; 490 struct ib_umem *umem; 491 u32 cq_depth; 492 u32 cons_index; 493 u32 *set_ci_db; 494 void __iomem *cq_db_l; 495 u16 *tptr_addr; 496 int arm_sn; 497 unsigned long cqn; 498 u32 vector; 499 atomic_t refcount; 500 struct completion free; 501 struct list_head sq_list; /* all qps on this send cq */ 502 struct list_head rq_list; /* all qps on this recv cq */ 503 int is_armed; /* cq is armed */ 504 struct list_head node; /* all armed cqs are on a list */ 505 }; 506 507 struct hns_roce_idx_que { 508 struct hns_roce_buf idx_buf; 509 int entry_sz; 510 u32 buf_size; 511 struct ib_umem *umem; 512 struct hns_roce_mtt mtt; 513 unsigned long *bitmap; 514 }; 515 516 struct hns_roce_srq { 517 struct ib_srq ibsrq; 518 unsigned long srqn; 519 u32 wqe_cnt; 520 int max_gs; 521 int wqe_shift; 522 void __iomem *db_reg_l; 523 524 atomic_t refcount; 525 struct completion free; 526 527 struct hns_roce_buf buf; 528 u64 *wrid; 529 struct ib_umem *umem; 530 struct hns_roce_mtt mtt; 531 struct hns_roce_idx_que idx_que; 532 spinlock_t lock; 533 int head; 534 int tail; 535 struct mutex mutex; 536 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 537 }; 538 539 struct hns_roce_uar_table { 540 struct hns_roce_bitmap bitmap; 541 }; 542 543 struct hns_roce_qp_table { 544 struct hns_roce_bitmap bitmap; 545 struct hns_roce_hem_table qp_table; 546 struct hns_roce_hem_table irrl_table; 547 struct hns_roce_hem_table trrl_table; 548 struct hns_roce_hem_table sccc_table; 549 struct mutex scc_mutex; 550 }; 551 552 struct hns_roce_cq_table { 553 struct hns_roce_bitmap bitmap; 554 struct xarray array; 555 struct hns_roce_hem_table table; 556 }; 557 558 struct hns_roce_srq_table { 559 struct hns_roce_bitmap bitmap; 560 struct xarray xa; 561 struct hns_roce_hem_table table; 562 }; 563 564 struct hns_roce_raq_table { 565 struct hns_roce_buf_list *e_raq_buf; 566 }; 567 568 struct hns_roce_av { 569 u8 port; 570 u8 gid_index; 571 u8 stat_rate; 572 u8 hop_limit; 573 u32 flowlabel; 574 u8 sl; 575 u8 tclass; 576 u8 dgid[HNS_ROCE_GID_SIZE]; 577 u8 mac[ETH_ALEN]; 578 u16 vlan_id; 579 bool vlan_en; 580 }; 581 582 struct hns_roce_ah { 583 struct ib_ah ibah; 584 struct hns_roce_av av; 585 }; 586 587 struct hns_roce_cmd_context { 588 struct completion done; 589 int result; 590 int next; 591 u64 out_param; 592 u16 token; 593 }; 594 595 struct hns_roce_cmdq { 596 struct dma_pool *pool; 597 struct mutex hcr_mutex; 598 struct semaphore poll_sem; 599 /* 600 * Event mode: cmd register mutex protection, 601 * ensure to not exceed max_cmds and user use limit region 602 */ 603 struct semaphore event_sem; 604 int max_cmds; 605 spinlock_t context_lock; 606 int free_head; 607 struct hns_roce_cmd_context *context; 608 /* 609 * Result of get integer part 610 * which max_comds compute according a power of 2 611 */ 612 u16 token_mask; 613 /* 614 * Process whether use event mode, init default non-zero 615 * After the event queue of cmd event ready, 616 * can switch into event mode 617 * close device, switch into poll mode(non event mode) 618 */ 619 u8 use_events; 620 }; 621 622 struct hns_roce_cmd_mailbox { 623 void *buf; 624 dma_addr_t dma; 625 }; 626 627 struct hns_roce_dev; 628 629 struct hns_roce_rinl_sge { 630 void *addr; 631 u32 len; 632 }; 633 634 struct hns_roce_rinl_wqe { 635 struct hns_roce_rinl_sge *sg_list; 636 u32 sge_cnt; 637 }; 638 639 struct hns_roce_rinl_buf { 640 struct hns_roce_rinl_wqe *wqe_list; 641 u32 wqe_cnt; 642 }; 643 644 enum { 645 HNS_ROCE_FLUSH_FLAG = 0, 646 }; 647 648 struct hns_roce_work { 649 struct hns_roce_dev *hr_dev; 650 struct work_struct work; 651 u32 qpn; 652 u32 cqn; 653 int event_type; 654 int sub_type; 655 }; 656 657 struct hns_roce_qp { 658 struct ib_qp ibqp; 659 struct hns_roce_buf hr_buf; 660 struct hns_roce_wq rq; 661 struct hns_roce_db rdb; 662 struct hns_roce_db sdb; 663 u8 rdb_en; 664 u8 sdb_en; 665 u32 doorbell_qpn; 666 u32 sq_signal_bits; 667 struct hns_roce_wq sq; 668 669 struct ib_umem *umem; 670 struct hns_roce_mtt mtt; 671 struct hns_roce_mtr mtr; 672 int wqe_bt_pg_shift; 673 674 u32 buff_size; 675 struct mutex mutex; 676 u8 port; 677 u8 phy_port; 678 u8 sl; 679 u8 resp_depth; 680 u8 state; 681 u32 access_flags; 682 u32 atomic_rd_en; 683 u32 pkey_index; 684 u32 qkey; 685 void (*event)(struct hns_roce_qp *qp, 686 enum hns_roce_event event_type); 687 unsigned long qpn; 688 689 atomic_t refcount; 690 struct completion free; 691 692 struct hns_roce_sge sge; 693 u32 next_sge; 694 695 /* 0: flush needed, 1: unneeded */ 696 unsigned long flush_flag; 697 struct hns_roce_work flush_work; 698 struct hns_roce_rinl_buf rq_inl_buf; 699 struct list_head node; /* all qps are on a list */ 700 struct list_head rq_node; /* all recv qps are on a list */ 701 struct list_head sq_node; /* all send qps are on a list */ 702 }; 703 704 struct hns_roce_ib_iboe { 705 spinlock_t lock; 706 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 707 struct notifier_block nb; 708 u8 phy_port[HNS_ROCE_MAX_PORTS]; 709 }; 710 711 enum { 712 HNS_ROCE_EQ_STAT_INVALID = 0, 713 HNS_ROCE_EQ_STAT_VALID = 2, 714 }; 715 716 struct hns_roce_ceqe { 717 __le32 comp; 718 }; 719 720 struct hns_roce_aeqe { 721 __le32 asyn; 722 union { 723 struct { 724 __le32 qp; 725 u32 rsv0; 726 u32 rsv1; 727 } qp_event; 728 729 struct { 730 __le32 srq; 731 u32 rsv0; 732 u32 rsv1; 733 } srq_event; 734 735 struct { 736 __le32 cq; 737 u32 rsv0; 738 u32 rsv1; 739 } cq_event; 740 741 struct { 742 __le32 ceqe; 743 u32 rsv0; 744 u32 rsv1; 745 } ce_event; 746 747 struct { 748 __le64 out_param; 749 __le16 token; 750 u8 status; 751 u8 rsv0; 752 } __packed cmd; 753 } event; 754 }; 755 756 struct hns_roce_eq { 757 struct hns_roce_dev *hr_dev; 758 void __iomem *doorbell; 759 760 int type_flag; /* Aeq:1 ceq:0 */ 761 int eqn; 762 u32 entries; 763 int log_entries; 764 int eqe_size; 765 int irq; 766 int log_page_size; 767 int cons_index; 768 struct hns_roce_buf_list *buf_list; 769 int over_ignore; 770 int coalesce; 771 int arm_st; 772 u64 eqe_ba; 773 int eqe_ba_pg_sz; 774 int eqe_buf_pg_sz; 775 int hop_num; 776 struct hns_roce_mtr mtr; 777 struct hns_roce_buf buf; 778 int eq_max_cnt; 779 int eq_period; 780 int shift; 781 dma_addr_t cur_eqe_ba; 782 dma_addr_t nxt_eqe_ba; 783 int event_type; 784 int sub_type; 785 }; 786 787 struct hns_roce_eq_table { 788 struct hns_roce_eq *eq; 789 void __iomem **eqc_base; /* only for hw v1 */ 790 }; 791 792 struct hns_roce_caps { 793 u64 fw_ver; 794 u8 num_ports; 795 int gid_table_len[HNS_ROCE_MAX_PORTS]; 796 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 797 int local_ca_ack_delay; 798 int num_uars; 799 u32 phy_num_uars; 800 u32 max_sq_sg; 801 u32 max_sq_inline; 802 u32 max_rq_sg; 803 u32 max_extend_sg; 804 int num_qps; 805 int reserved_qps; 806 int num_qpc_timer; 807 int num_cqc_timer; 808 int num_srqs; 809 u32 max_wqes; 810 u32 max_srq_wrs; 811 u32 max_srq_sges; 812 u32 max_sq_desc_sz; 813 u32 max_rq_desc_sz; 814 u32 max_srq_desc_sz; 815 int max_qp_init_rdma; 816 int max_qp_dest_rdma; 817 int num_cqs; 818 u32 max_cqes; 819 u32 min_cqes; 820 u32 min_wqes; 821 int reserved_cqs; 822 int reserved_srqs; 823 int num_aeq_vectors; 824 int num_comp_vectors; 825 int num_other_vectors; 826 int num_mtpts; 827 u32 num_mtt_segs; 828 u32 num_cqe_segs; 829 u32 num_srqwqe_segs; 830 u32 num_idx_segs; 831 int reserved_mrws; 832 int reserved_uars; 833 int num_pds; 834 int reserved_pds; 835 u32 mtt_entry_sz; 836 u32 cq_entry_sz; 837 u32 page_size_cap; 838 u32 reserved_lkey; 839 int mtpt_entry_sz; 840 int qpc_entry_sz; 841 int irrl_entry_sz; 842 int trrl_entry_sz; 843 int cqc_entry_sz; 844 int sccc_entry_sz; 845 int qpc_timer_entry_sz; 846 int cqc_timer_entry_sz; 847 int srqc_entry_sz; 848 int idx_entry_sz; 849 u32 pbl_ba_pg_sz; 850 u32 pbl_buf_pg_sz; 851 u32 pbl_hop_num; 852 int aeqe_depth; 853 int ceqe_depth; 854 enum ib_mtu max_mtu; 855 u32 qpc_bt_num; 856 u32 qpc_timer_bt_num; 857 u32 srqc_bt_num; 858 u32 cqc_bt_num; 859 u32 cqc_timer_bt_num; 860 u32 mpt_bt_num; 861 u32 sccc_bt_num; 862 u32 qpc_ba_pg_sz; 863 u32 qpc_buf_pg_sz; 864 u32 qpc_hop_num; 865 u32 srqc_ba_pg_sz; 866 u32 srqc_buf_pg_sz; 867 u32 srqc_hop_num; 868 u32 cqc_ba_pg_sz; 869 u32 cqc_buf_pg_sz; 870 u32 cqc_hop_num; 871 u32 mpt_ba_pg_sz; 872 u32 mpt_buf_pg_sz; 873 u32 mpt_hop_num; 874 u32 mtt_ba_pg_sz; 875 u32 mtt_buf_pg_sz; 876 u32 mtt_hop_num; 877 u32 wqe_sq_hop_num; 878 u32 wqe_sge_hop_num; 879 u32 wqe_rq_hop_num; 880 u32 sccc_ba_pg_sz; 881 u32 sccc_buf_pg_sz; 882 u32 sccc_hop_num; 883 u32 qpc_timer_ba_pg_sz; 884 u32 qpc_timer_buf_pg_sz; 885 u32 qpc_timer_hop_num; 886 u32 cqc_timer_ba_pg_sz; 887 u32 cqc_timer_buf_pg_sz; 888 u32 cqc_timer_hop_num; 889 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 890 u32 cqe_buf_pg_sz; 891 u32 cqe_hop_num; 892 u32 srqwqe_ba_pg_sz; 893 u32 srqwqe_buf_pg_sz; 894 u32 srqwqe_hop_num; 895 u32 idx_ba_pg_sz; 896 u32 idx_buf_pg_sz; 897 u32 idx_hop_num; 898 u32 eqe_ba_pg_sz; 899 u32 eqe_buf_pg_sz; 900 u32 eqe_hop_num; 901 u32 sl_num; 902 u32 tsq_buf_pg_sz; 903 u32 tpq_buf_pg_sz; 904 u32 chunk_sz; /* chunk size in non multihop mode */ 905 u64 flags; 906 u16 default_ceq_max_cnt; 907 u16 default_ceq_period; 908 u16 default_aeq_max_cnt; 909 u16 default_aeq_period; 910 u16 default_aeq_arm_st; 911 u16 default_ceq_arm_st; 912 }; 913 914 struct hns_roce_dfx_hw { 915 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 916 int *buffer); 917 }; 918 919 enum hns_roce_device_state { 920 HNS_ROCE_DEVICE_STATE_INITED, 921 HNS_ROCE_DEVICE_STATE_RST_DOWN, 922 HNS_ROCE_DEVICE_STATE_UNINIT, 923 }; 924 925 struct hns_roce_hw { 926 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 927 int (*cmq_init)(struct hns_roce_dev *hr_dev); 928 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 929 int (*hw_profile)(struct hns_roce_dev *hr_dev); 930 int (*hw_init)(struct hns_roce_dev *hr_dev); 931 void (*hw_exit)(struct hns_roce_dev *hr_dev); 932 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 933 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 934 u16 token, int event); 935 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 936 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 937 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 938 const union ib_gid *gid, const struct ib_gid_attr *attr); 939 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 940 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 941 enum ib_mtu mtu); 942 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 943 unsigned long mtpt_idx); 944 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 945 struct hns_roce_mr *mr, int flags, u32 pdn, 946 int mr_access_flags, u64 iova, u64 size, 947 void *mb_buf); 948 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 949 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 950 void (*write_cqc)(struct hns_roce_dev *hr_dev, 951 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 952 dma_addr_t dma_handle); 953 int (*set_hem)(struct hns_roce_dev *hr_dev, 954 struct hns_roce_hem_table *table, int obj, int step_idx); 955 int (*clear_hem)(struct hns_roce_dev *hr_dev, 956 struct hns_roce_hem_table *table, int obj, 957 int step_idx); 958 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 959 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 960 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 961 int attr_mask, enum ib_qp_state cur_state, 962 enum ib_qp_state new_state); 963 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 964 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 965 struct hns_roce_qp *hr_qp); 966 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 967 const struct ib_send_wr **bad_wr); 968 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 969 const struct ib_recv_wr **bad_recv_wr); 970 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 971 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 972 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 973 struct ib_udata *udata); 974 void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 975 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 976 int (*init_eq)(struct hns_roce_dev *hr_dev); 977 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 978 void (*write_srqc)(struct hns_roce_dev *hr_dev, 979 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 980 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 981 dma_addr_t dma_handle_wqe, 982 dma_addr_t dma_handle_idx); 983 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 984 enum ib_srq_attr_mask srq_attr_mask, 985 struct ib_udata *udata); 986 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 987 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 988 const struct ib_recv_wr **bad_wr); 989 const struct ib_device_ops *hns_roce_dev_ops; 990 const struct ib_device_ops *hns_roce_dev_srq_ops; 991 }; 992 993 struct hns_roce_dev { 994 struct ib_device ib_dev; 995 struct platform_device *pdev; 996 struct pci_dev *pci_dev; 997 struct device *dev; 998 struct hns_roce_uar priv_uar; 999 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 1000 spinlock_t sm_lock; 1001 spinlock_t bt_cmd_lock; 1002 bool active; 1003 bool is_reset; 1004 bool dis_db; 1005 unsigned long reset_cnt; 1006 struct hns_roce_ib_iboe iboe; 1007 enum hns_roce_device_state state; 1008 struct list_head qp_list; /* list of all qps on this dev */ 1009 spinlock_t qp_list_lock; /* protect qp_list */ 1010 1011 struct list_head pgdir_list; 1012 struct mutex pgdir_mutex; 1013 int irq[HNS_ROCE_MAX_IRQ_NUM]; 1014 u8 __iomem *reg_base; 1015 struct hns_roce_caps caps; 1016 struct xarray qp_table_xa; 1017 1018 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 1019 u64 sys_image_guid; 1020 u32 vendor_id; 1021 u32 vendor_part_id; 1022 u32 hw_rev; 1023 void __iomem *priv_addr; 1024 1025 struct hns_roce_cmdq cmd; 1026 struct hns_roce_bitmap pd_bitmap; 1027 struct hns_roce_uar_table uar_table; 1028 struct hns_roce_mr_table mr_table; 1029 struct hns_roce_cq_table cq_table; 1030 struct hns_roce_srq_table srq_table; 1031 struct hns_roce_qp_table qp_table; 1032 struct hns_roce_eq_table eq_table; 1033 struct hns_roce_hem_table qpc_timer_table; 1034 struct hns_roce_hem_table cqc_timer_table; 1035 1036 int cmd_mod; 1037 int loop_idc; 1038 u32 sdb_offset; 1039 u32 odb_offset; 1040 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1041 u32 tptr_size; /* only for hw v1 */ 1042 const struct hns_roce_hw *hw; 1043 void *priv; 1044 struct workqueue_struct *irq_workq; 1045 const struct hns_roce_dfx_hw *dfx; 1046 }; 1047 1048 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1049 { 1050 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1051 } 1052 1053 static inline struct hns_roce_ucontext 1054 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1055 { 1056 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1057 } 1058 1059 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1060 { 1061 return container_of(ibpd, struct hns_roce_pd, ibpd); 1062 } 1063 1064 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1065 { 1066 return container_of(ibah, struct hns_roce_ah, ibah); 1067 } 1068 1069 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1070 { 1071 return container_of(ibmr, struct hns_roce_mr, ibmr); 1072 } 1073 1074 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1075 { 1076 return container_of(ibmw, struct hns_roce_mw, ibmw); 1077 } 1078 1079 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1080 { 1081 return container_of(ibqp, struct hns_roce_qp, ibqp); 1082 } 1083 1084 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1085 { 1086 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1087 } 1088 1089 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1090 { 1091 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1092 } 1093 1094 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1095 { 1096 __raw_writeq(*(u64 *) val, dest); 1097 } 1098 1099 static inline struct hns_roce_qp 1100 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1101 { 1102 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1103 } 1104 1105 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 1106 { 1107 u32 page_size = 1 << buf->page_shift; 1108 1109 if (buf->nbufs == 1) 1110 return (char *)(buf->direct.buf) + offset; 1111 else 1112 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 1113 (offset & (page_size - 1)); 1114 } 1115 1116 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1117 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1118 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1119 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1120 1121 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1122 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1123 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1124 u64 out_param); 1125 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1126 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1127 1128 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, 1129 struct hns_roce_mtt *mtt); 1130 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, 1131 struct hns_roce_mtt *mtt); 1132 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, 1133 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf); 1134 1135 void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, 1136 int buf_pg_shift); 1137 int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1138 dma_addr_t **bufs, struct hns_roce_buf_region *regions, 1139 int region_cnt); 1140 void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev, 1141 struct hns_roce_mtr *mtr); 1142 1143 /* hns roce hw need current block and next block addr from mtt */ 1144 #define MTT_MIN_COUNT 2 1145 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1146 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1147 1148 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1149 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1150 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1151 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1152 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1153 1154 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1155 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1156 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1157 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1158 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1159 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1160 1161 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1162 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1163 int rr); 1164 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1165 u32 reserved_bot, u32 resetrved_top); 1166 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1167 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1168 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1169 int align, unsigned long *obj); 1170 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1171 unsigned long obj, int cnt, 1172 int rr); 1173 1174 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, 1175 u32 flags, struct ib_udata *udata); 1176 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1177 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags); 1178 1179 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1180 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1181 1182 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1183 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1184 u64 virt_addr, int access_flags, 1185 struct ib_udata *udata); 1186 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 1187 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 1188 struct ib_udata *udata); 1189 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1190 u32 max_num_sg, struct ib_udata *udata); 1191 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1192 unsigned int *sg_offset); 1193 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1194 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1195 struct hns_roce_cmd_mailbox *mailbox, 1196 unsigned long mpt_index); 1197 unsigned long key_to_hw_index(u32 key); 1198 1199 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, 1200 struct ib_udata *udata); 1201 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1202 1203 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 1204 struct hns_roce_buf *buf); 1205 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1206 struct hns_roce_buf *buf, u32 page_shift); 1207 1208 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 1209 struct hns_roce_mtt *mtt, struct ib_umem *umem); 1210 1211 void hns_roce_init_buf_region(struct hns_roce_buf_region *region, int hopnum, 1212 int offset, int buf_cnt); 1213 int hns_roce_alloc_buf_list(struct hns_roce_buf_region *regions, 1214 dma_addr_t **bufs, int count); 1215 void hns_roce_free_buf_list(dma_addr_t **bufs, int count); 1216 1217 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1218 int buf_cnt, int start, struct hns_roce_buf *buf); 1219 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1220 int buf_cnt, int start, struct ib_umem *umem, 1221 int page_shift); 1222 1223 int hns_roce_create_srq(struct ib_srq *srq, 1224 struct ib_srq_init_attr *srq_init_attr, 1225 struct ib_udata *udata); 1226 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1227 enum ib_srq_attr_mask srq_attr_mask, 1228 struct ib_udata *udata); 1229 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1230 1231 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1232 struct ib_qp_init_attr *init_attr, 1233 struct ib_udata *udata); 1234 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1235 int attr_mask, struct ib_udata *udata); 1236 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1237 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1238 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1239 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n); 1240 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1241 struct ib_cq *ib_cq); 1242 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1243 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1244 struct hns_roce_cq *recv_cq); 1245 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1246 struct hns_roce_cq *recv_cq); 1247 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1248 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1249 struct ib_udata *udata); 1250 __be32 send_ieth(const struct ib_send_wr *wr); 1251 int to_hr_qp_type(int qp_type); 1252 1253 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1254 struct ib_udata *udata); 1255 1256 void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1257 void hns_roce_free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq); 1258 1259 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1260 struct ib_udata *udata, unsigned long virt, 1261 struct hns_roce_db *db); 1262 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1263 struct hns_roce_db *db); 1264 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1265 int order); 1266 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1267 1268 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1269 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1270 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1271 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1272 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1273 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1274 int hns_roce_init(struct hns_roce_dev *hr_dev); 1275 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1276 1277 int hns_roce_fill_res_entry(struct sk_buff *msg, 1278 struct rdma_restrack_entry *res); 1279 #endif /* _HNS_ROCE_DEVICE_H */ 1280