1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define DRV_NAME "hns_roce" 40 41 #define PCI_REVISION_ID_HIP08 0x21 42 #define PCI_REVISION_ID_HIP09 0x30 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 49 50 #define HNS_ROCE_BA_SIZE (32 * 4096) 51 52 #define BA_BYTE_LEN 8 53 54 /* Hardware specification only for v1 engine */ 55 #define HNS_ROCE_MIN_CQE_NUM 0x40 56 #define HNS_ROCE_MIN_WQE_NUM 0x20 57 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 58 59 /* Hardware specification only for v1 engine */ 60 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 61 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 62 63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 65 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 67 #define HNS_ROCE_MIN_CQE_CNT 16 68 69 #define HNS_ROCE_RESERVED_SGE 1 70 71 #define HNS_ROCE_MAX_IRQ_NUM 128 72 73 #define HNS_ROCE_SGE_IN_WQE 2 74 #define HNS_ROCE_SGE_SHIFT 4 75 76 #define EQ_ENABLE 1 77 #define EQ_DISABLE 0 78 79 #define HNS_ROCE_CEQ 0 80 #define HNS_ROCE_AEQ 1 81 82 #define HNS_ROCE_CEQE_SIZE 0x4 83 #define HNS_ROCE_AEQE_SIZE 0x10 84 85 #define HNS_ROCE_V3_EQE_SIZE 0x40 86 87 #define HNS_ROCE_V2_CQE_SIZE 32 88 #define HNS_ROCE_V3_CQE_SIZE 64 89 90 #define HNS_ROCE_V2_QPC_SZ 256 91 #define HNS_ROCE_V3_QPC_SZ 512 92 93 #define HNS_ROCE_MAX_PORTS 6 94 #define HNS_ROCE_GID_SIZE 16 95 #define HNS_ROCE_SGE_SIZE 16 96 #define HNS_ROCE_DWQE_SIZE 65536 97 98 #define HNS_ROCE_HOP_NUM_0 0xff 99 100 #define BITMAP_NO_RR 0 101 #define BITMAP_RR 1 102 103 #define MR_TYPE_MR 0x00 104 #define MR_TYPE_FRMR 0x01 105 #define MR_TYPE_DMA 0x03 106 107 #define HNS_ROCE_FRMR_MAX_PA 512 108 109 #define PKEY_ID 0xffff 110 #define GUID_LEN 8 111 #define NODE_DESC_SIZE 64 112 #define DB_REG_OFFSET 0x1000 113 114 /* Configure to HW for PAGE_SIZE larger than 4KB */ 115 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 116 117 #define PAGES_SHIFT_8 8 118 #define PAGES_SHIFT_16 16 119 #define PAGES_SHIFT_24 24 120 #define PAGES_SHIFT_32 32 121 122 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 123 #define SRQ_DB_REG 0x230 124 125 #define HNS_ROCE_QP_BANK_NUM 8 126 #define HNS_ROCE_CQ_BANK_NUM 4 127 128 #define CQ_BANKID_SHIFT 2 129 130 /* The chip implementation of the consumer index is calculated 131 * according to twice the actual EQ depth 132 */ 133 #define EQ_DEPTH_COEFF 2 134 135 enum { 136 SERV_TYPE_RC, 137 SERV_TYPE_UC, 138 SERV_TYPE_RD, 139 SERV_TYPE_UD, 140 SERV_TYPE_XRC = 5, 141 }; 142 143 enum hns_roce_qp_state { 144 HNS_ROCE_QP_STATE_RST, 145 HNS_ROCE_QP_STATE_INIT, 146 HNS_ROCE_QP_STATE_RTR, 147 HNS_ROCE_QP_STATE_RTS, 148 HNS_ROCE_QP_STATE_SQD, 149 HNS_ROCE_QP_STATE_ERR, 150 HNS_ROCE_QP_NUM_STATE, 151 }; 152 153 enum hns_roce_event { 154 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 155 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 156 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 157 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 158 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 159 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 160 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 161 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 162 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 163 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 164 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 165 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 166 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 167 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 168 /* 0x10 and 0x11 is unused in currently application case */ 169 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 170 HNS_ROCE_EVENT_TYPE_MB = 0x13, 171 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 172 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 173 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 174 }; 175 176 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 177 178 enum { 179 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 180 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 181 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 182 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 183 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 184 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 185 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 186 HNS_ROCE_CAP_FLAG_MW = BIT(7), 187 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 188 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 189 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 190 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 191 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 192 }; 193 194 #define HNS_ROCE_DB_TYPE_COUNT 2 195 #define HNS_ROCE_DB_UNIT_SIZE 4 196 197 enum { 198 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 199 }; 200 201 enum hns_roce_reset_stage { 202 HNS_ROCE_STATE_NON_RST, 203 HNS_ROCE_STATE_RST_BEF_DOWN, 204 HNS_ROCE_STATE_RST_DOWN, 205 HNS_ROCE_STATE_RST_UNINIT, 206 HNS_ROCE_STATE_RST_INIT, 207 HNS_ROCE_STATE_RST_INITED, 208 }; 209 210 enum hns_roce_instance_state { 211 HNS_ROCE_STATE_NON_INIT, 212 HNS_ROCE_STATE_INIT, 213 HNS_ROCE_STATE_INITED, 214 HNS_ROCE_STATE_UNINIT, 215 }; 216 217 enum { 218 HNS_ROCE_RST_DIRECT_RETURN = 0, 219 }; 220 221 #define HNS_ROCE_CMD_SUCCESS 1 222 223 /* The minimum page size is 4K for hardware */ 224 #define HNS_HW_PAGE_SHIFT 12 225 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 226 227 struct hns_roce_uar { 228 u64 pfn; 229 unsigned long index; 230 unsigned long logic_idx; 231 }; 232 233 struct hns_roce_ucontext { 234 struct ib_ucontext ibucontext; 235 struct hns_roce_uar uar; 236 struct list_head page_list; 237 struct mutex page_mutex; 238 }; 239 240 struct hns_roce_pd { 241 struct ib_pd ibpd; 242 unsigned long pdn; 243 }; 244 245 struct hns_roce_xrcd { 246 struct ib_xrcd ibxrcd; 247 u32 xrcdn; 248 }; 249 250 struct hns_roce_bitmap { 251 /* Bitmap Traversal last a bit which is 1 */ 252 unsigned long last; 253 unsigned long top; 254 unsigned long max; 255 unsigned long reserved_top; 256 unsigned long mask; 257 spinlock_t lock; 258 unsigned long *table; 259 }; 260 261 /* For Hardware Entry Memory */ 262 struct hns_roce_hem_table { 263 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 264 u32 type; 265 /* HEM array elment num */ 266 unsigned long num_hem; 267 /* HEM entry record obj total num */ 268 unsigned long num_obj; 269 /* Single obj size */ 270 unsigned long obj_size; 271 unsigned long table_chunk_size; 272 int lowmem; 273 struct mutex mutex; 274 struct hns_roce_hem **hem; 275 u64 **bt_l1; 276 dma_addr_t *bt_l1_dma_addr; 277 u64 **bt_l0; 278 dma_addr_t *bt_l0_dma_addr; 279 }; 280 281 struct hns_roce_buf_region { 282 u32 offset; /* page offset */ 283 u32 count; /* page count */ 284 int hopnum; /* addressing hop num */ 285 }; 286 287 #define HNS_ROCE_MAX_BT_REGION 3 288 #define HNS_ROCE_MAX_BT_LEVEL 3 289 struct hns_roce_hem_list { 290 struct list_head root_bt; 291 /* link all bt dma mem by hop config */ 292 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 293 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 294 dma_addr_t root_ba; /* pointer to the root ba table */ 295 }; 296 297 struct hns_roce_buf_attr { 298 struct { 299 size_t size; /* region size */ 300 int hopnum; /* multi-hop addressing hop num */ 301 } region[HNS_ROCE_MAX_BT_REGION]; 302 unsigned int region_count; /* valid region count */ 303 unsigned int page_shift; /* buffer page shift */ 304 unsigned int user_access; /* umem access flag */ 305 bool mtt_only; /* only alloc buffer-required MTT memory */ 306 }; 307 308 struct hns_roce_hem_cfg { 309 dma_addr_t root_ba; /* root BA table's address */ 310 bool is_direct; /* addressing without BA table */ 311 unsigned int ba_pg_shift; /* BA table page shift */ 312 unsigned int buf_pg_shift; /* buffer page shift */ 313 unsigned int buf_pg_count; /* buffer page count */ 314 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 315 unsigned int region_count; 316 }; 317 318 /* memory translate region */ 319 struct hns_roce_mtr { 320 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 321 struct ib_umem *umem; /* user space buffer */ 322 struct hns_roce_buf *kmem; /* kernel space buffer */ 323 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 324 }; 325 326 struct hns_roce_mw { 327 struct ib_mw ibmw; 328 u32 pdn; 329 u32 rkey; 330 int enabled; /* MW's active status */ 331 u32 pbl_hop_num; 332 u32 pbl_ba_pg_sz; 333 u32 pbl_buf_pg_sz; 334 }; 335 336 /* Only support 4K page size for mr register */ 337 #define MR_SIZE_4K 0 338 339 struct hns_roce_mr { 340 struct ib_mr ibmr; 341 u64 iova; /* MR's virtual orignal addr */ 342 u64 size; /* Address range of MR */ 343 u32 key; /* Key of MR */ 344 u32 pd; /* PD num of MR */ 345 u32 access; /* Access permission of MR */ 346 int enabled; /* MR's active status */ 347 int type; /* MR's register type */ 348 u32 pbl_hop_num; /* multi-hop number */ 349 struct hns_roce_mtr pbl_mtr; 350 u32 npages; 351 dma_addr_t *page_list; 352 }; 353 354 struct hns_roce_mr_table { 355 struct hns_roce_bitmap mtpt_bitmap; 356 struct hns_roce_hem_table mtpt_table; 357 }; 358 359 struct hns_roce_wq { 360 u64 *wrid; /* Work request ID */ 361 spinlock_t lock; 362 u32 wqe_cnt; /* WQE num */ 363 u32 max_gs; 364 u32 rsv_sge; 365 int offset; 366 int wqe_shift; /* WQE size */ 367 u32 head; 368 u32 tail; 369 void __iomem *db_reg; 370 }; 371 372 struct hns_roce_sge { 373 unsigned int sge_cnt; /* SGE num */ 374 int offset; 375 int sge_shift; /* SGE size */ 376 }; 377 378 struct hns_roce_buf_list { 379 void *buf; 380 dma_addr_t map; 381 }; 382 383 /* 384 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 385 * dma address range. 386 * 387 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 388 * 389 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 390 * the allocated size is smaller than the required size. 391 */ 392 enum { 393 HNS_ROCE_BUF_DIRECT = BIT(0), 394 HNS_ROCE_BUF_NOSLEEP = BIT(1), 395 HNS_ROCE_BUF_NOFAIL = BIT(2), 396 }; 397 398 struct hns_roce_buf { 399 struct hns_roce_buf_list *trunk_list; 400 u32 ntrunks; 401 u32 npages; 402 unsigned int trunk_shift; 403 unsigned int page_shift; 404 }; 405 406 struct hns_roce_db_pgdir { 407 struct list_head list; 408 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 409 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 410 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 411 u32 *page; 412 dma_addr_t db_dma; 413 }; 414 415 struct hns_roce_user_db_page { 416 struct list_head list; 417 struct ib_umem *umem; 418 unsigned long user_virt; 419 refcount_t refcount; 420 }; 421 422 struct hns_roce_db { 423 u32 *db_record; 424 union { 425 struct hns_roce_db_pgdir *pgdir; 426 struct hns_roce_user_db_page *user_page; 427 } u; 428 dma_addr_t dma; 429 void *virt_addr; 430 unsigned long index; 431 unsigned long order; 432 }; 433 434 struct hns_roce_cq { 435 struct ib_cq ib_cq; 436 struct hns_roce_mtr mtr; 437 struct hns_roce_db db; 438 u32 flags; 439 spinlock_t lock; 440 u32 cq_depth; 441 u32 cons_index; 442 u32 *set_ci_db; 443 void __iomem *db_reg; 444 u16 *tptr_addr; 445 int arm_sn; 446 int cqe_size; 447 unsigned long cqn; 448 u32 vector; 449 atomic_t refcount; 450 struct completion free; 451 struct list_head sq_list; /* all qps on this send cq */ 452 struct list_head rq_list; /* all qps on this recv cq */ 453 int is_armed; /* cq is armed */ 454 struct list_head node; /* all armed cqs are on a list */ 455 }; 456 457 struct hns_roce_idx_que { 458 struct hns_roce_mtr mtr; 459 int entry_shift; 460 unsigned long *bitmap; 461 u32 head; 462 u32 tail; 463 }; 464 465 struct hns_roce_srq { 466 struct ib_srq ibsrq; 467 unsigned long srqn; 468 u32 wqe_cnt; 469 int max_gs; 470 u32 rsv_sge; 471 int wqe_shift; 472 u32 cqn; 473 u32 xrcdn; 474 void __iomem *db_reg; 475 476 atomic_t refcount; 477 struct completion free; 478 479 struct hns_roce_mtr buf_mtr; 480 481 u64 *wrid; 482 struct hns_roce_idx_que idx_que; 483 spinlock_t lock; 484 struct mutex mutex; 485 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 486 }; 487 488 struct hns_roce_uar_table { 489 struct hns_roce_bitmap bitmap; 490 }; 491 492 struct hns_roce_bank { 493 struct ida ida; 494 u32 inuse; /* Number of IDs allocated */ 495 u32 min; /* Lowest ID to allocate. */ 496 u32 max; /* Highest ID to allocate. */ 497 u32 next; /* Next ID to allocate. */ 498 }; 499 500 struct hns_roce_qp_table { 501 struct hns_roce_hem_table qp_table; 502 struct hns_roce_hem_table irrl_table; 503 struct hns_roce_hem_table trrl_table; 504 struct hns_roce_hem_table sccc_table; 505 struct mutex scc_mutex; 506 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 507 struct mutex bank_mutex; 508 }; 509 510 struct hns_roce_cq_table { 511 struct xarray array; 512 struct hns_roce_hem_table table; 513 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 514 struct mutex bank_mutex; 515 }; 516 517 struct hns_roce_srq_table { 518 struct hns_roce_bitmap bitmap; 519 struct xarray xa; 520 struct hns_roce_hem_table table; 521 }; 522 523 struct hns_roce_raq_table { 524 struct hns_roce_buf_list *e_raq_buf; 525 }; 526 527 struct hns_roce_av { 528 u8 port; 529 u8 gid_index; 530 u8 stat_rate; 531 u8 hop_limit; 532 u32 flowlabel; 533 u16 udp_sport; 534 u8 sl; 535 u8 tclass; 536 u8 dgid[HNS_ROCE_GID_SIZE]; 537 u8 mac[ETH_ALEN]; 538 u16 vlan_id; 539 u8 vlan_en; 540 }; 541 542 struct hns_roce_ah { 543 struct ib_ah ibah; 544 struct hns_roce_av av; 545 }; 546 547 struct hns_roce_cmd_context { 548 struct completion done; 549 int result; 550 int next; 551 u64 out_param; 552 u16 token; 553 u16 busy; 554 }; 555 556 struct hns_roce_cmdq { 557 struct dma_pool *pool; 558 struct mutex hcr_mutex; 559 struct semaphore poll_sem; 560 /* 561 * Event mode: cmd register mutex protection, 562 * ensure to not exceed max_cmds and user use limit region 563 */ 564 struct semaphore event_sem; 565 int max_cmds; 566 spinlock_t context_lock; 567 int free_head; 568 struct hns_roce_cmd_context *context; 569 /* 570 * Process whether use event mode, init default non-zero 571 * After the event queue of cmd event ready, 572 * can switch into event mode 573 * close device, switch into poll mode(non event mode) 574 */ 575 u8 use_events; 576 }; 577 578 struct hns_roce_cmd_mailbox { 579 void *buf; 580 dma_addr_t dma; 581 }; 582 583 struct hns_roce_dev; 584 585 struct hns_roce_rinl_sge { 586 void *addr; 587 u32 len; 588 }; 589 590 struct hns_roce_rinl_wqe { 591 struct hns_roce_rinl_sge *sg_list; 592 u32 sge_cnt; 593 }; 594 595 struct hns_roce_rinl_buf { 596 struct hns_roce_rinl_wqe *wqe_list; 597 u32 wqe_cnt; 598 }; 599 600 enum { 601 HNS_ROCE_FLUSH_FLAG = 0, 602 }; 603 604 struct hns_roce_work { 605 struct hns_roce_dev *hr_dev; 606 struct work_struct work; 607 int event_type; 608 int sub_type; 609 u32 queue_num; 610 }; 611 612 enum { 613 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), 614 }; 615 616 struct hns_roce_qp { 617 struct ib_qp ibqp; 618 struct hns_roce_wq rq; 619 struct hns_roce_db rdb; 620 struct hns_roce_db sdb; 621 unsigned long en_flags; 622 u32 doorbell_qpn; 623 enum ib_sig_type sq_signal_bits; 624 struct hns_roce_wq sq; 625 626 struct hns_roce_mtr mtr; 627 628 u32 buff_size; 629 struct mutex mutex; 630 u8 port; 631 u8 phy_port; 632 u8 sl; 633 u8 resp_depth; 634 u8 state; 635 u32 access_flags; 636 u32 atomic_rd_en; 637 u32 pkey_index; 638 u32 qkey; 639 void (*event)(struct hns_roce_qp *qp, 640 enum hns_roce_event event_type); 641 unsigned long qpn; 642 643 u32 xrcdn; 644 645 atomic_t refcount; 646 struct completion free; 647 648 struct hns_roce_sge sge; 649 u32 next_sge; 650 enum ib_mtu path_mtu; 651 u32 max_inline_data; 652 653 /* 0: flush needed, 1: unneeded */ 654 unsigned long flush_flag; 655 struct hns_roce_work flush_work; 656 struct hns_roce_rinl_buf rq_inl_buf; 657 struct list_head node; /* all qps are on a list */ 658 struct list_head rq_node; /* all recv qps are on a list */ 659 struct list_head sq_node; /* all send qps are on a list */ 660 }; 661 662 struct hns_roce_ib_iboe { 663 spinlock_t lock; 664 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 665 struct notifier_block nb; 666 u8 phy_port[HNS_ROCE_MAX_PORTS]; 667 }; 668 669 enum { 670 HNS_ROCE_EQ_STAT_INVALID = 0, 671 HNS_ROCE_EQ_STAT_VALID = 2, 672 }; 673 674 struct hns_roce_ceqe { 675 __le32 comp; 676 __le32 rsv[15]; 677 }; 678 679 struct hns_roce_aeqe { 680 __le32 asyn; 681 union { 682 struct { 683 __le32 num; 684 u32 rsv0; 685 u32 rsv1; 686 } queue_event; 687 688 struct { 689 __le64 out_param; 690 __le16 token; 691 u8 status; 692 u8 rsv0; 693 } __packed cmd; 694 } event; 695 __le32 rsv[12]; 696 }; 697 698 struct hns_roce_eq { 699 struct hns_roce_dev *hr_dev; 700 void __iomem *db_reg; 701 702 int type_flag; /* Aeq:1 ceq:0 */ 703 int eqn; 704 u32 entries; 705 u32 log_entries; 706 int eqe_size; 707 int irq; 708 int log_page_size; 709 u32 cons_index; 710 struct hns_roce_buf_list *buf_list; 711 int over_ignore; 712 int coalesce; 713 int arm_st; 714 int hop_num; 715 struct hns_roce_mtr mtr; 716 u16 eq_max_cnt; 717 u32 eq_period; 718 int shift; 719 int event_type; 720 int sub_type; 721 }; 722 723 struct hns_roce_eq_table { 724 struct hns_roce_eq *eq; 725 void __iomem **eqc_base; /* only for hw v1 */ 726 }; 727 728 enum cong_type { 729 CONG_TYPE_DCQCN, 730 CONG_TYPE_LDCP, 731 CONG_TYPE_HC3, 732 CONG_TYPE_DIP, 733 }; 734 735 struct hns_roce_caps { 736 u64 fw_ver; 737 u8 num_ports; 738 int gid_table_len[HNS_ROCE_MAX_PORTS]; 739 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 740 int local_ca_ack_delay; 741 int num_uars; 742 u32 phy_num_uars; 743 u32 max_sq_sg; 744 u32 max_sq_inline; 745 u32 max_rq_sg; 746 u32 max_extend_sg; 747 u32 num_qps; 748 u32 reserved_qps; 749 int num_qpc_timer; 750 int num_cqc_timer; 751 int num_srqs; 752 u32 max_wqes; 753 u32 max_srq_wrs; 754 u32 max_srq_sges; 755 u32 max_sq_desc_sz; 756 u32 max_rq_desc_sz; 757 u32 max_srq_desc_sz; 758 int max_qp_init_rdma; 759 int max_qp_dest_rdma; 760 u32 num_cqs; 761 u32 max_cqes; 762 u32 min_cqes; 763 u32 min_wqes; 764 u32 reserved_cqs; 765 int reserved_srqs; 766 int num_aeq_vectors; 767 int num_comp_vectors; 768 int num_other_vectors; 769 u32 num_mtpts; 770 u32 num_mtt_segs; 771 u32 num_srqwqe_segs; 772 u32 num_idx_segs; 773 int reserved_mrws; 774 int reserved_uars; 775 int num_pds; 776 int reserved_pds; 777 u32 num_xrcds; 778 u32 reserved_xrcds; 779 u32 mtt_entry_sz; 780 u32 cqe_sz; 781 u32 page_size_cap; 782 u32 reserved_lkey; 783 int mtpt_entry_sz; 784 int qpc_sz; 785 int irrl_entry_sz; 786 int trrl_entry_sz; 787 int cqc_entry_sz; 788 int sccc_sz; 789 int qpc_timer_entry_sz; 790 int cqc_timer_entry_sz; 791 int srqc_entry_sz; 792 int idx_entry_sz; 793 u32 pbl_ba_pg_sz; 794 u32 pbl_buf_pg_sz; 795 u32 pbl_hop_num; 796 int aeqe_depth; 797 int ceqe_depth; 798 u32 aeqe_size; 799 u32 ceqe_size; 800 enum ib_mtu max_mtu; 801 u32 qpc_bt_num; 802 u32 qpc_timer_bt_num; 803 u32 srqc_bt_num; 804 u32 cqc_bt_num; 805 u32 cqc_timer_bt_num; 806 u32 mpt_bt_num; 807 u32 eqc_bt_num; 808 u32 smac_bt_num; 809 u32 sgid_bt_num; 810 u32 sccc_bt_num; 811 u32 gmv_bt_num; 812 u32 qpc_ba_pg_sz; 813 u32 qpc_buf_pg_sz; 814 u32 qpc_hop_num; 815 u32 srqc_ba_pg_sz; 816 u32 srqc_buf_pg_sz; 817 u32 srqc_hop_num; 818 u32 cqc_ba_pg_sz; 819 u32 cqc_buf_pg_sz; 820 u32 cqc_hop_num; 821 u32 mpt_ba_pg_sz; 822 u32 mpt_buf_pg_sz; 823 u32 mpt_hop_num; 824 u32 mtt_ba_pg_sz; 825 u32 mtt_buf_pg_sz; 826 u32 mtt_hop_num; 827 u32 wqe_sq_hop_num; 828 u32 wqe_sge_hop_num; 829 u32 wqe_rq_hop_num; 830 u32 sccc_ba_pg_sz; 831 u32 sccc_buf_pg_sz; 832 u32 sccc_hop_num; 833 u32 qpc_timer_ba_pg_sz; 834 u32 qpc_timer_buf_pg_sz; 835 u32 qpc_timer_hop_num; 836 u32 cqc_timer_ba_pg_sz; 837 u32 cqc_timer_buf_pg_sz; 838 u32 cqc_timer_hop_num; 839 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 840 u32 cqe_buf_pg_sz; 841 u32 cqe_hop_num; 842 u32 srqwqe_ba_pg_sz; 843 u32 srqwqe_buf_pg_sz; 844 u32 srqwqe_hop_num; 845 u32 idx_ba_pg_sz; 846 u32 idx_buf_pg_sz; 847 u32 idx_hop_num; 848 u32 eqe_ba_pg_sz; 849 u32 eqe_buf_pg_sz; 850 u32 eqe_hop_num; 851 u32 gmv_entry_num; 852 u32 gmv_entry_sz; 853 u32 gmv_ba_pg_sz; 854 u32 gmv_buf_pg_sz; 855 u32 gmv_hop_num; 856 u32 sl_num; 857 u32 tsq_buf_pg_sz; 858 u32 tpq_buf_pg_sz; 859 u32 chunk_sz; /* chunk size in non multihop mode */ 860 u64 flags; 861 u16 default_ceq_max_cnt; 862 u16 default_ceq_period; 863 u16 default_aeq_max_cnt; 864 u16 default_aeq_period; 865 u16 default_aeq_arm_st; 866 u16 default_ceq_arm_st; 867 enum cong_type cong_type; 868 }; 869 870 struct hns_roce_dfx_hw { 871 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 872 int *buffer); 873 }; 874 875 enum hns_roce_device_state { 876 HNS_ROCE_DEVICE_STATE_INITED, 877 HNS_ROCE_DEVICE_STATE_RST_DOWN, 878 HNS_ROCE_DEVICE_STATE_UNINIT, 879 }; 880 881 struct hns_roce_hw { 882 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 883 int (*cmq_init)(struct hns_roce_dev *hr_dev); 884 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 885 int (*hw_profile)(struct hns_roce_dev *hr_dev); 886 int (*hw_init)(struct hns_roce_dev *hr_dev); 887 void (*hw_exit)(struct hns_roce_dev *hr_dev); 888 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 889 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 890 u16 token, int event); 891 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev, 892 unsigned int timeout); 893 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 894 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index, 895 const union ib_gid *gid, const struct ib_gid_attr *attr); 896 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 897 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 898 enum ib_mtu mtu); 899 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 900 struct hns_roce_mr *mr, unsigned long mtpt_idx); 901 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 902 struct hns_roce_mr *mr, int flags, 903 void *mb_buf); 904 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 905 struct hns_roce_mr *mr); 906 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 907 void (*write_cqc)(struct hns_roce_dev *hr_dev, 908 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 909 dma_addr_t dma_handle); 910 int (*set_hem)(struct hns_roce_dev *hr_dev, 911 struct hns_roce_hem_table *table, int obj, int step_idx); 912 int (*clear_hem)(struct hns_roce_dev *hr_dev, 913 struct hns_roce_hem_table *table, int obj, 914 int step_idx); 915 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 916 int attr_mask, enum ib_qp_state cur_state, 917 enum ib_qp_state new_state); 918 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 919 struct hns_roce_qp *hr_qp); 920 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 921 struct ib_udata *udata); 922 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 923 int (*init_eq)(struct hns_roce_dev *hr_dev); 924 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 925 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 926 const struct ib_device_ops *hns_roce_dev_ops; 927 const struct ib_device_ops *hns_roce_dev_srq_ops; 928 }; 929 930 struct hns_roce_dev { 931 struct ib_device ib_dev; 932 struct platform_device *pdev; 933 struct pci_dev *pci_dev; 934 struct device *dev; 935 struct hns_roce_uar priv_uar; 936 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 937 spinlock_t sm_lock; 938 spinlock_t bt_cmd_lock; 939 bool active; 940 bool is_reset; 941 bool dis_db; 942 unsigned long reset_cnt; 943 struct hns_roce_ib_iboe iboe; 944 enum hns_roce_device_state state; 945 struct list_head qp_list; /* list of all qps on this dev */ 946 spinlock_t qp_list_lock; /* protect qp_list */ 947 struct list_head dip_list; /* list of all dest ips on this dev */ 948 spinlock_t dip_list_lock; /* protect dip_list */ 949 950 struct list_head pgdir_list; 951 struct mutex pgdir_mutex; 952 int irq[HNS_ROCE_MAX_IRQ_NUM]; 953 u8 __iomem *reg_base; 954 void __iomem *mem_base; 955 struct hns_roce_caps caps; 956 struct xarray qp_table_xa; 957 958 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 959 u64 sys_image_guid; 960 u32 vendor_id; 961 u32 vendor_part_id; 962 u32 hw_rev; 963 void __iomem *priv_addr; 964 965 struct hns_roce_cmdq cmd; 966 struct hns_roce_bitmap pd_bitmap; 967 struct hns_roce_bitmap xrcd_bitmap; 968 struct hns_roce_uar_table uar_table; 969 struct hns_roce_mr_table mr_table; 970 struct hns_roce_cq_table cq_table; 971 struct hns_roce_srq_table srq_table; 972 struct hns_roce_qp_table qp_table; 973 struct hns_roce_eq_table eq_table; 974 struct hns_roce_hem_table qpc_timer_table; 975 struct hns_roce_hem_table cqc_timer_table; 976 /* GMV is the memory area that the driver allocates for the hardware 977 * to store SGID, SMAC and VLAN information. 978 */ 979 struct hns_roce_hem_table gmv_table; 980 981 int cmd_mod; 982 int loop_idc; 983 u32 sdb_offset; 984 u32 odb_offset; 985 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 986 u32 tptr_size; /* only for hw v1 */ 987 const struct hns_roce_hw *hw; 988 void *priv; 989 struct workqueue_struct *irq_workq; 990 const struct hns_roce_dfx_hw *dfx; 991 u32 func_num; 992 u32 is_vf; 993 u32 cong_algo_tmpl_id; 994 }; 995 996 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 997 { 998 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 999 } 1000 1001 static inline struct hns_roce_ucontext 1002 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1003 { 1004 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1005 } 1006 1007 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1008 { 1009 return container_of(ibpd, struct hns_roce_pd, ibpd); 1010 } 1011 1012 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1013 { 1014 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1015 } 1016 1017 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1018 { 1019 return container_of(ibah, struct hns_roce_ah, ibah); 1020 } 1021 1022 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1023 { 1024 return container_of(ibmr, struct hns_roce_mr, ibmr); 1025 } 1026 1027 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1028 { 1029 return container_of(ibmw, struct hns_roce_mw, ibmw); 1030 } 1031 1032 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1033 { 1034 return container_of(ibqp, struct hns_roce_qp, ibqp); 1035 } 1036 1037 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1038 { 1039 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1040 } 1041 1042 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1043 { 1044 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1045 } 1046 1047 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1048 { 1049 writeq(*(u64 *)val, dest); 1050 } 1051 1052 static inline struct hns_roce_qp 1053 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1054 { 1055 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1056 } 1057 1058 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1059 unsigned int offset) 1060 { 1061 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1062 (offset & ((1 << buf->trunk_shift) - 1)); 1063 } 1064 1065 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1066 { 1067 unsigned int offset = idx << buf->page_shift; 1068 1069 return buf->trunk_list[offset >> buf->trunk_shift].map + 1070 (offset & ((1 << buf->trunk_shift) - 1)); 1071 } 1072 1073 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1074 1075 static inline u64 to_hr_hw_page_addr(u64 addr) 1076 { 1077 return addr >> HNS_HW_PAGE_SHIFT; 1078 } 1079 1080 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1081 { 1082 return page_shift - HNS_HW_PAGE_SHIFT; 1083 } 1084 1085 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1086 { 1087 if (count > 0) 1088 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1089 1090 return 0; 1091 } 1092 1093 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1094 { 1095 return hr_hw_page_align(count << buf_shift); 1096 } 1097 1098 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1099 { 1100 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1101 } 1102 1103 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1104 { 1105 if (!count) 1106 return 0; 1107 1108 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1109 } 1110 1111 #define DSCP_SHIFT 2 1112 1113 static inline u8 get_tclass(const struct ib_global_route *grh) 1114 { 1115 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1116 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1117 } 1118 1119 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1120 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1121 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1122 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1123 1124 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1125 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1126 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1127 u64 out_param); 1128 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1129 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1130 1131 /* hns roce hw need current block and next block addr from mtt */ 1132 #define MTT_MIN_COUNT 2 1133 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1134 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1135 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1136 struct hns_roce_buf_attr *buf_attr, 1137 unsigned int page_shift, struct ib_udata *udata, 1138 unsigned long user_addr); 1139 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1140 struct hns_roce_mtr *mtr); 1141 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1142 dma_addr_t *pages, unsigned int page_cnt); 1143 1144 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1145 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1146 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1147 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1148 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1149 int hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1150 1151 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1152 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1153 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1154 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1155 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1156 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1157 void hns_roce_cleanup_xrcd_table(struct hns_roce_dev *hr_dev); 1158 1159 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1160 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1161 int rr); 1162 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1163 u32 reserved_bot, u32 resetrved_top); 1164 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1165 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1166 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1167 int align, unsigned long *obj); 1168 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1169 unsigned long obj, int cnt, 1170 int rr); 1171 1172 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1173 struct ib_udata *udata); 1174 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1175 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1176 { 1177 return 0; 1178 } 1179 1180 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1181 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1182 1183 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1184 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1185 u64 virt_addr, int access_flags, 1186 struct ib_udata *udata); 1187 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1188 u64 length, u64 virt_addr, 1189 int mr_access_flags, struct ib_pd *pd, 1190 struct ib_udata *udata); 1191 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1192 u32 max_num_sg); 1193 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1194 unsigned int *sg_offset); 1195 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1196 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1197 struct hns_roce_cmd_mailbox *mailbox, 1198 unsigned long mpt_index); 1199 unsigned long key_to_hw_index(u32 key); 1200 1201 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1202 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1203 1204 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1205 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1206 u32 page_shift, u32 flags); 1207 1208 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1209 int buf_cnt, int start, struct hns_roce_buf *buf); 1210 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1211 int buf_cnt, int start, struct ib_umem *umem, 1212 unsigned int page_shift); 1213 1214 int hns_roce_create_srq(struct ib_srq *srq, 1215 struct ib_srq_init_attr *srq_init_attr, 1216 struct ib_udata *udata); 1217 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1218 enum ib_srq_attr_mask srq_attr_mask, 1219 struct ib_udata *udata); 1220 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1221 1222 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1223 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1224 1225 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1226 struct ib_qp_init_attr *init_attr, 1227 struct ib_udata *udata); 1228 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1229 int attr_mask, struct ib_udata *udata); 1230 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1231 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1232 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1233 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1234 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1235 struct ib_cq *ib_cq); 1236 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1237 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1238 struct hns_roce_cq *recv_cq); 1239 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1240 struct hns_roce_cq *recv_cq); 1241 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1242 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1243 struct ib_udata *udata); 1244 __be32 send_ieth(const struct ib_send_wr *wr); 1245 int to_hr_qp_type(int qp_type); 1246 1247 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1248 struct ib_udata *udata); 1249 1250 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1251 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1252 struct ib_udata *udata, unsigned long virt, 1253 struct hns_roce_db *db); 1254 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1255 struct hns_roce_db *db); 1256 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1257 int order); 1258 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1259 1260 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1261 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1262 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1263 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1264 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index); 1265 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1266 int hns_roce_init(struct hns_roce_dev *hr_dev); 1267 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1268 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, 1269 struct ib_cq *ib_cq); 1270 #endif /* _HNS_ROCE_DEVICE_H */ 1271