1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define DRV_NAME "hns_roce" 40 41 #define PCI_REVISION_ID_HIP08 0x21 42 #define PCI_REVISION_ID_HIP09 0x30 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 49 50 #define BA_BYTE_LEN 8 51 52 /* Hardware specification only for v1 engine */ 53 #define HNS_ROCE_MIN_CQE_NUM 0x40 54 #define HNS_ROCE_MIN_WQE_NUM 0x20 55 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 56 57 /* Hardware specification only for v1 engine */ 58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 60 61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 63 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 65 #define HNS_ROCE_MIN_CQE_CNT 16 66 67 #define HNS_ROCE_RESERVED_SGE 1 68 69 #define HNS_ROCE_MAX_IRQ_NUM 128 70 71 #define HNS_ROCE_SGE_IN_WQE 2 72 #define HNS_ROCE_SGE_SHIFT 4 73 74 #define EQ_ENABLE 1 75 #define EQ_DISABLE 0 76 77 #define HNS_ROCE_CEQ 0 78 #define HNS_ROCE_AEQ 1 79 80 #define HNS_ROCE_CEQE_SIZE 0x4 81 #define HNS_ROCE_AEQE_SIZE 0x10 82 83 #define HNS_ROCE_V3_EQE_SIZE 0x40 84 85 #define HNS_ROCE_V2_CQE_SIZE 32 86 #define HNS_ROCE_V3_CQE_SIZE 64 87 88 #define HNS_ROCE_V2_QPC_SZ 256 89 #define HNS_ROCE_V3_QPC_SZ 512 90 91 #define HNS_ROCE_MAX_PORTS 6 92 #define HNS_ROCE_GID_SIZE 16 93 #define HNS_ROCE_SGE_SIZE 16 94 #define HNS_ROCE_DWQE_SIZE 65536 95 96 #define HNS_ROCE_HOP_NUM_0 0xff 97 98 #define MR_TYPE_MR 0x00 99 #define MR_TYPE_FRMR 0x01 100 #define MR_TYPE_DMA 0x03 101 102 #define HNS_ROCE_FRMR_MAX_PA 512 103 104 #define PKEY_ID 0xffff 105 #define GUID_LEN 8 106 #define NODE_DESC_SIZE 64 107 #define DB_REG_OFFSET 0x1000 108 109 /* Configure to HW for PAGE_SIZE larger than 4KB */ 110 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 111 112 #define PAGES_SHIFT_8 8 113 #define PAGES_SHIFT_16 16 114 #define PAGES_SHIFT_24 24 115 #define PAGES_SHIFT_32 32 116 117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 118 #define SRQ_DB_REG 0x230 119 120 #define HNS_ROCE_QP_BANK_NUM 8 121 #define HNS_ROCE_CQ_BANK_NUM 4 122 123 #define CQ_BANKID_SHIFT 2 124 125 /* The chip implementation of the consumer index is calculated 126 * according to twice the actual EQ depth 127 */ 128 #define EQ_DEPTH_COEFF 2 129 130 enum { 131 SERV_TYPE_RC, 132 SERV_TYPE_UC, 133 SERV_TYPE_RD, 134 SERV_TYPE_UD, 135 SERV_TYPE_XRC = 5, 136 }; 137 138 enum hns_roce_qp_state { 139 HNS_ROCE_QP_STATE_RST, 140 HNS_ROCE_QP_STATE_INIT, 141 HNS_ROCE_QP_STATE_RTR, 142 HNS_ROCE_QP_STATE_RTS, 143 HNS_ROCE_QP_STATE_SQD, 144 HNS_ROCE_QP_STATE_ERR, 145 HNS_ROCE_QP_NUM_STATE, 146 }; 147 148 enum hns_roce_event { 149 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 150 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 151 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 152 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 153 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 154 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 155 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 156 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 157 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 158 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 159 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 160 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 161 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 162 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 163 /* 0x10 and 0x11 is unused in currently application case */ 164 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 165 HNS_ROCE_EVENT_TYPE_MB = 0x13, 166 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 167 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 168 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 169 }; 170 171 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 172 173 enum { 174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 176 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 177 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 178 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 179 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 180 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 181 HNS_ROCE_CAP_FLAG_MW = BIT(7), 182 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 183 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 184 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 185 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 186 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 187 }; 188 189 #define HNS_ROCE_DB_TYPE_COUNT 2 190 #define HNS_ROCE_DB_UNIT_SIZE 4 191 192 enum { 193 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 194 }; 195 196 enum hns_roce_reset_stage { 197 HNS_ROCE_STATE_NON_RST, 198 HNS_ROCE_STATE_RST_BEF_DOWN, 199 HNS_ROCE_STATE_RST_DOWN, 200 HNS_ROCE_STATE_RST_UNINIT, 201 HNS_ROCE_STATE_RST_INIT, 202 HNS_ROCE_STATE_RST_INITED, 203 }; 204 205 enum hns_roce_instance_state { 206 HNS_ROCE_STATE_NON_INIT, 207 HNS_ROCE_STATE_INIT, 208 HNS_ROCE_STATE_INITED, 209 HNS_ROCE_STATE_UNINIT, 210 }; 211 212 enum { 213 HNS_ROCE_RST_DIRECT_RETURN = 0, 214 }; 215 216 #define HNS_ROCE_CMD_SUCCESS 1 217 218 /* The minimum page size is 4K for hardware */ 219 #define HNS_HW_PAGE_SHIFT 12 220 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 221 222 struct hns_roce_uar { 223 u64 pfn; 224 unsigned long index; 225 unsigned long logic_idx; 226 }; 227 228 struct hns_roce_ucontext { 229 struct ib_ucontext ibucontext; 230 struct hns_roce_uar uar; 231 struct list_head page_list; 232 struct mutex page_mutex; 233 }; 234 235 struct hns_roce_pd { 236 struct ib_pd ibpd; 237 unsigned long pdn; 238 }; 239 240 struct hns_roce_xrcd { 241 struct ib_xrcd ibxrcd; 242 u32 xrcdn; 243 }; 244 245 struct hns_roce_bitmap { 246 /* Bitmap Traversal last a bit which is 1 */ 247 unsigned long last; 248 unsigned long top; 249 unsigned long max; 250 unsigned long reserved_top; 251 unsigned long mask; 252 spinlock_t lock; 253 unsigned long *table; 254 }; 255 256 struct hns_roce_ida { 257 struct ida ida; 258 u32 min; /* Lowest ID to allocate. */ 259 u32 max; /* Highest ID to allocate. */ 260 }; 261 262 /* For Hardware Entry Memory */ 263 struct hns_roce_hem_table { 264 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 265 u32 type; 266 /* HEM array elment num */ 267 unsigned long num_hem; 268 /* Single obj size */ 269 unsigned long obj_size; 270 unsigned long table_chunk_size; 271 int lowmem; 272 struct mutex mutex; 273 struct hns_roce_hem **hem; 274 u64 **bt_l1; 275 dma_addr_t *bt_l1_dma_addr; 276 u64 **bt_l0; 277 dma_addr_t *bt_l0_dma_addr; 278 }; 279 280 struct hns_roce_buf_region { 281 u32 offset; /* page offset */ 282 u32 count; /* page count */ 283 int hopnum; /* addressing hop num */ 284 }; 285 286 #define HNS_ROCE_MAX_BT_REGION 3 287 #define HNS_ROCE_MAX_BT_LEVEL 3 288 struct hns_roce_hem_list { 289 struct list_head root_bt; 290 /* link all bt dma mem by hop config */ 291 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 292 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 293 dma_addr_t root_ba; /* pointer to the root ba table */ 294 }; 295 296 struct hns_roce_buf_attr { 297 struct { 298 size_t size; /* region size */ 299 int hopnum; /* multi-hop addressing hop num */ 300 } region[HNS_ROCE_MAX_BT_REGION]; 301 unsigned int region_count; /* valid region count */ 302 unsigned int page_shift; /* buffer page shift */ 303 unsigned int user_access; /* umem access flag */ 304 bool mtt_only; /* only alloc buffer-required MTT memory */ 305 }; 306 307 struct hns_roce_hem_cfg { 308 dma_addr_t root_ba; /* root BA table's address */ 309 bool is_direct; /* addressing without BA table */ 310 unsigned int ba_pg_shift; /* BA table page shift */ 311 unsigned int buf_pg_shift; /* buffer page shift */ 312 unsigned int buf_pg_count; /* buffer page count */ 313 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 314 unsigned int region_count; 315 }; 316 317 /* memory translate region */ 318 struct hns_roce_mtr { 319 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 320 struct ib_umem *umem; /* user space buffer */ 321 struct hns_roce_buf *kmem; /* kernel space buffer */ 322 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 323 }; 324 325 struct hns_roce_mw { 326 struct ib_mw ibmw; 327 u32 pdn; 328 u32 rkey; 329 int enabled; /* MW's active status */ 330 u32 pbl_hop_num; 331 u32 pbl_ba_pg_sz; 332 u32 pbl_buf_pg_sz; 333 }; 334 335 /* Only support 4K page size for mr register */ 336 #define MR_SIZE_4K 0 337 338 struct hns_roce_mr { 339 struct ib_mr ibmr; 340 u64 iova; /* MR's virtual original addr */ 341 u64 size; /* Address range of MR */ 342 u32 key; /* Key of MR */ 343 u32 pd; /* PD num of MR */ 344 u32 access; /* Access permission of MR */ 345 int enabled; /* MR's active status */ 346 int type; /* MR's register type */ 347 u32 pbl_hop_num; /* multi-hop number */ 348 struct hns_roce_mtr pbl_mtr; 349 u32 npages; 350 dma_addr_t *page_list; 351 }; 352 353 struct hns_roce_mr_table { 354 struct hns_roce_ida mtpt_ida; 355 struct hns_roce_hem_table mtpt_table; 356 }; 357 358 struct hns_roce_wq { 359 u64 *wrid; /* Work request ID */ 360 spinlock_t lock; 361 u32 wqe_cnt; /* WQE num */ 362 u32 max_gs; 363 u32 rsv_sge; 364 int offset; 365 int wqe_shift; /* WQE size */ 366 u32 head; 367 u32 tail; 368 void __iomem *db_reg; 369 }; 370 371 struct hns_roce_sge { 372 unsigned int sge_cnt; /* SGE num */ 373 int offset; 374 int sge_shift; /* SGE size */ 375 }; 376 377 struct hns_roce_buf_list { 378 void *buf; 379 dma_addr_t map; 380 }; 381 382 /* 383 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 384 * dma address range. 385 * 386 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 387 * 388 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 389 * the allocated size is smaller than the required size. 390 */ 391 enum { 392 HNS_ROCE_BUF_DIRECT = BIT(0), 393 HNS_ROCE_BUF_NOSLEEP = BIT(1), 394 HNS_ROCE_BUF_NOFAIL = BIT(2), 395 }; 396 397 struct hns_roce_buf { 398 struct hns_roce_buf_list *trunk_list; 399 u32 ntrunks; 400 u32 npages; 401 unsigned int trunk_shift; 402 unsigned int page_shift; 403 }; 404 405 struct hns_roce_db_pgdir { 406 struct list_head list; 407 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 408 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 409 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 410 u32 *page; 411 dma_addr_t db_dma; 412 }; 413 414 struct hns_roce_user_db_page { 415 struct list_head list; 416 struct ib_umem *umem; 417 unsigned long user_virt; 418 refcount_t refcount; 419 }; 420 421 struct hns_roce_db { 422 u32 *db_record; 423 union { 424 struct hns_roce_db_pgdir *pgdir; 425 struct hns_roce_user_db_page *user_page; 426 } u; 427 dma_addr_t dma; 428 void *virt_addr; 429 unsigned long index; 430 unsigned long order; 431 }; 432 433 struct hns_roce_cq { 434 struct ib_cq ib_cq; 435 struct hns_roce_mtr mtr; 436 struct hns_roce_db db; 437 u32 flags; 438 spinlock_t lock; 439 u32 cq_depth; 440 u32 cons_index; 441 u32 *set_ci_db; 442 void __iomem *db_reg; 443 u16 *tptr_addr; 444 int arm_sn; 445 int cqe_size; 446 unsigned long cqn; 447 u32 vector; 448 refcount_t refcount; 449 struct completion free; 450 struct list_head sq_list; /* all qps on this send cq */ 451 struct list_head rq_list; /* all qps on this recv cq */ 452 int is_armed; /* cq is armed */ 453 struct list_head node; /* all armed cqs are on a list */ 454 }; 455 456 struct hns_roce_idx_que { 457 struct hns_roce_mtr mtr; 458 int entry_shift; 459 unsigned long *bitmap; 460 u32 head; 461 u32 tail; 462 }; 463 464 struct hns_roce_srq { 465 struct ib_srq ibsrq; 466 unsigned long srqn; 467 u32 wqe_cnt; 468 int max_gs; 469 u32 rsv_sge; 470 int wqe_shift; 471 u32 cqn; 472 u32 xrcdn; 473 void __iomem *db_reg; 474 475 refcount_t refcount; 476 struct completion free; 477 478 struct hns_roce_mtr buf_mtr; 479 480 u64 *wrid; 481 struct hns_roce_idx_que idx_que; 482 spinlock_t lock; 483 struct mutex mutex; 484 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 485 }; 486 487 struct hns_roce_uar_table { 488 struct hns_roce_bitmap bitmap; 489 }; 490 491 struct hns_roce_bank { 492 struct ida ida; 493 u32 inuse; /* Number of IDs allocated */ 494 u32 min; /* Lowest ID to allocate. */ 495 u32 max; /* Highest ID to allocate. */ 496 u32 next; /* Next ID to allocate. */ 497 }; 498 499 struct hns_roce_qp_table { 500 struct hns_roce_hem_table qp_table; 501 struct hns_roce_hem_table irrl_table; 502 struct hns_roce_hem_table trrl_table; 503 struct hns_roce_hem_table sccc_table; 504 struct mutex scc_mutex; 505 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 506 struct mutex bank_mutex; 507 }; 508 509 struct hns_roce_cq_table { 510 struct xarray array; 511 struct hns_roce_hem_table table; 512 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 513 struct mutex bank_mutex; 514 }; 515 516 struct hns_roce_srq_table { 517 struct hns_roce_bitmap bitmap; 518 struct xarray xa; 519 struct hns_roce_hem_table table; 520 }; 521 522 struct hns_roce_raq_table { 523 struct hns_roce_buf_list *e_raq_buf; 524 }; 525 526 struct hns_roce_av { 527 u8 port; 528 u8 gid_index; 529 u8 stat_rate; 530 u8 hop_limit; 531 u32 flowlabel; 532 u16 udp_sport; 533 u8 sl; 534 u8 tclass; 535 u8 dgid[HNS_ROCE_GID_SIZE]; 536 u8 mac[ETH_ALEN]; 537 u16 vlan_id; 538 u8 vlan_en; 539 }; 540 541 struct hns_roce_ah { 542 struct ib_ah ibah; 543 struct hns_roce_av av; 544 }; 545 546 struct hns_roce_cmd_context { 547 struct completion done; 548 int result; 549 int next; 550 u64 out_param; 551 u16 token; 552 u16 busy; 553 }; 554 555 struct hns_roce_cmdq { 556 struct dma_pool *pool; 557 struct semaphore poll_sem; 558 /* 559 * Event mode: cmd register mutex protection, 560 * ensure to not exceed max_cmds and user use limit region 561 */ 562 struct semaphore event_sem; 563 int max_cmds; 564 spinlock_t context_lock; 565 int free_head; 566 struct hns_roce_cmd_context *context; 567 /* 568 * Process whether use event mode, init default non-zero 569 * After the event queue of cmd event ready, 570 * can switch into event mode 571 * close device, switch into poll mode(non event mode) 572 */ 573 u8 use_events; 574 }; 575 576 struct hns_roce_cmd_mailbox { 577 void *buf; 578 dma_addr_t dma; 579 }; 580 581 struct hns_roce_dev; 582 583 struct hns_roce_rinl_sge { 584 void *addr; 585 u32 len; 586 }; 587 588 struct hns_roce_rinl_wqe { 589 struct hns_roce_rinl_sge *sg_list; 590 u32 sge_cnt; 591 }; 592 593 struct hns_roce_rinl_buf { 594 struct hns_roce_rinl_wqe *wqe_list; 595 u32 wqe_cnt; 596 }; 597 598 enum { 599 HNS_ROCE_FLUSH_FLAG = 0, 600 }; 601 602 struct hns_roce_work { 603 struct hns_roce_dev *hr_dev; 604 struct work_struct work; 605 int event_type; 606 int sub_type; 607 u32 queue_num; 608 }; 609 610 enum { 611 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), 612 }; 613 614 struct hns_roce_qp { 615 struct ib_qp ibqp; 616 struct hns_roce_wq rq; 617 struct hns_roce_db rdb; 618 struct hns_roce_db sdb; 619 unsigned long en_flags; 620 u32 doorbell_qpn; 621 enum ib_sig_type sq_signal_bits; 622 struct hns_roce_wq sq; 623 624 struct hns_roce_mtr mtr; 625 626 u32 buff_size; 627 struct mutex mutex; 628 u8 port; 629 u8 phy_port; 630 u8 sl; 631 u8 resp_depth; 632 u8 state; 633 u32 access_flags; 634 u32 atomic_rd_en; 635 u32 pkey_index; 636 u32 qkey; 637 void (*event)(struct hns_roce_qp *qp, 638 enum hns_roce_event event_type); 639 unsigned long qpn; 640 641 u32 xrcdn; 642 643 refcount_t refcount; 644 struct completion free; 645 646 struct hns_roce_sge sge; 647 u32 next_sge; 648 enum ib_mtu path_mtu; 649 u32 max_inline_data; 650 651 /* 0: flush needed, 1: unneeded */ 652 unsigned long flush_flag; 653 struct hns_roce_work flush_work; 654 struct hns_roce_rinl_buf rq_inl_buf; 655 struct list_head node; /* all qps are on a list */ 656 struct list_head rq_node; /* all recv qps are on a list */ 657 struct list_head sq_node; /* all send qps are on a list */ 658 }; 659 660 struct hns_roce_ib_iboe { 661 spinlock_t lock; 662 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 663 struct notifier_block nb; 664 u8 phy_port[HNS_ROCE_MAX_PORTS]; 665 }; 666 667 enum { 668 HNS_ROCE_EQ_STAT_INVALID = 0, 669 HNS_ROCE_EQ_STAT_VALID = 2, 670 }; 671 672 struct hns_roce_ceqe { 673 __le32 comp; 674 __le32 rsv[15]; 675 }; 676 677 struct hns_roce_aeqe { 678 __le32 asyn; 679 union { 680 struct { 681 __le32 num; 682 u32 rsv0; 683 u32 rsv1; 684 } queue_event; 685 686 struct { 687 __le64 out_param; 688 __le16 token; 689 u8 status; 690 u8 rsv0; 691 } __packed cmd; 692 } event; 693 __le32 rsv[12]; 694 }; 695 696 struct hns_roce_eq { 697 struct hns_roce_dev *hr_dev; 698 void __iomem *db_reg; 699 700 int type_flag; /* Aeq:1 ceq:0 */ 701 int eqn; 702 u32 entries; 703 u32 log_entries; 704 int eqe_size; 705 int irq; 706 int log_page_size; 707 u32 cons_index; 708 struct hns_roce_buf_list *buf_list; 709 int over_ignore; 710 int coalesce; 711 int arm_st; 712 int hop_num; 713 struct hns_roce_mtr mtr; 714 u16 eq_max_cnt; 715 u32 eq_period; 716 int shift; 717 int event_type; 718 int sub_type; 719 }; 720 721 struct hns_roce_eq_table { 722 struct hns_roce_eq *eq; 723 void __iomem **eqc_base; /* only for hw v1 */ 724 }; 725 726 enum cong_type { 727 CONG_TYPE_DCQCN, 728 CONG_TYPE_LDCP, 729 CONG_TYPE_HC3, 730 CONG_TYPE_DIP, 731 }; 732 733 struct hns_roce_caps { 734 u64 fw_ver; 735 u8 num_ports; 736 int gid_table_len[HNS_ROCE_MAX_PORTS]; 737 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 738 int local_ca_ack_delay; 739 int num_uars; 740 u32 phy_num_uars; 741 u32 max_sq_sg; 742 u32 max_sq_inline; 743 u32 max_rq_sg; 744 u32 max_extend_sg; 745 u32 num_qps; 746 u32 num_pi_qps; 747 u32 reserved_qps; 748 int num_qpc_timer; 749 int num_cqc_timer; 750 int num_srqs; 751 u32 max_wqes; 752 u32 max_srq_wrs; 753 u32 max_srq_sges; 754 u32 max_sq_desc_sz; 755 u32 max_rq_desc_sz; 756 u32 max_srq_desc_sz; 757 int max_qp_init_rdma; 758 int max_qp_dest_rdma; 759 u32 num_cqs; 760 u32 max_cqes; 761 u32 min_cqes; 762 u32 min_wqes; 763 u32 reserved_cqs; 764 int reserved_srqs; 765 int num_aeq_vectors; 766 int num_comp_vectors; 767 int num_other_vectors; 768 u32 num_mtpts; 769 u32 num_mtt_segs; 770 u32 num_srqwqe_segs; 771 u32 num_idx_segs; 772 int reserved_mrws; 773 int reserved_uars; 774 int num_pds; 775 int reserved_pds; 776 u32 num_xrcds; 777 u32 reserved_xrcds; 778 u32 mtt_entry_sz; 779 u32 cqe_sz; 780 u32 page_size_cap; 781 u32 reserved_lkey; 782 int mtpt_entry_sz; 783 int qpc_sz; 784 int irrl_entry_sz; 785 int trrl_entry_sz; 786 int cqc_entry_sz; 787 int sccc_sz; 788 int qpc_timer_entry_sz; 789 int cqc_timer_entry_sz; 790 int srqc_entry_sz; 791 int idx_entry_sz; 792 u32 pbl_ba_pg_sz; 793 u32 pbl_buf_pg_sz; 794 u32 pbl_hop_num; 795 int aeqe_depth; 796 int ceqe_depth; 797 u32 aeqe_size; 798 u32 ceqe_size; 799 enum ib_mtu max_mtu; 800 u32 qpc_bt_num; 801 u32 qpc_timer_bt_num; 802 u32 srqc_bt_num; 803 u32 cqc_bt_num; 804 u32 cqc_timer_bt_num; 805 u32 mpt_bt_num; 806 u32 eqc_bt_num; 807 u32 smac_bt_num; 808 u32 sgid_bt_num; 809 u32 sccc_bt_num; 810 u32 gmv_bt_num; 811 u32 qpc_ba_pg_sz; 812 u32 qpc_buf_pg_sz; 813 u32 qpc_hop_num; 814 u32 srqc_ba_pg_sz; 815 u32 srqc_buf_pg_sz; 816 u32 srqc_hop_num; 817 u32 cqc_ba_pg_sz; 818 u32 cqc_buf_pg_sz; 819 u32 cqc_hop_num; 820 u32 mpt_ba_pg_sz; 821 u32 mpt_buf_pg_sz; 822 u32 mpt_hop_num; 823 u32 mtt_ba_pg_sz; 824 u32 mtt_buf_pg_sz; 825 u32 mtt_hop_num; 826 u32 wqe_sq_hop_num; 827 u32 wqe_sge_hop_num; 828 u32 wqe_rq_hop_num; 829 u32 sccc_ba_pg_sz; 830 u32 sccc_buf_pg_sz; 831 u32 sccc_hop_num; 832 u32 qpc_timer_ba_pg_sz; 833 u32 qpc_timer_buf_pg_sz; 834 u32 qpc_timer_hop_num; 835 u32 cqc_timer_ba_pg_sz; 836 u32 cqc_timer_buf_pg_sz; 837 u32 cqc_timer_hop_num; 838 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 839 u32 cqe_buf_pg_sz; 840 u32 cqe_hop_num; 841 u32 srqwqe_ba_pg_sz; 842 u32 srqwqe_buf_pg_sz; 843 u32 srqwqe_hop_num; 844 u32 idx_ba_pg_sz; 845 u32 idx_buf_pg_sz; 846 u32 idx_hop_num; 847 u32 eqe_ba_pg_sz; 848 u32 eqe_buf_pg_sz; 849 u32 eqe_hop_num; 850 u32 gmv_entry_num; 851 u32 gmv_entry_sz; 852 u32 gmv_ba_pg_sz; 853 u32 gmv_buf_pg_sz; 854 u32 gmv_hop_num; 855 u32 sl_num; 856 u32 llm_buf_pg_sz; 857 u32 chunk_sz; /* chunk size in non multihop mode */ 858 u64 flags; 859 u16 default_ceq_max_cnt; 860 u16 default_ceq_period; 861 u16 default_aeq_max_cnt; 862 u16 default_aeq_period; 863 u16 default_aeq_arm_st; 864 u16 default_ceq_arm_st; 865 enum cong_type cong_type; 866 }; 867 868 struct hns_roce_dfx_hw { 869 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 870 int *buffer); 871 }; 872 873 enum hns_roce_device_state { 874 HNS_ROCE_DEVICE_STATE_INITED, 875 HNS_ROCE_DEVICE_STATE_RST_DOWN, 876 HNS_ROCE_DEVICE_STATE_UNINIT, 877 }; 878 879 struct hns_roce_hw { 880 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 881 int (*cmq_init)(struct hns_roce_dev *hr_dev); 882 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 883 int (*hw_profile)(struct hns_roce_dev *hr_dev); 884 int (*hw_init)(struct hns_roce_dev *hr_dev); 885 void (*hw_exit)(struct hns_roce_dev *hr_dev); 886 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 887 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 888 u16 token, int event); 889 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev, 890 unsigned int timeout); 891 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 892 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index, 893 const union ib_gid *gid, const struct ib_gid_attr *attr); 894 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 895 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 896 enum ib_mtu mtu); 897 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 898 struct hns_roce_mr *mr, unsigned long mtpt_idx); 899 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 900 struct hns_roce_mr *mr, int flags, 901 void *mb_buf); 902 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 903 struct hns_roce_mr *mr); 904 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 905 void (*write_cqc)(struct hns_roce_dev *hr_dev, 906 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 907 dma_addr_t dma_handle); 908 int (*set_hem)(struct hns_roce_dev *hr_dev, 909 struct hns_roce_hem_table *table, int obj, int step_idx); 910 int (*clear_hem)(struct hns_roce_dev *hr_dev, 911 struct hns_roce_hem_table *table, int obj, 912 int step_idx); 913 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 914 int attr_mask, enum ib_qp_state cur_state, 915 enum ib_qp_state new_state); 916 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 917 struct hns_roce_qp *hr_qp); 918 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 919 struct ib_udata *udata); 920 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 921 int (*init_eq)(struct hns_roce_dev *hr_dev); 922 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 923 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 924 const struct ib_device_ops *hns_roce_dev_ops; 925 const struct ib_device_ops *hns_roce_dev_srq_ops; 926 }; 927 928 struct hns_roce_dev { 929 struct ib_device ib_dev; 930 struct platform_device *pdev; 931 struct pci_dev *pci_dev; 932 struct device *dev; 933 struct hns_roce_uar priv_uar; 934 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 935 spinlock_t sm_lock; 936 spinlock_t bt_cmd_lock; 937 bool active; 938 bool is_reset; 939 bool dis_db; 940 unsigned long reset_cnt; 941 struct hns_roce_ib_iboe iboe; 942 enum hns_roce_device_state state; 943 struct list_head qp_list; /* list of all qps on this dev */ 944 spinlock_t qp_list_lock; /* protect qp_list */ 945 struct list_head dip_list; /* list of all dest ips on this dev */ 946 spinlock_t dip_list_lock; /* protect dip_list */ 947 948 struct list_head pgdir_list; 949 struct mutex pgdir_mutex; 950 int irq[HNS_ROCE_MAX_IRQ_NUM]; 951 u8 __iomem *reg_base; 952 void __iomem *mem_base; 953 struct hns_roce_caps caps; 954 struct xarray qp_table_xa; 955 956 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 957 u64 sys_image_guid; 958 u32 vendor_id; 959 u32 vendor_part_id; 960 u32 hw_rev; 961 void __iomem *priv_addr; 962 963 struct hns_roce_cmdq cmd; 964 struct hns_roce_ida pd_ida; 965 struct hns_roce_ida xrcd_ida; 966 struct hns_roce_uar_table uar_table; 967 struct hns_roce_mr_table mr_table; 968 struct hns_roce_cq_table cq_table; 969 struct hns_roce_srq_table srq_table; 970 struct hns_roce_qp_table qp_table; 971 struct hns_roce_eq_table eq_table; 972 struct hns_roce_hem_table qpc_timer_table; 973 struct hns_roce_hem_table cqc_timer_table; 974 /* GMV is the memory area that the driver allocates for the hardware 975 * to store SGID, SMAC and VLAN information. 976 */ 977 struct hns_roce_hem_table gmv_table; 978 979 int cmd_mod; 980 int loop_idc; 981 u32 sdb_offset; 982 u32 odb_offset; 983 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 984 u32 tptr_size; /* only for hw v1 */ 985 const struct hns_roce_hw *hw; 986 void *priv; 987 struct workqueue_struct *irq_workq; 988 const struct hns_roce_dfx_hw *dfx; 989 u32 func_num; 990 u32 is_vf; 991 u32 cong_algo_tmpl_id; 992 }; 993 994 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 995 { 996 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 997 } 998 999 static inline struct hns_roce_ucontext 1000 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1001 { 1002 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1003 } 1004 1005 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1006 { 1007 return container_of(ibpd, struct hns_roce_pd, ibpd); 1008 } 1009 1010 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1011 { 1012 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1013 } 1014 1015 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1016 { 1017 return container_of(ibah, struct hns_roce_ah, ibah); 1018 } 1019 1020 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1021 { 1022 return container_of(ibmr, struct hns_roce_mr, ibmr); 1023 } 1024 1025 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1026 { 1027 return container_of(ibmw, struct hns_roce_mw, ibmw); 1028 } 1029 1030 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1031 { 1032 return container_of(ibqp, struct hns_roce_qp, ibqp); 1033 } 1034 1035 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1036 { 1037 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1038 } 1039 1040 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1041 { 1042 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1043 } 1044 1045 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1046 { 1047 writeq(*(u64 *)val, dest); 1048 } 1049 1050 static inline struct hns_roce_qp 1051 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1052 { 1053 return xa_load(&hr_dev->qp_table_xa, qpn); 1054 } 1055 1056 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1057 unsigned int offset) 1058 { 1059 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1060 (offset & ((1 << buf->trunk_shift) - 1)); 1061 } 1062 1063 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1064 unsigned int offset) 1065 { 1066 return buf->trunk_list[offset >> buf->trunk_shift].map + 1067 (offset & ((1 << buf->trunk_shift) - 1)); 1068 } 1069 1070 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1071 { 1072 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1073 } 1074 1075 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1076 1077 static inline u64 to_hr_hw_page_addr(u64 addr) 1078 { 1079 return addr >> HNS_HW_PAGE_SHIFT; 1080 } 1081 1082 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1083 { 1084 return page_shift - HNS_HW_PAGE_SHIFT; 1085 } 1086 1087 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1088 { 1089 if (count > 0) 1090 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1091 1092 return 0; 1093 } 1094 1095 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1096 { 1097 return hr_hw_page_align(count << buf_shift); 1098 } 1099 1100 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1101 { 1102 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1103 } 1104 1105 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1106 { 1107 if (!count) 1108 return 0; 1109 1110 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1111 } 1112 1113 #define DSCP_SHIFT 2 1114 1115 static inline u8 get_tclass(const struct ib_global_route *grh) 1116 { 1117 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1118 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1119 } 1120 1121 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1122 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1123 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1124 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1125 1126 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1127 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1128 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1129 u64 out_param); 1130 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1131 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1132 1133 /* hns roce hw need current block and next block addr from mtt */ 1134 #define MTT_MIN_COUNT 2 1135 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1136 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1137 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1138 struct hns_roce_buf_attr *buf_attr, 1139 unsigned int page_shift, struct ib_udata *udata, 1140 unsigned long user_addr); 1141 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1142 struct hns_roce_mtr *mtr); 1143 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1144 dma_addr_t *pages, unsigned int page_cnt); 1145 1146 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1147 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1148 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1149 void hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1150 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1151 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1152 1153 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1154 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1155 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1156 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1157 1158 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1159 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj); 1160 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1161 u32 reserved_bot, u32 resetrved_top); 1162 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1163 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1164 1165 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1166 struct ib_udata *udata); 1167 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1168 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1169 { 1170 return 0; 1171 } 1172 1173 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1174 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1175 1176 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1177 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1178 u64 virt_addr, int access_flags, 1179 struct ib_udata *udata); 1180 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1181 u64 length, u64 virt_addr, 1182 int mr_access_flags, struct ib_pd *pd, 1183 struct ib_udata *udata); 1184 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1185 u32 max_num_sg); 1186 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1187 unsigned int *sg_offset); 1188 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1189 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, 1190 struct hns_roce_cmd_mailbox *mailbox, 1191 unsigned long mpt_index); 1192 unsigned long key_to_hw_index(u32 key); 1193 1194 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1195 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1196 1197 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1198 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1199 u32 page_shift, u32 flags); 1200 1201 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1202 int buf_cnt, struct hns_roce_buf *buf, 1203 unsigned int page_shift); 1204 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1205 int buf_cnt, struct ib_umem *umem, 1206 unsigned int page_shift); 1207 1208 int hns_roce_create_srq(struct ib_srq *srq, 1209 struct ib_srq_init_attr *srq_init_attr, 1210 struct ib_udata *udata); 1211 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1212 enum ib_srq_attr_mask srq_attr_mask, 1213 struct ib_udata *udata); 1214 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1215 1216 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1217 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1218 1219 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1220 struct ib_qp_init_attr *init_attr, 1221 struct ib_udata *udata); 1222 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1223 int attr_mask, struct ib_udata *udata); 1224 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1225 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1226 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1227 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1228 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1229 struct ib_cq *ib_cq); 1230 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1231 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1232 struct hns_roce_cq *recv_cq); 1233 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1234 struct hns_roce_cq *recv_cq); 1235 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1236 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1237 struct ib_udata *udata); 1238 __be32 send_ieth(const struct ib_send_wr *wr); 1239 int to_hr_qp_type(int qp_type); 1240 1241 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1242 struct ib_udata *udata); 1243 1244 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1245 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1246 struct hns_roce_db *db); 1247 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1248 struct hns_roce_db *db); 1249 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1250 int order); 1251 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1252 1253 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1254 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1255 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1256 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1257 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1258 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index); 1259 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1260 int hns_roce_init(struct hns_roce_dev *hr_dev); 1261 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1262 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, 1263 struct ib_cq *ib_cq); 1264 #endif /* _HNS_ROCE_DEVICE_H */ 1265