1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 38 #define DRV_NAME "hns_roce" 39 40 /* hip08 is a pci device, it includes two version according pci version id */ 41 #define PCI_REVISION_ID_HIP08_A 0x20 42 #define PCI_REVISION_ID_HIP08_B 0x21 43 44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') 45 46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 47 48 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b)) 49 50 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 51 52 #define HNS_ROCE_BA_SIZE (32 * 4096) 53 54 #define BA_BYTE_LEN 8 55 56 #define BITS_PER_BYTE 8 57 58 /* Hardware specification only for v1 engine */ 59 #define HNS_ROCE_MIN_CQE_NUM 0x40 60 #define HNS_ROCE_MIN_WQE_NUM 0x20 61 62 /* Hardware specification only for v1 engine */ 63 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 64 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 65 #define HNS_ROCE_MAX_SGE_NUM 2 66 67 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 68 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ 69 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) 70 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 71 #define HNS_ROCE_MIN_CQE_CNT 16 72 73 #define HNS_ROCE_MAX_IRQ_NUM 128 74 75 #define HNS_ROCE_SGE_IN_WQE 2 76 #define HNS_ROCE_SGE_SHIFT 4 77 78 #define EQ_ENABLE 1 79 #define EQ_DISABLE 0 80 81 #define HNS_ROCE_CEQ 0 82 #define HNS_ROCE_AEQ 1 83 84 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 85 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 86 87 #define HNS_ROCE_SL_SHIFT 28 88 #define HNS_ROCE_TCLASS_SHIFT 20 89 #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff 90 91 #define HNS_ROCE_MAX_PORTS 6 92 #define HNS_ROCE_MAX_GID_NUM 16 93 #define HNS_ROCE_GID_SIZE 16 94 #define HNS_ROCE_SGE_SIZE 16 95 96 #define HNS_ROCE_HOP_NUM_0 0xff 97 98 #define BITMAP_NO_RR 0 99 #define BITMAP_RR 1 100 101 #define MR_TYPE_MR 0x00 102 #define MR_TYPE_FRMR 0x01 103 #define MR_TYPE_DMA 0x03 104 105 #define HNS_ROCE_FRMR_MAX_PA 512 106 107 #define PKEY_ID 0xffff 108 #define GUID_LEN 8 109 #define NODE_DESC_SIZE 64 110 #define DB_REG_OFFSET 0x1000 111 112 #define SERV_TYPE_RC 0 113 #define SERV_TYPE_RD 1 114 #define SERV_TYPE_UC 2 115 #define SERV_TYPE_UD 3 116 117 /* Configure to HW for PAGE_SIZE larger than 4KB */ 118 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 119 120 #define PAGES_SHIFT_8 8 121 #define PAGES_SHIFT_16 16 122 #define PAGES_SHIFT_24 24 123 #define PAGES_SHIFT_32 32 124 125 #define HNS_ROCE_PCI_BAR_NUM 2 126 127 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 128 #define SRQ_DB_REG 0x230 129 130 /* The chip implementation of the consumer index is calculated 131 * according to twice the actual EQ depth 132 */ 133 #define EQ_DEPTH_COEFF 2 134 135 enum { 136 HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0, 137 HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1, 138 }; 139 140 enum { 141 HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0, 142 }; 143 144 enum hns_roce_qp_state { 145 HNS_ROCE_QP_STATE_RST, 146 HNS_ROCE_QP_STATE_INIT, 147 HNS_ROCE_QP_STATE_RTR, 148 HNS_ROCE_QP_STATE_RTS, 149 HNS_ROCE_QP_STATE_SQD, 150 HNS_ROCE_QP_STATE_ERR, 151 HNS_ROCE_QP_NUM_STATE, 152 }; 153 154 enum hns_roce_event { 155 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 156 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 157 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 158 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 159 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 160 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 161 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 162 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 163 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 164 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 165 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 166 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 167 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 168 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 169 /* 0x10 and 0x11 is unused in currently application case */ 170 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 171 HNS_ROCE_EVENT_TYPE_MB = 0x13, 172 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, 173 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 174 }; 175 176 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ 177 enum { 178 HNS_ROCE_LWQCE_QPC_ERROR = 1, 179 HNS_ROCE_LWQCE_MTU_ERROR = 2, 180 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, 181 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, 182 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, 183 HNS_ROCE_LWQCE_SL_ERROR = 6, 184 HNS_ROCE_LWQCE_PORT_ERROR = 7, 185 }; 186 187 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ 188 enum { 189 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, 190 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, 191 HNS_ROCE_LAVWQE_VA_ERROR = 3, 192 HNS_ROCE_LAVWQE_PD_ERROR = 4, 193 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, 194 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, 195 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, 196 }; 197 198 /* DOORBELL overflow subtype */ 199 enum { 200 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, 201 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, 202 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, 203 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, 204 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, 205 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, 206 }; 207 208 enum { 209 /* RQ&SRQ related operations */ 210 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, 211 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, 212 }; 213 214 enum { 215 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 216 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 217 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 218 HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), 219 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), 220 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 221 HNS_ROCE_CAP_FLAG_MW = BIT(7), 222 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 223 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 224 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 225 }; 226 227 enum hns_roce_mtt_type { 228 MTT_TYPE_WQE, 229 MTT_TYPE_CQE, 230 MTT_TYPE_SRQWQE, 231 MTT_TYPE_IDX 232 }; 233 234 #define HNS_ROCE_DB_TYPE_COUNT 2 235 #define HNS_ROCE_DB_UNIT_SIZE 4 236 237 enum { 238 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 239 }; 240 241 enum hns_roce_reset_stage { 242 HNS_ROCE_STATE_NON_RST, 243 HNS_ROCE_STATE_RST_BEF_DOWN, 244 HNS_ROCE_STATE_RST_DOWN, 245 HNS_ROCE_STATE_RST_UNINIT, 246 HNS_ROCE_STATE_RST_INIT, 247 HNS_ROCE_STATE_RST_INITED, 248 }; 249 250 enum hns_roce_instance_state { 251 HNS_ROCE_STATE_NON_INIT, 252 HNS_ROCE_STATE_INIT, 253 HNS_ROCE_STATE_INITED, 254 HNS_ROCE_STATE_UNINIT, 255 }; 256 257 enum { 258 HNS_ROCE_RST_DIRECT_RETURN = 0, 259 }; 260 261 enum { 262 CMD_RST_PRC_OTHERS, 263 CMD_RST_PRC_SUCCESS, 264 CMD_RST_PRC_EBUSY, 265 }; 266 267 #define HNS_ROCE_CMD_SUCCESS 1 268 269 #define HNS_ROCE_PORT_DOWN 0 270 #define HNS_ROCE_PORT_UP 1 271 272 #define HNS_ROCE_MTT_ENTRY_PER_SEG 8 273 274 #define PAGE_ADDR_SHIFT 12 275 276 struct hns_roce_uar { 277 u64 pfn; 278 unsigned long index; 279 unsigned long logic_idx; 280 }; 281 282 struct hns_roce_ucontext { 283 struct ib_ucontext ibucontext; 284 struct hns_roce_uar uar; 285 struct list_head page_list; 286 struct mutex page_mutex; 287 }; 288 289 struct hns_roce_pd { 290 struct ib_pd ibpd; 291 unsigned long pdn; 292 }; 293 294 struct hns_roce_bitmap { 295 /* Bitmap Traversal last a bit which is 1 */ 296 unsigned long last; 297 unsigned long top; 298 unsigned long max; 299 unsigned long reserved_top; 300 unsigned long mask; 301 spinlock_t lock; 302 unsigned long *table; 303 }; 304 305 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */ 306 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ 307 /* Every bit repesent to a partner free/used status in bitmap */ 308 /* 309 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 310 * Bit = 1 represent to idle and available; bit = 0: not available 311 */ 312 struct hns_roce_buddy { 313 /* Members point to every order level bitmap */ 314 unsigned long **bits; 315 /* Represent to avail bits of the order level bitmap */ 316 u32 *num_free; 317 int max_order; 318 spinlock_t lock; 319 }; 320 321 /* For Hardware Entry Memory */ 322 struct hns_roce_hem_table { 323 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 324 u32 type; 325 /* HEM array elment num */ 326 unsigned long num_hem; 327 /* HEM entry record obj total num */ 328 unsigned long num_obj; 329 /* Single obj size */ 330 unsigned long obj_size; 331 unsigned long table_chunk_size; 332 int lowmem; 333 struct mutex mutex; 334 struct hns_roce_hem **hem; 335 u64 **bt_l1; 336 dma_addr_t *bt_l1_dma_addr; 337 u64 **bt_l0; 338 dma_addr_t *bt_l0_dma_addr; 339 }; 340 341 struct hns_roce_mtt { 342 unsigned long first_seg; 343 int order; 344 int page_shift; 345 enum hns_roce_mtt_type mtt_type; 346 }; 347 348 struct hns_roce_buf_region { 349 int offset; /* page offset */ 350 u32 count; /* page count */ 351 int hopnum; /* addressing hop num */ 352 }; 353 354 #define HNS_ROCE_MAX_BT_REGION 3 355 #define HNS_ROCE_MAX_BT_LEVEL 3 356 struct hns_roce_hem_list { 357 struct list_head root_bt; 358 /* link all bt dma mem by hop config */ 359 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 360 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 361 dma_addr_t root_ba; /* pointer to the root ba table */ 362 int bt_pg_shift; 363 }; 364 365 /* memory translate region */ 366 struct hns_roce_mtr { 367 struct hns_roce_hem_list hem_list; 368 int buf_pg_shift; 369 }; 370 371 struct hns_roce_mw { 372 struct ib_mw ibmw; 373 u32 pdn; 374 u32 rkey; 375 int enabled; /* MW's active status */ 376 u32 pbl_hop_num; 377 u32 pbl_ba_pg_sz; 378 u32 pbl_buf_pg_sz; 379 }; 380 381 /* Only support 4K page size for mr register */ 382 #define MR_SIZE_4K 0 383 384 struct hns_roce_mr { 385 struct ib_mr ibmr; 386 struct ib_umem *umem; 387 u64 iova; /* MR's virtual orignal addr */ 388 u64 size; /* Address range of MR */ 389 u32 key; /* Key of MR */ 390 u32 pd; /* PD num of MR */ 391 u32 access; /* Access permission of MR */ 392 u32 npages; 393 int enabled; /* MR's active status */ 394 int type; /* MR's register type */ 395 u64 *pbl_buf; /* MR's PBL space */ 396 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ 397 u32 pbl_size; /* PA number in the PBL */ 398 u64 pbl_ba; /* page table address */ 399 u32 l0_chunk_last_num; /* L0 last number */ 400 u32 l1_chunk_last_num; /* L1 last number */ 401 u64 **pbl_bt_l2; /* PBL BT L2 */ 402 u64 **pbl_bt_l1; /* PBL BT L1 */ 403 u64 *pbl_bt_l0; /* PBL BT L0 */ 404 dma_addr_t *pbl_l2_dma_addr; /* PBL BT L2 dma addr */ 405 dma_addr_t *pbl_l1_dma_addr; /* PBL BT L1 dma addr */ 406 dma_addr_t pbl_l0_dma_addr; /* PBL BT L0 dma addr */ 407 u32 pbl_ba_pg_sz; /* BT chunk page size */ 408 u32 pbl_buf_pg_sz; /* buf chunk page size */ 409 u32 pbl_hop_num; /* multi-hop number */ 410 }; 411 412 struct hns_roce_mr_table { 413 struct hns_roce_bitmap mtpt_bitmap; 414 struct hns_roce_buddy mtt_buddy; 415 struct hns_roce_hem_table mtt_table; 416 struct hns_roce_hem_table mtpt_table; 417 struct hns_roce_buddy mtt_cqe_buddy; 418 struct hns_roce_hem_table mtt_cqe_table; 419 struct hns_roce_buddy mtt_srqwqe_buddy; 420 struct hns_roce_hem_table mtt_srqwqe_table; 421 struct hns_roce_buddy mtt_idx_buddy; 422 struct hns_roce_hem_table mtt_idx_table; 423 }; 424 425 struct hns_roce_wq { 426 u64 *wrid; /* Work request ID */ 427 spinlock_t lock; 428 int wqe_cnt; /* WQE num */ 429 u32 max_post; 430 int max_gs; 431 int offset; 432 int wqe_shift; /* WQE size */ 433 u32 head; 434 u32 tail; 435 void __iomem *db_reg_l; 436 }; 437 438 struct hns_roce_sge { 439 int sge_cnt; /* SGE num */ 440 int offset; 441 int sge_shift; /* SGE size */ 442 }; 443 444 struct hns_roce_buf_list { 445 void *buf; 446 dma_addr_t map; 447 }; 448 449 struct hns_roce_buf { 450 struct hns_roce_buf_list direct; 451 struct hns_roce_buf_list *page_list; 452 int nbufs; 453 u32 npages; 454 int page_shift; 455 }; 456 457 struct hns_roce_db_pgdir { 458 struct list_head list; 459 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 460 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 461 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 462 u32 *page; 463 dma_addr_t db_dma; 464 }; 465 466 struct hns_roce_user_db_page { 467 struct list_head list; 468 struct ib_umem *umem; 469 unsigned long user_virt; 470 refcount_t refcount; 471 }; 472 473 struct hns_roce_db { 474 u32 *db_record; 475 union { 476 struct hns_roce_db_pgdir *pgdir; 477 struct hns_roce_user_db_page *user_page; 478 } u; 479 dma_addr_t dma; 480 void *virt_addr; 481 int index; 482 int order; 483 }; 484 485 struct hns_roce_cq_buf { 486 struct hns_roce_buf hr_buf; 487 struct hns_roce_mtt hr_mtt; 488 }; 489 490 struct hns_roce_cq { 491 struct ib_cq ib_cq; 492 struct hns_roce_cq_buf hr_buf; 493 struct hns_roce_db db; 494 u8 db_en; 495 spinlock_t lock; 496 struct ib_umem *umem; 497 void (*comp)(struct hns_roce_cq *cq); 498 void (*event)(struct hns_roce_cq *cq, enum hns_roce_event event_type); 499 500 struct hns_roce_uar *uar; 501 u32 cq_depth; 502 u32 cons_index; 503 u32 *set_ci_db; 504 void __iomem *cq_db_l; 505 u16 *tptr_addr; 506 int arm_sn; 507 unsigned long cqn; 508 u32 vector; 509 atomic_t refcount; 510 struct completion free; 511 }; 512 513 struct hns_roce_idx_que { 514 struct hns_roce_buf idx_buf; 515 int entry_sz; 516 u32 buf_size; 517 struct ib_umem *umem; 518 struct hns_roce_mtt mtt; 519 unsigned long *bitmap; 520 }; 521 522 struct hns_roce_srq { 523 struct ib_srq ibsrq; 524 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 525 unsigned long srqn; 526 int max; 527 int max_gs; 528 int wqe_shift; 529 void __iomem *db_reg_l; 530 531 atomic_t refcount; 532 struct completion free; 533 534 struct hns_roce_buf buf; 535 u64 *wrid; 536 struct ib_umem *umem; 537 struct hns_roce_mtt mtt; 538 struct hns_roce_idx_que idx_que; 539 spinlock_t lock; 540 int head; 541 int tail; 542 u16 wqe_ctr; 543 struct mutex mutex; 544 }; 545 546 struct hns_roce_uar_table { 547 struct hns_roce_bitmap bitmap; 548 }; 549 550 struct hns_roce_qp_table { 551 struct hns_roce_bitmap bitmap; 552 struct hns_roce_hem_table qp_table; 553 struct hns_roce_hem_table irrl_table; 554 struct hns_roce_hem_table trrl_table; 555 struct hns_roce_hem_table sccc_table; 556 struct mutex scc_mutex; 557 }; 558 559 struct hns_roce_cq_table { 560 struct hns_roce_bitmap bitmap; 561 struct xarray array; 562 struct hns_roce_hem_table table; 563 }; 564 565 struct hns_roce_srq_table { 566 struct hns_roce_bitmap bitmap; 567 struct xarray xa; 568 struct hns_roce_hem_table table; 569 }; 570 571 struct hns_roce_raq_table { 572 struct hns_roce_buf_list *e_raq_buf; 573 }; 574 575 struct hns_roce_av { 576 u8 port; 577 u8 gid_index; 578 u8 stat_rate; 579 u8 hop_limit; 580 u32 flowlabel; 581 u8 sl; 582 u8 tclass; 583 u8 dgid[HNS_ROCE_GID_SIZE]; 584 u8 mac[ETH_ALEN]; 585 u16 vlan; 586 bool vlan_en; 587 }; 588 589 struct hns_roce_ah { 590 struct ib_ah ibah; 591 struct hns_roce_av av; 592 }; 593 594 struct hns_roce_cmd_context { 595 struct completion done; 596 int result; 597 int next; 598 u64 out_param; 599 u16 token; 600 }; 601 602 struct hns_roce_cmdq { 603 struct dma_pool *pool; 604 struct mutex hcr_mutex; 605 struct semaphore poll_sem; 606 /* 607 * Event mode: cmd register mutex protection, 608 * ensure to not exceed max_cmds and user use limit region 609 */ 610 struct semaphore event_sem; 611 int max_cmds; 612 spinlock_t context_lock; 613 int free_head; 614 struct hns_roce_cmd_context *context; 615 /* 616 * Result of get integer part 617 * which max_comds compute according a power of 2 618 */ 619 u16 token_mask; 620 /* 621 * Process whether use event mode, init default non-zero 622 * After the event queue of cmd event ready, 623 * can switch into event mode 624 * close device, switch into poll mode(non event mode) 625 */ 626 u8 use_events; 627 }; 628 629 struct hns_roce_cmd_mailbox { 630 void *buf; 631 dma_addr_t dma; 632 }; 633 634 struct hns_roce_dev; 635 636 struct hns_roce_rinl_sge { 637 void *addr; 638 u32 len; 639 }; 640 641 struct hns_roce_rinl_wqe { 642 struct hns_roce_rinl_sge *sg_list; 643 u32 sge_cnt; 644 }; 645 646 struct hns_roce_rinl_buf { 647 struct hns_roce_rinl_wqe *wqe_list; 648 u32 wqe_cnt; 649 }; 650 651 struct hns_roce_qp { 652 struct ib_qp ibqp; 653 struct hns_roce_buf hr_buf; 654 struct hns_roce_wq rq; 655 struct hns_roce_db rdb; 656 struct hns_roce_db sdb; 657 u8 rdb_en; 658 u8 sdb_en; 659 u32 doorbell_qpn; 660 u32 sq_signal_bits; 661 u32 sq_next_wqe; 662 struct hns_roce_wq sq; 663 664 struct ib_umem *umem; 665 struct hns_roce_mtt mtt; 666 struct hns_roce_mtr mtr; 667 668 /* this define must less than HNS_ROCE_MAX_BT_REGION */ 669 #define HNS_ROCE_WQE_REGION_MAX 3 670 struct hns_roce_buf_region regions[HNS_ROCE_WQE_REGION_MAX]; 671 int region_cnt; 672 int wqe_bt_pg_shift; 673 674 u32 buff_size; 675 struct mutex mutex; 676 u8 port; 677 u8 phy_port; 678 u8 sl; 679 u8 resp_depth; 680 u8 state; 681 u32 access_flags; 682 u32 atomic_rd_en; 683 u32 pkey_index; 684 u32 qkey; 685 void (*event)(struct hns_roce_qp *qp, 686 enum hns_roce_event event_type); 687 unsigned long qpn; 688 689 atomic_t refcount; 690 struct completion free; 691 692 struct hns_roce_sge sge; 693 u32 next_sge; 694 695 struct hns_roce_rinl_buf rq_inl_buf; 696 }; 697 698 struct hns_roce_sqp { 699 struct hns_roce_qp hr_qp; 700 }; 701 702 struct hns_roce_ib_iboe { 703 spinlock_t lock; 704 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 705 struct notifier_block nb; 706 u8 phy_port[HNS_ROCE_MAX_PORTS]; 707 }; 708 709 enum { 710 HNS_ROCE_EQ_STAT_INVALID = 0, 711 HNS_ROCE_EQ_STAT_VALID = 2, 712 }; 713 714 struct hns_roce_ceqe { 715 __le32 comp; 716 }; 717 718 struct hns_roce_aeqe { 719 __le32 asyn; 720 union { 721 struct { 722 __le32 qp; 723 u32 rsv0; 724 u32 rsv1; 725 } qp_event; 726 727 struct { 728 __le32 srq; 729 u32 rsv0; 730 u32 rsv1; 731 } srq_event; 732 733 struct { 734 __le32 cq; 735 u32 rsv0; 736 u32 rsv1; 737 } cq_event; 738 739 struct { 740 __le32 ceqe; 741 u32 rsv0; 742 u32 rsv1; 743 } ce_event; 744 745 struct { 746 __le64 out_param; 747 __le16 token; 748 u8 status; 749 u8 rsv0; 750 } __packed cmd; 751 } event; 752 }; 753 754 struct hns_roce_eq { 755 struct hns_roce_dev *hr_dev; 756 void __iomem *doorbell; 757 758 int type_flag; /* Aeq:1 ceq:0 */ 759 int eqn; 760 u32 entries; 761 int log_entries; 762 int eqe_size; 763 int irq; 764 int log_page_size; 765 int cons_index; 766 struct hns_roce_buf_list *buf_list; 767 int over_ignore; 768 int coalesce; 769 int arm_st; 770 u64 eqe_ba; 771 int eqe_ba_pg_sz; 772 int eqe_buf_pg_sz; 773 int hop_num; 774 u64 *bt_l0; /* Base address table for L0 */ 775 u64 **bt_l1; /* Base address table for L1 */ 776 u64 **buf; 777 dma_addr_t l0_dma; 778 dma_addr_t *l1_dma; 779 dma_addr_t *buf_dma; 780 u32 l0_last_num; /* L0 last chunk num */ 781 u32 l1_last_num; /* L1 last chunk num */ 782 int eq_max_cnt; 783 int eq_period; 784 int shift; 785 dma_addr_t cur_eqe_ba; 786 dma_addr_t nxt_eqe_ba; 787 int event_type; 788 int sub_type; 789 }; 790 791 struct hns_roce_eq_table { 792 struct hns_roce_eq *eq; 793 void __iomem **eqc_base; /* only for hw v1 */ 794 }; 795 796 struct hns_roce_caps { 797 u64 fw_ver; 798 u8 num_ports; 799 int gid_table_len[HNS_ROCE_MAX_PORTS]; 800 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 801 int local_ca_ack_delay; 802 int num_uars; 803 u32 phy_num_uars; 804 u32 max_sq_sg; 805 u32 max_sq_inline; 806 u32 max_rq_sg; 807 u32 max_extend_sg; 808 int num_qps; 809 int reserved_qps; 810 int num_qpc_timer; 811 int num_cqc_timer; 812 u32 max_srq_sg; 813 int num_srqs; 814 u32 max_wqes; 815 u32 max_srqs; 816 u32 max_srq_wrs; 817 u32 max_srq_sges; 818 u32 max_sq_desc_sz; 819 u32 max_rq_desc_sz; 820 u32 max_srq_desc_sz; 821 int max_qp_init_rdma; 822 int max_qp_dest_rdma; 823 int num_cqs; 824 int max_cqes; 825 int min_cqes; 826 u32 min_wqes; 827 int reserved_cqs; 828 int reserved_srqs; 829 u32 max_srqwqes; 830 int num_aeq_vectors; 831 int num_comp_vectors; 832 int num_other_vectors; 833 int num_mtpts; 834 u32 num_mtt_segs; 835 u32 num_cqe_segs; 836 u32 num_srqwqe_segs; 837 u32 num_idx_segs; 838 int reserved_mrws; 839 int reserved_uars; 840 int num_pds; 841 int reserved_pds; 842 u32 mtt_entry_sz; 843 u32 cq_entry_sz; 844 u32 page_size_cap; 845 u32 reserved_lkey; 846 int mtpt_entry_sz; 847 int qpc_entry_sz; 848 int irrl_entry_sz; 849 int trrl_entry_sz; 850 int cqc_entry_sz; 851 int sccc_entry_sz; 852 int qpc_timer_entry_sz; 853 int cqc_timer_entry_sz; 854 int srqc_entry_sz; 855 int idx_entry_sz; 856 u32 pbl_ba_pg_sz; 857 u32 pbl_buf_pg_sz; 858 u32 pbl_hop_num; 859 int aeqe_depth; 860 int ceqe_depth; 861 enum ib_mtu max_mtu; 862 u32 qpc_bt_num; 863 u32 qpc_timer_bt_num; 864 u32 srqc_bt_num; 865 u32 cqc_bt_num; 866 u32 cqc_timer_bt_num; 867 u32 mpt_bt_num; 868 u32 sccc_bt_num; 869 u32 qpc_ba_pg_sz; 870 u32 qpc_buf_pg_sz; 871 u32 qpc_hop_num; 872 u32 srqc_ba_pg_sz; 873 u32 srqc_buf_pg_sz; 874 u32 srqc_hop_num; 875 u32 cqc_ba_pg_sz; 876 u32 cqc_buf_pg_sz; 877 u32 cqc_hop_num; 878 u32 mpt_ba_pg_sz; 879 u32 mpt_buf_pg_sz; 880 u32 mpt_hop_num; 881 u32 mtt_ba_pg_sz; 882 u32 mtt_buf_pg_sz; 883 u32 mtt_hop_num; 884 u32 wqe_sq_hop_num; 885 u32 wqe_sge_hop_num; 886 u32 wqe_rq_hop_num; 887 u32 sccc_ba_pg_sz; 888 u32 sccc_buf_pg_sz; 889 u32 sccc_hop_num; 890 u32 qpc_timer_ba_pg_sz; 891 u32 qpc_timer_buf_pg_sz; 892 u32 qpc_timer_hop_num; 893 u32 cqc_timer_ba_pg_sz; 894 u32 cqc_timer_buf_pg_sz; 895 u32 cqc_timer_hop_num; 896 u32 cqe_ba_pg_sz; 897 u32 cqe_buf_pg_sz; 898 u32 cqe_hop_num; 899 u32 srqwqe_ba_pg_sz; 900 u32 srqwqe_buf_pg_sz; 901 u32 srqwqe_hop_num; 902 u32 idx_ba_pg_sz; 903 u32 idx_buf_pg_sz; 904 u32 idx_hop_num; 905 u32 eqe_ba_pg_sz; 906 u32 eqe_buf_pg_sz; 907 u32 eqe_hop_num; 908 u32 sl_num; 909 u32 tsq_buf_pg_sz; 910 u32 tpq_buf_pg_sz; 911 u32 chunk_sz; /* chunk size in non multihop mode */ 912 u64 flags; 913 }; 914 915 struct hns_roce_work { 916 struct hns_roce_dev *hr_dev; 917 struct work_struct work; 918 u32 qpn; 919 u32 cqn; 920 int event_type; 921 int sub_type; 922 }; 923 924 struct hns_roce_dfx_hw { 925 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, 926 int *buffer); 927 }; 928 929 struct hns_roce_hw { 930 int (*reset)(struct hns_roce_dev *hr_dev, bool enable); 931 int (*cmq_init)(struct hns_roce_dev *hr_dev); 932 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 933 int (*hw_profile)(struct hns_roce_dev *hr_dev); 934 int (*hw_init)(struct hns_roce_dev *hr_dev); 935 void (*hw_exit)(struct hns_roce_dev *hr_dev); 936 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, 937 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, 938 u16 token, int event); 939 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); 940 int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); 941 int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, 942 const union ib_gid *gid, const struct ib_gid_attr *attr); 943 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); 944 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, 945 enum ib_mtu mtu); 946 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, 947 unsigned long mtpt_idx); 948 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 949 struct hns_roce_mr *mr, int flags, u32 pdn, 950 int mr_access_flags, u64 iova, u64 size, 951 void *mb_buf); 952 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 953 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 954 void (*write_cqc)(struct hns_roce_dev *hr_dev, 955 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 956 dma_addr_t dma_handle, int nent, u32 vector); 957 int (*set_hem)(struct hns_roce_dev *hr_dev, 958 struct hns_roce_hem_table *table, int obj, int step_idx); 959 int (*clear_hem)(struct hns_roce_dev *hr_dev, 960 struct hns_roce_hem_table *table, int obj, 961 int step_idx); 962 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 963 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); 964 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 965 int attr_mask, enum ib_qp_state cur_state, 966 enum ib_qp_state new_state); 967 int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); 968 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 969 struct hns_roce_qp *hr_qp); 970 int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, 971 const struct ib_send_wr **bad_wr); 972 int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, 973 const struct ib_recv_wr **bad_recv_wr); 974 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 975 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 976 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, 977 struct ib_udata *udata); 978 void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); 979 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); 980 int (*init_eq)(struct hns_roce_dev *hr_dev); 981 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 982 void (*write_srqc)(struct hns_roce_dev *hr_dev, 983 struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, 984 void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, 985 dma_addr_t dma_handle_wqe, 986 dma_addr_t dma_handle_idx); 987 int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 988 enum ib_srq_attr_mask srq_attr_mask, 989 struct ib_udata *udata); 990 int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); 991 int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 992 const struct ib_recv_wr **bad_wr); 993 const struct ib_device_ops *hns_roce_dev_ops; 994 const struct ib_device_ops *hns_roce_dev_srq_ops; 995 }; 996 997 struct hns_roce_dev { 998 struct ib_device ib_dev; 999 struct platform_device *pdev; 1000 struct pci_dev *pci_dev; 1001 struct device *dev; 1002 struct hns_roce_uar priv_uar; 1003 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 1004 spinlock_t sm_lock; 1005 spinlock_t bt_cmd_lock; 1006 bool active; 1007 bool is_reset; 1008 bool dis_db; 1009 unsigned long reset_cnt; 1010 struct hns_roce_ib_iboe iboe; 1011 1012 struct list_head pgdir_list; 1013 struct mutex pgdir_mutex; 1014 int irq[HNS_ROCE_MAX_IRQ_NUM]; 1015 u8 __iomem *reg_base; 1016 struct hns_roce_caps caps; 1017 struct xarray qp_table_xa; 1018 1019 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 1020 u64 sys_image_guid; 1021 u32 vendor_id; 1022 u32 vendor_part_id; 1023 u32 hw_rev; 1024 void __iomem *priv_addr; 1025 1026 struct hns_roce_cmdq cmd; 1027 struct hns_roce_bitmap pd_bitmap; 1028 struct hns_roce_uar_table uar_table; 1029 struct hns_roce_mr_table mr_table; 1030 struct hns_roce_cq_table cq_table; 1031 struct hns_roce_srq_table srq_table; 1032 struct hns_roce_qp_table qp_table; 1033 struct hns_roce_eq_table eq_table; 1034 struct hns_roce_hem_table qpc_timer_table; 1035 struct hns_roce_hem_table cqc_timer_table; 1036 1037 int cmd_mod; 1038 int loop_idc; 1039 u32 sdb_offset; 1040 u32 odb_offset; 1041 dma_addr_t tptr_dma_addr; /* only for hw v1 */ 1042 u32 tptr_size; /* only for hw v1 */ 1043 const struct hns_roce_hw *hw; 1044 void *priv; 1045 struct workqueue_struct *irq_workq; 1046 const struct hns_roce_dfx_hw *dfx; 1047 }; 1048 1049 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 1050 { 1051 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 1052 } 1053 1054 static inline struct hns_roce_ucontext 1055 *to_hr_ucontext(struct ib_ucontext *ibucontext) 1056 { 1057 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 1058 } 1059 1060 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 1061 { 1062 return container_of(ibpd, struct hns_roce_pd, ibpd); 1063 } 1064 1065 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1066 { 1067 return container_of(ibah, struct hns_roce_ah, ibah); 1068 } 1069 1070 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1071 { 1072 return container_of(ibmr, struct hns_roce_mr, ibmr); 1073 } 1074 1075 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1076 { 1077 return container_of(ibmw, struct hns_roce_mw, ibmw); 1078 } 1079 1080 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1081 { 1082 return container_of(ibqp, struct hns_roce_qp, ibqp); 1083 } 1084 1085 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1086 { 1087 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1088 } 1089 1090 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1091 { 1092 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1093 } 1094 1095 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp) 1096 { 1097 return container_of(hr_qp, struct hns_roce_sqp, hr_qp); 1098 } 1099 1100 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1101 { 1102 __raw_writeq(*(u64 *) val, dest); 1103 } 1104 1105 static inline struct hns_roce_qp 1106 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1107 { 1108 return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); 1109 } 1110 1111 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) 1112 { 1113 u32 page_size = 1 << buf->page_shift; 1114 1115 if (buf->nbufs == 1) 1116 return (char *)(buf->direct.buf) + offset; 1117 else 1118 return (char *)(buf->page_list[offset >> buf->page_shift].buf) + 1119 (offset & (page_size - 1)); 1120 } 1121 1122 int hns_roce_init_uar_table(struct hns_roce_dev *dev); 1123 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1124 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1125 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); 1126 1127 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1128 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1129 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1130 u64 out_param); 1131 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1132 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1133 1134 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, 1135 struct hns_roce_mtt *mtt); 1136 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, 1137 struct hns_roce_mtt *mtt); 1138 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, 1139 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf); 1140 1141 void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, 1142 int buf_pg_shift); 1143 int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1144 dma_addr_t **bufs, struct hns_roce_buf_region *regions, 1145 int region_cnt); 1146 void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev, 1147 struct hns_roce_mtr *mtr); 1148 1149 /* hns roce hw need current block and next block addr from mtt */ 1150 #define MTT_MIN_COUNT 2 1151 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1152 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1153 1154 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1155 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1156 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev); 1157 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1158 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1159 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1160 1161 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); 1162 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); 1163 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); 1164 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1165 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1166 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); 1167 1168 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 1169 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, 1170 int rr); 1171 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 1172 u32 reserved_bot, u32 resetrved_top); 1173 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 1174 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1175 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 1176 int align, unsigned long *obj); 1177 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 1178 unsigned long obj, int cnt, 1179 int rr); 1180 1181 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, 1182 u32 flags, struct ib_udata *udata); 1183 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1184 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags); 1185 1186 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1187 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1188 1189 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1190 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1191 u64 virt_addr, int access_flags, 1192 struct ib_udata *udata); 1193 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, 1194 u64 virt_addr, int mr_access_flags, struct ib_pd *pd, 1195 struct ib_udata *udata); 1196 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1197 u32 max_num_sg, struct ib_udata *udata); 1198 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1199 unsigned int *sg_offset); 1200 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1201 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev, 1202 struct hns_roce_cmd_mailbox *mailbox, 1203 unsigned long mpt_index); 1204 unsigned long key_to_hw_index(u32 key); 1205 1206 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, 1207 struct ib_udata *udata); 1208 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1209 1210 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 1211 struct hns_roce_buf *buf); 1212 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, 1213 struct hns_roce_buf *buf, u32 page_shift); 1214 1215 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, 1216 struct hns_roce_mtt *mtt, struct ib_umem *umem); 1217 1218 void hns_roce_init_buf_region(struct hns_roce_buf_region *region, int hopnum, 1219 int offset, int buf_cnt); 1220 int hns_roce_alloc_buf_list(struct hns_roce_buf_region *regions, 1221 dma_addr_t **bufs, int count); 1222 void hns_roce_free_buf_list(dma_addr_t **bufs, int count); 1223 1224 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1225 int buf_cnt, int start, struct hns_roce_buf *buf); 1226 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1227 int buf_cnt, int start, struct ib_umem *umem, 1228 int page_shift); 1229 1230 int hns_roce_create_srq(struct ib_srq *srq, 1231 struct ib_srq_init_attr *srq_init_attr, 1232 struct ib_udata *udata); 1233 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, 1234 enum ib_srq_attr_mask srq_attr_mask, 1235 struct ib_udata *udata); 1236 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1237 1238 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, 1239 struct ib_qp_init_attr *init_attr, 1240 struct ib_udata *udata); 1241 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1242 int attr_mask, struct ib_udata *udata); 1243 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n); 1244 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n); 1245 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n); 1246 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, 1247 struct ib_cq *ib_cq); 1248 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); 1249 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1250 struct hns_roce_cq *recv_cq); 1251 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1252 struct hns_roce_cq *recv_cq); 1253 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1254 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1255 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, 1256 int cnt); 1257 __be32 send_ieth(const struct ib_send_wr *wr); 1258 int to_hr_qp_type(int qp_type); 1259 1260 int hns_roce_ib_create_cq(struct ib_cq *ib_cq, 1261 const struct ib_cq_init_attr *attr, 1262 struct ib_udata *udata); 1263 1264 void hns_roce_ib_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1265 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq); 1266 1267 int hns_roce_db_map_user(struct hns_roce_ucontext *context, 1268 struct ib_udata *udata, unsigned long virt, 1269 struct hns_roce_db *db); 1270 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1271 struct hns_roce_db *db); 1272 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1273 int order); 1274 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1275 1276 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1277 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1278 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1279 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1280 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); 1281 int hns_roce_init(struct hns_roce_dev *hr_dev); 1282 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1283 1284 int hns_roce_fill_res_entry(struct sk_buff *msg, 1285 struct rdma_restrack_entry *res); 1286 #endif /* _HNS_ROCE_DEVICE_H */ 1287