1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define PCI_REVISION_ID_HIP08 0x21 40 #define PCI_REVISION_ID_HIP09 0x30 41 42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 43 44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 45 46 #define BA_BYTE_LEN 8 47 48 #define HNS_ROCE_MIN_CQE_NUM 0x40 49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 50 51 #define HNS_ROCE_MAX_IRQ_NUM 128 52 53 #define HNS_ROCE_SGE_IN_WQE 2 54 #define HNS_ROCE_SGE_SHIFT 4 55 56 #define EQ_ENABLE 1 57 #define EQ_DISABLE 0 58 59 #define HNS_ROCE_CEQ 0 60 #define HNS_ROCE_AEQ 1 61 62 #define HNS_ROCE_CEQE_SIZE 0x4 63 #define HNS_ROCE_AEQE_SIZE 0x10 64 65 #define HNS_ROCE_V3_EQE_SIZE 0x40 66 67 #define HNS_ROCE_V2_CQE_SIZE 32 68 #define HNS_ROCE_V3_CQE_SIZE 64 69 70 #define HNS_ROCE_V2_QPC_SZ 256 71 #define HNS_ROCE_V3_QPC_SZ 512 72 73 #define HNS_ROCE_MAX_PORTS 6 74 #define HNS_ROCE_GID_SIZE 16 75 #define HNS_ROCE_SGE_SIZE 16 76 #define HNS_ROCE_DWQE_SIZE 65536 77 78 #define HNS_ROCE_HOP_NUM_0 0xff 79 80 #define MR_TYPE_MR 0x00 81 #define MR_TYPE_FRMR 0x01 82 #define MR_TYPE_DMA 0x03 83 84 #define HNS_ROCE_FRMR_MAX_PA 512 85 86 #define PKEY_ID 0xffff 87 #define NODE_DESC_SIZE 64 88 #define DB_REG_OFFSET 0x1000 89 90 /* Configure to HW for PAGE_SIZE larger than 4KB */ 91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 92 93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 94 #define SRQ_DB_REG 0x230 95 96 #define HNS_ROCE_QP_BANK_NUM 8 97 #define HNS_ROCE_CQ_BANK_NUM 4 98 99 #define CQ_BANKID_SHIFT 2 100 #define CQ_BANKID_MASK GENMASK(1, 0) 101 102 enum { 103 SERV_TYPE_RC, 104 SERV_TYPE_UC, 105 SERV_TYPE_RD, 106 SERV_TYPE_UD, 107 SERV_TYPE_XRC = 5, 108 }; 109 110 enum hns_roce_event { 111 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 112 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 113 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 114 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 115 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 116 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 117 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 118 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 119 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 120 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 121 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 122 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 123 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 124 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 125 /* 0x10 and 0x11 is unused in currently application case */ 126 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 127 HNS_ROCE_EVENT_TYPE_MB = 0x13, 128 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 129 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 130 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 131 }; 132 133 enum { 134 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 135 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 136 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 137 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 138 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 139 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 140 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 141 HNS_ROCE_CAP_FLAG_MW = BIT(7), 142 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 143 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 144 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 145 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 146 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 147 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 148 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 149 }; 150 151 #define HNS_ROCE_DB_TYPE_COUNT 2 152 #define HNS_ROCE_DB_UNIT_SIZE 4 153 154 enum { 155 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 156 }; 157 158 enum hns_roce_reset_stage { 159 HNS_ROCE_STATE_NON_RST, 160 HNS_ROCE_STATE_RST_BEF_DOWN, 161 HNS_ROCE_STATE_RST_DOWN, 162 HNS_ROCE_STATE_RST_UNINIT, 163 HNS_ROCE_STATE_RST_INIT, 164 HNS_ROCE_STATE_RST_INITED, 165 }; 166 167 enum hns_roce_instance_state { 168 HNS_ROCE_STATE_NON_INIT, 169 HNS_ROCE_STATE_INIT, 170 HNS_ROCE_STATE_INITED, 171 HNS_ROCE_STATE_UNINIT, 172 }; 173 174 enum { 175 HNS_ROCE_RST_DIRECT_RETURN = 0, 176 }; 177 178 #define HNS_ROCE_CMD_SUCCESS 1 179 180 /* The minimum page size is 4K for hardware */ 181 #define HNS_HW_PAGE_SHIFT 12 182 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 183 184 struct hns_roce_uar { 185 u64 pfn; 186 unsigned long index; 187 unsigned long logic_idx; 188 }; 189 190 enum hns_roce_mmap_type { 191 HNS_ROCE_MMAP_TYPE_DB = 1, 192 HNS_ROCE_MMAP_TYPE_DWQE, 193 }; 194 195 struct hns_user_mmap_entry { 196 struct rdma_user_mmap_entry rdma_entry; 197 enum hns_roce_mmap_type mmap_type; 198 u64 address; 199 }; 200 201 struct hns_roce_ucontext { 202 struct ib_ucontext ibucontext; 203 struct hns_roce_uar uar; 204 struct list_head page_list; 205 struct mutex page_mutex; 206 struct hns_user_mmap_entry *db_mmap_entry; 207 u32 config; 208 }; 209 210 struct hns_roce_pd { 211 struct ib_pd ibpd; 212 unsigned long pdn; 213 }; 214 215 struct hns_roce_xrcd { 216 struct ib_xrcd ibxrcd; 217 u32 xrcdn; 218 }; 219 220 struct hns_roce_bitmap { 221 /* Bitmap Traversal last a bit which is 1 */ 222 unsigned long last; 223 unsigned long top; 224 unsigned long max; 225 unsigned long reserved_top; 226 unsigned long mask; 227 spinlock_t lock; 228 unsigned long *table; 229 }; 230 231 struct hns_roce_ida { 232 struct ida ida; 233 u32 min; /* Lowest ID to allocate. */ 234 u32 max; /* Highest ID to allocate. */ 235 }; 236 237 /* For Hardware Entry Memory */ 238 struct hns_roce_hem_table { 239 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 240 u32 type; 241 /* HEM array elment num */ 242 unsigned long num_hem; 243 /* Single obj size */ 244 unsigned long obj_size; 245 unsigned long table_chunk_size; 246 struct mutex mutex; 247 struct hns_roce_hem **hem; 248 u64 **bt_l1; 249 dma_addr_t *bt_l1_dma_addr; 250 u64 **bt_l0; 251 dma_addr_t *bt_l0_dma_addr; 252 }; 253 254 struct hns_roce_buf_region { 255 u32 offset; /* page offset */ 256 u32 count; /* page count */ 257 int hopnum; /* addressing hop num */ 258 }; 259 260 #define HNS_ROCE_MAX_BT_REGION 3 261 #define HNS_ROCE_MAX_BT_LEVEL 3 262 struct hns_roce_hem_list { 263 struct list_head root_bt; 264 /* link all bt dma mem by hop config */ 265 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 266 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 267 dma_addr_t root_ba; /* pointer to the root ba table */ 268 }; 269 270 struct hns_roce_buf_attr { 271 struct { 272 size_t size; /* region size */ 273 int hopnum; /* multi-hop addressing hop num */ 274 } region[HNS_ROCE_MAX_BT_REGION]; 275 unsigned int region_count; /* valid region count */ 276 unsigned int page_shift; /* buffer page shift */ 277 unsigned int user_access; /* umem access flag */ 278 bool mtt_only; /* only alloc buffer-required MTT memory */ 279 }; 280 281 struct hns_roce_hem_cfg { 282 dma_addr_t root_ba; /* root BA table's address */ 283 bool is_direct; /* addressing without BA table */ 284 unsigned int ba_pg_shift; /* BA table page shift */ 285 unsigned int buf_pg_shift; /* buffer page shift */ 286 unsigned int buf_pg_count; /* buffer page count */ 287 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 288 unsigned int region_count; 289 }; 290 291 /* memory translate region */ 292 struct hns_roce_mtr { 293 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 294 struct ib_umem *umem; /* user space buffer */ 295 struct hns_roce_buf *kmem; /* kernel space buffer */ 296 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 297 }; 298 299 struct hns_roce_mw { 300 struct ib_mw ibmw; 301 u32 pdn; 302 u32 rkey; 303 int enabled; /* MW's active status */ 304 u32 pbl_hop_num; 305 u32 pbl_ba_pg_sz; 306 u32 pbl_buf_pg_sz; 307 }; 308 309 struct hns_roce_mr { 310 struct ib_mr ibmr; 311 u64 iova; /* MR's virtual original addr */ 312 u64 size; /* Address range of MR */ 313 u32 key; /* Key of MR */ 314 u32 pd; /* PD num of MR */ 315 u32 access; /* Access permission of MR */ 316 int enabled; /* MR's active status */ 317 int type; /* MR's register type */ 318 u32 pbl_hop_num; /* multi-hop number */ 319 struct hns_roce_mtr pbl_mtr; 320 u32 npages; 321 dma_addr_t *page_list; 322 }; 323 324 struct hns_roce_mr_table { 325 struct hns_roce_ida mtpt_ida; 326 struct hns_roce_hem_table mtpt_table; 327 }; 328 329 struct hns_roce_wq { 330 u64 *wrid; /* Work request ID */ 331 spinlock_t lock; 332 u32 wqe_cnt; /* WQE num */ 333 u32 max_gs; 334 u32 rsv_sge; 335 u32 offset; 336 u32 wqe_shift; /* WQE size */ 337 u32 head; 338 u32 tail; 339 void __iomem *db_reg; 340 u32 ext_sge_cnt; 341 }; 342 343 struct hns_roce_sge { 344 unsigned int sge_cnt; /* SGE num */ 345 u32 offset; 346 u32 sge_shift; /* SGE size */ 347 }; 348 349 struct hns_roce_buf_list { 350 void *buf; 351 dma_addr_t map; 352 }; 353 354 /* 355 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 356 * dma address range. 357 * 358 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 359 * 360 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 361 * the allocated size is smaller than the required size. 362 */ 363 enum { 364 HNS_ROCE_BUF_DIRECT = BIT(0), 365 HNS_ROCE_BUF_NOSLEEP = BIT(1), 366 HNS_ROCE_BUF_NOFAIL = BIT(2), 367 }; 368 369 struct hns_roce_buf { 370 struct hns_roce_buf_list *trunk_list; 371 u32 ntrunks; 372 u32 npages; 373 unsigned int trunk_shift; 374 unsigned int page_shift; 375 }; 376 377 struct hns_roce_db_pgdir { 378 struct list_head list; 379 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 380 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 381 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 382 u32 *page; 383 dma_addr_t db_dma; 384 }; 385 386 struct hns_roce_user_db_page { 387 struct list_head list; 388 struct ib_umem *umem; 389 unsigned long user_virt; 390 refcount_t refcount; 391 }; 392 393 struct hns_roce_db { 394 u32 *db_record; 395 union { 396 struct hns_roce_db_pgdir *pgdir; 397 struct hns_roce_user_db_page *user_page; 398 } u; 399 dma_addr_t dma; 400 void *virt_addr; 401 unsigned long index; 402 unsigned long order; 403 }; 404 405 struct hns_roce_cq { 406 struct ib_cq ib_cq; 407 struct hns_roce_mtr mtr; 408 struct hns_roce_db db; 409 u32 flags; 410 spinlock_t lock; 411 u32 cq_depth; 412 u32 cons_index; 413 u32 *set_ci_db; 414 void __iomem *db_reg; 415 int arm_sn; 416 int cqe_size; 417 unsigned long cqn; 418 u32 vector; 419 refcount_t refcount; 420 struct completion free; 421 struct list_head sq_list; /* all qps on this send cq */ 422 struct list_head rq_list; /* all qps on this recv cq */ 423 int is_armed; /* cq is armed */ 424 struct list_head node; /* all armed cqs are on a list */ 425 }; 426 427 struct hns_roce_idx_que { 428 struct hns_roce_mtr mtr; 429 u32 entry_shift; 430 unsigned long *bitmap; 431 u32 head; 432 u32 tail; 433 }; 434 435 struct hns_roce_srq { 436 struct ib_srq ibsrq; 437 unsigned long srqn; 438 u32 wqe_cnt; 439 int max_gs; 440 u32 rsv_sge; 441 u32 wqe_shift; 442 u32 cqn; 443 u32 xrcdn; 444 void __iomem *db_reg; 445 446 refcount_t refcount; 447 struct completion free; 448 449 struct hns_roce_mtr buf_mtr; 450 451 u64 *wrid; 452 struct hns_roce_idx_que idx_que; 453 spinlock_t lock; 454 struct mutex mutex; 455 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 456 }; 457 458 struct hns_roce_uar_table { 459 struct hns_roce_bitmap bitmap; 460 }; 461 462 struct hns_roce_bank { 463 struct ida ida; 464 u32 inuse; /* Number of IDs allocated */ 465 u32 min; /* Lowest ID to allocate. */ 466 u32 max; /* Highest ID to allocate. */ 467 u32 next; /* Next ID to allocate. */ 468 }; 469 470 struct hns_roce_idx_table { 471 u32 *spare_idx; 472 u32 head; 473 u32 tail; 474 }; 475 476 struct hns_roce_qp_table { 477 struct hns_roce_hem_table qp_table; 478 struct hns_roce_hem_table irrl_table; 479 struct hns_roce_hem_table trrl_table; 480 struct hns_roce_hem_table sccc_table; 481 struct mutex scc_mutex; 482 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 483 struct mutex bank_mutex; 484 struct hns_roce_idx_table idx_table; 485 }; 486 487 struct hns_roce_cq_table { 488 struct xarray array; 489 struct hns_roce_hem_table table; 490 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 491 struct mutex bank_mutex; 492 }; 493 494 struct hns_roce_srq_table { 495 struct hns_roce_ida srq_ida; 496 struct xarray xa; 497 struct hns_roce_hem_table table; 498 }; 499 500 struct hns_roce_av { 501 u8 port; 502 u8 gid_index; 503 u8 stat_rate; 504 u8 hop_limit; 505 u32 flowlabel; 506 u16 udp_sport; 507 u8 sl; 508 u8 tclass; 509 u8 dgid[HNS_ROCE_GID_SIZE]; 510 u8 mac[ETH_ALEN]; 511 u16 vlan_id; 512 u8 vlan_en; 513 }; 514 515 struct hns_roce_ah { 516 struct ib_ah ibah; 517 struct hns_roce_av av; 518 }; 519 520 struct hns_roce_cmd_context { 521 struct completion done; 522 int result; 523 int next; 524 u64 out_param; 525 u16 token; 526 u16 busy; 527 }; 528 529 enum hns_roce_cmdq_state { 530 HNS_ROCE_CMDQ_STATE_NORMAL, 531 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 532 }; 533 534 struct hns_roce_cmdq { 535 struct dma_pool *pool; 536 struct semaphore poll_sem; 537 /* 538 * Event mode: cmd register mutex protection, 539 * ensure to not exceed max_cmds and user use limit region 540 */ 541 struct semaphore event_sem; 542 int max_cmds; 543 spinlock_t context_lock; 544 int free_head; 545 struct hns_roce_cmd_context *context; 546 /* 547 * Process whether use event mode, init default non-zero 548 * After the event queue of cmd event ready, 549 * can switch into event mode 550 * close device, switch into poll mode(non event mode) 551 */ 552 u8 use_events; 553 enum hns_roce_cmdq_state state; 554 }; 555 556 struct hns_roce_cmd_mailbox { 557 void *buf; 558 dma_addr_t dma; 559 }; 560 561 struct hns_roce_mbox_msg { 562 u64 in_param; 563 u64 out_param; 564 u8 cmd; 565 u32 tag; 566 u16 token; 567 u8 event_en; 568 }; 569 570 struct hns_roce_dev; 571 572 enum { 573 HNS_ROCE_FLUSH_FLAG = 0, 574 }; 575 576 struct hns_roce_work { 577 struct hns_roce_dev *hr_dev; 578 struct work_struct work; 579 int event_type; 580 int sub_type; 581 u32 queue_num; 582 }; 583 584 struct hns_roce_qp { 585 struct ib_qp ibqp; 586 struct hns_roce_wq rq; 587 struct hns_roce_db rdb; 588 struct hns_roce_db sdb; 589 unsigned long en_flags; 590 enum ib_sig_type sq_signal_bits; 591 struct hns_roce_wq sq; 592 593 struct hns_roce_mtr mtr; 594 595 u32 buff_size; 596 struct mutex mutex; 597 u8 port; 598 u8 phy_port; 599 u8 sl; 600 u8 resp_depth; 601 u8 state; 602 u32 atomic_rd_en; 603 u32 qkey; 604 void (*event)(struct hns_roce_qp *qp, 605 enum hns_roce_event event_type); 606 unsigned long qpn; 607 608 u32 xrcdn; 609 610 refcount_t refcount; 611 struct completion free; 612 613 struct hns_roce_sge sge; 614 u32 next_sge; 615 enum ib_mtu path_mtu; 616 u32 max_inline_data; 617 u8 free_mr_en; 618 619 /* 0: flush needed, 1: unneeded */ 620 unsigned long flush_flag; 621 struct hns_roce_work flush_work; 622 struct list_head node; /* all qps are on a list */ 623 struct list_head rq_node; /* all recv qps are on a list */ 624 struct list_head sq_node; /* all send qps are on a list */ 625 struct hns_user_mmap_entry *dwqe_mmap_entry; 626 u32 config; 627 }; 628 629 struct hns_roce_ib_iboe { 630 spinlock_t lock; 631 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 632 struct notifier_block nb; 633 u8 phy_port[HNS_ROCE_MAX_PORTS]; 634 }; 635 636 struct hns_roce_ceqe { 637 __le32 comp; 638 __le32 rsv[15]; 639 }; 640 641 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 642 643 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 644 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 645 646 struct hns_roce_aeqe { 647 __le32 asyn; 648 union { 649 struct { 650 __le32 num; 651 u32 rsv0; 652 u32 rsv1; 653 } queue_event; 654 655 struct { 656 __le64 out_param; 657 __le16 token; 658 u8 status; 659 u8 rsv0; 660 } __packed cmd; 661 } event; 662 __le32 rsv[12]; 663 }; 664 665 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 666 667 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 668 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 669 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 670 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 671 672 struct hns_roce_eq { 673 struct hns_roce_dev *hr_dev; 674 void __iomem *db_reg; 675 676 int type_flag; /* Aeq:1 ceq:0 */ 677 int eqn; 678 u32 entries; 679 int eqe_size; 680 int irq; 681 u32 cons_index; 682 int over_ignore; 683 int coalesce; 684 int arm_st; 685 int hop_num; 686 struct hns_roce_mtr mtr; 687 u16 eq_max_cnt; 688 u32 eq_period; 689 int shift; 690 int event_type; 691 int sub_type; 692 }; 693 694 struct hns_roce_eq_table { 695 struct hns_roce_eq *eq; 696 }; 697 698 enum cong_type { 699 CONG_TYPE_DCQCN, 700 CONG_TYPE_LDCP, 701 CONG_TYPE_HC3, 702 CONG_TYPE_DIP, 703 }; 704 705 struct hns_roce_caps { 706 u64 fw_ver; 707 u8 num_ports; 708 int gid_table_len[HNS_ROCE_MAX_PORTS]; 709 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 710 int local_ca_ack_delay; 711 int num_uars; 712 u32 phy_num_uars; 713 u32 max_sq_sg; 714 u32 max_sq_inline; 715 u32 max_rq_sg; 716 u32 rsv0; 717 u32 num_qps; 718 u32 reserved_qps; 719 u32 num_srqs; 720 u32 max_wqes; 721 u32 max_srq_wrs; 722 u32 max_srq_sges; 723 u32 max_sq_desc_sz; 724 u32 max_rq_desc_sz; 725 u32 rsv2; 726 int max_qp_init_rdma; 727 int max_qp_dest_rdma; 728 u32 num_cqs; 729 u32 max_cqes; 730 u32 min_cqes; 731 u32 min_wqes; 732 u32 reserved_cqs; 733 u32 reserved_srqs; 734 int num_aeq_vectors; 735 int num_comp_vectors; 736 int num_other_vectors; 737 u32 num_mtpts; 738 u32 rsv1; 739 u32 num_srqwqe_segs; 740 u32 num_idx_segs; 741 int reserved_mrws; 742 int reserved_uars; 743 int num_pds; 744 int reserved_pds; 745 u32 num_xrcds; 746 u32 reserved_xrcds; 747 u32 mtt_entry_sz; 748 u32 cqe_sz; 749 u32 page_size_cap; 750 u32 reserved_lkey; 751 int mtpt_entry_sz; 752 int qpc_sz; 753 int irrl_entry_sz; 754 int trrl_entry_sz; 755 int cqc_entry_sz; 756 int sccc_sz; 757 int qpc_timer_entry_sz; 758 int cqc_timer_entry_sz; 759 int srqc_entry_sz; 760 int idx_entry_sz; 761 u32 pbl_ba_pg_sz; 762 u32 pbl_buf_pg_sz; 763 u32 pbl_hop_num; 764 int aeqe_depth; 765 int ceqe_depth; 766 u32 aeqe_size; 767 u32 ceqe_size; 768 enum ib_mtu max_mtu; 769 u32 qpc_bt_num; 770 u32 qpc_timer_bt_num; 771 u32 srqc_bt_num; 772 u32 cqc_bt_num; 773 u32 cqc_timer_bt_num; 774 u32 mpt_bt_num; 775 u32 eqc_bt_num; 776 u32 smac_bt_num; 777 u32 sgid_bt_num; 778 u32 sccc_bt_num; 779 u32 gmv_bt_num; 780 u32 qpc_ba_pg_sz; 781 u32 qpc_buf_pg_sz; 782 u32 qpc_hop_num; 783 u32 srqc_ba_pg_sz; 784 u32 srqc_buf_pg_sz; 785 u32 srqc_hop_num; 786 u32 cqc_ba_pg_sz; 787 u32 cqc_buf_pg_sz; 788 u32 cqc_hop_num; 789 u32 mpt_ba_pg_sz; 790 u32 mpt_buf_pg_sz; 791 u32 mpt_hop_num; 792 u32 mtt_ba_pg_sz; 793 u32 mtt_buf_pg_sz; 794 u32 mtt_hop_num; 795 u32 wqe_sq_hop_num; 796 u32 wqe_sge_hop_num; 797 u32 wqe_rq_hop_num; 798 u32 sccc_ba_pg_sz; 799 u32 sccc_buf_pg_sz; 800 u32 sccc_hop_num; 801 u32 qpc_timer_ba_pg_sz; 802 u32 qpc_timer_buf_pg_sz; 803 u32 qpc_timer_hop_num; 804 u32 cqc_timer_ba_pg_sz; 805 u32 cqc_timer_buf_pg_sz; 806 u32 cqc_timer_hop_num; 807 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 808 u32 cqe_buf_pg_sz; 809 u32 cqe_hop_num; 810 u32 srqwqe_ba_pg_sz; 811 u32 srqwqe_buf_pg_sz; 812 u32 srqwqe_hop_num; 813 u32 idx_ba_pg_sz; 814 u32 idx_buf_pg_sz; 815 u32 idx_hop_num; 816 u32 eqe_ba_pg_sz; 817 u32 eqe_buf_pg_sz; 818 u32 eqe_hop_num; 819 u32 gmv_entry_num; 820 u32 gmv_entry_sz; 821 u32 gmv_ba_pg_sz; 822 u32 gmv_buf_pg_sz; 823 u32 gmv_hop_num; 824 u32 sl_num; 825 u32 llm_buf_pg_sz; 826 u32 chunk_sz; /* chunk size in non multihop mode */ 827 u64 flags; 828 u16 default_ceq_max_cnt; 829 u16 default_ceq_period; 830 u16 default_aeq_max_cnt; 831 u16 default_aeq_period; 832 u16 default_aeq_arm_st; 833 u16 default_ceq_arm_st; 834 enum cong_type cong_type; 835 }; 836 837 enum hns_roce_device_state { 838 HNS_ROCE_DEVICE_STATE_INITED, 839 HNS_ROCE_DEVICE_STATE_RST_DOWN, 840 HNS_ROCE_DEVICE_STATE_UNINIT, 841 }; 842 843 enum hns_roce_hw_pkt_stat_index { 844 HNS_ROCE_HW_RX_RC_PKT_CNT, 845 HNS_ROCE_HW_RX_UC_PKT_CNT, 846 HNS_ROCE_HW_RX_UD_PKT_CNT, 847 HNS_ROCE_HW_RX_XRC_PKT_CNT, 848 HNS_ROCE_HW_RX_PKT_CNT, 849 HNS_ROCE_HW_RX_ERR_PKT_CNT, 850 HNS_ROCE_HW_RX_CNP_PKT_CNT, 851 HNS_ROCE_HW_TX_RC_PKT_CNT, 852 HNS_ROCE_HW_TX_UC_PKT_CNT, 853 HNS_ROCE_HW_TX_UD_PKT_CNT, 854 HNS_ROCE_HW_TX_XRC_PKT_CNT, 855 HNS_ROCE_HW_TX_PKT_CNT, 856 HNS_ROCE_HW_TX_ERR_PKT_CNT, 857 HNS_ROCE_HW_TX_CNP_PKT_CNT, 858 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 859 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 860 HNS_ROCE_HW_ECN_DB_CNT, 861 HNS_ROCE_HW_RX_BUF_CNT, 862 HNS_ROCE_HW_TRP_RX_SOF_CNT, 863 HNS_ROCE_HW_CQ_CQE_CNT, 864 HNS_ROCE_HW_CQ_POE_CNT, 865 HNS_ROCE_HW_CQ_NOTIFY_CNT, 866 HNS_ROCE_HW_CNT_TOTAL 867 }; 868 869 struct hns_roce_hw { 870 int (*cmq_init)(struct hns_roce_dev *hr_dev); 871 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 872 int (*hw_profile)(struct hns_roce_dev *hr_dev); 873 int (*hw_init)(struct hns_roce_dev *hr_dev); 874 void (*hw_exit)(struct hns_roce_dev *hr_dev); 875 int (*post_mbox)(struct hns_roce_dev *hr_dev, 876 struct hns_roce_mbox_msg *mbox_msg); 877 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 878 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 879 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 880 const union ib_gid *gid, const struct ib_gid_attr *attr); 881 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 882 const u8 *addr); 883 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 884 struct hns_roce_mr *mr); 885 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 886 struct hns_roce_mr *mr, int flags, 887 void *mb_buf); 888 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 889 struct hns_roce_mr *mr); 890 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 891 void (*write_cqc)(struct hns_roce_dev *hr_dev, 892 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 893 dma_addr_t dma_handle); 894 int (*set_hem)(struct hns_roce_dev *hr_dev, 895 struct hns_roce_hem_table *table, int obj, u32 step_idx); 896 int (*clear_hem)(struct hns_roce_dev *hr_dev, 897 struct hns_roce_hem_table *table, int obj, 898 u32 step_idx); 899 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 900 int attr_mask, enum ib_qp_state cur_state, 901 enum ib_qp_state new_state, struct ib_udata *udata); 902 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 903 struct hns_roce_qp *hr_qp); 904 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 905 int (*init_eq)(struct hns_roce_dev *hr_dev); 906 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 907 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 908 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 909 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 910 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 911 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 912 u64 *stats, u32 port, int *hw_counters); 913 const struct ib_device_ops *hns_roce_dev_ops; 914 const struct ib_device_ops *hns_roce_dev_srq_ops; 915 }; 916 917 struct hns_roce_dev { 918 struct ib_device ib_dev; 919 struct pci_dev *pci_dev; 920 struct device *dev; 921 struct hns_roce_uar priv_uar; 922 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 923 spinlock_t sm_lock; 924 bool active; 925 bool is_reset; 926 bool dis_db; 927 unsigned long reset_cnt; 928 struct hns_roce_ib_iboe iboe; 929 enum hns_roce_device_state state; 930 struct list_head qp_list; /* list of all qps on this dev */ 931 spinlock_t qp_list_lock; /* protect qp_list */ 932 struct list_head dip_list; /* list of all dest ips on this dev */ 933 spinlock_t dip_list_lock; /* protect dip_list */ 934 935 struct list_head pgdir_list; 936 struct mutex pgdir_mutex; 937 int irq[HNS_ROCE_MAX_IRQ_NUM]; 938 u8 __iomem *reg_base; 939 void __iomem *mem_base; 940 struct hns_roce_caps caps; 941 struct xarray qp_table_xa; 942 943 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 944 u64 sys_image_guid; 945 u32 vendor_id; 946 u32 vendor_part_id; 947 u32 hw_rev; 948 void __iomem *priv_addr; 949 950 struct hns_roce_cmdq cmd; 951 struct hns_roce_ida pd_ida; 952 struct hns_roce_ida xrcd_ida; 953 struct hns_roce_ida uar_ida; 954 struct hns_roce_mr_table mr_table; 955 struct hns_roce_cq_table cq_table; 956 struct hns_roce_srq_table srq_table; 957 struct hns_roce_qp_table qp_table; 958 struct hns_roce_eq_table eq_table; 959 struct hns_roce_hem_table qpc_timer_table; 960 struct hns_roce_hem_table cqc_timer_table; 961 /* GMV is the memory area that the driver allocates for the hardware 962 * to store SGID, SMAC and VLAN information. 963 */ 964 struct hns_roce_hem_table gmv_table; 965 966 int cmd_mod; 967 int loop_idc; 968 u32 sdb_offset; 969 u32 odb_offset; 970 const struct hns_roce_hw *hw; 971 void *priv; 972 struct workqueue_struct *irq_workq; 973 struct work_struct ecc_work; 974 u32 func_num; 975 u32 is_vf; 976 u32 cong_algo_tmpl_id; 977 u64 dwqe_page; 978 }; 979 980 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 981 { 982 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 983 } 984 985 static inline struct hns_roce_ucontext 986 *to_hr_ucontext(struct ib_ucontext *ibucontext) 987 { 988 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 989 } 990 991 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 992 { 993 return container_of(ibpd, struct hns_roce_pd, ibpd); 994 } 995 996 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 997 { 998 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 999 } 1000 1001 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1002 { 1003 return container_of(ibah, struct hns_roce_ah, ibah); 1004 } 1005 1006 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1007 { 1008 return container_of(ibmr, struct hns_roce_mr, ibmr); 1009 } 1010 1011 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1012 { 1013 return container_of(ibmw, struct hns_roce_mw, ibmw); 1014 } 1015 1016 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1017 { 1018 return container_of(ibqp, struct hns_roce_qp, ibqp); 1019 } 1020 1021 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1022 { 1023 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1024 } 1025 1026 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1027 { 1028 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1029 } 1030 1031 static inline struct hns_user_mmap_entry * 1032 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1033 { 1034 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1035 } 1036 1037 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1038 { 1039 writeq(*(u64 *)val, dest); 1040 } 1041 1042 static inline struct hns_roce_qp 1043 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1044 { 1045 return xa_load(&hr_dev->qp_table_xa, qpn); 1046 } 1047 1048 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1049 unsigned int offset) 1050 { 1051 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1052 (offset & ((1 << buf->trunk_shift) - 1)); 1053 } 1054 1055 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1056 unsigned int offset) 1057 { 1058 return buf->trunk_list[offset >> buf->trunk_shift].map + 1059 (offset & ((1 << buf->trunk_shift) - 1)); 1060 } 1061 1062 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1063 { 1064 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1065 } 1066 1067 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1068 1069 static inline u64 to_hr_hw_page_addr(u64 addr) 1070 { 1071 return addr >> HNS_HW_PAGE_SHIFT; 1072 } 1073 1074 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1075 { 1076 return page_shift - HNS_HW_PAGE_SHIFT; 1077 } 1078 1079 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1080 { 1081 if (count > 0) 1082 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1083 1084 return 0; 1085 } 1086 1087 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1088 { 1089 return hr_hw_page_align(count << buf_shift); 1090 } 1091 1092 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1093 { 1094 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1095 } 1096 1097 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1098 { 1099 if (!count) 1100 return 0; 1101 1102 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1103 } 1104 1105 #define DSCP_SHIFT 2 1106 1107 static inline u8 get_tclass(const struct ib_global_route *grh) 1108 { 1109 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1110 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1111 } 1112 1113 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1114 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1115 1116 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1117 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1118 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1119 u64 out_param); 1120 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1121 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1122 1123 /* hns roce hw need current block and next block addr from mtt */ 1124 #define MTT_MIN_COUNT 2 1125 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1126 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); 1127 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1128 struct hns_roce_buf_attr *buf_attr, 1129 unsigned int page_shift, struct ib_udata *udata, 1130 unsigned long user_addr); 1131 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1132 struct hns_roce_mtr *mtr); 1133 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1134 dma_addr_t *pages, unsigned int page_cnt); 1135 1136 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1137 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1138 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1139 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1140 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1141 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1142 1143 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1144 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1145 1146 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1147 1148 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1149 struct ib_udata *udata); 1150 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1151 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1152 { 1153 return 0; 1154 } 1155 1156 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1157 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1158 1159 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1160 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1161 u64 virt_addr, int access_flags, 1162 struct ib_udata *udata); 1163 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1164 u64 length, u64 virt_addr, 1165 int mr_access_flags, struct ib_pd *pd, 1166 struct ib_udata *udata); 1167 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1168 u32 max_num_sg); 1169 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1170 unsigned int *sg_offset); 1171 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1172 unsigned long key_to_hw_index(u32 key); 1173 1174 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1175 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1176 1177 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1178 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1179 u32 page_shift, u32 flags); 1180 1181 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1182 int buf_cnt, struct hns_roce_buf *buf, 1183 unsigned int page_shift); 1184 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1185 int buf_cnt, struct ib_umem *umem, 1186 unsigned int page_shift); 1187 1188 int hns_roce_create_srq(struct ib_srq *srq, 1189 struct ib_srq_init_attr *srq_init_attr, 1190 struct ib_udata *udata); 1191 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1192 1193 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1194 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1195 1196 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1197 struct ib_udata *udata); 1198 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1199 int attr_mask, struct ib_udata *udata); 1200 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1201 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1202 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1203 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1204 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1205 struct ib_cq *ib_cq); 1206 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1207 struct hns_roce_cq *recv_cq); 1208 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1209 struct hns_roce_cq *recv_cq); 1210 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1211 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1212 struct ib_udata *udata); 1213 __be32 send_ieth(const struct ib_send_wr *wr); 1214 int to_hr_qp_type(int qp_type); 1215 1216 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1217 struct ib_udata *udata); 1218 1219 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1220 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1221 struct hns_roce_db *db); 1222 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1223 struct hns_roce_db *db); 1224 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1225 int order); 1226 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1227 1228 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1229 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1230 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1231 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1232 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1233 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1234 int hns_roce_init(struct hns_roce_dev *hr_dev); 1235 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1236 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1237 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1238 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1239 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1240 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1241 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1242 struct hns_user_mmap_entry * 1243 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1244 size_t length, 1245 enum hns_roce_mmap_type mmap_type); 1246 #endif /* _HNS_ROCE_DEVICE_H */ 1247